From 1282b9b77ef6b7182da9fc53f6d917da17f9008a Mon Sep 17 00:00:00 2001
From: FinleyHsu <152379270+FinleyHsu@users.noreply.github.com>
Date: Tue, 28 Jul 2026 11:01:55 +0800
Subject: [PATCH] feat: add STM32 four-channel weighing firmware

---
 STM32_4路称重_Git提交精简工程/.gitignore      |   22 +
 STM32_4路称重_Git提交精简工程/README.md       |   26 +
 .../Release/V2.1_260709_4CH.hex               | 5704 +++++++++++
 .../gcc_build/Makefile                        |   76 +
 .../gcc_build/extract_sources.pl              |   13 +
 .../gcc_build/gcc_compat.h                    |   12 +
 .../gcc_build/gcc_syscalls.c                  |   17 +
 .../gcc_build/startup_stm32f10x_hd_gcc.S      |  201 +
 .../gcc_build/stm32f103rc.ld                  |   95 +
 .../src/CMSIS/Startup/startup_stm32f10x_cl.s  |  368 +
 .../src/CMSIS/Startup/startup_stm32f10x_hd.s  |  358 +
 .../CMSIS/Startup/startup_stm32f10x_hd_vl.s   |  346 +
 .../src/CMSIS/Startup/startup_stm32f10x_ld.s  |  297 +
 .../CMSIS/Startup/startup_stm32f10x_ld_vl.s   |  304 +
 .../src/CMSIS/Startup/startup_stm32f10x_md.s  |  307 +
 .../CMSIS/Startup/startup_stm32f10x_md_vl.s   |  315 +
 .../src/CMSIS/Startup/startup_stm32f10x_xl.s  |  358 +
 .../src/CMSIS/core_cm3.c                      |  784 ++
 .../src/CMSIS/core_cm3.h                      | 1818 ++++
 .../src/CMSIS/stm32f10x.h                     | 8336 +++++++++++++++++
 .../src/CMSIS/system_stm32f10x.c              | 1094 +++
 .../src/CMSIS/system_stm32f10x.h              |   98 +
 .../src/HARDWARE/AUDIO/bsp_WM8978.h           |   79 +
 .../src/HARDWARE/AUDIO/bsp_i2c_gpio.c         |  232 +
 .../src/HARDWARE/AUDIO/bsp_i2c_gpio.h         |   44 +
 .../src/HARDWARE/AUDIO/bsp_wm8978.c           | 1103 +++
 .../src/HARDWARE/AUDIO/sound.c                |  198 +
 .../src/HARDWARE/AUDIO/sound.h                |   28 +
 .../src/HARDWARE/AUDIO/soundfilelists.h       |   15 +
 .../src/HARDWARE/BUZZER/buzzer.c              |  669 ++
 .../src/HARDWARE/BUZZER/buzzer.h              |   26 +
 .../src/HARDWARE/DEVICE/device.c              | 1387 +++
 .../src/HARDWARE/DEVICE/device.h              |   72 +
 .../src/HARDWARE/DEVICE/deviceSet.c           | 1694 ++++
 .../src/HARDWARE/DEVICE/deviceSet.h           |   36 +
 .../src/HARDWARE/DEVICE/distancer.c           |  387 +
 .../src/HARDWARE/DEVICE/distancer.h           |   47 +
 .../src/HARDWARE/DEVICE/m_s_comm.c            |  492 +
 .../src/HARDWARE/DEVICE/m_s_comm.h            |   16 +
 .../src/HARDWARE/Disinfection/disinfection.c  |  308 +
 .../src/HARDWARE/Disinfection/disinfection.h  |   28 +
 .../src/HARDWARE/EXTI/exti.c                  |   55 +
 .../src/HARDWARE/EXTI/exti.h                  |   21 +
 .../HARDWARE/ElectronicLock/ElectronicLock.c  |  270 +
 .../HARDWARE/ElectronicLock/ElectronicLock.h  |   29 +
 .../src/HARDWARE/FLASH/flash.c                |  257 +
 .../src/HARDWARE/FLASH/flash.h                |   81 +
 .../src/HARDWARE/GPS/gps.c                    |  265 +
 .../src/HARDWARE/GPS/gps.h                    |   54 +
 .../src/HARDWARE/GSM/at_proc.c                |  544 ++
 .../src/HARDWARE/GSM/at_proc.h                |  126 +
 .../src/HARDWARE/GSM/ec200x.c                 | 1569 ++++
 .../src/HARDWARE/GSM/ec200x.h                 |   37 +
 .../src/HARDWARE/GSM/gsm_gprs.c               | 1356 +++
 .../src/HARDWARE/GSM/gsm_gprs.h               |   33 +
 .../src/HARDWARE/GSM/gsm_uart.c               |  170 +
 .../src/HARDWARE/GSM/gsm_uart.h               |   20 +
 .../src/HARDWARE/GSM/gsm_uart_conf.c          |   23 +
 .../src/HARDWARE/GSM/gsm_uart_conf.h          |   58 +
 .../src/HARDWARE/GSM/netwer_appcall.c         |  341 +
 .../src/HARDWARE/GSM/netwer_appcall.h         |   26 +
 .../src/HARDWARE/IR_Distancer/IR_Distancer.c  |  421 +
 .../src/HARDWARE/IR_Distancer/IR_Distancer.h  |   25 +
 .../src/HARDWARE/KEY/key.c                    |  648 ++
 .../src/HARDWARE/KEY/key.h                    |   62 +
 .../src/HARDWARE/KEY/sw_key.c                 |  117 +
 .../src/HARDWARE/KEY/sw_key.h                 |   26 +
 .../src/HARDWARE/LCD/BMP.h                    |  216 +
 .../src/HARDWARE/LCD/SDWe_LCD.c               |  302 +
 .../src/HARDWARE/LCD/SDWe_LCD.h               |   20 +
 .../src/HARDWARE/LCD/display.c                | 1082 +++
 .../src/HARDWARE/LCD/display.h                |   33 +
 .../src/HARDWARE/LCD/icon.h                   |  192 +
 .../src/HARDWARE/LCD/lcd.c                    |  136 +
 .../src/HARDWARE/LCD/lcd.h                    |   25 +
 .../src/HARDWARE/LCD/lcd12864.c               |  523 ++
 .../src/HARDWARE/LCD/lcd12864.h               |   43 +
 .../src/HARDWARE/LED/led.c                    |  137 +
 .../src/HARDWARE/LED/led.h                    |   24 +
 .../src/HARDWARE/MOTOR/door_ctrl.c            | 1469 +++
 .../src/HARDWARE/MOTOR/door_ctrl.h            |   26 +
 .../src/HARDWARE/MOTOR/motor.c                |  474 +
 .../src/HARDWARE/MOTOR/motor.h                |   39 +
 .../src/HARDWARE/NTC_ADC/adc.c                |  113 +
 .../src/HARDWARE/NTC_ADC/adc.h                |   17 +
 .../src/HARDWARE/NTC_ADC/ntc.c                |  149 +
 .../src/HARDWARE/NTC_ADC/ntc.h                |   26 +
 .../src/HARDWARE/NTC_ADC/ntc_10K_tab.h        |   31 +
 .../src/HARDWARE/OPTO_SWITCH/opto_sw_key.c    |  367 +
 .../src/HARDWARE/OPTO_SWITCH/opto_sw_key.h    |   30 +
 .../src/HARDWARE/QR_Code/qr_code.c            |  202 +
 .../src/HARDWARE/QR_Code/qr_code.h            |   29 +
 .../src/HARDWARE/RFID/RFID_IC.c               |  331 +
 .../src/HARDWARE/RFID/RFID_IC.h               |   47 +
 .../src/HARDWARE/RFID/rfid_decode_yhk.c       |  127 +
 .../src/HARDWARE/RFID/rfid_decode_yhk.h       |   16 +
 .../src/HARDWARE/RFID/rfid_decode_yn.c        |  259 +
 .../src/HARDWARE/RFID/rfid_decode_yn.h        |   19 +
 .../src/HARDWARE/RFID/rfid_decode_zl.c        |   72 +
 .../src/HARDWARE/RFID/rfid_decode_zl.h        |   18 +
 .../src/HARDWARE/RS485/RS485.c                |  672 ++
 .../src/HARDWARE/RS485/RS485.h                |   44 +
 .../src/HARDWARE/SCALE/scale.c                |  177 +
 .../src/HARDWARE/SCALE/scale.h                |   53 +
 .../src/HARDWARE/SPI/spi.c                    |   87 +
 .../src/HARDWARE/SPI/spi.h                    |   10 +
 .../src/HARDWARE/STMFLASH/stmflash.c          |  459 +
 .../src/HARDWARE/STMFLASH/stmflash.h          |   32 +
 .../src/HARDWARE/TIMER/timer.c                |  353 +
 .../src/HARDWARE/TIMER/timer.h                |   35 +
 .../src/HARDWARE/USART/RS485.c                |  453 +
 .../src/HARDWARE/USART/UsarInterface.c        |   17 +
 .../src/HARDWARE/USART/UsarInterface.h        |   19 +
 .../src/HARDWARE/USART/crc16.c                |   77 +
 .../src/HARDWARE/USART/crc16.h                |    9 +
 .../src/HARDWARE/USART/printf.c               |   65 +
 .../src/HARDWARE/USART/rs485.h                |   37 +
 .../src/HARDWARE/USART/usart1.c               |  125 +
 .../src/HARDWARE/USART/usart1.h               |   25 +
 .../src/HARDWARE/USART/usart2.c               |  220 +
 .../src/HARDWARE/USART/usart2.h               |   26 +
 .../src/HARDWARE/USART/usart3.c               |  156 +
 .../src/HARDWARE/USART/usart3.h               |   19 +
 .../src/HARDWARE/USART/usart4.c               |  227 +
 .../src/HARDWARE/USART/usart4.h               |   26 +
 .../src/HARDWARE/USART/usart5.c               |  141 +
 .../src/HARDWARE/USART/usart5.h               |   27 +
 .../HARDWARE/UltrasonicWave/UltrasonicWave.c  |  518 +
 .../HARDWARE/UltrasonicWave/UltrasonicWave.h  |   28 +
 .../src/HARDWARE/WDG/wdg.c                    |   75 +
 .../src/HARDWARE/WDG/wdg.h                    |   18 +
 .../src/Project/Project.uvprojx               |  751 ++
 .../src/Project/stm32f10x_conf.h              |   77 +
 .../src/STM32F10x_FWLib/inc/misc.h            |  220 +
 .../src/STM32F10x_FWLib/inc/stm32f10x_adc.h   |  483 +
 .../src/STM32F10x_FWLib/inc/stm32f10x_bkp.h   |  195 +
 .../src/STM32F10x_FWLib/inc/stm32f10x_can.h   |  697 ++
 .../src/STM32F10x_FWLib/inc/stm32f10x_cec.h   |  210 +
 .../src/STM32F10x_FWLib/inc/stm32f10x_crc.h   |   94 +
 .../src/STM32F10x_FWLib/inc/stm32f10x_dac.h   |  317 +
 .../STM32F10x_FWLib/inc/stm32f10x_dbgmcu.h    |  119 +
 .../src/STM32F10x_FWLib/inc/stm32f10x_dma.h   |  439 +
 .../src/STM32F10x_FWLib/inc/stm32f10x_exti.h  |  184 +
 .../src/STM32F10x_FWLib/inc/stm32f10x_flash.h |  426 +
 .../src/STM32F10x_FWLib/inc/stm32f10x_fsmc.h  |  733 ++
 .../src/STM32F10x_FWLib/inc/stm32f10x_gpio.h  |  385 +
 .../src/STM32F10x_FWLib/inc/stm32f10x_i2c.h   |  684 ++
 .../src/STM32F10x_FWLib/inc/stm32f10x_iwdg.h  |  140 +
 .../src/STM32F10x_FWLib/inc/stm32f10x_pwr.h   |  156 +
 .../src/STM32F10x_FWLib/inc/stm32f10x_rcc.h   |  727 ++
 .../src/STM32F10x_FWLib/inc/stm32f10x_rtc.h   |  135 +
 .../src/STM32F10x_FWLib/inc/stm32f10x_sdio.h  |  531 ++
 .../src/STM32F10x_FWLib/inc/stm32f10x_spi.h   |  487 +
 .../src/STM32F10x_FWLib/inc/stm32f10x_tim.h   | 1164 +++
 .../src/STM32F10x_FWLib/inc/stm32f10x_usart.h |  412 +
 .../src/STM32F10x_FWLib/inc/stm32f10x_wwdg.h  |  115 +
 .../src/STM32F10x_FWLib/src/misc.c            |  225 +
 .../src/STM32F10x_FWLib/src/stm32f10x_adc.c   | 1307 +++
 .../src/STM32F10x_FWLib/src/stm32f10x_bkp.c   |  308 +
 .../src/STM32F10x_FWLib/src/stm32f10x_can.c   | 1415 +++
 .../src/STM32F10x_FWLib/src/stm32f10x_cec.c   |  433 +
 .../src/STM32F10x_FWLib/src/stm32f10x_crc.c   |  160 +
 .../src/STM32F10x_FWLib/src/stm32f10x_dac.c   |  571 ++
 .../STM32F10x_FWLib/src/stm32f10x_dbgmcu.c    |  162 +
 .../src/STM32F10x_FWLib/src/stm32f10x_dma.c   |  714 ++
 .../src/STM32F10x_FWLib/src/stm32f10x_exti.c  |  269 +
 .../src/STM32F10x_FWLib/src/stm32f10x_flash.c | 1684 ++++
 .../src/STM32F10x_FWLib/src/stm32f10x_fsmc.c  |  866 ++
 .../src/STM32F10x_FWLib/src/stm32f10x_gpio.c  |  650 ++
 .../src/STM32F10x_FWLib/src/stm32f10x_i2c.c   | 1331 +++
 .../src/STM32F10x_FWLib/src/stm32f10x_iwdg.c  |  190 +
 .../src/STM32F10x_FWLib/src/stm32f10x_pwr.c   |  307 +
 .../src/STM32F10x_FWLib/src/stm32f10x_rcc.c   | 1470 +++
 .../src/STM32F10x_FWLib/src/stm32f10x_rtc.c   |  339 +
 .../src/STM32F10x_FWLib/src/stm32f10x_sdio.c  |  799 ++
 .../src/STM32F10x_FWLib/src/stm32f10x_spi.c   |  908 ++
 .../src/STM32F10x_FWLib/src/stm32f10x_tim.c   | 2890 ++++++
 .../src/STM32F10x_FWLib/src/stm32f10x_usart.c | 1058 +++
 .../src/STM32F10x_FWLib/src/stm32f10x_wwdg.c  |  224 +
 .../src/SYSTEM/debug/debug_conf.c             |   36 +
 .../src/SYSTEM/debug/debug_conf.h             |   16 +
 .../src/SYSTEM/delay/delay.c                  |   54 +
 .../src/SYSTEM/delay/delay.h                  |   10 +
 .../src/USER/data_typedef.c                   |  371 +
 .../src/USER/data_typedef.h                   |  412 +
 .../src/USER/date_time.c                      |  102 +
 .../src/USER/date_time.h                      |   42 +
 STM32_4路称重_Git提交精简工程/src/USER/main.c |  259 +
 .../src/USER/message.c                        |   85 +
 .../src/USER/message.h                        |   60 +
 .../src/USER/my_math.c                        |  241 +
 .../src/USER/my_math.h                        |   26 +
 .../src/USER/over_flow.c                      |  739 ++
 .../src/USER/over_flow.h                      |   22 +
 .../src/USER/pc_protocol.c                    |  909 ++
 .../src/USER/pc_protocol.h                    |   16 +
 .../src/USER/stm32f10x_conf.h                 |   77 +
 .../src/USER/stm32f10x_it.c                   |   87 +
 .../src/USER/stm32f10x_it.h                   |   46 +
 .../src/USER/tcp_protocol.c                   | 1381 +++
 .../src/USER/tcp_protocol.h                   |   26 +
 .../src/USER/user_app.c                       | 1661 ++++
 .../src/USER/user_app.h                       |   31 +
 .../src/USER/user_manag.c                     |  207 +
 .../src/USER/user_manag.h                     |   31 +
 205 files changed, 80376 insertions(+)
 create mode 100644 STM32_4路称重_Git提交精简工程/.gitignore
 create mode 100644 STM32_4路称重_Git提交精简工程/README.md
 create mode 100644 STM32_4路称重_Git提交精简工程/Release/V2.1_260709_4CH.hex
 create mode 100644 STM32_4路称重_Git提交精简工程/gcc_build/Makefile
 create mode 100644 STM32_4路称重_Git提交精简工程/gcc_build/extract_sources.pl
 create mode 100644 STM32_4路称重_Git提交精简工程/gcc_build/gcc_compat.h
 create mode 100644 STM32_4路称重_Git提交精简工程/gcc_build/gcc_syscalls.c
 create mode 100644 STM32_4路称重_Git提交精简工程/gcc_build/startup_stm32f10x_hd_gcc.S
 create mode 100644 STM32_4路称重_Git提交精简工程/gcc_build/stm32f103rc.ld
 create mode 100755 STM32_4路称重_Git提交精简工程/src/CMSIS/Startup/startup_stm32f10x_cl.s
 create mode 100755 STM32_4路称重_Git提交精简工程/src/CMSIS/Startup/startup_stm32f10x_hd.s
 create mode 100755 STM32_4路称重_Git提交精简工程/src/CMSIS/Startup/startup_stm32f10x_hd_vl.s
 create mode 100755 STM32_4路称重_Git提交精简工程/src/CMSIS/Startup/startup_stm32f10x_ld.s
 create mode 100755 STM32_4路称重_Git提交精简工程/src/CMSIS/Startup/startup_stm32f10x_ld_vl.s
 create mode 100755 STM32_4路称重_Git提交精简工程/src/CMSIS/Startup/startup_stm32f10x_md.s
 create mode 100755 STM32_4路称重_Git提交精简工程/src/CMSIS/Startup/startup_stm32f10x_md_vl.s
 create mode 100755 STM32_4路称重_Git提交精简工程/src/CMSIS/Startup/startup_stm32f10x_xl.s
 create mode 100755 STM32_4路称重_Git提交精简工程/src/CMSIS/core_cm3.c
 create mode 100755 STM32_4路称重_Git提交精简工程/src/CMSIS/core_cm3.h
 create mode 100755 STM32_4路称重_Git提交精简工程/src/CMSIS/stm32f10x.h
 create mode 100755 STM32_4路称重_Git提交精简工程/src/CMSIS/system_stm32f10x.c
 create mode 100755 STM32_4路称重_Git提交精简工程/src/CMSIS/system_stm32f10x.h
 create mode 100755 STM32_4路称重_Git提交精简工程/src/HARDWARE/AUDIO/bsp_WM8978.h
 create mode 100755 STM32_4路称重_Git提交精简工程/src/HARDWARE/AUDIO/bsp_i2c_gpio.c
 create mode 100755 STM32_4路称重_Git提交精简工程/src/HARDWARE/AUDIO/bsp_i2c_gpio.h
 create mode 100755 STM32_4路称重_Git提交精简工程/src/HARDWARE/AUDIO/bsp_wm8978.c
 create mode 100755 STM32_4路称重_Git提交精简工程/src/HARDWARE/AUDIO/sound.c
 create mode 100755 STM32_4路称重_Git提交精简工程/src/HARDWARE/AUDIO/sound.h
 create mode 100755 STM32_4路称重_Git提交精简工程/src/HARDWARE/AUDIO/soundfilelists.h
 create mode 100755 STM32_4路称重_Git提交精简工程/src/HARDWARE/BUZZER/buzzer.c
 create mode 100755 STM32_4路称重_Git提交精简工程/src/HARDWARE/BUZZER/buzzer.h
 create mode 100755 STM32_4路称重_Git提交精简工程/src/HARDWARE/DEVICE/device.c
 create mode 100755 STM32_4路称重_Git提交精简工程/src/HARDWARE/DEVICE/device.h
 create mode 100755 STM32_4路称重_Git提交精简工程/src/HARDWARE/DEVICE/deviceSet.c
 create mode 100755 STM32_4路称重_Git提交精简工程/src/HARDWARE/DEVICE/deviceSet.h
 create mode 100755 STM32_4路称重_Git提交精简工程/src/HARDWARE/DEVICE/distancer.c
 create mode 100755 STM32_4路称重_Git提交精简工程/src/HARDWARE/DEVICE/distancer.h
 create mode 100755 STM32_4路称重_Git提交精简工程/src/HARDWARE/DEVICE/m_s_comm.c
 create mode 100755 STM32_4路称重_Git提交精简工程/src/HARDWARE/DEVICE/m_s_comm.h
 create mode 100755 STM32_4路称重_Git提交精简工程/src/HARDWARE/Disinfection/disinfection.c
 create mode 100755 STM32_4路称重_Git提交精简工程/src/HARDWARE/Disinfection/disinfection.h
 create mode 100755 STM32_4路称重_Git提交精简工程/src/HARDWARE/EXTI/exti.c
 create mode 100755 STM32_4路称重_Git提交精简工程/src/HARDWARE/EXTI/exti.h
 create mode 100755 STM32_4路称重_Git提交精简工程/src/HARDWARE/ElectronicLock/ElectronicLock.c
 create mode 100755 STM32_4路称重_Git提交精简工程/src/HARDWARE/ElectronicLock/ElectronicLock.h
 create mode 100755 STM32_4路称重_Git提交精简工程/src/HARDWARE/FLASH/flash.c
 create mode 100755 STM32_4路称重_Git提交精简工程/src/HARDWARE/FLASH/flash.h
 create mode 100755 STM32_4路称重_Git提交精简工程/src/HARDWARE/GPS/gps.c
 create mode 100755 STM32_4路称重_Git提交精简工程/src/HARDWARE/GPS/gps.h
 create mode 100755 STM32_4路称重_Git提交精简工程/src/HARDWARE/GSM/at_proc.c
 create mode 100755 STM32_4路称重_Git提交精简工程/src/HARDWARE/GSM/at_proc.h
 create mode 100755 STM32_4路称重_Git提交精简工程/src/HARDWARE/GSM/ec200x.c
 create mode 100755 STM32_4路称重_Git提交精简工程/src/HARDWARE/GSM/ec200x.h
 create mode 100755 STM32_4路称重_Git提交精简工程/src/HARDWARE/GSM/gsm_gprs.c
 create mode 100755 STM32_4路称重_Git提交精简工程/src/HARDWARE/GSM/gsm_gprs.h
 create mode 100755 STM32_4路称重_Git提交精简工程/src/HARDWARE/GSM/gsm_uart.c
 create mode 100755 STM32_4路称重_Git提交精简工程/src/HARDWARE/GSM/gsm_uart.h
 create mode 100755 STM32_4路称重_Git提交精简工程/src/HARDWARE/GSM/gsm_uart_conf.c
 create mode 100755 STM32_4路称重_Git提交精简工程/src/HARDWARE/GSM/gsm_uart_conf.h
 create mode 100755 STM32_4路称重_Git提交精简工程/src/HARDWARE/GSM/netwer_appcall.c
 create mode 100755 STM32_4路称重_Git提交精简工程/src/HARDWARE/GSM/netwer_appcall.h
 create mode 100755 STM32_4路称重_Git提交精简工程/src/HARDWARE/IR_Distancer/IR_Distancer.c
 create mode 100755 STM32_4路称重_Git提交精简工程/src/HARDWARE/IR_Distancer/IR_Distancer.h
 create mode 100755 STM32_4路称重_Git提交精简工程/src/HARDWARE/KEY/key.c
 create mode 100755 STM32_4路称重_Git提交精简工程/src/HARDWARE/KEY/key.h
 create mode 100755 STM32_4路称重_Git提交精简工程/src/HARDWARE/KEY/sw_key.c
 create mode 100755 STM32_4路称重_Git提交精简工程/src/HARDWARE/KEY/sw_key.h
 create mode 100755 STM32_4路称重_Git提交精简工程/src/HARDWARE/LCD/BMP.h
 create mode 100755 STM32_4路称重_Git提交精简工程/src/HARDWARE/LCD/SDWe_LCD.c
 create mode 100755 STM32_4路称重_Git提交精简工程/src/HARDWARE/LCD/SDWe_LCD.h
 create mode 100755 STM32_4路称重_Git提交精简工程/src/HARDWARE/LCD/display.c
 create mode 100755 STM32_4路称重_Git提交精简工程/src/HARDWARE/LCD/display.h
 create mode 100755 STM32_4路称重_Git提交精简工程/src/HARDWARE/LCD/icon.h
 create mode 100755 STM32_4路称重_Git提交精简工程/src/HARDWARE/LCD/lcd.c
 create mode 100755 STM32_4路称重_Git提交精简工程/src/HARDWARE/LCD/lcd.h
 create mode 100755 STM32_4路称重_Git提交精简工程/src/HARDWARE/LCD/lcd12864.c
 create mode 100755 STM32_4路称重_Git提交精简工程/src/HARDWARE/LCD/lcd12864.h
 create mode 100755 STM32_4路称重_Git提交精简工程/src/HARDWARE/LED/led.c
 create mode 100755 STM32_4路称重_Git提交精简工程/src/HARDWARE/LED/led.h
 create mode 100755 STM32_4路称重_Git提交精简工程/src/HARDWARE/MOTOR/door_ctrl.c
 create mode 100755 STM32_4路称重_Git提交精简工程/src/HARDWARE/MOTOR/door_ctrl.h
 create mode 100755 STM32_4路称重_Git提交精简工程/src/HARDWARE/MOTOR/motor.c
 create mode 100755 STM32_4路称重_Git提交精简工程/src/HARDWARE/MOTOR/motor.h
 create mode 100755 STM32_4路称重_Git提交精简工程/src/HARDWARE/NTC_ADC/adc.c
 create mode 100755 STM32_4路称重_Git提交精简工程/src/HARDWARE/NTC_ADC/adc.h
 create mode 100755 STM32_4路称重_Git提交精简工程/src/HARDWARE/NTC_ADC/ntc.c
 create mode 100755 STM32_4路称重_Git提交精简工程/src/HARDWARE/NTC_ADC/ntc.h
 create mode 100755 STM32_4路称重_Git提交精简工程/src/HARDWARE/NTC_ADC/ntc_10K_tab.h
 create mode 100755 STM32_4路称重_Git提交精简工程/src/HARDWARE/OPTO_SWITCH/opto_sw_key.c
 create mode 100755 STM32_4路称重_Git提交精简工程/src/HARDWARE/OPTO_SWITCH/opto_sw_key.h
 create mode 100755 STM32_4路称重_Git提交精简工程/src/HARDWARE/QR_Code/qr_code.c
 create mode 100755 STM32_4路称重_Git提交精简工程/src/HARDWARE/QR_Code/qr_code.h
 create mode 100755 STM32_4路称重_Git提交精简工程/src/HARDWARE/RFID/RFID_IC.c
 create mode 100755 STM32_4路称重_Git提交精简工程/src/HARDWARE/RFID/RFID_IC.h
 create mode 100755 STM32_4路称重_Git提交精简工程/src/HARDWARE/RFID/rfid_decode_yhk.c
 create mode 100755 STM32_4路称重_Git提交精简工程/src/HARDWARE/RFID/rfid_decode_yhk.h
 create mode 100755 STM32_4路称重_Git提交精简工程/src/HARDWARE/RFID/rfid_decode_yn.c
 create mode 100755 STM32_4路称重_Git提交精简工程/src/HARDWARE/RFID/rfid_decode_yn.h
 create mode 100755 STM32_4路称重_Git提交精简工程/src/HARDWARE/RFID/rfid_decode_zl.c
 create mode 100755 STM32_4路称重_Git提交精简工程/src/HARDWARE/RFID/rfid_decode_zl.h
 create mode 100755 STM32_4路称重_Git提交精简工程/src/HARDWARE/RS485/RS485.c
 create mode 100755 STM32_4路称重_Git提交精简工程/src/HARDWARE/RS485/RS485.h
 create mode 100755 STM32_4路称重_Git提交精简工程/src/HARDWARE/SCALE/scale.c
 create mode 100755 STM32_4路称重_Git提交精简工程/src/HARDWARE/SCALE/scale.h
 create mode 100755 STM32_4路称重_Git提交精简工程/src/HARDWARE/SPI/spi.c
 create mode 100755 STM32_4路称重_Git提交精简工程/src/HARDWARE/SPI/spi.h
 create mode 100755 STM32_4路称重_Git提交精简工程/src/HARDWARE/STMFLASH/stmflash.c
 create mode 100755 STM32_4路称重_Git提交精简工程/src/HARDWARE/STMFLASH/stmflash.h
 create mode 100755 STM32_4路称重_Git提交精简工程/src/HARDWARE/TIMER/timer.c
 create mode 100755 STM32_4路称重_Git提交精简工程/src/HARDWARE/TIMER/timer.h
 create mode 100755 STM32_4路称重_Git提交精简工程/src/HARDWARE/USART/RS485.c
 create mode 100755 STM32_4路称重_Git提交精简工程/src/HARDWARE/USART/UsarInterface.c
 create mode 100755 STM32_4路称重_Git提交精简工程/src/HARDWARE/USART/UsarInterface.h
 create mode 100755 STM32_4路称重_Git提交精简工程/src/HARDWARE/USART/crc16.c
 create mode 100755 STM32_4路称重_Git提交精简工程/src/HARDWARE/USART/crc16.h
 create mode 100755 STM32_4路称重_Git提交精简工程/src/HARDWARE/USART/printf.c
 create mode 100755 STM32_4路称重_Git提交精简工程/src/HARDWARE/USART/rs485.h
 create mode 100755 STM32_4路称重_Git提交精简工程/src/HARDWARE/USART/usart1.c
 create mode 100755 STM32_4路称重_Git提交精简工程/src/HARDWARE/USART/usart1.h
 create mode 100755 STM32_4路称重_Git提交精简工程/src/HARDWARE/USART/usart2.c
 create mode 100755 STM32_4路称重_Git提交精简工程/src/HARDWARE/USART/usart2.h
 create mode 100755 STM32_4路称重_Git提交精简工程/src/HARDWARE/USART/usart3.c
 create mode 100755 STM32_4路称重_Git提交精简工程/src/HARDWARE/USART/usart3.h
 create mode 100755 STM32_4路称重_Git提交精简工程/src/HARDWARE/USART/usart4.c
 create mode 100755 STM32_4路称重_Git提交精简工程/src/HARDWARE/USART/usart4.h
 create mode 100755 STM32_4路称重_Git提交精简工程/src/HARDWARE/USART/usart5.c
 create mode 100755 STM32_4路称重_Git提交精简工程/src/HARDWARE/USART/usart5.h
 create mode 100755 STM32_4路称重_Git提交精简工程/src/HARDWARE/UltrasonicWave/UltrasonicWave.c
 create mode 100755 STM32_4路称重_Git提交精简工程/src/HARDWARE/UltrasonicWave/UltrasonicWave.h
 create mode 100755 STM32_4路称重_Git提交精简工程/src/HARDWARE/WDG/wdg.c
 create mode 100755 STM32_4路称重_Git提交精简工程/src/HARDWARE/WDG/wdg.h
 create mode 100755 STM32_4路称重_Git提交精简工程/src/Project/Project.uvprojx
 create mode 100755 STM32_4路称重_Git提交精简工程/src/Project/stm32f10x_conf.h
 create mode 100755 STM32_4路称重_Git提交精简工程/src/STM32F10x_FWLib/inc/misc.h
 create mode 100755 STM32_4路称重_Git提交精简工程/src/STM32F10x_FWLib/inc/stm32f10x_adc.h
 create mode 100755 STM32_4路称重_Git提交精简工程/src/STM32F10x_FWLib/inc/stm32f10x_bkp.h
 create mode 100755 STM32_4路称重_Git提交精简工程/src/STM32F10x_FWLib/inc/stm32f10x_can.h
 create mode 100755 STM32_4路称重_Git提交精简工程/src/STM32F10x_FWLib/inc/stm32f10x_cec.h
 create mode 100755 STM32_4路称重_Git提交精简工程/src/STM32F10x_FWLib/inc/stm32f10x_crc.h
 create mode 100755 STM32_4路称重_Git提交精简工程/src/STM32F10x_FWLib/inc/stm32f10x_dac.h
 create mode 100755 STM32_4路称重_Git提交精简工程/src/STM32F10x_FWLib/inc/stm32f10x_dbgmcu.h
 create mode 100755 STM32_4路称重_Git提交精简工程/src/STM32F10x_FWLib/inc/stm32f10x_dma.h
 create mode 100755 STM32_4路称重_Git提交精简工程/src/STM32F10x_FWLib/inc/stm32f10x_exti.h
 create mode 100755 STM32_4路称重_Git提交精简工程/src/STM32F10x_FWLib/inc/stm32f10x_flash.h
 create mode 100755 STM32_4路称重_Git提交精简工程/src/STM32F10x_FWLib/inc/stm32f10x_fsmc.h
 create mode 100755 STM32_4路称重_Git提交精简工程/src/STM32F10x_FWLib/inc/stm32f10x_gpio.h
 create mode 100755 STM32_4路称重_Git提交精简工程/src/STM32F10x_FWLib/inc/stm32f10x_i2c.h
 create mode 100755 STM32_4路称重_Git提交精简工程/src/STM32F10x_FWLib/inc/stm32f10x_iwdg.h
 create mode 100755 STM32_4路称重_Git提交精简工程/src/STM32F10x_FWLib/inc/stm32f10x_pwr.h
 create mode 100755 STM32_4路称重_Git提交精简工程/src/STM32F10x_FWLib/inc/stm32f10x_rcc.h
 create mode 100755 STM32_4路称重_Git提交精简工程/src/STM32F10x_FWLib/inc/stm32f10x_rtc.h
 create mode 100755 STM32_4路称重_Git提交精简工程/src/STM32F10x_FWLib/inc/stm32f10x_sdio.h
 create mode 100755 STM32_4路称重_Git提交精简工程/src/STM32F10x_FWLib/inc/stm32f10x_spi.h
 create mode 100755 STM32_4路称重_Git提交精简工程/src/STM32F10x_FWLib/inc/stm32f10x_tim.h
 create mode 100755 STM32_4路称重_Git提交精简工程/src/STM32F10x_FWLib/inc/stm32f10x_usart.h
 create mode 100755 STM32_4路称重_Git提交精简工程/src/STM32F10x_FWLib/inc/stm32f10x_wwdg.h
 create mode 100755 STM32_4路称重_Git提交精简工程/src/STM32F10x_FWLib/src/misc.c
 create mode 100755 STM32_4路称重_Git提交精简工程/src/STM32F10x_FWLib/src/stm32f10x_adc.c
 create mode 100755 STM32_4路称重_Git提交精简工程/src/STM32F10x_FWLib/src/stm32f10x_bkp.c
 create mode 100755 STM32_4路称重_Git提交精简工程/src/STM32F10x_FWLib/src/stm32f10x_can.c
 create mode 100755 STM32_4路称重_Git提交精简工程/src/STM32F10x_FWLib/src/stm32f10x_cec.c
 create mode 100755 STM32_4路称重_Git提交精简工程/src/STM32F10x_FWLib/src/stm32f10x_crc.c
 create mode 100755 STM32_4路称重_Git提交精简工程/src/STM32F10x_FWLib/src/stm32f10x_dac.c
 create mode 100755 STM32_4路称重_Git提交精简工程/src/STM32F10x_FWLib/src/stm32f10x_dbgmcu.c
 create mode 100755 STM32_4路称重_Git提交精简工程/src/STM32F10x_FWLib/src/stm32f10x_dma.c
 create mode 100755 STM32_4路称重_Git提交精简工程/src/STM32F10x_FWLib/src/stm32f10x_exti.c
 create mode 100755 STM32_4路称重_Git提交精简工程/src/STM32F10x_FWLib/src/stm32f10x_flash.c
 create mode 100755 STM32_4路称重_Git提交精简工程/src/STM32F10x_FWLib/src/stm32f10x_fsmc.c
 create mode 100755 STM32_4路称重_Git提交精简工程/src/STM32F10x_FWLib/src/stm32f10x_gpio.c
 create mode 100755 STM32_4路称重_Git提交精简工程/src/STM32F10x_FWLib/src/stm32f10x_i2c.c
 create mode 100755 STM32_4路称重_Git提交精简工程/src/STM32F10x_FWLib/src/stm32f10x_iwdg.c
 create mode 100755 STM32_4路称重_Git提交精简工程/src/STM32F10x_FWLib/src/stm32f10x_pwr.c
 create mode 100755 STM32_4路称重_Git提交精简工程/src/STM32F10x_FWLib/src/stm32f10x_rcc.c
 create mode 100755 STM32_4路称重_Git提交精简工程/src/STM32F10x_FWLib/src/stm32f10x_rtc.c
 create mode 100755 STM32_4路称重_Git提交精简工程/src/STM32F10x_FWLib/src/stm32f10x_sdio.c
 create mode 100755 STM32_4路称重_Git提交精简工程/src/STM32F10x_FWLib/src/stm32f10x_spi.c
 create mode 100755 STM32_4路称重_Git提交精简工程/src/STM32F10x_FWLib/src/stm32f10x_tim.c
 create mode 100755 STM32_4路称重_Git提交精简工程/src/STM32F10x_FWLib/src/stm32f10x_usart.c
 create mode 100755 STM32_4路称重_Git提交精简工程/src/STM32F10x_FWLib/src/stm32f10x_wwdg.c
 create mode 100755 STM32_4路称重_Git提交精简工程/src/SYSTEM/debug/debug_conf.c
 create mode 100755 STM32_4路称重_Git提交精简工程/src/SYSTEM/debug/debug_conf.h
 create mode 100755 STM32_4路称重_Git提交精简工程/src/SYSTEM/delay/delay.c
 create mode 100755 STM32_4路称重_Git提交精简工程/src/SYSTEM/delay/delay.h
 create mode 100755 STM32_4路称重_Git提交精简工程/src/USER/data_typedef.c
 create mode 100755 STM32_4路称重_Git提交精简工程/src/USER/data_typedef.h
 create mode 100755 STM32_4路称重_Git提交精简工程/src/USER/date_time.c
 create mode 100755 STM32_4路称重_Git提交精简工程/src/USER/date_time.h
 create mode 100755 STM32_4路称重_Git提交精简工程/src/USER/main.c
 create mode 100755 STM32_4路称重_Git提交精简工程/src/USER/message.c
 create mode 100755 STM32_4路称重_Git提交精简工程/src/USER/message.h
 create mode 100755 STM32_4路称重_Git提交精简工程/src/USER/my_math.c
 create mode 100755 STM32_4路称重_Git提交精简工程/src/USER/my_math.h
 create mode 100755 STM32_4路称重_Git提交精简工程/src/USER/over_flow.c
 create mode 100755 STM32_4路称重_Git提交精简工程/src/USER/over_flow.h
 create mode 100755 STM32_4路称重_Git提交精简工程/src/USER/pc_protocol.c
 create mode 100755 STM32_4路称重_Git提交精简工程/src/USER/pc_protocol.h
 create mode 100755 STM32_4路称重_Git提交精简工程/src/USER/stm32f10x_conf.h
 create mode 100755 STM32_4路称重_Git提交精简工程/src/USER/stm32f10x_it.c
 create mode 100755 STM32_4路称重_Git提交精简工程/src/USER/stm32f10x_it.h
 create mode 100755 STM32_4路称重_Git提交精简工程/src/USER/tcp_protocol.c
 create mode 100755 STM32_4路称重_Git提交精简工程/src/USER/tcp_protocol.h
 create mode 100755 STM32_4路称重_Git提交精简工程/src/USER/user_app.c
 create mode 100755 STM32_4路称重_Git提交精简工程/src/USER/user_app.h
 create mode 100755 STM32_4路称重_Git提交精简工程/src/USER/user_manag.c
 create mode 100755 STM32_4路称重_Git提交精简工程/src/USER/user_manag.h

diff --git a/STM32_4路称重_Git提交精简工程/.gitignore b/STM32_4路称重_Git提交精简工程/.gitignore
new file mode 100644
index 0000000..d65edea
--- /dev/null
+++ b/STM32_4路称重_Git提交精简工程/.gitignore
@@ -0,0 +1,22 @@
+# Keil build outputs and user-local settings
+Output/
+Listing/
+Objects/
+*.o
+*.d
+*.crf
+*.axf
+*.elf
+*.map
+*.lst
+*.dep
+*.uvgui*
+*.uvopt*
+JLinkLog.txt
+
+# GCC build outputs
+gcc_build/build/
+
+# macOS metadata
+.DS_Store
+._*
diff --git a/STM32_4路称重_Git提交精简工程/README.md b/STM32_4路称重_Git提交精简工程/README.md
new file mode 100644
index 0000000..b6e8dd9
--- /dev/null
+++ b/STM32_4路称重_Git提交精简工程/README.md
@@ -0,0 +1,26 @@
+# STM32 四投口四路称重固件
+
+这是用于 Git 提交的精简工程包，保留了重新编译所需的源码、头文件、Keil 工程、STM32 标准外设库、CMSIS 和 GCC 构建配置。
+
+## 目录
+
+- `src/Project/Project.uvprojx`：Keil MDK 工程入口
+- `src/USER/`：主程序与业务逻辑
+- `src/HARDWARE/`：硬件驱动
+- `src/CMSIS/`：CMSIS 与启动文件
+- `src/STM32F10x_FWLib/`：STM32F10x 标准外设库
+- `src/SYSTEM/`：系统基础模块
+- `gcc_build/`：ARM GCC 构建脚本与链接脚本
+- `Release/V2.1_260709_4CH.hex`：可烧录固件
+
+## 构建
+
+Keil MDK：打开 `src/Project/Project.uvprojx`。
+
+ARM GCC：
+
+```sh
+make -C gcc_build
+```
+
+版本标识：`V2.1_260709_4CH`。
diff --git a/STM32_4路称重_Git提交精简工程/Release/V2.1_260709_4CH.hex b/STM32_4路称重_Git提交精简工程/Release/V2.1_260709_4CH.hex
new file mode 100644
index 0000000..f512da6
--- /dev/null
+++ b/STM32_4路称重_Git提交精简工程/Release/V2.1_260709_4CH.hex
@@ -0,0 +1,5704 @@
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diff --git a/STM32_4路称重_Git提交精简工程/gcc_build/Makefile b/STM32_4路称重_Git提交精简工程/gcc_build/Makefile
new file mode 100644
index 0000000..79b7d82
--- /dev/null
+++ b/STM32_4路称重_Git提交精简工程/gcc_build/Makefile
@@ -0,0 +1,76 @@
+PROJECT_XML := ../src/Project/Project.uvprojx
+BUILD_DIR := build
+TARGET := $(BUILD_DIR)/V2.1_260709_4CH
+
+CC := arm-none-eabi-gcc
+OBJCOPY := arm-none-eabi-objcopy
+SIZE := arm-none-eabi-size
+
+C_SOURCES := $(filter-out ../src/CMSIS/core_cm3.c,$(shell perl extract_sources.pl $(PROJECT_XML)))
+S_SOURCES := startup_stm32f10x_hd_gcc.S
+OBJECTS := $(patsubst ../src/%.c,$(BUILD_DIR)/%.o,$(C_SOURCES))
+OBJECTS += $(BUILD_DIR)/gcc_syscalls.o
+OBJECTS += $(BUILD_DIR)/startup_stm32f10x_hd_gcc.o
+
+INCLUDES := \
+	-I../src/USER -I../src/CORE -I../src/CMSIS \
+	-I../src/SYSTEM/delay -I../src/SYSTEM/debug -I../src/SYSTEM/usart \
+	-I../src/STM32F10x_FWLib/inc \
+	-I../src/HARDWARE/LED -I../src/HARDWARE/KEY -I../src/HARDWARE/LCD \
+	-I../src/HARDWARE/24CXX -I../src/HARDWARE/FLASH -I../src/HARDWARE/IIC \
+	-I../src/HARDWARE/SPI -I../src/HARDWARE/BUZZER -I../src/HARDWARE/RFID \
+	-I../src/HARDWARE/EXTI -I../src/HARDWARE/TIMER \
+	-I../src/HARDWARE/UltrasonicWave -I../src/HARDWARE/USART \
+	-I../src/HARDWARE/GPS -I../src/HARDWARE/GSM -I../src/HARDWARE/QR_Code \
+	-I../src/HARDWARE/DEVICE -I../src/HARDWARE/NTC_ADC -I../src/HARDWARE/WDG \
+	-I../src/HARDWARE/SCALE -I../src/HARDWARE/ElectronicLock \
+	-I../src/HARDWARE/MOTOR -I../src/HARDWARE/AUDIO -I../src/HARDWARE/OPTO_SWITCH \
+	-I../src/HARDWARE/IR_Distancer -I../src/HARDWARE/RS485 \
+	-I../src/HARDWARE/STMFLASH -I../src/HARDWARE/Disinfection
+
+ARCH_FLAGS := -mcpu=cortex-m3 -mthumb
+DEFINES := -DSTM32F10X_HD -DUSE_STDPERIPH_DRIVER -Dsignal=gsm_signal_strength
+WARNINGS := -Wall -Wextra -Wno-unused-parameter -Wno-unused-variable \
+	-Wno-unused-but-set-variable -Wno-sign-compare -Wno-implicit-int \
+	-Wno-unknown-pragmas -Wno-format
+CFLAGS := $(ARCH_FLAGS) -std=gnu99 -Os -g3 -ffunction-sections -fdata-sections \
+	-fcommon -fno-strict-aliasing -fno-builtin -include gcc_compat.h $(DEFINES) $(INCLUDES) $(WARNINGS)
+ASFLAGS := $(ARCH_FLAGS) -x assembler-with-cpp -g3
+LDFLAGS := $(ARCH_FLAGS) -T stm32f103rc.ld -Wl,--gc-sections \
+	-Wl,-Map=$(TARGET).map,--cref -Wl,--print-memory-usage \
+	--specs=nano.specs --specs=nosys.specs -u _printf_float
+LDLIBS := -Wl,--start-group -lc -lm -Wl,--end-group
+
+.PHONY: all clean verify
+
+all: $(TARGET).hex $(TARGET).bin
+	$(SIZE) $(TARGET).elf
+
+$(TARGET).elf: $(OBJECTS) stm32f103rc.ld | $(BUILD_DIR)
+	$(CC) $(OBJECTS) $(LDFLAGS) $(LDLIBS) -o $@
+
+$(TARGET).hex: $(TARGET).elf
+	$(OBJCOPY) -O ihex $< $@
+
+$(TARGET).bin: $(TARGET).elf
+	$(OBJCOPY) -O binary $< $@
+
+$(BUILD_DIR)/%.o: ../src/%.c gcc_compat.h
+	@mkdir -p $(dir $@)
+	$(CC) $(CFLAGS) -MMD -MP -c $< -o $@
+
+$(BUILD_DIR)/startup_stm32f10x_hd_gcc.o: startup_stm32f10x_hd_gcc.S
+	@mkdir -p $(dir $@)
+	$(CC) $(ASFLAGS) -c $< -o $@
+
+$(BUILD_DIR)/gcc_syscalls.o: gcc_syscalls.c gcc_compat.h
+	@mkdir -p $(dir $@)
+	$(CC) $(CFLAGS) -MMD -MP -c $< -o $@
+
+$(BUILD_DIR):
+	mkdir -p $@
+
+clean:
+	rm -rf $(BUILD_DIR)
+
+-include $(OBJECTS:.o=.d)
diff --git a/STM32_4路称重_Git提交精简工程/gcc_build/extract_sources.pl b/STM32_4路称重_Git提交精简工程/gcc_build/extract_sources.pl
new file mode 100644
index 0000000..374c0f9
--- /dev/null
+++ b/STM32_4路称重_Git提交精简工程/gcc_build/extract_sources.pl
@@ -0,0 +1,13 @@
+#!/usr/bin/env perl
+use strict;
+use warnings;
+
+my $project = shift @ARGV or die "usage: $0 Project.uvprojx\n";
+open my $fh, '<', $project or die "cannot open $project: $!\n";
+while (my $line = <$fh>) {
+    next unless $line =~ m{<FilePath>\.\.\\(.+\.c)</FilePath>};
+    my $path = $1;
+    $path =~ s{\\}{/}g;
+    print "../src/$path ";
+}
+close $fh;
diff --git a/STM32_4路称重_Git提交精简工程/gcc_build/gcc_compat.h b/STM32_4路称重_Git提交精简工程/gcc_build/gcc_compat.h
new file mode 100644
index 0000000..8a15067
--- /dev/null
+++ b/STM32_4路称重_Git提交精简工程/gcc_build/gcc_compat.h
@@ -0,0 +1,12 @@
+#ifndef GCC_COMPAT_H
+#define GCC_COMPAT_H
+
+#ifndef __align
+#define __align(n) __attribute__((aligned(n)))
+#endif
+
+#ifndef __packed
+#define __packed __attribute__((packed))
+#endif
+
+#endif
diff --git a/STM32_4路称重_Git提交精简工程/gcc_build/gcc_syscalls.c b/STM32_4路称重_Git提交精简工程/gcc_build/gcc_syscalls.c
new file mode 100644
index 0000000..1b200d2
--- /dev/null
+++ b/STM32_4路称重_Git提交精简工程/gcc_build/gcc_syscalls.c
@@ -0,0 +1,17 @@
+#include "stm32f10x.h"
+
+int _write(int file, char *data, int length)
+{
+    int index;
+
+    (void)file;
+    for (index = 0; index < length; ++index)
+    {
+        while (USART_GetFlagStatus(UART5, USART_FLAG_TC) == RESET)
+        {
+        }
+        USART_SendData(UART5, (uint8_t)data[index]);
+    }
+
+    return length;
+}
diff --git a/STM32_4路称重_Git提交精简工程/gcc_build/startup_stm32f10x_hd_gcc.S b/STM32_4路称重_Git提交精简工程/gcc_build/startup_stm32f10x_hd_gcc.S
new file mode 100644
index 0000000..d6eb084
--- /dev/null
+++ b/STM32_4路称重_Git提交精简工程/gcc_build/startup_stm32f10x_hd_gcc.S
@@ -0,0 +1,201 @@
+.syntax unified
+.cpu cortex-m3
+.thumb
+
+.global g_pfnVectors
+.global Reset_Handler
+.extern SystemInit
+.extern main
+.extern __libc_init_array
+
+.section .isr_vector,"a",%progbits
+.type g_pfnVectors, %object
+g_pfnVectors:
+  .word _estack
+  .word Reset_Handler
+  .word NMI_Handler
+  .word HardFault_Handler
+  .word MemManage_Handler
+  .word BusFault_Handler
+  .word UsageFault_Handler
+  .word 0, 0, 0, 0
+  .word SVC_Handler
+  .word DebugMon_Handler
+  .word 0
+  .word PendSV_Handler
+  .word SysTick_Handler
+  .word WWDG_IRQHandler
+  .word PVD_IRQHandler
+  .word TAMPER_IRQHandler
+  .word RTC_IRQHandler
+  .word FLASH_IRQHandler
+  .word RCC_IRQHandler
+  .word EXTI0_IRQHandler
+  .word EXTI1_IRQHandler
+  .word EXTI2_IRQHandler
+  .word EXTI3_IRQHandler
+  .word EXTI4_IRQHandler
+  .word DMA1_Channel1_IRQHandler
+  .word DMA1_Channel2_IRQHandler
+  .word DMA1_Channel3_IRQHandler
+  .word DMA1_Channel4_IRQHandler
+  .word DMA1_Channel5_IRQHandler
+  .word DMA1_Channel6_IRQHandler
+  .word DMA1_Channel7_IRQHandler
+  .word ADC1_2_IRQHandler
+  .word USB_HP_CAN1_TX_IRQHandler
+  .word USB_LP_CAN1_RX0_IRQHandler
+  .word CAN1_RX1_IRQHandler
+  .word CAN1_SCE_IRQHandler
+  .word EXTI9_5_IRQHandler
+  .word TIM1_BRK_IRQHandler
+  .word TIM1_UP_IRQHandler
+  .word TIM1_TRG_COM_IRQHandler
+  .word TIM1_CC_IRQHandler
+  .word TIM2_IRQHandler
+  .word TIM3_IRQHandler
+  .word TIM4_IRQHandler
+  .word I2C1_EV_IRQHandler
+  .word I2C1_ER_IRQHandler
+  .word I2C2_EV_IRQHandler
+  .word I2C2_ER_IRQHandler
+  .word SPI1_IRQHandler
+  .word SPI2_IRQHandler
+  .word USART1_IRQHandler
+  .word USART2_IRQHandler
+  .word USART3_IRQHandler
+  .word EXTI15_10_IRQHandler
+  .word RTCAlarm_IRQHandler
+  .word USBWakeUp_IRQHandler
+  .word TIM8_BRK_IRQHandler
+  .word TIM8_UP_IRQHandler
+  .word TIM8_TRG_COM_IRQHandler
+  .word TIM8_CC_IRQHandler
+  .word ADC3_IRQHandler
+  .word FSMC_IRQHandler
+  .word SDIO_IRQHandler
+  .word TIM5_IRQHandler
+  .word SPI3_IRQHandler
+  .word UART4_IRQHandler
+  .word UART5_IRQHandler
+  .word TIM6_IRQHandler
+  .word TIM7_IRQHandler
+  .word DMA2_Channel1_IRQHandler
+  .word DMA2_Channel2_IRQHandler
+  .word DMA2_Channel3_IRQHandler
+  .word DMA2_Channel4_5_IRQHandler
+.size g_pfnVectors, .-g_pfnVectors
+
+.section .text.Reset_Handler,"ax",%progbits
+.thumb_func
+Reset_Handler:
+  ldr r0, =_sidata
+  ldr r1, =_sdata
+  ldr r2, =_edata
+1:
+  cmp r1, r2
+  bcc 2f
+  b 3f
+2:
+  ldr r3, [r0], #4
+  str r3, [r1], #4
+  b 1b
+3:
+  ldr r1, =_sbss
+  ldr r2, =_ebss
+  movs r3, #0
+4:
+  cmp r1, r2
+  bcc 5f
+  b 6f
+5:
+  str r3, [r1], #4
+  b 4b
+6:
+  bl SystemInit
+  bl __libc_init_array
+  bl main
+7:
+  b 7b
+
+.section .text.Default_Handler,"ax",%progbits
+.thumb_func
+Default_Handler:
+  b Default_Handler
+
+.macro weak_handler name
+  .weak \name
+  .thumb_set \name, Default_Handler
+.endm
+
+weak_handler NMI_Handler
+weak_handler HardFault_Handler
+weak_handler MemManage_Handler
+weak_handler BusFault_Handler
+weak_handler UsageFault_Handler
+weak_handler SVC_Handler
+weak_handler DebugMon_Handler
+weak_handler PendSV_Handler
+weak_handler SysTick_Handler
+weak_handler WWDG_IRQHandler
+weak_handler PVD_IRQHandler
+weak_handler TAMPER_IRQHandler
+weak_handler RTC_IRQHandler
+weak_handler FLASH_IRQHandler
+weak_handler RCC_IRQHandler
+weak_handler EXTI0_IRQHandler
+weak_handler EXTI1_IRQHandler
+weak_handler EXTI2_IRQHandler
+weak_handler EXTI3_IRQHandler
+weak_handler EXTI4_IRQHandler
+weak_handler DMA1_Channel1_IRQHandler
+weak_handler DMA1_Channel2_IRQHandler
+weak_handler DMA1_Channel3_IRQHandler
+weak_handler DMA1_Channel4_IRQHandler
+weak_handler DMA1_Channel5_IRQHandler
+weak_handler DMA1_Channel6_IRQHandler
+weak_handler DMA1_Channel7_IRQHandler
+weak_handler ADC1_2_IRQHandler
+weak_handler USB_HP_CAN1_TX_IRQHandler
+weak_handler USB_LP_CAN1_RX0_IRQHandler
+weak_handler CAN1_RX1_IRQHandler
+weak_handler CAN1_SCE_IRQHandler
+weak_handler EXTI9_5_IRQHandler
+weak_handler TIM1_BRK_IRQHandler
+weak_handler TIM1_UP_IRQHandler
+weak_handler TIM1_TRG_COM_IRQHandler
+weak_handler TIM1_CC_IRQHandler
+weak_handler TIM2_IRQHandler
+weak_handler TIM3_IRQHandler
+weak_handler TIM4_IRQHandler
+weak_handler I2C1_EV_IRQHandler
+weak_handler I2C1_ER_IRQHandler
+weak_handler I2C2_EV_IRQHandler
+weak_handler I2C2_ER_IRQHandler
+weak_handler SPI1_IRQHandler
+weak_handler SPI2_IRQHandler
+weak_handler USART1_IRQHandler
+weak_handler USART2_IRQHandler
+weak_handler USART3_IRQHandler
+weak_handler EXTI15_10_IRQHandler
+weak_handler RTCAlarm_IRQHandler
+weak_handler USBWakeUp_IRQHandler
+weak_handler TIM8_BRK_IRQHandler
+weak_handler TIM8_UP_IRQHandler
+weak_handler TIM8_TRG_COM_IRQHandler
+weak_handler TIM8_CC_IRQHandler
+weak_handler ADC3_IRQHandler
+weak_handler FSMC_IRQHandler
+weak_handler SDIO_IRQHandler
+weak_handler TIM5_IRQHandler
+weak_handler SPI3_IRQHandler
+weak_handler UART4_IRQHandler
+weak_handler UART5_IRQHandler
+weak_handler TIM6_IRQHandler
+weak_handler TIM7_IRQHandler
+weak_handler DMA2_Channel1_IRQHandler
+weak_handler DMA2_Channel2_IRQHandler
+weak_handler DMA2_Channel3_IRQHandler
+weak_handler DMA2_Channel4_5_IRQHandler
+
+.section .note.GNU-stack,"",%progbits
diff --git a/STM32_4路称重_Git提交精简工程/gcc_build/stm32f103rc.ld b/STM32_4路称重_Git提交精简工程/gcc_build/stm32f103rc.ld
new file mode 100644
index 0000000..6c6f1bf
--- /dev/null
+++ b/STM32_4路称重_Git提交精简工程/gcc_build/stm32f103rc.ld
@@ -0,0 +1,95 @@
+ENTRY(Reset_Handler)
+
+MEMORY
+{
+  FLASH (rx)  : ORIGIN = 0x08000000, LENGTH = 256K
+  RAM   (xrw) : ORIGIN = 0x20000000, LENGTH = 48K
+}
+
+_estack = ORIGIN(RAM) + LENGTH(RAM);
+_Min_Heap_Size = 0x200;
+_Min_Stack_Size = 0x400;
+
+SECTIONS
+{
+  .isr_vector :
+  {
+    . = ALIGN(4);
+    KEEP(*(.isr_vector))
+    . = ALIGN(4);
+  } > FLASH
+
+  .text :
+  {
+    . = ALIGN(4);
+    *(.text .text.*)
+    *(.rodata .rodata.*)
+    KEEP(*(.init))
+    KEEP(*(.fini))
+    . = ALIGN(4);
+    _etext = .;
+  } > FLASH
+
+  .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } > FLASH
+  .ARM.exidx :
+  {
+    __exidx_start = .;
+    *(.ARM.exidx*)
+    __exidx_end = .;
+  } > FLASH
+
+  .preinit_array :
+  {
+    PROVIDE_HIDDEN(__preinit_array_start = .);
+    KEEP(*(.preinit_array*))
+    PROVIDE_HIDDEN(__preinit_array_end = .);
+  } > FLASH
+  .init_array :
+  {
+    PROVIDE_HIDDEN(__init_array_start = .);
+    KEEP(*(SORT(.init_array.*)))
+    KEEP(*(.init_array*))
+    PROVIDE_HIDDEN(__init_array_end = .);
+  } > FLASH
+  .fini_array :
+  {
+    PROVIDE_HIDDEN(__fini_array_start = .);
+    KEEP(*(SORT(.fini_array.*)))
+    KEEP(*(.fini_array*))
+    PROVIDE_HIDDEN(__fini_array_end = .);
+  } > FLASH
+
+  _sidata = LOADADDR(.data);
+  .data :
+  {
+    . = ALIGN(4);
+    _sdata = .;
+    *(.data .data.*)
+    . = ALIGN(4);
+    _edata = .;
+  } > RAM AT > FLASH
+
+  .bss (NOLOAD) :
+  {
+    . = ALIGN(4);
+    _sbss = .;
+    __bss_start__ = _sbss;
+    *(.bss .bss.*)
+    *(COMMON)
+    . = ALIGN(4);
+    _ebss = .;
+    __bss_end__ = _ebss;
+  } > RAM
+
+  ._user_heap_stack (NOLOAD) :
+  {
+    . = ALIGN(8);
+    PROVIDE(end = .);
+    PROVIDE(_end = .);
+    . += _Min_Heap_Size;
+    . += _Min_Stack_Size;
+    . = ALIGN(8);
+  } > RAM
+
+  /DISCARD/ : { *(.note.GNU-stack) }
+}
diff --git a/STM32_4路称重_Git提交精简工程/src/CMSIS/Startup/startup_stm32f10x_cl.s b/STM32_4路称重_Git提交精简工程/src/CMSIS/Startup/startup_stm32f10x_cl.s
new file mode 100755
index 0000000..8196e69
--- /dev/null
+++ b/STM32_4路称重_Git提交精简工程/src/CMSIS/Startup/startup_stm32f10x_cl.s
@@ -0,0 +1,368 @@
+;******************** (C) COPYRIGHT 2011 STMicroelectronics ********************
+;* File Name          : startup_stm32f10x_cl.s
+;* Author             : MCD Application Team
+;* Version            : V3.5.0
+;* Date               : 11-March-2011
+;* Description        : STM32F10x Connectivity line devices vector table for MDK-ARM 
+;*                      toolchain. 
+;*                      This module performs:
+;*                      - Set the initial SP
+;*                      - Set the initial PC == Reset_Handler
+;*                      - Set the vector table entries with the exceptions ISR address
+;*                      - Configure the clock system
+;*                      - Branches to __main in the C library (which eventually
+;*                        calls main()).
+;*                      After Reset the CortexM3 processor is in Thread mode,
+;*                      priority is Privileged, and the Stack is set to Main.
+;* <<< Use Configuration Wizard in Context Menu >>>   
+;*******************************************************************************
+; THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+; WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
+; AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
+; INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
+; CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
+; INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+;*******************************************************************************
+
+; Amount of memory (in bytes) allocated for Stack
+; Tailor this value to your application needs
+; <h> Stack Configuration
+;   <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Stack_Size      EQU     0x00000400
+
+                AREA    STACK, NOINIT, READWRITE, ALIGN=3
+Stack_Mem       SPACE   Stack_Size
+__initial_sp
+
+
+; <h> Heap Configuration
+;   <o>  Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Heap_Size       EQU     0x00000200
+
+                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem        SPACE   Heap_Size
+__heap_limit
+
+                PRESERVE8
+                THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+                AREA    RESET, DATA, READONLY
+                EXPORT  __Vectors
+                EXPORT  __Vectors_End
+                EXPORT  __Vectors_Size
+
+__Vectors       DCD     __initial_sp               ; Top of Stack
+                DCD     Reset_Handler              ; Reset Handler
+                DCD     NMI_Handler                ; NMI Handler
+                DCD     HardFault_Handler          ; Hard Fault Handler
+                DCD     MemManage_Handler          ; MPU Fault Handler
+                DCD     BusFault_Handler           ; Bus Fault Handler
+                DCD     UsageFault_Handler         ; Usage Fault Handler
+                DCD     0                          ; Reserved
+                DCD     0                          ; Reserved
+                DCD     0                          ; Reserved
+                DCD     0                          ; Reserved
+                DCD     SVC_Handler                ; SVCall Handler
+                DCD     DebugMon_Handler           ; Debug Monitor Handler
+                DCD     0                          ; Reserved
+                DCD     PendSV_Handler             ; PendSV Handler
+                DCD     SysTick_Handler            ; SysTick Handler
+
+                ; External Interrupts
+                DCD     WWDG_IRQHandler            ; Window Watchdog
+                DCD     PVD_IRQHandler             ; PVD through EXTI Line detect
+                DCD     TAMPER_IRQHandler          ; Tamper
+                DCD     RTC_IRQHandler             ; RTC
+                DCD     FLASH_IRQHandler           ; Flash
+                DCD     RCC_IRQHandler             ; RCC
+                DCD     EXTI0_IRQHandler           ; EXTI Line 0
+                DCD     EXTI1_IRQHandler           ; EXTI Line 1
+                DCD     EXTI2_IRQHandler           ; EXTI Line 2
+                DCD     EXTI3_IRQHandler           ; EXTI Line 3
+                DCD     EXTI4_IRQHandler           ; EXTI Line 4
+                DCD     DMA1_Channel1_IRQHandler   ; DMA1 Channel 1
+                DCD     DMA1_Channel2_IRQHandler   ; DMA1 Channel 2
+                DCD     DMA1_Channel3_IRQHandler   ; DMA1 Channel 3
+                DCD     DMA1_Channel4_IRQHandler   ; DMA1 Channel 4
+                DCD     DMA1_Channel5_IRQHandler   ; DMA1 Channel 5
+                DCD     DMA1_Channel6_IRQHandler   ; DMA1 Channel 6
+                DCD     DMA1_Channel7_IRQHandler   ; DMA1 Channel 7
+                DCD     ADC1_2_IRQHandler          ; ADC1 and ADC2
+                DCD     CAN1_TX_IRQHandler         ; CAN1 TX
+                DCD     CAN1_RX0_IRQHandler        ; CAN1 RX0
+                DCD     CAN1_RX1_IRQHandler        ; CAN1 RX1
+                DCD     CAN1_SCE_IRQHandler        ; CAN1 SCE
+                DCD     EXTI9_5_IRQHandler         ; EXTI Line 9..5
+                DCD     TIM1_BRK_IRQHandler        ; TIM1 Break
+                DCD     TIM1_UP_IRQHandler         ; TIM1 Update
+                DCD     TIM1_TRG_COM_IRQHandler    ; TIM1 Trigger and Commutation
+                DCD     TIM1_CC_IRQHandler         ; TIM1 Capture Compare
+                DCD     TIM2_IRQHandler            ; TIM2
+                DCD     TIM3_IRQHandler            ; TIM3
+                DCD     TIM4_IRQHandler            ; TIM4
+                DCD     I2C1_EV_IRQHandler         ; I2C1 Event
+                DCD     I2C1_ER_IRQHandler         ; I2C1 Error
+                DCD     I2C2_EV_IRQHandler         ; I2C2 Event
+                DCD     I2C2_ER_IRQHandler         ; I2C1 Error
+                DCD     SPI1_IRQHandler            ; SPI1
+                DCD     SPI2_IRQHandler            ; SPI2
+                DCD     USART1_IRQHandler          ; USART1
+                DCD     USART2_IRQHandler          ; USART2
+                DCD     USART3_IRQHandler          ; USART3
+                DCD     EXTI15_10_IRQHandler       ; EXTI Line 15..10
+                DCD     RTCAlarm_IRQHandler        ; RTC alarm through EXTI line
+                DCD     OTG_FS_WKUP_IRQHandler     ; USB OTG FS Wakeup through EXTI line
+                DCD     0                          ; Reserved
+                DCD     0                          ; Reserved
+                DCD     0                          ; Reserved
+                DCD     0                          ; Reserved
+                DCD     0                          ; Reserved
+                DCD     0                          ; Reserved
+                DCD     0                          ; Reserved
+                DCD     TIM5_IRQHandler            ; TIM5
+                DCD     SPI3_IRQHandler            ; SPI3
+                DCD     UART4_IRQHandler           ; UART4
+                DCD     UART5_IRQHandler           ; UART5
+                DCD     TIM6_IRQHandler            ; TIM6
+                DCD     TIM7_IRQHandler            ; TIM7
+                DCD     DMA2_Channel1_IRQHandler   ; DMA2 Channel1
+                DCD     DMA2_Channel2_IRQHandler   ; DMA2 Channel2
+                DCD     DMA2_Channel3_IRQHandler   ; DMA2 Channel3
+                DCD     DMA2_Channel4_IRQHandler   ; DMA2 Channel4
+                DCD     DMA2_Channel5_IRQHandler   ; DMA2 Channel5
+                DCD     ETH_IRQHandler             ; Ethernet
+                DCD     ETH_WKUP_IRQHandler        ; Ethernet Wakeup through EXTI line
+                DCD     CAN2_TX_IRQHandler         ; CAN2 TX
+                DCD     CAN2_RX0_IRQHandler        ; CAN2 RX0
+                DCD     CAN2_RX1_IRQHandler        ; CAN2 RX1
+                DCD     CAN2_SCE_IRQHandler        ; CAN2 SCE
+                DCD     OTG_FS_IRQHandler          ; USB OTG FS
+__Vectors_End
+
+__Vectors_Size  EQU  __Vectors_End - __Vectors
+
+                AREA    |.text|, CODE, READONLY
+
+; Reset handler
+Reset_Handler    PROC
+                 EXPORT  Reset_Handler             [WEAK]
+        IMPORT  SystemInit
+        IMPORT  __main
+                 LDR     R0, =SystemInit
+                 BLX     R0
+                 LDR     R0, =__main
+                 BX      R0
+                 ENDP
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler     PROC
+                EXPORT  NMI_Handler                [WEAK]
+                B       .
+                ENDP
+HardFault_Handler\
+                PROC
+                EXPORT  HardFault_Handler          [WEAK]
+                B       .
+                ENDP
+MemManage_Handler\
+                PROC
+                EXPORT  MemManage_Handler          [WEAK]
+                B       .
+                ENDP
+BusFault_Handler\
+                PROC
+                EXPORT  BusFault_Handler           [WEAK]
+                B       .
+                ENDP
+UsageFault_Handler\
+                PROC
+                EXPORT  UsageFault_Handler         [WEAK]
+                B       .
+                ENDP
+SVC_Handler     PROC
+                EXPORT  SVC_Handler                [WEAK]
+                B       .
+                ENDP
+DebugMon_Handler\
+                PROC
+                EXPORT  DebugMon_Handler           [WEAK]
+                B       .
+                ENDP
+PendSV_Handler  PROC
+                EXPORT  PendSV_Handler             [WEAK]
+                B       .
+                ENDP
+SysTick_Handler PROC
+                EXPORT  SysTick_Handler            [WEAK]
+                B       .
+                ENDP
+
+Default_Handler PROC
+
+                EXPORT  WWDG_IRQHandler            [WEAK]
+                EXPORT  PVD_IRQHandler             [WEAK]
+                EXPORT  TAMPER_IRQHandler          [WEAK]
+                EXPORT  RTC_IRQHandler             [WEAK]
+                EXPORT  FLASH_IRQHandler           [WEAK]
+                EXPORT  RCC_IRQHandler             [WEAK]
+                EXPORT  EXTI0_IRQHandler           [WEAK]
+                EXPORT  EXTI1_IRQHandler           [WEAK]
+                EXPORT  EXTI2_IRQHandler           [WEAK]
+                EXPORT  EXTI3_IRQHandler           [WEAK]
+                EXPORT  EXTI4_IRQHandler           [WEAK]
+                EXPORT  DMA1_Channel1_IRQHandler   [WEAK]
+                EXPORT  DMA1_Channel2_IRQHandler   [WEAK]
+                EXPORT  DMA1_Channel3_IRQHandler   [WEAK]
+                EXPORT  DMA1_Channel4_IRQHandler   [WEAK]
+                EXPORT  DMA1_Channel5_IRQHandler   [WEAK]
+                EXPORT  DMA1_Channel6_IRQHandler   [WEAK]
+                EXPORT  DMA1_Channel7_IRQHandler   [WEAK]
+                EXPORT  ADC1_2_IRQHandler          [WEAK]
+                EXPORT  CAN1_TX_IRQHandler         [WEAK]
+                EXPORT  CAN1_RX0_IRQHandler        [WEAK]
+                EXPORT  CAN1_RX1_IRQHandler        [WEAK]
+                EXPORT  CAN1_SCE_IRQHandler        [WEAK]
+                EXPORT  EXTI9_5_IRQHandler         [WEAK]
+                EXPORT  TIM1_BRK_IRQHandler        [WEAK]
+                EXPORT  TIM1_UP_IRQHandler         [WEAK]
+                EXPORT  TIM1_TRG_COM_IRQHandler    [WEAK]
+                EXPORT  TIM1_CC_IRQHandler         [WEAK]
+                EXPORT  TIM2_IRQHandler            [WEAK]
+                EXPORT  TIM3_IRQHandler            [WEAK]
+                EXPORT  TIM4_IRQHandler            [WEAK]
+                EXPORT  I2C1_EV_IRQHandler         [WEAK]
+                EXPORT  I2C1_ER_IRQHandler         [WEAK]
+                EXPORT  I2C2_EV_IRQHandler         [WEAK]
+                EXPORT  I2C2_ER_IRQHandler         [WEAK]
+                EXPORT  SPI1_IRQHandler            [WEAK]
+                EXPORT  SPI2_IRQHandler            [WEAK]
+                EXPORT  USART1_IRQHandler          [WEAK]
+                EXPORT  USART2_IRQHandler          [WEAK]
+                EXPORT  USART3_IRQHandler          [WEAK]
+                EXPORT  EXTI15_10_IRQHandler       [WEAK]
+                EXPORT  RTCAlarm_IRQHandler        [WEAK]
+                EXPORT  OTG_FS_WKUP_IRQHandler     [WEAK]
+                EXPORT  TIM5_IRQHandler            [WEAK]
+                EXPORT  SPI3_IRQHandler            [WEAK]
+                EXPORT  UART4_IRQHandler           [WEAK]
+                EXPORT  UART5_IRQHandler           [WEAK]
+                EXPORT  TIM6_IRQHandler            [WEAK]
+                EXPORT  TIM7_IRQHandler            [WEAK]
+                EXPORT  DMA2_Channel1_IRQHandler   [WEAK]
+                EXPORT  DMA2_Channel2_IRQHandler   [WEAK]
+                EXPORT  DMA2_Channel3_IRQHandler   [WEAK]
+                EXPORT  DMA2_Channel4_IRQHandler   [WEAK]
+                EXPORT  DMA2_Channel5_IRQHandler   [WEAK]
+                EXPORT  ETH_IRQHandler             [WEAK]
+                EXPORT  ETH_WKUP_IRQHandler        [WEAK]
+                EXPORT  CAN2_TX_IRQHandler         [WEAK]
+                EXPORT  CAN2_RX0_IRQHandler        [WEAK]
+                EXPORT  CAN2_RX1_IRQHandler        [WEAK]
+                EXPORT  CAN2_SCE_IRQHandler        [WEAK]
+                EXPORT  OTG_FS_IRQHandler          [WEAK]
+
+WWDG_IRQHandler
+PVD_IRQHandler
+TAMPER_IRQHandler
+RTC_IRQHandler
+FLASH_IRQHandler
+RCC_IRQHandler
+EXTI0_IRQHandler
+EXTI1_IRQHandler
+EXTI2_IRQHandler
+EXTI3_IRQHandler
+EXTI4_IRQHandler
+DMA1_Channel1_IRQHandler
+DMA1_Channel2_IRQHandler
+DMA1_Channel3_IRQHandler
+DMA1_Channel4_IRQHandler
+DMA1_Channel5_IRQHandler
+DMA1_Channel6_IRQHandler
+DMA1_Channel7_IRQHandler
+ADC1_2_IRQHandler
+CAN1_TX_IRQHandler
+CAN1_RX0_IRQHandler
+CAN1_RX1_IRQHandler
+CAN1_SCE_IRQHandler
+EXTI9_5_IRQHandler
+TIM1_BRK_IRQHandler
+TIM1_UP_IRQHandler
+TIM1_TRG_COM_IRQHandler
+TIM1_CC_IRQHandler
+TIM2_IRQHandler
+TIM3_IRQHandler
+TIM4_IRQHandler
+I2C1_EV_IRQHandler
+I2C1_ER_IRQHandler
+I2C2_EV_IRQHandler
+I2C2_ER_IRQHandler
+SPI1_IRQHandler
+SPI2_IRQHandler
+USART1_IRQHandler
+USART2_IRQHandler
+USART3_IRQHandler
+EXTI15_10_IRQHandler
+RTCAlarm_IRQHandler
+OTG_FS_WKUP_IRQHandler
+TIM5_IRQHandler
+SPI3_IRQHandler
+UART4_IRQHandler
+UART5_IRQHandler
+TIM6_IRQHandler
+TIM7_IRQHandler
+DMA2_Channel1_IRQHandler
+DMA2_Channel2_IRQHandler
+DMA2_Channel3_IRQHandler
+DMA2_Channel4_IRQHandler
+DMA2_Channel5_IRQHandler
+ETH_IRQHandler
+ETH_WKUP_IRQHandler
+CAN2_TX_IRQHandler
+CAN2_RX0_IRQHandler
+CAN2_RX1_IRQHandler
+CAN2_SCE_IRQHandler
+OTG_FS_IRQHandler
+
+                B       .
+
+                ENDP
+
+                ALIGN
+
+;*******************************************************************************
+; User Stack and Heap initialization
+;*******************************************************************************
+                 IF      :DEF:__MICROLIB
+                
+                 EXPORT  __initial_sp
+                 EXPORT  __heap_base
+                 EXPORT  __heap_limit
+                
+                 ELSE
+                
+                 IMPORT  __use_two_region_memory
+                 EXPORT  __user_initial_stackheap
+                 
+__user_initial_stackheap
+
+                 LDR     R0, =  Heap_Mem
+                 LDR     R1, =(Stack_Mem + Stack_Size)
+                 LDR     R2, = (Heap_Mem +  Heap_Size)
+                 LDR     R3, = Stack_Mem
+                 BX      LR
+
+                 ALIGN
+
+                 ENDIF
+
+                 END
+
+;******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE*****
diff --git a/STM32_4路称重_Git提交精简工程/src/CMSIS/Startup/startup_stm32f10x_hd.s b/STM32_4路称重_Git提交精简工程/src/CMSIS/Startup/startup_stm32f10x_hd.s
new file mode 100755
index 0000000..adc9b94
--- /dev/null
+++ b/STM32_4路称重_Git提交精简工程/src/CMSIS/Startup/startup_stm32f10x_hd.s
@@ -0,0 +1,358 @@
+;******************** (C) COPYRIGHT 2011 STMicroelectronics ********************
+;* File Name          : startup_stm32f10x_hd.s
+;* Author             : MCD Application Team
+;* Version            : V3.5.0
+;* Date               : 11-March-2011
+;* Description        : STM32F10x High Density Devices vector table for MDK-ARM 
+;*                      toolchain. 
+;*                      This module performs:
+;*                      - Set the initial SP
+;*                      - Set the initial PC == Reset_Handler
+;*                      - Set the vector table entries with the exceptions ISR address
+;*                      - Configure the clock system and also configure the external 
+;*                        SRAM mounted on STM3210E-EVAL board to be used as data 
+;*                        memory (optional, to be enabled by user)
+;*                      - Branches to __main in the C library (which eventually
+;*                        calls main()).
+;*                      After Reset the CortexM3 processor is in Thread mode,
+;*                      priority is Privileged, and the Stack is set to Main.
+;* <<< Use Configuration Wizard in Context Menu >>>   
+;*******************************************************************************
+; THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+; WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
+; AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
+; INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
+; CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
+; INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+;*******************************************************************************
+
+; Amount of memory (in bytes) allocated for Stack
+; Tailor this value to your application needs
+; <h> Stack Configuration
+;   <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Stack_Size      EQU     0x00000400
+
+                AREA    STACK, NOINIT, READWRITE, ALIGN=3
+Stack_Mem       SPACE   Stack_Size
+__initial_sp
+                                                  
+; <h> Heap Configuration
+;   <o>  Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Heap_Size       EQU     0x00000200
+
+                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem        SPACE   Heap_Size
+__heap_limit
+
+                PRESERVE8
+                THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+                AREA    RESET, DATA, READONLY
+                EXPORT  __Vectors
+                EXPORT  __Vectors_End
+                EXPORT  __Vectors_Size
+
+__Vectors       DCD     __initial_sp               ; Top of Stack
+                DCD     Reset_Handler              ; Reset Handler
+                DCD     NMI_Handler                ; NMI Handler
+                DCD     HardFault_Handler          ; Hard Fault Handler
+                DCD     MemManage_Handler          ; MPU Fault Handler
+                DCD     BusFault_Handler           ; Bus Fault Handler
+                DCD     UsageFault_Handler         ; Usage Fault Handler
+                DCD     0                          ; Reserved
+                DCD     0                          ; Reserved
+                DCD     0                          ; Reserved
+                DCD     0                          ; Reserved
+                DCD     SVC_Handler                ; SVCall Handler
+                DCD     DebugMon_Handler           ; Debug Monitor Handler
+                DCD     0                          ; Reserved
+                DCD     PendSV_Handler             ; PendSV Handler
+                DCD     SysTick_Handler            ; SysTick Handler
+
+                ; External Interrupts
+                DCD     WWDG_IRQHandler            ; Window Watchdog
+                DCD     PVD_IRQHandler             ; PVD through EXTI Line detect
+                DCD     TAMPER_IRQHandler          ; Tamper
+                DCD     RTC_IRQHandler             ; RTC
+                DCD     FLASH_IRQHandler           ; Flash
+                DCD     RCC_IRQHandler             ; RCC
+                DCD     EXTI0_IRQHandler           ; EXTI Line 0
+                DCD     EXTI1_IRQHandler           ; EXTI Line 1
+                DCD     EXTI2_IRQHandler           ; EXTI Line 2
+                DCD     EXTI3_IRQHandler           ; EXTI Line 3
+                DCD     EXTI4_IRQHandler           ; EXTI Line 4
+                DCD     DMA1_Channel1_IRQHandler   ; DMA1 Channel 1
+                DCD     DMA1_Channel2_IRQHandler   ; DMA1 Channel 2
+                DCD     DMA1_Channel3_IRQHandler   ; DMA1 Channel 3
+                DCD     DMA1_Channel4_IRQHandler   ; DMA1 Channel 4
+                DCD     DMA1_Channel5_IRQHandler   ; DMA1 Channel 5
+                DCD     DMA1_Channel6_IRQHandler   ; DMA1 Channel 6
+                DCD     DMA1_Channel7_IRQHandler   ; DMA1 Channel 7
+                DCD     ADC1_2_IRQHandler          ; ADC1 & ADC2
+                DCD     USB_HP_CAN1_TX_IRQHandler  ; USB High Priority or CAN1 TX
+                DCD     USB_LP_CAN1_RX0_IRQHandler ; USB Low  Priority or CAN1 RX0
+                DCD     CAN1_RX1_IRQHandler        ; CAN1 RX1
+                DCD     CAN1_SCE_IRQHandler        ; CAN1 SCE
+                DCD     EXTI9_5_IRQHandler         ; EXTI Line 9..5
+                DCD     TIM1_BRK_IRQHandler        ; TIM1 Break
+                DCD     TIM1_UP_IRQHandler         ; TIM1 Update
+                DCD     TIM1_TRG_COM_IRQHandler    ; TIM1 Trigger and Commutation
+                DCD     TIM1_CC_IRQHandler         ; TIM1 Capture Compare
+                DCD     TIM2_IRQHandler            ; TIM2
+                DCD     TIM3_IRQHandler            ; TIM3
+                DCD     TIM4_IRQHandler            ; TIM4
+                DCD     I2C1_EV_IRQHandler         ; I2C1 Event
+                DCD     I2C1_ER_IRQHandler         ; I2C1 Error
+                DCD     I2C2_EV_IRQHandler         ; I2C2 Event
+                DCD     I2C2_ER_IRQHandler         ; I2C2 Error
+                DCD     SPI1_IRQHandler            ; SPI1
+                DCD     SPI2_IRQHandler            ; SPI2
+                DCD     USART1_IRQHandler          ; USART1
+                DCD     USART2_IRQHandler          ; USART2
+                DCD     USART3_IRQHandler          ; USART3
+                DCD     EXTI15_10_IRQHandler       ; EXTI Line 15..10
+                DCD     RTCAlarm_IRQHandler        ; RTC Alarm through EXTI Line
+                DCD     USBWakeUp_IRQHandler       ; USB Wakeup from suspend
+                DCD     TIM8_BRK_IRQHandler        ; TIM8 Break
+                DCD     TIM8_UP_IRQHandler         ; TIM8 Update
+                DCD     TIM8_TRG_COM_IRQHandler    ; TIM8 Trigger and Commutation
+                DCD     TIM8_CC_IRQHandler         ; TIM8 Capture Compare
+                DCD     ADC3_IRQHandler            ; ADC3
+                DCD     FSMC_IRQHandler            ; FSMC
+                DCD     SDIO_IRQHandler            ; SDIO
+                DCD     TIM5_IRQHandler            ; TIM5
+                DCD     SPI3_IRQHandler            ; SPI3
+                DCD     UART4_IRQHandler           ; UART4
+                DCD     UART5_IRQHandler           ; UART5
+                DCD     TIM6_IRQHandler            ; TIM6
+                DCD     TIM7_IRQHandler            ; TIM7
+                DCD     DMA2_Channel1_IRQHandler   ; DMA2 Channel1
+                DCD     DMA2_Channel2_IRQHandler   ; DMA2 Channel2
+                DCD     DMA2_Channel3_IRQHandler   ; DMA2 Channel3
+                DCD     DMA2_Channel4_5_IRQHandler ; DMA2 Channel4 & Channel5
+__Vectors_End
+
+__Vectors_Size  EQU  __Vectors_End - __Vectors
+
+                AREA    |.text|, CODE, READONLY
+                
+; Reset handler
+Reset_Handler   PROC
+                EXPORT  Reset_Handler             [WEAK]
+                IMPORT  __main
+                IMPORT  SystemInit
+                LDR     R0, =SystemInit
+                BLX     R0               
+                LDR     R0, =__main
+                BX      R0
+                ENDP
+                
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler     PROC
+                EXPORT  NMI_Handler                [WEAK]
+                B       .
+                ENDP
+HardFault_Handler\
+                PROC
+                EXPORT  HardFault_Handler          [WEAK]
+                B       .
+                ENDP
+MemManage_Handler\
+                PROC
+                EXPORT  MemManage_Handler          [WEAK]
+                B       .
+                ENDP
+BusFault_Handler\
+                PROC
+                EXPORT  BusFault_Handler           [WEAK]
+                B       .
+                ENDP
+UsageFault_Handler\
+                PROC
+                EXPORT  UsageFault_Handler         [WEAK]
+                B       .
+                ENDP
+SVC_Handler     PROC
+                EXPORT  SVC_Handler                [WEAK]
+                B       .
+                ENDP
+DebugMon_Handler\
+                PROC
+                EXPORT  DebugMon_Handler           [WEAK]
+                B       .
+                ENDP
+PendSV_Handler  PROC
+                EXPORT  PendSV_Handler             [WEAK]
+                B       .
+                ENDP
+SysTick_Handler PROC
+                EXPORT  SysTick_Handler            [WEAK]
+                B       .
+                ENDP
+
+Default_Handler PROC
+
+                EXPORT  WWDG_IRQHandler            [WEAK]
+                EXPORT  PVD_IRQHandler             [WEAK]
+                EXPORT  TAMPER_IRQHandler          [WEAK]
+                EXPORT  RTC_IRQHandler             [WEAK]
+                EXPORT  FLASH_IRQHandler           [WEAK]
+                EXPORT  RCC_IRQHandler             [WEAK]
+                EXPORT  EXTI0_IRQHandler           [WEAK]
+                EXPORT  EXTI1_IRQHandler           [WEAK]
+                EXPORT  EXTI2_IRQHandler           [WEAK]
+                EXPORT  EXTI3_IRQHandler           [WEAK]
+                EXPORT  EXTI4_IRQHandler           [WEAK]
+                EXPORT  DMA1_Channel1_IRQHandler   [WEAK]
+                EXPORT  DMA1_Channel2_IRQHandler   [WEAK]
+                EXPORT  DMA1_Channel3_IRQHandler   [WEAK]
+                EXPORT  DMA1_Channel4_IRQHandler   [WEAK]
+                EXPORT  DMA1_Channel5_IRQHandler   [WEAK]
+                EXPORT  DMA1_Channel6_IRQHandler   [WEAK]
+                EXPORT  DMA1_Channel7_IRQHandler   [WEAK]
+                EXPORT  ADC1_2_IRQHandler          [WEAK]
+                EXPORT  USB_HP_CAN1_TX_IRQHandler  [WEAK]
+                EXPORT  USB_LP_CAN1_RX0_IRQHandler [WEAK]
+                EXPORT  CAN1_RX1_IRQHandler        [WEAK]
+                EXPORT  CAN1_SCE_IRQHandler        [WEAK]
+                EXPORT  EXTI9_5_IRQHandler         [WEAK]
+                EXPORT  TIM1_BRK_IRQHandler        [WEAK]
+                EXPORT  TIM1_UP_IRQHandler         [WEAK]
+                EXPORT  TIM1_TRG_COM_IRQHandler    [WEAK]
+                EXPORT  TIM1_CC_IRQHandler         [WEAK]
+                EXPORT  TIM2_IRQHandler            [WEAK]
+                EXPORT  TIM3_IRQHandler            [WEAK]
+                EXPORT  TIM4_IRQHandler            [WEAK]
+                EXPORT  I2C1_EV_IRQHandler         [WEAK]
+                EXPORT  I2C1_ER_IRQHandler         [WEAK]
+                EXPORT  I2C2_EV_IRQHandler         [WEAK]
+                EXPORT  I2C2_ER_IRQHandler         [WEAK]
+                EXPORT  SPI1_IRQHandler            [WEAK]
+                EXPORT  SPI2_IRQHandler            [WEAK]
+                EXPORT  USART1_IRQHandler          [WEAK]
+                EXPORT  USART2_IRQHandler          [WEAK]
+                EXPORT  USART3_IRQHandler          [WEAK]
+                EXPORT  EXTI15_10_IRQHandler       [WEAK]
+                EXPORT  RTCAlarm_IRQHandler        [WEAK]
+                EXPORT  USBWakeUp_IRQHandler       [WEAK]
+                EXPORT  TIM8_BRK_IRQHandler        [WEAK]
+                EXPORT  TIM8_UP_IRQHandler         [WEAK]
+                EXPORT  TIM8_TRG_COM_IRQHandler    [WEAK]
+                EXPORT  TIM8_CC_IRQHandler         [WEAK]
+                EXPORT  ADC3_IRQHandler            [WEAK]
+                EXPORT  FSMC_IRQHandler            [WEAK]
+                EXPORT  SDIO_IRQHandler            [WEAK]
+                EXPORT  TIM5_IRQHandler            [WEAK]
+                EXPORT  SPI3_IRQHandler            [WEAK]
+                EXPORT  UART4_IRQHandler           [WEAK]
+                EXPORT  UART5_IRQHandler           [WEAK]
+                EXPORT  TIM6_IRQHandler            [WEAK]
+                EXPORT  TIM7_IRQHandler            [WEAK]
+                EXPORT  DMA2_Channel1_IRQHandler   [WEAK]
+                EXPORT  DMA2_Channel2_IRQHandler   [WEAK]
+                EXPORT  DMA2_Channel3_IRQHandler   [WEAK]
+                EXPORT  DMA2_Channel4_5_IRQHandler [WEAK]
+
+WWDG_IRQHandler
+PVD_IRQHandler
+TAMPER_IRQHandler
+RTC_IRQHandler
+FLASH_IRQHandler
+RCC_IRQHandler
+EXTI0_IRQHandler
+EXTI1_IRQHandler
+EXTI2_IRQHandler
+EXTI3_IRQHandler
+EXTI4_IRQHandler
+DMA1_Channel1_IRQHandler
+DMA1_Channel2_IRQHandler
+DMA1_Channel3_IRQHandler
+DMA1_Channel4_IRQHandler
+DMA1_Channel5_IRQHandler
+DMA1_Channel6_IRQHandler
+DMA1_Channel7_IRQHandler
+ADC1_2_IRQHandler
+USB_HP_CAN1_TX_IRQHandler
+USB_LP_CAN1_RX0_IRQHandler
+CAN1_RX1_IRQHandler
+CAN1_SCE_IRQHandler
+EXTI9_5_IRQHandler
+TIM1_BRK_IRQHandler
+TIM1_UP_IRQHandler
+TIM1_TRG_COM_IRQHandler
+TIM1_CC_IRQHandler
+TIM2_IRQHandler
+TIM3_IRQHandler
+TIM4_IRQHandler
+I2C1_EV_IRQHandler
+I2C1_ER_IRQHandler
+I2C2_EV_IRQHandler
+I2C2_ER_IRQHandler
+SPI1_IRQHandler
+SPI2_IRQHandler
+USART1_IRQHandler
+USART2_IRQHandler
+USART3_IRQHandler
+EXTI15_10_IRQHandler
+RTCAlarm_IRQHandler
+USBWakeUp_IRQHandler
+TIM8_BRK_IRQHandler
+TIM8_UP_IRQHandler
+TIM8_TRG_COM_IRQHandler
+TIM8_CC_IRQHandler
+ADC3_IRQHandler
+FSMC_IRQHandler
+SDIO_IRQHandler
+TIM5_IRQHandler
+SPI3_IRQHandler
+UART4_IRQHandler
+UART5_IRQHandler
+TIM6_IRQHandler
+TIM7_IRQHandler
+DMA2_Channel1_IRQHandler
+DMA2_Channel2_IRQHandler
+DMA2_Channel3_IRQHandler
+DMA2_Channel4_5_IRQHandler
+                B       .
+
+                ENDP
+
+                ALIGN
+
+;*******************************************************************************
+; User Stack and Heap initialization
+;*******************************************************************************
+                 IF      :DEF:__MICROLIB
+                
+                 EXPORT  __initial_sp
+                 EXPORT  __heap_base
+                 EXPORT  __heap_limit
+                
+                 ELSE
+                
+                 IMPORT  __use_two_region_memory
+                 EXPORT  __user_initial_stackheap
+                 
+__user_initial_stackheap
+
+                 LDR     R0, =  Heap_Mem
+                 LDR     R1, =(Stack_Mem + Stack_Size)
+                 LDR     R2, = (Heap_Mem +  Heap_Size)
+                 LDR     R3, = Stack_Mem
+                 BX      LR
+
+                 ALIGN
+
+                 ENDIF
+
+                 END
+
+;******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE*****
diff --git a/STM32_4路称重_Git提交精简工程/src/CMSIS/Startup/startup_stm32f10x_hd_vl.s b/STM32_4路称重_Git提交精简工程/src/CMSIS/Startup/startup_stm32f10x_hd_vl.s
new file mode 100755
index 0000000..d6082b0
--- /dev/null
+++ b/STM32_4路称重_Git提交精简工程/src/CMSIS/Startup/startup_stm32f10x_hd_vl.s
@@ -0,0 +1,346 @@
+;******************** (C) COPYRIGHT 2011 STMicroelectronics ********************
+;* File Name          : startup_stm32f10x_hd_vl.s
+;* Author             : MCD Application Team
+;* Version            : V3.5.0
+;* Date               : 11-March-2011
+;* Description        : STM32F10x High Density Value Line Devices vector table  
+;*                      for MDK-ARM toolchain.  
+;*                      This module performs:
+;*                      - Set the initial SP
+;*                      - Set the initial PC == Reset_Handler
+;*                      - Set the vector table entries with the exceptions ISR address
+;*                      - Configure the clock system and also configure the external 
+;*                        SRAM mounted on STM32100E-EVAL board to be used as data 
+;*                        memory (optional, to be enabled by user)
+;*                      - Branches to __main in the C library (which eventually
+;*                        calls main()).
+;*                      After Reset the CortexM3 processor is in Thread mode,
+;*                      priority is Privileged, and the Stack is set to Main.
+;* <<< Use Configuration Wizard in Context Menu >>>   
+;*******************************************************************************
+; THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+; WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
+; AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
+; INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
+; CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
+; INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+;*******************************************************************************
+
+; Amount of memory (in bytes) allocated for Stack
+; Tailor this value to your application needs
+; <h> Stack Configuration
+;   <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Stack_Size      EQU     0x00000400
+
+                AREA    STACK, NOINIT, READWRITE, ALIGN=3
+Stack_Mem       SPACE   Stack_Size
+__initial_sp
+
+
+; <h> Heap Configuration
+;   <o>  Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Heap_Size       EQU     0x00000200
+
+                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem        SPACE   Heap_Size
+__heap_limit
+
+                PRESERVE8
+                THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+                AREA    RESET, DATA, READONLY
+                EXPORT  __Vectors
+                EXPORT  __Vectors_End
+                EXPORT  __Vectors_Size
+
+__Vectors       DCD     __initial_sp                    ; Top of Stack
+                DCD     Reset_Handler                   ; Reset Handler
+                DCD     NMI_Handler                     ; NMI Handler
+                DCD     HardFault_Handler               ; Hard Fault Handler
+                DCD     MemManage_Handler               ; MPU Fault Handler
+                DCD     BusFault_Handler                ; Bus Fault Handler
+                DCD     UsageFault_Handler              ; Usage Fault Handler
+                DCD     0                               ; Reserved
+                DCD     0                               ; Reserved
+                DCD     0                               ; Reserved
+                DCD     0                               ; Reserved
+                DCD     SVC_Handler                     ; SVCall Handler
+                DCD     DebugMon_Handler                ; Debug Monitor Handler
+                DCD     0                               ; Reserved
+                DCD     PendSV_Handler                  ; PendSV Handler
+                DCD     SysTick_Handler                 ; SysTick Handler
+
+                ; External Interrupts
+                DCD     WWDG_IRQHandler                 ; Window Watchdog
+                DCD     PVD_IRQHandler                  ; PVD through EXTI Line detect
+                DCD     TAMPER_IRQHandler               ; Tamper
+                DCD     RTC_IRQHandler                  ; RTC
+                DCD     FLASH_IRQHandler                ; Flash
+                DCD     RCC_IRQHandler                  ; RCC
+                DCD     EXTI0_IRQHandler                ; EXTI Line 0
+                DCD     EXTI1_IRQHandler                ; EXTI Line 1
+                DCD     EXTI2_IRQHandler                ; EXTI Line 2
+                DCD     EXTI3_IRQHandler                ; EXTI Line 3
+                DCD     EXTI4_IRQHandler                ; EXTI Line 4
+                DCD     DMA1_Channel1_IRQHandler        ; DMA1 Channel 1
+                DCD     DMA1_Channel2_IRQHandler        ; DMA1 Channel 2
+                DCD     DMA1_Channel3_IRQHandler        ; DMA1 Channel 3
+                DCD     DMA1_Channel4_IRQHandler        ; DMA1 Channel 4
+                DCD     DMA1_Channel5_IRQHandler        ; DMA1 Channel 5
+                DCD     DMA1_Channel6_IRQHandler        ; DMA1 Channel 6
+                DCD     DMA1_Channel7_IRQHandler        ; DMA1 Channel 7
+                DCD     ADC1_IRQHandler                 ; ADC1
+                DCD     0                               ; Reserved
+                DCD     0                               ; Reserved
+                DCD     0                               ; Reserved
+                DCD     0                               ; Reserved
+                DCD     EXTI9_5_IRQHandler              ; EXTI Line 9..5
+                DCD     TIM1_BRK_TIM15_IRQHandler       ; TIM1 Break and TIM15
+                DCD     TIM1_UP_TIM16_IRQHandler        ; TIM1 Update and TIM16
+                DCD     TIM1_TRG_COM_TIM17_IRQHandler   ; TIM1 Trigger and Commutation and TIM17
+                DCD     TIM1_CC_IRQHandler              ; TIM1 Capture Compare
+                DCD     TIM2_IRQHandler                 ; TIM2
+                DCD     TIM3_IRQHandler                 ; TIM3
+                DCD     TIM4_IRQHandler                 ; TIM4
+                DCD     I2C1_EV_IRQHandler              ; I2C1 Event
+                DCD     I2C1_ER_IRQHandler              ; I2C1 Error
+                DCD     I2C2_EV_IRQHandler              ; I2C2 Event
+                DCD     I2C2_ER_IRQHandler              ; I2C2 Error
+                DCD     SPI1_IRQHandler                 ; SPI1
+                DCD     SPI2_IRQHandler                 ; SPI2
+                DCD     USART1_IRQHandler               ; USART1
+                DCD     USART2_IRQHandler               ; USART2
+                DCD     USART3_IRQHandler               ; USART3
+                DCD     EXTI15_10_IRQHandler            ; EXTI Line 15..10
+                DCD     RTCAlarm_IRQHandler             ; RTC Alarm through EXTI Line
+                DCD     CEC_IRQHandler                  ; HDMI-CEC
+                DCD     TIM12_IRQHandler                ; TIM12
+                DCD     TIM13_IRQHandler                ; TIM13 
+                DCD     TIM14_IRQHandler                ; TIM14
+                DCD     0                               ; Reserved
+                DCD     0                               ; Reserved
+                DCD     0                               ; Reserved
+                DCD     0                               ; Reserved
+                DCD     TIM5_IRQHandler                 ; TIM5
+                DCD     SPI3_IRQHandler                 ; SPI3
+                DCD     UART4_IRQHandler                ; UART4
+                DCD     UART5_IRQHandler                ; UART5
+                DCD     TIM6_DAC_IRQHandler             ; TIM6 and DAC underrun
+                DCD     TIM7_IRQHandler                 ; TIM7
+                DCD     DMA2_Channel1_IRQHandler        ; DMA2 Channel1
+                DCD     DMA2_Channel2_IRQHandler        ; DMA2 Channel2
+                DCD     DMA2_Channel3_IRQHandler        ; DMA2 Channel3
+                DCD     DMA2_Channel4_5_IRQHandler      ; DMA2 Channel4 & Channel5
+                DCD     DMA2_Channel5_IRQHandler        ; DMA2 Channel5                
+__Vectors_End
+
+__Vectors_Size  EQU  __Vectors_End - __Vectors
+
+                AREA    |.text|, CODE, READONLY
+
+; Reset handler
+Reset_Handler    PROC
+                 EXPORT  Reset_Handler             [WEAK]
+     IMPORT  __main
+     IMPORT  SystemInit
+                 LDR     R0, =SystemInit
+                 BLX     R0
+                 LDR     R0, =__main
+                 BX      R0
+                 ENDP
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler     PROC
+                EXPORT  NMI_Handler                      [WEAK]
+                B       .
+                ENDP
+HardFault_Handler\
+                PROC
+                EXPORT  HardFault_Handler                [WEAK]
+                B       .
+                ENDP
+MemManage_Handler\
+                PROC
+                EXPORT  MemManage_Handler                [WEAK]
+                B       .
+                ENDP
+BusFault_Handler\
+                PROC
+                EXPORT  BusFault_Handler                 [WEAK]
+                B       .
+                ENDP
+UsageFault_Handler\
+                PROC
+                EXPORT  UsageFault_Handler               [WEAK]
+                B       .
+                ENDP
+SVC_Handler     PROC
+                EXPORT  SVC_Handler                      [WEAK]
+                B       .
+                ENDP
+DebugMon_Handler\
+                PROC
+                EXPORT  DebugMon_Handler                 [WEAK]
+                B       .
+                ENDP
+PendSV_Handler  PROC
+                EXPORT  PendSV_Handler                   [WEAK]
+                B       .
+                ENDP
+SysTick_Handler PROC
+                EXPORT  SysTick_Handler                  [WEAK]
+                B       .
+                ENDP
+
+Default_Handler PROC
+
+                EXPORT  WWDG_IRQHandler                  [WEAK]
+                EXPORT  PVD_IRQHandler                   [WEAK]
+                EXPORT  TAMPER_IRQHandler                [WEAK]
+                EXPORT  RTC_IRQHandler                   [WEAK]
+                EXPORT  FLASH_IRQHandler                 [WEAK]
+                EXPORT  RCC_IRQHandler                   [WEAK]
+                EXPORT  EXTI0_IRQHandler                 [WEAK]
+                EXPORT  EXTI1_IRQHandler                 [WEAK]
+                EXPORT  EXTI2_IRQHandler                 [WEAK]
+                EXPORT  EXTI3_IRQHandler                 [WEAK]
+                EXPORT  EXTI4_IRQHandler                 [WEAK]
+                EXPORT  DMA1_Channel1_IRQHandler         [WEAK]
+                EXPORT  DMA1_Channel2_IRQHandler         [WEAK]
+                EXPORT  DMA1_Channel3_IRQHandler         [WEAK]
+                EXPORT  DMA1_Channel4_IRQHandler         [WEAK]
+                EXPORT  DMA1_Channel5_IRQHandler         [WEAK]
+                EXPORT  DMA1_Channel6_IRQHandler         [WEAK]
+                EXPORT  DMA1_Channel7_IRQHandler         [WEAK]
+                EXPORT  ADC1_IRQHandler                  [WEAK]
+                EXPORT  EXTI9_5_IRQHandler               [WEAK]
+                EXPORT  TIM1_BRK_TIM15_IRQHandler        [WEAK]
+                EXPORT  TIM1_UP_TIM16_IRQHandler         [WEAK]
+                EXPORT  TIM1_TRG_COM_TIM17_IRQHandler    [WEAK]
+                EXPORT  TIM1_CC_IRQHandler               [WEAK]
+                EXPORT  TIM2_IRQHandler                  [WEAK]
+                EXPORT  TIM3_IRQHandler                  [WEAK]
+                EXPORT  TIM4_IRQHandler                  [WEAK]
+                EXPORT  I2C1_EV_IRQHandler               [WEAK]
+                EXPORT  I2C1_ER_IRQHandler               [WEAK]
+                EXPORT  I2C2_EV_IRQHandler               [WEAK]
+                EXPORT  I2C2_ER_IRQHandler               [WEAK]
+                EXPORT  SPI1_IRQHandler                  [WEAK]
+                EXPORT  SPI2_IRQHandler                  [WEAK]
+                EXPORT  USART1_IRQHandler                [WEAK]
+                EXPORT  USART2_IRQHandler                [WEAK]
+                EXPORT  USART3_IRQHandler                [WEAK]
+                EXPORT  EXTI15_10_IRQHandler             [WEAK]
+                EXPORT  RTCAlarm_IRQHandler              [WEAK]
+                EXPORT  CEC_IRQHandler                   [WEAK]
+                EXPORT  TIM12_IRQHandler                 [WEAK]
+                EXPORT  TIM13_IRQHandler                 [WEAK]
+                EXPORT  TIM14_IRQHandler                 [WEAK]
+                EXPORT  TIM5_IRQHandler                  [WEAK]
+                EXPORT  SPI3_IRQHandler                  [WEAK]
+                EXPORT  UART4_IRQHandler                 [WEAK]
+                EXPORT  UART5_IRQHandler                 [WEAK]                
+                EXPORT  TIM6_DAC_IRQHandler              [WEAK]
+                EXPORT  TIM7_IRQHandler                  [WEAK]
+                EXPORT  DMA2_Channel1_IRQHandler         [WEAK]
+                EXPORT  DMA2_Channel2_IRQHandler         [WEAK]
+                EXPORT  DMA2_Channel3_IRQHandler         [WEAK]
+                EXPORT  DMA2_Channel4_5_IRQHandler       [WEAK]
+                EXPORT  DMA2_Channel5_IRQHandler         [WEAK]                
+
+WWDG_IRQHandler
+PVD_IRQHandler
+TAMPER_IRQHandler
+RTC_IRQHandler
+FLASH_IRQHandler
+RCC_IRQHandler
+EXTI0_IRQHandler
+EXTI1_IRQHandler
+EXTI2_IRQHandler
+EXTI3_IRQHandler
+EXTI4_IRQHandler
+DMA1_Channel1_IRQHandler
+DMA1_Channel2_IRQHandler
+DMA1_Channel3_IRQHandler
+DMA1_Channel4_IRQHandler
+DMA1_Channel5_IRQHandler
+DMA1_Channel6_IRQHandler
+DMA1_Channel7_IRQHandler
+ADC1_IRQHandler
+EXTI9_5_IRQHandler
+TIM1_BRK_TIM15_IRQHandler
+TIM1_UP_TIM16_IRQHandler
+TIM1_TRG_COM_TIM17_IRQHandler
+TIM1_CC_IRQHandler
+TIM2_IRQHandler
+TIM3_IRQHandler
+TIM4_IRQHandler
+I2C1_EV_IRQHandler
+I2C1_ER_IRQHandler
+I2C2_EV_IRQHandler
+I2C2_ER_IRQHandler
+SPI1_IRQHandler
+SPI2_IRQHandler
+USART1_IRQHandler
+USART2_IRQHandler
+USART3_IRQHandler
+EXTI15_10_IRQHandler
+RTCAlarm_IRQHandler
+CEC_IRQHandler
+TIM12_IRQHandler
+TIM13_IRQHandler
+TIM14_IRQHandler
+TIM5_IRQHandler
+SPI3_IRQHandler
+UART4_IRQHandler
+UART5_IRQHandler
+TIM6_DAC_IRQHandler
+TIM7_IRQHandler
+DMA2_Channel1_IRQHandler
+DMA2_Channel2_IRQHandler
+DMA2_Channel3_IRQHandler
+DMA2_Channel4_5_IRQHandler
+DMA2_Channel5_IRQHandler
+                B       .
+
+                ENDP
+
+                ALIGN
+
+;*******************************************************************************
+; User Stack and Heap initialization
+;*******************************************************************************
+                 IF      :DEF:__MICROLIB           
+                
+                 EXPORT  __initial_sp
+                 EXPORT  __heap_base
+                 EXPORT  __heap_limit
+                
+                 ELSE
+                
+                 IMPORT  __use_two_region_memory
+                 EXPORT  __user_initial_stackheap
+                 
+__user_initial_stackheap
+
+                 LDR     R0, =  Heap_Mem
+                 LDR     R1, =(Stack_Mem + Stack_Size)
+                 LDR     R2, = (Heap_Mem +  Heap_Size)
+                 LDR     R3, = Stack_Mem
+                 BX      LR
+
+                 ALIGN
+
+                 ENDIF
+
+                 END
+
+;******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE*****
diff --git a/STM32_4路称重_Git提交精简工程/src/CMSIS/Startup/startup_stm32f10x_ld.s b/STM32_4路称重_Git提交精简工程/src/CMSIS/Startup/startup_stm32f10x_ld.s
new file mode 100755
index 0000000..3f3ac2f
--- /dev/null
+++ b/STM32_4路称重_Git提交精简工程/src/CMSIS/Startup/startup_stm32f10x_ld.s
@@ -0,0 +1,297 @@
+;******************** (C) COPYRIGHT 2011 STMicroelectronics ********************
+;* File Name          : startup_stm32f10x_ld.s
+;* Author             : MCD Application Team
+;* Version            : V3.5.0
+;* Date               : 11-March-2011
+;* Description        : STM32F10x Low Density Devices vector table for MDK-ARM 
+;*                      toolchain. 
+;*                      This module performs:
+;*                      - Set the initial SP
+;*                      - Set the initial PC == Reset_Handler
+;*                      - Set the vector table entries with the exceptions ISR address
+;*                      - Configure the clock system
+;*                      - Branches to __main in the C library (which eventually
+;*                        calls main()).
+;*                      After Reset the CortexM3 processor is in Thread mode,
+;*                      priority is Privileged, and the Stack is set to Main.
+;* <<< Use Configuration Wizard in Context Menu >>>   
+;*******************************************************************************
+; THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+; WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
+; AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
+; INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
+; CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
+; INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+;*******************************************************************************
+
+; Amount of memory (in bytes) allocated for Stack
+; Tailor this value to your application needs
+; <h> Stack Configuration
+;   <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Stack_Size      EQU     0x00000400
+
+                AREA    STACK, NOINIT, READWRITE, ALIGN=3
+Stack_Mem       SPACE   Stack_Size
+__initial_sp
+
+
+; <h> Heap Configuration
+;   <o>  Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Heap_Size       EQU     0x00000200
+
+                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem        SPACE   Heap_Size
+__heap_limit
+
+                PRESERVE8
+                THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+                AREA    RESET, DATA, READONLY
+                EXPORT  __Vectors
+                EXPORT  __Vectors_End
+                EXPORT  __Vectors_Size
+
+__Vectors       DCD     __initial_sp               ; Top of Stack
+                DCD     Reset_Handler              ; Reset Handler
+                DCD     NMI_Handler                ; NMI Handler
+                DCD     HardFault_Handler          ; Hard Fault Handler
+                DCD     MemManage_Handler          ; MPU Fault Handler
+                DCD     BusFault_Handler           ; Bus Fault Handler
+                DCD     UsageFault_Handler         ; Usage Fault Handler
+                DCD     0                          ; Reserved
+                DCD     0                          ; Reserved
+                DCD     0                          ; Reserved
+                DCD     0                          ; Reserved
+                DCD     SVC_Handler                ; SVCall Handler
+                DCD     DebugMon_Handler           ; Debug Monitor Handler
+                DCD     0                          ; Reserved
+                DCD     PendSV_Handler             ; PendSV Handler
+                DCD     SysTick_Handler            ; SysTick Handler
+
+                ; External Interrupts
+                DCD     WWDG_IRQHandler            ; Window Watchdog
+                DCD     PVD_IRQHandler             ; PVD through EXTI Line detect
+                DCD     TAMPER_IRQHandler          ; Tamper
+                DCD     RTC_IRQHandler             ; RTC
+                DCD     FLASH_IRQHandler           ; Flash
+                DCD     RCC_IRQHandler             ; RCC
+                DCD     EXTI0_IRQHandler           ; EXTI Line 0
+                DCD     EXTI1_IRQHandler           ; EXTI Line 1
+                DCD     EXTI2_IRQHandler           ; EXTI Line 2
+                DCD     EXTI3_IRQHandler           ; EXTI Line 3
+                DCD     EXTI4_IRQHandler           ; EXTI Line 4
+                DCD     DMA1_Channel1_IRQHandler   ; DMA1 Channel 1
+                DCD     DMA1_Channel2_IRQHandler   ; DMA1 Channel 2
+                DCD     DMA1_Channel3_IRQHandler   ; DMA1 Channel 3
+                DCD     DMA1_Channel4_IRQHandler   ; DMA1 Channel 4
+                DCD     DMA1_Channel5_IRQHandler   ; DMA1 Channel 5
+                DCD     DMA1_Channel6_IRQHandler   ; DMA1 Channel 6
+                DCD     DMA1_Channel7_IRQHandler   ; DMA1 Channel 7
+                DCD     ADC1_2_IRQHandler          ; ADC1_2
+                DCD     USB_HP_CAN1_TX_IRQHandler  ; USB High Priority or CAN1 TX
+                DCD     USB_LP_CAN1_RX0_IRQHandler ; USB Low  Priority or CAN1 RX0
+                DCD     CAN1_RX1_IRQHandler        ; CAN1 RX1
+                DCD     CAN1_SCE_IRQHandler        ; CAN1 SCE
+                DCD     EXTI9_5_IRQHandler         ; EXTI Line 9..5
+                DCD     TIM1_BRK_IRQHandler        ; TIM1 Break
+                DCD     TIM1_UP_IRQHandler         ; TIM1 Update
+                DCD     TIM1_TRG_COM_IRQHandler    ; TIM1 Trigger and Commutation
+                DCD     TIM1_CC_IRQHandler         ; TIM1 Capture Compare
+                DCD     TIM2_IRQHandler            ; TIM2
+                DCD     TIM3_IRQHandler            ; TIM3
+                DCD     0                          ; Reserved
+                DCD     I2C1_EV_IRQHandler         ; I2C1 Event
+                DCD     I2C1_ER_IRQHandler         ; I2C1 Error
+                DCD     0                          ; Reserved
+                DCD     0                          ; Reserved
+                DCD     SPI1_IRQHandler            ; SPI1
+                DCD     0                          ; Reserved
+                DCD     USART1_IRQHandler          ; USART1
+                DCD     USART2_IRQHandler          ; USART2
+                DCD     0                          ; Reserved
+                DCD     EXTI15_10_IRQHandler       ; EXTI Line 15..10
+                DCD     RTCAlarm_IRQHandler        ; RTC Alarm through EXTI Line
+                DCD     USBWakeUp_IRQHandler       ; USB Wakeup from suspend
+__Vectors_End
+
+__Vectors_Size  EQU  __Vectors_End - __Vectors
+
+                AREA    |.text|, CODE, READONLY
+
+; Reset handler routine
+Reset_Handler    PROC
+                 EXPORT  Reset_Handler             [WEAK]
+     IMPORT  __main
+     IMPORT  SystemInit
+                 LDR     R0, =SystemInit
+                 BLX     R0
+                 LDR     R0, =__main
+                 BX      R0
+                 ENDP
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler     PROC
+                EXPORT  NMI_Handler                [WEAK]
+                B       .
+                ENDP
+HardFault_Handler\
+                PROC
+                EXPORT  HardFault_Handler          [WEAK]
+                B       .
+                ENDP
+MemManage_Handler\
+                PROC
+                EXPORT  MemManage_Handler          [WEAK]
+                B       .
+                ENDP
+BusFault_Handler\
+                PROC
+                EXPORT  BusFault_Handler           [WEAK]
+                B       .
+                ENDP
+UsageFault_Handler\
+                PROC
+                EXPORT  UsageFault_Handler         [WEAK]
+                B       .
+                ENDP
+SVC_Handler     PROC
+                EXPORT  SVC_Handler                [WEAK]
+                B       .
+                ENDP
+DebugMon_Handler\
+                PROC
+                EXPORT  DebugMon_Handler           [WEAK]
+                B       .
+                ENDP
+PendSV_Handler  PROC
+                EXPORT  PendSV_Handler             [WEAK]
+                B       .
+                ENDP
+SysTick_Handler PROC
+                EXPORT  SysTick_Handler            [WEAK]
+                B       .
+                ENDP
+
+Default_Handler PROC
+
+                EXPORT  WWDG_IRQHandler            [WEAK]
+                EXPORT  PVD_IRQHandler             [WEAK]
+                EXPORT  TAMPER_IRQHandler          [WEAK]
+                EXPORT  RTC_IRQHandler             [WEAK]
+                EXPORT  FLASH_IRQHandler           [WEAK]
+                EXPORT  RCC_IRQHandler             [WEAK]
+                EXPORT  EXTI0_IRQHandler           [WEAK]
+                EXPORT  EXTI1_IRQHandler           [WEAK]
+                EXPORT  EXTI2_IRQHandler           [WEAK]
+                EXPORT  EXTI3_IRQHandler           [WEAK]
+                EXPORT  EXTI4_IRQHandler           [WEAK]
+                EXPORT  DMA1_Channel1_IRQHandler   [WEAK]
+                EXPORT  DMA1_Channel2_IRQHandler   [WEAK]
+                EXPORT  DMA1_Channel3_IRQHandler   [WEAK]
+                EXPORT  DMA1_Channel4_IRQHandler   [WEAK]
+                EXPORT  DMA1_Channel5_IRQHandler   [WEAK]
+                EXPORT  DMA1_Channel6_IRQHandler   [WEAK]
+                EXPORT  DMA1_Channel7_IRQHandler   [WEAK]
+                EXPORT  ADC1_2_IRQHandler          [WEAK]
+                EXPORT  USB_HP_CAN1_TX_IRQHandler  [WEAK]
+                EXPORT  USB_LP_CAN1_RX0_IRQHandler [WEAK]
+                EXPORT  CAN1_RX1_IRQHandler        [WEAK]
+                EXPORT  CAN1_SCE_IRQHandler        [WEAK]
+                EXPORT  EXTI9_5_IRQHandler         [WEAK]
+                EXPORT  TIM1_BRK_IRQHandler        [WEAK]
+                EXPORT  TIM1_UP_IRQHandler         [WEAK]
+                EXPORT  TIM1_TRG_COM_IRQHandler    [WEAK]
+                EXPORT  TIM1_CC_IRQHandler         [WEAK]
+                EXPORT  TIM2_IRQHandler            [WEAK]
+                EXPORT  TIM3_IRQHandler            [WEAK]
+                EXPORT  I2C1_EV_IRQHandler         [WEAK]
+                EXPORT  I2C1_ER_IRQHandler         [WEAK]
+                EXPORT  SPI1_IRQHandler            [WEAK]
+                EXPORT  USART1_IRQHandler          [WEAK]
+                EXPORT  USART2_IRQHandler          [WEAK]
+                EXPORT  EXTI15_10_IRQHandler       [WEAK]
+                EXPORT  RTCAlarm_IRQHandler        [WEAK]
+                EXPORT  USBWakeUp_IRQHandler       [WEAK]
+
+WWDG_IRQHandler
+PVD_IRQHandler
+TAMPER_IRQHandler
+RTC_IRQHandler
+FLASH_IRQHandler
+RCC_IRQHandler
+EXTI0_IRQHandler
+EXTI1_IRQHandler
+EXTI2_IRQHandler
+EXTI3_IRQHandler
+EXTI4_IRQHandler
+DMA1_Channel1_IRQHandler
+DMA1_Channel2_IRQHandler
+DMA1_Channel3_IRQHandler
+DMA1_Channel4_IRQHandler
+DMA1_Channel5_IRQHandler
+DMA1_Channel6_IRQHandler
+DMA1_Channel7_IRQHandler
+ADC1_2_IRQHandler
+USB_HP_CAN1_TX_IRQHandler
+USB_LP_CAN1_RX0_IRQHandler
+CAN1_RX1_IRQHandler
+CAN1_SCE_IRQHandler
+EXTI9_5_IRQHandler
+TIM1_BRK_IRQHandler
+TIM1_UP_IRQHandler
+TIM1_TRG_COM_IRQHandler
+TIM1_CC_IRQHandler
+TIM2_IRQHandler
+TIM3_IRQHandler
+I2C1_EV_IRQHandler
+I2C1_ER_IRQHandler
+SPI1_IRQHandler
+USART1_IRQHandler
+USART2_IRQHandler
+EXTI15_10_IRQHandler
+RTCAlarm_IRQHandler
+USBWakeUp_IRQHandler
+
+                B       .
+
+                ENDP
+
+                ALIGN
+
+;*******************************************************************************
+; User Stack and Heap initialization
+;*******************************************************************************
+                 IF      :DEF:__MICROLIB
+                
+                 EXPORT  __initial_sp
+                 EXPORT  __heap_base
+                 EXPORT  __heap_limit
+                
+                 ELSE
+                
+                 IMPORT  __use_two_region_memory
+                 EXPORT  __user_initial_stackheap
+                 
+__user_initial_stackheap
+
+                 LDR     R0, =  Heap_Mem
+                 LDR     R1, =(Stack_Mem + Stack_Size)
+                 LDR     R2, = (Heap_Mem +  Heap_Size)
+                 LDR     R3, = Stack_Mem
+                 BX      LR
+
+                 ALIGN
+
+                 ENDIF
+
+                 END
+
+;******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE*****
diff --git a/STM32_4路称重_Git提交精简工程/src/CMSIS/Startup/startup_stm32f10x_ld_vl.s b/STM32_4路称重_Git提交精简工程/src/CMSIS/Startup/startup_stm32f10x_ld_vl.s
new file mode 100755
index 0000000..fe22fc0
--- /dev/null
+++ b/STM32_4路称重_Git提交精简工程/src/CMSIS/Startup/startup_stm32f10x_ld_vl.s
@@ -0,0 +1,304 @@
+;******************** (C) COPYRIGHT 2011 STMicroelectronics ********************
+;* File Name          : startup_stm32f10x_ld_vl.s
+;* Author             : MCD Application Team
+;* Version            : V3.5.0
+;* Date               : 11-March-2011
+;* Description        : STM32F10x Low Density Value Line Devices vector table  
+;*                      for MDK-ARM toolchain.  
+;*                      This module performs:
+;*                      - Set the initial SP
+;*                      - Set the initial PC == Reset_Handler
+;*                      - Set the vector table entries with the exceptions ISR address
+;*                      - Configure the clock system
+;*                      - Branches to __main in the C library (which eventually
+;*                        calls main()).
+;*                      After Reset the CortexM3 processor is in Thread mode,
+;*                      priority is Privileged, and the Stack is set to Main.
+;* <<< Use Configuration Wizard in Context Menu >>>   
+;*******************************************************************************
+; THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+; WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
+; AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
+; INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
+; CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
+; INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+;*******************************************************************************
+
+; Amount of memory (in bytes) allocated for Stack
+; Tailor this value to your application needs
+; <h> Stack Configuration
+;   <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Stack_Size      EQU     0x00000400
+
+                AREA    STACK, NOINIT, READWRITE, ALIGN=3
+Stack_Mem       SPACE   Stack_Size
+__initial_sp
+
+
+; <h> Heap Configuration
+;   <o>  Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Heap_Size       EQU     0x00000200
+
+                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem        SPACE   Heap_Size
+__heap_limit
+
+                PRESERVE8
+                THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+                AREA    RESET, DATA, READONLY
+                EXPORT  __Vectors
+                EXPORT  __Vectors_End
+                EXPORT  __Vectors_Size
+
+__Vectors       DCD     __initial_sp                    ; Top of Stack
+                DCD     Reset_Handler                   ; Reset Handler
+                DCD     NMI_Handler                     ; NMI Handler
+                DCD     HardFault_Handler               ; Hard Fault Handler
+                DCD     MemManage_Handler               ; MPU Fault Handler
+                DCD     BusFault_Handler                ; Bus Fault Handler
+                DCD     UsageFault_Handler              ; Usage Fault Handler
+                DCD     0                               ; Reserved
+                DCD     0                               ; Reserved
+                DCD     0                               ; Reserved
+                DCD     0                               ; Reserved
+                DCD     SVC_Handler                     ; SVCall Handler
+                DCD     DebugMon_Handler                ; Debug Monitor Handler
+                DCD     0                               ; Reserved
+                DCD     PendSV_Handler                  ; PendSV Handler
+                DCD     SysTick_Handler                 ; SysTick Handler
+
+                ; External Interrupts
+                DCD     WWDG_IRQHandler                 ; Window Watchdog
+                DCD     PVD_IRQHandler                  ; PVD through EXTI Line detect
+                DCD     TAMPER_IRQHandler               ; Tamper
+                DCD     RTC_IRQHandler                  ; RTC
+                DCD     FLASH_IRQHandler                ; Flash
+                DCD     RCC_IRQHandler                  ; RCC
+                DCD     EXTI0_IRQHandler                ; EXTI Line 0
+                DCD     EXTI1_IRQHandler                ; EXTI Line 1
+                DCD     EXTI2_IRQHandler                ; EXTI Line 2
+                DCD     EXTI3_IRQHandler                ; EXTI Line 3
+                DCD     EXTI4_IRQHandler                ; EXTI Line 4
+                DCD     DMA1_Channel1_IRQHandler        ; DMA1 Channel 1
+                DCD     DMA1_Channel2_IRQHandler        ; DMA1 Channel 2
+                DCD     DMA1_Channel3_IRQHandler        ; DMA1 Channel 3
+                DCD     DMA1_Channel4_IRQHandler        ; DMA1 Channel 4
+                DCD     DMA1_Channel5_IRQHandler        ; DMA1 Channel 5
+                DCD     DMA1_Channel6_IRQHandler        ; DMA1 Channel 6
+                DCD     DMA1_Channel7_IRQHandler        ; DMA1 Channel 7
+                DCD     ADC1_IRQHandler                 ; ADC1
+                DCD     0                               ; Reserved
+                DCD     0                               ; Reserved
+                DCD     0                               ; Reserved
+                DCD     0                               ; Reserved
+                DCD     EXTI9_5_IRQHandler              ; EXTI Line 9..5
+                DCD     TIM1_BRK_TIM15_IRQHandler       ; TIM1 Break and TIM15
+                DCD     TIM1_UP_TIM16_IRQHandler        ; TIM1 Update and TIM16
+                DCD     TIM1_TRG_COM_TIM17_IRQHandler   ; TIM1 Trigger and Commutation and TIM17
+                DCD     TIM1_CC_IRQHandler              ; TIM1 Capture Compare
+                DCD     TIM2_IRQHandler                 ; TIM2
+                DCD     TIM3_IRQHandler                 ; TIM3
+                DCD     0                               ; Reserved
+                DCD     I2C1_EV_IRQHandler              ; I2C1 Event
+                DCD     I2C1_ER_IRQHandler              ; I2C1 Error
+                DCD     0                               ; Reserved
+                DCD     0                               ; Reserved
+                DCD     SPI1_IRQHandler                 ; SPI1
+                DCD     0                               ; Reserved
+                DCD     USART1_IRQHandler               ; USART1
+                DCD     USART2_IRQHandler               ; USART2
+                DCD     0                               ; Reserved
+                DCD     EXTI15_10_IRQHandler            ; EXTI Line 15..10
+                DCD     RTCAlarm_IRQHandler             ; RTC Alarm through EXTI Line
+                DCD     CEC_IRQHandler                  ; HDMI-CEC
+                DCD     0                               ; Reserved
+                DCD     0                               ; Reserved
+                DCD     0                               ; Reserved
+                DCD     0                               ; Reserved 
+                DCD     0                               ; Reserved
+                DCD     0                               ; Reserved
+                DCD     0                               ; Reserved
+                DCD     0                               ; Reserved 
+                DCD     0                               ; Reserved
+                DCD     0                               ; Reserved
+                DCD     0                               ; Reserved
+                DCD     TIM6_DAC_IRQHandler             ; TIM6 and DAC underrun
+                DCD     TIM7_IRQHandler                 ; TIM7
+__Vectors_End
+
+__Vectors_Size  EQU  __Vectors_End - __Vectors
+
+                AREA    |.text|, CODE, READONLY
+
+; Reset handler
+Reset_Handler    PROC
+                 EXPORT  Reset_Handler             [WEAK]
+     IMPORT  __main
+     IMPORT  SystemInit
+                 LDR     R0, =SystemInit
+                 BLX     R0
+                 LDR     R0, =__main
+                 BX      R0
+                 ENDP
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler     PROC
+                EXPORT  NMI_Handler                      [WEAK]
+                B       .
+                ENDP
+HardFault_Handler\
+                PROC
+                EXPORT  HardFault_Handler                [WEAK]
+                B       .
+                ENDP
+MemManage_Handler\
+                PROC
+                EXPORT  MemManage_Handler                [WEAK]
+                B       .
+                ENDP
+BusFault_Handler\
+                PROC
+                EXPORT  BusFault_Handler                 [WEAK]
+                B       .
+                ENDP
+UsageFault_Handler\
+                PROC
+                EXPORT  UsageFault_Handler               [WEAK]
+                B       .
+                ENDP
+SVC_Handler     PROC
+                EXPORT  SVC_Handler                      [WEAK]
+                B       .
+                ENDP
+DebugMon_Handler\
+                PROC
+                EXPORT  DebugMon_Handler                 [WEAK]
+                B       .
+                ENDP
+PendSV_Handler  PROC
+                EXPORT  PendSV_Handler                   [WEAK]
+                B       .
+                ENDP
+SysTick_Handler PROC
+                EXPORT  SysTick_Handler                  [WEAK]
+                B       .
+                ENDP
+
+Default_Handler PROC
+
+                EXPORT  WWDG_IRQHandler                  [WEAK]
+                EXPORT  PVD_IRQHandler                   [WEAK]
+                EXPORT  TAMPER_IRQHandler                [WEAK]
+                EXPORT  RTC_IRQHandler                   [WEAK]
+                EXPORT  FLASH_IRQHandler                 [WEAK]
+                EXPORT  RCC_IRQHandler                   [WEAK]
+                EXPORT  EXTI0_IRQHandler                 [WEAK]
+                EXPORT  EXTI1_IRQHandler                 [WEAK]
+                EXPORT  EXTI2_IRQHandler                 [WEAK]
+                EXPORT  EXTI3_IRQHandler                 [WEAK]
+                EXPORT  EXTI4_IRQHandler                 [WEAK]
+                EXPORT  DMA1_Channel1_IRQHandler         [WEAK]
+                EXPORT  DMA1_Channel2_IRQHandler         [WEAK]
+                EXPORT  DMA1_Channel3_IRQHandler         [WEAK]
+                EXPORT  DMA1_Channel4_IRQHandler         [WEAK]
+                EXPORT  DMA1_Channel5_IRQHandler         [WEAK]
+                EXPORT  DMA1_Channel6_IRQHandler         [WEAK]
+                EXPORT  DMA1_Channel7_IRQHandler         [WEAK]
+                EXPORT  ADC1_IRQHandler                  [WEAK]
+                EXPORT  EXTI9_5_IRQHandler               [WEAK]
+                EXPORT  TIM1_BRK_TIM15_IRQHandler        [WEAK]
+                EXPORT  TIM1_UP_TIM16_IRQHandler         [WEAK]
+                EXPORT  TIM1_TRG_COM_TIM17_IRQHandler    [WEAK]
+                EXPORT  TIM1_CC_IRQHandler               [WEAK]
+                EXPORT  TIM2_IRQHandler                  [WEAK]
+                EXPORT  TIM3_IRQHandler                  [WEAK]
+                EXPORT  I2C1_EV_IRQHandler               [WEAK]
+                EXPORT  I2C1_ER_IRQHandler               [WEAK]
+                EXPORT  SPI1_IRQHandler                  [WEAK]
+                EXPORT  USART1_IRQHandler                [WEAK]
+                EXPORT  USART2_IRQHandler                [WEAK]
+                EXPORT  EXTI15_10_IRQHandler             [WEAK]
+                EXPORT  RTCAlarm_IRQHandler              [WEAK]
+                EXPORT  CEC_IRQHandler                   [WEAK]
+                EXPORT  TIM6_DAC_IRQHandler              [WEAK]
+                EXPORT  TIM7_IRQHandler                  [WEAK]
+WWDG_IRQHandler
+PVD_IRQHandler
+TAMPER_IRQHandler
+RTC_IRQHandler
+FLASH_IRQHandler
+RCC_IRQHandler
+EXTI0_IRQHandler
+EXTI1_IRQHandler
+EXTI2_IRQHandler
+EXTI3_IRQHandler
+EXTI4_IRQHandler
+DMA1_Channel1_IRQHandler
+DMA1_Channel2_IRQHandler
+DMA1_Channel3_IRQHandler
+DMA1_Channel4_IRQHandler
+DMA1_Channel5_IRQHandler
+DMA1_Channel6_IRQHandler
+DMA1_Channel7_IRQHandler
+ADC1_IRQHandler
+EXTI9_5_IRQHandler
+TIM1_BRK_TIM15_IRQHandler
+TIM1_UP_TIM16_IRQHandler
+TIM1_TRG_COM_TIM17_IRQHandler
+TIM1_CC_IRQHandler
+TIM2_IRQHandler
+TIM3_IRQHandler
+I2C1_EV_IRQHandler
+I2C1_ER_IRQHandler
+SPI1_IRQHandler
+USART1_IRQHandler
+USART2_IRQHandler
+EXTI15_10_IRQHandler
+RTCAlarm_IRQHandler
+CEC_IRQHandler
+TIM6_DAC_IRQHandler
+TIM7_IRQHandler
+                B       .
+
+                ENDP
+
+                ALIGN
+
+;*******************************************************************************
+; User Stack and Heap initialization
+;*******************************************************************************
+                 IF      :DEF:__MICROLIB           
+                
+                 EXPORT  __initial_sp
+                 EXPORT  __heap_base
+                 EXPORT  __heap_limit
+                
+                 ELSE
+                
+                 IMPORT  __use_two_region_memory
+                 EXPORT  __user_initial_stackheap
+                 
+__user_initial_stackheap
+
+                 LDR     R0, =  Heap_Mem
+                 LDR     R1, =(Stack_Mem + Stack_Size)
+                 LDR     R2, = (Heap_Mem +  Heap_Size)
+                 LDR     R3, = Stack_Mem
+                 BX      LR
+
+                 ALIGN
+
+                 ENDIF
+
+                 END
+
+;******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE*****
diff --git a/STM32_4路称重_Git提交精简工程/src/CMSIS/Startup/startup_stm32f10x_md.s b/STM32_4路称重_Git提交精简工程/src/CMSIS/Startup/startup_stm32f10x_md.s
new file mode 100755
index 0000000..3223fc9
--- /dev/null
+++ b/STM32_4路称重_Git提交精简工程/src/CMSIS/Startup/startup_stm32f10x_md.s
@@ -0,0 +1,307 @@
+;******************** (C) COPYRIGHT 2011 STMicroelectronics ********************
+;* File Name          : startup_stm32f10x_md.s
+;* Author             : MCD Application Team
+;* Version            : V3.5.0
+;* Date               : 11-March-2011
+;* Description        : STM32F10x Medium Density Devices vector table for MDK-ARM 
+;*                      toolchain.  
+;*                      This module performs:
+;*                      - Set the initial SP
+;*                      - Set the initial PC == Reset_Handler
+;*                      - Set the vector table entries with the exceptions ISR address
+;*                      - Configure the clock system
+;*                      - Branches to __main in the C library (which eventually
+;*                        calls main()).
+;*                      After Reset the CortexM3 processor is in Thread mode,
+;*                      priority is Privileged, and the Stack is set to Main.
+;* <<< Use Configuration Wizard in Context Menu >>>   
+;*******************************************************************************
+; THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+; WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
+; AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
+; INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
+; CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
+; INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+;*******************************************************************************
+
+; Amount of memory (in bytes) allocated for Stack
+; Tailor this value to your application needs
+; <h> Stack Configuration
+;   <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Stack_Size      EQU     0x00000400
+
+                AREA    STACK, NOINIT, READWRITE, ALIGN=3
+Stack_Mem       SPACE   Stack_Size
+__initial_sp
+
+
+; <h> Heap Configuration
+;   <o>  Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Heap_Size       EQU     0x00000200
+
+                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem        SPACE   Heap_Size
+__heap_limit
+
+                PRESERVE8
+                THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+                AREA    RESET, DATA, READONLY
+                EXPORT  __Vectors
+                EXPORT  __Vectors_End
+                EXPORT  __Vectors_Size
+
+__Vectors       DCD     __initial_sp               ; Top of Stack
+                DCD     Reset_Handler              ; Reset Handler
+                DCD     NMI_Handler                ; NMI Handler
+                DCD     HardFault_Handler          ; Hard Fault Handler
+                DCD     MemManage_Handler          ; MPU Fault Handler
+                DCD     BusFault_Handler           ; Bus Fault Handler
+                DCD     UsageFault_Handler         ; Usage Fault Handler
+                DCD     0                          ; Reserved
+                DCD     0                          ; Reserved
+                DCD     0                          ; Reserved
+                DCD     0                          ; Reserved
+                DCD     SVC_Handler                ; SVCall Handler
+                DCD     DebugMon_Handler           ; Debug Monitor Handler
+                DCD     0                          ; Reserved
+                DCD     PendSV_Handler             ; PendSV Handler
+                DCD     SysTick_Handler            ; SysTick Handler
+
+                ; External Interrupts
+                DCD     WWDG_IRQHandler            ; Window Watchdog
+                DCD     PVD_IRQHandler             ; PVD through EXTI Line detect
+                DCD     TAMPER_IRQHandler          ; Tamper
+                DCD     RTC_IRQHandler             ; RTC
+                DCD     FLASH_IRQHandler           ; Flash
+                DCD     RCC_IRQHandler             ; RCC
+                DCD     EXTI0_IRQHandler           ; EXTI Line 0
+                DCD     EXTI1_IRQHandler           ; EXTI Line 1
+                DCD     EXTI2_IRQHandler           ; EXTI Line 2
+                DCD     EXTI3_IRQHandler           ; EXTI Line 3
+                DCD     EXTI4_IRQHandler           ; EXTI Line 4
+                DCD     DMA1_Channel1_IRQHandler   ; DMA1 Channel 1
+                DCD     DMA1_Channel2_IRQHandler   ; DMA1 Channel 2
+                DCD     DMA1_Channel3_IRQHandler   ; DMA1 Channel 3
+                DCD     DMA1_Channel4_IRQHandler   ; DMA1 Channel 4
+                DCD     DMA1_Channel5_IRQHandler   ; DMA1 Channel 5
+                DCD     DMA1_Channel6_IRQHandler   ; DMA1 Channel 6
+                DCD     DMA1_Channel7_IRQHandler   ; DMA1 Channel 7
+                DCD     ADC1_2_IRQHandler          ; ADC1_2
+                DCD     USB_HP_CAN1_TX_IRQHandler  ; USB High Priority or CAN1 TX
+                DCD     USB_LP_CAN1_RX0_IRQHandler ; USB Low  Priority or CAN1 RX0
+                DCD     CAN1_RX1_IRQHandler        ; CAN1 RX1
+                DCD     CAN1_SCE_IRQHandler        ; CAN1 SCE
+                DCD     EXTI9_5_IRQHandler         ; EXTI Line 9..5
+                DCD     TIM1_BRK_IRQHandler        ; TIM1 Break
+                DCD     TIM1_UP_IRQHandler         ; TIM1 Update
+                DCD     TIM1_TRG_COM_IRQHandler    ; TIM1 Trigger and Commutation
+                DCD     TIM1_CC_IRQHandler         ; TIM1 Capture Compare
+                DCD     TIM2_IRQHandler            ; TIM2
+                DCD     TIM3_IRQHandler            ; TIM3
+                DCD     TIM4_IRQHandler            ; TIM4
+                DCD     I2C1_EV_IRQHandler         ; I2C1 Event
+                DCD     I2C1_ER_IRQHandler         ; I2C1 Error
+                DCD     I2C2_EV_IRQHandler         ; I2C2 Event
+                DCD     I2C2_ER_IRQHandler         ; I2C2 Error
+                DCD     SPI1_IRQHandler            ; SPI1
+                DCD     SPI2_IRQHandler            ; SPI2
+                DCD     USART1_IRQHandler          ; USART1
+                DCD     USART2_IRQHandler          ; USART2
+                DCD     USART3_IRQHandler          ; USART3
+                DCD     EXTI15_10_IRQHandler       ; EXTI Line 15..10
+                DCD     RTCAlarm_IRQHandler        ; RTC Alarm through EXTI Line
+                DCD     USBWakeUp_IRQHandler       ; USB Wakeup from suspend
+__Vectors_End
+
+__Vectors_Size  EQU  __Vectors_End - __Vectors
+
+                AREA    |.text|, CODE, READONLY
+
+; Reset handler
+Reset_Handler    PROC
+                 EXPORT  Reset_Handler             [WEAK]
+     IMPORT  __main
+     IMPORT  SystemInit
+                 LDR     R0, =SystemInit
+                 BLX     R0
+                 LDR     R0, =__main
+                 BX      R0
+                 ENDP
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler     PROC
+                EXPORT  NMI_Handler                [WEAK]
+                B       .
+                ENDP
+HardFault_Handler\
+                PROC
+                EXPORT  HardFault_Handler          [WEAK]
+                B       .
+                ENDP
+MemManage_Handler\
+                PROC
+                EXPORT  MemManage_Handler          [WEAK]
+                B       .
+                ENDP
+BusFault_Handler\
+                PROC
+                EXPORT  BusFault_Handler           [WEAK]
+                B       .
+                ENDP
+UsageFault_Handler\
+                PROC
+                EXPORT  UsageFault_Handler         [WEAK]
+                B       .
+                ENDP
+SVC_Handler     PROC
+                EXPORT  SVC_Handler                [WEAK]
+                B       .
+                ENDP
+DebugMon_Handler\
+                PROC
+                EXPORT  DebugMon_Handler           [WEAK]
+                B       .
+                ENDP
+PendSV_Handler  PROC
+                EXPORT  PendSV_Handler             [WEAK]
+                B       .
+                ENDP
+SysTick_Handler PROC
+                EXPORT  SysTick_Handler            [WEAK]
+                B       .
+                ENDP
+
+Default_Handler PROC
+
+                EXPORT  WWDG_IRQHandler            [WEAK]
+                EXPORT  PVD_IRQHandler             [WEAK]
+                EXPORT  TAMPER_IRQHandler          [WEAK]
+                EXPORT  RTC_IRQHandler             [WEAK]
+                EXPORT  FLASH_IRQHandler           [WEAK]
+                EXPORT  RCC_IRQHandler             [WEAK]
+                EXPORT  EXTI0_IRQHandler           [WEAK]
+                EXPORT  EXTI1_IRQHandler           [WEAK]
+                EXPORT  EXTI2_IRQHandler           [WEAK]
+                EXPORT  EXTI3_IRQHandler           [WEAK]
+                EXPORT  EXTI4_IRQHandler           [WEAK]
+                EXPORT  DMA1_Channel1_IRQHandler   [WEAK]
+                EXPORT  DMA1_Channel2_IRQHandler   [WEAK]
+                EXPORT  DMA1_Channel3_IRQHandler   [WEAK]
+                EXPORT  DMA1_Channel4_IRQHandler   [WEAK]
+                EXPORT  DMA1_Channel5_IRQHandler   [WEAK]
+                EXPORT  DMA1_Channel6_IRQHandler   [WEAK]
+                EXPORT  DMA1_Channel7_IRQHandler   [WEAK]
+                EXPORT  ADC1_2_IRQHandler          [WEAK]
+                EXPORT  USB_HP_CAN1_TX_IRQHandler  [WEAK]
+                EXPORT  USB_LP_CAN1_RX0_IRQHandler [WEAK]
+                EXPORT  CAN1_RX1_IRQHandler        [WEAK]
+                EXPORT  CAN1_SCE_IRQHandler        [WEAK]
+                EXPORT  EXTI9_5_IRQHandler         [WEAK]
+                EXPORT  TIM1_BRK_IRQHandler        [WEAK]
+                EXPORT  TIM1_UP_IRQHandler         [WEAK]
+                EXPORT  TIM1_TRG_COM_IRQHandler    [WEAK]
+                EXPORT  TIM1_CC_IRQHandler         [WEAK]
+                EXPORT  TIM2_IRQHandler            [WEAK]
+                EXPORT  TIM3_IRQHandler            [WEAK]
+                EXPORT  TIM4_IRQHandler            [WEAK]
+                EXPORT  I2C1_EV_IRQHandler         [WEAK]
+                EXPORT  I2C1_ER_IRQHandler         [WEAK]
+                EXPORT  I2C2_EV_IRQHandler         [WEAK]
+                EXPORT  I2C2_ER_IRQHandler         [WEAK]
+                EXPORT  SPI1_IRQHandler            [WEAK]
+                EXPORT  SPI2_IRQHandler            [WEAK]
+                EXPORT  USART1_IRQHandler          [WEAK]
+                EXPORT  USART2_IRQHandler          [WEAK]
+                EXPORT  USART3_IRQHandler          [WEAK]
+                EXPORT  EXTI15_10_IRQHandler       [WEAK]
+                EXPORT  RTCAlarm_IRQHandler        [WEAK]
+                EXPORT  USBWakeUp_IRQHandler       [WEAK]
+
+WWDG_IRQHandler
+PVD_IRQHandler
+TAMPER_IRQHandler
+RTC_IRQHandler
+FLASH_IRQHandler
+RCC_IRQHandler
+EXTI0_IRQHandler
+EXTI1_IRQHandler
+EXTI2_IRQHandler
+EXTI3_IRQHandler
+EXTI4_IRQHandler
+DMA1_Channel1_IRQHandler
+DMA1_Channel2_IRQHandler
+DMA1_Channel3_IRQHandler
+DMA1_Channel4_IRQHandler
+DMA1_Channel5_IRQHandler
+DMA1_Channel6_IRQHandler
+DMA1_Channel7_IRQHandler
+ADC1_2_IRQHandler
+USB_HP_CAN1_TX_IRQHandler
+USB_LP_CAN1_RX0_IRQHandler
+CAN1_RX1_IRQHandler
+CAN1_SCE_IRQHandler
+EXTI9_5_IRQHandler
+TIM1_BRK_IRQHandler
+TIM1_UP_IRQHandler
+TIM1_TRG_COM_IRQHandler
+TIM1_CC_IRQHandler
+TIM2_IRQHandler
+TIM3_IRQHandler
+TIM4_IRQHandler
+I2C1_EV_IRQHandler
+I2C1_ER_IRQHandler
+I2C2_EV_IRQHandler
+I2C2_ER_IRQHandler
+SPI1_IRQHandler
+SPI2_IRQHandler
+USART1_IRQHandler
+USART2_IRQHandler
+USART3_IRQHandler
+EXTI15_10_IRQHandler
+RTCAlarm_IRQHandler
+USBWakeUp_IRQHandler
+
+                B       .
+
+                ENDP
+
+                ALIGN
+
+;*******************************************************************************
+; User Stack and Heap initialization
+;*******************************************************************************
+                 IF      :DEF:__MICROLIB           
+                
+                 EXPORT  __initial_sp
+                 EXPORT  __heap_base
+                 EXPORT  __heap_limit
+                
+                 ELSE
+                
+                 IMPORT  __use_two_region_memory
+                 EXPORT  __user_initial_stackheap
+                 
+__user_initial_stackheap
+
+                 LDR     R0, =  Heap_Mem
+                 LDR     R1, =(Stack_Mem + Stack_Size)
+                 LDR     R2, = (Heap_Mem +  Heap_Size)
+                 LDR     R3, = Stack_Mem
+                 BX      LR
+
+                 ALIGN
+
+                 ENDIF
+
+                 END
+
+;******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE*****
diff --git a/STM32_4路称重_Git提交精简工程/src/CMSIS/Startup/startup_stm32f10x_md_vl.s b/STM32_4路称重_Git提交精简工程/src/CMSIS/Startup/startup_stm32f10x_md_vl.s
new file mode 100755
index 0000000..d3b8aa6
--- /dev/null
+++ b/STM32_4路称重_Git提交精简工程/src/CMSIS/Startup/startup_stm32f10x_md_vl.s
@@ -0,0 +1,315 @@
+;******************** (C) COPYRIGHT 2011 STMicroelectronics ********************
+;* File Name          : startup_stm32f10x_md_vl.s
+;* Author             : MCD Application Team
+;* Version            : V3.5.0
+;* Date               : 11-March-2011
+;* Description        : STM32F10x Medium Density Value Line Devices vector table  
+;*                      for MDK-ARM toolchain.  
+;*                      This module performs:
+;*                      - Set the initial SP
+;*                      - Set the initial PC == Reset_Handler
+;*                      - Set the vector table entries with the exceptions ISR address
+;*                      - Configure the clock system
+;*                      - Branches to __main in the C library (which eventually
+;*                        calls main()).
+;*                      After Reset the CortexM3 processor is in Thread mode,
+;*                      priority is Privileged, and the Stack is set to Main.
+;* <<< Use Configuration Wizard in Context Menu >>>   
+;*******************************************************************************
+; THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+; WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
+; AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
+; INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
+; CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
+; INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+;*******************************************************************************
+
+; Amount of memory (in bytes) allocated for Stack
+; Tailor this value to your application needs
+; <h> Stack Configuration
+;   <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Stack_Size      EQU     0x00000400
+
+                AREA    STACK, NOINIT, READWRITE, ALIGN=3
+Stack_Mem       SPACE   Stack_Size
+__initial_sp
+
+
+; <h> Heap Configuration
+;   <o>  Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Heap_Size       EQU     0x00000200
+
+                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem        SPACE   Heap_Size
+__heap_limit
+
+                PRESERVE8
+                THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+                AREA    RESET, DATA, READONLY
+                EXPORT  __Vectors
+                EXPORT  __Vectors_End
+                EXPORT  __Vectors_Size
+
+__Vectors       DCD     __initial_sp                    ; Top of Stack
+                DCD     Reset_Handler                   ; Reset Handler
+                DCD     NMI_Handler                     ; NMI Handler
+                DCD     HardFault_Handler               ; Hard Fault Handler
+                DCD     MemManage_Handler               ; MPU Fault Handler
+                DCD     BusFault_Handler                ; Bus Fault Handler
+                DCD     UsageFault_Handler              ; Usage Fault Handler
+                DCD     0                               ; Reserved
+                DCD     0                               ; Reserved
+                DCD     0                               ; Reserved
+                DCD     0                               ; Reserved
+                DCD     SVC_Handler                     ; SVCall Handler
+                DCD     DebugMon_Handler                ; Debug Monitor Handler
+                DCD     0                               ; Reserved
+                DCD     PendSV_Handler                  ; PendSV Handler
+                DCD     SysTick_Handler                 ; SysTick Handler
+
+                ; External Interrupts
+                DCD     WWDG_IRQHandler                 ; Window Watchdog
+                DCD     PVD_IRQHandler                  ; PVD through EXTI Line detect
+                DCD     TAMPER_IRQHandler               ; Tamper
+                DCD     RTC_IRQHandler                  ; RTC
+                DCD     FLASH_IRQHandler                ; Flash
+                DCD     RCC_IRQHandler                  ; RCC
+                DCD     EXTI0_IRQHandler                ; EXTI Line 0
+                DCD     EXTI1_IRQHandler                ; EXTI Line 1
+                DCD     EXTI2_IRQHandler                ; EXTI Line 2
+                DCD     EXTI3_IRQHandler                ; EXTI Line 3
+                DCD     EXTI4_IRQHandler                ; EXTI Line 4
+                DCD     DMA1_Channel1_IRQHandler        ; DMA1 Channel 1
+                DCD     DMA1_Channel2_IRQHandler        ; DMA1 Channel 2
+                DCD     DMA1_Channel3_IRQHandler        ; DMA1 Channel 3
+                DCD     DMA1_Channel4_IRQHandler        ; DMA1 Channel 4
+                DCD     DMA1_Channel5_IRQHandler        ; DMA1 Channel 5
+                DCD     DMA1_Channel6_IRQHandler        ; DMA1 Channel 6
+                DCD     DMA1_Channel7_IRQHandler        ; DMA1 Channel 7
+                DCD     ADC1_IRQHandler                 ; ADC1
+                DCD     0                               ; Reserved
+                DCD     0                               ; Reserved
+                DCD     0                               ; Reserved
+                DCD     0                               ; Reserved
+                DCD     EXTI9_5_IRQHandler              ; EXTI Line 9..5
+                DCD     TIM1_BRK_TIM15_IRQHandler       ; TIM1 Break and TIM15
+                DCD     TIM1_UP_TIM16_IRQHandler        ; TIM1 Update and TIM16
+                DCD     TIM1_TRG_COM_TIM17_IRQHandler   ; TIM1 Trigger and Commutation and TIM17
+                DCD     TIM1_CC_IRQHandler              ; TIM1 Capture Compare
+                DCD     TIM2_IRQHandler                 ; TIM2
+                DCD     TIM3_IRQHandler                 ; TIM3
+                DCD     TIM4_IRQHandler                 ; TIM4
+                DCD     I2C1_EV_IRQHandler              ; I2C1 Event
+                DCD     I2C1_ER_IRQHandler              ; I2C1 Error
+                DCD     I2C2_EV_IRQHandler              ; I2C2 Event
+                DCD     I2C2_ER_IRQHandler              ; I2C2 Error
+                DCD     SPI1_IRQHandler                 ; SPI1
+                DCD     SPI2_IRQHandler                 ; SPI2
+                DCD     USART1_IRQHandler               ; USART1
+                DCD     USART2_IRQHandler               ; USART2
+                DCD     USART3_IRQHandler               ; USART3
+                DCD     EXTI15_10_IRQHandler            ; EXTI Line 15..10
+                DCD     RTCAlarm_IRQHandler             ; RTC Alarm through EXTI Line
+                DCD     CEC_IRQHandler                  ; HDMI-CEC
+                DCD     0                               ; Reserved
+                DCD     0                               ; Reserved
+                DCD     0                               ; Reserved
+                DCD     0                               ; Reserved 
+                DCD     0                               ; Reserved
+                DCD     0                               ; Reserved
+                DCD     0                               ; Reserved
+                DCD     0                               ; Reserved 
+                DCD     0                               ; Reserved
+                DCD     0                               ; Reserved
+                DCD     0                               ; Reserved
+                DCD     TIM6_DAC_IRQHandler             ; TIM6 and DAC underrun
+                DCD     TIM7_IRQHandler                 ; TIM7
+__Vectors_End
+
+__Vectors_Size  EQU  __Vectors_End - __Vectors
+
+                AREA    |.text|, CODE, READONLY
+
+; Reset handler
+Reset_Handler    PROC
+                 EXPORT  Reset_Handler             [WEAK]
+     IMPORT  __main
+     IMPORT  SystemInit
+                 LDR     R0, =SystemInit
+                 BLX     R0
+                 LDR     R0, =__main
+                 BX      R0
+                 ENDP
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler     PROC
+                EXPORT  NMI_Handler                      [WEAK]
+                B       .
+                ENDP
+HardFault_Handler\
+                PROC
+                EXPORT  HardFault_Handler                [WEAK]
+                B       .
+                ENDP
+MemManage_Handler\
+                PROC
+                EXPORT  MemManage_Handler                [WEAK]
+                B       .
+                ENDP
+BusFault_Handler\
+                PROC
+                EXPORT  BusFault_Handler                 [WEAK]
+                B       .
+                ENDP
+UsageFault_Handler\
+                PROC
+                EXPORT  UsageFault_Handler               [WEAK]
+                B       .
+                ENDP
+SVC_Handler     PROC
+                EXPORT  SVC_Handler                      [WEAK]
+                B       .
+                ENDP
+DebugMon_Handler\
+                PROC
+                EXPORT  DebugMon_Handler                 [WEAK]
+                B       .
+                ENDP
+PendSV_Handler  PROC
+                EXPORT  PendSV_Handler                   [WEAK]
+                B       .
+                ENDP
+SysTick_Handler PROC
+                EXPORT  SysTick_Handler                  [WEAK]
+                B       .
+                ENDP
+
+Default_Handler PROC
+
+                EXPORT  WWDG_IRQHandler                  [WEAK]
+                EXPORT  PVD_IRQHandler                   [WEAK]
+                EXPORT  TAMPER_IRQHandler                [WEAK]
+                EXPORT  RTC_IRQHandler                   [WEAK]
+                EXPORT  FLASH_IRQHandler                 [WEAK]
+                EXPORT  RCC_IRQHandler                   [WEAK]
+                EXPORT  EXTI0_IRQHandler                 [WEAK]
+                EXPORT  EXTI1_IRQHandler                 [WEAK]
+                EXPORT  EXTI2_IRQHandler                 [WEAK]
+                EXPORT  EXTI3_IRQHandler                 [WEAK]
+                EXPORT  EXTI4_IRQHandler                 [WEAK]
+                EXPORT  DMA1_Channel1_IRQHandler         [WEAK]
+                EXPORT  DMA1_Channel2_IRQHandler         [WEAK]
+                EXPORT  DMA1_Channel3_IRQHandler         [WEAK]
+                EXPORT  DMA1_Channel4_IRQHandler         [WEAK]
+                EXPORT  DMA1_Channel5_IRQHandler         [WEAK]
+                EXPORT  DMA1_Channel6_IRQHandler         [WEAK]
+                EXPORT  DMA1_Channel7_IRQHandler         [WEAK]
+                EXPORT  ADC1_IRQHandler                  [WEAK]
+                EXPORT  EXTI9_5_IRQHandler               [WEAK]
+                EXPORT  TIM1_BRK_TIM15_IRQHandler        [WEAK]
+                EXPORT  TIM1_UP_TIM16_IRQHandler         [WEAK]
+                EXPORT  TIM1_TRG_COM_TIM17_IRQHandler    [WEAK]
+                EXPORT  TIM1_CC_IRQHandler               [WEAK]
+                EXPORT  TIM2_IRQHandler                  [WEAK]
+                EXPORT  TIM3_IRQHandler                  [WEAK]
+                EXPORT  TIM4_IRQHandler                  [WEAK]
+                EXPORT  I2C1_EV_IRQHandler               [WEAK]
+                EXPORT  I2C1_ER_IRQHandler               [WEAK]
+                EXPORT  I2C2_EV_IRQHandler               [WEAK]
+                EXPORT  I2C2_ER_IRQHandler               [WEAK]
+                EXPORT  SPI1_IRQHandler                  [WEAK]
+                EXPORT  SPI2_IRQHandler                  [WEAK]
+                EXPORT  USART1_IRQHandler                [WEAK]
+                EXPORT  USART2_IRQHandler                [WEAK]
+                EXPORT  USART3_IRQHandler                [WEAK]
+                EXPORT  EXTI15_10_IRQHandler             [WEAK]
+                EXPORT  RTCAlarm_IRQHandler              [WEAK]
+                EXPORT  CEC_IRQHandler                   [WEAK]
+                EXPORT  TIM6_DAC_IRQHandler              [WEAK]
+                EXPORT  TIM7_IRQHandler                  [WEAK]
+
+WWDG_IRQHandler
+PVD_IRQHandler
+TAMPER_IRQHandler
+RTC_IRQHandler
+FLASH_IRQHandler
+RCC_IRQHandler
+EXTI0_IRQHandler
+EXTI1_IRQHandler
+EXTI2_IRQHandler
+EXTI3_IRQHandler
+EXTI4_IRQHandler
+DMA1_Channel1_IRQHandler
+DMA1_Channel2_IRQHandler
+DMA1_Channel3_IRQHandler
+DMA1_Channel4_IRQHandler
+DMA1_Channel5_IRQHandler
+DMA1_Channel6_IRQHandler
+DMA1_Channel7_IRQHandler
+ADC1_IRQHandler
+EXTI9_5_IRQHandler
+TIM1_BRK_TIM15_IRQHandler
+TIM1_UP_TIM16_IRQHandler
+TIM1_TRG_COM_TIM17_IRQHandler
+TIM1_CC_IRQHandler
+TIM2_IRQHandler
+TIM3_IRQHandler
+TIM4_IRQHandler
+I2C1_EV_IRQHandler
+I2C1_ER_IRQHandler
+I2C2_EV_IRQHandler
+I2C2_ER_IRQHandler
+SPI1_IRQHandler
+SPI2_IRQHandler
+USART1_IRQHandler
+USART2_IRQHandler
+USART3_IRQHandler
+EXTI15_10_IRQHandler
+RTCAlarm_IRQHandler
+CEC_IRQHandler
+TIM6_DAC_IRQHandler
+TIM7_IRQHandler
+                B       .
+
+                ENDP
+
+                ALIGN
+
+;*******************************************************************************
+; User Stack and Heap initialization
+;*******************************************************************************
+                 IF      :DEF:__MICROLIB           
+                
+                 EXPORT  __initial_sp
+                 EXPORT  __heap_base
+                 EXPORT  __heap_limit
+                
+                 ELSE
+                
+                 IMPORT  __use_two_region_memory
+                 EXPORT  __user_initial_stackheap
+                 
+__user_initial_stackheap
+
+                 LDR     R0, =  Heap_Mem
+                 LDR     R1, =(Stack_Mem + Stack_Size)
+                 LDR     R2, = (Heap_Mem +  Heap_Size)
+                 LDR     R3, = Stack_Mem
+                 BX      LR
+
+                 ALIGN
+
+                 ENDIF
+
+                 END
+
+;******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE*****
diff --git a/STM32_4路称重_Git提交精简工程/src/CMSIS/Startup/startup_stm32f10x_xl.s b/STM32_4路称重_Git提交精简工程/src/CMSIS/Startup/startup_stm32f10x_xl.s
new file mode 100755
index 0000000..7970052
--- /dev/null
+++ b/STM32_4路称重_Git提交精简工程/src/CMSIS/Startup/startup_stm32f10x_xl.s
@@ -0,0 +1,358 @@
+;******************** (C) COPYRIGHT 2011 STMicroelectronics ********************
+;* File Name          : startup_stm32f10x_xl.s
+;* Author             : MCD Application Team
+;* Version            : V3.5.0
+;* Date               : 11-March-2011
+;* Description        : STM32F10x XL-Density Devices vector table for MDK-ARM 
+;*                      toolchain. 
+;*                      This module performs:
+;*                      - Set the initial SP
+;*                      - Set the initial PC == Reset_Handler
+;*                      - Set the vector table entries with the exceptions ISR address
+;*                      - Configure the clock system and also configure the external 
+;*                        SRAM mounted on STM3210E-EVAL board to be used as data 
+;*                        memory (optional, to be enabled by user)
+;*                      - Branches to __main in the C library (which eventually
+;*                        calls main()).
+;*                      After Reset the CortexM3 processor is in Thread mode,
+;*                      priority is Privileged, and the Stack is set to Main.
+;* <<< Use Configuration Wizard in Context Menu >>>   
+;*******************************************************************************
+; THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+; WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
+; AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
+; INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
+; CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
+; INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+;*******************************************************************************
+
+; Amount of memory (in bytes) allocated for Stack
+; Tailor this value to your application needs
+; <h> Stack Configuration
+;   <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Stack_Size      EQU     0x00000400
+
+                AREA    STACK, NOINIT, READWRITE, ALIGN=3
+Stack_Mem       SPACE   Stack_Size
+__initial_sp
+                                                  
+; <h> Heap Configuration
+;   <o>  Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Heap_Size       EQU     0x00000200
+
+                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem        SPACE   Heap_Size
+__heap_limit
+
+                PRESERVE8
+                THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+                AREA    RESET, DATA, READONLY
+                EXPORT  __Vectors
+                EXPORT  __Vectors_End
+                EXPORT  __Vectors_Size
+
+__Vectors       DCD     __initial_sp               ; Top of Stack
+                DCD     Reset_Handler              ; Reset Handler
+                DCD     NMI_Handler                ; NMI Handler
+                DCD     HardFault_Handler          ; Hard Fault Handler
+                DCD     MemManage_Handler          ; MPU Fault Handler
+                DCD     BusFault_Handler           ; Bus Fault Handler
+                DCD     UsageFault_Handler         ; Usage Fault Handler
+                DCD     0                          ; Reserved
+                DCD     0                          ; Reserved
+                DCD     0                          ; Reserved
+                DCD     0                          ; Reserved
+                DCD     SVC_Handler                ; SVCall Handler
+                DCD     DebugMon_Handler           ; Debug Monitor Handler
+                DCD     0                          ; Reserved
+                DCD     PendSV_Handler             ; PendSV Handler
+                DCD     SysTick_Handler            ; SysTick Handler
+
+                ; External Interrupts
+                DCD     WWDG_IRQHandler               ; Window Watchdog
+                DCD     PVD_IRQHandler                ; PVD through EXTI Line detect
+                DCD     TAMPER_IRQHandler             ; Tamper
+                DCD     RTC_IRQHandler                ; RTC
+                DCD     FLASH_IRQHandler              ; Flash
+                DCD     RCC_IRQHandler                ; RCC
+                DCD     EXTI0_IRQHandler              ; EXTI Line 0
+                DCD     EXTI1_IRQHandler              ; EXTI Line 1
+                DCD     EXTI2_IRQHandler              ; EXTI Line 2
+                DCD     EXTI3_IRQHandler              ; EXTI Line 3
+                DCD     EXTI4_IRQHandler              ; EXTI Line 4
+                DCD     DMA1_Channel1_IRQHandler      ; DMA1 Channel 1
+                DCD     DMA1_Channel2_IRQHandler      ; DMA1 Channel 2
+                DCD     DMA1_Channel3_IRQHandler      ; DMA1 Channel 3
+                DCD     DMA1_Channel4_IRQHandler      ; DMA1 Channel 4
+                DCD     DMA1_Channel5_IRQHandler      ; DMA1 Channel 5
+                DCD     DMA1_Channel6_IRQHandler      ; DMA1 Channel 6
+                DCD     DMA1_Channel7_IRQHandler      ; DMA1 Channel 7
+                DCD     ADC1_2_IRQHandler             ; ADC1 & ADC2
+                DCD     USB_HP_CAN1_TX_IRQHandler     ; USB High Priority or CAN1 TX
+                DCD     USB_LP_CAN1_RX0_IRQHandler    ; USB Low  Priority or CAN1 RX0
+                DCD     CAN1_RX1_IRQHandler           ; CAN1 RX1
+                DCD     CAN1_SCE_IRQHandler           ; CAN1 SCE
+                DCD     EXTI9_5_IRQHandler            ; EXTI Line 9..5
+                DCD     TIM1_BRK_TIM9_IRQHandler      ; TIM1 Break and TIM9
+                DCD     TIM1_UP_TIM10_IRQHandler      ; TIM1 Update and TIM10
+                DCD     TIM1_TRG_COM_TIM11_IRQHandler ; TIM1 Trigger and Commutation and TIM11
+                DCD     TIM1_CC_IRQHandler            ; TIM1 Capture Compare
+                DCD     TIM2_IRQHandler               ; TIM2
+                DCD     TIM3_IRQHandler               ; TIM3
+                DCD     TIM4_IRQHandler               ; TIM4
+                DCD     I2C1_EV_IRQHandler            ; I2C1 Event
+                DCD     I2C1_ER_IRQHandler            ; I2C1 Error
+                DCD     I2C2_EV_IRQHandler            ; I2C2 Event
+                DCD     I2C2_ER_IRQHandler            ; I2C2 Error
+                DCD     SPI1_IRQHandler               ; SPI1
+                DCD     SPI2_IRQHandler               ; SPI2
+                DCD     USART1_IRQHandler             ; USART1
+                DCD     USART2_IRQHandler             ; USART2
+                DCD     USART3_IRQHandler             ; USART3
+                DCD     EXTI15_10_IRQHandler          ; EXTI Line 15..10
+                DCD     RTCAlarm_IRQHandler           ; RTC Alarm through EXTI Line
+                DCD     USBWakeUp_IRQHandler          ; USB Wakeup from suspend
+                DCD     TIM8_BRK_TIM12_IRQHandler     ; TIM8 Break and TIM12
+                DCD     TIM8_UP_TIM13_IRQHandler      ; TIM8 Update and TIM13
+                DCD     TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation and TIM14
+                DCD     TIM8_CC_IRQHandler            ; TIM8 Capture Compare
+                DCD     ADC3_IRQHandler               ; ADC3
+                DCD     FSMC_IRQHandler               ; FSMC
+                DCD     SDIO_IRQHandler               ; SDIO
+                DCD     TIM5_IRQHandler               ; TIM5
+                DCD     SPI3_IRQHandler               ; SPI3
+                DCD     UART4_IRQHandler              ; UART4
+                DCD     UART5_IRQHandler              ; UART5
+                DCD     TIM6_IRQHandler               ; TIM6
+                DCD     TIM7_IRQHandler               ; TIM7
+                DCD     DMA2_Channel1_IRQHandler      ; DMA2 Channel1
+                DCD     DMA2_Channel2_IRQHandler      ; DMA2 Channel2
+                DCD     DMA2_Channel3_IRQHandler      ; DMA2 Channel3
+                DCD     DMA2_Channel4_5_IRQHandler    ; DMA2 Channel4 & Channel5
+__Vectors_End
+
+__Vectors_Size  EQU  __Vectors_End - __Vectors
+
+                AREA    |.text|, CODE, READONLY
+                
+; Reset handler
+Reset_Handler   PROC
+                EXPORT  Reset_Handler             [WEAK]
+                IMPORT  __main
+                IMPORT  SystemInit
+                LDR     R0, =SystemInit
+                BLX     R0               
+                LDR     R0, =__main
+                BX      R0
+                ENDP
+                
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler     PROC
+                EXPORT  NMI_Handler                [WEAK]
+                B       .
+                ENDP
+HardFault_Handler\
+                PROC
+                EXPORT  HardFault_Handler          [WEAK]
+                B       .
+                ENDP
+MemManage_Handler\
+                PROC
+                EXPORT  MemManage_Handler          [WEAK]
+                B       .
+                ENDP
+BusFault_Handler\
+                PROC
+                EXPORT  BusFault_Handler           [WEAK]
+                B       .
+                ENDP
+UsageFault_Handler\
+                PROC
+                EXPORT  UsageFault_Handler         [WEAK]
+                B       .
+                ENDP
+SVC_Handler     PROC
+                EXPORT  SVC_Handler                [WEAK]
+                B       .
+                ENDP
+DebugMon_Handler\
+                PROC
+                EXPORT  DebugMon_Handler           [WEAK]
+                B       .
+                ENDP
+PendSV_Handler  PROC
+                EXPORT  PendSV_Handler             [WEAK]
+                B       .
+                ENDP
+SysTick_Handler PROC
+                EXPORT  SysTick_Handler            [WEAK]
+                B       .
+                ENDP
+
+Default_Handler PROC
+
+                EXPORT  WWDG_IRQHandler               [WEAK]
+                EXPORT  PVD_IRQHandler                [WEAK]
+                EXPORT  TAMPER_IRQHandler             [WEAK]
+                EXPORT  RTC_IRQHandler                [WEAK]
+                EXPORT  FLASH_IRQHandler              [WEAK]
+                EXPORT  RCC_IRQHandler                [WEAK]
+                EXPORT  EXTI0_IRQHandler              [WEAK]
+                EXPORT  EXTI1_IRQHandler              [WEAK]
+                EXPORT  EXTI2_IRQHandler              [WEAK]
+                EXPORT  EXTI3_IRQHandler              [WEAK]
+                EXPORT  EXTI4_IRQHandler              [WEAK]
+                EXPORT  DMA1_Channel1_IRQHandler      [WEAK]
+                EXPORT  DMA1_Channel2_IRQHandler      [WEAK]
+                EXPORT  DMA1_Channel3_IRQHandler      [WEAK]
+                EXPORT  DMA1_Channel4_IRQHandler      [WEAK]
+                EXPORT  DMA1_Channel5_IRQHandler      [WEAK]
+                EXPORT  DMA1_Channel6_IRQHandler      [WEAK]
+                EXPORT  DMA1_Channel7_IRQHandler      [WEAK]
+                EXPORT  ADC1_2_IRQHandler             [WEAK]
+                EXPORT  USB_HP_CAN1_TX_IRQHandler     [WEAK]
+                EXPORT  USB_LP_CAN1_RX0_IRQHandler    [WEAK]
+                EXPORT  CAN1_RX1_IRQHandler           [WEAK]
+                EXPORT  CAN1_SCE_IRQHandler           [WEAK]
+                EXPORT  EXTI9_5_IRQHandler            [WEAK]
+                EXPORT  TIM1_BRK_TIM9_IRQHandler      [WEAK]
+                EXPORT  TIM1_UP_TIM10_IRQHandler      [WEAK]
+                EXPORT  TIM1_TRG_COM_TIM11_IRQHandler [WEAK]
+                EXPORT  TIM1_CC_IRQHandler            [WEAK]
+                EXPORT  TIM2_IRQHandler               [WEAK]
+                EXPORT  TIM3_IRQHandler               [WEAK]
+                EXPORT  TIM4_IRQHandler               [WEAK]
+                EXPORT  I2C1_EV_IRQHandler            [WEAK]
+                EXPORT  I2C1_ER_IRQHandler            [WEAK]
+                EXPORT  I2C2_EV_IRQHandler            [WEAK]
+                EXPORT  I2C2_ER_IRQHandler            [WEAK]
+                EXPORT  SPI1_IRQHandler               [WEAK]
+                EXPORT  SPI2_IRQHandler               [WEAK]
+                EXPORT  USART1_IRQHandler             [WEAK]
+                EXPORT  USART2_IRQHandler             [WEAK]
+                EXPORT  USART3_IRQHandler             [WEAK]
+                EXPORT  EXTI15_10_IRQHandler          [WEAK]
+                EXPORT  RTCAlarm_IRQHandler           [WEAK]
+                EXPORT  USBWakeUp_IRQHandler          [WEAK]
+                EXPORT  TIM8_BRK_TIM12_IRQHandler     [WEAK]
+                EXPORT  TIM8_UP_TIM13_IRQHandler      [WEAK]
+                EXPORT  TIM8_TRG_COM_TIM14_IRQHandler [WEAK]
+                EXPORT  TIM8_CC_IRQHandler            [WEAK]
+                EXPORT  ADC3_IRQHandler               [WEAK]
+                EXPORT  FSMC_IRQHandler               [WEAK]
+                EXPORT  SDIO_IRQHandler               [WEAK]
+                EXPORT  TIM5_IRQHandler               [WEAK]
+                EXPORT  SPI3_IRQHandler               [WEAK]
+                EXPORT  UART4_IRQHandler              [WEAK]
+                EXPORT  UART5_IRQHandler              [WEAK]
+                EXPORT  TIM6_IRQHandler               [WEAK]
+                EXPORT  TIM7_IRQHandler               [WEAK]
+                EXPORT  DMA2_Channel1_IRQHandler      [WEAK]
+                EXPORT  DMA2_Channel2_IRQHandler      [WEAK]
+                EXPORT  DMA2_Channel3_IRQHandler      [WEAK]
+                EXPORT  DMA2_Channel4_5_IRQHandler    [WEAK]
+
+WWDG_IRQHandler
+PVD_IRQHandler
+TAMPER_IRQHandler
+RTC_IRQHandler
+FLASH_IRQHandler
+RCC_IRQHandler
+EXTI0_IRQHandler
+EXTI1_IRQHandler
+EXTI2_IRQHandler
+EXTI3_IRQHandler
+EXTI4_IRQHandler
+DMA1_Channel1_IRQHandler
+DMA1_Channel2_IRQHandler
+DMA1_Channel3_IRQHandler
+DMA1_Channel4_IRQHandler
+DMA1_Channel5_IRQHandler
+DMA1_Channel6_IRQHandler
+DMA1_Channel7_IRQHandler
+ADC1_2_IRQHandler
+USB_HP_CAN1_TX_IRQHandler
+USB_LP_CAN1_RX0_IRQHandler
+CAN1_RX1_IRQHandler
+CAN1_SCE_IRQHandler
+EXTI9_5_IRQHandler
+TIM1_BRK_TIM9_IRQHandler
+TIM1_UP_TIM10_IRQHandler
+TIM1_TRG_COM_TIM11_IRQHandler
+TIM1_CC_IRQHandler
+TIM2_IRQHandler
+TIM3_IRQHandler
+TIM4_IRQHandler
+I2C1_EV_IRQHandler
+I2C1_ER_IRQHandler
+I2C2_EV_IRQHandler
+I2C2_ER_IRQHandler
+SPI1_IRQHandler
+SPI2_IRQHandler
+USART1_IRQHandler
+USART2_IRQHandler
+USART3_IRQHandler
+EXTI15_10_IRQHandler
+RTCAlarm_IRQHandler
+USBWakeUp_IRQHandler
+TIM8_BRK_TIM12_IRQHandler
+TIM8_UP_TIM13_IRQHandler
+TIM8_TRG_COM_TIM14_IRQHandler
+TIM8_CC_IRQHandler
+ADC3_IRQHandler
+FSMC_IRQHandler
+SDIO_IRQHandler
+TIM5_IRQHandler
+SPI3_IRQHandler
+UART4_IRQHandler
+UART5_IRQHandler
+TIM6_IRQHandler
+TIM7_IRQHandler
+DMA2_Channel1_IRQHandler
+DMA2_Channel2_IRQHandler
+DMA2_Channel3_IRQHandler
+DMA2_Channel4_5_IRQHandler
+                B       .
+
+                ENDP
+
+                ALIGN
+
+;*******************************************************************************
+; User Stack and Heap initialization
+;*******************************************************************************
+                 IF      :DEF:__MICROLIB
+                
+                 EXPORT  __initial_sp
+                 EXPORT  __heap_base
+                 EXPORT  __heap_limit
+                
+                 ELSE
+                
+                 IMPORT  __use_two_region_memory
+                 EXPORT  __user_initial_stackheap
+                 
+__user_initial_stackheap
+
+                 LDR     R0, =  Heap_Mem
+                 LDR     R1, =(Stack_Mem + Stack_Size)
+                 LDR     R2, = (Heap_Mem +  Heap_Size)
+                 LDR     R3, = Stack_Mem
+                 BX      LR
+
+                 ALIGN
+
+                 ENDIF
+
+                 END
+
+;******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE*****
diff --git a/STM32_4路称重_Git提交精简工程/src/CMSIS/core_cm3.c b/STM32_4路称重_Git提交精简工程/src/CMSIS/core_cm3.c
new file mode 100755
index 0000000..56fddc5
--- /dev/null
+++ b/STM32_4路称重_Git提交精简工程/src/CMSIS/core_cm3.c
@@ -0,0 +1,784 @@
+/**************************************************************************//**
+ * @file     core_cm3.c
+ * @brief    CMSIS Cortex-M3 Core Peripheral Access Layer Source File
+ * @version  V1.30
+ * @date     30. October 2009
+ *
+ * @note
+ * Copyright (C) 2009 ARM Limited. All rights reserved.
+ *
+ * @par
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M 
+ * processor based microcontrollers.  This file can be freely distributed 
+ * within development tools that are supporting such ARM based processors. 
+ *
+ * @par
+ * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ ******************************************************************************/
+
+#include <stdint.h>
+
+/* define compiler specific symbols */
+#if defined ( __CC_ARM   )
+  #define __ASM            __asm                                      /*!< asm keyword for ARM Compiler          */
+  #define __INLINE         __inline                                   /*!< inline keyword for ARM Compiler       */
+
+#elif defined ( __ICCARM__ )
+  #define __ASM           __asm                                       /*!< asm keyword for IAR Compiler          */
+  #define __INLINE        inline                                      /*!< inline keyword for IAR Compiler. Only avaiable in High optimization mode! */
+
+#elif defined   (  __GNUC__  )
+  #define __ASM            __asm                                      /*!< asm keyword for GNU Compiler          */
+  #define __INLINE         inline                                     /*!< inline keyword for GNU Compiler       */
+
+#elif defined   (  __TASKING__  )
+  #define __ASM            __asm                                      /*!< asm keyword for TASKING Compiler      */
+  #define __INLINE         inline                                     /*!< inline keyword for TASKING Compiler   */
+
+#endif
+
+
+/* ###################  Compiler specific Intrinsics  ########################### */
+
+#if defined ( __CC_ARM   ) /*------------------RealView Compiler -----------------*/
+/* ARM armcc specific functions */
+
+/**
+ * @brief  Return the Process Stack Pointer
+ *
+ * @return ProcessStackPointer
+ *
+ * Return the actual process stack pointer
+ */
+__ASM uint32_t __get_PSP(void)
+{
+  mrs r0, psp
+  bx lr
+}
+
+/**
+ * @brief  Set the Process Stack Pointer
+ *
+ * @param  topOfProcStack  Process Stack Pointer
+ *
+ * Assign the value ProcessStackPointer to the MSP 
+ * (process stack pointer) Cortex processor register
+ */
+__ASM void __set_PSP(uint32_t topOfProcStack)
+{
+  msr psp, r0
+  bx lr
+}
+
+/**
+ * @brief  Return the Main Stack Pointer
+ *
+ * @return Main Stack Pointer
+ *
+ * Return the current value of the MSP (main stack pointer)
+ * Cortex processor register
+ */
+__ASM uint32_t __get_MSP(void)
+{
+  mrs r0, msp
+  bx lr
+}
+
+/**
+ * @brief  Set the Main Stack Pointer
+ *
+ * @param  topOfMainStack  Main Stack Pointer
+ *
+ * Assign the value mainStackPointer to the MSP 
+ * (main stack pointer) Cortex processor register
+ */
+__ASM void __set_MSP(uint32_t mainStackPointer)
+{
+  msr msp, r0
+  bx lr
+}
+
+/**
+ * @brief  Reverse byte order in unsigned short value
+ *
+ * @param   value  value to reverse
+ * @return         reversed value
+ *
+ * Reverse byte order in unsigned short value
+ */
+__ASM uint32_t __REV16(uint16_t value)
+{
+  rev16 r0, r0
+  bx lr
+}
+
+/**
+ * @brief  Reverse byte order in signed short value with sign extension to integer
+ *
+ * @param   value  value to reverse
+ * @return         reversed value
+ *
+ * Reverse byte order in signed short value with sign extension to integer
+ */
+__ASM int32_t __REVSH(int16_t value)
+{
+  revsh r0, r0
+  bx lr
+}
+
+
+#if (__ARMCC_VERSION < 400000)
+
+/**
+ * @brief  Remove the exclusive lock created by ldrex
+ *
+ * Removes the exclusive lock which is created by ldrex.
+ */
+__ASM void __CLREX(void)
+{
+  clrex
+}
+
+/**
+ * @brief  Return the Base Priority value
+ *
+ * @return BasePriority
+ *
+ * Return the content of the base priority register
+ */
+__ASM uint32_t  __get_BASEPRI(void)
+{
+  mrs r0, basepri
+  bx lr
+}
+
+/**
+ * @brief  Set the Base Priority value
+ *
+ * @param  basePri  BasePriority
+ *
+ * Set the base priority register
+ */
+__ASM void __set_BASEPRI(uint32_t basePri)
+{
+  msr basepri, r0
+  bx lr
+}
+
+/**
+ * @brief  Return the Priority Mask value
+ *
+ * @return PriMask
+ *
+ * Return state of the priority mask bit from the priority mask register
+ */
+__ASM uint32_t __get_PRIMASK(void)
+{
+  mrs r0, primask
+  bx lr
+}
+
+/**
+ * @brief  Set the Priority Mask value
+ *
+ * @param  priMask  PriMask
+ *
+ * Set the priority mask bit in the priority mask register
+ */
+__ASM void __set_PRIMASK(uint32_t priMask)
+{
+  msr primask, r0
+  bx lr
+}
+
+/**
+ * @brief  Return the Fault Mask value
+ *
+ * @return FaultMask
+ *
+ * Return the content of the fault mask register
+ */
+__ASM uint32_t  __get_FAULTMASK(void)
+{
+  mrs r0, faultmask
+  bx lr
+}
+
+/**
+ * @brief  Set the Fault Mask value
+ *
+ * @param  faultMask  faultMask value
+ *
+ * Set the fault mask register
+ */
+__ASM void __set_FAULTMASK(uint32_t faultMask)
+{
+  msr faultmask, r0
+  bx lr
+}
+
+/**
+ * @brief  Return the Control Register value
+ * 
+ * @return Control value
+ *
+ * Return the content of the control register
+ */
+__ASM uint32_t __get_CONTROL(void)
+{
+  mrs r0, control
+  bx lr
+}
+
+/**
+ * @brief  Set the Control Register value
+ *
+ * @param  control  Control value
+ *
+ * Set the control register
+ */
+__ASM void __set_CONTROL(uint32_t control)
+{
+  msr control, r0
+  bx lr
+}
+
+#endif /* __ARMCC_VERSION  */ 
+
+
+
+#elif (defined (__ICCARM__)) /*------------------ ICC Compiler -------------------*/
+/* IAR iccarm specific functions */
+#pragma diag_suppress=Pe940
+
+/**
+ * @brief  Return the Process Stack Pointer
+ *
+ * @return ProcessStackPointer
+ *
+ * Return the actual process stack pointer
+ */
+uint32_t __get_PSP(void)
+{
+  __ASM("mrs r0, psp");
+  __ASM("bx lr");
+}
+
+/**
+ * @brief  Set the Process Stack Pointer
+ *
+ * @param  topOfProcStack  Process Stack Pointer
+ *
+ * Assign the value ProcessStackPointer to the MSP 
+ * (process stack pointer) Cortex processor register
+ */
+void __set_PSP(uint32_t topOfProcStack)
+{
+  __ASM("msr psp, r0");
+  __ASM("bx lr");
+}
+
+/**
+ * @brief  Return the Main Stack Pointer
+ *
+ * @return Main Stack Pointer
+ *
+ * Return the current value of the MSP (main stack pointer)
+ * Cortex processor register
+ */
+uint32_t __get_MSP(void)
+{
+  __ASM("mrs r0, msp");
+  __ASM("bx lr");
+}
+
+/**
+ * @brief  Set the Main Stack Pointer
+ *
+ * @param  topOfMainStack  Main Stack Pointer
+ *
+ * Assign the value mainStackPointer to the MSP 
+ * (main stack pointer) Cortex processor register
+ */
+void __set_MSP(uint32_t topOfMainStack)
+{
+  __ASM("msr msp, r0");
+  __ASM("bx lr");
+}
+
+/**
+ * @brief  Reverse byte order in unsigned short value
+ *
+ * @param  value  value to reverse
+ * @return        reversed value
+ *
+ * Reverse byte order in unsigned short value
+ */
+uint32_t __REV16(uint16_t value)
+{
+  __ASM("rev16 r0, r0");
+  __ASM("bx lr");
+}
+
+/**
+ * @brief  Reverse bit order of value
+ *
+ * @param  value  value to reverse
+ * @return        reversed value
+ *
+ * Reverse bit order of value
+ */
+uint32_t __RBIT(uint32_t value)
+{
+  __ASM("rbit r0, r0");
+  __ASM("bx lr");
+}
+
+/**
+ * @brief  LDR Exclusive (8 bit)
+ *
+ * @param  *addr  address pointer
+ * @return        value of (*address)
+ *
+ * Exclusive LDR command for 8 bit values)
+ */
+uint8_t __LDREXB(uint8_t *addr)
+{
+  __ASM("ldrexb r0, [r0]");
+  __ASM("bx lr"); 
+}
+
+/**
+ * @brief  LDR Exclusive (16 bit)
+ *
+ * @param  *addr  address pointer
+ * @return        value of (*address)
+ *
+ * Exclusive LDR command for 16 bit values
+ */
+uint16_t __LDREXH(uint16_t *addr)
+{
+  __ASM("ldrexh r0, [r0]");
+  __ASM("bx lr");
+}
+
+/**
+ * @brief  LDR Exclusive (32 bit)
+ *
+ * @param  *addr  address pointer
+ * @return        value of (*address)
+ *
+ * Exclusive LDR command for 32 bit values
+ */
+uint32_t __LDREXW(uint32_t *addr)
+{
+  __ASM("ldrex r0, [r0]");
+  __ASM("bx lr");
+}
+
+/**
+ * @brief  STR Exclusive (8 bit)
+ *
+ * @param  value  value to store
+ * @param  *addr  address pointer
+ * @return        successful / failed
+ *
+ * Exclusive STR command for 8 bit values
+ */
+uint32_t __STREXB(uint8_t value, uint8_t *addr)
+{
+  __ASM("strexb r0, r0, [r1]");
+  __ASM("bx lr");
+}
+
+/**
+ * @brief  STR Exclusive (16 bit)
+ *
+ * @param  value  value to store
+ * @param  *addr  address pointer
+ * @return        successful / failed
+ *
+ * Exclusive STR command for 16 bit values
+ */
+uint32_t __STREXH(uint16_t value, uint16_t *addr)
+{
+  __ASM("strexh r0, r0, [r1]");
+  __ASM("bx lr");
+}
+
+/**
+ * @brief  STR Exclusive (32 bit)
+ *
+ * @param  value  value to store
+ * @param  *addr  address pointer
+ * @return        successful / failed
+ *
+ * Exclusive STR command for 32 bit values
+ */
+uint32_t __STREXW(uint32_t value, uint32_t *addr)
+{
+  __ASM("strex r0, r0, [r1]");
+  __ASM("bx lr");
+}
+
+#pragma diag_default=Pe940
+
+
+#elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/
+/* GNU gcc specific functions */
+
+/**
+ * @brief  Return the Process Stack Pointer
+ *
+ * @return ProcessStackPointer
+ *
+ * Return the actual process stack pointer
+ */
+uint32_t __get_PSP(void) __attribute__( ( naked ) );
+uint32_t __get_PSP(void)
+{
+  uint32_t result=0;
+
+  __ASM volatile ("MRS %0, psp\n\t" 
+                  "MOV r0, %0 \n\t"
+                  "BX  lr     \n\t"  : "=r" (result) );
+  return(result);
+}
+
+/**
+ * @brief  Set the Process Stack Pointer
+ *
+ * @param  topOfProcStack  Process Stack Pointer
+ *
+ * Assign the value ProcessStackPointer to the MSP 
+ * (process stack pointer) Cortex processor register
+ */
+void __set_PSP(uint32_t topOfProcStack) __attribute__( ( naked ) );
+void __set_PSP(uint32_t topOfProcStack)
+{
+  __ASM volatile ("MSR psp, %0\n\t"
+                  "BX  lr     \n\t" : : "r" (topOfProcStack) );
+}
+
+/**
+ * @brief  Return the Main Stack Pointer
+ *
+ * @return Main Stack Pointer
+ *
+ * Return the current value of the MSP (main stack pointer)
+ * Cortex processor register
+ */
+uint32_t __get_MSP(void) __attribute__( ( naked ) );
+uint32_t __get_MSP(void)
+{
+  uint32_t result=0;
+
+  __ASM volatile ("MRS %0, msp\n\t" 
+                  "MOV r0, %0 \n\t"
+                  "BX  lr     \n\t"  : "=r" (result) );
+  return(result);
+}
+
+/**
+ * @brief  Set the Main Stack Pointer
+ *
+ * @param  topOfMainStack  Main Stack Pointer
+ *
+ * Assign the value mainStackPointer to the MSP 
+ * (main stack pointer) Cortex processor register
+ */
+void __set_MSP(uint32_t topOfMainStack) __attribute__( ( naked ) );
+void __set_MSP(uint32_t topOfMainStack)
+{
+  __ASM volatile ("MSR msp, %0\n\t"
+                  "BX  lr     \n\t" : : "r" (topOfMainStack) );
+}
+
+/**
+ * @brief  Return the Base Priority value
+ *
+ * @return BasePriority
+ *
+ * Return the content of the base priority register
+ */
+uint32_t __get_BASEPRI(void)
+{
+  uint32_t result=0;
+  
+  __ASM volatile ("MRS %0, basepri_max" : "=r" (result) );
+  return(result);
+}
+
+/**
+ * @brief  Set the Base Priority value
+ *
+ * @param  basePri  BasePriority
+ *
+ * Set the base priority register
+ */
+void __set_BASEPRI(uint32_t value)
+{
+  __ASM volatile ("MSR basepri, %0" : : "r" (value) );
+}
+
+/**
+ * @brief  Return the Priority Mask value
+ *
+ * @return PriMask
+ *
+ * Return state of the priority mask bit from the priority mask register
+ */
+uint32_t __get_PRIMASK(void)
+{
+  uint32_t result=0;
+
+  __ASM volatile ("MRS %0, primask" : "=r" (result) );
+  return(result);
+}
+
+/**
+ * @brief  Set the Priority Mask value
+ *
+ * @param  priMask  PriMask
+ *
+ * Set the priority mask bit in the priority mask register
+ */
+void __set_PRIMASK(uint32_t priMask)
+{
+  __ASM volatile ("MSR primask, %0" : : "r" (priMask) );
+}
+
+/**
+ * @brief  Return the Fault Mask value
+ *
+ * @return FaultMask
+ *
+ * Return the content of the fault mask register
+ */
+uint32_t __get_FAULTMASK(void)
+{
+  uint32_t result=0;
+  
+  __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
+  return(result);
+}
+
+/**
+ * @brief  Set the Fault Mask value
+ *
+ * @param  faultMask  faultMask value
+ *
+ * Set the fault mask register
+ */
+void __set_FAULTMASK(uint32_t faultMask)
+{
+  __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) );
+}
+
+/**
+ * @brief  Return the Control Register value
+* 
+*  @return Control value
+ *
+ * Return the content of the control register
+ */
+uint32_t __get_CONTROL(void)
+{
+  uint32_t result=0;
+
+  __ASM volatile ("MRS %0, control" : "=r" (result) );
+  return(result);
+}
+
+/**
+ * @brief  Set the Control Register value
+ *
+ * @param  control  Control value
+ *
+ * Set the control register
+ */
+void __set_CONTROL(uint32_t control)
+{
+  __ASM volatile ("MSR control, %0" : : "r" (control) );
+}
+
+
+/**
+ * @brief  Reverse byte order in integer value
+ *
+ * @param  value  value to reverse
+ * @return        reversed value
+ *
+ * Reverse byte order in integer value
+ */
+uint32_t __REV(uint32_t value)
+{
+  uint32_t result=0;
+  
+  __ASM volatile ("rev %0, %1" : "=r" (result) : "r" (value) );
+  return(result);
+}
+
+/**
+ * @brief  Reverse byte order in unsigned short value
+ *
+ * @param  value  value to reverse
+ * @return        reversed value
+ *
+ * Reverse byte order in unsigned short value
+ */
+uint32_t __REV16(uint16_t value)
+{
+  uint32_t result=0;
+  
+  __ASM volatile ("rev16 %0, %1" : "=r" (result) : "r" (value) );
+  return(result);
+}
+
+/**
+ * @brief  Reverse byte order in signed short value with sign extension to integer
+ *
+ * @param  value  value to reverse
+ * @return        reversed value
+ *
+ * Reverse byte order in signed short value with sign extension to integer
+ */
+int32_t __REVSH(int16_t value)
+{
+  uint32_t result=0;
+  
+  __ASM volatile ("revsh %0, %1" : "=r" (result) : "r" (value) );
+  return(result);
+}
+
+/**
+ * @brief  Reverse bit order of value
+ *
+ * @param  value  value to reverse
+ * @return        reversed value
+ *
+ * Reverse bit order of value
+ */
+uint32_t __RBIT(uint32_t value)
+{
+  uint32_t result=0;
+  
+   __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
+   return(result);
+}
+
+/**
+ * @brief  LDR Exclusive (8 bit)
+ *
+ * @param  *addr  address pointer
+ * @return        value of (*address)
+ *
+ * Exclusive LDR command for 8 bit value
+ */
+uint8_t __LDREXB(uint8_t *addr)
+{
+    uint8_t result=0;
+  
+   __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) );
+   return(result);
+}
+
+/**
+ * @brief  LDR Exclusive (16 bit)
+ *
+ * @param  *addr  address pointer
+ * @return        value of (*address)
+ *
+ * Exclusive LDR command for 16 bit values
+ */
+uint16_t __LDREXH(uint16_t *addr)
+{
+    uint16_t result=0;
+  
+   __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) );
+   return(result);
+}
+
+/**
+ * @brief  LDR Exclusive (32 bit)
+ *
+ * @param  *addr  address pointer
+ * @return        value of (*address)
+ *
+ * Exclusive LDR command for 32 bit values
+ */
+uint32_t __LDREXW(uint32_t *addr)
+{
+    uint32_t result=0;
+  
+   __ASM volatile ("ldrex %0, [%1]" : "=r" (result) : "r" (addr) );
+   return(result);
+}
+
+/**
+ * @brief  STR Exclusive (8 bit)
+ *
+ * @param  value  value to store
+ * @param  *addr  address pointer
+ * @return        successful / failed
+ *
+ * Exclusive STR command for 8 bit values
+ */
+uint32_t __STREXB(uint8_t value, uint8_t *addr)
+{
+   uint32_t result=0;
+  
+   __ASM volatile ("strexb %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) );
+   return(result);
+}
+
+/**
+ * @brief  STR Exclusive (16 bit)
+ *
+ * @param  value  value to store
+ * @param  *addr  address pointer
+ * @return        successful / failed
+ *
+ * Exclusive STR command for 16 bit values
+ */
+uint32_t __STREXH(uint16_t value, uint16_t *addr)
+{
+   uint32_t result=0;
+  
+   __ASM volatile ("strexh %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) );
+   return(result);
+}
+
+/**
+ * @brief  STR Exclusive (32 bit)
+ *
+ * @param  value  value to store
+ * @param  *addr  address pointer
+ * @return        successful / failed
+ *
+ * Exclusive STR command for 32 bit values
+ */
+uint32_t __STREXW(uint32_t value, uint32_t *addr)
+{
+   uint32_t result=0;
+  
+   __ASM volatile ("strex %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) );
+   return(result);
+}
+
+
+#elif (defined (__TASKING__)) /*------------------ TASKING Compiler ---------------------*/
+/* TASKING carm specific functions */
+
+/*
+ * The CMSIS functions have been implemented as intrinsics in the compiler.
+ * Please use "carm -?i" to get an up to date list of all instrinsics,
+ * Including the CMSIS ones.
+ */
+
+#endif
diff --git a/STM32_4路称重_Git提交精简工程/src/CMSIS/core_cm3.h b/STM32_4路称重_Git提交精简工程/src/CMSIS/core_cm3.h
new file mode 100755
index 0000000..2b6b51a
--- /dev/null
+++ b/STM32_4路称重_Git提交精简工程/src/CMSIS/core_cm3.h
@@ -0,0 +1,1818 @@
+/**************************************************************************//**
+ * @file     core_cm3.h
+ * @brief    CMSIS Cortex-M3 Core Peripheral Access Layer Header File
+ * @version  V1.30
+ * @date     30. October 2009
+ *
+ * @note
+ * Copyright (C) 2009 ARM Limited. All rights reserved.
+ *
+ * @par
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M 
+ * processor based microcontrollers.  This file can be freely distributed 
+ * within development tools that are supporting such ARM based processors. 
+ *
+ * @par
+ * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ ******************************************************************************/
+
+#ifndef __CM3_CORE_H__
+#define __CM3_CORE_H__
+
+/** @addtogroup CMSIS_CM3_core_LintCinfiguration CMSIS CM3 Core Lint Configuration
+ *
+ * List of Lint messages which will be suppressed and not shown:
+ *   - Error 10: \n
+ *     register uint32_t __regBasePri         __asm("basepri"); \n
+ *     Error 10: Expecting ';'
+ * .
+ *   - Error 530: \n
+ *     return(__regBasePri); \n
+ *     Warning 530: Symbol '__regBasePri' (line 264) not initialized
+ * . 
+ *   - Error 550: \n
+ *     __regBasePri = (basePri & 0x1ff); \n
+ *     Warning 550: Symbol '__regBasePri' (line 271) not accessed
+ * .
+ *   - Error 754: \n
+ *     uint32_t RESERVED0[24]; \n
+ *     Info 754: local structure member '<some, not used in the HAL>' (line 109, file ./cm3_core.h) not referenced
+ * .
+ *   - Error 750: \n
+ *     #define __CM3_CORE_H__ \n
+ *     Info 750: local macro '__CM3_CORE_H__' (line 43, file./cm3_core.h) not referenced
+ * .
+ *   - Error 528: \n
+ *     static __INLINE void NVIC_DisableIRQ(uint32_t IRQn) \n
+ *     Warning 528: Symbol 'NVIC_DisableIRQ(unsigned int)' (line 419, file ./cm3_core.h) not referenced
+ * .
+ *   - Error 751: \n
+ *     } InterruptType_Type; \n
+ *     Info 751: local typedef 'InterruptType_Type' (line 170, file ./cm3_core.h) not referenced
+ * .
+ * Note:  To re-enable a Message, insert a space before 'lint' *
+ *
+ */
+
+/*lint -save */
+/*lint -e10  */
+/*lint -e530 */
+/*lint -e550 */
+/*lint -e754 */
+/*lint -e750 */
+/*lint -e528 */
+/*lint -e751 */
+
+
+/** @addtogroup CMSIS_CM3_core_definitions CM3 Core Definitions
+  This file defines all structures and symbols for CMSIS core:
+    - CMSIS version number
+    - Cortex-M core registers and bitfields
+    - Cortex-M core peripheral base address
+  @{
+ */
+
+#ifdef __cplusplus
+ extern "C" {
+#endif 
+
+#define __CM3_CMSIS_VERSION_MAIN  (0x01)                                                       /*!< [31:16] CMSIS HAL main version */
+#define __CM3_CMSIS_VERSION_SUB   (0x30)                                                       /*!< [15:0]  CMSIS HAL sub version  */
+#define __CM3_CMSIS_VERSION       ((__CM3_CMSIS_VERSION_MAIN << 16) | __CM3_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number       */
+
+#define __CORTEX_M                (0x03)                                                       /*!< Cortex core                    */
+
+#include <stdint.h>                           /* Include standard types */
+
+#if defined (__ICCARM__)
+  #include <intrinsics.h>                     /* IAR Intrinsics   */
+#endif
+
+
+#ifndef __NVIC_PRIO_BITS
+  #define __NVIC_PRIO_BITS    4               /*!< standard definition for NVIC Priority Bits */
+#endif
+
+
+
+
+/**
+ * IO definitions
+ *
+ * define access restrictions to peripheral registers
+ */
+
+#ifdef __cplusplus
+  #define     __I     volatile                /*!< defines 'read only' permissions      */
+#else
+  #define     __I     volatile const          /*!< defines 'read only' permissions      */
+#endif
+#define     __O     volatile                  /*!< defines 'write only' permissions     */
+#define     __IO    volatile                  /*!< defines 'read / write' permissions   */
+
+
+
+/*******************************************************************************
+ *                 Register Abstraction
+ ******************************************************************************/
+/** @addtogroup CMSIS_CM3_core_register CMSIS CM3 Core Register
+ @{
+*/
+
+
+/** @addtogroup CMSIS_CM3_NVIC CMSIS CM3 NVIC
+  memory mapped structure for Nested Vectored Interrupt Controller (NVIC)
+  @{
+ */
+typedef struct
+{
+  __IO uint32_t ISER[8];                      /*!< Offset: 0x000  Interrupt Set Enable Register           */
+       uint32_t RESERVED0[24];                                   
+  __IO uint32_t ICER[8];                      /*!< Offset: 0x080  Interrupt Clear Enable Register         */
+       uint32_t RSERVED1[24];                                    
+  __IO uint32_t ISPR[8];                      /*!< Offset: 0x100  Interrupt Set Pending Register          */
+       uint32_t RESERVED2[24];                                   
+  __IO uint32_t ICPR[8];                      /*!< Offset: 0x180  Interrupt Clear Pending Register        */
+       uint32_t RESERVED3[24];                                   
+  __IO uint32_t IABR[8];                      /*!< Offset: 0x200  Interrupt Active bit Register           */
+       uint32_t RESERVED4[56];                                   
+  __IO uint8_t  IP[240];                      /*!< Offset: 0x300  Interrupt Priority Register (8Bit wide) */
+       uint32_t RESERVED5[644];                                  
+  __O  uint32_t STIR;                         /*!< Offset: 0xE00  Software Trigger Interrupt Register     */
+}  NVIC_Type;                                               
+/*@}*/ /* end of group CMSIS_CM3_NVIC */
+
+
+/** @addtogroup CMSIS_CM3_SCB CMSIS CM3 SCB
+  memory mapped structure for System Control Block (SCB)
+  @{
+ */
+typedef struct
+{
+  __I  uint32_t CPUID;                        /*!< Offset: 0x00  CPU ID Base Register                                  */
+  __IO uint32_t ICSR;                         /*!< Offset: 0x04  Interrupt Control State Register                      */
+  __IO uint32_t VTOR;                         /*!< Offset: 0x08  Vector Table Offset Register                          */
+  __IO uint32_t AIRCR;                        /*!< Offset: 0x0C  Application Interrupt / Reset Control Register        */
+  __IO uint32_t SCR;                          /*!< Offset: 0x10  System Control Register                               */
+  __IO uint32_t CCR;                          /*!< Offset: 0x14  Configuration Control Register                        */
+  __IO uint8_t  SHP[12];                      /*!< Offset: 0x18  System Handlers Priority Registers (4-7, 8-11, 12-15) */
+  __IO uint32_t SHCSR;                        /*!< Offset: 0x24  System Handler Control and State Register             */
+  __IO uint32_t CFSR;                         /*!< Offset: 0x28  Configurable Fault Status Register                    */
+  __IO uint32_t HFSR;                         /*!< Offset: 0x2C  Hard Fault Status Register                            */
+  __IO uint32_t DFSR;                         /*!< Offset: 0x30  Debug Fault Status Register                           */
+  __IO uint32_t MMFAR;                        /*!< Offset: 0x34  Mem Manage Address Register                           */
+  __IO uint32_t BFAR;                         /*!< Offset: 0x38  Bus Fault Address Register                            */
+  __IO uint32_t AFSR;                         /*!< Offset: 0x3C  Auxiliary Fault Status Register                       */
+  __I  uint32_t PFR[2];                       /*!< Offset: 0x40  Processor Feature Register                            */
+  __I  uint32_t DFR;                          /*!< Offset: 0x48  Debug Feature Register                                */
+  __I  uint32_t ADR;                          /*!< Offset: 0x4C  Auxiliary Feature Register                            */
+  __I  uint32_t MMFR[4];                      /*!< Offset: 0x50  Memory Model Feature Register                         */
+  __I  uint32_t ISAR[5];                      /*!< Offset: 0x60  ISA Feature Register                                  */
+} SCB_Type;                                                
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos          24                                             /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFul << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos              20                                             /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk              (0xFul << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_PARTNO_Pos                4                                             /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk               (0xFFFul << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos              0                                             /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk             (0xFul << SCB_CPUID_REVISION_Pos)              /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos            31                                             /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk            (1ul << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos             28                                             /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk             (1ul << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos             27                                             /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk             (1ul << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos             26                                             /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk             (1ul << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos             25                                             /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk             (1ul << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos            23                                             /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk            (1ul << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos            22                                             /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk            (1ul << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos           12                                             /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk           (0x1FFul << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos             11                                             /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk             (1ul << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos             0                                             /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFul << SCB_ICSR_VECTACTIVE_Pos)           /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_VTOR_TBLBASE_Pos               29                                             /*!< SCB VTOR: TBLBASE Position */
+#define SCB_VTOR_TBLBASE_Msk               (0x1FFul << SCB_VTOR_TBLBASE_Pos)              /*!< SCB VTOR: TBLBASE Mask */
+
+#define SCB_VTOR_TBLOFF_Pos                 7                                             /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk                (0x3FFFFFul << SCB_VTOR_TBLOFF_Pos)            /*!< SCB VTOR: TBLOFF Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos              16                                             /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFul << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos          16                                             /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFul << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos            15                                             /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk            (1ul << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIGROUP_Pos              8                                             /*!< SCB AIRCR: PRIGROUP Position */
+#define SCB_AIRCR_PRIGROUP_Msk             (7ul << SCB_AIRCR_PRIGROUP_Pos)                /*!< SCB AIRCR: PRIGROUP Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos           2                                             /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk          (1ul << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos         1                                             /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1ul << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+#define SCB_AIRCR_VECTRESET_Pos             0                                             /*!< SCB AIRCR: VECTRESET Position */
+#define SCB_AIRCR_VECTRESET_Msk            (1ul << SCB_AIRCR_VECTRESET_Pos)               /*!< SCB AIRCR: VECTRESET Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos               4                                             /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk              (1ul << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos               2                                             /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk              (1ul << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos             1                                             /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk            (1ul << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos                9                                             /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk               (1ul << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos               8                                             /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk              (1ul << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos               4                                             /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk              (1ul << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos             3                                             /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk            (1ul << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos            1                                             /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk           (1ul << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB CCR: USERSETMPEND Mask */
+
+#define SCB_CCR_NONBASETHRDENA_Pos          0                                             /*!< SCB CCR: NONBASETHRDENA Position */
+#define SCB_CCR_NONBASETHRDENA_Msk         (1ul << SCB_CCR_NONBASETHRDENA_Pos)            /*!< SCB CCR: NONBASETHRDENA Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_USGFAULTENA_Pos          18                                             /*!< SCB SHCSR: USGFAULTENA Position */
+#define SCB_SHCSR_USGFAULTENA_Msk          (1ul << SCB_SHCSR_USGFAULTENA_Pos)             /*!< SCB SHCSR: USGFAULTENA Mask */
+
+#define SCB_SHCSR_BUSFAULTENA_Pos          17                                             /*!< SCB SHCSR: BUSFAULTENA Position */
+#define SCB_SHCSR_BUSFAULTENA_Msk          (1ul << SCB_SHCSR_BUSFAULTENA_Pos)             /*!< SCB SHCSR: BUSFAULTENA Mask */
+
+#define SCB_SHCSR_MEMFAULTENA_Pos          16                                             /*!< SCB SHCSR: MEMFAULTENA Position */
+#define SCB_SHCSR_MEMFAULTENA_Msk          (1ul << SCB_SHCSR_MEMFAULTENA_Pos)             /*!< SCB SHCSR: MEMFAULTENA Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos         15                                             /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk         (1ul << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_BUSFAULTPENDED_Pos       14                                             /*!< SCB SHCSR: BUSFAULTPENDED Position */
+#define SCB_SHCSR_BUSFAULTPENDED_Msk       (1ul << SCB_SHCSR_BUSFAULTPENDED_Pos)          /*!< SCB SHCSR: BUSFAULTPENDED Mask */
+
+#define SCB_SHCSR_MEMFAULTPENDED_Pos       13                                             /*!< SCB SHCSR: MEMFAULTPENDED Position */
+#define SCB_SHCSR_MEMFAULTPENDED_Msk       (1ul << SCB_SHCSR_MEMFAULTPENDED_Pos)          /*!< SCB SHCSR: MEMFAULTPENDED Mask */
+
+#define SCB_SHCSR_USGFAULTPENDED_Pos       12                                             /*!< SCB SHCSR: USGFAULTPENDED Position */
+#define SCB_SHCSR_USGFAULTPENDED_Msk       (1ul << SCB_SHCSR_USGFAULTPENDED_Pos)          /*!< SCB SHCSR: USGFAULTPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos           11                                             /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk           (1ul << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos            10                                             /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk            (1ul << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_MONITORACT_Pos            8                                             /*!< SCB SHCSR: MONITORACT Position */
+#define SCB_SHCSR_MONITORACT_Msk           (1ul << SCB_SHCSR_MONITORACT_Pos)              /*!< SCB SHCSR: MONITORACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos             7                                             /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk            (1ul << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB SHCSR: SVCALLACT Mask */
+                                     
+#define SCB_SHCSR_USGFAULTACT_Pos           3                                             /*!< SCB SHCSR: USGFAULTACT Position */
+#define SCB_SHCSR_USGFAULTACT_Msk          (1ul << SCB_SHCSR_USGFAULTACT_Pos)             /*!< SCB SHCSR: USGFAULTACT Mask */
+
+#define SCB_SHCSR_BUSFAULTACT_Pos           1                                             /*!< SCB SHCSR: BUSFAULTACT Position */
+#define SCB_SHCSR_BUSFAULTACT_Msk          (1ul << SCB_SHCSR_BUSFAULTACT_Pos)             /*!< SCB SHCSR: BUSFAULTACT Mask */
+
+#define SCB_SHCSR_MEMFAULTACT_Pos           0                                             /*!< SCB SHCSR: MEMFAULTACT Position */
+#define SCB_SHCSR_MEMFAULTACT_Msk          (1ul << SCB_SHCSR_MEMFAULTACT_Pos)             /*!< SCB SHCSR: MEMFAULTACT Mask */
+
+/* SCB Configurable Fault Status Registers Definitions */
+#define SCB_CFSR_USGFAULTSR_Pos            16                                             /*!< SCB CFSR: Usage Fault Status Register Position */
+#define SCB_CFSR_USGFAULTSR_Msk            (0xFFFFul << SCB_CFSR_USGFAULTSR_Pos)          /*!< SCB CFSR: Usage Fault Status Register Mask */
+
+#define SCB_CFSR_BUSFAULTSR_Pos             8                                             /*!< SCB CFSR: Bus Fault Status Register Position */
+#define SCB_CFSR_BUSFAULTSR_Msk            (0xFFul << SCB_CFSR_BUSFAULTSR_Pos)            /*!< SCB CFSR: Bus Fault Status Register Mask */
+
+#define SCB_CFSR_MEMFAULTSR_Pos             0                                             /*!< SCB CFSR: Memory Manage Fault Status Register Position */
+#define SCB_CFSR_MEMFAULTSR_Msk            (0xFFul << SCB_CFSR_MEMFAULTSR_Pos)            /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
+
+/* SCB Hard Fault Status Registers Definitions */
+#define SCB_HFSR_DEBUGEVT_Pos              31                                             /*!< SCB HFSR: DEBUGEVT Position */
+#define SCB_HFSR_DEBUGEVT_Msk              (1ul << SCB_HFSR_DEBUGEVT_Pos)                 /*!< SCB HFSR: DEBUGEVT Mask */
+
+#define SCB_HFSR_FORCED_Pos                30                                             /*!< SCB HFSR: FORCED Position */
+#define SCB_HFSR_FORCED_Msk                (1ul << SCB_HFSR_FORCED_Pos)                   /*!< SCB HFSR: FORCED Mask */
+
+#define SCB_HFSR_VECTTBL_Pos                1                                             /*!< SCB HFSR: VECTTBL Position */
+#define SCB_HFSR_VECTTBL_Msk               (1ul << SCB_HFSR_VECTTBL_Pos)                  /*!< SCB HFSR: VECTTBL Mask */
+
+/* SCB Debug Fault Status Register Definitions */
+#define SCB_DFSR_EXTERNAL_Pos               4                                             /*!< SCB DFSR: EXTERNAL Position */
+#define SCB_DFSR_EXTERNAL_Msk              (1ul << SCB_DFSR_EXTERNAL_Pos)                 /*!< SCB DFSR: EXTERNAL Mask */
+
+#define SCB_DFSR_VCATCH_Pos                 3                                             /*!< SCB DFSR: VCATCH Position */
+#define SCB_DFSR_VCATCH_Msk                (1ul << SCB_DFSR_VCATCH_Pos)                   /*!< SCB DFSR: VCATCH Mask */
+
+#define SCB_DFSR_DWTTRAP_Pos                2                                             /*!< SCB DFSR: DWTTRAP Position */
+#define SCB_DFSR_DWTTRAP_Msk               (1ul << SCB_DFSR_DWTTRAP_Pos)                  /*!< SCB DFSR: DWTTRAP Mask */
+
+#define SCB_DFSR_BKPT_Pos                   1                                             /*!< SCB DFSR: BKPT Position */
+#define SCB_DFSR_BKPT_Msk                  (1ul << SCB_DFSR_BKPT_Pos)                     /*!< SCB DFSR: BKPT Mask */
+
+#define SCB_DFSR_HALTED_Pos                 0                                             /*!< SCB DFSR: HALTED Position */
+#define SCB_DFSR_HALTED_Msk                (1ul << SCB_DFSR_HALTED_Pos)                   /*!< SCB DFSR: HALTED Mask */
+/*@}*/ /* end of group CMSIS_CM3_SCB */
+
+
+/** @addtogroup CMSIS_CM3_SysTick CMSIS CM3 SysTick
+  memory mapped structure for SysTick
+  @{
+ */
+typedef struct
+{
+  __IO uint32_t CTRL;                         /*!< Offset: 0x00  SysTick Control and Status Register */
+  __IO uint32_t LOAD;                         /*!< Offset: 0x04  SysTick Reload Value Register       */
+  __IO uint32_t VAL;                          /*!< Offset: 0x08  SysTick Current Value Register      */
+  __I  uint32_t CALIB;                        /*!< Offset: 0x0C  SysTick Calibration Register        */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos         16                                             /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk         (1ul << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos          2                                             /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk         (1ul << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos            1                                             /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk           (1ul << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos             0                                             /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk            (1ul << SysTick_CTRL_ENABLE_Pos)               /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos             0                                             /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFul << SysTick_LOAD_RELOAD_Pos)        /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos             0                                             /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFul << SysTick_VAL_CURRENT_Pos)        /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos            31                                             /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk            (1ul << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos             30                                             /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk             (1ul << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos             0                                             /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFul << SysTick_VAL_CURRENT_Pos)        /*!< SysTick CALIB: TENMS Mask */
+/*@}*/ /* end of group CMSIS_CM3_SysTick */
+
+
+/** @addtogroup CMSIS_CM3_ITM CMSIS CM3 ITM
+  memory mapped structure for Instrumentation Trace Macrocell (ITM)
+  @{
+ */
+typedef struct
+{
+  __O  union  
+  {
+    __O  uint8_t    u8;                       /*!< Offset:       ITM Stimulus Port 8-bit                   */
+    __O  uint16_t   u16;                      /*!< Offset:       ITM Stimulus Port 16-bit                  */
+    __O  uint32_t   u32;                      /*!< Offset:       ITM Stimulus Port 32-bit                  */
+  }  PORT [32];                               /*!< Offset: 0x00  ITM Stimulus Port Registers               */
+       uint32_t RESERVED0[864];                                 
+  __IO uint32_t TER;                          /*!< Offset:       ITM Trace Enable Register                 */
+       uint32_t RESERVED1[15];                                  
+  __IO uint32_t TPR;                          /*!< Offset:       ITM Trace Privilege Register              */
+       uint32_t RESERVED2[15];                                  
+  __IO uint32_t TCR;                          /*!< Offset:       ITM Trace Control Register                */
+       uint32_t RESERVED3[29];                                  
+  __IO uint32_t IWR;                          /*!< Offset:       ITM Integration Write Register            */
+  __IO uint32_t IRR;                          /*!< Offset:       ITM Integration Read Register             */
+  __IO uint32_t IMCR;                         /*!< Offset:       ITM Integration Mode Control Register     */
+       uint32_t RESERVED4[43];                                  
+  __IO uint32_t LAR;                          /*!< Offset:       ITM Lock Access Register                  */
+  __IO uint32_t LSR;                          /*!< Offset:       ITM Lock Status Register                  */
+       uint32_t RESERVED5[6];                                   
+  __I  uint32_t PID4;                         /*!< Offset:       ITM Peripheral Identification Register #4 */
+  __I  uint32_t PID5;                         /*!< Offset:       ITM Peripheral Identification Register #5 */
+  __I  uint32_t PID6;                         /*!< Offset:       ITM Peripheral Identification Register #6 */
+  __I  uint32_t PID7;                         /*!< Offset:       ITM Peripheral Identification Register #7 */
+  __I  uint32_t PID0;                         /*!< Offset:       ITM Peripheral Identification Register #0 */
+  __I  uint32_t PID1;                         /*!< Offset:       ITM Peripheral Identification Register #1 */
+  __I  uint32_t PID2;                         /*!< Offset:       ITM Peripheral Identification Register #2 */
+  __I  uint32_t PID3;                         /*!< Offset:       ITM Peripheral Identification Register #3 */
+  __I  uint32_t CID0;                         /*!< Offset:       ITM Component  Identification Register #0 */
+  __I  uint32_t CID1;                         /*!< Offset:       ITM Component  Identification Register #1 */
+  __I  uint32_t CID2;                         /*!< Offset:       ITM Component  Identification Register #2 */
+  __I  uint32_t CID3;                         /*!< Offset:       ITM Component  Identification Register #3 */
+} ITM_Type;                                                
+
+/* ITM Trace Privilege Register Definitions */
+#define ITM_TPR_PRIVMASK_Pos                0                                             /*!< ITM TPR: PRIVMASK Position */
+#define ITM_TPR_PRIVMASK_Msk               (0xFul << ITM_TPR_PRIVMASK_Pos)                /*!< ITM TPR: PRIVMASK Mask */
+
+/* ITM Trace Control Register Definitions */
+#define ITM_TCR_BUSY_Pos                   23                                             /*!< ITM TCR: BUSY Position */
+#define ITM_TCR_BUSY_Msk                   (1ul << ITM_TCR_BUSY_Pos)                      /*!< ITM TCR: BUSY Mask */
+
+#define ITM_TCR_ATBID_Pos                  16                                             /*!< ITM TCR: ATBID Position */
+#define ITM_TCR_ATBID_Msk                  (0x7Ful << ITM_TCR_ATBID_Pos)                  /*!< ITM TCR: ATBID Mask */
+
+#define ITM_TCR_TSPrescale_Pos              8                                             /*!< ITM TCR: TSPrescale Position */
+#define ITM_TCR_TSPrescale_Msk             (3ul << ITM_TCR_TSPrescale_Pos)                /*!< ITM TCR: TSPrescale Mask */
+
+#define ITM_TCR_SWOENA_Pos                  4                                             /*!< ITM TCR: SWOENA Position */
+#define ITM_TCR_SWOENA_Msk                 (1ul << ITM_TCR_SWOENA_Pos)                    /*!< ITM TCR: SWOENA Mask */
+
+#define ITM_TCR_DWTENA_Pos                  3                                             /*!< ITM TCR: DWTENA Position */
+#define ITM_TCR_DWTENA_Msk                 (1ul << ITM_TCR_DWTENA_Pos)                    /*!< ITM TCR: DWTENA Mask */
+
+#define ITM_TCR_SYNCENA_Pos                 2                                             /*!< ITM TCR: SYNCENA Position */
+#define ITM_TCR_SYNCENA_Msk                (1ul << ITM_TCR_SYNCENA_Pos)                   /*!< ITM TCR: SYNCENA Mask */
+
+#define ITM_TCR_TSENA_Pos                   1                                             /*!< ITM TCR: TSENA Position */
+#define ITM_TCR_TSENA_Msk                  (1ul << ITM_TCR_TSENA_Pos)                     /*!< ITM TCR: TSENA Mask */
+
+#define ITM_TCR_ITMENA_Pos                  0                                             /*!< ITM TCR: ITM Enable bit Position */
+#define ITM_TCR_ITMENA_Msk                 (1ul << ITM_TCR_ITMENA_Pos)                    /*!< ITM TCR: ITM Enable bit Mask */
+
+/* ITM Integration Write Register Definitions */
+#define ITM_IWR_ATVALIDM_Pos                0                                             /*!< ITM IWR: ATVALIDM Position */
+#define ITM_IWR_ATVALIDM_Msk               (1ul << ITM_IWR_ATVALIDM_Pos)                  /*!< ITM IWR: ATVALIDM Mask */
+
+/* ITM Integration Read Register Definitions */
+#define ITM_IRR_ATREADYM_Pos                0                                             /*!< ITM IRR: ATREADYM Position */
+#define ITM_IRR_ATREADYM_Msk               (1ul << ITM_IRR_ATREADYM_Pos)                  /*!< ITM IRR: ATREADYM Mask */
+
+/* ITM Integration Mode Control Register Definitions */
+#define ITM_IMCR_INTEGRATION_Pos            0                                             /*!< ITM IMCR: INTEGRATION Position */
+#define ITM_IMCR_INTEGRATION_Msk           (1ul << ITM_IMCR_INTEGRATION_Pos)              /*!< ITM IMCR: INTEGRATION Mask */
+
+/* ITM Lock Status Register Definitions */
+#define ITM_LSR_ByteAcc_Pos                 2                                             /*!< ITM LSR: ByteAcc Position */
+#define ITM_LSR_ByteAcc_Msk                (1ul << ITM_LSR_ByteAcc_Pos)                   /*!< ITM LSR: ByteAcc Mask */
+
+#define ITM_LSR_Access_Pos                  1                                             /*!< ITM LSR: Access Position */
+#define ITM_LSR_Access_Msk                 (1ul << ITM_LSR_Access_Pos)                    /*!< ITM LSR: Access Mask */
+
+#define ITM_LSR_Present_Pos                 0                                             /*!< ITM LSR: Present Position */
+#define ITM_LSR_Present_Msk                (1ul << ITM_LSR_Present_Pos)                   /*!< ITM LSR: Present Mask */
+/*@}*/ /* end of group CMSIS_CM3_ITM */
+
+
+/** @addtogroup CMSIS_CM3_InterruptType CMSIS CM3 Interrupt Type
+  memory mapped structure for Interrupt Type
+  @{
+ */
+typedef struct
+{
+       uint32_t RESERVED0;
+  __I  uint32_t ICTR;                         /*!< Offset: 0x04  Interrupt Control Type Register */
+#if ((defined __CM3_REV) && (__CM3_REV >= 0x200))
+  __IO uint32_t ACTLR;                        /*!< Offset: 0x08  Auxiliary Control Register      */
+#else
+       uint32_t RESERVED1;
+#endif
+} InterruptType_Type;
+
+/* Interrupt Controller Type Register Definitions */
+#define InterruptType_ICTR_INTLINESNUM_Pos  0                                             /*!< InterruptType ICTR: INTLINESNUM Position */
+#define InterruptType_ICTR_INTLINESNUM_Msk (0x1Ful << InterruptType_ICTR_INTLINESNUM_Pos) /*!< InterruptType ICTR: INTLINESNUM Mask */
+
+/* Auxiliary Control Register Definitions */
+#define InterruptType_ACTLR_DISFOLD_Pos     2                                             /*!< InterruptType ACTLR: DISFOLD Position */
+#define InterruptType_ACTLR_DISFOLD_Msk    (1ul << InterruptType_ACTLR_DISFOLD_Pos)       /*!< InterruptType ACTLR: DISFOLD Mask */
+
+#define InterruptType_ACTLR_DISDEFWBUF_Pos  1                                             /*!< InterruptType ACTLR: DISDEFWBUF Position */
+#define InterruptType_ACTLR_DISDEFWBUF_Msk (1ul << InterruptType_ACTLR_DISDEFWBUF_Pos)    /*!< InterruptType ACTLR: DISDEFWBUF Mask */
+
+#define InterruptType_ACTLR_DISMCYCINT_Pos  0                                             /*!< InterruptType ACTLR: DISMCYCINT Position */
+#define InterruptType_ACTLR_DISMCYCINT_Msk (1ul << InterruptType_ACTLR_DISMCYCINT_Pos)    /*!< InterruptType ACTLR: DISMCYCINT Mask */
+/*@}*/ /* end of group CMSIS_CM3_InterruptType */
+
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1)
+/** @addtogroup CMSIS_CM3_MPU CMSIS CM3 MPU
+  memory mapped structure for Memory Protection Unit (MPU)
+  @{
+ */
+typedef struct
+{
+  __I  uint32_t TYPE;                         /*!< Offset: 0x00  MPU Type Register                              */
+  __IO uint32_t CTRL;                         /*!< Offset: 0x04  MPU Control Register                           */
+  __IO uint32_t RNR;                          /*!< Offset: 0x08  MPU Region RNRber Register                     */
+  __IO uint32_t RBAR;                         /*!< Offset: 0x0C  MPU Region Base Address Register               */
+  __IO uint32_t RASR;                         /*!< Offset: 0x10  MPU Region Attribute and Size Register         */
+  __IO uint32_t RBAR_A1;                      /*!< Offset: 0x14  MPU Alias 1 Region Base Address Register       */
+  __IO uint32_t RASR_A1;                      /*!< Offset: 0x18  MPU Alias 1 Region Attribute and Size Register */
+  __IO uint32_t RBAR_A2;                      /*!< Offset: 0x1C  MPU Alias 2 Region Base Address Register       */
+  __IO uint32_t RASR_A2;                      /*!< Offset: 0x20  MPU Alias 2 Region Attribute and Size Register */
+  __IO uint32_t RBAR_A3;                      /*!< Offset: 0x24  MPU Alias 3 Region Base Address Register       */
+  __IO uint32_t RASR_A3;                      /*!< Offset: 0x28  MPU Alias 3 Region Attribute and Size Register */
+} MPU_Type;                                                
+
+/* MPU Type Register */
+#define MPU_TYPE_IREGION_Pos               16                                             /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk               (0xFFul << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos                8                                             /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk               (0xFFul << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos               0                                             /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk              (1ul << MPU_TYPE_SEPARATE_Pos)                 /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register */
+#define MPU_CTRL_PRIVDEFENA_Pos             2                                             /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk            (1ul << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos               1                                             /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk              (1ul << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos                 0                                             /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk                (1ul << MPU_CTRL_ENABLE_Pos)                   /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register */
+#define MPU_RNR_REGION_Pos                  0                                             /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk                 (0xFFul << MPU_RNR_REGION_Pos)                 /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register */
+#define MPU_RBAR_ADDR_Pos                   5                                             /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk                  (0x7FFFFFFul << MPU_RBAR_ADDR_Pos)             /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos                  4                                             /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk                 (1ul << MPU_RBAR_VALID_Pos)                    /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos                 0                                             /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk                (0xFul << MPU_RBAR_REGION_Pos)                 /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register */
+#define MPU_RASR_XN_Pos                    28                                             /*!< MPU RASR: XN Position */
+#define MPU_RASR_XN_Msk                    (1ul << MPU_RASR_XN_Pos)                       /*!< MPU RASR: XN Mask */
+
+#define MPU_RASR_AP_Pos                    24                                             /*!< MPU RASR: AP Position */
+#define MPU_RASR_AP_Msk                    (7ul << MPU_RASR_AP_Pos)                       /*!< MPU RASR: AP Mask */
+
+#define MPU_RASR_TEX_Pos                   19                                             /*!< MPU RASR: TEX Position */
+#define MPU_RASR_TEX_Msk                   (7ul << MPU_RASR_TEX_Pos)                      /*!< MPU RASR: TEX Mask */
+
+#define MPU_RASR_S_Pos                     18                                             /*!< MPU RASR: Shareable bit Position */
+#define MPU_RASR_S_Msk                     (1ul << MPU_RASR_S_Pos)                        /*!< MPU RASR: Shareable bit Mask */
+
+#define MPU_RASR_C_Pos                     17                                             /*!< MPU RASR: Cacheable bit Position */
+#define MPU_RASR_C_Msk                     (1ul << MPU_RASR_C_Pos)                        /*!< MPU RASR: Cacheable bit Mask */
+
+#define MPU_RASR_B_Pos                     16                                             /*!< MPU RASR: Bufferable bit Position */
+#define MPU_RASR_B_Msk                     (1ul << MPU_RASR_B_Pos)                        /*!< MPU RASR: Bufferable bit Mask */
+
+#define MPU_RASR_SRD_Pos                    8                                             /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk                   (0xFFul << MPU_RASR_SRD_Pos)                   /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos                   1                                             /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk                  (0x1Ful << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENA_Pos                     0                                            /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENA_Msk                    (0x1Ful << MPU_RASR_ENA_Pos)                  /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@}*/ /* end of group CMSIS_CM3_MPU */
+#endif
+
+
+/** @addtogroup CMSIS_CM3_CoreDebug CMSIS CM3 Core Debug
+  memory mapped structure for Core Debug Register
+  @{
+ */
+typedef struct
+{
+  __IO uint32_t DHCSR;                        /*!< Offset: 0x00  Debug Halting Control and Status Register    */
+  __O  uint32_t DCRSR;                        /*!< Offset: 0x04  Debug Core Register Selector Register        */
+  __IO uint32_t DCRDR;                        /*!< Offset: 0x08  Debug Core Register Data Register            */
+  __IO uint32_t DEMCR;                        /*!< Offset: 0x0C  Debug Exception and Monitor Control Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register */
+#define CoreDebug_DHCSR_DBGKEY_Pos         16                                             /*!< CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFul << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos     25                                             /*!< CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk     (1ul << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24                                             /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1ul << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos       19                                             /*!< CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk       (1ul << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos        18                                             /*!< CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk        (1ul << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos         17                                             /*!< CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk         (1ul << CoreDebug_DHCSR_S_HALT_Pos)            /*!< CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos       16                                             /*!< CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk       (1ul << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos     5                                             /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk    (1ul << CoreDebug_DHCSR_C_SNAPSTALL_Pos)       /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos      3                                             /*!< CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk     (1ul << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos          2                                             /*!< CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk         (1ul << CoreDebug_DHCSR_C_STEP_Pos)            /*!< CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos          1                                             /*!< CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk         (1ul << CoreDebug_DHCSR_C_HALT_Pos)            /*!< CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos       0                                             /*!< CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1ul << CoreDebug_DHCSR_C_DEBUGEN_Pos)         /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register */
+#define CoreDebug_DCRSR_REGWnR_Pos         16                                             /*!< CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk         (1ul << CoreDebug_DCRSR_REGWnR_Pos)            /*!< CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos          0                                             /*!< CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk         (0x1Ful << CoreDebug_DCRSR_REGSEL_Pos)         /*!< CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register */
+#define CoreDebug_DEMCR_TRCENA_Pos         24                                             /*!< CoreDebug DEMCR: TRCENA Position */
+#define CoreDebug_DEMCR_TRCENA_Msk         (1ul << CoreDebug_DEMCR_TRCENA_Pos)            /*!< CoreDebug DEMCR: TRCENA Mask */
+
+#define CoreDebug_DEMCR_MON_REQ_Pos        19                                             /*!< CoreDebug DEMCR: MON_REQ Position */
+#define CoreDebug_DEMCR_MON_REQ_Msk        (1ul << CoreDebug_DEMCR_MON_REQ_Pos)           /*!< CoreDebug DEMCR: MON_REQ Mask */
+
+#define CoreDebug_DEMCR_MON_STEP_Pos       18                                             /*!< CoreDebug DEMCR: MON_STEP Position */
+#define CoreDebug_DEMCR_MON_STEP_Msk       (1ul << CoreDebug_DEMCR_MON_STEP_Pos)          /*!< CoreDebug DEMCR: MON_STEP Mask */
+
+#define CoreDebug_DEMCR_MON_PEND_Pos       17                                             /*!< CoreDebug DEMCR: MON_PEND Position */
+#define CoreDebug_DEMCR_MON_PEND_Msk       (1ul << CoreDebug_DEMCR_MON_PEND_Pos)          /*!< CoreDebug DEMCR: MON_PEND Mask */
+
+#define CoreDebug_DEMCR_MON_EN_Pos         16                                             /*!< CoreDebug DEMCR: MON_EN Position */
+#define CoreDebug_DEMCR_MON_EN_Msk         (1ul << CoreDebug_DEMCR_MON_EN_Pos)            /*!< CoreDebug DEMCR: MON_EN Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos     10                                             /*!< CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk     (1ul << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_INTERR_Pos       9                                             /*!< CoreDebug DEMCR: VC_INTERR Position */
+#define CoreDebug_DEMCR_VC_INTERR_Msk      (1ul << CoreDebug_DEMCR_VC_INTERR_Pos)         /*!< CoreDebug DEMCR: VC_INTERR Mask */
+
+#define CoreDebug_DEMCR_VC_BUSERR_Pos       8                                             /*!< CoreDebug DEMCR: VC_BUSERR Position */
+#define CoreDebug_DEMCR_VC_BUSERR_Msk      (1ul << CoreDebug_DEMCR_VC_BUSERR_Pos)         /*!< CoreDebug DEMCR: VC_BUSERR Mask */
+
+#define CoreDebug_DEMCR_VC_STATERR_Pos      7                                             /*!< CoreDebug DEMCR: VC_STATERR Position */
+#define CoreDebug_DEMCR_VC_STATERR_Msk     (1ul << CoreDebug_DEMCR_VC_STATERR_Pos)        /*!< CoreDebug DEMCR: VC_STATERR Mask */
+
+#define CoreDebug_DEMCR_VC_CHKERR_Pos       6                                             /*!< CoreDebug DEMCR: VC_CHKERR Position */
+#define CoreDebug_DEMCR_VC_CHKERR_Msk      (1ul << CoreDebug_DEMCR_VC_CHKERR_Pos)         /*!< CoreDebug DEMCR: VC_CHKERR Mask */
+
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos      5                                             /*!< CoreDebug DEMCR: VC_NOCPERR Position */
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk     (1ul << CoreDebug_DEMCR_VC_NOCPERR_Pos)        /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
+
+#define CoreDebug_DEMCR_VC_MMERR_Pos        4                                             /*!< CoreDebug DEMCR: VC_MMERR Position */
+#define CoreDebug_DEMCR_VC_MMERR_Msk       (1ul << CoreDebug_DEMCR_VC_MMERR_Pos)          /*!< CoreDebug DEMCR: VC_MMERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos    0                                             /*!< CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1ul << CoreDebug_DEMCR_VC_CORERESET_Pos)      /*!< CoreDebug DEMCR: VC_CORERESET Mask */
+/*@}*/ /* end of group CMSIS_CM3_CoreDebug */
+
+
+/* Memory mapping of Cortex-M3 Hardware */
+#define SCS_BASE            (0xE000E000)                              /*!< System Control Space Base Address */
+#define ITM_BASE            (0xE0000000)                              /*!< ITM Base Address                  */
+#define CoreDebug_BASE      (0xE000EDF0)                              /*!< Core Debug Base Address           */
+#define SysTick_BASE        (SCS_BASE +  0x0010)                      /*!< SysTick Base Address              */
+#define NVIC_BASE           (SCS_BASE +  0x0100)                      /*!< NVIC Base Address                 */
+#define SCB_BASE            (SCS_BASE +  0x0D00)                      /*!< System Control Block Base Address */
+
+#define InterruptType       ((InterruptType_Type *) SCS_BASE)         /*!< Interrupt Type Register           */
+#define SCB                 ((SCB_Type *)           SCB_BASE)         /*!< SCB configuration struct          */
+#define SysTick             ((SysTick_Type *)       SysTick_BASE)     /*!< SysTick configuration struct      */
+#define NVIC                ((NVIC_Type *)          NVIC_BASE)        /*!< NVIC configuration struct         */
+#define ITM                 ((ITM_Type *)           ITM_BASE)         /*!< ITM configuration struct          */
+#define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE)   /*!< Core Debug configuration struct   */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1)
+  #define MPU_BASE          (SCS_BASE +  0x0D90)                      /*!< Memory Protection Unit            */
+  #define MPU               ((MPU_Type*)            MPU_BASE)         /*!< Memory Protection Unit            */
+#endif
+
+/*@}*/ /* end of group CMSIS_CM3_core_register */
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+ ******************************************************************************/
+
+#if defined ( __CC_ARM   )
+  #define __ASM            __asm                                      /*!< asm keyword for ARM Compiler          */
+  #define __INLINE         __inline                                   /*!< inline keyword for ARM Compiler       */
+
+#elif defined ( __ICCARM__ )
+  #define __ASM           __asm                                       /*!< asm keyword for IAR Compiler          */
+  #define __INLINE        inline                                      /*!< inline keyword for IAR Compiler. Only avaiable in High optimization mode! */
+
+#elif defined   (  __GNUC__  )
+  #define __ASM            __asm                                      /*!< asm keyword for GNU Compiler          */
+  #define __INLINE         inline                                     /*!< inline keyword for GNU Compiler       */
+
+#elif defined   (  __TASKING__  )
+  #define __ASM            __asm                                      /*!< asm keyword for TASKING Compiler      */
+  #define __INLINE         inline                                     /*!< inline keyword for TASKING Compiler   */
+
+#endif
+
+
+/* ###################  Compiler specific Intrinsics  ########################### */
+
+#if defined ( __CC_ARM   ) /*------------------RealView Compiler -----------------*/
+/* ARM armcc specific functions */
+
+#define __enable_fault_irq                __enable_fiq
+#define __disable_fault_irq               __disable_fiq
+
+#define __NOP                             __nop
+#define __WFI                             __wfi
+#define __WFE                             __wfe
+#define __SEV                             __sev
+#define __ISB()                           __isb(0)
+#define __DSB()                           __dsb(0)
+#define __DMB()                           __dmb(0)
+#define __REV                             __rev
+#define __RBIT                            __rbit
+#define __LDREXB(ptr)                     ((unsigned char ) __ldrex(ptr))
+#define __LDREXH(ptr)                     ((unsigned short) __ldrex(ptr))
+#define __LDREXW(ptr)                     ((unsigned int  ) __ldrex(ptr))
+#define __STREXB(value, ptr)              __strex(value, ptr)
+#define __STREXH(value, ptr)              __strex(value, ptr)
+#define __STREXW(value, ptr)              __strex(value, ptr)
+
+
+/* intrinsic unsigned long long __ldrexd(volatile void *ptr) */
+/* intrinsic int __strexd(unsigned long long val, volatile void *ptr) */
+/* intrinsic void __enable_irq();     */
+/* intrinsic void __disable_irq();    */
+
+
+/**
+ * @brief  Return the Process Stack Pointer
+ *
+ * @return ProcessStackPointer
+ *
+ * Return the actual process stack pointer
+ */
+extern uint32_t __get_PSP(void);
+
+/**
+ * @brief  Set the Process Stack Pointer
+ *
+ * @param  topOfProcStack  Process Stack Pointer
+ *
+ * Assign the value ProcessStackPointer to the MSP 
+ * (process stack pointer) Cortex processor register
+ */
+extern void __set_PSP(uint32_t topOfProcStack);
+
+/**
+ * @brief  Return the Main Stack Pointer
+ *
+ * @return Main Stack Pointer
+ *
+ * Return the current value of the MSP (main stack pointer)
+ * Cortex processor register
+ */
+extern uint32_t __get_MSP(void);
+
+/**
+ * @brief  Set the Main Stack Pointer
+ *
+ * @param  topOfMainStack  Main Stack Pointer
+ *
+ * Assign the value mainStackPointer to the MSP 
+ * (main stack pointer) Cortex processor register
+ */
+extern void __set_MSP(uint32_t topOfMainStack);
+
+/**
+ * @brief  Reverse byte order in unsigned short value
+ *
+ * @param   value  value to reverse
+ * @return         reversed value
+ *
+ * Reverse byte order in unsigned short value
+ */
+extern uint32_t __REV16(uint16_t value);
+
+/**
+ * @brief  Reverse byte order in signed short value with sign extension to integer
+ *
+ * @param   value  value to reverse
+ * @return         reversed value
+ *
+ * Reverse byte order in signed short value with sign extension to integer
+ */
+extern int32_t __REVSH(int16_t value);
+
+
+#if (__ARMCC_VERSION < 400000)
+
+/**
+ * @brief  Remove the exclusive lock created by ldrex
+ *
+ * Removes the exclusive lock which is created by ldrex.
+ */
+extern void __CLREX(void);
+
+/**
+ * @brief  Return the Base Priority value
+ *
+ * @return BasePriority
+ *
+ * Return the content of the base priority register
+ */
+extern uint32_t __get_BASEPRI(void);
+
+/**
+ * @brief  Set the Base Priority value
+ *
+ * @param  basePri  BasePriority
+ *
+ * Set the base priority register
+ */
+extern void __set_BASEPRI(uint32_t basePri);
+
+/**
+ * @brief  Return the Priority Mask value
+ *
+ * @return PriMask
+ *
+ * Return state of the priority mask bit from the priority mask register
+ */
+extern uint32_t __get_PRIMASK(void);
+
+/**
+ * @brief  Set the Priority Mask value
+ *
+ * @param   priMask  PriMask
+ *
+ * Set the priority mask bit in the priority mask register
+ */
+extern void __set_PRIMASK(uint32_t priMask);
+
+/**
+ * @brief  Return the Fault Mask value
+ *
+ * @return FaultMask
+ *
+ * Return the content of the fault mask register
+ */
+extern uint32_t __get_FAULTMASK(void);
+
+/**
+ * @brief  Set the Fault Mask value
+ *
+ * @param  faultMask faultMask value
+ *
+ * Set the fault mask register
+ */
+extern void __set_FAULTMASK(uint32_t faultMask);
+
+/**
+ * @brief  Return the Control Register value
+ * 
+ * @return Control value
+ *
+ * Return the content of the control register
+ */
+extern uint32_t __get_CONTROL(void);
+
+/**
+ * @brief  Set the Control Register value
+ *
+ * @param  control  Control value
+ *
+ * Set the control register
+ */
+extern void __set_CONTROL(uint32_t control);
+
+#else  /* (__ARMCC_VERSION >= 400000)  */
+
+/**
+ * @brief  Remove the exclusive lock created by ldrex
+ *
+ * Removes the exclusive lock which is created by ldrex.
+ */
+#define __CLREX                           __clrex
+
+/**
+ * @brief  Return the Base Priority value
+ *
+ * @return BasePriority
+ *
+ * Return the content of the base priority register
+ */
+static __INLINE uint32_t  __get_BASEPRI(void)
+{
+  register uint32_t __regBasePri         __ASM("basepri");
+  return(__regBasePri);
+}
+
+/**
+ * @brief  Set the Base Priority value
+ *
+ * @param  basePri  BasePriority
+ *
+ * Set the base priority register
+ */
+static __INLINE void __set_BASEPRI(uint32_t basePri)
+{
+  register uint32_t __regBasePri         __ASM("basepri");
+  __regBasePri = (basePri & 0xff);
+}
+
+/**
+ * @brief  Return the Priority Mask value
+ *
+ * @return PriMask
+ *
+ * Return state of the priority mask bit from the priority mask register
+ */
+static __INLINE uint32_t __get_PRIMASK(void)
+{
+  register uint32_t __regPriMask         __ASM("primask");
+  return(__regPriMask);
+}
+
+/**
+ * @brief  Set the Priority Mask value
+ *
+ * @param  priMask  PriMask
+ *
+ * Set the priority mask bit in the priority mask register
+ */
+static __INLINE void __set_PRIMASK(uint32_t priMask)
+{
+  register uint32_t __regPriMask         __ASM("primask");
+  __regPriMask = (priMask);
+}
+
+/**
+ * @brief  Return the Fault Mask value
+ *
+ * @return FaultMask
+ *
+ * Return the content of the fault mask register
+ */
+static __INLINE uint32_t __get_FAULTMASK(void)
+{
+  register uint32_t __regFaultMask       __ASM("faultmask");
+  return(__regFaultMask);
+}
+
+/**
+ * @brief  Set the Fault Mask value
+ *
+ * @param  faultMask  faultMask value
+ *
+ * Set the fault mask register
+ */
+static __INLINE void __set_FAULTMASK(uint32_t faultMask)
+{
+  register uint32_t __regFaultMask       __ASM("faultmask");
+  __regFaultMask = (faultMask & 1);
+}
+
+/**
+ * @brief  Return the Control Register value
+ * 
+ * @return Control value
+ *
+ * Return the content of the control register
+ */
+static __INLINE uint32_t __get_CONTROL(void)
+{
+  register uint32_t __regControl         __ASM("control");
+  return(__regControl);
+}
+
+/**
+ * @brief  Set the Control Register value
+ *
+ * @param  control  Control value
+ *
+ * Set the control register
+ */
+static __INLINE void __set_CONTROL(uint32_t control)
+{
+  register uint32_t __regControl         __ASM("control");
+  __regControl = control;
+}
+
+#endif /* __ARMCC_VERSION  */ 
+
+
+
+#elif (defined (__ICCARM__)) /*------------------ ICC Compiler -------------------*/
+/* IAR iccarm specific functions */
+
+#define __enable_irq                              __enable_interrupt        /*!< global Interrupt enable */
+#define __disable_irq                             __disable_interrupt       /*!< global Interrupt disable */
+
+static __INLINE void __enable_fault_irq()         { __ASM ("cpsie f"); }
+static __INLINE void __disable_fault_irq()        { __ASM ("cpsid f"); }
+
+#define __NOP                                     __no_operation            /*!< no operation intrinsic in IAR Compiler */ 
+static __INLINE  void __WFI()                     { __ASM ("wfi"); }
+static __INLINE  void __WFE()                     { __ASM ("wfe"); }
+static __INLINE  void __SEV()                     { __ASM ("sev"); }
+static __INLINE  void __CLREX()                   { __ASM ("clrex"); }
+
+/* intrinsic void __ISB(void)                                     */
+/* intrinsic void __DSB(void)                                     */
+/* intrinsic void __DMB(void)                                     */
+/* intrinsic void __set_PRIMASK();                                */
+/* intrinsic void __get_PRIMASK();                                */
+/* intrinsic void __set_FAULTMASK();                              */
+/* intrinsic void __get_FAULTMASK();                              */
+/* intrinsic uint32_t __REV(uint32_t value);                      */
+/* intrinsic uint32_t __REVSH(uint32_t value);                    */
+/* intrinsic unsigned long __STREX(unsigned long, unsigned long); */
+/* intrinsic unsigned long __LDREX(unsigned long *);              */
+
+
+/**
+ * @brief  Return the Process Stack Pointer
+ *
+ * @return ProcessStackPointer
+ *
+ * Return the actual process stack pointer
+ */
+extern uint32_t __get_PSP(void);
+
+/**
+ * @brief  Set the Process Stack Pointer
+ *
+ * @param  topOfProcStack  Process Stack Pointer
+ *
+ * Assign the value ProcessStackPointer to the MSP 
+ * (process stack pointer) Cortex processor register
+ */
+extern void __set_PSP(uint32_t topOfProcStack);
+
+/**
+ * @brief  Return the Main Stack Pointer
+ *
+ * @return Main Stack Pointer
+ *
+ * Return the current value of the MSP (main stack pointer)
+ * Cortex processor register
+ */
+extern uint32_t __get_MSP(void);
+
+/**
+ * @brief  Set the Main Stack Pointer
+ *
+ * @param  topOfMainStack  Main Stack Pointer
+ *
+ * Assign the value mainStackPointer to the MSP 
+ * (main stack pointer) Cortex processor register
+ */
+extern void __set_MSP(uint32_t topOfMainStack);
+
+/**
+ * @brief  Reverse byte order in unsigned short value
+ *
+ * @param  value  value to reverse
+ * @return        reversed value
+ *
+ * Reverse byte order in unsigned short value
+ */
+extern uint32_t __REV16(uint16_t value);
+
+/**
+ * @brief  Reverse bit order of value
+ *
+ * @param  value  value to reverse
+ * @return        reversed value
+ *
+ * Reverse bit order of value
+ */
+extern uint32_t __RBIT(uint32_t value);
+
+/**
+ * @brief  LDR Exclusive (8 bit)
+ *
+ * @param  *addr  address pointer
+ * @return        value of (*address)
+ *
+ * Exclusive LDR command for 8 bit values)
+ */
+extern uint8_t __LDREXB(uint8_t *addr);
+
+/**
+ * @brief  LDR Exclusive (16 bit)
+ *
+ * @param  *addr  address pointer
+ * @return        value of (*address)
+ *
+ * Exclusive LDR command for 16 bit values
+ */
+extern uint16_t __LDREXH(uint16_t *addr);
+
+/**
+ * @brief  LDR Exclusive (32 bit)
+ *
+ * @param  *addr  address pointer
+ * @return        value of (*address)
+ *
+ * Exclusive LDR command for 32 bit values
+ */
+extern uint32_t __LDREXW(uint32_t *addr);
+
+/**
+ * @brief  STR Exclusive (8 bit)
+ *
+ * @param  value  value to store
+ * @param  *addr  address pointer
+ * @return        successful / failed
+ *
+ * Exclusive STR command for 8 bit values
+ */
+extern uint32_t __STREXB(uint8_t value, uint8_t *addr);
+
+/**
+ * @brief  STR Exclusive (16 bit)
+ *
+ * @param  value  value to store
+ * @param  *addr  address pointer
+ * @return        successful / failed
+ *
+ * Exclusive STR command for 16 bit values
+ */
+extern uint32_t __STREXH(uint16_t value, uint16_t *addr);
+
+/**
+ * @brief  STR Exclusive (32 bit)
+ *
+ * @param  value  value to store
+ * @param  *addr  address pointer
+ * @return        successful / failed
+ *
+ * Exclusive STR command for 32 bit values
+ */
+extern uint32_t __STREXW(uint32_t value, uint32_t *addr);
+
+
+
+#elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/
+/* GNU gcc specific functions */
+
+static __INLINE void __enable_irq()               { __ASM volatile ("cpsie i"); }
+static __INLINE void __disable_irq()              { __ASM volatile ("cpsid i"); }
+
+static __INLINE void __enable_fault_irq()         { __ASM volatile ("cpsie f"); }
+static __INLINE void __disable_fault_irq()        { __ASM volatile ("cpsid f"); }
+
+static __INLINE void __NOP()                      { __ASM volatile ("nop"); }
+static __INLINE void __WFI()                      { __ASM volatile ("wfi"); }
+static __INLINE void __WFE()                      { __ASM volatile ("wfe"); }
+static __INLINE void __SEV()                      { __ASM volatile ("sev"); }
+static __INLINE void __ISB()                      { __ASM volatile ("isb"); }
+static __INLINE void __DSB()                      { __ASM volatile ("dsb"); }
+static __INLINE void __DMB()                      { __ASM volatile ("dmb"); }
+static __INLINE void __CLREX()                    { __ASM volatile ("clrex"); }
+
+
+/**
+ * @brief  Return the Process Stack Pointer
+ *
+ * @return ProcessStackPointer
+ *
+ * Return the actual process stack pointer
+ */
+extern uint32_t __get_PSP(void);
+
+/**
+ * @brief  Set the Process Stack Pointer
+ *
+ * @param  topOfProcStack  Process Stack Pointer
+ *
+ * Assign the value ProcessStackPointer to the MSP 
+ * (process stack pointer) Cortex processor register
+ */
+extern void __set_PSP(uint32_t topOfProcStack);
+
+/**
+ * @brief  Return the Main Stack Pointer
+ *
+ * @return Main Stack Pointer
+ *
+ * Return the current value of the MSP (main stack pointer)
+ * Cortex processor register
+ */
+extern uint32_t __get_MSP(void);
+
+/**
+ * @brief  Set the Main Stack Pointer
+ *
+ * @param  topOfMainStack  Main Stack Pointer
+ *
+ * Assign the value mainStackPointer to the MSP 
+ * (main stack pointer) Cortex processor register
+ */
+extern void __set_MSP(uint32_t topOfMainStack);
+
+/**
+ * @brief  Return the Base Priority value
+ *
+ * @return BasePriority
+ *
+ * Return the content of the base priority register
+ */
+extern uint32_t __get_BASEPRI(void);
+
+/**
+ * @brief  Set the Base Priority value
+ *
+ * @param  basePri  BasePriority
+ *
+ * Set the base priority register
+ */
+extern void __set_BASEPRI(uint32_t basePri);
+
+/**
+ * @brief  Return the Priority Mask value
+ *
+ * @return PriMask
+ *
+ * Return state of the priority mask bit from the priority mask register
+ */
+extern uint32_t  __get_PRIMASK(void);
+
+/**
+ * @brief  Set the Priority Mask value
+ *
+ * @param  priMask  PriMask
+ *
+ * Set the priority mask bit in the priority mask register
+ */
+extern void __set_PRIMASK(uint32_t priMask);
+
+/**
+ * @brief  Return the Fault Mask value
+ *
+ * @return FaultMask
+ *
+ * Return the content of the fault mask register
+ */
+extern uint32_t __get_FAULTMASK(void);
+
+/**
+ * @brief  Set the Fault Mask value
+ *
+ * @param  faultMask  faultMask value
+ *
+ * Set the fault mask register
+ */
+extern void __set_FAULTMASK(uint32_t faultMask);
+
+/**
+ * @brief  Return the Control Register value
+* 
+*  @return Control value
+ *
+ * Return the content of the control register
+ */
+extern uint32_t __get_CONTROL(void);
+
+/**
+ * @brief  Set the Control Register value
+ *
+ * @param  control  Control value
+ *
+ * Set the control register
+ */
+extern void __set_CONTROL(uint32_t control);
+
+/**
+ * @brief  Reverse byte order in integer value
+ *
+ * @param  value  value to reverse
+ * @return        reversed value
+ *
+ * Reverse byte order in integer value
+ */
+extern uint32_t __REV(uint32_t value);
+
+/**
+ * @brief  Reverse byte order in unsigned short value
+ *
+ * @param  value  value to reverse
+ * @return        reversed value
+ *
+ * Reverse byte order in unsigned short value
+ */
+extern uint32_t __REV16(uint16_t value);
+
+/**
+ * @brief  Reverse byte order in signed short value with sign extension to integer
+ *
+ * @param  value  value to reverse
+ * @return        reversed value
+ *
+ * Reverse byte order in signed short value with sign extension to integer
+ */
+extern int32_t __REVSH(int16_t value);
+
+/**
+ * @brief  Reverse bit order of value
+ *
+ * @param  value  value to reverse
+ * @return        reversed value
+ *
+ * Reverse bit order of value
+ */
+extern uint32_t __RBIT(uint32_t value);
+
+/**
+ * @brief  LDR Exclusive (8 bit)
+ *
+ * @param  *addr  address pointer
+ * @return        value of (*address)
+ *
+ * Exclusive LDR command for 8 bit value
+ */
+extern uint8_t __LDREXB(uint8_t *addr);
+
+/**
+ * @brief  LDR Exclusive (16 bit)
+ *
+ * @param  *addr  address pointer
+ * @return        value of (*address)
+ *
+ * Exclusive LDR command for 16 bit values
+ */
+extern uint16_t __LDREXH(uint16_t *addr);
+
+/**
+ * @brief  LDR Exclusive (32 bit)
+ *
+ * @param  *addr  address pointer
+ * @return        value of (*address)
+ *
+ * Exclusive LDR command for 32 bit values
+ */
+extern uint32_t __LDREXW(uint32_t *addr);
+
+/**
+ * @brief  STR Exclusive (8 bit)
+ *
+ * @param  value  value to store
+ * @param  *addr  address pointer
+ * @return        successful / failed
+ *
+ * Exclusive STR command for 8 bit values
+ */
+extern uint32_t __STREXB(uint8_t value, uint8_t *addr);
+
+/**
+ * @brief  STR Exclusive (16 bit)
+ *
+ * @param  value  value to store
+ * @param  *addr  address pointer
+ * @return        successful / failed
+ *
+ * Exclusive STR command for 16 bit values
+ */
+extern uint32_t __STREXH(uint16_t value, uint16_t *addr);
+
+/**
+ * @brief  STR Exclusive (32 bit)
+ *
+ * @param  value  value to store
+ * @param  *addr  address pointer
+ * @return        successful / failed
+ *
+ * Exclusive STR command for 32 bit values
+ */
+extern uint32_t __STREXW(uint32_t value, uint32_t *addr);
+
+
+#elif (defined (__TASKING__)) /*------------------ TASKING Compiler ---------------------*/
+/* TASKING carm specific functions */
+
+/*
+ * The CMSIS functions have been implemented as intrinsics in the compiler.
+ * Please use "carm -?i" to get an up to date list of all instrinsics,
+ * Including the CMSIS ones.
+ */
+
+#endif
+
+
+/** @addtogroup CMSIS_CM3_Core_FunctionInterface CMSIS CM3 Core Function Interface
+  Core  Function Interface containing:
+  - Core NVIC Functions
+  - Core SysTick Functions
+  - Core Reset Functions
+*/
+/*@{*/
+
+/* ##########################   NVIC functions  #################################### */
+
+/**
+ * @brief  Set the Priority Grouping in NVIC Interrupt Controller
+ *
+ * @param  PriorityGroup is priority grouping field
+ *
+ * Set the priority grouping field using the required unlock sequence.
+ * The parameter priority_grouping is assigned to the field 
+ * SCB->AIRCR [10:8] PRIGROUP field. Only values from 0..7 are used.
+ * In case of a conflict between priority grouping and available
+ * priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+ */
+static __INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+{
+  uint32_t reg_value;
+  uint32_t PriorityGroupTmp = (PriorityGroup & 0x07);                         /* only values 0..7 are used          */
+  
+  reg_value  =  SCB->AIRCR;                                                   /* read old register configuration    */
+  reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk);             /* clear bits to change               */
+  reg_value  =  (reg_value                       |
+                (0x5FA << SCB_AIRCR_VECTKEY_Pos) | 
+                (PriorityGroupTmp << 8));                                     /* Insert write key and priorty group */
+  SCB->AIRCR =  reg_value;
+}
+
+/**
+ * @brief  Get the Priority Grouping from NVIC Interrupt Controller
+ *
+ * @return priority grouping field 
+ *
+ * Get the priority grouping from NVIC Interrupt Controller.
+ * priority grouping is SCB->AIRCR [10:8] PRIGROUP field.
+ */
+static __INLINE uint32_t NVIC_GetPriorityGrouping(void)
+{
+  return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos);   /* read priority grouping field */
+}
+
+/**
+ * @brief  Enable Interrupt in NVIC Interrupt Controller
+ *
+ * @param  IRQn   The positive number of the external interrupt to enable
+ *
+ * Enable a device specific interupt in the NVIC interrupt controller.
+ * The interrupt number cannot be a negative value.
+ */
+static __INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+  NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* enable interrupt */
+}
+
+/**
+ * @brief  Disable the interrupt line for external interrupt specified
+ * 
+ * @param  IRQn   The positive number of the external interrupt to disable
+ * 
+ * Disable a device specific interupt in the NVIC interrupt controller.
+ * The interrupt number cannot be a negative value.
+ */
+static __INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+  NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */
+}
+
+/**
+ * @brief  Read the interrupt pending bit for a device specific interrupt source
+ * 
+ * @param  IRQn    The number of the device specifc interrupt
+ * @return         1 = interrupt pending, 0 = interrupt not pending
+ *
+ * Read the pending register in NVIC and return 1 if its status is pending, 
+ * otherwise it returns 0
+ */
+static __INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+  return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */
+}
+
+/**
+ * @brief  Set the pending bit for an external interrupt
+ * 
+ * @param  IRQn    The number of the interrupt for set pending
+ *
+ * Set the pending bit for the specified interrupt.
+ * The interrupt number cannot be a negative value.
+ */
+static __INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+  NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */
+}
+
+/**
+ * @brief  Clear the pending bit for an external interrupt
+ *
+ * @param  IRQn    The number of the interrupt for clear pending
+ *
+ * Clear the pending bit for the specified interrupt. 
+ * The interrupt number cannot be a negative value.
+ */
+static __INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+  NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
+}
+
+/**
+ * @brief  Read the active bit for an external interrupt
+ *
+ * @param  IRQn    The number of the interrupt for read active bit
+ * @return         1 = interrupt active, 0 = interrupt not active
+ *
+ * Read the active register in NVIC and returns 1 if its status is active, 
+ * otherwise it returns 0.
+ */
+static __INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
+{
+  return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */
+}
+
+/**
+ * @brief  Set the priority for an interrupt
+ *
+ * @param  IRQn      The number of the interrupt for set priority
+ * @param  priority  The priority to set
+ *
+ * Set the priority for the specified interrupt. The interrupt 
+ * number can be positive to specify an external (device specific) 
+ * interrupt, or negative to specify an internal (core) interrupt.
+ *
+ * Note: The priority cannot be set for every core interrupt.
+ */
+static __INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+  if(IRQn < 0) {
+    SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M3 System Interrupts */
+  else {
+    NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff);    }        /* set Priority for device specific Interrupts  */
+}
+
+/**
+ * @brief  Read the priority for an interrupt
+ *
+ * @param  IRQn      The number of the interrupt for get priority
+ * @return           The priority for the interrupt
+ *
+ * Read the priority for the specified interrupt. The interrupt 
+ * number can be positive to specify an external (device specific) 
+ * interrupt, or negative to specify an internal (core) interrupt.
+ *
+ * The returned priority value is automatically aligned to the implemented
+ * priority bits of the microcontroller.
+ *
+ * Note: The priority cannot be set for every core interrupt.
+ */
+static __INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+  if(IRQn < 0) {
+    return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS)));  } /* get priority for Cortex-M3 system interrupts */
+  else {
+    return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)]           >> (8 - __NVIC_PRIO_BITS)));  } /* get priority for device specific interrupts  */
+}
+
+
+/**
+ * @brief  Encode the priority for an interrupt
+ *
+ * @param  PriorityGroup    The used priority group
+ * @param  PreemptPriority  The preemptive priority value (starting from 0)
+ * @param  SubPriority      The sub priority value (starting from 0)
+ * @return                  The encoded priority for the interrupt
+ *
+ * Encode the priority for an interrupt with the given priority group,
+ * preemptive priority value and sub priority value.
+ * In case of a conflict between priority grouping and available
+ * priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set.
+ *
+ * The returned priority value can be used for NVIC_SetPriority(...) function
+ */
+static __INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & 0x07);          /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
+  SubPriorityBits     = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
+ 
+  return (
+           ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) |
+           ((SubPriority     & ((1 << (SubPriorityBits    )) - 1)))
+         );
+}
+
+
+/**
+ * @brief  Decode the priority of an interrupt
+ *
+ * @param  Priority           The priority for the interrupt
+ * @param  PriorityGroup      The used priority group
+ * @param  pPreemptPriority   The preemptive priority value (starting from 0)
+ * @param  pSubPriority       The sub priority value (starting from 0)
+ *
+ * Decode an interrupt priority value with the given priority group to 
+ * preemptive priority value and sub priority value.
+ * In case of a conflict between priority grouping and available
+ * priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set.
+ *
+ * The priority value can be retrieved with NVIC_GetPriority(...) function
+ */
+static __INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & 0x07);          /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
+  SubPriorityBits     = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
+  
+  *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1);
+  *pSubPriority     = (Priority                   ) & ((1 << (SubPriorityBits    )) - 1);
+}
+
+
+
+/* ##################################    SysTick function  ############################################ */
+
+#if (!defined (__Vendor_SysTickConfig)) || (__Vendor_SysTickConfig == 0)
+
+/**
+ * @brief  Initialize and start the SysTick counter and its interrupt.
+ *
+ * @param   ticks   number of ticks between two interrupts
+ * @return  1 = failed, 0 = successful
+ *
+ * Initialise the system tick timer and its interrupt and start the
+ * system tick timer / counter in free running mode to generate 
+ * periodical interrupts.
+ */
+static __INLINE uint32_t SysTick_Config(uint32_t ticks)
+{ 
+  if (ticks > SysTick_LOAD_RELOAD_Msk)  return (1);            /* Reload value impossible */
+                                                               
+  SysTick->LOAD  = (ticks & SysTick_LOAD_RELOAD_Msk) - 1;      /* set reload register */
+  NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1);  /* set Priority for Cortex-M0 System Interrupts */
+  SysTick->VAL   = 0;                                          /* Load the SysTick Counter Value */
+  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk | 
+                   SysTick_CTRL_TICKINT_Msk   | 
+                   SysTick_CTRL_ENABLE_Msk;                    /* Enable SysTick IRQ and SysTick Timer */
+  return (0);                                                  /* Function successful */
+}
+
+#endif
+
+
+
+
+/* ##################################    Reset function  ############################################ */
+
+/**
+ * @brief  Initiate a system reset request.
+ *
+ * Initiate a system reset request to reset the MCU
+ */
+static __INLINE void NVIC_SystemReset(void)
+{
+  SCB->AIRCR  = ((0x5FA << SCB_AIRCR_VECTKEY_Pos)      | 
+                 (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | 
+                 SCB_AIRCR_SYSRESETREQ_Msk);                   /* Keep priority group unchanged */
+  __DSB();                                                     /* Ensure completion of memory access */              
+  while(1);                                                    /* wait until reset */
+}
+
+/*@}*/ /* end of group CMSIS_CM3_Core_FunctionInterface */
+
+
+
+/* ##################################### Debug In/Output function ########################################### */
+
+/** @addtogroup CMSIS_CM3_CoreDebugInterface CMSIS CM3 Core Debug Interface
+  Core Debug Interface containing:
+  - Core Debug Receive / Transmit Functions
+  - Core Debug Defines
+  - Core Debug Variables
+*/
+/*@{*/
+
+extern volatile int ITM_RxBuffer;                    /*!< variable to receive characters                             */
+#define             ITM_RXBUFFER_EMPTY    0x5AA55AA5 /*!< value identifying ITM_RxBuffer is ready for next character */
+
+
+/**
+ * @brief  Outputs a character via the ITM channel 0
+ *
+ * @param  ch   character to output
+ * @return      character to output
+ *
+ * The function outputs a character via the ITM channel 0. 
+ * The function returns when no debugger is connected that has booked the output.  
+ * It is blocking when a debugger is connected, but the previous character send is not transmitted. 
+ */
+static __INLINE uint32_t ITM_SendChar (uint32_t ch)
+{
+  if ((CoreDebug->DEMCR & CoreDebug_DEMCR_TRCENA_Msk)  &&      /* Trace enabled */
+      (ITM->TCR & ITM_TCR_ITMENA_Msk)                  &&      /* ITM enabled */
+      (ITM->TER & (1ul << 0)        )                    )     /* ITM Port #0 enabled */
+  {
+    while (ITM->PORT[0].u32 == 0);
+    ITM->PORT[0].u8 = (uint8_t) ch;
+  }  
+  return (ch);
+}
+
+
+/**
+ * @brief  Inputs a character via variable ITM_RxBuffer
+ *
+ * @return      received character, -1 = no character received
+ *
+ * The function inputs a character via variable ITM_RxBuffer. 
+ * The function returns when no debugger is connected that has booked the output.  
+ * It is blocking when a debugger is connected, but the previous character send is not transmitted. 
+ */
+static __INLINE int ITM_ReceiveChar (void) {
+  int ch = -1;                               /* no character available */
+
+  if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
+    ch = ITM_RxBuffer;
+    ITM_RxBuffer = ITM_RXBUFFER_EMPTY;       /* ready for next character */
+  }
+  
+  return (ch); 
+}
+
+
+/**
+ * @brief  Check if a character via variable ITM_RxBuffer is available
+ *
+ * @return      1 = character available, 0 = no character available
+ *
+ * The function checks  variable ITM_RxBuffer whether a character is available or not. 
+ * The function returns '1' if a character is available and '0' if no character is available. 
+ */
+static __INLINE int ITM_CheckChar (void) {
+
+  if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
+    return (0);                                 /* no character available */
+  } else {
+    return (1);                                 /*    character available */
+  }
+}
+
+/*@}*/ /* end of group CMSIS_CM3_core_DebugInterface */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+/*@}*/ /* end of group CMSIS_CM3_core_definitions */
+
+#endif /* __CM3_CORE_H__ */
+
+/*lint -restore */
diff --git a/STM32_4路称重_Git提交精简工程/src/CMSIS/stm32f10x.h b/STM32_4路称重_Git提交精简工程/src/CMSIS/stm32f10x.h
new file mode 100755
index 0000000..af0c7c9
--- /dev/null
+++ b/STM32_4路称重_Git提交精简工程/src/CMSIS/stm32f10x.h
@@ -0,0 +1,8336 @@
+/**
+  ******************************************************************************
+  * @file    stm32f10x.h
+  * @author  MCD Application Team
+  * @version V3.5.0
+  * @date    11-March-2011
+  * @brief   CMSIS Cortex-M3 Device Peripheral Access Layer Header File. 
+  *          This file contains all the peripheral register's definitions, bits 
+  *          definitions and memory mapping for STM32F10x Connectivity line, 
+  *          High density, High density value line, Medium density, 
+  *          Medium density Value line, Low density, Low density Value line 
+  *          and XL-density devices.
+  *
+  *          The file is the unique include file that the application programmer
+  *          is using in the C source code, usually in main.c. This file contains:
+  *           - Configuration section that allows to select:
+  *              - The device used in the target application
+  *              - To use or not the peripheral�s drivers in application code(i.e. 
+  *                code will be based on direct access to peripheral�s registers 
+  *                rather than drivers API), this option is controlled by 
+  *                "#define USE_STDPERIPH_DRIVER"
+  *              - To change few application-specific parameters such as the HSE 
+  *                crystal frequency
+  *           - Data structures and the address mapping for all peripherals
+  *           - Peripheral's registers declarations and bits definition
+  *           - Macros to access peripheral�s registers hardware
+  *
+  ******************************************************************************
+  * @attention
+  *
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+  *
+  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
+  ******************************************************************************
+  */
+
+/** @addtogroup CMSIS
+  * @{
+  */
+
+/** @addtogroup stm32f10x
+  * @{
+  */
+    
+#ifndef __STM32F10x_H
+#define __STM32F10x_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif 
+  
+/** @addtogroup Library_configuration_section
+  * @{
+  */
+  
+/* Uncomment the line below according to the target STM32 device used in your
+   application 
+  */
+
+#if !defined (STM32F10X_LD) && !defined (STM32F10X_LD_VL) && !defined (STM32F10X_MD) && !defined (STM32F10X_MD_VL) && !defined (STM32F10X_HD) && !defined (STM32F10X_HD_VL) && !defined (STM32F10X_XL) && !defined (STM32F10X_CL) 
+  /* #define STM32F10X_LD */     /*!< STM32F10X_LD: STM32 Low density devices */
+  /* #define STM32F10X_LD_VL */  /*!< STM32F10X_LD_VL: STM32 Low density Value Line devices */  
+  /* #define STM32F10X_MD */     /*!< STM32F10X_MD: STM32 Medium density devices */
+  /* #define STM32F10X_MD_VL */  /*!< STM32F10X_MD_VL: STM32 Medium density Value Line devices */  
+  /* #define STM32F10X_HD */     /*!< STM32F10X_HD: STM32 High density devices */
+  /* #define STM32F10X_HD_VL */  /*!< STM32F10X_HD_VL: STM32 High density value line devices */  
+  /* #define STM32F10X_XL */     /*!< STM32F10X_XL: STM32 XL-density devices */
+  /* #define STM32F10X_CL */     /*!< STM32F10X_CL: STM32 Connectivity line devices */
+#endif
+/*  Tip: To avoid modifying this file each time you need to switch between these
+        devices, you can define the device in your toolchain compiler preprocessor.
+
+ - Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers
+   where the Flash memory density ranges between 16 and 32 Kbytes.
+ - Low-density value line devices are STM32F100xx microcontrollers where the Flash
+   memory density ranges between 16 and 32 Kbytes.
+ - Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers
+   where the Flash memory density ranges between 64 and 128 Kbytes.
+ - Medium-density value line devices are STM32F100xx microcontrollers where the 
+   Flash memory density ranges between 64 and 128 Kbytes.   
+ - High-density devices are STM32F101xx and STM32F103xx microcontrollers where
+   the Flash memory density ranges between 256 and 512 Kbytes.
+ - High-density value line devices are STM32F100xx microcontrollers where the 
+   Flash memory density ranges between 256 and 512 Kbytes.   
+ - XL-density devices are STM32F101xx and STM32F103xx microcontrollers where
+   the Flash memory density ranges between 512 and 1024 Kbytes.
+ - Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers.
+  */
+
+#if !defined (STM32F10X_LD) && !defined (STM32F10X_LD_VL) && !defined (STM32F10X_MD) && !defined (STM32F10X_MD_VL) && !defined (STM32F10X_HD) && !defined (STM32F10X_HD_VL) && !defined (STM32F10X_XL) && !defined (STM32F10X_CL)
+ #error "Please select first the target STM32F10x device used in your application (in stm32f10x.h file)"
+#endif
+
+#if !defined  USE_STDPERIPH_DRIVER
+/**
+ * @brief Comment the line below if you will not use the peripherals drivers.
+   In this case, these drivers will not be included and the application code will 
+   be based on direct access to peripherals registers 
+   */
+  /*#define USE_STDPERIPH_DRIVER*/
+#endif
+
+/**
+ * @brief In the following line adjust the value of External High Speed oscillator (HSE)
+   used in your application 
+   
+   Tip: To avoid modifying this file each time you need to use different HSE, you
+        can define the HSE value in your toolchain compiler preprocessor.
+  */           
+#if !defined  HSE_VALUE
+ #ifdef STM32F10X_CL   
+  #define HSE_VALUE    ((uint32_t)25000000) /*!< Value of the External oscillator in Hz */
+ #else 
+  #define HSE_VALUE    ((uint32_t)8000000) /*!< Value of the External oscillator in Hz */
+ #endif /* STM32F10X_CL */
+#endif /* HSE_VALUE */
+
+
+/**
+ * @brief In the following line adjust the External High Speed oscillator (HSE) Startup 
+   Timeout value 
+   */
+#define HSE_STARTUP_TIMEOUT   ((uint16_t)0x0500) /*!< Time out for HSE start up */
+
+#define HSI_VALUE    ((uint32_t)8000000) /*!< Value of the Internal oscillator in Hz*/
+
+/**
+ * @brief STM32F10x Standard Peripheral Library version number
+   */
+#define __STM32F10X_STDPERIPH_VERSION_MAIN   (0x03) /*!< [31:24] main version */                                  
+#define __STM32F10X_STDPERIPH_VERSION_SUB1   (0x05) /*!< [23:16] sub1 version */
+#define __STM32F10X_STDPERIPH_VERSION_SUB2   (0x00) /*!< [15:8]  sub2 version */
+#define __STM32F10X_STDPERIPH_VERSION_RC     (0x00) /*!< [7:0]  release candidate */ 
+#define __STM32F10X_STDPERIPH_VERSION       ( (__STM32F10X_STDPERIPH_VERSION_MAIN << 24)\
+                                             |(__STM32F10X_STDPERIPH_VERSION_SUB1 << 16)\
+                                             |(__STM32F10X_STDPERIPH_VERSION_SUB2 << 8)\
+                                             |(__STM32F10X_STDPERIPH_VERSION_RC))
+
+/**
+  * @}
+  */
+
+/** @addtogroup Configuration_section_for_CMSIS
+  * @{
+  */
+
+/**
+ * @brief Configuration of the Cortex-M3 Processor and Core Peripherals 
+ */
+#ifdef STM32F10X_XL
+ #define __MPU_PRESENT             1 /*!< STM32 XL-density devices provide an MPU */
+#else
+ #define __MPU_PRESENT             0 /*!< Other STM32 devices does not provide an MPU */
+#endif /* STM32F10X_XL */
+#define __NVIC_PRIO_BITS          4 /*!< STM32 uses 4 Bits for the Priority Levels    */
+#define __Vendor_SysTickConfig    0 /*!< Set to 1 if different SysTick Config is used */
+
+/**
+ * @brief STM32F10x Interrupt Number Definition, according to the selected device 
+ *        in @ref Library_configuration_section 
+ */
+typedef enum IRQn
+{
+/******  Cortex-M3 Processor Exceptions Numbers ***************************************************/
+  NonMaskableInt_IRQn         = -14,    /*!< 2 Non Maskable Interrupt                             */
+  MemoryManagement_IRQn       = -12,    /*!< 4 Cortex-M3 Memory Management Interrupt              */
+  BusFault_IRQn               = -11,    /*!< 5 Cortex-M3 Bus Fault Interrupt                      */
+  UsageFault_IRQn             = -10,    /*!< 6 Cortex-M3 Usage Fault Interrupt                    */
+  SVCall_IRQn                 = -5,     /*!< 11 Cortex-M3 SV Call Interrupt                       */
+  DebugMonitor_IRQn           = -4,     /*!< 12 Cortex-M3 Debug Monitor Interrupt                 */
+  PendSV_IRQn                 = -2,     /*!< 14 Cortex-M3 Pend SV Interrupt                       */
+  SysTick_IRQn                = -1,     /*!< 15 Cortex-M3 System Tick Interrupt                   */
+
+/******  STM32 specific Interrupt Numbers *********************************************************/
+  WWDG_IRQn                   = 0,      /*!< Window WatchDog Interrupt                            */
+  PVD_IRQn                    = 1,      /*!< PVD through EXTI Line detection Interrupt            */
+  TAMPER_IRQn                 = 2,      /*!< Tamper Interrupt                                     */
+  RTC_IRQn                    = 3,      /*!< RTC global Interrupt                                 */
+  FLASH_IRQn                  = 4,      /*!< FLASH global Interrupt                               */
+  RCC_IRQn                    = 5,      /*!< RCC global Interrupt                                 */
+  EXTI0_IRQn                  = 6,      /*!< EXTI Line0 Interrupt                                 */
+  EXTI1_IRQn                  = 7,      /*!< EXTI Line1 Interrupt                                 */
+  EXTI2_IRQn                  = 8,      /*!< EXTI Line2 Interrupt                                 */
+  EXTI3_IRQn                  = 9,      /*!< EXTI Line3 Interrupt                                 */
+  EXTI4_IRQn                  = 10,     /*!< EXTI Line4 Interrupt                                 */
+  DMA1_Channel1_IRQn          = 11,     /*!< DMA1 Channel 1 global Interrupt                      */
+  DMA1_Channel2_IRQn          = 12,     /*!< DMA1 Channel 2 global Interrupt                      */
+  DMA1_Channel3_IRQn          = 13,     /*!< DMA1 Channel 3 global Interrupt                      */
+  DMA1_Channel4_IRQn          = 14,     /*!< DMA1 Channel 4 global Interrupt                      */
+  DMA1_Channel5_IRQn          = 15,     /*!< DMA1 Channel 5 global Interrupt                      */
+  DMA1_Channel6_IRQn          = 16,     /*!< DMA1 Channel 6 global Interrupt                      */
+  DMA1_Channel7_IRQn          = 17,     /*!< DMA1 Channel 7 global Interrupt                      */
+
+#ifdef STM32F10X_LD
+  ADC1_2_IRQn                 = 18,     /*!< ADC1 and ADC2 global Interrupt                       */
+  USB_HP_CAN1_TX_IRQn         = 19,     /*!< USB Device High Priority or CAN1 TX Interrupts       */
+  USB_LP_CAN1_RX0_IRQn        = 20,     /*!< USB Device Low Priority or CAN1 RX0 Interrupts       */
+  CAN1_RX1_IRQn               = 21,     /*!< CAN1 RX1 Interrupt                                   */
+  CAN1_SCE_IRQn               = 22,     /*!< CAN1 SCE Interrupt                                   */
+  EXTI9_5_IRQn                = 23,     /*!< External Line[9:5] Interrupts                        */
+  TIM1_BRK_IRQn               = 24,     /*!< TIM1 Break Interrupt                                 */
+  TIM1_UP_IRQn                = 25,     /*!< TIM1 Update Interrupt                                */
+  TIM1_TRG_COM_IRQn           = 26,     /*!< TIM1 Trigger and Commutation Interrupt               */
+  TIM1_CC_IRQn                = 27,     /*!< TIM1 Capture Compare Interrupt                       */
+  TIM2_IRQn                   = 28,     /*!< TIM2 global Interrupt                                */
+  TIM3_IRQn                   = 29,     /*!< TIM3 global Interrupt                                */
+  I2C1_EV_IRQn                = 31,     /*!< I2C1 Event Interrupt                                 */
+  I2C1_ER_IRQn                = 32,     /*!< I2C1 Error Interrupt                                 */
+  SPI1_IRQn                   = 35,     /*!< SPI1 global Interrupt                                */
+  USART1_IRQn                 = 37,     /*!< USART1 global Interrupt                              */
+  USART2_IRQn                 = 38,     /*!< USART2 global Interrupt                              */
+  EXTI15_10_IRQn              = 40,     /*!< External Line[15:10] Interrupts                      */
+  RTCAlarm_IRQn               = 41,     /*!< RTC Alarm through EXTI Line Interrupt                */
+  USBWakeUp_IRQn              = 42      /*!< USB Device WakeUp from suspend through EXTI Line Interrupt */    
+#endif /* STM32F10X_LD */  
+
+#ifdef STM32F10X_LD_VL
+  ADC1_IRQn                   = 18,     /*!< ADC1 global Interrupt                                */
+  EXTI9_5_IRQn                = 23,     /*!< External Line[9:5] Interrupts                        */
+  TIM1_BRK_TIM15_IRQn         = 24,     /*!< TIM1 Break and TIM15 Interrupts                      */
+  TIM1_UP_TIM16_IRQn          = 25,     /*!< TIM1 Update and TIM16 Interrupts                     */
+  TIM1_TRG_COM_TIM17_IRQn     = 26,     /*!< TIM1 Trigger and Commutation and TIM17 Interrupt     */
+  TIM1_CC_IRQn                = 27,     /*!< TIM1 Capture Compare Interrupt                       */
+  TIM2_IRQn                   = 28,     /*!< TIM2 global Interrupt                                */
+  TIM3_IRQn                   = 29,     /*!< TIM3 global Interrupt                                */
+  I2C1_EV_IRQn                = 31,     /*!< I2C1 Event Interrupt                                 */
+  I2C1_ER_IRQn                = 32,     /*!< I2C1 Error Interrupt                                 */
+  SPI1_IRQn                   = 35,     /*!< SPI1 global Interrupt                                */
+  USART1_IRQn                 = 37,     /*!< USART1 global Interrupt                              */
+  USART2_IRQn                 = 38,     /*!< USART2 global Interrupt                              */
+  EXTI15_10_IRQn              = 40,     /*!< External Line[15:10] Interrupts                      */
+  RTCAlarm_IRQn               = 41,     /*!< RTC Alarm through EXTI Line Interrupt                */
+  CEC_IRQn                    = 42,     /*!< HDMI-CEC Interrupt                                   */
+  TIM6_DAC_IRQn               = 54,     /*!< TIM6 and DAC underrun Interrupt                      */
+  TIM7_IRQn                   = 55      /*!< TIM7 Interrupt                                       */       
+#endif /* STM32F10X_LD_VL */
+
+#ifdef STM32F10X_MD
+  ADC1_2_IRQn                 = 18,     /*!< ADC1 and ADC2 global Interrupt                       */
+  USB_HP_CAN1_TX_IRQn         = 19,     /*!< USB Device High Priority or CAN1 TX Interrupts       */
+  USB_LP_CAN1_RX0_IRQn        = 20,     /*!< USB Device Low Priority or CAN1 RX0 Interrupts       */
+  CAN1_RX1_IRQn               = 21,     /*!< CAN1 RX1 Interrupt                                   */
+  CAN1_SCE_IRQn               = 22,     /*!< CAN1 SCE Interrupt                                   */
+  EXTI9_5_IRQn                = 23,     /*!< External Line[9:5] Interrupts                        */
+  TIM1_BRK_IRQn               = 24,     /*!< TIM1 Break Interrupt                                 */
+  TIM1_UP_IRQn                = 25,     /*!< TIM1 Update Interrupt                                */
+  TIM1_TRG_COM_IRQn           = 26,     /*!< TIM1 Trigger and Commutation Interrupt               */
+  TIM1_CC_IRQn                = 27,     /*!< TIM1 Capture Compare Interrupt                       */
+  TIM2_IRQn                   = 28,     /*!< TIM2 global Interrupt                                */
+  TIM3_IRQn                   = 29,     /*!< TIM3 global Interrupt                                */
+  TIM4_IRQn                   = 30,     /*!< TIM4 global Interrupt                                */
+  I2C1_EV_IRQn                = 31,     /*!< I2C1 Event Interrupt                                 */
+  I2C1_ER_IRQn                = 32,     /*!< I2C1 Error Interrupt                                 */
+  I2C2_EV_IRQn                = 33,     /*!< I2C2 Event Interrupt                                 */
+  I2C2_ER_IRQn                = 34,     /*!< I2C2 Error Interrupt                                 */
+  SPI1_IRQn                   = 35,     /*!< SPI1 global Interrupt                                */
+  SPI2_IRQn                   = 36,     /*!< SPI2 global Interrupt                                */
+  USART1_IRQn                 = 37,     /*!< USART1 global Interrupt                              */
+  USART2_IRQn                 = 38,     /*!< USART2 global Interrupt                              */
+  USART3_IRQn                 = 39,     /*!< USART3 global Interrupt                              */
+  EXTI15_10_IRQn              = 40,     /*!< External Line[15:10] Interrupts                      */
+  RTCAlarm_IRQn               = 41,     /*!< RTC Alarm through EXTI Line Interrupt                */
+  USBWakeUp_IRQn              = 42      /*!< USB Device WakeUp from suspend through EXTI Line Interrupt */  
+#endif /* STM32F10X_MD */  
+
+#ifdef STM32F10X_MD_VL
+  ADC1_IRQn                   = 18,     /*!< ADC1 global Interrupt                                */
+  EXTI9_5_IRQn                = 23,     /*!< External Line[9:5] Interrupts                        */
+  TIM1_BRK_TIM15_IRQn         = 24,     /*!< TIM1 Break and TIM15 Interrupts                      */
+  TIM1_UP_TIM16_IRQn          = 25,     /*!< TIM1 Update and TIM16 Interrupts                     */
+  TIM1_TRG_COM_TIM17_IRQn     = 26,     /*!< TIM1 Trigger and Commutation and TIM17 Interrupt     */
+  TIM1_CC_IRQn                = 27,     /*!< TIM1 Capture Compare Interrupt                       */
+  TIM2_IRQn                   = 28,     /*!< TIM2 global Interrupt                                */
+  TIM3_IRQn                   = 29,     /*!< TIM3 global Interrupt                                */
+  TIM4_IRQn                   = 30,     /*!< TIM4 global Interrupt                                */
+  I2C1_EV_IRQn                = 31,     /*!< I2C1 Event Interrupt                                 */
+  I2C1_ER_IRQn                = 32,     /*!< I2C1 Error Interrupt                                 */
+  I2C2_EV_IRQn                = 33,     /*!< I2C2 Event Interrupt                                 */
+  I2C2_ER_IRQn                = 34,     /*!< I2C2 Error Interrupt                                 */
+  SPI1_IRQn                   = 35,     /*!< SPI1 global Interrupt                                */
+  SPI2_IRQn                   = 36,     /*!< SPI2 global Interrupt                                */
+  USART1_IRQn                 = 37,     /*!< USART1 global Interrupt                              */
+  USART2_IRQn                 = 38,     /*!< USART2 global Interrupt                              */
+  USART3_IRQn                 = 39,     /*!< USART3 global Interrupt                              */
+  EXTI15_10_IRQn              = 40,     /*!< External Line[15:10] Interrupts                      */
+  RTCAlarm_IRQn               = 41,     /*!< RTC Alarm through EXTI Line Interrupt                */
+  CEC_IRQn                    = 42,     /*!< HDMI-CEC Interrupt                                   */
+  TIM6_DAC_IRQn               = 54,     /*!< TIM6 and DAC underrun Interrupt                      */
+  TIM7_IRQn                   = 55      /*!< TIM7 Interrupt                                       */       
+#endif /* STM32F10X_MD_VL */
+
+#ifdef STM32F10X_HD
+  ADC1_2_IRQn                 = 18,     /*!< ADC1 and ADC2 global Interrupt                       */
+  USB_HP_CAN1_TX_IRQn         = 19,     /*!< USB Device High Priority or CAN1 TX Interrupts       */
+  USB_LP_CAN1_RX0_IRQn        = 20,     /*!< USB Device Low Priority or CAN1 RX0 Interrupts       */
+  CAN1_RX1_IRQn               = 21,     /*!< CAN1 RX1 Interrupt                                   */
+  CAN1_SCE_IRQn               = 22,     /*!< CAN1 SCE Interrupt                                   */
+  EXTI9_5_IRQn                = 23,     /*!< External Line[9:5] Interrupts                        */
+  TIM1_BRK_IRQn               = 24,     /*!< TIM1 Break Interrupt                                 */
+  TIM1_UP_IRQn                = 25,     /*!< TIM1 Update Interrupt                                */
+  TIM1_TRG_COM_IRQn           = 26,     /*!< TIM1 Trigger and Commutation Interrupt               */
+  TIM1_CC_IRQn                = 27,     /*!< TIM1 Capture Compare Interrupt                       */
+  TIM2_IRQn                   = 28,     /*!< TIM2 global Interrupt                                */
+  TIM3_IRQn                   = 29,     /*!< TIM3 global Interrupt                                */
+  TIM4_IRQn                   = 30,     /*!< TIM4 global Interrupt                                */
+  I2C1_EV_IRQn                = 31,     /*!< I2C1 Event Interrupt                                 */
+  I2C1_ER_IRQn                = 32,     /*!< I2C1 Error Interrupt                                 */
+  I2C2_EV_IRQn                = 33,     /*!< I2C2 Event Interrupt                                 */
+  I2C2_ER_IRQn                = 34,     /*!< I2C2 Error Interrupt                                 */
+  SPI1_IRQn                   = 35,     /*!< SPI1 global Interrupt                                */
+  SPI2_IRQn                   = 36,     /*!< SPI2 global Interrupt                                */
+  USART1_IRQn                 = 37,     /*!< USART1 global Interrupt                              */
+  USART2_IRQn                 = 38,     /*!< USART2 global Interrupt                              */
+  USART3_IRQn                 = 39,     /*!< USART3 global Interrupt                              */
+  EXTI15_10_IRQn              = 40,     /*!< External Line[15:10] Interrupts                      */
+  RTCAlarm_IRQn               = 41,     /*!< RTC Alarm through EXTI Line Interrupt                */
+  USBWakeUp_IRQn              = 42,     /*!< USB Device WakeUp from suspend through EXTI Line Interrupt */
+  TIM8_BRK_IRQn               = 43,     /*!< TIM8 Break Interrupt                                 */
+  TIM8_UP_IRQn                = 44,     /*!< TIM8 Update Interrupt                                */
+  TIM8_TRG_COM_IRQn           = 45,     /*!< TIM8 Trigger and Commutation Interrupt               */
+  TIM8_CC_IRQn                = 46,     /*!< TIM8 Capture Compare Interrupt                       */
+  ADC3_IRQn                   = 47,     /*!< ADC3 global Interrupt                                */
+  FSMC_IRQn                   = 48,     /*!< FSMC global Interrupt                                */
+  SDIO_IRQn                   = 49,     /*!< SDIO global Interrupt                                */
+  TIM5_IRQn                   = 50,     /*!< TIM5 global Interrupt                                */
+  SPI3_IRQn                   = 51,     /*!< SPI3 global Interrupt                                */
+  UART4_IRQn                  = 52,     /*!< UART4 global Interrupt                               */
+  UART5_IRQn                  = 53,     /*!< UART5 global Interrupt                               */
+  TIM6_IRQn                   = 54,     /*!< TIM6 global Interrupt                                */
+  TIM7_IRQn                   = 55,     /*!< TIM7 global Interrupt                                */
+  DMA2_Channel1_IRQn          = 56,     /*!< DMA2 Channel 1 global Interrupt                      */
+  DMA2_Channel2_IRQn          = 57,     /*!< DMA2 Channel 2 global Interrupt                      */
+  DMA2_Channel3_IRQn          = 58,     /*!< DMA2 Channel 3 global Interrupt                      */
+  DMA2_Channel4_5_IRQn        = 59      /*!< DMA2 Channel 4 and Channel 5 global Interrupt        */
+#endif /* STM32F10X_HD */  
+
+#ifdef STM32F10X_HD_VL
+  ADC1_IRQn                   = 18,     /*!< ADC1 global Interrupt                                */
+  EXTI9_5_IRQn                = 23,     /*!< External Line[9:5] Interrupts                        */
+  TIM1_BRK_TIM15_IRQn         = 24,     /*!< TIM1 Break and TIM15 Interrupts                      */
+  TIM1_UP_TIM16_IRQn          = 25,     /*!< TIM1 Update and TIM16 Interrupts                     */
+  TIM1_TRG_COM_TIM17_IRQn     = 26,     /*!< TIM1 Trigger and Commutation and TIM17 Interrupt     */
+  TIM1_CC_IRQn                = 27,     /*!< TIM1 Capture Compare Interrupt                       */
+  TIM2_IRQn                   = 28,     /*!< TIM2 global Interrupt                                */
+  TIM3_IRQn                   = 29,     /*!< TIM3 global Interrupt                                */
+  TIM4_IRQn                   = 30,     /*!< TIM4 global Interrupt                                */
+  I2C1_EV_IRQn                = 31,     /*!< I2C1 Event Interrupt                                 */
+  I2C1_ER_IRQn                = 32,     /*!< I2C1 Error Interrupt                                 */
+  I2C2_EV_IRQn                = 33,     /*!< I2C2 Event Interrupt                                 */
+  I2C2_ER_IRQn                = 34,     /*!< I2C2 Error Interrupt                                 */
+  SPI1_IRQn                   = 35,     /*!< SPI1 global Interrupt                                */
+  SPI2_IRQn                   = 36,     /*!< SPI2 global Interrupt                                */
+  USART1_IRQn                 = 37,     /*!< USART1 global Interrupt                              */
+  USART2_IRQn                 = 38,     /*!< USART2 global Interrupt                              */
+  USART3_IRQn                 = 39,     /*!< USART3 global Interrupt                              */
+  EXTI15_10_IRQn              = 40,     /*!< External Line[15:10] Interrupts                      */
+  RTCAlarm_IRQn               = 41,     /*!< RTC Alarm through EXTI Line Interrupt                */
+  CEC_IRQn                    = 42,     /*!< HDMI-CEC Interrupt                                   */
+  TIM12_IRQn                  = 43,     /*!< TIM12 global Interrupt                               */
+  TIM13_IRQn                  = 44,     /*!< TIM13 global Interrupt                               */
+  TIM14_IRQn                  = 45,     /*!< TIM14 global Interrupt                               */
+  TIM5_IRQn                   = 50,     /*!< TIM5 global Interrupt                                */
+  SPI3_IRQn                   = 51,     /*!< SPI3 global Interrupt                                */
+  UART4_IRQn                  = 52,     /*!< UART4 global Interrupt                               */
+  UART5_IRQn                  = 53,     /*!< UART5 global Interrupt                               */  
+  TIM6_DAC_IRQn               = 54,     /*!< TIM6 and DAC underrun Interrupt                      */
+  TIM7_IRQn                   = 55,     /*!< TIM7 Interrupt                                       */  
+  DMA2_Channel1_IRQn          = 56,     /*!< DMA2 Channel 1 global Interrupt                      */
+  DMA2_Channel2_IRQn          = 57,     /*!< DMA2 Channel 2 global Interrupt                      */
+  DMA2_Channel3_IRQn          = 58,     /*!< DMA2 Channel 3 global Interrupt                      */
+  DMA2_Channel4_5_IRQn        = 59,     /*!< DMA2 Channel 4 and Channel 5 global Interrupt        */
+  DMA2_Channel5_IRQn          = 60      /*!< DMA2 Channel 5 global Interrupt (DMA2 Channel 5 is 
+                                             mapped at position 60 only if the MISC_REMAP bit in 
+                                             the AFIO_MAPR2 register is set)                      */       
+#endif /* STM32F10X_HD_VL */
+
+#ifdef STM32F10X_XL
+  ADC1_2_IRQn                 = 18,     /*!< ADC1 and ADC2 global Interrupt                       */
+  USB_HP_CAN1_TX_IRQn         = 19,     /*!< USB Device High Priority or CAN1 TX Interrupts       */
+  USB_LP_CAN1_RX0_IRQn        = 20,     /*!< USB Device Low Priority or CAN1 RX0 Interrupts       */
+  CAN1_RX1_IRQn               = 21,     /*!< CAN1 RX1 Interrupt                                   */
+  CAN1_SCE_IRQn               = 22,     /*!< CAN1 SCE Interrupt                                   */
+  EXTI9_5_IRQn                = 23,     /*!< External Line[9:5] Interrupts                        */
+  TIM1_BRK_TIM9_IRQn          = 24,     /*!< TIM1 Break Interrupt and TIM9 global Interrupt       */
+  TIM1_UP_TIM10_IRQn          = 25,     /*!< TIM1 Update Interrupt and TIM10 global Interrupt     */
+  TIM1_TRG_COM_TIM11_IRQn     = 26,     /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */
+  TIM1_CC_IRQn                = 27,     /*!< TIM1 Capture Compare Interrupt                       */
+  TIM2_IRQn                   = 28,     /*!< TIM2 global Interrupt                                */
+  TIM3_IRQn                   = 29,     /*!< TIM3 global Interrupt                                */
+  TIM4_IRQn                   = 30,     /*!< TIM4 global Interrupt                                */
+  I2C1_EV_IRQn                = 31,     /*!< I2C1 Event Interrupt                                 */
+  I2C1_ER_IRQn                = 32,     /*!< I2C1 Error Interrupt                                 */
+  I2C2_EV_IRQn                = 33,     /*!< I2C2 Event Interrupt                                 */
+  I2C2_ER_IRQn                = 34,     /*!< I2C2 Error Interrupt                                 */
+  SPI1_IRQn                   = 35,     /*!< SPI1 global Interrupt                                */
+  SPI2_IRQn                   = 36,     /*!< SPI2 global Interrupt                                */
+  USART1_IRQn                 = 37,     /*!< USART1 global Interrupt                              */
+  USART2_IRQn                 = 38,     /*!< USART2 global Interrupt                              */
+  USART3_IRQn                 = 39,     /*!< USART3 global Interrupt                              */
+  EXTI15_10_IRQn              = 40,     /*!< External Line[15:10] Interrupts                      */
+  RTCAlarm_IRQn               = 41,     /*!< RTC Alarm through EXTI Line Interrupt                */
+  USBWakeUp_IRQn              = 42,     /*!< USB Device WakeUp from suspend through EXTI Line Interrupt */
+  TIM8_BRK_TIM12_IRQn         = 43,     /*!< TIM8 Break Interrupt and TIM12 global Interrupt      */
+  TIM8_UP_TIM13_IRQn          = 44,     /*!< TIM8 Update Interrupt and TIM13 global Interrupt     */
+  TIM8_TRG_COM_TIM14_IRQn     = 45,     /*!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */
+  TIM8_CC_IRQn                = 46,     /*!< TIM8 Capture Compare Interrupt                       */
+  ADC3_IRQn                   = 47,     /*!< ADC3 global Interrupt                                */
+  FSMC_IRQn                   = 48,     /*!< FSMC global Interrupt                                */
+  SDIO_IRQn                   = 49,     /*!< SDIO global Interrupt                                */
+  TIM5_IRQn                   = 50,     /*!< TIM5 global Interrupt                                */
+  SPI3_IRQn                   = 51,     /*!< SPI3 global Interrupt                                */
+  UART4_IRQn                  = 52,     /*!< UART4 global Interrupt                               */
+  UART5_IRQn                  = 53,     /*!< UART5 global Interrupt                               */
+  TIM6_IRQn                   = 54,     /*!< TIM6 global Interrupt                                */
+  TIM7_IRQn                   = 55,     /*!< TIM7 global Interrupt                                */
+  DMA2_Channel1_IRQn          = 56,     /*!< DMA2 Channel 1 global Interrupt                      */
+  DMA2_Channel2_IRQn          = 57,     /*!< DMA2 Channel 2 global Interrupt                      */
+  DMA2_Channel3_IRQn          = 58,     /*!< DMA2 Channel 3 global Interrupt                      */
+  DMA2_Channel4_5_IRQn        = 59      /*!< DMA2 Channel 4 and Channel 5 global Interrupt        */
+#endif /* STM32F10X_XL */  
+
+#ifdef STM32F10X_CL
+  ADC1_2_IRQn                 = 18,     /*!< ADC1 and ADC2 global Interrupt                       */
+  CAN1_TX_IRQn                = 19,     /*!< USB Device High Priority or CAN1 TX Interrupts       */
+  CAN1_RX0_IRQn               = 20,     /*!< USB Device Low Priority or CAN1 RX0 Interrupts       */
+  CAN1_RX1_IRQn               = 21,     /*!< CAN1 RX1 Interrupt                                   */
+  CAN1_SCE_IRQn               = 22,     /*!< CAN1 SCE Interrupt                                   */
+  EXTI9_5_IRQn                = 23,     /*!< External Line[9:5] Interrupts                        */
+  TIM1_BRK_IRQn               = 24,     /*!< TIM1 Break Interrupt                                 */
+  TIM1_UP_IRQn                = 25,     /*!< TIM1 Update Interrupt                                */
+  TIM1_TRG_COM_IRQn           = 26,     /*!< TIM1 Trigger and Commutation Interrupt               */
+  TIM1_CC_IRQn                = 27,     /*!< TIM1 Capture Compare Interrupt                       */
+  TIM2_IRQn                   = 28,     /*!< TIM2 global Interrupt                                */
+  TIM3_IRQn                   = 29,     /*!< TIM3 global Interrupt                                */
+  TIM4_IRQn                   = 30,     /*!< TIM4 global Interrupt                                */
+  I2C1_EV_IRQn                = 31,     /*!< I2C1 Event Interrupt                                 */
+  I2C1_ER_IRQn                = 32,     /*!< I2C1 Error Interrupt                                 */
+  I2C2_EV_IRQn                = 33,     /*!< I2C2 Event Interrupt                                 */
+  I2C2_ER_IRQn                = 34,     /*!< I2C2 Error Interrupt                                 */
+  SPI1_IRQn                   = 35,     /*!< SPI1 global Interrupt                                */
+  SPI2_IRQn                   = 36,     /*!< SPI2 global Interrupt                                */
+  USART1_IRQn                 = 37,     /*!< USART1 global Interrupt                              */
+  USART2_IRQn                 = 38,     /*!< USART2 global Interrupt                              */
+  USART3_IRQn                 = 39,     /*!< USART3 global Interrupt                              */
+  EXTI15_10_IRQn              = 40,     /*!< External Line[15:10] Interrupts                      */
+  RTCAlarm_IRQn               = 41,     /*!< RTC Alarm through EXTI Line Interrupt                */
+  OTG_FS_WKUP_IRQn            = 42,     /*!< USB OTG FS WakeUp from suspend through EXTI Line Interrupt */
+  TIM5_IRQn                   = 50,     /*!< TIM5 global Interrupt                                */
+  SPI3_IRQn                   = 51,     /*!< SPI3 global Interrupt                                */
+  UART4_IRQn                  = 52,     /*!< UART4 global Interrupt                               */
+  UART5_IRQn                  = 53,     /*!< UART5 global Interrupt                               */
+  TIM6_IRQn                   = 54,     /*!< TIM6 global Interrupt                                */
+  TIM7_IRQn                   = 55,     /*!< TIM7 global Interrupt                                */
+  DMA2_Channel1_IRQn          = 56,     /*!< DMA2 Channel 1 global Interrupt                      */
+  DMA2_Channel2_IRQn          = 57,     /*!< DMA2 Channel 2 global Interrupt                      */
+  DMA2_Channel3_IRQn          = 58,     /*!< DMA2 Channel 3 global Interrupt                      */
+  DMA2_Channel4_IRQn          = 59,     /*!< DMA2 Channel 4 global Interrupt                      */
+  DMA2_Channel5_IRQn          = 60,     /*!< DMA2 Channel 5 global Interrupt                      */
+  ETH_IRQn                    = 61,     /*!< Ethernet global Interrupt                            */
+  ETH_WKUP_IRQn               = 62,     /*!< Ethernet Wakeup through EXTI line Interrupt          */
+  CAN2_TX_IRQn                = 63,     /*!< CAN2 TX Interrupt                                    */
+  CAN2_RX0_IRQn               = 64,     /*!< CAN2 RX0 Interrupt                                   */
+  CAN2_RX1_IRQn               = 65,     /*!< CAN2 RX1 Interrupt                                   */
+  CAN2_SCE_IRQn               = 66,     /*!< CAN2 SCE Interrupt                                   */
+  OTG_FS_IRQn                 = 67      /*!< USB OTG FS global Interrupt                          */
+#endif /* STM32F10X_CL */     
+} IRQn_Type;
+
+/**
+  * @}
+  */
+
+#include "core_cm3.h"
+#include "system_stm32f10x.h"
+#include <stdint.h>
+
+/** @addtogroup Exported_types
+  * @{
+  */  
+
+/*!< STM32F10x Standard Peripheral Library old types (maintained for legacy purpose) */
+typedef int32_t  s32;
+typedef int16_t s16;
+typedef int8_t  s8;
+
+typedef const int32_t sc32;  /*!< Read Only */
+typedef const int16_t sc16;  /*!< Read Only */
+typedef const int8_t sc8;   /*!< Read Only */
+
+typedef __IO int32_t  vs32;
+typedef __IO int16_t  vs16;
+typedef __IO int8_t   vs8;
+
+typedef __I int32_t vsc32;  /*!< Read Only */
+typedef __I int16_t vsc16;  /*!< Read Only */
+typedef __I int8_t vsc8;   /*!< Read Only */
+
+typedef uint32_t  u32;
+typedef uint16_t u16;
+typedef uint8_t  u8;
+
+typedef const uint32_t uc32;  /*!< Read Only */
+typedef const uint16_t uc16;  /*!< Read Only */
+typedef const uint8_t uc8;   /*!< Read Only */
+
+typedef __IO uint32_t  vu32;
+typedef __IO uint16_t vu16;
+typedef __IO uint8_t  vu8;
+
+typedef __I uint32_t vuc32;  /*!< Read Only */
+typedef __I uint16_t vuc16;  /*!< Read Only */
+typedef __I uint8_t vuc8;   /*!< Read Only */
+
+typedef enum {RESET = 0, SET = !RESET} FlagStatus, ITStatus;
+
+typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState;
+#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))
+
+typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrorStatus;
+
+/*!< STM32F10x Standard Peripheral Library old definitions (maintained for legacy purpose) */
+#define HSEStartUp_TimeOut   HSE_STARTUP_TIMEOUT
+#define HSE_Value            HSE_VALUE
+#define HSI_Value            HSI_VALUE
+/**
+  * @}
+  */
+
+/** @addtogroup Peripheral_registers_structures
+  * @{
+  */   
+
+/** 
+  * @brief Analog to Digital Converter  
+  */
+
+typedef struct
+{
+  __IO uint32_t SR;
+  __IO uint32_t CR1;
+  __IO uint32_t CR2;
+  __IO uint32_t SMPR1;
+  __IO uint32_t SMPR2;
+  __IO uint32_t JOFR1;
+  __IO uint32_t JOFR2;
+  __IO uint32_t JOFR3;
+  __IO uint32_t JOFR4;
+  __IO uint32_t HTR;
+  __IO uint32_t LTR;
+  __IO uint32_t SQR1;
+  __IO uint32_t SQR2;
+  __IO uint32_t SQR3;
+  __IO uint32_t JSQR;
+  __IO uint32_t JDR1;
+  __IO uint32_t JDR2;
+  __IO uint32_t JDR3;
+  __IO uint32_t JDR4;
+  __IO uint32_t DR;
+} ADC_TypeDef;
+
+/** 
+  * @brief Backup Registers  
+  */
+
+typedef struct
+{
+  uint32_t  RESERVED0;
+  __IO uint16_t DR1;
+  uint16_t  RESERVED1;
+  __IO uint16_t DR2;
+  uint16_t  RESERVED2;
+  __IO uint16_t DR3;
+  uint16_t  RESERVED3;
+  __IO uint16_t DR4;
+  uint16_t  RESERVED4;
+  __IO uint16_t DR5;
+  uint16_t  RESERVED5;
+  __IO uint16_t DR6;
+  uint16_t  RESERVED6;
+  __IO uint16_t DR7;
+  uint16_t  RESERVED7;
+  __IO uint16_t DR8;
+  uint16_t  RESERVED8;
+  __IO uint16_t DR9;
+  uint16_t  RESERVED9;
+  __IO uint16_t DR10;
+  uint16_t  RESERVED10; 
+  __IO uint16_t RTCCR;
+  uint16_t  RESERVED11;
+  __IO uint16_t CR;
+  uint16_t  RESERVED12;
+  __IO uint16_t CSR;
+  uint16_t  RESERVED13[5];
+  __IO uint16_t DR11;
+  uint16_t  RESERVED14;
+  __IO uint16_t DR12;
+  uint16_t  RESERVED15;
+  __IO uint16_t DR13;
+  uint16_t  RESERVED16;
+  __IO uint16_t DR14;
+  uint16_t  RESERVED17;
+  __IO uint16_t DR15;
+  uint16_t  RESERVED18;
+  __IO uint16_t DR16;
+  uint16_t  RESERVED19;
+  __IO uint16_t DR17;
+  uint16_t  RESERVED20;
+  __IO uint16_t DR18;
+  uint16_t  RESERVED21;
+  __IO uint16_t DR19;
+  uint16_t  RESERVED22;
+  __IO uint16_t DR20;
+  uint16_t  RESERVED23;
+  __IO uint16_t DR21;
+  uint16_t  RESERVED24;
+  __IO uint16_t DR22;
+  uint16_t  RESERVED25;
+  __IO uint16_t DR23;
+  uint16_t  RESERVED26;
+  __IO uint16_t DR24;
+  uint16_t  RESERVED27;
+  __IO uint16_t DR25;
+  uint16_t  RESERVED28;
+  __IO uint16_t DR26;
+  uint16_t  RESERVED29;
+  __IO uint16_t DR27;
+  uint16_t  RESERVED30;
+  __IO uint16_t DR28;
+  uint16_t  RESERVED31;
+  __IO uint16_t DR29;
+  uint16_t  RESERVED32;
+  __IO uint16_t DR30;
+  uint16_t  RESERVED33; 
+  __IO uint16_t DR31;
+  uint16_t  RESERVED34;
+  __IO uint16_t DR32;
+  uint16_t  RESERVED35;
+  __IO uint16_t DR33;
+  uint16_t  RESERVED36;
+  __IO uint16_t DR34;
+  uint16_t  RESERVED37;
+  __IO uint16_t DR35;
+  uint16_t  RESERVED38;
+  __IO uint16_t DR36;
+  uint16_t  RESERVED39;
+  __IO uint16_t DR37;
+  uint16_t  RESERVED40;
+  __IO uint16_t DR38;
+  uint16_t  RESERVED41;
+  __IO uint16_t DR39;
+  uint16_t  RESERVED42;
+  __IO uint16_t DR40;
+  uint16_t  RESERVED43;
+  __IO uint16_t DR41;
+  uint16_t  RESERVED44;
+  __IO uint16_t DR42;
+  uint16_t  RESERVED45;    
+} BKP_TypeDef;
+  
+/** 
+  * @brief Controller Area Network TxMailBox 
+  */
+
+typedef struct
+{
+  __IO uint32_t TIR;
+  __IO uint32_t TDTR;
+  __IO uint32_t TDLR;
+  __IO uint32_t TDHR;
+} CAN_TxMailBox_TypeDef;
+
+/** 
+  * @brief Controller Area Network FIFOMailBox 
+  */
+  
+typedef struct
+{
+  __IO uint32_t RIR;
+  __IO uint32_t RDTR;
+  __IO uint32_t RDLR;
+  __IO uint32_t RDHR;
+} CAN_FIFOMailBox_TypeDef;
+
+/** 
+  * @brief Controller Area Network FilterRegister 
+  */
+  
+typedef struct
+{
+  __IO uint32_t FR1;
+  __IO uint32_t FR2;
+} CAN_FilterRegister_TypeDef;
+
+/** 
+  * @brief Controller Area Network 
+  */
+  
+typedef struct
+{
+  __IO uint32_t MCR;
+  __IO uint32_t MSR;
+  __IO uint32_t TSR;
+  __IO uint32_t RF0R;
+  __IO uint32_t RF1R;
+  __IO uint32_t IER;
+  __IO uint32_t ESR;
+  __IO uint32_t BTR;
+  uint32_t  RESERVED0[88];
+  CAN_TxMailBox_TypeDef sTxMailBox[3];
+  CAN_FIFOMailBox_TypeDef sFIFOMailBox[2];
+  uint32_t  RESERVED1[12];
+  __IO uint32_t FMR;
+  __IO uint32_t FM1R;
+  uint32_t  RESERVED2;
+  __IO uint32_t FS1R;
+  uint32_t  RESERVED3;
+  __IO uint32_t FFA1R;
+  uint32_t  RESERVED4;
+  __IO uint32_t FA1R;
+  uint32_t  RESERVED5[8];
+#ifndef STM32F10X_CL
+  CAN_FilterRegister_TypeDef sFilterRegister[14];
+#else
+  CAN_FilterRegister_TypeDef sFilterRegister[28];
+#endif /* STM32F10X_CL */  
+} CAN_TypeDef;
+
+/** 
+  * @brief Consumer Electronics Control (CEC)
+  */
+typedef struct
+{
+  __IO uint32_t CFGR;
+  __IO uint32_t OAR;
+  __IO uint32_t PRES;
+  __IO uint32_t ESR;
+  __IO uint32_t CSR;
+  __IO uint32_t TXD;
+  __IO uint32_t RXD;  
+} CEC_TypeDef;
+
+/** 
+  * @brief CRC calculation unit 
+  */
+
+typedef struct
+{
+  __IO uint32_t DR;
+  __IO uint8_t  IDR;
+  uint8_t   RESERVED0;
+  uint16_t  RESERVED1;
+  __IO uint32_t CR;
+} CRC_TypeDef;
+
+/** 
+  * @brief Digital to Analog Converter
+  */
+
+typedef struct
+{
+  __IO uint32_t CR;
+  __IO uint32_t SWTRIGR;
+  __IO uint32_t DHR12R1;
+  __IO uint32_t DHR12L1;
+  __IO uint32_t DHR8R1;
+  __IO uint32_t DHR12R2;
+  __IO uint32_t DHR12L2;
+  __IO uint32_t DHR8R2;
+  __IO uint32_t DHR12RD;
+  __IO uint32_t DHR12LD;
+  __IO uint32_t DHR8RD;
+  __IO uint32_t DOR1;
+  __IO uint32_t DOR2;
+#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
+  __IO uint32_t SR;
+#endif
+} DAC_TypeDef;
+
+/** 
+  * @brief Debug MCU
+  */
+
+typedef struct
+{
+  __IO uint32_t IDCODE;
+  __IO uint32_t CR;	
+}DBGMCU_TypeDef;
+
+/** 
+  * @brief DMA Controller
+  */
+
+typedef struct
+{
+  __IO uint32_t CCR;
+  __IO uint32_t CNDTR;
+  __IO uint32_t CPAR;
+  __IO uint32_t CMAR;
+} DMA_Channel_TypeDef;
+
+typedef struct
+{
+  __IO uint32_t ISR;
+  __IO uint32_t IFCR;
+} DMA_TypeDef;
+
+/** 
+  * @brief Ethernet MAC
+  */
+
+typedef struct
+{
+  __IO uint32_t MACCR;
+  __IO uint32_t MACFFR;
+  __IO uint32_t MACHTHR;
+  __IO uint32_t MACHTLR;
+  __IO uint32_t MACMIIAR;
+  __IO uint32_t MACMIIDR;
+  __IO uint32_t MACFCR;
+  __IO uint32_t MACVLANTR;             /*    8 */
+       uint32_t RESERVED0[2];
+  __IO uint32_t MACRWUFFR;             /*   11 */
+  __IO uint32_t MACPMTCSR;
+       uint32_t RESERVED1[2];
+  __IO uint32_t MACSR;                 /*   15 */
+  __IO uint32_t MACIMR;
+  __IO uint32_t MACA0HR;
+  __IO uint32_t MACA0LR;
+  __IO uint32_t MACA1HR;
+  __IO uint32_t MACA1LR;
+  __IO uint32_t MACA2HR;
+  __IO uint32_t MACA2LR;
+  __IO uint32_t MACA3HR;
+  __IO uint32_t MACA3LR;               /*   24 */
+       uint32_t RESERVED2[40];
+  __IO uint32_t MMCCR;                 /*   65 */
+  __IO uint32_t MMCRIR;
+  __IO uint32_t MMCTIR;
+  __IO uint32_t MMCRIMR;
+  __IO uint32_t MMCTIMR;               /*   69 */
+       uint32_t RESERVED3[14];
+  __IO uint32_t MMCTGFSCCR;            /*   84 */
+  __IO uint32_t MMCTGFMSCCR;
+       uint32_t RESERVED4[5];
+  __IO uint32_t MMCTGFCR;
+       uint32_t RESERVED5[10];
+  __IO uint32_t MMCRFCECR;
+  __IO uint32_t MMCRFAECR;
+       uint32_t RESERVED6[10];
+  __IO uint32_t MMCRGUFCR;
+       uint32_t RESERVED7[334];
+  __IO uint32_t PTPTSCR;
+  __IO uint32_t PTPSSIR;
+  __IO uint32_t PTPTSHR;
+  __IO uint32_t PTPTSLR;
+  __IO uint32_t PTPTSHUR;
+  __IO uint32_t PTPTSLUR;
+  __IO uint32_t PTPTSAR;
+  __IO uint32_t PTPTTHR;
+  __IO uint32_t PTPTTLR;
+       uint32_t RESERVED8[567];
+  __IO uint32_t DMABMR;
+  __IO uint32_t DMATPDR;
+  __IO uint32_t DMARPDR;
+  __IO uint32_t DMARDLAR;
+  __IO uint32_t DMATDLAR;
+  __IO uint32_t DMASR;
+  __IO uint32_t DMAOMR;
+  __IO uint32_t DMAIER;
+  __IO uint32_t DMAMFBOCR;
+       uint32_t RESERVED9[9];
+  __IO uint32_t DMACHTDR;
+  __IO uint32_t DMACHRDR;
+  __IO uint32_t DMACHTBAR;
+  __IO uint32_t DMACHRBAR;
+} ETH_TypeDef;
+
+/** 
+  * @brief External Interrupt/Event Controller
+  */
+
+typedef struct
+{
+  __IO uint32_t IMR;
+  __IO uint32_t EMR;
+  __IO uint32_t RTSR;
+  __IO uint32_t FTSR;
+  __IO uint32_t SWIER;
+  __IO uint32_t PR;
+} EXTI_TypeDef;
+
+/** 
+  * @brief FLASH Registers
+  */
+
+typedef struct
+{
+  __IO uint32_t ACR;
+  __IO uint32_t KEYR;
+  __IO uint32_t OPTKEYR;
+  __IO uint32_t SR;
+  __IO uint32_t CR;
+  __IO uint32_t AR;
+  __IO uint32_t RESERVED;
+  __IO uint32_t OBR;
+  __IO uint32_t WRPR;
+#ifdef STM32F10X_XL
+  uint32_t RESERVED1[8]; 
+  __IO uint32_t KEYR2;
+  uint32_t RESERVED2;   
+  __IO uint32_t SR2;
+  __IO uint32_t CR2;
+  __IO uint32_t AR2; 
+#endif /* STM32F10X_XL */  
+} FLASH_TypeDef;
+
+/** 
+  * @brief Option Bytes Registers
+  */
+  
+typedef struct
+{
+  __IO uint16_t RDP;
+  __IO uint16_t USER;
+  __IO uint16_t Data0;
+  __IO uint16_t Data1;
+  __IO uint16_t WRP0;
+  __IO uint16_t WRP1;
+  __IO uint16_t WRP2;
+  __IO uint16_t WRP3;
+} OB_TypeDef;
+
+/** 
+  * @brief Flexible Static Memory Controller
+  */
+
+typedef struct
+{
+  __IO uint32_t BTCR[8];   
+} FSMC_Bank1_TypeDef; 
+
+/** 
+  * @brief Flexible Static Memory Controller Bank1E
+  */
+  
+typedef struct
+{
+  __IO uint32_t BWTR[7];
+} FSMC_Bank1E_TypeDef;
+
+/** 
+  * @brief Flexible Static Memory Controller Bank2
+  */
+  
+typedef struct
+{
+  __IO uint32_t PCR2;
+  __IO uint32_t SR2;
+  __IO uint32_t PMEM2;
+  __IO uint32_t PATT2;
+  uint32_t  RESERVED0;   
+  __IO uint32_t ECCR2; 
+} FSMC_Bank2_TypeDef;  
+
+/** 
+  * @brief Flexible Static Memory Controller Bank3
+  */
+  
+typedef struct
+{
+  __IO uint32_t PCR3;
+  __IO uint32_t SR3;
+  __IO uint32_t PMEM3;
+  __IO uint32_t PATT3;
+  uint32_t  RESERVED0;   
+  __IO uint32_t ECCR3; 
+} FSMC_Bank3_TypeDef; 
+
+/** 
+  * @brief Flexible Static Memory Controller Bank4
+  */
+  
+typedef struct
+{
+  __IO uint32_t PCR4;
+  __IO uint32_t SR4;
+  __IO uint32_t PMEM4;
+  __IO uint32_t PATT4;
+  __IO uint32_t PIO4; 
+} FSMC_Bank4_TypeDef; 
+
+/** 
+  * @brief General Purpose I/O
+  */
+
+typedef struct
+{
+  __IO uint32_t CRL;
+  __IO uint32_t CRH;
+  __IO uint32_t IDR;
+  __IO uint32_t ODR;
+  __IO uint32_t BSRR;
+  __IO uint32_t BRR;
+  __IO uint32_t LCKR;
+} GPIO_TypeDef;
+
+/** 
+  * @brief Alternate Function I/O
+  */
+
+typedef struct
+{
+  __IO uint32_t EVCR;
+  __IO uint32_t MAPR;
+  __IO uint32_t EXTICR[4];
+  uint32_t RESERVED0;
+  __IO uint32_t MAPR2;  
+} AFIO_TypeDef;
+/** 
+  * @brief Inter Integrated Circuit Interface
+  */
+
+typedef struct
+{
+  __IO uint16_t CR1;
+  uint16_t  RESERVED0;
+  __IO uint16_t CR2;
+  uint16_t  RESERVED1;
+  __IO uint16_t OAR1;
+  uint16_t  RESERVED2;
+  __IO uint16_t OAR2;
+  uint16_t  RESERVED3;
+  __IO uint16_t DR;
+  uint16_t  RESERVED4;
+  __IO uint16_t SR1;
+  uint16_t  RESERVED5;
+  __IO uint16_t SR2;
+  uint16_t  RESERVED6;
+  __IO uint16_t CCR;
+  uint16_t  RESERVED7;
+  __IO uint16_t TRISE;
+  uint16_t  RESERVED8;
+} I2C_TypeDef;
+
+/** 
+  * @brief Independent WATCHDOG
+  */
+
+typedef struct
+{
+  __IO uint32_t KR;
+  __IO uint32_t PR;
+  __IO uint32_t RLR;
+  __IO uint32_t SR;
+} IWDG_TypeDef;
+
+/** 
+  * @brief Power Control
+  */
+
+typedef struct
+{
+  __IO uint32_t CR;
+  __IO uint32_t CSR;
+} PWR_TypeDef;
+
+/** 
+  * @brief Reset and Clock Control
+  */
+
+typedef struct
+{
+  __IO uint32_t CR;
+  __IO uint32_t CFGR;
+  __IO uint32_t CIR;
+  __IO uint32_t APB2RSTR;
+  __IO uint32_t APB1RSTR;
+  __IO uint32_t AHBENR;
+  __IO uint32_t APB2ENR;
+  __IO uint32_t APB1ENR;
+  __IO uint32_t BDCR;
+  __IO uint32_t CSR;
+
+#ifdef STM32F10X_CL  
+  __IO uint32_t AHBRSTR;
+  __IO uint32_t CFGR2;
+#endif /* STM32F10X_CL */ 
+
+#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)   
+  uint32_t RESERVED0;
+  __IO uint32_t CFGR2;
+#endif /* STM32F10X_LD_VL || STM32F10X_MD_VL || STM32F10X_HD_VL */ 
+} RCC_TypeDef;
+
+/** 
+  * @brief Real-Time Clock
+  */
+
+typedef struct
+{
+  __IO uint16_t CRH;
+  uint16_t  RESERVED0;
+  __IO uint16_t CRL;
+  uint16_t  RESERVED1;
+  __IO uint16_t PRLH;
+  uint16_t  RESERVED2;
+  __IO uint16_t PRLL;
+  uint16_t  RESERVED3;
+  __IO uint16_t DIVH;
+  uint16_t  RESERVED4;
+  __IO uint16_t DIVL;
+  uint16_t  RESERVED5;
+  __IO uint16_t CNTH;
+  uint16_t  RESERVED6;
+  __IO uint16_t CNTL;
+  uint16_t  RESERVED7;
+  __IO uint16_t ALRH;
+  uint16_t  RESERVED8;
+  __IO uint16_t ALRL;
+  uint16_t  RESERVED9;
+} RTC_TypeDef;
+
+/** 
+  * @brief SD host Interface
+  */
+
+typedef struct
+{
+  __IO uint32_t POWER;
+  __IO uint32_t CLKCR;
+  __IO uint32_t ARG;
+  __IO uint32_t CMD;
+  __I uint32_t RESPCMD;
+  __I uint32_t RESP1;
+  __I uint32_t RESP2;
+  __I uint32_t RESP3;
+  __I uint32_t RESP4;
+  __IO uint32_t DTIMER;
+  __IO uint32_t DLEN;
+  __IO uint32_t DCTRL;
+  __I uint32_t DCOUNT;
+  __I uint32_t STA;
+  __IO uint32_t ICR;
+  __IO uint32_t MASK;
+  uint32_t  RESERVED0[2];
+  __I uint32_t FIFOCNT;
+  uint32_t  RESERVED1[13];
+  __IO uint32_t FIFO;
+} SDIO_TypeDef;
+
+/** 
+  * @brief Serial Peripheral Interface
+  */
+
+typedef struct
+{
+  __IO uint16_t CR1;
+  uint16_t  RESERVED0;
+  __IO uint16_t CR2;
+  uint16_t  RESERVED1;
+  __IO uint16_t SR;
+  uint16_t  RESERVED2;
+  __IO uint16_t DR;
+  uint16_t  RESERVED3;
+  __IO uint16_t CRCPR;
+  uint16_t  RESERVED4;
+  __IO uint16_t RXCRCR;
+  uint16_t  RESERVED5;
+  __IO uint16_t TXCRCR;
+  uint16_t  RESERVED6;
+  __IO uint16_t I2SCFGR;
+  uint16_t  RESERVED7;
+  __IO uint16_t I2SPR;
+  uint16_t  RESERVED8;  
+} SPI_TypeDef;
+
+/** 
+  * @brief TIM
+  */
+
+typedef struct
+{
+  __IO uint16_t CR1;
+  uint16_t  RESERVED0;
+  __IO uint16_t CR2;
+  uint16_t  RESERVED1;
+  __IO uint16_t SMCR;
+  uint16_t  RESERVED2;
+  __IO uint16_t DIER;
+  uint16_t  RESERVED3;
+  __IO uint16_t SR;
+  uint16_t  RESERVED4;
+  __IO uint16_t EGR;
+  uint16_t  RESERVED5;
+  __IO uint16_t CCMR1;
+  uint16_t  RESERVED6;
+  __IO uint16_t CCMR2;
+  uint16_t  RESERVED7;
+  __IO uint16_t CCER;
+  uint16_t  RESERVED8;
+  __IO uint16_t CNT;
+  uint16_t  RESERVED9;
+  __IO uint16_t PSC;
+  uint16_t  RESERVED10;
+  __IO uint16_t ARR;
+  uint16_t  RESERVED11;
+  __IO uint16_t RCR;
+  uint16_t  RESERVED12;
+  __IO uint16_t CCR1;
+  uint16_t  RESERVED13;
+  __IO uint16_t CCR2;
+  uint16_t  RESERVED14;
+  __IO uint16_t CCR3;
+  uint16_t  RESERVED15;
+  __IO uint16_t CCR4;
+  uint16_t  RESERVED16;
+  __IO uint16_t BDTR;
+  uint16_t  RESERVED17;
+  __IO uint16_t DCR;
+  uint16_t  RESERVED18;
+  __IO uint16_t DMAR;
+  uint16_t  RESERVED19;
+} TIM_TypeDef;
+
+/** 
+  * @brief Universal Synchronous Asynchronous Receiver Transmitter
+  */
+ 
+typedef struct
+{
+  __IO uint16_t SR;
+  uint16_t  RESERVED0;
+  __IO uint16_t DR;
+  uint16_t  RESERVED1;
+  __IO uint16_t BRR;
+  uint16_t  RESERVED2;
+  __IO uint16_t CR1;
+  uint16_t  RESERVED3;
+  __IO uint16_t CR2;
+  uint16_t  RESERVED4;
+  __IO uint16_t CR3;
+  uint16_t  RESERVED5;
+  __IO uint16_t GTPR;
+  uint16_t  RESERVED6;
+} USART_TypeDef;
+
+/** 
+  * @brief Window WATCHDOG
+  */
+
+typedef struct
+{
+  __IO uint32_t CR;
+  __IO uint32_t CFR;
+  __IO uint32_t SR;
+} WWDG_TypeDef;
+
+/**
+  * @}
+  */
+  
+/** @addtogroup Peripheral_memory_map
+  * @{
+  */
+
+
+#define FLASH_BASE            ((uint32_t)0x08000000) /*!< FLASH base address in the alias region */
+#define SRAM_BASE             ((uint32_t)0x20000000) /*!< SRAM base address in the alias region */
+#define PERIPH_BASE           ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */
+
+#define SRAM_BB_BASE          ((uint32_t)0x22000000) /*!< SRAM base address in the bit-band region */
+#define PERIPH_BB_BASE        ((uint32_t)0x42000000) /*!< Peripheral base address in the bit-band region */
+
+#define FSMC_R_BASE           ((uint32_t)0xA0000000) /*!< FSMC registers base address */
+
+/*!< Peripheral memory map */
+#define APB1PERIPH_BASE       PERIPH_BASE
+#define APB2PERIPH_BASE       (PERIPH_BASE + 0x10000)
+#define AHBPERIPH_BASE        (PERIPH_BASE + 0x20000)
+
+#define TIM2_BASE             (APB1PERIPH_BASE + 0x0000)
+#define TIM3_BASE             (APB1PERIPH_BASE + 0x0400)
+#define TIM4_BASE             (APB1PERIPH_BASE + 0x0800)
+#define TIM5_BASE             (APB1PERIPH_BASE + 0x0C00)
+#define TIM6_BASE             (APB1PERIPH_BASE + 0x1000)
+#define TIM7_BASE             (APB1PERIPH_BASE + 0x1400)
+#define TIM12_BASE            (APB1PERIPH_BASE + 0x1800)
+#define TIM13_BASE            (APB1PERIPH_BASE + 0x1C00)
+#define TIM14_BASE            (APB1PERIPH_BASE + 0x2000)
+#define RTC_BASE              (APB1PERIPH_BASE + 0x2800)
+#define WWDG_BASE             (APB1PERIPH_BASE + 0x2C00)
+#define IWDG_BASE             (APB1PERIPH_BASE + 0x3000)
+#define SPI2_BASE             (APB1PERIPH_BASE + 0x3800)
+#define SPI3_BASE             (APB1PERIPH_BASE + 0x3C00)
+#define USART2_BASE           (APB1PERIPH_BASE + 0x4400)
+#define USART3_BASE           (APB1PERIPH_BASE + 0x4800)
+#define UART4_BASE            (APB1PERIPH_BASE + 0x4C00)
+#define UART5_BASE            (APB1PERIPH_BASE + 0x5000)
+#define I2C1_BASE             (APB1PERIPH_BASE + 0x5400)
+#define I2C2_BASE             (APB1PERIPH_BASE + 0x5800)
+#define CAN1_BASE             (APB1PERIPH_BASE + 0x6400)
+#define CAN2_BASE             (APB1PERIPH_BASE + 0x6800)
+#define BKP_BASE              (APB1PERIPH_BASE + 0x6C00)
+#define PWR_BASE              (APB1PERIPH_BASE + 0x7000)
+#define DAC_BASE              (APB1PERIPH_BASE + 0x7400)
+#define CEC_BASE              (APB1PERIPH_BASE + 0x7800)
+
+#define AFIO_BASE             (APB2PERIPH_BASE + 0x0000)
+#define EXTI_BASE             (APB2PERIPH_BASE + 0x0400)
+#define GPIOA_BASE            (APB2PERIPH_BASE + 0x0800)
+#define GPIOB_BASE            (APB2PERIPH_BASE + 0x0C00)
+#define GPIOC_BASE            (APB2PERIPH_BASE + 0x1000)
+#define GPIOD_BASE            (APB2PERIPH_BASE + 0x1400)
+#define GPIOE_BASE            (APB2PERIPH_BASE + 0x1800)
+#define GPIOF_BASE            (APB2PERIPH_BASE + 0x1C00)
+#define GPIOG_BASE            (APB2PERIPH_BASE + 0x2000)
+#define ADC1_BASE             (APB2PERIPH_BASE + 0x2400)
+#define ADC2_BASE             (APB2PERIPH_BASE + 0x2800)
+#define TIM1_BASE             (APB2PERIPH_BASE + 0x2C00)
+#define SPI1_BASE             (APB2PERIPH_BASE + 0x3000)
+#define TIM8_BASE             (APB2PERIPH_BASE + 0x3400)
+#define USART1_BASE           (APB2PERIPH_BASE + 0x3800)
+#define ADC3_BASE             (APB2PERIPH_BASE + 0x3C00)
+#define TIM15_BASE            (APB2PERIPH_BASE + 0x4000)
+#define TIM16_BASE            (APB2PERIPH_BASE + 0x4400)
+#define TIM17_BASE            (APB2PERIPH_BASE + 0x4800)
+#define TIM9_BASE             (APB2PERIPH_BASE + 0x4C00)
+#define TIM10_BASE            (APB2PERIPH_BASE + 0x5000)
+#define TIM11_BASE            (APB2PERIPH_BASE + 0x5400)
+
+#define SDIO_BASE             (PERIPH_BASE + 0x18000)
+
+#define DMA1_BASE             (AHBPERIPH_BASE + 0x0000)
+#define DMA1_Channel1_BASE    (AHBPERIPH_BASE + 0x0008)
+#define DMA1_Channel2_BASE    (AHBPERIPH_BASE + 0x001C)
+#define DMA1_Channel3_BASE    (AHBPERIPH_BASE + 0x0030)
+#define DMA1_Channel4_BASE    (AHBPERIPH_BASE + 0x0044)
+#define DMA1_Channel5_BASE    (AHBPERIPH_BASE + 0x0058)
+#define DMA1_Channel6_BASE    (AHBPERIPH_BASE + 0x006C)
+#define DMA1_Channel7_BASE    (AHBPERIPH_BASE + 0x0080)
+#define DMA2_BASE             (AHBPERIPH_BASE + 0x0400)
+#define DMA2_Channel1_BASE    (AHBPERIPH_BASE + 0x0408)
+#define DMA2_Channel2_BASE    (AHBPERIPH_BASE + 0x041C)
+#define DMA2_Channel3_BASE    (AHBPERIPH_BASE + 0x0430)
+#define DMA2_Channel4_BASE    (AHBPERIPH_BASE + 0x0444)
+#define DMA2_Channel5_BASE    (AHBPERIPH_BASE + 0x0458)
+#define RCC_BASE              (AHBPERIPH_BASE + 0x1000)
+#define CRC_BASE              (AHBPERIPH_BASE + 0x3000)
+
+#define FLASH_R_BASE          (AHBPERIPH_BASE + 0x2000) /*!< Flash registers base address */
+#define OB_BASE               ((uint32_t)0x1FFFF800)    /*!< Flash Option Bytes base address */
+
+#define ETH_BASE              (AHBPERIPH_BASE + 0x8000)
+#define ETH_MAC_BASE          (ETH_BASE)
+#define ETH_MMC_BASE          (ETH_BASE + 0x0100)
+#define ETH_PTP_BASE          (ETH_BASE + 0x0700)
+#define ETH_DMA_BASE          (ETH_BASE + 0x1000)
+
+#define FSMC_Bank1_R_BASE     (FSMC_R_BASE + 0x0000) /*!< FSMC Bank1 registers base address */
+#define FSMC_Bank1E_R_BASE    (FSMC_R_BASE + 0x0104) /*!< FSMC Bank1E registers base address */
+#define FSMC_Bank2_R_BASE     (FSMC_R_BASE + 0x0060) /*!< FSMC Bank2 registers base address */
+#define FSMC_Bank3_R_BASE     (FSMC_R_BASE + 0x0080) /*!< FSMC Bank3 registers base address */
+#define FSMC_Bank4_R_BASE     (FSMC_R_BASE + 0x00A0) /*!< FSMC Bank4 registers base address */
+
+#define DBGMCU_BASE          ((uint32_t)0xE0042000) /*!< Debug MCU registers base address */
+
+/**
+  * @}
+  */
+  
+/** @addtogroup Peripheral_declaration
+  * @{
+  */  
+
+#define TIM2                ((TIM_TypeDef *) TIM2_BASE)
+#define TIM3                ((TIM_TypeDef *) TIM3_BASE)
+#define TIM4                ((TIM_TypeDef *) TIM4_BASE)
+#define TIM5                ((TIM_TypeDef *) TIM5_BASE)
+#define TIM6                ((TIM_TypeDef *) TIM6_BASE)
+#define TIM7                ((TIM_TypeDef *) TIM7_BASE)
+#define TIM12               ((TIM_TypeDef *) TIM12_BASE)
+#define TIM13               ((TIM_TypeDef *) TIM13_BASE)
+#define TIM14               ((TIM_TypeDef *) TIM14_BASE)
+#define RTC                 ((RTC_TypeDef *) RTC_BASE)
+#define WWDG                ((WWDG_TypeDef *) WWDG_BASE)
+#define IWDG                ((IWDG_TypeDef *) IWDG_BASE)
+#define SPI2                ((SPI_TypeDef *) SPI2_BASE)
+#define SPI3                ((SPI_TypeDef *) SPI3_BASE)
+#define USART2              ((USART_TypeDef *) USART2_BASE)
+#define USART3              ((USART_TypeDef *) USART3_BASE)
+#define UART4               ((USART_TypeDef *) UART4_BASE)
+#define UART5               ((USART_TypeDef *) UART5_BASE)
+#define I2C1                ((I2C_TypeDef *) I2C1_BASE)
+#define I2C2                ((I2C_TypeDef *) I2C2_BASE)
+#define CAN1                ((CAN_TypeDef *) CAN1_BASE)
+#define CAN2                ((CAN_TypeDef *) CAN2_BASE)
+#define BKP                 ((BKP_TypeDef *) BKP_BASE)
+#define PWR                 ((PWR_TypeDef *) PWR_BASE)
+#define DAC                 ((DAC_TypeDef *) DAC_BASE)
+#define CEC                 ((CEC_TypeDef *) CEC_BASE)
+#define AFIO                ((AFIO_TypeDef *) AFIO_BASE)
+#define EXTI                ((EXTI_TypeDef *) EXTI_BASE)
+#define GPIOA               ((GPIO_TypeDef *) GPIOA_BASE)
+#define GPIOB               ((GPIO_TypeDef *) GPIOB_BASE)
+#define GPIOC               ((GPIO_TypeDef *) GPIOC_BASE)
+#define GPIOD               ((GPIO_TypeDef *) GPIOD_BASE)
+#define GPIOE               ((GPIO_TypeDef *) GPIOE_BASE)
+#define GPIOF               ((GPIO_TypeDef *) GPIOF_BASE)
+#define GPIOG               ((GPIO_TypeDef *) GPIOG_BASE)
+#define ADC1                ((ADC_TypeDef *) ADC1_BASE)
+#define ADC2                ((ADC_TypeDef *) ADC2_BASE)
+#define TIM1                ((TIM_TypeDef *) TIM1_BASE)
+#define SPI1                ((SPI_TypeDef *) SPI1_BASE)
+#define TIM8                ((TIM_TypeDef *) TIM8_BASE)
+#define USART1              ((USART_TypeDef *) USART1_BASE)
+#define ADC3                ((ADC_TypeDef *) ADC3_BASE)
+#define TIM15               ((TIM_TypeDef *) TIM15_BASE)
+#define TIM16               ((TIM_TypeDef *) TIM16_BASE)
+#define TIM17               ((TIM_TypeDef *) TIM17_BASE)
+#define TIM9                ((TIM_TypeDef *) TIM9_BASE)
+#define TIM10               ((TIM_TypeDef *) TIM10_BASE)
+#define TIM11               ((TIM_TypeDef *) TIM11_BASE)
+#define SDIO                ((SDIO_TypeDef *) SDIO_BASE)
+#define DMA1                ((DMA_TypeDef *) DMA1_BASE)
+#define DMA2                ((DMA_TypeDef *) DMA2_BASE)
+#define DMA1_Channel1       ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)
+#define DMA1_Channel2       ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)
+#define DMA1_Channel3       ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)
+#define DMA1_Channel4       ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)
+#define DMA1_Channel5       ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)
+#define DMA1_Channel6       ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE)
+#define DMA1_Channel7       ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE)
+#define DMA2_Channel1       ((DMA_Channel_TypeDef *) DMA2_Channel1_BASE)
+#define DMA2_Channel2       ((DMA_Channel_TypeDef *) DMA2_Channel2_BASE)
+#define DMA2_Channel3       ((DMA_Channel_TypeDef *) DMA2_Channel3_BASE)
+#define DMA2_Channel4       ((DMA_Channel_TypeDef *) DMA2_Channel4_BASE)
+#define DMA2_Channel5       ((DMA_Channel_TypeDef *) DMA2_Channel5_BASE)
+#define RCC                 ((RCC_TypeDef *) RCC_BASE)
+#define CRC                 ((CRC_TypeDef *) CRC_BASE)
+#define FLASH               ((FLASH_TypeDef *) FLASH_R_BASE)
+#define OB                  ((OB_TypeDef *) OB_BASE) 
+#define ETH                 ((ETH_TypeDef *) ETH_BASE)
+#define FSMC_Bank1          ((FSMC_Bank1_TypeDef *) FSMC_Bank1_R_BASE)
+#define FSMC_Bank1E         ((FSMC_Bank1E_TypeDef *) FSMC_Bank1E_R_BASE)
+#define FSMC_Bank2          ((FSMC_Bank2_TypeDef *) FSMC_Bank2_R_BASE)
+#define FSMC_Bank3          ((FSMC_Bank3_TypeDef *) FSMC_Bank3_R_BASE)
+#define FSMC_Bank4          ((FSMC_Bank4_TypeDef *) FSMC_Bank4_R_BASE)
+#define DBGMCU              ((DBGMCU_TypeDef *) DBGMCU_BASE)
+
+/**
+  * @}
+  */
+
+/** @addtogroup Exported_constants
+  * @{
+  */
+  
+  /** @addtogroup Peripheral_Registers_Bits_Definition
+  * @{
+  */
+    
+/******************************************************************************/
+/*                         Peripheral Registers_Bits_Definition               */
+/******************************************************************************/
+
+/******************************************************************************/
+/*                                                                            */
+/*                          CRC calculation unit                              */
+/*                                                                            */
+/******************************************************************************/
+
+/*******************  Bit definition for CRC_DR register  *********************/
+#define  CRC_DR_DR                           ((uint32_t)0xFFFFFFFF) /*!< Data register bits */
+
+
+/*******************  Bit definition for CRC_IDR register  ********************/
+#define  CRC_IDR_IDR                         ((uint8_t)0xFF)        /*!< General-purpose 8-bit data register bits */
+
+
+/********************  Bit definition for CRC_CR register  ********************/
+#define  CRC_CR_RESET                        ((uint8_t)0x01)        /*!< RESET bit */
+
+/******************************************************************************/
+/*                                                                            */
+/*                             Power Control                                  */
+/*                                                                            */
+/******************************************************************************/
+
+/********************  Bit definition for PWR_CR register  ********************/
+#define  PWR_CR_LPDS                         ((uint16_t)0x0001)     /*!< Low-Power Deepsleep */
+#define  PWR_CR_PDDS                         ((uint16_t)0x0002)     /*!< Power Down Deepsleep */
+#define  PWR_CR_CWUF                         ((uint16_t)0x0004)     /*!< Clear Wakeup Flag */
+#define  PWR_CR_CSBF                         ((uint16_t)0x0008)     /*!< Clear Standby Flag */
+#define  PWR_CR_PVDE                         ((uint16_t)0x0010)     /*!< Power Voltage Detector Enable */
+
+#define  PWR_CR_PLS                          ((uint16_t)0x00E0)     /*!< PLS[2:0] bits (PVD Level Selection) */
+#define  PWR_CR_PLS_0                        ((uint16_t)0x0020)     /*!< Bit 0 */
+#define  PWR_CR_PLS_1                        ((uint16_t)0x0040)     /*!< Bit 1 */
+#define  PWR_CR_PLS_2                        ((uint16_t)0x0080)     /*!< Bit 2 */
+
+/*!< PVD level configuration */
+#define  PWR_CR_PLS_2V2                      ((uint16_t)0x0000)     /*!< PVD level 2.2V */
+#define  PWR_CR_PLS_2V3                      ((uint16_t)0x0020)     /*!< PVD level 2.3V */
+#define  PWR_CR_PLS_2V4                      ((uint16_t)0x0040)     /*!< PVD level 2.4V */
+#define  PWR_CR_PLS_2V5                      ((uint16_t)0x0060)     /*!< PVD level 2.5V */
+#define  PWR_CR_PLS_2V6                      ((uint16_t)0x0080)     /*!< PVD level 2.6V */
+#define  PWR_CR_PLS_2V7                      ((uint16_t)0x00A0)     /*!< PVD level 2.7V */
+#define  PWR_CR_PLS_2V8                      ((uint16_t)0x00C0)     /*!< PVD level 2.8V */
+#define  PWR_CR_PLS_2V9                      ((uint16_t)0x00E0)     /*!< PVD level 2.9V */
+
+#define  PWR_CR_DBP                          ((uint16_t)0x0100)     /*!< Disable Backup Domain write protection */
+
+
+/*******************  Bit definition for PWR_CSR register  ********************/
+#define  PWR_CSR_WUF                         ((uint16_t)0x0001)     /*!< Wakeup Flag */
+#define  PWR_CSR_SBF                         ((uint16_t)0x0002)     /*!< Standby Flag */
+#define  PWR_CSR_PVDO                        ((uint16_t)0x0004)     /*!< PVD Output */
+#define  PWR_CSR_EWUP                        ((uint16_t)0x0100)     /*!< Enable WKUP pin */
+
+/******************************************************************************/
+/*                                                                            */
+/*                            Backup registers                                */
+/*                                                                            */
+/******************************************************************************/
+
+/*******************  Bit definition for BKP_DR1 register  ********************/
+#define  BKP_DR1_D                           ((uint16_t)0xFFFF)     /*!< Backup data */
+
+/*******************  Bit definition for BKP_DR2 register  ********************/
+#define  BKP_DR2_D                           ((uint16_t)0xFFFF)     /*!< Backup data */
+
+/*******************  Bit definition for BKP_DR3 register  ********************/
+#define  BKP_DR3_D                           ((uint16_t)0xFFFF)     /*!< Backup data */
+
+/*******************  Bit definition for BKP_DR4 register  ********************/
+#define  BKP_DR4_D                           ((uint16_t)0xFFFF)     /*!< Backup data */
+
+/*******************  Bit definition for BKP_DR5 register  ********************/
+#define  BKP_DR5_D                           ((uint16_t)0xFFFF)     /*!< Backup data */
+
+/*******************  Bit definition for BKP_DR6 register  ********************/
+#define  BKP_DR6_D                           ((uint16_t)0xFFFF)     /*!< Backup data */
+
+/*******************  Bit definition for BKP_DR7 register  ********************/
+#define  BKP_DR7_D                           ((uint16_t)0xFFFF)     /*!< Backup data */
+
+/*******************  Bit definition for BKP_DR8 register  ********************/
+#define  BKP_DR8_D                           ((uint16_t)0xFFFF)     /*!< Backup data */
+
+/*******************  Bit definition for BKP_DR9 register  ********************/
+#define  BKP_DR9_D                           ((uint16_t)0xFFFF)     /*!< Backup data */
+
+/*******************  Bit definition for BKP_DR10 register  *******************/
+#define  BKP_DR10_D                          ((uint16_t)0xFFFF)     /*!< Backup data */
+
+/*******************  Bit definition for BKP_DR11 register  *******************/
+#define  BKP_DR11_D                          ((uint16_t)0xFFFF)     /*!< Backup data */
+
+/*******************  Bit definition for BKP_DR12 register  *******************/
+#define  BKP_DR12_D                          ((uint16_t)0xFFFF)     /*!< Backup data */
+
+/*******************  Bit definition for BKP_DR13 register  *******************/
+#define  BKP_DR13_D                          ((uint16_t)0xFFFF)     /*!< Backup data */
+
+/*******************  Bit definition for BKP_DR14 register  *******************/
+#define  BKP_DR14_D                          ((uint16_t)0xFFFF)     /*!< Backup data */
+
+/*******************  Bit definition for BKP_DR15 register  *******************/
+#define  BKP_DR15_D                          ((uint16_t)0xFFFF)     /*!< Backup data */
+
+/*******************  Bit definition for BKP_DR16 register  *******************/
+#define  BKP_DR16_D                          ((uint16_t)0xFFFF)     /*!< Backup data */
+
+/*******************  Bit definition for BKP_DR17 register  *******************/
+#define  BKP_DR17_D                          ((uint16_t)0xFFFF)     /*!< Backup data */
+
+/******************  Bit definition for BKP_DR18 register  ********************/
+#define  BKP_DR18_D                          ((uint16_t)0xFFFF)     /*!< Backup data */
+
+/*******************  Bit definition for BKP_DR19 register  *******************/
+#define  BKP_DR19_D                          ((uint16_t)0xFFFF)     /*!< Backup data */
+
+/*******************  Bit definition for BKP_DR20 register  *******************/
+#define  BKP_DR20_D                          ((uint16_t)0xFFFF)     /*!< Backup data */
+
+/*******************  Bit definition for BKP_DR21 register  *******************/
+#define  BKP_DR21_D                          ((uint16_t)0xFFFF)     /*!< Backup data */
+
+/*******************  Bit definition for BKP_DR22 register  *******************/
+#define  BKP_DR22_D                          ((uint16_t)0xFFFF)     /*!< Backup data */
+
+/*******************  Bit definition for BKP_DR23 register  *******************/
+#define  BKP_DR23_D                          ((uint16_t)0xFFFF)     /*!< Backup data */
+
+/*******************  Bit definition for BKP_DR24 register  *******************/
+#define  BKP_DR24_D                          ((uint16_t)0xFFFF)     /*!< Backup data */
+
+/*******************  Bit definition for BKP_DR25 register  *******************/
+#define  BKP_DR25_D                          ((uint16_t)0xFFFF)     /*!< Backup data */
+
+/*******************  Bit definition for BKP_DR26 register  *******************/
+#define  BKP_DR26_D                          ((uint16_t)0xFFFF)     /*!< Backup data */
+
+/*******************  Bit definition for BKP_DR27 register  *******************/
+#define  BKP_DR27_D                          ((uint16_t)0xFFFF)     /*!< Backup data */
+
+/*******************  Bit definition for BKP_DR28 register  *******************/
+#define  BKP_DR28_D                          ((uint16_t)0xFFFF)     /*!< Backup data */
+
+/*******************  Bit definition for BKP_DR29 register  *******************/
+#define  BKP_DR29_D                          ((uint16_t)0xFFFF)     /*!< Backup data */
+
+/*******************  Bit definition for BKP_DR30 register  *******************/
+#define  BKP_DR30_D                          ((uint16_t)0xFFFF)     /*!< Backup data */
+
+/*******************  Bit definition for BKP_DR31 register  *******************/
+#define  BKP_DR31_D                          ((uint16_t)0xFFFF)     /*!< Backup data */
+
+/*******************  Bit definition for BKP_DR32 register  *******************/
+#define  BKP_DR32_D                          ((uint16_t)0xFFFF)     /*!< Backup data */
+
+/*******************  Bit definition for BKP_DR33 register  *******************/
+#define  BKP_DR33_D                          ((uint16_t)0xFFFF)     /*!< Backup data */
+
+/*******************  Bit definition for BKP_DR34 register  *******************/
+#define  BKP_DR34_D                          ((uint16_t)0xFFFF)     /*!< Backup data */
+
+/*******************  Bit definition for BKP_DR35 register  *******************/
+#define  BKP_DR35_D                          ((uint16_t)0xFFFF)     /*!< Backup data */
+
+/*******************  Bit definition for BKP_DR36 register  *******************/
+#define  BKP_DR36_D                          ((uint16_t)0xFFFF)     /*!< Backup data */
+
+/*******************  Bit definition for BKP_DR37 register  *******************/
+#define  BKP_DR37_D                          ((uint16_t)0xFFFF)     /*!< Backup data */
+
+/*******************  Bit definition for BKP_DR38 register  *******************/
+#define  BKP_DR38_D                          ((uint16_t)0xFFFF)     /*!< Backup data */
+
+/*******************  Bit definition for BKP_DR39 register  *******************/
+#define  BKP_DR39_D                          ((uint16_t)0xFFFF)     /*!< Backup data */
+
+/*******************  Bit definition for BKP_DR40 register  *******************/
+#define  BKP_DR40_D                          ((uint16_t)0xFFFF)     /*!< Backup data */
+
+/*******************  Bit definition for BKP_DR41 register  *******************/
+#define  BKP_DR41_D                          ((uint16_t)0xFFFF)     /*!< Backup data */
+
+/*******************  Bit definition for BKP_DR42 register  *******************/
+#define  BKP_DR42_D                          ((uint16_t)0xFFFF)     /*!< Backup data */
+
+/******************  Bit definition for BKP_RTCCR register  *******************/
+#define  BKP_RTCCR_CAL                       ((uint16_t)0x007F)     /*!< Calibration value */
+#define  BKP_RTCCR_CCO                       ((uint16_t)0x0080)     /*!< Calibration Clock Output */
+#define  BKP_RTCCR_ASOE                      ((uint16_t)0x0100)     /*!< Alarm or Second Output Enable */
+#define  BKP_RTCCR_ASOS                      ((uint16_t)0x0200)     /*!< Alarm or Second Output Selection */
+
+/********************  Bit definition for BKP_CR register  ********************/
+#define  BKP_CR_TPE                          ((uint8_t)0x01)        /*!< TAMPER pin enable */
+#define  BKP_CR_TPAL                         ((uint8_t)0x02)        /*!< TAMPER pin active level */
+
+/*******************  Bit definition for BKP_CSR register  ********************/
+#define  BKP_CSR_CTE                         ((uint16_t)0x0001)     /*!< Clear Tamper event */
+#define  BKP_CSR_CTI                         ((uint16_t)0x0002)     /*!< Clear Tamper Interrupt */
+#define  BKP_CSR_TPIE                        ((uint16_t)0x0004)     /*!< TAMPER Pin interrupt enable */
+#define  BKP_CSR_TEF                         ((uint16_t)0x0100)     /*!< Tamper Event Flag */
+#define  BKP_CSR_TIF                         ((uint16_t)0x0200)     /*!< Tamper Interrupt Flag */
+
+/******************************************************************************/
+/*                                                                            */
+/*                         Reset and Clock Control                            */
+/*                                                                            */
+/******************************************************************************/
+
+/********************  Bit definition for RCC_CR register  ********************/
+#define  RCC_CR_HSION                        ((uint32_t)0x00000001)        /*!< Internal High Speed clock enable */
+#define  RCC_CR_HSIRDY                       ((uint32_t)0x00000002)        /*!< Internal High Speed clock ready flag */
+#define  RCC_CR_HSITRIM                      ((uint32_t)0x000000F8)        /*!< Internal High Speed clock trimming */
+#define  RCC_CR_HSICAL                       ((uint32_t)0x0000FF00)        /*!< Internal High Speed clock Calibration */
+#define  RCC_CR_HSEON                        ((uint32_t)0x00010000)        /*!< External High Speed clock enable */
+#define  RCC_CR_HSERDY                       ((uint32_t)0x00020000)        /*!< External High Speed clock ready flag */
+#define  RCC_CR_HSEBYP                       ((uint32_t)0x00040000)        /*!< External High Speed clock Bypass */
+#define  RCC_CR_CSSON                        ((uint32_t)0x00080000)        /*!< Clock Security System enable */
+#define  RCC_CR_PLLON                        ((uint32_t)0x01000000)        /*!< PLL enable */
+#define  RCC_CR_PLLRDY                       ((uint32_t)0x02000000)        /*!< PLL clock ready flag */
+
+#ifdef STM32F10X_CL
+ #define  RCC_CR_PLL2ON                       ((uint32_t)0x04000000)        /*!< PLL2 enable */
+ #define  RCC_CR_PLL2RDY                      ((uint32_t)0x08000000)        /*!< PLL2 clock ready flag */
+ #define  RCC_CR_PLL3ON                       ((uint32_t)0x10000000)        /*!< PLL3 enable */
+ #define  RCC_CR_PLL3RDY                      ((uint32_t)0x20000000)        /*!< PLL3 clock ready flag */
+#endif /* STM32F10X_CL */
+
+/*******************  Bit definition for RCC_CFGR register  *******************/
+/*!< SW configuration */
+#define  RCC_CFGR_SW                         ((uint32_t)0x00000003)        /*!< SW[1:0] bits (System clock Switch) */
+#define  RCC_CFGR_SW_0                       ((uint32_t)0x00000001)        /*!< Bit 0 */
+#define  RCC_CFGR_SW_1                       ((uint32_t)0x00000002)        /*!< Bit 1 */
+
+#define  RCC_CFGR_SW_HSI                     ((uint32_t)0x00000000)        /*!< HSI selected as system clock */
+#define  RCC_CFGR_SW_HSE                     ((uint32_t)0x00000001)        /*!< HSE selected as system clock */
+#define  RCC_CFGR_SW_PLL                     ((uint32_t)0x00000002)        /*!< PLL selected as system clock */
+
+/*!< SWS configuration */
+#define  RCC_CFGR_SWS                        ((uint32_t)0x0000000C)        /*!< SWS[1:0] bits (System Clock Switch Status) */
+#define  RCC_CFGR_SWS_0                      ((uint32_t)0x00000004)        /*!< Bit 0 */
+#define  RCC_CFGR_SWS_1                      ((uint32_t)0x00000008)        /*!< Bit 1 */
+
+#define  RCC_CFGR_SWS_HSI                    ((uint32_t)0x00000000)        /*!< HSI oscillator used as system clock */
+#define  RCC_CFGR_SWS_HSE                    ((uint32_t)0x00000004)        /*!< HSE oscillator used as system clock */
+#define  RCC_CFGR_SWS_PLL                    ((uint32_t)0x00000008)        /*!< PLL used as system clock */
+
+/*!< HPRE configuration */
+#define  RCC_CFGR_HPRE                       ((uint32_t)0x000000F0)        /*!< HPRE[3:0] bits (AHB prescaler) */
+#define  RCC_CFGR_HPRE_0                     ((uint32_t)0x00000010)        /*!< Bit 0 */
+#define  RCC_CFGR_HPRE_1                     ((uint32_t)0x00000020)        /*!< Bit 1 */
+#define  RCC_CFGR_HPRE_2                     ((uint32_t)0x00000040)        /*!< Bit 2 */
+#define  RCC_CFGR_HPRE_3                     ((uint32_t)0x00000080)        /*!< Bit 3 */
+
+#define  RCC_CFGR_HPRE_DIV1                  ((uint32_t)0x00000000)        /*!< SYSCLK not divided */
+#define  RCC_CFGR_HPRE_DIV2                  ((uint32_t)0x00000080)        /*!< SYSCLK divided by 2 */
+#define  RCC_CFGR_HPRE_DIV4                  ((uint32_t)0x00000090)        /*!< SYSCLK divided by 4 */
+#define  RCC_CFGR_HPRE_DIV8                  ((uint32_t)0x000000A0)        /*!< SYSCLK divided by 8 */
+#define  RCC_CFGR_HPRE_DIV16                 ((uint32_t)0x000000B0)        /*!< SYSCLK divided by 16 */
+#define  RCC_CFGR_HPRE_DIV64                 ((uint32_t)0x000000C0)        /*!< SYSCLK divided by 64 */
+#define  RCC_CFGR_HPRE_DIV128                ((uint32_t)0x000000D0)        /*!< SYSCLK divided by 128 */
+#define  RCC_CFGR_HPRE_DIV256                ((uint32_t)0x000000E0)        /*!< SYSCLK divided by 256 */
+#define  RCC_CFGR_HPRE_DIV512                ((uint32_t)0x000000F0)        /*!< SYSCLK divided by 512 */
+
+/*!< PPRE1 configuration */
+#define  RCC_CFGR_PPRE1                      ((uint32_t)0x00000700)        /*!< PRE1[2:0] bits (APB1 prescaler) */
+#define  RCC_CFGR_PPRE1_0                    ((uint32_t)0x00000100)        /*!< Bit 0 */
+#define  RCC_CFGR_PPRE1_1                    ((uint32_t)0x00000200)        /*!< Bit 1 */
+#define  RCC_CFGR_PPRE1_2                    ((uint32_t)0x00000400)        /*!< Bit 2 */
+
+#define  RCC_CFGR_PPRE1_DIV1                 ((uint32_t)0x00000000)        /*!< HCLK not divided */
+#define  RCC_CFGR_PPRE1_DIV2                 ((uint32_t)0x00000400)        /*!< HCLK divided by 2 */
+#define  RCC_CFGR_PPRE1_DIV4                 ((uint32_t)0x00000500)        /*!< HCLK divided by 4 */
+#define  RCC_CFGR_PPRE1_DIV8                 ((uint32_t)0x00000600)        /*!< HCLK divided by 8 */
+#define  RCC_CFGR_PPRE1_DIV16                ((uint32_t)0x00000700)        /*!< HCLK divided by 16 */
+
+/*!< PPRE2 configuration */
+#define  RCC_CFGR_PPRE2                      ((uint32_t)0x00003800)        /*!< PRE2[2:0] bits (APB2 prescaler) */
+#define  RCC_CFGR_PPRE2_0                    ((uint32_t)0x00000800)        /*!< Bit 0 */
+#define  RCC_CFGR_PPRE2_1                    ((uint32_t)0x00001000)        /*!< Bit 1 */
+#define  RCC_CFGR_PPRE2_2                    ((uint32_t)0x00002000)        /*!< Bit 2 */
+
+#define  RCC_CFGR_PPRE2_DIV1                 ((uint32_t)0x00000000)        /*!< HCLK not divided */
+#define  RCC_CFGR_PPRE2_DIV2                 ((uint32_t)0x00002000)        /*!< HCLK divided by 2 */
+#define  RCC_CFGR_PPRE2_DIV4                 ((uint32_t)0x00002800)        /*!< HCLK divided by 4 */
+#define  RCC_CFGR_PPRE2_DIV8                 ((uint32_t)0x00003000)        /*!< HCLK divided by 8 */
+#define  RCC_CFGR_PPRE2_DIV16                ((uint32_t)0x00003800)        /*!< HCLK divided by 16 */
+
+/*!< ADCPPRE configuration */
+#define  RCC_CFGR_ADCPRE                     ((uint32_t)0x0000C000)        /*!< ADCPRE[1:0] bits (ADC prescaler) */
+#define  RCC_CFGR_ADCPRE_0                   ((uint32_t)0x00004000)        /*!< Bit 0 */
+#define  RCC_CFGR_ADCPRE_1                   ((uint32_t)0x00008000)        /*!< Bit 1 */
+
+#define  RCC_CFGR_ADCPRE_DIV2                ((uint32_t)0x00000000)        /*!< PCLK2 divided by 2 */
+#define  RCC_CFGR_ADCPRE_DIV4                ((uint32_t)0x00004000)        /*!< PCLK2 divided by 4 */
+#define  RCC_CFGR_ADCPRE_DIV6                ((uint32_t)0x00008000)        /*!< PCLK2 divided by 6 */
+#define  RCC_CFGR_ADCPRE_DIV8                ((uint32_t)0x0000C000)        /*!< PCLK2 divided by 8 */
+
+#define  RCC_CFGR_PLLSRC                     ((uint32_t)0x00010000)        /*!< PLL entry clock source */
+
+#define  RCC_CFGR_PLLXTPRE                   ((uint32_t)0x00020000)        /*!< HSE divider for PLL entry */
+
+/*!< PLLMUL configuration */
+#define  RCC_CFGR_PLLMULL                    ((uint32_t)0x003C0000)        /*!< PLLMUL[3:0] bits (PLL multiplication factor) */
+#define  RCC_CFGR_PLLMULL_0                  ((uint32_t)0x00040000)        /*!< Bit 0 */
+#define  RCC_CFGR_PLLMULL_1                  ((uint32_t)0x00080000)        /*!< Bit 1 */
+#define  RCC_CFGR_PLLMULL_2                  ((uint32_t)0x00100000)        /*!< Bit 2 */
+#define  RCC_CFGR_PLLMULL_3                  ((uint32_t)0x00200000)        /*!< Bit 3 */
+
+#ifdef STM32F10X_CL
+ #define  RCC_CFGR_PLLSRC_HSI_Div2           ((uint32_t)0x00000000)        /*!< HSI clock divided by 2 selected as PLL entry clock source */
+ #define  RCC_CFGR_PLLSRC_PREDIV1            ((uint32_t)0x00010000)        /*!< PREDIV1 clock selected as PLL entry clock source */
+
+ #define  RCC_CFGR_PLLXTPRE_PREDIV1          ((uint32_t)0x00000000)        /*!< PREDIV1 clock not divided for PLL entry */
+ #define  RCC_CFGR_PLLXTPRE_PREDIV1_Div2     ((uint32_t)0x00020000)        /*!< PREDIV1 clock divided by 2 for PLL entry */
+
+ #define  RCC_CFGR_PLLMULL4                  ((uint32_t)0x00080000)        /*!< PLL input clock * 4 */
+ #define  RCC_CFGR_PLLMULL5                  ((uint32_t)0x000C0000)        /*!< PLL input clock * 5 */
+ #define  RCC_CFGR_PLLMULL6                  ((uint32_t)0x00100000)        /*!< PLL input clock * 6 */
+ #define  RCC_CFGR_PLLMULL7                  ((uint32_t)0x00140000)        /*!< PLL input clock * 7 */
+ #define  RCC_CFGR_PLLMULL8                  ((uint32_t)0x00180000)        /*!< PLL input clock * 8 */
+ #define  RCC_CFGR_PLLMULL9                  ((uint32_t)0x001C0000)        /*!< PLL input clock * 9 */
+ #define  RCC_CFGR_PLLMULL6_5                ((uint32_t)0x00340000)        /*!< PLL input clock * 6.5 */
+ 
+ #define  RCC_CFGR_OTGFSPRE                  ((uint32_t)0x00400000)        /*!< USB OTG FS prescaler */
+ 
+/*!< MCO configuration */
+ #define  RCC_CFGR_MCO                       ((uint32_t)0x0F000000)        /*!< MCO[3:0] bits (Microcontroller Clock Output) */
+ #define  RCC_CFGR_MCO_0                     ((uint32_t)0x01000000)        /*!< Bit 0 */
+ #define  RCC_CFGR_MCO_1                     ((uint32_t)0x02000000)        /*!< Bit 1 */
+ #define  RCC_CFGR_MCO_2                     ((uint32_t)0x04000000)        /*!< Bit 2 */
+ #define  RCC_CFGR_MCO_3                     ((uint32_t)0x08000000)        /*!< Bit 3 */
+
+ #define  RCC_CFGR_MCO_NOCLOCK               ((uint32_t)0x00000000)        /*!< No clock */
+ #define  RCC_CFGR_MCO_SYSCLK                ((uint32_t)0x04000000)        /*!< System clock selected as MCO source */
+ #define  RCC_CFGR_MCO_HSI                   ((uint32_t)0x05000000)        /*!< HSI clock selected as MCO source */
+ #define  RCC_CFGR_MCO_HSE                   ((uint32_t)0x06000000)        /*!< HSE clock selected as MCO source */
+ #define  RCC_CFGR_MCO_PLLCLK_Div2           ((uint32_t)0x07000000)        /*!< PLL clock divided by 2 selected as MCO source */
+ #define  RCC_CFGR_MCO_PLL2CLK               ((uint32_t)0x08000000)        /*!< PLL2 clock selected as MCO source*/
+ #define  RCC_CFGR_MCO_PLL3CLK_Div2          ((uint32_t)0x09000000)        /*!< PLL3 clock divided by 2 selected as MCO source*/
+ #define  RCC_CFGR_MCO_Ext_HSE               ((uint32_t)0x0A000000)        /*!< XT1 external 3-25 MHz oscillator clock selected as MCO source */
+ #define  RCC_CFGR_MCO_PLL3CLK               ((uint32_t)0x0B000000)        /*!< PLL3 clock selected as MCO source */
+#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
+ #define  RCC_CFGR_PLLSRC_HSI_Div2           ((uint32_t)0x00000000)        /*!< HSI clock divided by 2 selected as PLL entry clock source */
+ #define  RCC_CFGR_PLLSRC_PREDIV1            ((uint32_t)0x00010000)        /*!< PREDIV1 clock selected as PLL entry clock source */
+
+ #define  RCC_CFGR_PLLXTPRE_PREDIV1          ((uint32_t)0x00000000)        /*!< PREDIV1 clock not divided for PLL entry */
+ #define  RCC_CFGR_PLLXTPRE_PREDIV1_Div2     ((uint32_t)0x00020000)        /*!< PREDIV1 clock divided by 2 for PLL entry */
+
+ #define  RCC_CFGR_PLLMULL2                  ((uint32_t)0x00000000)        /*!< PLL input clock*2 */
+ #define  RCC_CFGR_PLLMULL3                  ((uint32_t)0x00040000)        /*!< PLL input clock*3 */
+ #define  RCC_CFGR_PLLMULL4                  ((uint32_t)0x00080000)        /*!< PLL input clock*4 */
+ #define  RCC_CFGR_PLLMULL5                  ((uint32_t)0x000C0000)        /*!< PLL input clock*5 */
+ #define  RCC_CFGR_PLLMULL6                  ((uint32_t)0x00100000)        /*!< PLL input clock*6 */
+ #define  RCC_CFGR_PLLMULL7                  ((uint32_t)0x00140000)        /*!< PLL input clock*7 */
+ #define  RCC_CFGR_PLLMULL8                  ((uint32_t)0x00180000)        /*!< PLL input clock*8 */
+ #define  RCC_CFGR_PLLMULL9                  ((uint32_t)0x001C0000)        /*!< PLL input clock*9 */
+ #define  RCC_CFGR_PLLMULL10                 ((uint32_t)0x00200000)        /*!< PLL input clock10 */
+ #define  RCC_CFGR_PLLMULL11                 ((uint32_t)0x00240000)        /*!< PLL input clock*11 */
+ #define  RCC_CFGR_PLLMULL12                 ((uint32_t)0x00280000)        /*!< PLL input clock*12 */
+ #define  RCC_CFGR_PLLMULL13                 ((uint32_t)0x002C0000)        /*!< PLL input clock*13 */
+ #define  RCC_CFGR_PLLMULL14                 ((uint32_t)0x00300000)        /*!< PLL input clock*14 */
+ #define  RCC_CFGR_PLLMULL15                 ((uint32_t)0x00340000)        /*!< PLL input clock*15 */
+ #define  RCC_CFGR_PLLMULL16                 ((uint32_t)0x00380000)        /*!< PLL input clock*16 */
+
+/*!< MCO configuration */
+ #define  RCC_CFGR_MCO                       ((uint32_t)0x07000000)        /*!< MCO[2:0] bits (Microcontroller Clock Output) */
+ #define  RCC_CFGR_MCO_0                     ((uint32_t)0x01000000)        /*!< Bit 0 */
+ #define  RCC_CFGR_MCO_1                     ((uint32_t)0x02000000)        /*!< Bit 1 */
+ #define  RCC_CFGR_MCO_2                     ((uint32_t)0x04000000)        /*!< Bit 2 */
+
+ #define  RCC_CFGR_MCO_NOCLOCK               ((uint32_t)0x00000000)        /*!< No clock */
+ #define  RCC_CFGR_MCO_SYSCLK                ((uint32_t)0x04000000)        /*!< System clock selected as MCO source */
+ #define  RCC_CFGR_MCO_HSI                   ((uint32_t)0x05000000)        /*!< HSI clock selected as MCO source */
+ #define  RCC_CFGR_MCO_HSE                   ((uint32_t)0x06000000)        /*!< HSE clock selected as MCO source  */
+ #define  RCC_CFGR_MCO_PLL                   ((uint32_t)0x07000000)        /*!< PLL clock divided by 2 selected as MCO source */
+#else
+ #define  RCC_CFGR_PLLSRC_HSI_Div2           ((uint32_t)0x00000000)        /*!< HSI clock divided by 2 selected as PLL entry clock source */
+ #define  RCC_CFGR_PLLSRC_HSE                ((uint32_t)0x00010000)        /*!< HSE clock selected as PLL entry clock source */
+
+ #define  RCC_CFGR_PLLXTPRE_HSE              ((uint32_t)0x00000000)        /*!< HSE clock not divided for PLL entry */
+ #define  RCC_CFGR_PLLXTPRE_HSE_Div2         ((uint32_t)0x00020000)        /*!< HSE clock divided by 2 for PLL entry */
+
+ #define  RCC_CFGR_PLLMULL2                  ((uint32_t)0x00000000)        /*!< PLL input clock*2 */
+ #define  RCC_CFGR_PLLMULL3                  ((uint32_t)0x00040000)        /*!< PLL input clock*3 */
+ #define  RCC_CFGR_PLLMULL4                  ((uint32_t)0x00080000)        /*!< PLL input clock*4 */
+ #define  RCC_CFGR_PLLMULL5                  ((uint32_t)0x000C0000)        /*!< PLL input clock*5 */
+ #define  RCC_CFGR_PLLMULL6                  ((uint32_t)0x00100000)        /*!< PLL input clock*6 */
+ #define  RCC_CFGR_PLLMULL7                  ((uint32_t)0x00140000)        /*!< PLL input clock*7 */
+ #define  RCC_CFGR_PLLMULL8                  ((uint32_t)0x00180000)        /*!< PLL input clock*8 */
+ #define  RCC_CFGR_PLLMULL9                  ((uint32_t)0x001C0000)        /*!< PLL input clock*9 */
+ #define  RCC_CFGR_PLLMULL10                 ((uint32_t)0x00200000)        /*!< PLL input clock10 */
+ #define  RCC_CFGR_PLLMULL11                 ((uint32_t)0x00240000)        /*!< PLL input clock*11 */
+ #define  RCC_CFGR_PLLMULL12                 ((uint32_t)0x00280000)        /*!< PLL input clock*12 */
+ #define  RCC_CFGR_PLLMULL13                 ((uint32_t)0x002C0000)        /*!< PLL input clock*13 */
+ #define  RCC_CFGR_PLLMULL14                 ((uint32_t)0x00300000)        /*!< PLL input clock*14 */
+ #define  RCC_CFGR_PLLMULL15                 ((uint32_t)0x00340000)        /*!< PLL input clock*15 */
+ #define  RCC_CFGR_PLLMULL16                 ((uint32_t)0x00380000)        /*!< PLL input clock*16 */
+ #define  RCC_CFGR_USBPRE                    ((uint32_t)0x00400000)        /*!< USB Device prescaler */
+
+/*!< MCO configuration */
+ #define  RCC_CFGR_MCO                       ((uint32_t)0x07000000)        /*!< MCO[2:0] bits (Microcontroller Clock Output) */
+ #define  RCC_CFGR_MCO_0                     ((uint32_t)0x01000000)        /*!< Bit 0 */
+ #define  RCC_CFGR_MCO_1                     ((uint32_t)0x02000000)        /*!< Bit 1 */
+ #define  RCC_CFGR_MCO_2                     ((uint32_t)0x04000000)        /*!< Bit 2 */
+
+ #define  RCC_CFGR_MCO_NOCLOCK               ((uint32_t)0x00000000)        /*!< No clock */
+ #define  RCC_CFGR_MCO_SYSCLK                ((uint32_t)0x04000000)        /*!< System clock selected as MCO source */
+ #define  RCC_CFGR_MCO_HSI                   ((uint32_t)0x05000000)        /*!< HSI clock selected as MCO source */
+ #define  RCC_CFGR_MCO_HSE                   ((uint32_t)0x06000000)        /*!< HSE clock selected as MCO source  */
+ #define  RCC_CFGR_MCO_PLL                   ((uint32_t)0x07000000)        /*!< PLL clock divided by 2 selected as MCO source */
+#endif /* STM32F10X_CL */
+
+/*!<******************  Bit definition for RCC_CIR register  ********************/
+#define  RCC_CIR_LSIRDYF                     ((uint32_t)0x00000001)        /*!< LSI Ready Interrupt flag */
+#define  RCC_CIR_LSERDYF                     ((uint32_t)0x00000002)        /*!< LSE Ready Interrupt flag */
+#define  RCC_CIR_HSIRDYF                     ((uint32_t)0x00000004)        /*!< HSI Ready Interrupt flag */
+#define  RCC_CIR_HSERDYF                     ((uint32_t)0x00000008)        /*!< HSE Ready Interrupt flag */
+#define  RCC_CIR_PLLRDYF                     ((uint32_t)0x00000010)        /*!< PLL Ready Interrupt flag */
+#define  RCC_CIR_CSSF                        ((uint32_t)0x00000080)        /*!< Clock Security System Interrupt flag */
+#define  RCC_CIR_LSIRDYIE                    ((uint32_t)0x00000100)        /*!< LSI Ready Interrupt Enable */
+#define  RCC_CIR_LSERDYIE                    ((uint32_t)0x00000200)        /*!< LSE Ready Interrupt Enable */
+#define  RCC_CIR_HSIRDYIE                    ((uint32_t)0x00000400)        /*!< HSI Ready Interrupt Enable */
+#define  RCC_CIR_HSERDYIE                    ((uint32_t)0x00000800)        /*!< HSE Ready Interrupt Enable */
+#define  RCC_CIR_PLLRDYIE                    ((uint32_t)0x00001000)        /*!< PLL Ready Interrupt Enable */
+#define  RCC_CIR_LSIRDYC                     ((uint32_t)0x00010000)        /*!< LSI Ready Interrupt Clear */
+#define  RCC_CIR_LSERDYC                     ((uint32_t)0x00020000)        /*!< LSE Ready Interrupt Clear */
+#define  RCC_CIR_HSIRDYC                     ((uint32_t)0x00040000)        /*!< HSI Ready Interrupt Clear */
+#define  RCC_CIR_HSERDYC                     ((uint32_t)0x00080000)        /*!< HSE Ready Interrupt Clear */
+#define  RCC_CIR_PLLRDYC                     ((uint32_t)0x00100000)        /*!< PLL Ready Interrupt Clear */
+#define  RCC_CIR_CSSC                        ((uint32_t)0x00800000)        /*!< Clock Security System Interrupt Clear */
+
+#ifdef STM32F10X_CL
+ #define  RCC_CIR_PLL2RDYF                    ((uint32_t)0x00000020)        /*!< PLL2 Ready Interrupt flag */
+ #define  RCC_CIR_PLL3RDYF                    ((uint32_t)0x00000040)        /*!< PLL3 Ready Interrupt flag */
+ #define  RCC_CIR_PLL2RDYIE                   ((uint32_t)0x00002000)        /*!< PLL2 Ready Interrupt Enable */
+ #define  RCC_CIR_PLL3RDYIE                   ((uint32_t)0x00004000)        /*!< PLL3 Ready Interrupt Enable */
+ #define  RCC_CIR_PLL2RDYC                    ((uint32_t)0x00200000)        /*!< PLL2 Ready Interrupt Clear */
+ #define  RCC_CIR_PLL3RDYC                    ((uint32_t)0x00400000)        /*!< PLL3 Ready Interrupt Clear */
+#endif /* STM32F10X_CL */
+
+/*****************  Bit definition for RCC_APB2RSTR register  *****************/
+#define  RCC_APB2RSTR_AFIORST                ((uint32_t)0x00000001)        /*!< Alternate Function I/O reset */
+#define  RCC_APB2RSTR_IOPARST                ((uint32_t)0x00000004)        /*!< I/O port A reset */
+#define  RCC_APB2RSTR_IOPBRST                ((uint32_t)0x00000008)        /*!< I/O port B reset */
+#define  RCC_APB2RSTR_IOPCRST                ((uint32_t)0x00000010)        /*!< I/O port C reset */
+#define  RCC_APB2RSTR_IOPDRST                ((uint32_t)0x00000020)        /*!< I/O port D reset */
+#define  RCC_APB2RSTR_ADC1RST                ((uint32_t)0x00000200)        /*!< ADC 1 interface reset */
+
+#if !defined (STM32F10X_LD_VL) && !defined (STM32F10X_MD_VL) && !defined (STM32F10X_HD_VL)
+#define  RCC_APB2RSTR_ADC2RST                ((uint32_t)0x00000400)        /*!< ADC 2 interface reset */
+#endif
+
+#define  RCC_APB2RSTR_TIM1RST                ((uint32_t)0x00000800)        /*!< TIM1 Timer reset */
+#define  RCC_APB2RSTR_SPI1RST                ((uint32_t)0x00001000)        /*!< SPI 1 reset */
+#define  RCC_APB2RSTR_USART1RST              ((uint32_t)0x00004000)        /*!< USART1 reset */
+
+#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
+#define  RCC_APB2RSTR_TIM15RST               ((uint32_t)0x00010000)        /*!< TIM15 Timer reset */
+#define  RCC_APB2RSTR_TIM16RST               ((uint32_t)0x00020000)        /*!< TIM16 Timer reset */
+#define  RCC_APB2RSTR_TIM17RST               ((uint32_t)0x00040000)        /*!< TIM17 Timer reset */
+#endif
+
+#if !defined (STM32F10X_LD) && !defined (STM32F10X_LD_VL)
+ #define  RCC_APB2RSTR_IOPERST               ((uint32_t)0x00000040)        /*!< I/O port E reset */
+#endif /* STM32F10X_LD && STM32F10X_LD_VL */
+
+#if defined (STM32F10X_HD) || defined (STM32F10X_XL)
+ #define  RCC_APB2RSTR_IOPFRST               ((uint32_t)0x00000080)        /*!< I/O port F reset */
+ #define  RCC_APB2RSTR_IOPGRST               ((uint32_t)0x00000100)        /*!< I/O port G reset */
+ #define  RCC_APB2RSTR_TIM8RST               ((uint32_t)0x00002000)        /*!< TIM8 Timer reset */
+ #define  RCC_APB2RSTR_ADC3RST               ((uint32_t)0x00008000)        /*!< ADC3 interface reset */
+#endif
+
+#if defined (STM32F10X_HD_VL)
+ #define  RCC_APB2RSTR_IOPFRST               ((uint32_t)0x00000080)        /*!< I/O port F reset */
+ #define  RCC_APB2RSTR_IOPGRST               ((uint32_t)0x00000100)        /*!< I/O port G reset */
+#endif
+
+#ifdef STM32F10X_XL
+ #define  RCC_APB2RSTR_TIM9RST               ((uint32_t)0x00080000)         /*!< TIM9 Timer reset */
+ #define  RCC_APB2RSTR_TIM10RST              ((uint32_t)0x00100000)         /*!< TIM10 Timer reset */
+ #define  RCC_APB2RSTR_TIM11RST              ((uint32_t)0x00200000)         /*!< TIM11 Timer reset */
+#endif /* STM32F10X_XL */
+
+/*****************  Bit definition for RCC_APB1RSTR register  *****************/
+#define  RCC_APB1RSTR_TIM2RST                ((uint32_t)0x00000001)        /*!< Timer 2 reset */
+#define  RCC_APB1RSTR_TIM3RST                ((uint32_t)0x00000002)        /*!< Timer 3 reset */
+#define  RCC_APB1RSTR_WWDGRST                ((uint32_t)0x00000800)        /*!< Window Watchdog reset */
+#define  RCC_APB1RSTR_USART2RST              ((uint32_t)0x00020000)        /*!< USART 2 reset */
+#define  RCC_APB1RSTR_I2C1RST                ((uint32_t)0x00200000)        /*!< I2C 1 reset */
+
+#if !defined (STM32F10X_LD_VL) && !defined (STM32F10X_MD_VL) && !defined (STM32F10X_HD_VL)
+#define  RCC_APB1RSTR_CAN1RST                ((uint32_t)0x02000000)        /*!< CAN1 reset */
+#endif
+
+#define  RCC_APB1RSTR_BKPRST                 ((uint32_t)0x08000000)        /*!< Backup interface reset */
+#define  RCC_APB1RSTR_PWRRST                 ((uint32_t)0x10000000)        /*!< Power interface reset */
+
+#if !defined (STM32F10X_LD) && !defined (STM32F10X_LD_VL)
+ #define  RCC_APB1RSTR_TIM4RST               ((uint32_t)0x00000004)        /*!< Timer 4 reset */
+ #define  RCC_APB1RSTR_SPI2RST               ((uint32_t)0x00004000)        /*!< SPI 2 reset */
+ #define  RCC_APB1RSTR_USART3RST             ((uint32_t)0x00040000)        /*!< USART 3 reset */
+ #define  RCC_APB1RSTR_I2C2RST               ((uint32_t)0x00400000)        /*!< I2C 2 reset */
+#endif /* STM32F10X_LD && STM32F10X_LD_VL */
+
+#if defined (STM32F10X_HD) || defined (STM32F10X_MD) || defined (STM32F10X_LD) || defined  (STM32F10X_XL)
+ #define  RCC_APB1RSTR_USBRST                ((uint32_t)0x00800000)        /*!< USB Device reset */
+#endif
+
+#if defined (STM32F10X_HD) || defined  (STM32F10X_CL) || defined  (STM32F10X_XL)
+ #define  RCC_APB1RSTR_TIM5RST                ((uint32_t)0x00000008)        /*!< Timer 5 reset */
+ #define  RCC_APB1RSTR_TIM6RST                ((uint32_t)0x00000010)        /*!< Timer 6 reset */
+ #define  RCC_APB1RSTR_TIM7RST                ((uint32_t)0x00000020)        /*!< Timer 7 reset */
+ #define  RCC_APB1RSTR_SPI3RST                ((uint32_t)0x00008000)        /*!< SPI 3 reset */
+ #define  RCC_APB1RSTR_UART4RST               ((uint32_t)0x00080000)        /*!< UART 4 reset */
+ #define  RCC_APB1RSTR_UART5RST               ((uint32_t)0x00100000)        /*!< UART 5 reset */
+ #define  RCC_APB1RSTR_DACRST                 ((uint32_t)0x20000000)        /*!< DAC interface reset */
+#endif
+
+#if defined (STM32F10X_LD_VL) || defined  (STM32F10X_MD_VL) || defined  (STM32F10X_HD_VL)
+ #define  RCC_APB1RSTR_TIM6RST                ((uint32_t)0x00000010)        /*!< Timer 6 reset */
+ #define  RCC_APB1RSTR_TIM7RST                ((uint32_t)0x00000020)        /*!< Timer 7 reset */
+ #define  RCC_APB1RSTR_DACRST                 ((uint32_t)0x20000000)        /*!< DAC interface reset */
+ #define  RCC_APB1RSTR_CECRST                 ((uint32_t)0x40000000)        /*!< CEC interface reset */ 
+#endif
+
+#if defined  (STM32F10X_HD_VL)
+ #define  RCC_APB1RSTR_TIM5RST                ((uint32_t)0x00000008)        /*!< Timer 5 reset */
+ #define  RCC_APB1RSTR_TIM12RST               ((uint32_t)0x00000040)        /*!< TIM12 Timer reset */
+ #define  RCC_APB1RSTR_TIM13RST               ((uint32_t)0x00000080)        /*!< TIM13 Timer reset */
+ #define  RCC_APB1RSTR_TIM14RST               ((uint32_t)0x00000100)        /*!< TIM14 Timer reset */
+ #define  RCC_APB1RSTR_SPI3RST                ((uint32_t)0x00008000)        /*!< SPI 3 reset */ 
+ #define  RCC_APB1RSTR_UART4RST               ((uint32_t)0x00080000)        /*!< UART 4 reset */
+ #define  RCC_APB1RSTR_UART5RST               ((uint32_t)0x00100000)        /*!< UART 5 reset */ 
+#endif
+
+#ifdef STM32F10X_CL
+ #define  RCC_APB1RSTR_CAN2RST                ((uint32_t)0x04000000)        /*!< CAN2 reset */
+#endif /* STM32F10X_CL */
+
+#ifdef STM32F10X_XL
+ #define  RCC_APB1RSTR_TIM12RST               ((uint32_t)0x00000040)         /*!< TIM12 Timer reset */
+ #define  RCC_APB1RSTR_TIM13RST               ((uint32_t)0x00000080)         /*!< TIM13 Timer reset */
+ #define  RCC_APB1RSTR_TIM14RST               ((uint32_t)0x00000100)         /*!< TIM14 Timer reset */
+#endif /* STM32F10X_XL */
+
+/******************  Bit definition for RCC_AHBENR register  ******************/
+#define  RCC_AHBENR_DMA1EN                   ((uint16_t)0x0001)            /*!< DMA1 clock enable */
+#define  RCC_AHBENR_SRAMEN                   ((uint16_t)0x0004)            /*!< SRAM interface clock enable */
+#define  RCC_AHBENR_FLITFEN                  ((uint16_t)0x0010)            /*!< FLITF clock enable */
+#define  RCC_AHBENR_CRCEN                    ((uint16_t)0x0040)            /*!< CRC clock enable */
+
+#if defined (STM32F10X_HD) || defined  (STM32F10X_CL) || defined  (STM32F10X_HD_VL)
+ #define  RCC_AHBENR_DMA2EN                  ((uint16_t)0x0002)            /*!< DMA2 clock enable */
+#endif
+
+#if defined (STM32F10X_HD) || defined (STM32F10X_XL)
+ #define  RCC_AHBENR_FSMCEN                  ((uint16_t)0x0100)            /*!< FSMC clock enable */
+ #define  RCC_AHBENR_SDIOEN                  ((uint16_t)0x0400)            /*!< SDIO clock enable */
+#endif
+
+#if defined (STM32F10X_HD_VL)
+ #define  RCC_AHBENR_FSMCEN                  ((uint16_t)0x0100)            /*!< FSMC clock enable */
+#endif
+
+#ifdef STM32F10X_CL
+ #define  RCC_AHBENR_OTGFSEN                 ((uint32_t)0x00001000)         /*!< USB OTG FS clock enable */
+ #define  RCC_AHBENR_ETHMACEN                ((uint32_t)0x00004000)         /*!< ETHERNET MAC clock enable */
+ #define  RCC_AHBENR_ETHMACTXEN              ((uint32_t)0x00008000)         /*!< ETHERNET MAC Tx clock enable */
+ #define  RCC_AHBENR_ETHMACRXEN              ((uint32_t)0x00010000)         /*!< ETHERNET MAC Rx clock enable */
+#endif /* STM32F10X_CL */
+
+/******************  Bit definition for RCC_APB2ENR register  *****************/
+#define  RCC_APB2ENR_AFIOEN                  ((uint32_t)0x00000001)         /*!< Alternate Function I/O clock enable */
+#define  RCC_APB2ENR_IOPAEN                  ((uint32_t)0x00000004)         /*!< I/O port A clock enable */
+#define  RCC_APB2ENR_IOPBEN                  ((uint32_t)0x00000008)         /*!< I/O port B clock enable */
+#define  RCC_APB2ENR_IOPCEN                  ((uint32_t)0x00000010)         /*!< I/O port C clock enable */
+#define  RCC_APB2ENR_IOPDEN                  ((uint32_t)0x00000020)         /*!< I/O port D clock enable */
+#define  RCC_APB2ENR_ADC1EN                  ((uint32_t)0x00000200)         /*!< ADC 1 interface clock enable */
+
+#if !defined (STM32F10X_LD_VL) && !defined (STM32F10X_MD_VL) && !defined (STM32F10X_HD_VL)
+#define  RCC_APB2ENR_ADC2EN                  ((uint32_t)0x00000400)         /*!< ADC 2 interface clock enable */
+#endif
+
+#define  RCC_APB2ENR_TIM1EN                  ((uint32_t)0x00000800)         /*!< TIM1 Timer clock enable */
+#define  RCC_APB2ENR_SPI1EN                  ((uint32_t)0x00001000)         /*!< SPI 1 clock enable */
+#define  RCC_APB2ENR_USART1EN                ((uint32_t)0x00004000)         /*!< USART1 clock enable */
+
+#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
+#define  RCC_APB2ENR_TIM15EN                 ((uint32_t)0x00010000)         /*!< TIM15 Timer clock enable */
+#define  RCC_APB2ENR_TIM16EN                 ((uint32_t)0x00020000)         /*!< TIM16 Timer clock enable */
+#define  RCC_APB2ENR_TIM17EN                 ((uint32_t)0x00040000)         /*!< TIM17 Timer clock enable */
+#endif
+
+#if !defined (STM32F10X_LD) && !defined (STM32F10X_LD_VL)
+ #define  RCC_APB2ENR_IOPEEN                 ((uint32_t)0x00000040)         /*!< I/O port E clock enable */
+#endif /* STM32F10X_LD && STM32F10X_LD_VL */
+
+#if defined (STM32F10X_HD) || defined (STM32F10X_XL)
+ #define  RCC_APB2ENR_IOPFEN                 ((uint32_t)0x00000080)         /*!< I/O port F clock enable */
+ #define  RCC_APB2ENR_IOPGEN                 ((uint32_t)0x00000100)         /*!< I/O port G clock enable */
+ #define  RCC_APB2ENR_TIM8EN                 ((uint32_t)0x00002000)         /*!< TIM8 Timer clock enable */
+ #define  RCC_APB2ENR_ADC3EN                 ((uint32_t)0x00008000)         /*!< DMA1 clock enable */
+#endif
+
+#if defined (STM32F10X_HD_VL)
+ #define  RCC_APB2ENR_IOPFEN                 ((uint32_t)0x00000080)         /*!< I/O port F clock enable */
+ #define  RCC_APB2ENR_IOPGEN                 ((uint32_t)0x00000100)         /*!< I/O port G clock enable */
+#endif
+
+#ifdef STM32F10X_XL
+ #define  RCC_APB2ENR_TIM9EN                 ((uint32_t)0x00080000)         /*!< TIM9 Timer clock enable  */
+ #define  RCC_APB2ENR_TIM10EN                ((uint32_t)0x00100000)         /*!< TIM10 Timer clock enable  */
+ #define  RCC_APB2ENR_TIM11EN                ((uint32_t)0x00200000)         /*!< TIM11 Timer clock enable */
+#endif
+
+/*****************  Bit definition for RCC_APB1ENR register  ******************/
+#define  RCC_APB1ENR_TIM2EN                  ((uint32_t)0x00000001)        /*!< Timer 2 clock enabled*/
+#define  RCC_APB1ENR_TIM3EN                  ((uint32_t)0x00000002)        /*!< Timer 3 clock enable */
+#define  RCC_APB1ENR_WWDGEN                  ((uint32_t)0x00000800)        /*!< Window Watchdog clock enable */
+#define  RCC_APB1ENR_USART2EN                ((uint32_t)0x00020000)        /*!< USART 2 clock enable */
+#define  RCC_APB1ENR_I2C1EN                  ((uint32_t)0x00200000)        /*!< I2C 1 clock enable */
+
+#if !defined (STM32F10X_LD_VL) && !defined (STM32F10X_MD_VL) && !defined (STM32F10X_HD_VL)
+#define  RCC_APB1ENR_CAN1EN                  ((uint32_t)0x02000000)        /*!< CAN1 clock enable */
+#endif
+
+#define  RCC_APB1ENR_BKPEN                   ((uint32_t)0x08000000)        /*!< Backup interface clock enable */
+#define  RCC_APB1ENR_PWREN                   ((uint32_t)0x10000000)        /*!< Power interface clock enable */
+
+#if !defined (STM32F10X_LD) && !defined (STM32F10X_LD_VL)
+ #define  RCC_APB1ENR_TIM4EN                 ((uint32_t)0x00000004)        /*!< Timer 4 clock enable */
+ #define  RCC_APB1ENR_SPI2EN                 ((uint32_t)0x00004000)        /*!< SPI 2 clock enable */
+ #define  RCC_APB1ENR_USART3EN               ((uint32_t)0x00040000)        /*!< USART 3 clock enable */
+ #define  RCC_APB1ENR_I2C2EN                 ((uint32_t)0x00400000)        /*!< I2C 2 clock enable */
+#endif /* STM32F10X_LD && STM32F10X_LD_VL */
+
+#if defined (STM32F10X_HD) || defined (STM32F10X_MD) || defined  (STM32F10X_LD)
+ #define  RCC_APB1ENR_USBEN                  ((uint32_t)0x00800000)        /*!< USB Device clock enable */
+#endif
+
+#if defined (STM32F10X_HD) || defined  (STM32F10X_CL)
+ #define  RCC_APB1ENR_TIM5EN                 ((uint32_t)0x00000008)        /*!< Timer 5 clock enable */
+ #define  RCC_APB1ENR_TIM6EN                 ((uint32_t)0x00000010)        /*!< Timer 6 clock enable */
+ #define  RCC_APB1ENR_TIM7EN                 ((uint32_t)0x00000020)        /*!< Timer 7 clock enable */
+ #define  RCC_APB1ENR_SPI3EN                 ((uint32_t)0x00008000)        /*!< SPI 3 clock enable */
+ #define  RCC_APB1ENR_UART4EN                ((uint32_t)0x00080000)        /*!< UART 4 clock enable */
+ #define  RCC_APB1ENR_UART5EN                ((uint32_t)0x00100000)        /*!< UART 5 clock enable */
+ #define  RCC_APB1ENR_DACEN                  ((uint32_t)0x20000000)        /*!< DAC interface clock enable */
+#endif
+
+#if defined (STM32F10X_LD_VL) || defined  (STM32F10X_MD_VL) || defined  (STM32F10X_HD_VL)
+ #define  RCC_APB1ENR_TIM6EN                 ((uint32_t)0x00000010)        /*!< Timer 6 clock enable */
+ #define  RCC_APB1ENR_TIM7EN                 ((uint32_t)0x00000020)        /*!< Timer 7 clock enable */
+ #define  RCC_APB1ENR_DACEN                  ((uint32_t)0x20000000)        /*!< DAC interface clock enable */
+ #define  RCC_APB1ENR_CECEN                  ((uint32_t)0x40000000)        /*!< CEC interface clock enable */ 
+#endif
+
+#ifdef STM32F10X_HD_VL
+ #define  RCC_APB1ENR_TIM5EN                 ((uint32_t)0x00000008)        /*!< Timer 5 clock enable */
+ #define  RCC_APB1ENR_TIM12EN                ((uint32_t)0x00000040)         /*!< TIM12 Timer clock enable  */
+ #define  RCC_APB1ENR_TIM13EN                ((uint32_t)0x00000080)         /*!< TIM13 Timer clock enable  */
+ #define  RCC_APB1ENR_TIM14EN                ((uint32_t)0x00000100)         /*!< TIM14 Timer clock enable */
+ #define  RCC_APB1ENR_SPI3EN                 ((uint32_t)0x00008000)        /*!< SPI 3 clock enable */
+ #define  RCC_APB1ENR_UART4EN                ((uint32_t)0x00080000)        /*!< UART 4 clock enable */
+ #define  RCC_APB1ENR_UART5EN                ((uint32_t)0x00100000)        /*!< UART 5 clock enable */ 
+#endif /* STM32F10X_HD_VL */
+
+#ifdef STM32F10X_CL
+ #define  RCC_APB1ENR_CAN2EN                  ((uint32_t)0x04000000)        /*!< CAN2 clock enable */
+#endif /* STM32F10X_CL */
+
+#ifdef STM32F10X_XL
+ #define  RCC_APB1ENR_TIM12EN                ((uint32_t)0x00000040)         /*!< TIM12 Timer clock enable  */
+ #define  RCC_APB1ENR_TIM13EN                ((uint32_t)0x00000080)         /*!< TIM13 Timer clock enable  */
+ #define  RCC_APB1ENR_TIM14EN                ((uint32_t)0x00000100)         /*!< TIM14 Timer clock enable */
+#endif /* STM32F10X_XL */
+
+/*******************  Bit definition for RCC_BDCR register  *******************/
+#define  RCC_BDCR_LSEON                      ((uint32_t)0x00000001)        /*!< External Low Speed oscillator enable */
+#define  RCC_BDCR_LSERDY                     ((uint32_t)0x00000002)        /*!< External Low Speed oscillator Ready */
+#define  RCC_BDCR_LSEBYP                     ((uint32_t)0x00000004)        /*!< External Low Speed oscillator Bypass */
+
+#define  RCC_BDCR_RTCSEL                     ((uint32_t)0x00000300)        /*!< RTCSEL[1:0] bits (RTC clock source selection) */
+#define  RCC_BDCR_RTCSEL_0                   ((uint32_t)0x00000100)        /*!< Bit 0 */
+#define  RCC_BDCR_RTCSEL_1                   ((uint32_t)0x00000200)        /*!< Bit 1 */
+
+/*!< RTC congiguration */
+#define  RCC_BDCR_RTCSEL_NOCLOCK             ((uint32_t)0x00000000)        /*!< No clock */
+#define  RCC_BDCR_RTCSEL_LSE                 ((uint32_t)0x00000100)        /*!< LSE oscillator clock used as RTC clock */
+#define  RCC_BDCR_RTCSEL_LSI                 ((uint32_t)0x00000200)        /*!< LSI oscillator clock used as RTC clock */
+#define  RCC_BDCR_RTCSEL_HSE                 ((uint32_t)0x00000300)        /*!< HSE oscillator clock divided by 128 used as RTC clock */
+
+#define  RCC_BDCR_RTCEN                      ((uint32_t)0x00008000)        /*!< RTC clock enable */
+#define  RCC_BDCR_BDRST                      ((uint32_t)0x00010000)        /*!< Backup domain software reset  */
+
+/*******************  Bit definition for RCC_CSR register  ********************/  
+#define  RCC_CSR_LSION                       ((uint32_t)0x00000001)        /*!< Internal Low Speed oscillator enable */
+#define  RCC_CSR_LSIRDY                      ((uint32_t)0x00000002)        /*!< Internal Low Speed oscillator Ready */
+#define  RCC_CSR_RMVF                        ((uint32_t)0x01000000)        /*!< Remove reset flag */
+#define  RCC_CSR_PINRSTF                     ((uint32_t)0x04000000)        /*!< PIN reset flag */
+#define  RCC_CSR_PORRSTF                     ((uint32_t)0x08000000)        /*!< POR/PDR reset flag */
+#define  RCC_CSR_SFTRSTF                     ((uint32_t)0x10000000)        /*!< Software Reset flag */
+#define  RCC_CSR_IWDGRSTF                    ((uint32_t)0x20000000)        /*!< Independent Watchdog reset flag */
+#define  RCC_CSR_WWDGRSTF                    ((uint32_t)0x40000000)        /*!< Window watchdog reset flag */
+#define  RCC_CSR_LPWRRSTF                    ((uint32_t)0x80000000)        /*!< Low-Power reset flag */
+
+#ifdef STM32F10X_CL
+/*******************  Bit definition for RCC_AHBRSTR register  ****************/
+ #define  RCC_AHBRSTR_OTGFSRST               ((uint32_t)0x00001000)         /*!< USB OTG FS reset */
+ #define  RCC_AHBRSTR_ETHMACRST              ((uint32_t)0x00004000)         /*!< ETHERNET MAC reset */
+
+/*******************  Bit definition for RCC_CFGR2 register  ******************/
+/*!< PREDIV1 configuration */
+ #define  RCC_CFGR2_PREDIV1                  ((uint32_t)0x0000000F)        /*!< PREDIV1[3:0] bits */
+ #define  RCC_CFGR2_PREDIV1_0                ((uint32_t)0x00000001)        /*!< Bit 0 */
+ #define  RCC_CFGR2_PREDIV1_1                ((uint32_t)0x00000002)        /*!< Bit 1 */
+ #define  RCC_CFGR2_PREDIV1_2                ((uint32_t)0x00000004)        /*!< Bit 2 */
+ #define  RCC_CFGR2_PREDIV1_3                ((uint32_t)0x00000008)        /*!< Bit 3 */
+
+ #define  RCC_CFGR2_PREDIV1_DIV1             ((uint32_t)0x00000000)        /*!< PREDIV1 input clock not divided */
+ #define  RCC_CFGR2_PREDIV1_DIV2             ((uint32_t)0x00000001)        /*!< PREDIV1 input clock divided by 2 */
+ #define  RCC_CFGR2_PREDIV1_DIV3             ((uint32_t)0x00000002)        /*!< PREDIV1 input clock divided by 3 */
+ #define  RCC_CFGR2_PREDIV1_DIV4             ((uint32_t)0x00000003)        /*!< PREDIV1 input clock divided by 4 */
+ #define  RCC_CFGR2_PREDIV1_DIV5             ((uint32_t)0x00000004)        /*!< PREDIV1 input clock divided by 5 */
+ #define  RCC_CFGR2_PREDIV1_DIV6             ((uint32_t)0x00000005)        /*!< PREDIV1 input clock divided by 6 */
+ #define  RCC_CFGR2_PREDIV1_DIV7             ((uint32_t)0x00000006)        /*!< PREDIV1 input clock divided by 7 */
+ #define  RCC_CFGR2_PREDIV1_DIV8             ((uint32_t)0x00000007)        /*!< PREDIV1 input clock divided by 8 */
+ #define  RCC_CFGR2_PREDIV1_DIV9             ((uint32_t)0x00000008)        /*!< PREDIV1 input clock divided by 9 */
+ #define  RCC_CFGR2_PREDIV1_DIV10            ((uint32_t)0x00000009)        /*!< PREDIV1 input clock divided by 10 */
+ #define  RCC_CFGR2_PREDIV1_DIV11            ((uint32_t)0x0000000A)        /*!< PREDIV1 input clock divided by 11 */
+ #define  RCC_CFGR2_PREDIV1_DIV12            ((uint32_t)0x0000000B)        /*!< PREDIV1 input clock divided by 12 */
+ #define  RCC_CFGR2_PREDIV1_DIV13            ((uint32_t)0x0000000C)        /*!< PREDIV1 input clock divided by 13 */
+ #define  RCC_CFGR2_PREDIV1_DIV14            ((uint32_t)0x0000000D)        /*!< PREDIV1 input clock divided by 14 */
+ #define  RCC_CFGR2_PREDIV1_DIV15            ((uint32_t)0x0000000E)        /*!< PREDIV1 input clock divided by 15 */
+ #define  RCC_CFGR2_PREDIV1_DIV16            ((uint32_t)0x0000000F)        /*!< PREDIV1 input clock divided by 16 */
+
+/*!< PREDIV2 configuration */
+ #define  RCC_CFGR2_PREDIV2                  ((uint32_t)0x000000F0)        /*!< PREDIV2[3:0] bits */
+ #define  RCC_CFGR2_PREDIV2_0                ((uint32_t)0x00000010)        /*!< Bit 0 */
+ #define  RCC_CFGR2_PREDIV2_1                ((uint32_t)0x00000020)        /*!< Bit 1 */
+ #define  RCC_CFGR2_PREDIV2_2                ((uint32_t)0x00000040)        /*!< Bit 2 */
+ #define  RCC_CFGR2_PREDIV2_3                ((uint32_t)0x00000080)        /*!< Bit 3 */
+
+ #define  RCC_CFGR2_PREDIV2_DIV1             ((uint32_t)0x00000000)        /*!< PREDIV2 input clock not divided */
+ #define  RCC_CFGR2_PREDIV2_DIV2             ((uint32_t)0x00000010)        /*!< PREDIV2 input clock divided by 2 */
+ #define  RCC_CFGR2_PREDIV2_DIV3             ((uint32_t)0x00000020)        /*!< PREDIV2 input clock divided by 3 */
+ #define  RCC_CFGR2_PREDIV2_DIV4             ((uint32_t)0x00000030)        /*!< PREDIV2 input clock divided by 4 */
+ #define  RCC_CFGR2_PREDIV2_DIV5             ((uint32_t)0x00000040)        /*!< PREDIV2 input clock divided by 5 */
+ #define  RCC_CFGR2_PREDIV2_DIV6             ((uint32_t)0x00000050)        /*!< PREDIV2 input clock divided by 6 */
+ #define  RCC_CFGR2_PREDIV2_DIV7             ((uint32_t)0x00000060)        /*!< PREDIV2 input clock divided by 7 */
+ #define  RCC_CFGR2_PREDIV2_DIV8             ((uint32_t)0x00000070)        /*!< PREDIV2 input clock divided by 8 */
+ #define  RCC_CFGR2_PREDIV2_DIV9             ((uint32_t)0x00000080)        /*!< PREDIV2 input clock divided by 9 */
+ #define  RCC_CFGR2_PREDIV2_DIV10            ((uint32_t)0x00000090)        /*!< PREDIV2 input clock divided by 10 */
+ #define  RCC_CFGR2_PREDIV2_DIV11            ((uint32_t)0x000000A0)        /*!< PREDIV2 input clock divided by 11 */
+ #define  RCC_CFGR2_PREDIV2_DIV12            ((uint32_t)0x000000B0)        /*!< PREDIV2 input clock divided by 12 */
+ #define  RCC_CFGR2_PREDIV2_DIV13            ((uint32_t)0x000000C0)        /*!< PREDIV2 input clock divided by 13 */
+ #define  RCC_CFGR2_PREDIV2_DIV14            ((uint32_t)0x000000D0)        /*!< PREDIV2 input clock divided by 14 */
+ #define  RCC_CFGR2_PREDIV2_DIV15            ((uint32_t)0x000000E0)        /*!< PREDIV2 input clock divided by 15 */
+ #define  RCC_CFGR2_PREDIV2_DIV16            ((uint32_t)0x000000F0)        /*!< PREDIV2 input clock divided by 16 */
+
+/*!< PLL2MUL configuration */
+ #define  RCC_CFGR2_PLL2MUL                  ((uint32_t)0x00000F00)        /*!< PLL2MUL[3:0] bits */
+ #define  RCC_CFGR2_PLL2MUL_0                ((uint32_t)0x00000100)        /*!< Bit 0 */
+ #define  RCC_CFGR2_PLL2MUL_1                ((uint32_t)0x00000200)        /*!< Bit 1 */
+ #define  RCC_CFGR2_PLL2MUL_2                ((uint32_t)0x00000400)        /*!< Bit 2 */
+ #define  RCC_CFGR2_PLL2MUL_3                ((uint32_t)0x00000800)        /*!< Bit 3 */
+
+ #define  RCC_CFGR2_PLL2MUL8                 ((uint32_t)0x00000600)        /*!< PLL2 input clock * 8 */
+ #define  RCC_CFGR2_PLL2MUL9                 ((uint32_t)0x00000700)        /*!< PLL2 input clock * 9 */
+ #define  RCC_CFGR2_PLL2MUL10                ((uint32_t)0x00000800)        /*!< PLL2 input clock * 10 */
+ #define  RCC_CFGR2_PLL2MUL11                ((uint32_t)0x00000900)        /*!< PLL2 input clock * 11 */
+ #define  RCC_CFGR2_PLL2MUL12                ((uint32_t)0x00000A00)        /*!< PLL2 input clock * 12 */
+ #define  RCC_CFGR2_PLL2MUL13                ((uint32_t)0x00000B00)        /*!< PLL2 input clock * 13 */
+ #define  RCC_CFGR2_PLL2MUL14                ((uint32_t)0x00000C00)        /*!< PLL2 input clock * 14 */
+ #define  RCC_CFGR2_PLL2MUL16                ((uint32_t)0x00000E00)        /*!< PLL2 input clock * 16 */
+ #define  RCC_CFGR2_PLL2MUL20                ((uint32_t)0x00000F00)        /*!< PLL2 input clock * 20 */
+
+/*!< PLL3MUL configuration */
+ #define  RCC_CFGR2_PLL3MUL                  ((uint32_t)0x0000F000)        /*!< PLL3MUL[3:0] bits */
+ #define  RCC_CFGR2_PLL3MUL_0                ((uint32_t)0x00001000)        /*!< Bit 0 */
+ #define  RCC_CFGR2_PLL3MUL_1                ((uint32_t)0x00002000)        /*!< Bit 1 */
+ #define  RCC_CFGR2_PLL3MUL_2                ((uint32_t)0x00004000)        /*!< Bit 2 */
+ #define  RCC_CFGR2_PLL3MUL_3                ((uint32_t)0x00008000)        /*!< Bit 3 */
+
+ #define  RCC_CFGR2_PLL3MUL8                 ((uint32_t)0x00006000)        /*!< PLL3 input clock * 8 */
+ #define  RCC_CFGR2_PLL3MUL9                 ((uint32_t)0x00007000)        /*!< PLL3 input clock * 9 */
+ #define  RCC_CFGR2_PLL3MUL10                ((uint32_t)0x00008000)        /*!< PLL3 input clock * 10 */
+ #define  RCC_CFGR2_PLL3MUL11                ((uint32_t)0x00009000)        /*!< PLL3 input clock * 11 */
+ #define  RCC_CFGR2_PLL3MUL12                ((uint32_t)0x0000A000)        /*!< PLL3 input clock * 12 */
+ #define  RCC_CFGR2_PLL3MUL13                ((uint32_t)0x0000B000)        /*!< PLL3 input clock * 13 */
+ #define  RCC_CFGR2_PLL3MUL14                ((uint32_t)0x0000C000)        /*!< PLL3 input clock * 14 */
+ #define  RCC_CFGR2_PLL3MUL16                ((uint32_t)0x0000E000)        /*!< PLL3 input clock * 16 */
+ #define  RCC_CFGR2_PLL3MUL20                ((uint32_t)0x0000F000)        /*!< PLL3 input clock * 20 */
+
+ #define  RCC_CFGR2_PREDIV1SRC               ((uint32_t)0x00010000)        /*!< PREDIV1 entry clock source */
+ #define  RCC_CFGR2_PREDIV1SRC_PLL2          ((uint32_t)0x00010000)        /*!< PLL2 selected as PREDIV1 entry clock source */
+ #define  RCC_CFGR2_PREDIV1SRC_HSE           ((uint32_t)0x00000000)        /*!< HSE selected as PREDIV1 entry clock source */
+ #define  RCC_CFGR2_I2S2SRC                  ((uint32_t)0x00020000)        /*!< I2S2 entry clock source */
+ #define  RCC_CFGR2_I2S3SRC                  ((uint32_t)0x00040000)        /*!< I2S3 clock source */
+#endif /* STM32F10X_CL */
+
+#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
+/*******************  Bit definition for RCC_CFGR2 register  ******************/
+/*!< PREDIV1 configuration */
+ #define  RCC_CFGR2_PREDIV1                  ((uint32_t)0x0000000F)        /*!< PREDIV1[3:0] bits */
+ #define  RCC_CFGR2_PREDIV1_0                ((uint32_t)0x00000001)        /*!< Bit 0 */
+ #define  RCC_CFGR2_PREDIV1_1                ((uint32_t)0x00000002)        /*!< Bit 1 */
+ #define  RCC_CFGR2_PREDIV1_2                ((uint32_t)0x00000004)        /*!< Bit 2 */
+ #define  RCC_CFGR2_PREDIV1_3                ((uint32_t)0x00000008)        /*!< Bit 3 */
+
+ #define  RCC_CFGR2_PREDIV1_DIV1             ((uint32_t)0x00000000)        /*!< PREDIV1 input clock not divided */
+ #define  RCC_CFGR2_PREDIV1_DIV2             ((uint32_t)0x00000001)        /*!< PREDIV1 input clock divided by 2 */
+ #define  RCC_CFGR2_PREDIV1_DIV3             ((uint32_t)0x00000002)        /*!< PREDIV1 input clock divided by 3 */
+ #define  RCC_CFGR2_PREDIV1_DIV4             ((uint32_t)0x00000003)        /*!< PREDIV1 input clock divided by 4 */
+ #define  RCC_CFGR2_PREDIV1_DIV5             ((uint32_t)0x00000004)        /*!< PREDIV1 input clock divided by 5 */
+ #define  RCC_CFGR2_PREDIV1_DIV6             ((uint32_t)0x00000005)        /*!< PREDIV1 input clock divided by 6 */
+ #define  RCC_CFGR2_PREDIV1_DIV7             ((uint32_t)0x00000006)        /*!< PREDIV1 input clock divided by 7 */
+ #define  RCC_CFGR2_PREDIV1_DIV8             ((uint32_t)0x00000007)        /*!< PREDIV1 input clock divided by 8 */
+ #define  RCC_CFGR2_PREDIV1_DIV9             ((uint32_t)0x00000008)        /*!< PREDIV1 input clock divided by 9 */
+ #define  RCC_CFGR2_PREDIV1_DIV10            ((uint32_t)0x00000009)        /*!< PREDIV1 input clock divided by 10 */
+ #define  RCC_CFGR2_PREDIV1_DIV11            ((uint32_t)0x0000000A)        /*!< PREDIV1 input clock divided by 11 */
+ #define  RCC_CFGR2_PREDIV1_DIV12            ((uint32_t)0x0000000B)        /*!< PREDIV1 input clock divided by 12 */
+ #define  RCC_CFGR2_PREDIV1_DIV13            ((uint32_t)0x0000000C)        /*!< PREDIV1 input clock divided by 13 */
+ #define  RCC_CFGR2_PREDIV1_DIV14            ((uint32_t)0x0000000D)        /*!< PREDIV1 input clock divided by 14 */
+ #define  RCC_CFGR2_PREDIV1_DIV15            ((uint32_t)0x0000000E)        /*!< PREDIV1 input clock divided by 15 */
+ #define  RCC_CFGR2_PREDIV1_DIV16            ((uint32_t)0x0000000F)        /*!< PREDIV1 input clock divided by 16 */
+#endif
+ 
+/******************************************************************************/
+/*                                                                            */
+/*                General Purpose and Alternate Function I/O                  */
+/*                                                                            */
+/******************************************************************************/
+
+/*******************  Bit definition for GPIO_CRL register  *******************/
+#define  GPIO_CRL_MODE                       ((uint32_t)0x33333333)        /*!< Port x mode bits */
+
+#define  GPIO_CRL_MODE0                      ((uint32_t)0x00000003)        /*!< MODE0[1:0] bits (Port x mode bits, pin 0) */
+#define  GPIO_CRL_MODE0_0                    ((uint32_t)0x00000001)        /*!< Bit 0 */
+#define  GPIO_CRL_MODE0_1                    ((uint32_t)0x00000002)        /*!< Bit 1 */
+
+#define  GPIO_CRL_MODE1                      ((uint32_t)0x00000030)        /*!< MODE1[1:0] bits (Port x mode bits, pin 1) */
+#define  GPIO_CRL_MODE1_0                    ((uint32_t)0x00000010)        /*!< Bit 0 */
+#define  GPIO_CRL_MODE1_1                    ((uint32_t)0x00000020)        /*!< Bit 1 */
+
+#define  GPIO_CRL_MODE2                      ((uint32_t)0x00000300)        /*!< MODE2[1:0] bits (Port x mode bits, pin 2) */
+#define  GPIO_CRL_MODE2_0                    ((uint32_t)0x00000100)        /*!< Bit 0 */
+#define  GPIO_CRL_MODE2_1                    ((uint32_t)0x00000200)        /*!< Bit 1 */
+
+#define  GPIO_CRL_MODE3                      ((uint32_t)0x00003000)        /*!< MODE3[1:0] bits (Port x mode bits, pin 3) */
+#define  GPIO_CRL_MODE3_0                    ((uint32_t)0x00001000)        /*!< Bit 0 */
+#define  GPIO_CRL_MODE3_1                    ((uint32_t)0x00002000)        /*!< Bit 1 */
+
+#define  GPIO_CRL_MODE4                      ((uint32_t)0x00030000)        /*!< MODE4[1:0] bits (Port x mode bits, pin 4) */
+#define  GPIO_CRL_MODE4_0                    ((uint32_t)0x00010000)        /*!< Bit 0 */
+#define  GPIO_CRL_MODE4_1                    ((uint32_t)0x00020000)        /*!< Bit 1 */
+
+#define  GPIO_CRL_MODE5                      ((uint32_t)0x00300000)        /*!< MODE5[1:0] bits (Port x mode bits, pin 5) */
+#define  GPIO_CRL_MODE5_0                    ((uint32_t)0x00100000)        /*!< Bit 0 */
+#define  GPIO_CRL_MODE5_1                    ((uint32_t)0x00200000)        /*!< Bit 1 */
+
+#define  GPIO_CRL_MODE6                      ((uint32_t)0x03000000)        /*!< MODE6[1:0] bits (Port x mode bits, pin 6) */
+#define  GPIO_CRL_MODE6_0                    ((uint32_t)0x01000000)        /*!< Bit 0 */
+#define  GPIO_CRL_MODE6_1                    ((uint32_t)0x02000000)        /*!< Bit 1 */
+
+#define  GPIO_CRL_MODE7                      ((uint32_t)0x30000000)        /*!< MODE7[1:0] bits (Port x mode bits, pin 7) */
+#define  GPIO_CRL_MODE7_0                    ((uint32_t)0x10000000)        /*!< Bit 0 */
+#define  GPIO_CRL_MODE7_1                    ((uint32_t)0x20000000)        /*!< Bit 1 */
+
+#define  GPIO_CRL_CNF                        ((uint32_t)0xCCCCCCCC)        /*!< Port x configuration bits */
+
+#define  GPIO_CRL_CNF0                       ((uint32_t)0x0000000C)        /*!< CNF0[1:0] bits (Port x configuration bits, pin 0) */
+#define  GPIO_CRL_CNF0_0                     ((uint32_t)0x00000004)        /*!< Bit 0 */
+#define  GPIO_CRL_CNF0_1                     ((uint32_t)0x00000008)        /*!< Bit 1 */
+
+#define  GPIO_CRL_CNF1                       ((uint32_t)0x000000C0)        /*!< CNF1[1:0] bits (Port x configuration bits, pin 1) */
+#define  GPIO_CRL_CNF1_0                     ((uint32_t)0x00000040)        /*!< Bit 0 */
+#define  GPIO_CRL_CNF1_1                     ((uint32_t)0x00000080)        /*!< Bit 1 */
+
+#define  GPIO_CRL_CNF2                       ((uint32_t)0x00000C00)        /*!< CNF2[1:0] bits (Port x configuration bits, pin 2) */
+#define  GPIO_CRL_CNF2_0                     ((uint32_t)0x00000400)        /*!< Bit 0 */
+#define  GPIO_CRL_CNF2_1                     ((uint32_t)0x00000800)        /*!< Bit 1 */
+
+#define  GPIO_CRL_CNF3                       ((uint32_t)0x0000C000)        /*!< CNF3[1:0] bits (Port x configuration bits, pin 3) */
+#define  GPIO_CRL_CNF3_0                     ((uint32_t)0x00004000)        /*!< Bit 0 */
+#define  GPIO_CRL_CNF3_1                     ((uint32_t)0x00008000)        /*!< Bit 1 */
+
+#define  GPIO_CRL_CNF4                       ((uint32_t)0x000C0000)        /*!< CNF4[1:0] bits (Port x configuration bits, pin 4) */
+#define  GPIO_CRL_CNF4_0                     ((uint32_t)0x00040000)        /*!< Bit 0 */
+#define  GPIO_CRL_CNF4_1                     ((uint32_t)0x00080000)        /*!< Bit 1 */
+
+#define  GPIO_CRL_CNF5                       ((uint32_t)0x00C00000)        /*!< CNF5[1:0] bits (Port x configuration bits, pin 5) */
+#define  GPIO_CRL_CNF5_0                     ((uint32_t)0x00400000)        /*!< Bit 0 */
+#define  GPIO_CRL_CNF5_1                     ((uint32_t)0x00800000)        /*!< Bit 1 */
+
+#define  GPIO_CRL_CNF6                       ((uint32_t)0x0C000000)        /*!< CNF6[1:0] bits (Port x configuration bits, pin 6) */
+#define  GPIO_CRL_CNF6_0                     ((uint32_t)0x04000000)        /*!< Bit 0 */
+#define  GPIO_CRL_CNF6_1                     ((uint32_t)0x08000000)        /*!< Bit 1 */
+
+#define  GPIO_CRL_CNF7                       ((uint32_t)0xC0000000)        /*!< CNF7[1:0] bits (Port x configuration bits, pin 7) */
+#define  GPIO_CRL_CNF7_0                     ((uint32_t)0x40000000)        /*!< Bit 0 */
+#define  GPIO_CRL_CNF7_1                     ((uint32_t)0x80000000)        /*!< Bit 1 */
+
+/*******************  Bit definition for GPIO_CRH register  *******************/
+#define  GPIO_CRH_MODE                       ((uint32_t)0x33333333)        /*!< Port x mode bits */
+
+#define  GPIO_CRH_MODE8                      ((uint32_t)0x00000003)        /*!< MODE8[1:0] bits (Port x mode bits, pin 8) */
+#define  GPIO_CRH_MODE8_0                    ((uint32_t)0x00000001)        /*!< Bit 0 */
+#define  GPIO_CRH_MODE8_1                    ((uint32_t)0x00000002)        /*!< Bit 1 */
+
+#define  GPIO_CRH_MODE9                      ((uint32_t)0x00000030)        /*!< MODE9[1:0] bits (Port x mode bits, pin 9) */
+#define  GPIO_CRH_MODE9_0                    ((uint32_t)0x00000010)        /*!< Bit 0 */
+#define  GPIO_CRH_MODE9_1                    ((uint32_t)0x00000020)        /*!< Bit 1 */
+
+#define  GPIO_CRH_MODE10                     ((uint32_t)0x00000300)        /*!< MODE10[1:0] bits (Port x mode bits, pin 10) */
+#define  GPIO_CRH_MODE10_0                   ((uint32_t)0x00000100)        /*!< Bit 0 */
+#define  GPIO_CRH_MODE10_1                   ((uint32_t)0x00000200)        /*!< Bit 1 */
+
+#define  GPIO_CRH_MODE11                     ((uint32_t)0x00003000)        /*!< MODE11[1:0] bits (Port x mode bits, pin 11) */
+#define  GPIO_CRH_MODE11_0                   ((uint32_t)0x00001000)        /*!< Bit 0 */
+#define  GPIO_CRH_MODE11_1                   ((uint32_t)0x00002000)        /*!< Bit 1 */
+
+#define  GPIO_CRH_MODE12                     ((uint32_t)0x00030000)        /*!< MODE12[1:0] bits (Port x mode bits, pin 12) */
+#define  GPIO_CRH_MODE12_0                   ((uint32_t)0x00010000)        /*!< Bit 0 */
+#define  GPIO_CRH_MODE12_1                   ((uint32_t)0x00020000)        /*!< Bit 1 */
+
+#define  GPIO_CRH_MODE13                     ((uint32_t)0x00300000)        /*!< MODE13[1:0] bits (Port x mode bits, pin 13) */
+#define  GPIO_CRH_MODE13_0                   ((uint32_t)0x00100000)        /*!< Bit 0 */
+#define  GPIO_CRH_MODE13_1                   ((uint32_t)0x00200000)        /*!< Bit 1 */
+
+#define  GPIO_CRH_MODE14                     ((uint32_t)0x03000000)        /*!< MODE14[1:0] bits (Port x mode bits, pin 14) */
+#define  GPIO_CRH_MODE14_0                   ((uint32_t)0x01000000)        /*!< Bit 0 */
+#define  GPIO_CRH_MODE14_1                   ((uint32_t)0x02000000)        /*!< Bit 1 */
+
+#define  GPIO_CRH_MODE15                     ((uint32_t)0x30000000)        /*!< MODE15[1:0] bits (Port x mode bits, pin 15) */
+#define  GPIO_CRH_MODE15_0                   ((uint32_t)0x10000000)        /*!< Bit 0 */
+#define  GPIO_CRH_MODE15_1                   ((uint32_t)0x20000000)        /*!< Bit 1 */
+
+#define  GPIO_CRH_CNF                        ((uint32_t)0xCCCCCCCC)        /*!< Port x configuration bits */
+
+#define  GPIO_CRH_CNF8                       ((uint32_t)0x0000000C)        /*!< CNF8[1:0] bits (Port x configuration bits, pin 8) */
+#define  GPIO_CRH_CNF8_0                     ((uint32_t)0x00000004)        /*!< Bit 0 */
+#define  GPIO_CRH_CNF8_1                     ((uint32_t)0x00000008)        /*!< Bit 1 */
+
+#define  GPIO_CRH_CNF9                       ((uint32_t)0x000000C0)        /*!< CNF9[1:0] bits (Port x configuration bits, pin 9) */
+#define  GPIO_CRH_CNF9_0                     ((uint32_t)0x00000040)        /*!< Bit 0 */
+#define  GPIO_CRH_CNF9_1                     ((uint32_t)0x00000080)        /*!< Bit 1 */
+
+#define  GPIO_CRH_CNF10                      ((uint32_t)0x00000C00)        /*!< CNF10[1:0] bits (Port x configuration bits, pin 10) */
+#define  GPIO_CRH_CNF10_0                    ((uint32_t)0x00000400)        /*!< Bit 0 */
+#define  GPIO_CRH_CNF10_1                    ((uint32_t)0x00000800)        /*!< Bit 1 */
+
+#define  GPIO_CRH_CNF11                      ((uint32_t)0x0000C000)        /*!< CNF11[1:0] bits (Port x configuration bits, pin 11) */
+#define  GPIO_CRH_CNF11_0                    ((uint32_t)0x00004000)        /*!< Bit 0 */
+#define  GPIO_CRH_CNF11_1                    ((uint32_t)0x00008000)        /*!< Bit 1 */
+
+#define  GPIO_CRH_CNF12                      ((uint32_t)0x000C0000)        /*!< CNF12[1:0] bits (Port x configuration bits, pin 12) */
+#define  GPIO_CRH_CNF12_0                    ((uint32_t)0x00040000)        /*!< Bit 0 */
+#define  GPIO_CRH_CNF12_1                    ((uint32_t)0x00080000)        /*!< Bit 1 */
+
+#define  GPIO_CRH_CNF13                      ((uint32_t)0x00C00000)        /*!< CNF13[1:0] bits (Port x configuration bits, pin 13) */
+#define  GPIO_CRH_CNF13_0                    ((uint32_t)0x00400000)        /*!< Bit 0 */
+#define  GPIO_CRH_CNF13_1                    ((uint32_t)0x00800000)        /*!< Bit 1 */
+
+#define  GPIO_CRH_CNF14                      ((uint32_t)0x0C000000)        /*!< CNF14[1:0] bits (Port x configuration bits, pin 14) */
+#define  GPIO_CRH_CNF14_0                    ((uint32_t)0x04000000)        /*!< Bit 0 */
+#define  GPIO_CRH_CNF14_1                    ((uint32_t)0x08000000)        /*!< Bit 1 */
+
+#define  GPIO_CRH_CNF15                      ((uint32_t)0xC0000000)        /*!< CNF15[1:0] bits (Port x configuration bits, pin 15) */
+#define  GPIO_CRH_CNF15_0                    ((uint32_t)0x40000000)        /*!< Bit 0 */
+#define  GPIO_CRH_CNF15_1                    ((uint32_t)0x80000000)        /*!< Bit 1 */
+
+/*!<******************  Bit definition for GPIO_IDR register  *******************/
+#define GPIO_IDR_IDR0                        ((uint16_t)0x0001)            /*!< Port input data, bit 0 */
+#define GPIO_IDR_IDR1                        ((uint16_t)0x0002)            /*!< Port input data, bit 1 */
+#define GPIO_IDR_IDR2                        ((uint16_t)0x0004)            /*!< Port input data, bit 2 */
+#define GPIO_IDR_IDR3                        ((uint16_t)0x0008)            /*!< Port input data, bit 3 */
+#define GPIO_IDR_IDR4                        ((uint16_t)0x0010)            /*!< Port input data, bit 4 */
+#define GPIO_IDR_IDR5                        ((uint16_t)0x0020)            /*!< Port input data, bit 5 */
+#define GPIO_IDR_IDR6                        ((uint16_t)0x0040)            /*!< Port input data, bit 6 */
+#define GPIO_IDR_IDR7                        ((uint16_t)0x0080)            /*!< Port input data, bit 7 */
+#define GPIO_IDR_IDR8                        ((uint16_t)0x0100)            /*!< Port input data, bit 8 */
+#define GPIO_IDR_IDR9                        ((uint16_t)0x0200)            /*!< Port input data, bit 9 */
+#define GPIO_IDR_IDR10                       ((uint16_t)0x0400)            /*!< Port input data, bit 10 */
+#define GPIO_IDR_IDR11                       ((uint16_t)0x0800)            /*!< Port input data, bit 11 */
+#define GPIO_IDR_IDR12                       ((uint16_t)0x1000)            /*!< Port input data, bit 12 */
+#define GPIO_IDR_IDR13                       ((uint16_t)0x2000)            /*!< Port input data, bit 13 */
+#define GPIO_IDR_IDR14                       ((uint16_t)0x4000)            /*!< Port input data, bit 14 */
+#define GPIO_IDR_IDR15                       ((uint16_t)0x8000)            /*!< Port input data, bit 15 */
+
+/*******************  Bit definition for GPIO_ODR register  *******************/
+#define GPIO_ODR_ODR0                        ((uint16_t)0x0001)            /*!< Port output data, bit 0 */
+#define GPIO_ODR_ODR1                        ((uint16_t)0x0002)            /*!< Port output data, bit 1 */
+#define GPIO_ODR_ODR2                        ((uint16_t)0x0004)            /*!< Port output data, bit 2 */
+#define GPIO_ODR_ODR3                        ((uint16_t)0x0008)            /*!< Port output data, bit 3 */
+#define GPIO_ODR_ODR4                        ((uint16_t)0x0010)            /*!< Port output data, bit 4 */
+#define GPIO_ODR_ODR5                        ((uint16_t)0x0020)            /*!< Port output data, bit 5 */
+#define GPIO_ODR_ODR6                        ((uint16_t)0x0040)            /*!< Port output data, bit 6 */
+#define GPIO_ODR_ODR7                        ((uint16_t)0x0080)            /*!< Port output data, bit 7 */
+#define GPIO_ODR_ODR8                        ((uint16_t)0x0100)            /*!< Port output data, bit 8 */
+#define GPIO_ODR_ODR9                        ((uint16_t)0x0200)            /*!< Port output data, bit 9 */
+#define GPIO_ODR_ODR10                       ((uint16_t)0x0400)            /*!< Port output data, bit 10 */
+#define GPIO_ODR_ODR11                       ((uint16_t)0x0800)            /*!< Port output data, bit 11 */
+#define GPIO_ODR_ODR12                       ((uint16_t)0x1000)            /*!< Port output data, bit 12 */
+#define GPIO_ODR_ODR13                       ((uint16_t)0x2000)            /*!< Port output data, bit 13 */
+#define GPIO_ODR_ODR14                       ((uint16_t)0x4000)            /*!< Port output data, bit 14 */
+#define GPIO_ODR_ODR15                       ((uint16_t)0x8000)            /*!< Port output data, bit 15 */
+
+/******************  Bit definition for GPIO_BSRR register  *******************/
+#define GPIO_BSRR_BS0                        ((uint32_t)0x00000001)        /*!< Port x Set bit 0 */
+#define GPIO_BSRR_BS1                        ((uint32_t)0x00000002)        /*!< Port x Set bit 1 */
+#define GPIO_BSRR_BS2                        ((uint32_t)0x00000004)        /*!< Port x Set bit 2 */
+#define GPIO_BSRR_BS3                        ((uint32_t)0x00000008)        /*!< Port x Set bit 3 */
+#define GPIO_BSRR_BS4                        ((uint32_t)0x00000010)        /*!< Port x Set bit 4 */
+#define GPIO_BSRR_BS5                        ((uint32_t)0x00000020)        /*!< Port x Set bit 5 */
+#define GPIO_BSRR_BS6                        ((uint32_t)0x00000040)        /*!< Port x Set bit 6 */
+#define GPIO_BSRR_BS7                        ((uint32_t)0x00000080)        /*!< Port x Set bit 7 */
+#define GPIO_BSRR_BS8                        ((uint32_t)0x00000100)        /*!< Port x Set bit 8 */
+#define GPIO_BSRR_BS9                        ((uint32_t)0x00000200)        /*!< Port x Set bit 9 */
+#define GPIO_BSRR_BS10                       ((uint32_t)0x00000400)        /*!< Port x Set bit 10 */
+#define GPIO_BSRR_BS11                       ((uint32_t)0x00000800)        /*!< Port x Set bit 11 */
+#define GPIO_BSRR_BS12                       ((uint32_t)0x00001000)        /*!< Port x Set bit 12 */
+#define GPIO_BSRR_BS13                       ((uint32_t)0x00002000)        /*!< Port x Set bit 13 */
+#define GPIO_BSRR_BS14                       ((uint32_t)0x00004000)        /*!< Port x Set bit 14 */
+#define GPIO_BSRR_BS15                       ((uint32_t)0x00008000)        /*!< Port x Set bit 15 */
+
+#define GPIO_BSRR_BR0                        ((uint32_t)0x00010000)        /*!< Port x Reset bit 0 */
+#define GPIO_BSRR_BR1                        ((uint32_t)0x00020000)        /*!< Port x Reset bit 1 */
+#define GPIO_BSRR_BR2                        ((uint32_t)0x00040000)        /*!< Port x Reset bit 2 */
+#define GPIO_BSRR_BR3                        ((uint32_t)0x00080000)        /*!< Port x Reset bit 3 */
+#define GPIO_BSRR_BR4                        ((uint32_t)0x00100000)        /*!< Port x Reset bit 4 */
+#define GPIO_BSRR_BR5                        ((uint32_t)0x00200000)        /*!< Port x Reset bit 5 */
+#define GPIO_BSRR_BR6                        ((uint32_t)0x00400000)        /*!< Port x Reset bit 6 */
+#define GPIO_BSRR_BR7                        ((uint32_t)0x00800000)        /*!< Port x Reset bit 7 */
+#define GPIO_BSRR_BR8                        ((uint32_t)0x01000000)        /*!< Port x Reset bit 8 */
+#define GPIO_BSRR_BR9                        ((uint32_t)0x02000000)        /*!< Port x Reset bit 9 */
+#define GPIO_BSRR_BR10                       ((uint32_t)0x04000000)        /*!< Port x Reset bit 10 */
+#define GPIO_BSRR_BR11                       ((uint32_t)0x08000000)        /*!< Port x Reset bit 11 */
+#define GPIO_BSRR_BR12                       ((uint32_t)0x10000000)        /*!< Port x Reset bit 12 */
+#define GPIO_BSRR_BR13                       ((uint32_t)0x20000000)        /*!< Port x Reset bit 13 */
+#define GPIO_BSRR_BR14                       ((uint32_t)0x40000000)        /*!< Port x Reset bit 14 */
+#define GPIO_BSRR_BR15                       ((uint32_t)0x80000000)        /*!< Port x Reset bit 15 */
+
+/*******************  Bit definition for GPIO_BRR register  *******************/
+#define GPIO_BRR_BR0                         ((uint16_t)0x0001)            /*!< Port x Reset bit 0 */
+#define GPIO_BRR_BR1                         ((uint16_t)0x0002)            /*!< Port x Reset bit 1 */
+#define GPIO_BRR_BR2                         ((uint16_t)0x0004)            /*!< Port x Reset bit 2 */
+#define GPIO_BRR_BR3                         ((uint16_t)0x0008)            /*!< Port x Reset bit 3 */
+#define GPIO_BRR_BR4                         ((uint16_t)0x0010)            /*!< Port x Reset bit 4 */
+#define GPIO_BRR_BR5                         ((uint16_t)0x0020)            /*!< Port x Reset bit 5 */
+#define GPIO_BRR_BR6                         ((uint16_t)0x0040)            /*!< Port x Reset bit 6 */
+#define GPIO_BRR_BR7                         ((uint16_t)0x0080)            /*!< Port x Reset bit 7 */
+#define GPIO_BRR_BR8                         ((uint16_t)0x0100)            /*!< Port x Reset bit 8 */
+#define GPIO_BRR_BR9                         ((uint16_t)0x0200)            /*!< Port x Reset bit 9 */
+#define GPIO_BRR_BR10                        ((uint16_t)0x0400)            /*!< Port x Reset bit 10 */
+#define GPIO_BRR_BR11                        ((uint16_t)0x0800)            /*!< Port x Reset bit 11 */
+#define GPIO_BRR_BR12                        ((uint16_t)0x1000)            /*!< Port x Reset bit 12 */
+#define GPIO_BRR_BR13                        ((uint16_t)0x2000)            /*!< Port x Reset bit 13 */
+#define GPIO_BRR_BR14                        ((uint16_t)0x4000)            /*!< Port x Reset bit 14 */
+#define GPIO_BRR_BR15                        ((uint16_t)0x8000)            /*!< Port x Reset bit 15 */
+
+/******************  Bit definition for GPIO_LCKR register  *******************/
+#define GPIO_LCKR_LCK0                       ((uint32_t)0x00000001)        /*!< Port x Lock bit 0 */
+#define GPIO_LCKR_LCK1                       ((uint32_t)0x00000002)        /*!< Port x Lock bit 1 */
+#define GPIO_LCKR_LCK2                       ((uint32_t)0x00000004)        /*!< Port x Lock bit 2 */
+#define GPIO_LCKR_LCK3                       ((uint32_t)0x00000008)        /*!< Port x Lock bit 3 */
+#define GPIO_LCKR_LCK4                       ((uint32_t)0x00000010)        /*!< Port x Lock bit 4 */
+#define GPIO_LCKR_LCK5                       ((uint32_t)0x00000020)        /*!< Port x Lock bit 5 */
+#define GPIO_LCKR_LCK6                       ((uint32_t)0x00000040)        /*!< Port x Lock bit 6 */
+#define GPIO_LCKR_LCK7                       ((uint32_t)0x00000080)        /*!< Port x Lock bit 7 */
+#define GPIO_LCKR_LCK8                       ((uint32_t)0x00000100)        /*!< Port x Lock bit 8 */
+#define GPIO_LCKR_LCK9                       ((uint32_t)0x00000200)        /*!< Port x Lock bit 9 */
+#define GPIO_LCKR_LCK10                      ((uint32_t)0x00000400)        /*!< Port x Lock bit 10 */
+#define GPIO_LCKR_LCK11                      ((uint32_t)0x00000800)        /*!< Port x Lock bit 11 */
+#define GPIO_LCKR_LCK12                      ((uint32_t)0x00001000)        /*!< Port x Lock bit 12 */
+#define GPIO_LCKR_LCK13                      ((uint32_t)0x00002000)        /*!< Port x Lock bit 13 */
+#define GPIO_LCKR_LCK14                      ((uint32_t)0x00004000)        /*!< Port x Lock bit 14 */
+#define GPIO_LCKR_LCK15                      ((uint32_t)0x00008000)        /*!< Port x Lock bit 15 */
+#define GPIO_LCKR_LCKK                       ((uint32_t)0x00010000)        /*!< Lock key */
+
+/*----------------------------------------------------------------------------*/
+
+/******************  Bit definition for AFIO_EVCR register  *******************/
+#define AFIO_EVCR_PIN                        ((uint8_t)0x0F)               /*!< PIN[3:0] bits (Pin selection) */
+#define AFIO_EVCR_PIN_0                      ((uint8_t)0x01)               /*!< Bit 0 */
+#define AFIO_EVCR_PIN_1                      ((uint8_t)0x02)               /*!< Bit 1 */
+#define AFIO_EVCR_PIN_2                      ((uint8_t)0x04)               /*!< Bit 2 */
+#define AFIO_EVCR_PIN_3                      ((uint8_t)0x08)               /*!< Bit 3 */
+
+/*!< PIN configuration */
+#define AFIO_EVCR_PIN_PX0                    ((uint8_t)0x00)               /*!< Pin 0 selected */
+#define AFIO_EVCR_PIN_PX1                    ((uint8_t)0x01)               /*!< Pin 1 selected */
+#define AFIO_EVCR_PIN_PX2                    ((uint8_t)0x02)               /*!< Pin 2 selected */
+#define AFIO_EVCR_PIN_PX3                    ((uint8_t)0x03)               /*!< Pin 3 selected */
+#define AFIO_EVCR_PIN_PX4                    ((uint8_t)0x04)               /*!< Pin 4 selected */
+#define AFIO_EVCR_PIN_PX5                    ((uint8_t)0x05)               /*!< Pin 5 selected */
+#define AFIO_EVCR_PIN_PX6                    ((uint8_t)0x06)               /*!< Pin 6 selected */
+#define AFIO_EVCR_PIN_PX7                    ((uint8_t)0x07)               /*!< Pin 7 selected */
+#define AFIO_EVCR_PIN_PX8                    ((uint8_t)0x08)               /*!< Pin 8 selected */
+#define AFIO_EVCR_PIN_PX9                    ((uint8_t)0x09)               /*!< Pin 9 selected */
+#define AFIO_EVCR_PIN_PX10                   ((uint8_t)0x0A)               /*!< Pin 10 selected */
+#define AFIO_EVCR_PIN_PX11                   ((uint8_t)0x0B)               /*!< Pin 11 selected */
+#define AFIO_EVCR_PIN_PX12                   ((uint8_t)0x0C)               /*!< Pin 12 selected */
+#define AFIO_EVCR_PIN_PX13                   ((uint8_t)0x0D)               /*!< Pin 13 selected */
+#define AFIO_EVCR_PIN_PX14                   ((uint8_t)0x0E)               /*!< Pin 14 selected */
+#define AFIO_EVCR_PIN_PX15                   ((uint8_t)0x0F)               /*!< Pin 15 selected */
+
+#define AFIO_EVCR_PORT                       ((uint8_t)0x70)               /*!< PORT[2:0] bits (Port selection) */
+#define AFIO_EVCR_PORT_0                     ((uint8_t)0x10)               /*!< Bit 0 */
+#define AFIO_EVCR_PORT_1                     ((uint8_t)0x20)               /*!< Bit 1 */
+#define AFIO_EVCR_PORT_2                     ((uint8_t)0x40)               /*!< Bit 2 */
+
+/*!< PORT configuration */
+#define AFIO_EVCR_PORT_PA                    ((uint8_t)0x00)               /*!< Port A selected */
+#define AFIO_EVCR_PORT_PB                    ((uint8_t)0x10)               /*!< Port B selected */
+#define AFIO_EVCR_PORT_PC                    ((uint8_t)0x20)               /*!< Port C selected */
+#define AFIO_EVCR_PORT_PD                    ((uint8_t)0x30)               /*!< Port D selected */
+#define AFIO_EVCR_PORT_PE                    ((uint8_t)0x40)               /*!< Port E selected */
+
+#define AFIO_EVCR_EVOE                       ((uint8_t)0x80)               /*!< Event Output Enable */
+
+/******************  Bit definition for AFIO_MAPR register  *******************/
+#define AFIO_MAPR_SPI1_REMAP                 ((uint32_t)0x00000001)        /*!< SPI1 remapping */
+#define AFIO_MAPR_I2C1_REMAP                 ((uint32_t)0x00000002)        /*!< I2C1 remapping */
+#define AFIO_MAPR_USART1_REMAP               ((uint32_t)0x00000004)        /*!< USART1 remapping */
+#define AFIO_MAPR_USART2_REMAP               ((uint32_t)0x00000008)        /*!< USART2 remapping */
+
+#define AFIO_MAPR_USART3_REMAP               ((uint32_t)0x00000030)        /*!< USART3_REMAP[1:0] bits (USART3 remapping) */
+#define AFIO_MAPR_USART3_REMAP_0             ((uint32_t)0x00000010)        /*!< Bit 0 */
+#define AFIO_MAPR_USART3_REMAP_1             ((uint32_t)0x00000020)        /*!< Bit 1 */
+
+/* USART3_REMAP configuration */
+#define AFIO_MAPR_USART3_REMAP_NOREMAP       ((uint32_t)0x00000000)        /*!< No remap (TX/PB10, RX/PB11, CK/PB12, CTS/PB13, RTS/PB14) */
+#define AFIO_MAPR_USART3_REMAP_PARTIALREMAP  ((uint32_t)0x00000010)        /*!< Partial remap (TX/PC10, RX/PC11, CK/PC12, CTS/PB13, RTS/PB14) */
+#define AFIO_MAPR_USART3_REMAP_FULLREMAP     ((uint32_t)0x00000030)        /*!< Full remap (TX/PD8, RX/PD9, CK/PD10, CTS/PD11, RTS/PD12) */
+
+#define AFIO_MAPR_TIM1_REMAP                 ((uint32_t)0x000000C0)        /*!< TIM1_REMAP[1:0] bits (TIM1 remapping) */
+#define AFIO_MAPR_TIM1_REMAP_0               ((uint32_t)0x00000040)        /*!< Bit 0 */
+#define AFIO_MAPR_TIM1_REMAP_1               ((uint32_t)0x00000080)        /*!< Bit 1 */
+
+/*!< TIM1_REMAP configuration */
+#define AFIO_MAPR_TIM1_REMAP_NOREMAP         ((uint32_t)0x00000000)        /*!< No remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PB12, CH1N/PB13, CH2N/PB14, CH3N/PB15) */
+#define AFIO_MAPR_TIM1_REMAP_PARTIALREMAP    ((uint32_t)0x00000040)        /*!< Partial remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PA6, CH1N/PA7, CH2N/PB0, CH3N/PB1) */
+#define AFIO_MAPR_TIM1_REMAP_FULLREMAP       ((uint32_t)0x000000C0)        /*!< Full remap (ETR/PE7, CH1/PE9, CH2/PE11, CH3/PE13, CH4/PE14, BKIN/PE15, CH1N/PE8, CH2N/PE10, CH3N/PE12) */
+
+#define AFIO_MAPR_TIM2_REMAP                 ((uint32_t)0x00000300)        /*!< TIM2_REMAP[1:0] bits (TIM2 remapping) */
+#define AFIO_MAPR_TIM2_REMAP_0               ((uint32_t)0x00000100)        /*!< Bit 0 */
+#define AFIO_MAPR_TIM2_REMAP_1               ((uint32_t)0x00000200)        /*!< Bit 1 */
+
+/*!< TIM2_REMAP configuration */
+#define AFIO_MAPR_TIM2_REMAP_NOREMAP         ((uint32_t)0x00000000)        /*!< No remap (CH1/ETR/PA0, CH2/PA1, CH3/PA2, CH4/PA3) */
+#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1   ((uint32_t)0x00000100)        /*!< Partial remap (CH1/ETR/PA15, CH2/PB3, CH3/PA2, CH4/PA3) */
+#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2   ((uint32_t)0x00000200)        /*!< Partial remap (CH1/ETR/PA0, CH2/PA1, CH3/PB10, CH4/PB11) */
+#define AFIO_MAPR_TIM2_REMAP_FULLREMAP       ((uint32_t)0x00000300)        /*!< Full remap (CH1/ETR/PA15, CH2/PB3, CH3/PB10, CH4/PB11) */
+
+#define AFIO_MAPR_TIM3_REMAP                 ((uint32_t)0x00000C00)        /*!< TIM3_REMAP[1:0] bits (TIM3 remapping) */
+#define AFIO_MAPR_TIM3_REMAP_0               ((uint32_t)0x00000400)        /*!< Bit 0 */
+#define AFIO_MAPR_TIM3_REMAP_1               ((uint32_t)0x00000800)        /*!< Bit 1 */
+
+/*!< TIM3_REMAP configuration */
+#define AFIO_MAPR_TIM3_REMAP_NOREMAP         ((uint32_t)0x00000000)        /*!< No remap (CH1/PA6, CH2/PA7, CH3/PB0, CH4/PB1) */
+#define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP    ((uint32_t)0x00000800)        /*!< Partial remap (CH1/PB4, CH2/PB5, CH3/PB0, CH4/PB1) */
+#define AFIO_MAPR_TIM3_REMAP_FULLREMAP       ((uint32_t)0x00000C00)        /*!< Full remap (CH1/PC6, CH2/PC7, CH3/PC8, CH4/PC9) */
+
+#define AFIO_MAPR_TIM4_REMAP                 ((uint32_t)0x00001000)        /*!< TIM4_REMAP bit (TIM4 remapping) */
+
+#define AFIO_MAPR_CAN_REMAP                  ((uint32_t)0x00006000)        /*!< CAN_REMAP[1:0] bits (CAN Alternate function remapping) */
+#define AFIO_MAPR_CAN_REMAP_0                ((uint32_t)0x00002000)        /*!< Bit 0 */
+#define AFIO_MAPR_CAN_REMAP_1                ((uint32_t)0x00004000)        /*!< Bit 1 */
+
+/*!< CAN_REMAP configuration */
+#define AFIO_MAPR_CAN_REMAP_REMAP1           ((uint32_t)0x00000000)        /*!< CANRX mapped to PA11, CANTX mapped to PA12 */
+#define AFIO_MAPR_CAN_REMAP_REMAP2           ((uint32_t)0x00004000)        /*!< CANRX mapped to PB8, CANTX mapped to PB9 */
+#define AFIO_MAPR_CAN_REMAP_REMAP3           ((uint32_t)0x00006000)        /*!< CANRX mapped to PD0, CANTX mapped to PD1 */
+
+#define AFIO_MAPR_PD01_REMAP                 ((uint32_t)0x00008000)        /*!< Port D0/Port D1 mapping on OSC_IN/OSC_OUT */
+#define AFIO_MAPR_TIM5CH4_IREMAP             ((uint32_t)0x00010000)        /*!< TIM5 Channel4 Internal Remap */
+#define AFIO_MAPR_ADC1_ETRGINJ_REMAP         ((uint32_t)0x00020000)        /*!< ADC 1 External Trigger Injected Conversion remapping */
+#define AFIO_MAPR_ADC1_ETRGREG_REMAP         ((uint32_t)0x00040000)        /*!< ADC 1 External Trigger Regular Conversion remapping */
+#define AFIO_MAPR_ADC2_ETRGINJ_REMAP         ((uint32_t)0x00080000)        /*!< ADC 2 External Trigger Injected Conversion remapping */
+#define AFIO_MAPR_ADC2_ETRGREG_REMAP         ((uint32_t)0x00100000)        /*!< ADC 2 External Trigger Regular Conversion remapping */
+
+/*!< SWJ_CFG configuration */
+#define AFIO_MAPR_SWJ_CFG                    ((uint32_t)0x07000000)        /*!< SWJ_CFG[2:0] bits (Serial Wire JTAG configuration) */
+#define AFIO_MAPR_SWJ_CFG_0                  ((uint32_t)0x01000000)        /*!< Bit 0 */
+#define AFIO_MAPR_SWJ_CFG_1                  ((uint32_t)0x02000000)        /*!< Bit 1 */
+#define AFIO_MAPR_SWJ_CFG_2                  ((uint32_t)0x04000000)        /*!< Bit 2 */
+
+#define AFIO_MAPR_SWJ_CFG_RESET              ((uint32_t)0x00000000)        /*!< Full SWJ (JTAG-DP + SW-DP) : Reset State */
+#define AFIO_MAPR_SWJ_CFG_NOJNTRST           ((uint32_t)0x01000000)        /*!< Full SWJ (JTAG-DP + SW-DP) but without JNTRST */
+#define AFIO_MAPR_SWJ_CFG_JTAGDISABLE        ((uint32_t)0x02000000)        /*!< JTAG-DP Disabled and SW-DP Enabled */
+#define AFIO_MAPR_SWJ_CFG_DISABLE            ((uint32_t)0x04000000)        /*!< JTAG-DP Disabled and SW-DP Disabled */
+
+#ifdef STM32F10X_CL
+/*!< ETH_REMAP configuration */
+ #define AFIO_MAPR_ETH_REMAP                  ((uint32_t)0x00200000)        /*!< SPI3_REMAP bit (Ethernet MAC I/O remapping) */
+
+/*!< CAN2_REMAP configuration */
+ #define AFIO_MAPR_CAN2_REMAP                 ((uint32_t)0x00400000)        /*!< CAN2_REMAP bit (CAN2 I/O remapping) */
+
+/*!< MII_RMII_SEL configuration */
+ #define AFIO_MAPR_MII_RMII_SEL               ((uint32_t)0x00800000)        /*!< MII_RMII_SEL bit (Ethernet MII or RMII selection) */
+
+/*!< SPI3_REMAP configuration */
+ #define AFIO_MAPR_SPI3_REMAP                 ((uint32_t)0x10000000)        /*!< SPI3_REMAP bit (SPI3 remapping) */
+
+/*!< TIM2ITR1_IREMAP configuration */
+ #define AFIO_MAPR_TIM2ITR1_IREMAP            ((uint32_t)0x20000000)        /*!< TIM2ITR1_IREMAP bit (TIM2 internal trigger 1 remapping) */
+
+/*!< PTP_PPS_REMAP configuration */
+ #define AFIO_MAPR_PTP_PPS_REMAP              ((uint32_t)0x40000000)        /*!< PTP_PPS_REMAP bit (Ethernet PTP PPS remapping) */
+#endif
+
+/*****************  Bit definition for AFIO_EXTICR1 register  *****************/
+#define AFIO_EXTICR1_EXTI0                   ((uint16_t)0x000F)            /*!< EXTI 0 configuration */
+#define AFIO_EXTICR1_EXTI1                   ((uint16_t)0x00F0)            /*!< EXTI 1 configuration */
+#define AFIO_EXTICR1_EXTI2                   ((uint16_t)0x0F00)            /*!< EXTI 2 configuration */
+#define AFIO_EXTICR1_EXTI3                   ((uint16_t)0xF000)            /*!< EXTI 3 configuration */
+
+/*!< EXTI0 configuration */
+#define AFIO_EXTICR1_EXTI0_PA                ((uint16_t)0x0000)            /*!< PA[0] pin */
+#define AFIO_EXTICR1_EXTI0_PB                ((uint16_t)0x0001)            /*!< PB[0] pin */
+#define AFIO_EXTICR1_EXTI0_PC                ((uint16_t)0x0002)            /*!< PC[0] pin */
+#define AFIO_EXTICR1_EXTI0_PD                ((uint16_t)0x0003)            /*!< PD[0] pin */
+#define AFIO_EXTICR1_EXTI0_PE                ((uint16_t)0x0004)            /*!< PE[0] pin */
+#define AFIO_EXTICR1_EXTI0_PF                ((uint16_t)0x0005)            /*!< PF[0] pin */
+#define AFIO_EXTICR1_EXTI0_PG                ((uint16_t)0x0006)            /*!< PG[0] pin */
+
+/*!< EXTI1 configuration */
+#define AFIO_EXTICR1_EXTI1_PA                ((uint16_t)0x0000)            /*!< PA[1] pin */
+#define AFIO_EXTICR1_EXTI1_PB                ((uint16_t)0x0010)            /*!< PB[1] pin */
+#define AFIO_EXTICR1_EXTI1_PC                ((uint16_t)0x0020)            /*!< PC[1] pin */
+#define AFIO_EXTICR1_EXTI1_PD                ((uint16_t)0x0030)            /*!< PD[1] pin */
+#define AFIO_EXTICR1_EXTI1_PE                ((uint16_t)0x0040)            /*!< PE[1] pin */
+#define AFIO_EXTICR1_EXTI1_PF                ((uint16_t)0x0050)            /*!< PF[1] pin */
+#define AFIO_EXTICR1_EXTI1_PG                ((uint16_t)0x0060)            /*!< PG[1] pin */
+
+/*!< EXTI2 configuration */  
+#define AFIO_EXTICR1_EXTI2_PA                ((uint16_t)0x0000)            /*!< PA[2] pin */
+#define AFIO_EXTICR1_EXTI2_PB                ((uint16_t)0x0100)            /*!< PB[2] pin */
+#define AFIO_EXTICR1_EXTI2_PC                ((uint16_t)0x0200)            /*!< PC[2] pin */
+#define AFIO_EXTICR1_EXTI2_PD                ((uint16_t)0x0300)            /*!< PD[2] pin */
+#define AFIO_EXTICR1_EXTI2_PE                ((uint16_t)0x0400)            /*!< PE[2] pin */
+#define AFIO_EXTICR1_EXTI2_PF                ((uint16_t)0x0500)            /*!< PF[2] pin */
+#define AFIO_EXTICR1_EXTI2_PG                ((uint16_t)0x0600)            /*!< PG[2] pin */
+
+/*!< EXTI3 configuration */
+#define AFIO_EXTICR1_EXTI3_PA                ((uint16_t)0x0000)            /*!< PA[3] pin */
+#define AFIO_EXTICR1_EXTI3_PB                ((uint16_t)0x1000)            /*!< PB[3] pin */
+#define AFIO_EXTICR1_EXTI3_PC                ((uint16_t)0x2000)            /*!< PC[3] pin */
+#define AFIO_EXTICR1_EXTI3_PD                ((uint16_t)0x3000)            /*!< PD[3] pin */
+#define AFIO_EXTICR1_EXTI3_PE                ((uint16_t)0x4000)            /*!< PE[3] pin */
+#define AFIO_EXTICR1_EXTI3_PF                ((uint16_t)0x5000)            /*!< PF[3] pin */
+#define AFIO_EXTICR1_EXTI3_PG                ((uint16_t)0x6000)            /*!< PG[3] pin */
+
+/*****************  Bit definition for AFIO_EXTICR2 register  *****************/
+#define AFIO_EXTICR2_EXTI4                   ((uint16_t)0x000F)            /*!< EXTI 4 configuration */
+#define AFIO_EXTICR2_EXTI5                   ((uint16_t)0x00F0)            /*!< EXTI 5 configuration */
+#define AFIO_EXTICR2_EXTI6                   ((uint16_t)0x0F00)            /*!< EXTI 6 configuration */
+#define AFIO_EXTICR2_EXTI7                   ((uint16_t)0xF000)            /*!< EXTI 7 configuration */
+
+/*!< EXTI4 configuration */
+#define AFIO_EXTICR2_EXTI4_PA                ((uint16_t)0x0000)            /*!< PA[4] pin */
+#define AFIO_EXTICR2_EXTI4_PB                ((uint16_t)0x0001)            /*!< PB[4] pin */
+#define AFIO_EXTICR2_EXTI4_PC                ((uint16_t)0x0002)            /*!< PC[4] pin */
+#define AFIO_EXTICR2_EXTI4_PD                ((uint16_t)0x0003)            /*!< PD[4] pin */
+#define AFIO_EXTICR2_EXTI4_PE                ((uint16_t)0x0004)            /*!< PE[4] pin */
+#define AFIO_EXTICR2_EXTI4_PF                ((uint16_t)0x0005)            /*!< PF[4] pin */
+#define AFIO_EXTICR2_EXTI4_PG                ((uint16_t)0x0006)            /*!< PG[4] pin */
+
+/* EXTI5 configuration */
+#define AFIO_EXTICR2_EXTI5_PA                ((uint16_t)0x0000)            /*!< PA[5] pin */
+#define AFIO_EXTICR2_EXTI5_PB                ((uint16_t)0x0010)            /*!< PB[5] pin */
+#define AFIO_EXTICR2_EXTI5_PC                ((uint16_t)0x0020)            /*!< PC[5] pin */
+#define AFIO_EXTICR2_EXTI5_PD                ((uint16_t)0x0030)            /*!< PD[5] pin */
+#define AFIO_EXTICR2_EXTI5_PE                ((uint16_t)0x0040)            /*!< PE[5] pin */
+#define AFIO_EXTICR2_EXTI5_PF                ((uint16_t)0x0050)            /*!< PF[5] pin */
+#define AFIO_EXTICR2_EXTI5_PG                ((uint16_t)0x0060)            /*!< PG[5] pin */
+
+/*!< EXTI6 configuration */  
+#define AFIO_EXTICR2_EXTI6_PA                ((uint16_t)0x0000)            /*!< PA[6] pin */
+#define AFIO_EXTICR2_EXTI6_PB                ((uint16_t)0x0100)            /*!< PB[6] pin */
+#define AFIO_EXTICR2_EXTI6_PC                ((uint16_t)0x0200)            /*!< PC[6] pin */
+#define AFIO_EXTICR2_EXTI6_PD                ((uint16_t)0x0300)            /*!< PD[6] pin */
+#define AFIO_EXTICR2_EXTI6_PE                ((uint16_t)0x0400)            /*!< PE[6] pin */
+#define AFIO_EXTICR2_EXTI6_PF                ((uint16_t)0x0500)            /*!< PF[6] pin */
+#define AFIO_EXTICR2_EXTI6_PG                ((uint16_t)0x0600)            /*!< PG[6] pin */
+
+/*!< EXTI7 configuration */
+#define AFIO_EXTICR2_EXTI7_PA                ((uint16_t)0x0000)            /*!< PA[7] pin */
+#define AFIO_EXTICR2_EXTI7_PB                ((uint16_t)0x1000)            /*!< PB[7] pin */
+#define AFIO_EXTICR2_EXTI7_PC                ((uint16_t)0x2000)            /*!< PC[7] pin */
+#define AFIO_EXTICR2_EXTI7_PD                ((uint16_t)0x3000)            /*!< PD[7] pin */
+#define AFIO_EXTICR2_EXTI7_PE                ((uint16_t)0x4000)            /*!< PE[7] pin */
+#define AFIO_EXTICR2_EXTI7_PF                ((uint16_t)0x5000)            /*!< PF[7] pin */
+#define AFIO_EXTICR2_EXTI7_PG                ((uint16_t)0x6000)            /*!< PG[7] pin */
+
+/*****************  Bit definition for AFIO_EXTICR3 register  *****************/
+#define AFIO_EXTICR3_EXTI8                   ((uint16_t)0x000F)            /*!< EXTI 8 configuration */
+#define AFIO_EXTICR3_EXTI9                   ((uint16_t)0x00F0)            /*!< EXTI 9 configuration */
+#define AFIO_EXTICR3_EXTI10                  ((uint16_t)0x0F00)            /*!< EXTI 10 configuration */
+#define AFIO_EXTICR3_EXTI11                  ((uint16_t)0xF000)            /*!< EXTI 11 configuration */
+
+/*!< EXTI8 configuration */
+#define AFIO_EXTICR3_EXTI8_PA                ((uint16_t)0x0000)            /*!< PA[8] pin */
+#define AFIO_EXTICR3_EXTI8_PB                ((uint16_t)0x0001)            /*!< PB[8] pin */
+#define AFIO_EXTICR3_EXTI8_PC                ((uint16_t)0x0002)            /*!< PC[8] pin */
+#define AFIO_EXTICR3_EXTI8_PD                ((uint16_t)0x0003)            /*!< PD[8] pin */
+#define AFIO_EXTICR3_EXTI8_PE                ((uint16_t)0x0004)            /*!< PE[8] pin */
+#define AFIO_EXTICR3_EXTI8_PF                ((uint16_t)0x0005)            /*!< PF[8] pin */
+#define AFIO_EXTICR3_EXTI8_PG                ((uint16_t)0x0006)            /*!< PG[8] pin */
+
+/*!< EXTI9 configuration */
+#define AFIO_EXTICR3_EXTI9_PA                ((uint16_t)0x0000)            /*!< PA[9] pin */
+#define AFIO_EXTICR3_EXTI9_PB                ((uint16_t)0x0010)            /*!< PB[9] pin */
+#define AFIO_EXTICR3_EXTI9_PC                ((uint16_t)0x0020)            /*!< PC[9] pin */
+#define AFIO_EXTICR3_EXTI9_PD                ((uint16_t)0x0030)            /*!< PD[9] pin */
+#define AFIO_EXTICR3_EXTI9_PE                ((uint16_t)0x0040)            /*!< PE[9] pin */
+#define AFIO_EXTICR3_EXTI9_PF                ((uint16_t)0x0050)            /*!< PF[9] pin */
+#define AFIO_EXTICR3_EXTI9_PG                ((uint16_t)0x0060)            /*!< PG[9] pin */
+
+/*!< EXTI10 configuration */  
+#define AFIO_EXTICR3_EXTI10_PA               ((uint16_t)0x0000)            /*!< PA[10] pin */
+#define AFIO_EXTICR3_EXTI10_PB               ((uint16_t)0x0100)            /*!< PB[10] pin */
+#define AFIO_EXTICR3_EXTI10_PC               ((uint16_t)0x0200)            /*!< PC[10] pin */
+#define AFIO_EXTICR3_EXTI10_PD               ((uint16_t)0x0300)            /*!< PD[10] pin */
+#define AFIO_EXTICR3_EXTI10_PE               ((uint16_t)0x0400)            /*!< PE[10] pin */
+#define AFIO_EXTICR3_EXTI10_PF               ((uint16_t)0x0500)            /*!< PF[10] pin */
+#define AFIO_EXTICR3_EXTI10_PG               ((uint16_t)0x0600)            /*!< PG[10] pin */
+
+/*!< EXTI11 configuration */
+#define AFIO_EXTICR3_EXTI11_PA               ((uint16_t)0x0000)            /*!< PA[11] pin */
+#define AFIO_EXTICR3_EXTI11_PB               ((uint16_t)0x1000)            /*!< PB[11] pin */
+#define AFIO_EXTICR3_EXTI11_PC               ((uint16_t)0x2000)            /*!< PC[11] pin */
+#define AFIO_EXTICR3_EXTI11_PD               ((uint16_t)0x3000)            /*!< PD[11] pin */
+#define AFIO_EXTICR3_EXTI11_PE               ((uint16_t)0x4000)            /*!< PE[11] pin */
+#define AFIO_EXTICR3_EXTI11_PF               ((uint16_t)0x5000)            /*!< PF[11] pin */
+#define AFIO_EXTICR3_EXTI11_PG               ((uint16_t)0x6000)            /*!< PG[11] pin */
+
+/*****************  Bit definition for AFIO_EXTICR4 register  *****************/
+#define AFIO_EXTICR4_EXTI12                  ((uint16_t)0x000F)            /*!< EXTI 12 configuration */
+#define AFIO_EXTICR4_EXTI13                  ((uint16_t)0x00F0)            /*!< EXTI 13 configuration */
+#define AFIO_EXTICR4_EXTI14                  ((uint16_t)0x0F00)            /*!< EXTI 14 configuration */
+#define AFIO_EXTICR4_EXTI15                  ((uint16_t)0xF000)            /*!< EXTI 15 configuration */
+
+/* EXTI12 configuration */
+#define AFIO_EXTICR4_EXTI12_PA               ((uint16_t)0x0000)            /*!< PA[12] pin */
+#define AFIO_EXTICR4_EXTI12_PB               ((uint16_t)0x0001)            /*!< PB[12] pin */
+#define AFIO_EXTICR4_EXTI12_PC               ((uint16_t)0x0002)            /*!< PC[12] pin */
+#define AFIO_EXTICR4_EXTI12_PD               ((uint16_t)0x0003)            /*!< PD[12] pin */
+#define AFIO_EXTICR4_EXTI12_PE               ((uint16_t)0x0004)            /*!< PE[12] pin */
+#define AFIO_EXTICR4_EXTI12_PF               ((uint16_t)0x0005)            /*!< PF[12] pin */
+#define AFIO_EXTICR4_EXTI12_PG               ((uint16_t)0x0006)            /*!< PG[12] pin */
+
+/* EXTI13 configuration */
+#define AFIO_EXTICR4_EXTI13_PA               ((uint16_t)0x0000)            /*!< PA[13] pin */
+#define AFIO_EXTICR4_EXTI13_PB               ((uint16_t)0x0010)            /*!< PB[13] pin */
+#define AFIO_EXTICR4_EXTI13_PC               ((uint16_t)0x0020)            /*!< PC[13] pin */
+#define AFIO_EXTICR4_EXTI13_PD               ((uint16_t)0x0030)            /*!< PD[13] pin */
+#define AFIO_EXTICR4_EXTI13_PE               ((uint16_t)0x0040)            /*!< PE[13] pin */
+#define AFIO_EXTICR4_EXTI13_PF               ((uint16_t)0x0050)            /*!< PF[13] pin */
+#define AFIO_EXTICR4_EXTI13_PG               ((uint16_t)0x0060)            /*!< PG[13] pin */
+
+/*!< EXTI14 configuration */  
+#define AFIO_EXTICR4_EXTI14_PA               ((uint16_t)0x0000)            /*!< PA[14] pin */
+#define AFIO_EXTICR4_EXTI14_PB               ((uint16_t)0x0100)            /*!< PB[14] pin */
+#define AFIO_EXTICR4_EXTI14_PC               ((uint16_t)0x0200)            /*!< PC[14] pin */
+#define AFIO_EXTICR4_EXTI14_PD               ((uint16_t)0x0300)            /*!< PD[14] pin */
+#define AFIO_EXTICR4_EXTI14_PE               ((uint16_t)0x0400)            /*!< PE[14] pin */
+#define AFIO_EXTICR4_EXTI14_PF               ((uint16_t)0x0500)            /*!< PF[14] pin */
+#define AFIO_EXTICR4_EXTI14_PG               ((uint16_t)0x0600)            /*!< PG[14] pin */
+
+/*!< EXTI15 configuration */
+#define AFIO_EXTICR4_EXTI15_PA               ((uint16_t)0x0000)            /*!< PA[15] pin */
+#define AFIO_EXTICR4_EXTI15_PB               ((uint16_t)0x1000)            /*!< PB[15] pin */
+#define AFIO_EXTICR4_EXTI15_PC               ((uint16_t)0x2000)            /*!< PC[15] pin */
+#define AFIO_EXTICR4_EXTI15_PD               ((uint16_t)0x3000)            /*!< PD[15] pin */
+#define AFIO_EXTICR4_EXTI15_PE               ((uint16_t)0x4000)            /*!< PE[15] pin */
+#define AFIO_EXTICR4_EXTI15_PF               ((uint16_t)0x5000)            /*!< PF[15] pin */
+#define AFIO_EXTICR4_EXTI15_PG               ((uint16_t)0x6000)            /*!< PG[15] pin */
+
+#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
+/******************  Bit definition for AFIO_MAPR2 register  ******************/
+#define AFIO_MAPR2_TIM15_REMAP               ((uint32_t)0x00000001)        /*!< TIM15 remapping */
+#define AFIO_MAPR2_TIM16_REMAP               ((uint32_t)0x00000002)        /*!< TIM16 remapping */
+#define AFIO_MAPR2_TIM17_REMAP               ((uint32_t)0x00000004)        /*!< TIM17 remapping */
+#define AFIO_MAPR2_CEC_REMAP                 ((uint32_t)0x00000008)        /*!< CEC remapping */
+#define AFIO_MAPR2_TIM1_DMA_REMAP            ((uint32_t)0x00000010)        /*!< TIM1_DMA remapping */
+#endif
+
+#ifdef STM32F10X_HD_VL
+#define AFIO_MAPR2_TIM13_REMAP               ((uint32_t)0x00000100)        /*!< TIM13 remapping */
+#define AFIO_MAPR2_TIM14_REMAP               ((uint32_t)0x00000200)        /*!< TIM14 remapping */
+#define AFIO_MAPR2_FSMC_NADV_REMAP           ((uint32_t)0x00000400)        /*!< FSMC NADV remapping */
+#define AFIO_MAPR2_TIM67_DAC_DMA_REMAP       ((uint32_t)0x00000800)        /*!< TIM6/TIM7 and DAC DMA remapping */
+#define AFIO_MAPR2_TIM12_REMAP               ((uint32_t)0x00001000)        /*!< TIM12 remapping */
+#define AFIO_MAPR2_MISC_REMAP                ((uint32_t)0x00002000)        /*!< Miscellaneous remapping */
+#endif
+
+#ifdef STM32F10X_XL 
+/******************  Bit definition for AFIO_MAPR2 register  ******************/
+#define AFIO_MAPR2_TIM9_REMAP                ((uint32_t)0x00000020)        /*!< TIM9 remapping */
+#define AFIO_MAPR2_TIM10_REMAP               ((uint32_t)0x00000040)        /*!< TIM10 remapping */
+#define AFIO_MAPR2_TIM11_REMAP               ((uint32_t)0x00000080)        /*!< TIM11 remapping */
+#define AFIO_MAPR2_TIM13_REMAP               ((uint32_t)0x00000100)        /*!< TIM13 remapping */
+#define AFIO_MAPR2_TIM14_REMAP               ((uint32_t)0x00000200)        /*!< TIM14 remapping */
+#define AFIO_MAPR2_FSMC_NADV_REMAP           ((uint32_t)0x00000400)        /*!< FSMC NADV remapping */
+#endif
+
+/******************************************************************************/
+/*                                                                            */
+/*                               SystemTick                                   */
+/*                                                                            */
+/******************************************************************************/
+
+/*****************  Bit definition for SysTick_CTRL register  *****************/
+#define  SysTick_CTRL_ENABLE                 ((uint32_t)0x00000001)        /*!< Counter enable */
+#define  SysTick_CTRL_TICKINT                ((uint32_t)0x00000002)        /*!< Counting down to 0 pends the SysTick handler */
+#define  SysTick_CTRL_CLKSOURCE              ((uint32_t)0x00000004)        /*!< Clock source */
+#define  SysTick_CTRL_COUNTFLAG              ((uint32_t)0x00010000)        /*!< Count Flag */
+
+/*****************  Bit definition for SysTick_LOAD register  *****************/
+#define  SysTick_LOAD_RELOAD                 ((uint32_t)0x00FFFFFF)        /*!< Value to load into the SysTick Current Value Register when the counter reaches 0 */
+
+/*****************  Bit definition for SysTick_VAL register  ******************/
+#define  SysTick_VAL_CURRENT                 ((uint32_t)0x00FFFFFF)        /*!< Current value at the time the register is accessed */
+
+/*****************  Bit definition for SysTick_CALIB register  ****************/
+#define  SysTick_CALIB_TENMS                 ((uint32_t)0x00FFFFFF)        /*!< Reload value to use for 10ms timing */
+#define  SysTick_CALIB_SKEW                  ((uint32_t)0x40000000)        /*!< Calibration value is not exactly 10 ms */
+#define  SysTick_CALIB_NOREF                 ((uint32_t)0x80000000)        /*!< The reference clock is not provided */
+
+/******************************************************************************/
+/*                                                                            */
+/*                  Nested Vectored Interrupt Controller                      */
+/*                                                                            */
+/******************************************************************************/
+
+/******************  Bit definition for NVIC_ISER register  *******************/
+#define  NVIC_ISER_SETENA                    ((uint32_t)0xFFFFFFFF)        /*!< Interrupt set enable bits */
+#define  NVIC_ISER_SETENA_0                  ((uint32_t)0x00000001)        /*!< bit 0 */
+#define  NVIC_ISER_SETENA_1                  ((uint32_t)0x00000002)        /*!< bit 1 */
+#define  NVIC_ISER_SETENA_2                  ((uint32_t)0x00000004)        /*!< bit 2 */
+#define  NVIC_ISER_SETENA_3                  ((uint32_t)0x00000008)        /*!< bit 3 */
+#define  NVIC_ISER_SETENA_4                  ((uint32_t)0x00000010)        /*!< bit 4 */
+#define  NVIC_ISER_SETENA_5                  ((uint32_t)0x00000020)        /*!< bit 5 */
+#define  NVIC_ISER_SETENA_6                  ((uint32_t)0x00000040)        /*!< bit 6 */
+#define  NVIC_ISER_SETENA_7                  ((uint32_t)0x00000080)        /*!< bit 7 */
+#define  NVIC_ISER_SETENA_8                  ((uint32_t)0x00000100)        /*!< bit 8 */
+#define  NVIC_ISER_SETENA_9                  ((uint32_t)0x00000200)        /*!< bit 9 */
+#define  NVIC_ISER_SETENA_10                 ((uint32_t)0x00000400)        /*!< bit 10 */
+#define  NVIC_ISER_SETENA_11                 ((uint32_t)0x00000800)        /*!< bit 11 */
+#define  NVIC_ISER_SETENA_12                 ((uint32_t)0x00001000)        /*!< bit 12 */
+#define  NVIC_ISER_SETENA_13                 ((uint32_t)0x00002000)        /*!< bit 13 */
+#define  NVIC_ISER_SETENA_14                 ((uint32_t)0x00004000)        /*!< bit 14 */
+#define  NVIC_ISER_SETENA_15                 ((uint32_t)0x00008000)        /*!< bit 15 */
+#define  NVIC_ISER_SETENA_16                 ((uint32_t)0x00010000)        /*!< bit 16 */
+#define  NVIC_ISER_SETENA_17                 ((uint32_t)0x00020000)        /*!< bit 17 */
+#define  NVIC_ISER_SETENA_18                 ((uint32_t)0x00040000)        /*!< bit 18 */
+#define  NVIC_ISER_SETENA_19                 ((uint32_t)0x00080000)        /*!< bit 19 */
+#define  NVIC_ISER_SETENA_20                 ((uint32_t)0x00100000)        /*!< bit 20 */
+#define  NVIC_ISER_SETENA_21                 ((uint32_t)0x00200000)        /*!< bit 21 */
+#define  NVIC_ISER_SETENA_22                 ((uint32_t)0x00400000)        /*!< bit 22 */
+#define  NVIC_ISER_SETENA_23                 ((uint32_t)0x00800000)        /*!< bit 23 */
+#define  NVIC_ISER_SETENA_24                 ((uint32_t)0x01000000)        /*!< bit 24 */
+#define  NVIC_ISER_SETENA_25                 ((uint32_t)0x02000000)        /*!< bit 25 */
+#define  NVIC_ISER_SETENA_26                 ((uint32_t)0x04000000)        /*!< bit 26 */
+#define  NVIC_ISER_SETENA_27                 ((uint32_t)0x08000000)        /*!< bit 27 */
+#define  NVIC_ISER_SETENA_28                 ((uint32_t)0x10000000)        /*!< bit 28 */
+#define  NVIC_ISER_SETENA_29                 ((uint32_t)0x20000000)        /*!< bit 29 */
+#define  NVIC_ISER_SETENA_30                 ((uint32_t)0x40000000)        /*!< bit 30 */
+#define  NVIC_ISER_SETENA_31                 ((uint32_t)0x80000000)        /*!< bit 31 */
+
+/******************  Bit definition for NVIC_ICER register  *******************/
+#define  NVIC_ICER_CLRENA                   ((uint32_t)0xFFFFFFFF)        /*!< Interrupt clear-enable bits */
+#define  NVIC_ICER_CLRENA_0                  ((uint32_t)0x00000001)        /*!< bit 0 */
+#define  NVIC_ICER_CLRENA_1                  ((uint32_t)0x00000002)        /*!< bit 1 */
+#define  NVIC_ICER_CLRENA_2                  ((uint32_t)0x00000004)        /*!< bit 2 */
+#define  NVIC_ICER_CLRENA_3                  ((uint32_t)0x00000008)        /*!< bit 3 */
+#define  NVIC_ICER_CLRENA_4                  ((uint32_t)0x00000010)        /*!< bit 4 */
+#define  NVIC_ICER_CLRENA_5                  ((uint32_t)0x00000020)        /*!< bit 5 */
+#define  NVIC_ICER_CLRENA_6                  ((uint32_t)0x00000040)        /*!< bit 6 */
+#define  NVIC_ICER_CLRENA_7                  ((uint32_t)0x00000080)        /*!< bit 7 */
+#define  NVIC_ICER_CLRENA_8                  ((uint32_t)0x00000100)        /*!< bit 8 */
+#define  NVIC_ICER_CLRENA_9                  ((uint32_t)0x00000200)        /*!< bit 9 */
+#define  NVIC_ICER_CLRENA_10                 ((uint32_t)0x00000400)        /*!< bit 10 */
+#define  NVIC_ICER_CLRENA_11                 ((uint32_t)0x00000800)        /*!< bit 11 */
+#define  NVIC_ICER_CLRENA_12                 ((uint32_t)0x00001000)        /*!< bit 12 */
+#define  NVIC_ICER_CLRENA_13                 ((uint32_t)0x00002000)        /*!< bit 13 */
+#define  NVIC_ICER_CLRENA_14                 ((uint32_t)0x00004000)        /*!< bit 14 */
+#define  NVIC_ICER_CLRENA_15                 ((uint32_t)0x00008000)        /*!< bit 15 */
+#define  NVIC_ICER_CLRENA_16                 ((uint32_t)0x00010000)        /*!< bit 16 */
+#define  NVIC_ICER_CLRENA_17                 ((uint32_t)0x00020000)        /*!< bit 17 */
+#define  NVIC_ICER_CLRENA_18                 ((uint32_t)0x00040000)        /*!< bit 18 */
+#define  NVIC_ICER_CLRENA_19                 ((uint32_t)0x00080000)        /*!< bit 19 */
+#define  NVIC_ICER_CLRENA_20                 ((uint32_t)0x00100000)        /*!< bit 20 */
+#define  NVIC_ICER_CLRENA_21                 ((uint32_t)0x00200000)        /*!< bit 21 */
+#define  NVIC_ICER_CLRENA_22                 ((uint32_t)0x00400000)        /*!< bit 22 */
+#define  NVIC_ICER_CLRENA_23                 ((uint32_t)0x00800000)        /*!< bit 23 */
+#define  NVIC_ICER_CLRENA_24                 ((uint32_t)0x01000000)        /*!< bit 24 */
+#define  NVIC_ICER_CLRENA_25                 ((uint32_t)0x02000000)        /*!< bit 25 */
+#define  NVIC_ICER_CLRENA_26                 ((uint32_t)0x04000000)        /*!< bit 26 */
+#define  NVIC_ICER_CLRENA_27                 ((uint32_t)0x08000000)        /*!< bit 27 */
+#define  NVIC_ICER_CLRENA_28                 ((uint32_t)0x10000000)        /*!< bit 28 */
+#define  NVIC_ICER_CLRENA_29                 ((uint32_t)0x20000000)        /*!< bit 29 */
+#define  NVIC_ICER_CLRENA_30                 ((uint32_t)0x40000000)        /*!< bit 30 */
+#define  NVIC_ICER_CLRENA_31                 ((uint32_t)0x80000000)        /*!< bit 31 */
+
+/******************  Bit definition for NVIC_ISPR register  *******************/
+#define  NVIC_ISPR_SETPEND                   ((uint32_t)0xFFFFFFFF)        /*!< Interrupt set-pending bits */
+#define  NVIC_ISPR_SETPEND_0                 ((uint32_t)0x00000001)        /*!< bit 0 */
+#define  NVIC_ISPR_SETPEND_1                 ((uint32_t)0x00000002)        /*!< bit 1 */
+#define  NVIC_ISPR_SETPEND_2                 ((uint32_t)0x00000004)        /*!< bit 2 */
+#define  NVIC_ISPR_SETPEND_3                 ((uint32_t)0x00000008)        /*!< bit 3 */
+#define  NVIC_ISPR_SETPEND_4                 ((uint32_t)0x00000010)        /*!< bit 4 */
+#define  NVIC_ISPR_SETPEND_5                 ((uint32_t)0x00000020)        /*!< bit 5 */
+#define  NVIC_ISPR_SETPEND_6                 ((uint32_t)0x00000040)        /*!< bit 6 */
+#define  NVIC_ISPR_SETPEND_7                 ((uint32_t)0x00000080)        /*!< bit 7 */
+#define  NVIC_ISPR_SETPEND_8                 ((uint32_t)0x00000100)        /*!< bit 8 */
+#define  NVIC_ISPR_SETPEND_9                 ((uint32_t)0x00000200)        /*!< bit 9 */
+#define  NVIC_ISPR_SETPEND_10                ((uint32_t)0x00000400)        /*!< bit 10 */
+#define  NVIC_ISPR_SETPEND_11                ((uint32_t)0x00000800)        /*!< bit 11 */
+#define  NVIC_ISPR_SETPEND_12                ((uint32_t)0x00001000)        /*!< bit 12 */
+#define  NVIC_ISPR_SETPEND_13                ((uint32_t)0x00002000)        /*!< bit 13 */
+#define  NVIC_ISPR_SETPEND_14                ((uint32_t)0x00004000)        /*!< bit 14 */
+#define  NVIC_ISPR_SETPEND_15                ((uint32_t)0x00008000)        /*!< bit 15 */
+#define  NVIC_ISPR_SETPEND_16                ((uint32_t)0x00010000)        /*!< bit 16 */
+#define  NVIC_ISPR_SETPEND_17                ((uint32_t)0x00020000)        /*!< bit 17 */
+#define  NVIC_ISPR_SETPEND_18                ((uint32_t)0x00040000)        /*!< bit 18 */
+#define  NVIC_ISPR_SETPEND_19                ((uint32_t)0x00080000)        /*!< bit 19 */
+#define  NVIC_ISPR_SETPEND_20                ((uint32_t)0x00100000)        /*!< bit 20 */
+#define  NVIC_ISPR_SETPEND_21                ((uint32_t)0x00200000)        /*!< bit 21 */
+#define  NVIC_ISPR_SETPEND_22                ((uint32_t)0x00400000)        /*!< bit 22 */
+#define  NVIC_ISPR_SETPEND_23                ((uint32_t)0x00800000)        /*!< bit 23 */
+#define  NVIC_ISPR_SETPEND_24                ((uint32_t)0x01000000)        /*!< bit 24 */
+#define  NVIC_ISPR_SETPEND_25                ((uint32_t)0x02000000)        /*!< bit 25 */
+#define  NVIC_ISPR_SETPEND_26                ((uint32_t)0x04000000)        /*!< bit 26 */
+#define  NVIC_ISPR_SETPEND_27                ((uint32_t)0x08000000)        /*!< bit 27 */
+#define  NVIC_ISPR_SETPEND_28                ((uint32_t)0x10000000)        /*!< bit 28 */
+#define  NVIC_ISPR_SETPEND_29                ((uint32_t)0x20000000)        /*!< bit 29 */
+#define  NVIC_ISPR_SETPEND_30                ((uint32_t)0x40000000)        /*!< bit 30 */
+#define  NVIC_ISPR_SETPEND_31                ((uint32_t)0x80000000)        /*!< bit 31 */
+
+/******************  Bit definition for NVIC_ICPR register  *******************/
+#define  NVIC_ICPR_CLRPEND                   ((uint32_t)0xFFFFFFFF)        /*!< Interrupt clear-pending bits */
+#define  NVIC_ICPR_CLRPEND_0                 ((uint32_t)0x00000001)        /*!< bit 0 */
+#define  NVIC_ICPR_CLRPEND_1                 ((uint32_t)0x00000002)        /*!< bit 1 */
+#define  NVIC_ICPR_CLRPEND_2                 ((uint32_t)0x00000004)        /*!< bit 2 */
+#define  NVIC_ICPR_CLRPEND_3                 ((uint32_t)0x00000008)        /*!< bit 3 */
+#define  NVIC_ICPR_CLRPEND_4                 ((uint32_t)0x00000010)        /*!< bit 4 */
+#define  NVIC_ICPR_CLRPEND_5                 ((uint32_t)0x00000020)        /*!< bit 5 */
+#define  NVIC_ICPR_CLRPEND_6                 ((uint32_t)0x00000040)        /*!< bit 6 */
+#define  NVIC_ICPR_CLRPEND_7                 ((uint32_t)0x00000080)        /*!< bit 7 */
+#define  NVIC_ICPR_CLRPEND_8                 ((uint32_t)0x00000100)        /*!< bit 8 */
+#define  NVIC_ICPR_CLRPEND_9                 ((uint32_t)0x00000200)        /*!< bit 9 */
+#define  NVIC_ICPR_CLRPEND_10                ((uint32_t)0x00000400)        /*!< bit 10 */
+#define  NVIC_ICPR_CLRPEND_11                ((uint32_t)0x00000800)        /*!< bit 11 */
+#define  NVIC_ICPR_CLRPEND_12                ((uint32_t)0x00001000)        /*!< bit 12 */
+#define  NVIC_ICPR_CLRPEND_13                ((uint32_t)0x00002000)        /*!< bit 13 */
+#define  NVIC_ICPR_CLRPEND_14                ((uint32_t)0x00004000)        /*!< bit 14 */
+#define  NVIC_ICPR_CLRPEND_15                ((uint32_t)0x00008000)        /*!< bit 15 */
+#define  NVIC_ICPR_CLRPEND_16                ((uint32_t)0x00010000)        /*!< bit 16 */
+#define  NVIC_ICPR_CLRPEND_17                ((uint32_t)0x00020000)        /*!< bit 17 */
+#define  NVIC_ICPR_CLRPEND_18                ((uint32_t)0x00040000)        /*!< bit 18 */
+#define  NVIC_ICPR_CLRPEND_19                ((uint32_t)0x00080000)        /*!< bit 19 */
+#define  NVIC_ICPR_CLRPEND_20                ((uint32_t)0x00100000)        /*!< bit 20 */
+#define  NVIC_ICPR_CLRPEND_21                ((uint32_t)0x00200000)        /*!< bit 21 */
+#define  NVIC_ICPR_CLRPEND_22                ((uint32_t)0x00400000)        /*!< bit 22 */
+#define  NVIC_ICPR_CLRPEND_23                ((uint32_t)0x00800000)        /*!< bit 23 */
+#define  NVIC_ICPR_CLRPEND_24                ((uint32_t)0x01000000)        /*!< bit 24 */
+#define  NVIC_ICPR_CLRPEND_25                ((uint32_t)0x02000000)        /*!< bit 25 */
+#define  NVIC_ICPR_CLRPEND_26                ((uint32_t)0x04000000)        /*!< bit 26 */
+#define  NVIC_ICPR_CLRPEND_27                ((uint32_t)0x08000000)        /*!< bit 27 */
+#define  NVIC_ICPR_CLRPEND_28                ((uint32_t)0x10000000)        /*!< bit 28 */
+#define  NVIC_ICPR_CLRPEND_29                ((uint32_t)0x20000000)        /*!< bit 29 */
+#define  NVIC_ICPR_CLRPEND_30                ((uint32_t)0x40000000)        /*!< bit 30 */
+#define  NVIC_ICPR_CLRPEND_31                ((uint32_t)0x80000000)        /*!< bit 31 */
+
+/******************  Bit definition for NVIC_IABR register  *******************/
+#define  NVIC_IABR_ACTIVE                    ((uint32_t)0xFFFFFFFF)        /*!< Interrupt active flags */
+#define  NVIC_IABR_ACTIVE_0                  ((uint32_t)0x00000001)        /*!< bit 0 */
+#define  NVIC_IABR_ACTIVE_1                  ((uint32_t)0x00000002)        /*!< bit 1 */
+#define  NVIC_IABR_ACTIVE_2                  ((uint32_t)0x00000004)        /*!< bit 2 */
+#define  NVIC_IABR_ACTIVE_3                  ((uint32_t)0x00000008)        /*!< bit 3 */
+#define  NVIC_IABR_ACTIVE_4                  ((uint32_t)0x00000010)        /*!< bit 4 */
+#define  NVIC_IABR_ACTIVE_5                  ((uint32_t)0x00000020)        /*!< bit 5 */
+#define  NVIC_IABR_ACTIVE_6                  ((uint32_t)0x00000040)        /*!< bit 6 */
+#define  NVIC_IABR_ACTIVE_7                  ((uint32_t)0x00000080)        /*!< bit 7 */
+#define  NVIC_IABR_ACTIVE_8                  ((uint32_t)0x00000100)        /*!< bit 8 */
+#define  NVIC_IABR_ACTIVE_9                  ((uint32_t)0x00000200)        /*!< bit 9 */
+#define  NVIC_IABR_ACTIVE_10                 ((uint32_t)0x00000400)        /*!< bit 10 */
+#define  NVIC_IABR_ACTIVE_11                 ((uint32_t)0x00000800)        /*!< bit 11 */
+#define  NVIC_IABR_ACTIVE_12                 ((uint32_t)0x00001000)        /*!< bit 12 */
+#define  NVIC_IABR_ACTIVE_13                 ((uint32_t)0x00002000)        /*!< bit 13 */
+#define  NVIC_IABR_ACTIVE_14                 ((uint32_t)0x00004000)        /*!< bit 14 */
+#define  NVIC_IABR_ACTIVE_15                 ((uint32_t)0x00008000)        /*!< bit 15 */
+#define  NVIC_IABR_ACTIVE_16                 ((uint32_t)0x00010000)        /*!< bit 16 */
+#define  NVIC_IABR_ACTIVE_17                 ((uint32_t)0x00020000)        /*!< bit 17 */
+#define  NVIC_IABR_ACTIVE_18                 ((uint32_t)0x00040000)        /*!< bit 18 */
+#define  NVIC_IABR_ACTIVE_19                 ((uint32_t)0x00080000)        /*!< bit 19 */
+#define  NVIC_IABR_ACTIVE_20                 ((uint32_t)0x00100000)        /*!< bit 20 */
+#define  NVIC_IABR_ACTIVE_21                 ((uint32_t)0x00200000)        /*!< bit 21 */
+#define  NVIC_IABR_ACTIVE_22                 ((uint32_t)0x00400000)        /*!< bit 22 */
+#define  NVIC_IABR_ACTIVE_23                 ((uint32_t)0x00800000)        /*!< bit 23 */
+#define  NVIC_IABR_ACTIVE_24                 ((uint32_t)0x01000000)        /*!< bit 24 */
+#define  NVIC_IABR_ACTIVE_25                 ((uint32_t)0x02000000)        /*!< bit 25 */
+#define  NVIC_IABR_ACTIVE_26                 ((uint32_t)0x04000000)        /*!< bit 26 */
+#define  NVIC_IABR_ACTIVE_27                 ((uint32_t)0x08000000)        /*!< bit 27 */
+#define  NVIC_IABR_ACTIVE_28                 ((uint32_t)0x10000000)        /*!< bit 28 */
+#define  NVIC_IABR_ACTIVE_29                 ((uint32_t)0x20000000)        /*!< bit 29 */
+#define  NVIC_IABR_ACTIVE_30                 ((uint32_t)0x40000000)        /*!< bit 30 */
+#define  NVIC_IABR_ACTIVE_31                 ((uint32_t)0x80000000)        /*!< bit 31 */
+
+/******************  Bit definition for NVIC_PRI0 register  *******************/
+#define  NVIC_IPR0_PRI_0                     ((uint32_t)0x000000FF)        /*!< Priority of interrupt 0 */
+#define  NVIC_IPR0_PRI_1                     ((uint32_t)0x0000FF00)        /*!< Priority of interrupt 1 */
+#define  NVIC_IPR0_PRI_2                     ((uint32_t)0x00FF0000)        /*!< Priority of interrupt 2 */
+#define  NVIC_IPR0_PRI_3                     ((uint32_t)0xFF000000)        /*!< Priority of interrupt 3 */
+
+/******************  Bit definition for NVIC_PRI1 register  *******************/
+#define  NVIC_IPR1_PRI_4                     ((uint32_t)0x000000FF)        /*!< Priority of interrupt 4 */
+#define  NVIC_IPR1_PRI_5                     ((uint32_t)0x0000FF00)        /*!< Priority of interrupt 5 */
+#define  NVIC_IPR1_PRI_6                     ((uint32_t)0x00FF0000)        /*!< Priority of interrupt 6 */
+#define  NVIC_IPR1_PRI_7                     ((uint32_t)0xFF000000)        /*!< Priority of interrupt 7 */
+
+/******************  Bit definition for NVIC_PRI2 register  *******************/
+#define  NVIC_IPR2_PRI_8                     ((uint32_t)0x000000FF)        /*!< Priority of interrupt 8 */
+#define  NVIC_IPR2_PRI_9                     ((uint32_t)0x0000FF00)        /*!< Priority of interrupt 9 */
+#define  NVIC_IPR2_PRI_10                    ((uint32_t)0x00FF0000)        /*!< Priority of interrupt 10 */
+#define  NVIC_IPR2_PRI_11                    ((uint32_t)0xFF000000)        /*!< Priority of interrupt 11 */
+
+/******************  Bit definition for NVIC_PRI3 register  *******************/
+#define  NVIC_IPR3_PRI_12                    ((uint32_t)0x000000FF)        /*!< Priority of interrupt 12 */
+#define  NVIC_IPR3_PRI_13                    ((uint32_t)0x0000FF00)        /*!< Priority of interrupt 13 */
+#define  NVIC_IPR3_PRI_14                    ((uint32_t)0x00FF0000)        /*!< Priority of interrupt 14 */
+#define  NVIC_IPR3_PRI_15                    ((uint32_t)0xFF000000)        /*!< Priority of interrupt 15 */
+
+/******************  Bit definition for NVIC_PRI4 register  *******************/
+#define  NVIC_IPR4_PRI_16                    ((uint32_t)0x000000FF)        /*!< Priority of interrupt 16 */
+#define  NVIC_IPR4_PRI_17                    ((uint32_t)0x0000FF00)        /*!< Priority of interrupt 17 */
+#define  NVIC_IPR4_PRI_18                    ((uint32_t)0x00FF0000)        /*!< Priority of interrupt 18 */
+#define  NVIC_IPR4_PRI_19                    ((uint32_t)0xFF000000)        /*!< Priority of interrupt 19 */
+
+/******************  Bit definition for NVIC_PRI5 register  *******************/
+#define  NVIC_IPR5_PRI_20                    ((uint32_t)0x000000FF)        /*!< Priority of interrupt 20 */
+#define  NVIC_IPR5_PRI_21                    ((uint32_t)0x0000FF00)        /*!< Priority of interrupt 21 */
+#define  NVIC_IPR5_PRI_22                    ((uint32_t)0x00FF0000)        /*!< Priority of interrupt 22 */
+#define  NVIC_IPR5_PRI_23                    ((uint32_t)0xFF000000)        /*!< Priority of interrupt 23 */
+
+/******************  Bit definition for NVIC_PRI6 register  *******************/
+#define  NVIC_IPR6_PRI_24                    ((uint32_t)0x000000FF)        /*!< Priority of interrupt 24 */
+#define  NVIC_IPR6_PRI_25                    ((uint32_t)0x0000FF00)        /*!< Priority of interrupt 25 */
+#define  NVIC_IPR6_PRI_26                    ((uint32_t)0x00FF0000)        /*!< Priority of interrupt 26 */
+#define  NVIC_IPR6_PRI_27                    ((uint32_t)0xFF000000)        /*!< Priority of interrupt 27 */
+
+/******************  Bit definition for NVIC_PRI7 register  *******************/
+#define  NVIC_IPR7_PRI_28                    ((uint32_t)0x000000FF)        /*!< Priority of interrupt 28 */
+#define  NVIC_IPR7_PRI_29                    ((uint32_t)0x0000FF00)        /*!< Priority of interrupt 29 */
+#define  NVIC_IPR7_PRI_30                    ((uint32_t)0x00FF0000)        /*!< Priority of interrupt 30 */
+#define  NVIC_IPR7_PRI_31                    ((uint32_t)0xFF000000)        /*!< Priority of interrupt 31 */
+
+/******************  Bit definition for SCB_CPUID register  *******************/
+#define  SCB_CPUID_REVISION                  ((uint32_t)0x0000000F)        /*!< Implementation defined revision number */
+#define  SCB_CPUID_PARTNO                    ((uint32_t)0x0000FFF0)        /*!< Number of processor within family */
+#define  SCB_CPUID_Constant                  ((uint32_t)0x000F0000)        /*!< Reads as 0x0F */
+#define  SCB_CPUID_VARIANT                   ((uint32_t)0x00F00000)        /*!< Implementation defined variant number */
+#define  SCB_CPUID_IMPLEMENTER               ((uint32_t)0xFF000000)        /*!< Implementer code. ARM is 0x41 */
+
+/*******************  Bit definition for SCB_ICSR register  *******************/
+#define  SCB_ICSR_VECTACTIVE                 ((uint32_t)0x000001FF)        /*!< Active ISR number field */
+#define  SCB_ICSR_RETTOBASE                  ((uint32_t)0x00000800)        /*!< All active exceptions minus the IPSR_current_exception yields the empty set */
+#define  SCB_ICSR_VECTPENDING                ((uint32_t)0x003FF000)        /*!< Pending ISR number field */
+#define  SCB_ICSR_ISRPENDING                 ((uint32_t)0x00400000)        /*!< Interrupt pending flag */
+#define  SCB_ICSR_ISRPREEMPT                 ((uint32_t)0x00800000)        /*!< It indicates that a pending interrupt becomes active in the next running cycle */
+#define  SCB_ICSR_PENDSTCLR                  ((uint32_t)0x02000000)        /*!< Clear pending SysTick bit */
+#define  SCB_ICSR_PENDSTSET                  ((uint32_t)0x04000000)        /*!< Set pending SysTick bit */
+#define  SCB_ICSR_PENDSVCLR                  ((uint32_t)0x08000000)        /*!< Clear pending pendSV bit */
+#define  SCB_ICSR_PENDSVSET                  ((uint32_t)0x10000000)        /*!< Set pending pendSV bit */
+#define  SCB_ICSR_NMIPENDSET                 ((uint32_t)0x80000000)        /*!< Set pending NMI bit */
+
+/*******************  Bit definition for SCB_VTOR register  *******************/
+#define  SCB_VTOR_TBLOFF                     ((uint32_t)0x1FFFFF80)        /*!< Vector table base offset field */
+#define  SCB_VTOR_TBLBASE                    ((uint32_t)0x20000000)        /*!< Table base in code(0) or RAM(1) */
+
+/*!<*****************  Bit definition for SCB_AIRCR register  *******************/
+#define  SCB_AIRCR_VECTRESET                 ((uint32_t)0x00000001)        /*!< System Reset bit */
+#define  SCB_AIRCR_VECTCLRACTIVE             ((uint32_t)0x00000002)        /*!< Clear active vector bit */
+#define  SCB_AIRCR_SYSRESETREQ               ((uint32_t)0x00000004)        /*!< Requests chip control logic to generate a reset */
+
+#define  SCB_AIRCR_PRIGROUP                  ((uint32_t)0x00000700)        /*!< PRIGROUP[2:0] bits (Priority group) */
+#define  SCB_AIRCR_PRIGROUP_0                ((uint32_t)0x00000100)        /*!< Bit 0 */
+#define  SCB_AIRCR_PRIGROUP_1                ((uint32_t)0x00000200)        /*!< Bit 1 */
+#define  SCB_AIRCR_PRIGROUP_2                ((uint32_t)0x00000400)        /*!< Bit 2  */
+
+/* prority group configuration */
+#define  SCB_AIRCR_PRIGROUP0                 ((uint32_t)0x00000000)        /*!< Priority group=0 (7 bits of pre-emption priority, 1 bit of subpriority) */
+#define  SCB_AIRCR_PRIGROUP1                 ((uint32_t)0x00000100)        /*!< Priority group=1 (6 bits of pre-emption priority, 2 bits of subpriority) */
+#define  SCB_AIRCR_PRIGROUP2                 ((uint32_t)0x00000200)        /*!< Priority group=2 (5 bits of pre-emption priority, 3 bits of subpriority) */
+#define  SCB_AIRCR_PRIGROUP3                 ((uint32_t)0x00000300)        /*!< Priority group=3 (4 bits of pre-emption priority, 4 bits of subpriority) */
+#define  SCB_AIRCR_PRIGROUP4                 ((uint32_t)0x00000400)        /*!< Priority group=4 (3 bits of pre-emption priority, 5 bits of subpriority) */
+#define  SCB_AIRCR_PRIGROUP5                 ((uint32_t)0x00000500)        /*!< Priority group=5 (2 bits of pre-emption priority, 6 bits of subpriority) */
+#define  SCB_AIRCR_PRIGROUP6                 ((uint32_t)0x00000600)        /*!< Priority group=6 (1 bit of pre-emption priority, 7 bits of subpriority) */
+#define  SCB_AIRCR_PRIGROUP7                 ((uint32_t)0x00000700)        /*!< Priority group=7 (no pre-emption priority, 8 bits of subpriority) */
+
+#define  SCB_AIRCR_ENDIANESS                 ((uint32_t)0x00008000)        /*!< Data endianness bit */
+#define  SCB_AIRCR_VECTKEY                   ((uint32_t)0xFFFF0000)        /*!< Register key (VECTKEY) - Reads as 0xFA05 (VECTKEYSTAT) */
+
+/*******************  Bit definition for SCB_SCR register  ********************/
+#define  SCB_SCR_SLEEPONEXIT                 ((uint8_t)0x02)               /*!< Sleep on exit bit */
+#define  SCB_SCR_SLEEPDEEP                   ((uint8_t)0x04)               /*!< Sleep deep bit */
+#define  SCB_SCR_SEVONPEND                   ((uint8_t)0x10)               /*!< Wake up from WFE */
+
+/********************  Bit definition for SCB_CCR register  *******************/
+#define  SCB_CCR_NONBASETHRDENA              ((uint16_t)0x0001)            /*!< Thread mode can be entered from any level in Handler mode by controlled return value */
+#define  SCB_CCR_USERSETMPEND                ((uint16_t)0x0002)            /*!< Enables user code to write the Software Trigger Interrupt register to trigger (pend) a Main exception */
+#define  SCB_CCR_UNALIGN_TRP                 ((uint16_t)0x0008)            /*!< Trap for unaligned access */
+#define  SCB_CCR_DIV_0_TRP                   ((uint16_t)0x0010)            /*!< Trap on Divide by 0 */
+#define  SCB_CCR_BFHFNMIGN                   ((uint16_t)0x0100)            /*!< Handlers running at priority -1 and -2 */
+#define  SCB_CCR_STKALIGN                    ((uint16_t)0x0200)            /*!< On exception entry, the SP used prior to the exception is adjusted to be 8-byte aligned */
+
+/*******************  Bit definition for SCB_SHPR register ********************/
+#define  SCB_SHPR_PRI_N                      ((uint32_t)0x000000FF)        /*!< Priority of system handler 4,8, and 12. Mem Manage, reserved and Debug Monitor */
+#define  SCB_SHPR_PRI_N1                     ((uint32_t)0x0000FF00)        /*!< Priority of system handler 5,9, and 13. Bus Fault, reserved and reserved */
+#define  SCB_SHPR_PRI_N2                     ((uint32_t)0x00FF0000)        /*!< Priority of system handler 6,10, and 14. Usage Fault, reserved and PendSV */
+#define  SCB_SHPR_PRI_N3                     ((uint32_t)0xFF000000)        /*!< Priority of system handler 7,11, and 15. Reserved, SVCall and SysTick */
+
+/******************  Bit definition for SCB_SHCSR register  *******************/
+#define  SCB_SHCSR_MEMFAULTACT               ((uint32_t)0x00000001)        /*!< MemManage is active */
+#define  SCB_SHCSR_BUSFAULTACT               ((uint32_t)0x00000002)        /*!< BusFault is active */
+#define  SCB_SHCSR_USGFAULTACT               ((uint32_t)0x00000008)        /*!< UsageFault is active */
+#define  SCB_SHCSR_SVCALLACT                 ((uint32_t)0x00000080)        /*!< SVCall is active */
+#define  SCB_SHCSR_MONITORACT                ((uint32_t)0x00000100)        /*!< Monitor is active */
+#define  SCB_SHCSR_PENDSVACT                 ((uint32_t)0x00000400)        /*!< PendSV is active */
+#define  SCB_SHCSR_SYSTICKACT                ((uint32_t)0x00000800)        /*!< SysTick is active */
+#define  SCB_SHCSR_USGFAULTPENDED            ((uint32_t)0x00001000)        /*!< Usage Fault is pended */
+#define  SCB_SHCSR_MEMFAULTPENDED            ((uint32_t)0x00002000)        /*!< MemManage is pended */
+#define  SCB_SHCSR_BUSFAULTPENDED            ((uint32_t)0x00004000)        /*!< Bus Fault is pended */
+#define  SCB_SHCSR_SVCALLPENDED              ((uint32_t)0x00008000)        /*!< SVCall is pended */
+#define  SCB_SHCSR_MEMFAULTENA               ((uint32_t)0x00010000)        /*!< MemManage enable */
+#define  SCB_SHCSR_BUSFAULTENA               ((uint32_t)0x00020000)        /*!< Bus Fault enable */
+#define  SCB_SHCSR_USGFAULTENA               ((uint32_t)0x00040000)        /*!< UsageFault enable */
+
+/*******************  Bit definition for SCB_CFSR register  *******************/
+/*!< MFSR */
+#define  SCB_CFSR_IACCVIOL                   ((uint32_t)0x00000001)        /*!< Instruction access violation */
+#define  SCB_CFSR_DACCVIOL                   ((uint32_t)0x00000002)        /*!< Data access violation */
+#define  SCB_CFSR_MUNSTKERR                  ((uint32_t)0x00000008)        /*!< Unstacking error */
+#define  SCB_CFSR_MSTKERR                    ((uint32_t)0x00000010)        /*!< Stacking error */
+#define  SCB_CFSR_MMARVALID                  ((uint32_t)0x00000080)        /*!< Memory Manage Address Register address valid flag */
+/*!< BFSR */
+#define  SCB_CFSR_IBUSERR                    ((uint32_t)0x00000100)        /*!< Instruction bus error flag */
+#define  SCB_CFSR_PRECISERR                  ((uint32_t)0x00000200)        /*!< Precise data bus error */
+#define  SCB_CFSR_IMPRECISERR                ((uint32_t)0x00000400)        /*!< Imprecise data bus error */
+#define  SCB_CFSR_UNSTKERR                   ((uint32_t)0x00000800)        /*!< Unstacking error */
+#define  SCB_CFSR_STKERR                     ((uint32_t)0x00001000)        /*!< Stacking error */
+#define  SCB_CFSR_BFARVALID                  ((uint32_t)0x00008000)        /*!< Bus Fault Address Register address valid flag */
+/*!< UFSR */
+#define  SCB_CFSR_UNDEFINSTR                 ((uint32_t)0x00010000)        /*!< The processor attempt to execute an undefined instruction */
+#define  SCB_CFSR_INVSTATE                   ((uint32_t)0x00020000)        /*!< Invalid combination of EPSR and instruction */
+#define  SCB_CFSR_INVPC                      ((uint32_t)0x00040000)        /*!< Attempt to load EXC_RETURN into pc illegally */
+#define  SCB_CFSR_NOCP                       ((uint32_t)0x00080000)        /*!< Attempt to use a coprocessor instruction */
+#define  SCB_CFSR_UNALIGNED                  ((uint32_t)0x01000000)        /*!< Fault occurs when there is an attempt to make an unaligned memory access */
+#define  SCB_CFSR_DIVBYZERO                  ((uint32_t)0x02000000)        /*!< Fault occurs when SDIV or DIV instruction is used with a divisor of 0 */
+
+/*******************  Bit definition for SCB_HFSR register  *******************/
+#define  SCB_HFSR_VECTTBL                    ((uint32_t)0x00000002)        /*!< Fault occurs because of vector table read on exception processing */
+#define  SCB_HFSR_FORCED                     ((uint32_t)0x40000000)        /*!< Hard Fault activated when a configurable Fault was received and cannot activate */
+#define  SCB_HFSR_DEBUGEVT                   ((uint32_t)0x80000000)        /*!< Fault related to debug */
+
+/*******************  Bit definition for SCB_DFSR register  *******************/
+#define  SCB_DFSR_HALTED                     ((uint8_t)0x01)               /*!< Halt request flag */
+#define  SCB_DFSR_BKPT                       ((uint8_t)0x02)               /*!< BKPT flag */
+#define  SCB_DFSR_DWTTRAP                    ((uint8_t)0x04)               /*!< Data Watchpoint and Trace (DWT) flag */
+#define  SCB_DFSR_VCATCH                     ((uint8_t)0x08)               /*!< Vector catch flag */
+#define  SCB_DFSR_EXTERNAL                   ((uint8_t)0x10)               /*!< External debug request flag */
+
+/*******************  Bit definition for SCB_MMFAR register  ******************/
+#define  SCB_MMFAR_ADDRESS                   ((uint32_t)0xFFFFFFFF)        /*!< Mem Manage fault address field */
+
+/*******************  Bit definition for SCB_BFAR register  *******************/
+#define  SCB_BFAR_ADDRESS                    ((uint32_t)0xFFFFFFFF)        /*!< Bus fault address field */
+
+/*******************  Bit definition for SCB_afsr register  *******************/
+#define  SCB_AFSR_IMPDEF                     ((uint32_t)0xFFFFFFFF)        /*!< Implementation defined */
+
+/******************************************************************************/
+/*                                                                            */
+/*                    External Interrupt/Event Controller                     */
+/*                                                                            */
+/******************************************************************************/
+
+/*******************  Bit definition for EXTI_IMR register  *******************/
+#define  EXTI_IMR_MR0                        ((uint32_t)0x00000001)        /*!< Interrupt Mask on line 0 */
+#define  EXTI_IMR_MR1                        ((uint32_t)0x00000002)        /*!< Interrupt Mask on line 1 */
+#define  EXTI_IMR_MR2                        ((uint32_t)0x00000004)        /*!< Interrupt Mask on line 2 */
+#define  EXTI_IMR_MR3                        ((uint32_t)0x00000008)        /*!< Interrupt Mask on line 3 */
+#define  EXTI_IMR_MR4                        ((uint32_t)0x00000010)        /*!< Interrupt Mask on line 4 */
+#define  EXTI_IMR_MR5                        ((uint32_t)0x00000020)        /*!< Interrupt Mask on line 5 */
+#define  EXTI_IMR_MR6                        ((uint32_t)0x00000040)        /*!< Interrupt Mask on line 6 */
+#define  EXTI_IMR_MR7                        ((uint32_t)0x00000080)        /*!< Interrupt Mask on line 7 */
+#define  EXTI_IMR_MR8                        ((uint32_t)0x00000100)        /*!< Interrupt Mask on line 8 */
+#define  EXTI_IMR_MR9                        ((uint32_t)0x00000200)        /*!< Interrupt Mask on line 9 */
+#define  EXTI_IMR_MR10                       ((uint32_t)0x00000400)        /*!< Interrupt Mask on line 10 */
+#define  EXTI_IMR_MR11                       ((uint32_t)0x00000800)        /*!< Interrupt Mask on line 11 */
+#define  EXTI_IMR_MR12                       ((uint32_t)0x00001000)        /*!< Interrupt Mask on line 12 */
+#define  EXTI_IMR_MR13                       ((uint32_t)0x00002000)        /*!< Interrupt Mask on line 13 */
+#define  EXTI_IMR_MR14                       ((uint32_t)0x00004000)        /*!< Interrupt Mask on line 14 */
+#define  EXTI_IMR_MR15                       ((uint32_t)0x00008000)        /*!< Interrupt Mask on line 15 */
+#define  EXTI_IMR_MR16                       ((uint32_t)0x00010000)        /*!< Interrupt Mask on line 16 */
+#define  EXTI_IMR_MR17                       ((uint32_t)0x00020000)        /*!< Interrupt Mask on line 17 */
+#define  EXTI_IMR_MR18                       ((uint32_t)0x00040000)        /*!< Interrupt Mask on line 18 */
+#define  EXTI_IMR_MR19                       ((uint32_t)0x00080000)        /*!< Interrupt Mask on line 19 */
+
+/*******************  Bit definition for EXTI_EMR register  *******************/
+#define  EXTI_EMR_MR0                        ((uint32_t)0x00000001)        /*!< Event Mask on line 0 */
+#define  EXTI_EMR_MR1                        ((uint32_t)0x00000002)        /*!< Event Mask on line 1 */
+#define  EXTI_EMR_MR2                        ((uint32_t)0x00000004)        /*!< Event Mask on line 2 */
+#define  EXTI_EMR_MR3                        ((uint32_t)0x00000008)        /*!< Event Mask on line 3 */
+#define  EXTI_EMR_MR4                        ((uint32_t)0x00000010)        /*!< Event Mask on line 4 */
+#define  EXTI_EMR_MR5                        ((uint32_t)0x00000020)        /*!< Event Mask on line 5 */
+#define  EXTI_EMR_MR6                        ((uint32_t)0x00000040)        /*!< Event Mask on line 6 */
+#define  EXTI_EMR_MR7                        ((uint32_t)0x00000080)        /*!< Event Mask on line 7 */
+#define  EXTI_EMR_MR8                        ((uint32_t)0x00000100)        /*!< Event Mask on line 8 */
+#define  EXTI_EMR_MR9                        ((uint32_t)0x00000200)        /*!< Event Mask on line 9 */
+#define  EXTI_EMR_MR10                       ((uint32_t)0x00000400)        /*!< Event Mask on line 10 */
+#define  EXTI_EMR_MR11                       ((uint32_t)0x00000800)        /*!< Event Mask on line 11 */
+#define  EXTI_EMR_MR12                       ((uint32_t)0x00001000)        /*!< Event Mask on line 12 */
+#define  EXTI_EMR_MR13                       ((uint32_t)0x00002000)        /*!< Event Mask on line 13 */
+#define  EXTI_EMR_MR14                       ((uint32_t)0x00004000)        /*!< Event Mask on line 14 */
+#define  EXTI_EMR_MR15                       ((uint32_t)0x00008000)        /*!< Event Mask on line 15 */
+#define  EXTI_EMR_MR16                       ((uint32_t)0x00010000)        /*!< Event Mask on line 16 */
+#define  EXTI_EMR_MR17                       ((uint32_t)0x00020000)        /*!< Event Mask on line 17 */
+#define  EXTI_EMR_MR18                       ((uint32_t)0x00040000)        /*!< Event Mask on line 18 */
+#define  EXTI_EMR_MR19                       ((uint32_t)0x00080000)        /*!< Event Mask on line 19 */
+
+/******************  Bit definition for EXTI_RTSR register  *******************/
+#define  EXTI_RTSR_TR0                       ((uint32_t)0x00000001)        /*!< Rising trigger event configuration bit of line 0 */
+#define  EXTI_RTSR_TR1                       ((uint32_t)0x00000002)        /*!< Rising trigger event configuration bit of line 1 */
+#define  EXTI_RTSR_TR2                       ((uint32_t)0x00000004)        /*!< Rising trigger event configuration bit of line 2 */
+#define  EXTI_RTSR_TR3                       ((uint32_t)0x00000008)        /*!< Rising trigger event configuration bit of line 3 */
+#define  EXTI_RTSR_TR4                       ((uint32_t)0x00000010)        /*!< Rising trigger event configuration bit of line 4 */
+#define  EXTI_RTSR_TR5                       ((uint32_t)0x00000020)        /*!< Rising trigger event configuration bit of line 5 */
+#define  EXTI_RTSR_TR6                       ((uint32_t)0x00000040)        /*!< Rising trigger event configuration bit of line 6 */
+#define  EXTI_RTSR_TR7                       ((uint32_t)0x00000080)        /*!< Rising trigger event configuration bit of line 7 */
+#define  EXTI_RTSR_TR8                       ((uint32_t)0x00000100)        /*!< Rising trigger event configuration bit of line 8 */
+#define  EXTI_RTSR_TR9                       ((uint32_t)0x00000200)        /*!< Rising trigger event configuration bit of line 9 */
+#define  EXTI_RTSR_TR10                      ((uint32_t)0x00000400)        /*!< Rising trigger event configuration bit of line 10 */
+#define  EXTI_RTSR_TR11                      ((uint32_t)0x00000800)        /*!< Rising trigger event configuration bit of line 11 */
+#define  EXTI_RTSR_TR12                      ((uint32_t)0x00001000)        /*!< Rising trigger event configuration bit of line 12 */
+#define  EXTI_RTSR_TR13                      ((uint32_t)0x00002000)        /*!< Rising trigger event configuration bit of line 13 */
+#define  EXTI_RTSR_TR14                      ((uint32_t)0x00004000)        /*!< Rising trigger event configuration bit of line 14 */
+#define  EXTI_RTSR_TR15                      ((uint32_t)0x00008000)        /*!< Rising trigger event configuration bit of line 15 */
+#define  EXTI_RTSR_TR16                      ((uint32_t)0x00010000)        /*!< Rising trigger event configuration bit of line 16 */
+#define  EXTI_RTSR_TR17                      ((uint32_t)0x00020000)        /*!< Rising trigger event configuration bit of line 17 */
+#define  EXTI_RTSR_TR18                      ((uint32_t)0x00040000)        /*!< Rising trigger event configuration bit of line 18 */
+#define  EXTI_RTSR_TR19                      ((uint32_t)0x00080000)        /*!< Rising trigger event configuration bit of line 19 */
+
+/******************  Bit definition for EXTI_FTSR register  *******************/
+#define  EXTI_FTSR_TR0                       ((uint32_t)0x00000001)        /*!< Falling trigger event configuration bit of line 0 */
+#define  EXTI_FTSR_TR1                       ((uint32_t)0x00000002)        /*!< Falling trigger event configuration bit of line 1 */
+#define  EXTI_FTSR_TR2                       ((uint32_t)0x00000004)        /*!< Falling trigger event configuration bit of line 2 */
+#define  EXTI_FTSR_TR3                       ((uint32_t)0x00000008)        /*!< Falling trigger event configuration bit of line 3 */
+#define  EXTI_FTSR_TR4                       ((uint32_t)0x00000010)        /*!< Falling trigger event configuration bit of line 4 */
+#define  EXTI_FTSR_TR5                       ((uint32_t)0x00000020)        /*!< Falling trigger event configuration bit of line 5 */
+#define  EXTI_FTSR_TR6                       ((uint32_t)0x00000040)        /*!< Falling trigger event configuration bit of line 6 */
+#define  EXTI_FTSR_TR7                       ((uint32_t)0x00000080)        /*!< Falling trigger event configuration bit of line 7 */
+#define  EXTI_FTSR_TR8                       ((uint32_t)0x00000100)        /*!< Falling trigger event configuration bit of line 8 */
+#define  EXTI_FTSR_TR9                       ((uint32_t)0x00000200)        /*!< Falling trigger event configuration bit of line 9 */
+#define  EXTI_FTSR_TR10                      ((uint32_t)0x00000400)        /*!< Falling trigger event configuration bit of line 10 */
+#define  EXTI_FTSR_TR11                      ((uint32_t)0x00000800)        /*!< Falling trigger event configuration bit of line 11 */
+#define  EXTI_FTSR_TR12                      ((uint32_t)0x00001000)        /*!< Falling trigger event configuration bit of line 12 */
+#define  EXTI_FTSR_TR13                      ((uint32_t)0x00002000)        /*!< Falling trigger event configuration bit of line 13 */
+#define  EXTI_FTSR_TR14                      ((uint32_t)0x00004000)        /*!< Falling trigger event configuration bit of line 14 */
+#define  EXTI_FTSR_TR15                      ((uint32_t)0x00008000)        /*!< Falling trigger event configuration bit of line 15 */
+#define  EXTI_FTSR_TR16                      ((uint32_t)0x00010000)        /*!< Falling trigger event configuration bit of line 16 */
+#define  EXTI_FTSR_TR17                      ((uint32_t)0x00020000)        /*!< Falling trigger event configuration bit of line 17 */
+#define  EXTI_FTSR_TR18                      ((uint32_t)0x00040000)        /*!< Falling trigger event configuration bit of line 18 */
+#define  EXTI_FTSR_TR19                      ((uint32_t)0x00080000)        /*!< Falling trigger event configuration bit of line 19 */
+
+/******************  Bit definition for EXTI_SWIER register  ******************/
+#define  EXTI_SWIER_SWIER0                   ((uint32_t)0x00000001)        /*!< Software Interrupt on line 0 */
+#define  EXTI_SWIER_SWIER1                   ((uint32_t)0x00000002)        /*!< Software Interrupt on line 1 */
+#define  EXTI_SWIER_SWIER2                   ((uint32_t)0x00000004)        /*!< Software Interrupt on line 2 */
+#define  EXTI_SWIER_SWIER3                   ((uint32_t)0x00000008)        /*!< Software Interrupt on line 3 */
+#define  EXTI_SWIER_SWIER4                   ((uint32_t)0x00000010)        /*!< Software Interrupt on line 4 */
+#define  EXTI_SWIER_SWIER5                   ((uint32_t)0x00000020)        /*!< Software Interrupt on line 5 */
+#define  EXTI_SWIER_SWIER6                   ((uint32_t)0x00000040)        /*!< Software Interrupt on line 6 */
+#define  EXTI_SWIER_SWIER7                   ((uint32_t)0x00000080)        /*!< Software Interrupt on line 7 */
+#define  EXTI_SWIER_SWIER8                   ((uint32_t)0x00000100)        /*!< Software Interrupt on line 8 */
+#define  EXTI_SWIER_SWIER9                   ((uint32_t)0x00000200)        /*!< Software Interrupt on line 9 */
+#define  EXTI_SWIER_SWIER10                  ((uint32_t)0x00000400)        /*!< Software Interrupt on line 10 */
+#define  EXTI_SWIER_SWIER11                  ((uint32_t)0x00000800)        /*!< Software Interrupt on line 11 */
+#define  EXTI_SWIER_SWIER12                  ((uint32_t)0x00001000)        /*!< Software Interrupt on line 12 */
+#define  EXTI_SWIER_SWIER13                  ((uint32_t)0x00002000)        /*!< Software Interrupt on line 13 */
+#define  EXTI_SWIER_SWIER14                  ((uint32_t)0x00004000)        /*!< Software Interrupt on line 14 */
+#define  EXTI_SWIER_SWIER15                  ((uint32_t)0x00008000)        /*!< Software Interrupt on line 15 */
+#define  EXTI_SWIER_SWIER16                  ((uint32_t)0x00010000)        /*!< Software Interrupt on line 16 */
+#define  EXTI_SWIER_SWIER17                  ((uint32_t)0x00020000)        /*!< Software Interrupt on line 17 */
+#define  EXTI_SWIER_SWIER18                  ((uint32_t)0x00040000)        /*!< Software Interrupt on line 18 */
+#define  EXTI_SWIER_SWIER19                  ((uint32_t)0x00080000)        /*!< Software Interrupt on line 19 */
+
+/*******************  Bit definition for EXTI_PR register  ********************/
+#define  EXTI_PR_PR0                         ((uint32_t)0x00000001)        /*!< Pending bit for line 0 */
+#define  EXTI_PR_PR1                         ((uint32_t)0x00000002)        /*!< Pending bit for line 1 */
+#define  EXTI_PR_PR2                         ((uint32_t)0x00000004)        /*!< Pending bit for line 2 */
+#define  EXTI_PR_PR3                         ((uint32_t)0x00000008)        /*!< Pending bit for line 3 */
+#define  EXTI_PR_PR4                         ((uint32_t)0x00000010)        /*!< Pending bit for line 4 */
+#define  EXTI_PR_PR5                         ((uint32_t)0x00000020)        /*!< Pending bit for line 5 */
+#define  EXTI_PR_PR6                         ((uint32_t)0x00000040)        /*!< Pending bit for line 6 */
+#define  EXTI_PR_PR7                         ((uint32_t)0x00000080)        /*!< Pending bit for line 7 */
+#define  EXTI_PR_PR8                         ((uint32_t)0x00000100)        /*!< Pending bit for line 8 */
+#define  EXTI_PR_PR9                         ((uint32_t)0x00000200)        /*!< Pending bit for line 9 */
+#define  EXTI_PR_PR10                        ((uint32_t)0x00000400)        /*!< Pending bit for line 10 */
+#define  EXTI_PR_PR11                        ((uint32_t)0x00000800)        /*!< Pending bit for line 11 */
+#define  EXTI_PR_PR12                        ((uint32_t)0x00001000)        /*!< Pending bit for line 12 */
+#define  EXTI_PR_PR13                        ((uint32_t)0x00002000)        /*!< Pending bit for line 13 */
+#define  EXTI_PR_PR14                        ((uint32_t)0x00004000)        /*!< Pending bit for line 14 */
+#define  EXTI_PR_PR15                        ((uint32_t)0x00008000)        /*!< Pending bit for line 15 */
+#define  EXTI_PR_PR16                        ((uint32_t)0x00010000)        /*!< Pending bit for line 16 */
+#define  EXTI_PR_PR17                        ((uint32_t)0x00020000)        /*!< Pending bit for line 17 */
+#define  EXTI_PR_PR18                        ((uint32_t)0x00040000)        /*!< Pending bit for line 18 */
+#define  EXTI_PR_PR19                        ((uint32_t)0x00080000)        /*!< Pending bit for line 19 */
+
+/******************************************************************************/
+/*                                                                            */
+/*                             DMA Controller                                 */
+/*                                                                            */
+/******************************************************************************/
+
+/*******************  Bit definition for DMA_ISR register  ********************/
+#define  DMA_ISR_GIF1                        ((uint32_t)0x00000001)        /*!< Channel 1 Global interrupt flag */
+#define  DMA_ISR_TCIF1                       ((uint32_t)0x00000002)        /*!< Channel 1 Transfer Complete flag */
+#define  DMA_ISR_HTIF1                       ((uint32_t)0x00000004)        /*!< Channel 1 Half Transfer flag */
+#define  DMA_ISR_TEIF1                       ((uint32_t)0x00000008)        /*!< Channel 1 Transfer Error flag */
+#define  DMA_ISR_GIF2                        ((uint32_t)0x00000010)        /*!< Channel 2 Global interrupt flag */
+#define  DMA_ISR_TCIF2                       ((uint32_t)0x00000020)        /*!< Channel 2 Transfer Complete flag */
+#define  DMA_ISR_HTIF2                       ((uint32_t)0x00000040)        /*!< Channel 2 Half Transfer flag */
+#define  DMA_ISR_TEIF2                       ((uint32_t)0x00000080)        /*!< Channel 2 Transfer Error flag */
+#define  DMA_ISR_GIF3                        ((uint32_t)0x00000100)        /*!< Channel 3 Global interrupt flag */
+#define  DMA_ISR_TCIF3                       ((uint32_t)0x00000200)        /*!< Channel 3 Transfer Complete flag */
+#define  DMA_ISR_HTIF3                       ((uint32_t)0x00000400)        /*!< Channel 3 Half Transfer flag */
+#define  DMA_ISR_TEIF3                       ((uint32_t)0x00000800)        /*!< Channel 3 Transfer Error flag */
+#define  DMA_ISR_GIF4                        ((uint32_t)0x00001000)        /*!< Channel 4 Global interrupt flag */
+#define  DMA_ISR_TCIF4                       ((uint32_t)0x00002000)        /*!< Channel 4 Transfer Complete flag */
+#define  DMA_ISR_HTIF4                       ((uint32_t)0x00004000)        /*!< Channel 4 Half Transfer flag */
+#define  DMA_ISR_TEIF4                       ((uint32_t)0x00008000)        /*!< Channel 4 Transfer Error flag */
+#define  DMA_ISR_GIF5                        ((uint32_t)0x00010000)        /*!< Channel 5 Global interrupt flag */
+#define  DMA_ISR_TCIF5                       ((uint32_t)0x00020000)        /*!< Channel 5 Transfer Complete flag */
+#define  DMA_ISR_HTIF5                       ((uint32_t)0x00040000)        /*!< Channel 5 Half Transfer flag */
+#define  DMA_ISR_TEIF5                       ((uint32_t)0x00080000)        /*!< Channel 5 Transfer Error flag */
+#define  DMA_ISR_GIF6                        ((uint32_t)0x00100000)        /*!< Channel 6 Global interrupt flag */
+#define  DMA_ISR_TCIF6                       ((uint32_t)0x00200000)        /*!< Channel 6 Transfer Complete flag */
+#define  DMA_ISR_HTIF6                       ((uint32_t)0x00400000)        /*!< Channel 6 Half Transfer flag */
+#define  DMA_ISR_TEIF6                       ((uint32_t)0x00800000)        /*!< Channel 6 Transfer Error flag */
+#define  DMA_ISR_GIF7                        ((uint32_t)0x01000000)        /*!< Channel 7 Global interrupt flag */
+#define  DMA_ISR_TCIF7                       ((uint32_t)0x02000000)        /*!< Channel 7 Transfer Complete flag */
+#define  DMA_ISR_HTIF7                       ((uint32_t)0x04000000)        /*!< Channel 7 Half Transfer flag */
+#define  DMA_ISR_TEIF7                       ((uint32_t)0x08000000)        /*!< Channel 7 Transfer Error flag */
+
+/*******************  Bit definition for DMA_IFCR register  *******************/
+#define  DMA_IFCR_CGIF1                      ((uint32_t)0x00000001)        /*!< Channel 1 Global interrupt clear */
+#define  DMA_IFCR_CTCIF1                     ((uint32_t)0x00000002)        /*!< Channel 1 Transfer Complete clear */
+#define  DMA_IFCR_CHTIF1                     ((uint32_t)0x00000004)        /*!< Channel 1 Half Transfer clear */
+#define  DMA_IFCR_CTEIF1                     ((uint32_t)0x00000008)        /*!< Channel 1 Transfer Error clear */
+#define  DMA_IFCR_CGIF2                      ((uint32_t)0x00000010)        /*!< Channel 2 Global interrupt clear */
+#define  DMA_IFCR_CTCIF2                     ((uint32_t)0x00000020)        /*!< Channel 2 Transfer Complete clear */
+#define  DMA_IFCR_CHTIF2                     ((uint32_t)0x00000040)        /*!< Channel 2 Half Transfer clear */
+#define  DMA_IFCR_CTEIF2                     ((uint32_t)0x00000080)        /*!< Channel 2 Transfer Error clear */
+#define  DMA_IFCR_CGIF3                      ((uint32_t)0x00000100)        /*!< Channel 3 Global interrupt clear */
+#define  DMA_IFCR_CTCIF3                     ((uint32_t)0x00000200)        /*!< Channel 3 Transfer Complete clear */
+#define  DMA_IFCR_CHTIF3                     ((uint32_t)0x00000400)        /*!< Channel 3 Half Transfer clear */
+#define  DMA_IFCR_CTEIF3                     ((uint32_t)0x00000800)        /*!< Channel 3 Transfer Error clear */
+#define  DMA_IFCR_CGIF4                      ((uint32_t)0x00001000)        /*!< Channel 4 Global interrupt clear */
+#define  DMA_IFCR_CTCIF4                     ((uint32_t)0x00002000)        /*!< Channel 4 Transfer Complete clear */
+#define  DMA_IFCR_CHTIF4                     ((uint32_t)0x00004000)        /*!< Channel 4 Half Transfer clear */
+#define  DMA_IFCR_CTEIF4                     ((uint32_t)0x00008000)        /*!< Channel 4 Transfer Error clear */
+#define  DMA_IFCR_CGIF5                      ((uint32_t)0x00010000)        /*!< Channel 5 Global interrupt clear */
+#define  DMA_IFCR_CTCIF5                     ((uint32_t)0x00020000)        /*!< Channel 5 Transfer Complete clear */
+#define  DMA_IFCR_CHTIF5                     ((uint32_t)0x00040000)        /*!< Channel 5 Half Transfer clear */
+#define  DMA_IFCR_CTEIF5                     ((uint32_t)0x00080000)        /*!< Channel 5 Transfer Error clear */
+#define  DMA_IFCR_CGIF6                      ((uint32_t)0x00100000)        /*!< Channel 6 Global interrupt clear */
+#define  DMA_IFCR_CTCIF6                     ((uint32_t)0x00200000)        /*!< Channel 6 Transfer Complete clear */
+#define  DMA_IFCR_CHTIF6                     ((uint32_t)0x00400000)        /*!< Channel 6 Half Transfer clear */
+#define  DMA_IFCR_CTEIF6                     ((uint32_t)0x00800000)        /*!< Channel 6 Transfer Error clear */
+#define  DMA_IFCR_CGIF7                      ((uint32_t)0x01000000)        /*!< Channel 7 Global interrupt clear */
+#define  DMA_IFCR_CTCIF7                     ((uint32_t)0x02000000)        /*!< Channel 7 Transfer Complete clear */
+#define  DMA_IFCR_CHTIF7                     ((uint32_t)0x04000000)        /*!< Channel 7 Half Transfer clear */
+#define  DMA_IFCR_CTEIF7                     ((uint32_t)0x08000000)        /*!< Channel 7 Transfer Error clear */
+
+/*******************  Bit definition for DMA_CCR1 register  *******************/
+#define  DMA_CCR1_EN                         ((uint16_t)0x0001)            /*!< Channel enable*/
+#define  DMA_CCR1_TCIE                       ((uint16_t)0x0002)            /*!< Transfer complete interrupt enable */
+#define  DMA_CCR1_HTIE                       ((uint16_t)0x0004)            /*!< Half Transfer interrupt enable */
+#define  DMA_CCR1_TEIE                       ((uint16_t)0x0008)            /*!< Transfer error interrupt enable */
+#define  DMA_CCR1_DIR                        ((uint16_t)0x0010)            /*!< Data transfer direction */
+#define  DMA_CCR1_CIRC                       ((uint16_t)0x0020)            /*!< Circular mode */
+#define  DMA_CCR1_PINC                       ((uint16_t)0x0040)            /*!< Peripheral increment mode */
+#define  DMA_CCR1_MINC                       ((uint16_t)0x0080)            /*!< Memory increment mode */
+
+#define  DMA_CCR1_PSIZE                      ((uint16_t)0x0300)            /*!< PSIZE[1:0] bits (Peripheral size) */
+#define  DMA_CCR1_PSIZE_0                    ((uint16_t)0x0100)            /*!< Bit 0 */
+#define  DMA_CCR1_PSIZE_1                    ((uint16_t)0x0200)            /*!< Bit 1 */
+
+#define  DMA_CCR1_MSIZE                      ((uint16_t)0x0C00)            /*!< MSIZE[1:0] bits (Memory size) */
+#define  DMA_CCR1_MSIZE_0                    ((uint16_t)0x0400)            /*!< Bit 0 */
+#define  DMA_CCR1_MSIZE_1                    ((uint16_t)0x0800)            /*!< Bit 1 */
+
+#define  DMA_CCR1_PL                         ((uint16_t)0x3000)            /*!< PL[1:0] bits(Channel Priority level) */
+#define  DMA_CCR1_PL_0                       ((uint16_t)0x1000)            /*!< Bit 0 */
+#define  DMA_CCR1_PL_1                       ((uint16_t)0x2000)            /*!< Bit 1 */
+
+#define  DMA_CCR1_MEM2MEM                    ((uint16_t)0x4000)            /*!< Memory to memory mode */
+
+/*******************  Bit definition for DMA_CCR2 register  *******************/
+#define  DMA_CCR2_EN                         ((uint16_t)0x0001)            /*!< Channel enable */
+#define  DMA_CCR2_TCIE                       ((uint16_t)0x0002)            /*!< Transfer complete interrupt enable */
+#define  DMA_CCR2_HTIE                       ((uint16_t)0x0004)            /*!< Half Transfer interrupt enable */
+#define  DMA_CCR2_TEIE                       ((uint16_t)0x0008)            /*!< Transfer error interrupt enable */
+#define  DMA_CCR2_DIR                        ((uint16_t)0x0010)            /*!< Data transfer direction */
+#define  DMA_CCR2_CIRC                       ((uint16_t)0x0020)            /*!< Circular mode */
+#define  DMA_CCR2_PINC                       ((uint16_t)0x0040)            /*!< Peripheral increment mode */
+#define  DMA_CCR2_MINC                       ((uint16_t)0x0080)            /*!< Memory increment mode */
+
+#define  DMA_CCR2_PSIZE                      ((uint16_t)0x0300)            /*!< PSIZE[1:0] bits (Peripheral size) */
+#define  DMA_CCR2_PSIZE_0                    ((uint16_t)0x0100)            /*!< Bit 0 */
+#define  DMA_CCR2_PSIZE_1                    ((uint16_t)0x0200)            /*!< Bit 1 */
+
+#define  DMA_CCR2_MSIZE                      ((uint16_t)0x0C00)            /*!< MSIZE[1:0] bits (Memory size) */
+#define  DMA_CCR2_MSIZE_0                    ((uint16_t)0x0400)            /*!< Bit 0 */
+#define  DMA_CCR2_MSIZE_1                    ((uint16_t)0x0800)            /*!< Bit 1 */
+
+#define  DMA_CCR2_PL                         ((uint16_t)0x3000)            /*!< PL[1:0] bits (Channel Priority level) */
+#define  DMA_CCR2_PL_0                       ((uint16_t)0x1000)            /*!< Bit 0 */
+#define  DMA_CCR2_PL_1                       ((uint16_t)0x2000)            /*!< Bit 1 */
+
+#define  DMA_CCR2_MEM2MEM                    ((uint16_t)0x4000)            /*!< Memory to memory mode */
+
+/*******************  Bit definition for DMA_CCR3 register  *******************/
+#define  DMA_CCR3_EN                         ((uint16_t)0x0001)            /*!< Channel enable */
+#define  DMA_CCR3_TCIE                       ((uint16_t)0x0002)            /*!< Transfer complete interrupt enable */
+#define  DMA_CCR3_HTIE                       ((uint16_t)0x0004)            /*!< Half Transfer interrupt enable */
+#define  DMA_CCR3_TEIE                       ((uint16_t)0x0008)            /*!< Transfer error interrupt enable */
+#define  DMA_CCR3_DIR                        ((uint16_t)0x0010)            /*!< Data transfer direction */
+#define  DMA_CCR3_CIRC                       ((uint16_t)0x0020)            /*!< Circular mode */
+#define  DMA_CCR3_PINC                       ((uint16_t)0x0040)            /*!< Peripheral increment mode */
+#define  DMA_CCR3_MINC                       ((uint16_t)0x0080)            /*!< Memory increment mode */
+
+#define  DMA_CCR3_PSIZE                      ((uint16_t)0x0300)            /*!< PSIZE[1:0] bits (Peripheral size) */
+#define  DMA_CCR3_PSIZE_0                    ((uint16_t)0x0100)            /*!< Bit 0 */
+#define  DMA_CCR3_PSIZE_1                    ((uint16_t)0x0200)            /*!< Bit 1 */
+
+#define  DMA_CCR3_MSIZE                      ((uint16_t)0x0C00)            /*!< MSIZE[1:0] bits (Memory size) */
+#define  DMA_CCR3_MSIZE_0                    ((uint16_t)0x0400)            /*!< Bit 0 */
+#define  DMA_CCR3_MSIZE_1                    ((uint16_t)0x0800)            /*!< Bit 1 */
+
+#define  DMA_CCR3_PL                         ((uint16_t)0x3000)            /*!< PL[1:0] bits (Channel Priority level) */
+#define  DMA_CCR3_PL_0                       ((uint16_t)0x1000)            /*!< Bit 0 */
+#define  DMA_CCR3_PL_1                       ((uint16_t)0x2000)            /*!< Bit 1 */
+
+#define  DMA_CCR3_MEM2MEM                    ((uint16_t)0x4000)            /*!< Memory to memory mode */
+
+/*!<******************  Bit definition for DMA_CCR4 register  *******************/
+#define  DMA_CCR4_EN                         ((uint16_t)0x0001)            /*!< Channel enable */
+#define  DMA_CCR4_TCIE                       ((uint16_t)0x0002)            /*!< Transfer complete interrupt enable */
+#define  DMA_CCR4_HTIE                       ((uint16_t)0x0004)            /*!< Half Transfer interrupt enable */
+#define  DMA_CCR4_TEIE                       ((uint16_t)0x0008)            /*!< Transfer error interrupt enable */
+#define  DMA_CCR4_DIR                        ((uint16_t)0x0010)            /*!< Data transfer direction */
+#define  DMA_CCR4_CIRC                       ((uint16_t)0x0020)            /*!< Circular mode */
+#define  DMA_CCR4_PINC                       ((uint16_t)0x0040)            /*!< Peripheral increment mode */
+#define  DMA_CCR4_MINC                       ((uint16_t)0x0080)            /*!< Memory increment mode */
+
+#define  DMA_CCR4_PSIZE                      ((uint16_t)0x0300)            /*!< PSIZE[1:0] bits (Peripheral size) */
+#define  DMA_CCR4_PSIZE_0                    ((uint16_t)0x0100)            /*!< Bit 0 */
+#define  DMA_CCR4_PSIZE_1                    ((uint16_t)0x0200)            /*!< Bit 1 */
+
+#define  DMA_CCR4_MSIZE                      ((uint16_t)0x0C00)            /*!< MSIZE[1:0] bits (Memory size) */
+#define  DMA_CCR4_MSIZE_0                    ((uint16_t)0x0400)            /*!< Bit 0 */
+#define  DMA_CCR4_MSIZE_1                    ((uint16_t)0x0800)            /*!< Bit 1 */
+
+#define  DMA_CCR4_PL                         ((uint16_t)0x3000)            /*!< PL[1:0] bits (Channel Priority level) */
+#define  DMA_CCR4_PL_0                       ((uint16_t)0x1000)            /*!< Bit 0 */
+#define  DMA_CCR4_PL_1                       ((uint16_t)0x2000)            /*!< Bit 1 */
+
+#define  DMA_CCR4_MEM2MEM                    ((uint16_t)0x4000)            /*!< Memory to memory mode */
+
+/******************  Bit definition for DMA_CCR5 register  *******************/
+#define  DMA_CCR5_EN                         ((uint16_t)0x0001)            /*!< Channel enable */
+#define  DMA_CCR5_TCIE                       ((uint16_t)0x0002)            /*!< Transfer complete interrupt enable */
+#define  DMA_CCR5_HTIE                       ((uint16_t)0x0004)            /*!< Half Transfer interrupt enable */
+#define  DMA_CCR5_TEIE                       ((uint16_t)0x0008)            /*!< Transfer error interrupt enable */
+#define  DMA_CCR5_DIR                        ((uint16_t)0x0010)            /*!< Data transfer direction */
+#define  DMA_CCR5_CIRC                       ((uint16_t)0x0020)            /*!< Circular mode */
+#define  DMA_CCR5_PINC                       ((uint16_t)0x0040)            /*!< Peripheral increment mode */
+#define  DMA_CCR5_MINC                       ((uint16_t)0x0080)            /*!< Memory increment mode */
+
+#define  DMA_CCR5_PSIZE                      ((uint16_t)0x0300)            /*!< PSIZE[1:0] bits (Peripheral size) */
+#define  DMA_CCR5_PSIZE_0                    ((uint16_t)0x0100)            /*!< Bit 0 */
+#define  DMA_CCR5_PSIZE_1                    ((uint16_t)0x0200)            /*!< Bit 1 */
+
+#define  DMA_CCR5_MSIZE                      ((uint16_t)0x0C00)            /*!< MSIZE[1:0] bits (Memory size) */
+#define  DMA_CCR5_MSIZE_0                    ((uint16_t)0x0400)            /*!< Bit 0 */
+#define  DMA_CCR5_MSIZE_1                    ((uint16_t)0x0800)            /*!< Bit 1 */
+
+#define  DMA_CCR5_PL                         ((uint16_t)0x3000)            /*!< PL[1:0] bits (Channel Priority level) */
+#define  DMA_CCR5_PL_0                       ((uint16_t)0x1000)            /*!< Bit 0 */
+#define  DMA_CCR5_PL_1                       ((uint16_t)0x2000)            /*!< Bit 1 */
+
+#define  DMA_CCR5_MEM2MEM                    ((uint16_t)0x4000)            /*!< Memory to memory mode enable */
+
+/*******************  Bit definition for DMA_CCR6 register  *******************/
+#define  DMA_CCR6_EN                         ((uint16_t)0x0001)            /*!< Channel enable */
+#define  DMA_CCR6_TCIE                       ((uint16_t)0x0002)            /*!< Transfer complete interrupt enable */
+#define  DMA_CCR6_HTIE                       ((uint16_t)0x0004)            /*!< Half Transfer interrupt enable */
+#define  DMA_CCR6_TEIE                       ((uint16_t)0x0008)            /*!< Transfer error interrupt enable */
+#define  DMA_CCR6_DIR                        ((uint16_t)0x0010)            /*!< Data transfer direction */
+#define  DMA_CCR6_CIRC                       ((uint16_t)0x0020)            /*!< Circular mode */
+#define  DMA_CCR6_PINC                       ((uint16_t)0x0040)            /*!< Peripheral increment mode */
+#define  DMA_CCR6_MINC                       ((uint16_t)0x0080)            /*!< Memory increment mode */
+
+#define  DMA_CCR6_PSIZE                      ((uint16_t)0x0300)            /*!< PSIZE[1:0] bits (Peripheral size) */
+#define  DMA_CCR6_PSIZE_0                    ((uint16_t)0x0100)            /*!< Bit 0 */
+#define  DMA_CCR6_PSIZE_1                    ((uint16_t)0x0200)            /*!< Bit 1 */
+
+#define  DMA_CCR6_MSIZE                      ((uint16_t)0x0C00)            /*!< MSIZE[1:0] bits (Memory size) */
+#define  DMA_CCR6_MSIZE_0                    ((uint16_t)0x0400)            /*!< Bit 0 */
+#define  DMA_CCR6_MSIZE_1                    ((uint16_t)0x0800)            /*!< Bit 1 */
+
+#define  DMA_CCR6_PL                         ((uint16_t)0x3000)            /*!< PL[1:0] bits (Channel Priority level) */
+#define  DMA_CCR6_PL_0                       ((uint16_t)0x1000)            /*!< Bit 0 */
+#define  DMA_CCR6_PL_1                       ((uint16_t)0x2000)            /*!< Bit 1 */
+
+#define  DMA_CCR6_MEM2MEM                    ((uint16_t)0x4000)            /*!< Memory to memory mode */
+
+/*******************  Bit definition for DMA_CCR7 register  *******************/
+#define  DMA_CCR7_EN                         ((uint16_t)0x0001)            /*!< Channel enable */
+#define  DMA_CCR7_TCIE                       ((uint16_t)0x0002)            /*!< Transfer complete interrupt enable */
+#define  DMA_CCR7_HTIE                       ((uint16_t)0x0004)            /*!< Half Transfer interrupt enable */
+#define  DMA_CCR7_TEIE                       ((uint16_t)0x0008)            /*!< Transfer error interrupt enable */
+#define  DMA_CCR7_DIR                        ((uint16_t)0x0010)            /*!< Data transfer direction */
+#define  DMA_CCR7_CIRC                       ((uint16_t)0x0020)            /*!< Circular mode */
+#define  DMA_CCR7_PINC                       ((uint16_t)0x0040)            /*!< Peripheral increment mode */
+#define  DMA_CCR7_MINC                       ((uint16_t)0x0080)            /*!< Memory increment mode */
+
+#define  DMA_CCR7_PSIZE            ,         ((uint16_t)0x0300)            /*!< PSIZE[1:0] bits (Peripheral size) */
+#define  DMA_CCR7_PSIZE_0                    ((uint16_t)0x0100)            /*!< Bit 0 */
+#define  DMA_CCR7_PSIZE_1                    ((uint16_t)0x0200)            /*!< Bit 1 */
+
+#define  DMA_CCR7_MSIZE                      ((uint16_t)0x0C00)            /*!< MSIZE[1:0] bits (Memory size) */
+#define  DMA_CCR7_MSIZE_0                    ((uint16_t)0x0400)            /*!< Bit 0 */
+#define  DMA_CCR7_MSIZE_1                    ((uint16_t)0x0800)            /*!< Bit 1 */
+
+#define  DMA_CCR7_PL                         ((uint16_t)0x3000)            /*!< PL[1:0] bits (Channel Priority level) */
+#define  DMA_CCR7_PL_0                       ((uint16_t)0x1000)            /*!< Bit 0 */
+#define  DMA_CCR7_PL_1                       ((uint16_t)0x2000)            /*!< Bit 1 */
+
+#define  DMA_CCR7_MEM2MEM                    ((uint16_t)0x4000)            /*!< Memory to memory mode enable */
+
+/******************  Bit definition for DMA_CNDTR1 register  ******************/
+#define  DMA_CNDTR1_NDT                      ((uint16_t)0xFFFF)            /*!< Number of data to Transfer */
+
+/******************  Bit definition for DMA_CNDTR2 register  ******************/
+#define  DMA_CNDTR2_NDT                      ((uint16_t)0xFFFF)            /*!< Number of data to Transfer */
+
+/******************  Bit definition for DMA_CNDTR3 register  ******************/
+#define  DMA_CNDTR3_NDT                      ((uint16_t)0xFFFF)            /*!< Number of data to Transfer */
+
+/******************  Bit definition for DMA_CNDTR4 register  ******************/
+#define  DMA_CNDTR4_NDT                      ((uint16_t)0xFFFF)            /*!< Number of data to Transfer */
+
+/******************  Bit definition for DMA_CNDTR5 register  ******************/
+#define  DMA_CNDTR5_NDT                      ((uint16_t)0xFFFF)            /*!< Number of data to Transfer */
+
+/******************  Bit definition for DMA_CNDTR6 register  ******************/
+#define  DMA_CNDTR6_NDT                      ((uint16_t)0xFFFF)            /*!< Number of data to Transfer */
+
+/******************  Bit definition for DMA_CNDTR7 register  ******************/
+#define  DMA_CNDTR7_NDT                      ((uint16_t)0xFFFF)            /*!< Number of data to Transfer */
+
+/******************  Bit definition for DMA_CPAR1 register  *******************/
+#define  DMA_CPAR1_PA                        ((uint32_t)0xFFFFFFFF)        /*!< Peripheral Address */
+
+/******************  Bit definition for DMA_CPAR2 register  *******************/
+#define  DMA_CPAR2_PA                        ((uint32_t)0xFFFFFFFF)        /*!< Peripheral Address */
+
+/******************  Bit definition for DMA_CPAR3 register  *******************/
+#define  DMA_CPAR3_PA                        ((uint32_t)0xFFFFFFFF)        /*!< Peripheral Address */
+
+
+/******************  Bit definition for DMA_CPAR4 register  *******************/
+#define  DMA_CPAR4_PA                        ((uint32_t)0xFFFFFFFF)        /*!< Peripheral Address */
+
+/******************  Bit definition for DMA_CPAR5 register  *******************/
+#define  DMA_CPAR5_PA                        ((uint32_t)0xFFFFFFFF)        /*!< Peripheral Address */
+
+/******************  Bit definition for DMA_CPAR6 register  *******************/
+#define  DMA_CPAR6_PA                        ((uint32_t)0xFFFFFFFF)        /*!< Peripheral Address */
+
+
+/******************  Bit definition for DMA_CPAR7 register  *******************/
+#define  DMA_CPAR7_PA                        ((uint32_t)0xFFFFFFFF)        /*!< Peripheral Address */
+
+/******************  Bit definition for DMA_CMAR1 register  *******************/
+#define  DMA_CMAR1_MA                        ((uint32_t)0xFFFFFFFF)        /*!< Memory Address */
+
+/******************  Bit definition for DMA_CMAR2 register  *******************/
+#define  DMA_CMAR2_MA                        ((uint32_t)0xFFFFFFFF)        /*!< Memory Address */
+
+/******************  Bit definition for DMA_CMAR3 register  *******************/
+#define  DMA_CMAR3_MA                        ((uint32_t)0xFFFFFFFF)        /*!< Memory Address */
+
+
+/******************  Bit definition for DMA_CMAR4 register  *******************/
+#define  DMA_CMAR4_MA                        ((uint32_t)0xFFFFFFFF)        /*!< Memory Address */
+
+/******************  Bit definition for DMA_CMAR5 register  *******************/
+#define  DMA_CMAR5_MA                        ((uint32_t)0xFFFFFFFF)        /*!< Memory Address */
+
+/******************  Bit definition for DMA_CMAR6 register  *******************/
+#define  DMA_CMAR6_MA                        ((uint32_t)0xFFFFFFFF)        /*!< Memory Address */
+
+/******************  Bit definition for DMA_CMAR7 register  *******************/
+#define  DMA_CMAR7_MA                        ((uint32_t)0xFFFFFFFF)        /*!< Memory Address */
+
+/******************************************************************************/
+/*                                                                            */
+/*                        Analog to Digital Converter                         */
+/*                                                                            */
+/******************************************************************************/
+
+/********************  Bit definition for ADC_SR register  ********************/
+#define  ADC_SR_AWD                          ((uint8_t)0x01)               /*!< Analog watchdog flag */
+#define  ADC_SR_EOC                          ((uint8_t)0x02)               /*!< End of conversion */
+#define  ADC_SR_JEOC                         ((uint8_t)0x04)               /*!< Injected channel end of conversion */
+#define  ADC_SR_JSTRT                        ((uint8_t)0x08)               /*!< Injected channel Start flag */
+#define  ADC_SR_STRT                         ((uint8_t)0x10)               /*!< Regular channel Start flag */
+
+/*******************  Bit definition for ADC_CR1 register  ********************/
+#define  ADC_CR1_AWDCH                       ((uint32_t)0x0000001F)        /*!< AWDCH[4:0] bits (Analog watchdog channel select bits) */
+#define  ADC_CR1_AWDCH_0                     ((uint32_t)0x00000001)        /*!< Bit 0 */
+#define  ADC_CR1_AWDCH_1                     ((uint32_t)0x00000002)        /*!< Bit 1 */
+#define  ADC_CR1_AWDCH_2                     ((uint32_t)0x00000004)        /*!< Bit 2 */
+#define  ADC_CR1_AWDCH_3                     ((uint32_t)0x00000008)        /*!< Bit 3 */
+#define  ADC_CR1_AWDCH_4                     ((uint32_t)0x00000010)        /*!< Bit 4 */
+
+#define  ADC_CR1_EOCIE                       ((uint32_t)0x00000020)        /*!< Interrupt enable for EOC */
+#define  ADC_CR1_AWDIE                       ((uint32_t)0x00000040)        /*!< Analog Watchdog interrupt enable */
+#define  ADC_CR1_JEOCIE                      ((uint32_t)0x00000080)        /*!< Interrupt enable for injected channels */
+#define  ADC_CR1_SCAN                        ((uint32_t)0x00000100)        /*!< Scan mode */
+#define  ADC_CR1_AWDSGL                      ((uint32_t)0x00000200)        /*!< Enable the watchdog on a single channel in scan mode */
+#define  ADC_CR1_JAUTO                       ((uint32_t)0x00000400)        /*!< Automatic injected group conversion */
+#define  ADC_CR1_DISCEN                      ((uint32_t)0x00000800)        /*!< Discontinuous mode on regular channels */
+#define  ADC_CR1_JDISCEN                     ((uint32_t)0x00001000)        /*!< Discontinuous mode on injected channels */
+
+#define  ADC_CR1_DISCNUM                     ((uint32_t)0x0000E000)        /*!< DISCNUM[2:0] bits (Discontinuous mode channel count) */
+#define  ADC_CR1_DISCNUM_0                   ((uint32_t)0x00002000)        /*!< Bit 0 */
+#define  ADC_CR1_DISCNUM_1                   ((uint32_t)0x00004000)        /*!< Bit 1 */
+#define  ADC_CR1_DISCNUM_2                   ((uint32_t)0x00008000)        /*!< Bit 2 */
+
+#define  ADC_CR1_DUALMOD                     ((uint32_t)0x000F0000)        /*!< DUALMOD[3:0] bits (Dual mode selection) */
+#define  ADC_CR1_DUALMOD_0                   ((uint32_t)0x00010000)        /*!< Bit 0 */
+#define  ADC_CR1_DUALMOD_1                   ((uint32_t)0x00020000)        /*!< Bit 1 */
+#define  ADC_CR1_DUALMOD_2                   ((uint32_t)0x00040000)        /*!< Bit 2 */
+#define  ADC_CR1_DUALMOD_3                   ((uint32_t)0x00080000)        /*!< Bit 3 */
+
+#define  ADC_CR1_JAWDEN                      ((uint32_t)0x00400000)        /*!< Analog watchdog enable on injected channels */
+#define  ADC_CR1_AWDEN                       ((uint32_t)0x00800000)        /*!< Analog watchdog enable on regular channels */
+
+  
+/*******************  Bit definition for ADC_CR2 register  ********************/
+#define  ADC_CR2_ADON                        ((uint32_t)0x00000001)        /*!< A/D Converter ON / OFF */
+#define  ADC_CR2_CONT                        ((uint32_t)0x00000002)        /*!< Continuous Conversion */
+#define  ADC_CR2_CAL                         ((uint32_t)0x00000004)        /*!< A/D Calibration */
+#define  ADC_CR2_RSTCAL                      ((uint32_t)0x00000008)        /*!< Reset Calibration */
+#define  ADC_CR2_DMA                         ((uint32_t)0x00000100)        /*!< Direct Memory access mode */
+#define  ADC_CR2_ALIGN                       ((uint32_t)0x00000800)        /*!< Data Alignment */
+
+#define  ADC_CR2_JEXTSEL                     ((uint32_t)0x00007000)        /*!< JEXTSEL[2:0] bits (External event select for injected group) */
+#define  ADC_CR2_JEXTSEL_0                   ((uint32_t)0x00001000)        /*!< Bit 0 */
+#define  ADC_CR2_JEXTSEL_1                   ((uint32_t)0x00002000)        /*!< Bit 1 */
+#define  ADC_CR2_JEXTSEL_2                   ((uint32_t)0x00004000)        /*!< Bit 2 */
+
+#define  ADC_CR2_JEXTTRIG                    ((uint32_t)0x00008000)        /*!< External Trigger Conversion mode for injected channels */
+
+#define  ADC_CR2_EXTSEL                      ((uint32_t)0x000E0000)        /*!< EXTSEL[2:0] bits (External Event Select for regular group) */
+#define  ADC_CR2_EXTSEL_0                    ((uint32_t)0x00020000)        /*!< Bit 0 */
+#define  ADC_CR2_EXTSEL_1                    ((uint32_t)0x00040000)        /*!< Bit 1 */
+#define  ADC_CR2_EXTSEL_2                    ((uint32_t)0x00080000)        /*!< Bit 2 */
+
+#define  ADC_CR2_EXTTRIG                     ((uint32_t)0x00100000)        /*!< External Trigger Conversion mode for regular channels */
+#define  ADC_CR2_JSWSTART                    ((uint32_t)0x00200000)        /*!< Start Conversion of injected channels */
+#define  ADC_CR2_SWSTART                     ((uint32_t)0x00400000)        /*!< Start Conversion of regular channels */
+#define  ADC_CR2_TSVREFE                     ((uint32_t)0x00800000)        /*!< Temperature Sensor and VREFINT Enable */
+
+/******************  Bit definition for ADC_SMPR1 register  *******************/
+#define  ADC_SMPR1_SMP10                     ((uint32_t)0x00000007)        /*!< SMP10[2:0] bits (Channel 10 Sample time selection) */
+#define  ADC_SMPR1_SMP10_0                   ((uint32_t)0x00000001)        /*!< Bit 0 */
+#define  ADC_SMPR1_SMP10_1                   ((uint32_t)0x00000002)        /*!< Bit 1 */
+#define  ADC_SMPR1_SMP10_2                   ((uint32_t)0x00000004)        /*!< Bit 2 */
+
+#define  ADC_SMPR1_SMP11                     ((uint32_t)0x00000038)        /*!< SMP11[2:0] bits (Channel 11 Sample time selection) */
+#define  ADC_SMPR1_SMP11_0                   ((uint32_t)0x00000008)        /*!< Bit 0 */
+#define  ADC_SMPR1_SMP11_1                   ((uint32_t)0x00000010)        /*!< Bit 1 */
+#define  ADC_SMPR1_SMP11_2                   ((uint32_t)0x00000020)        /*!< Bit 2 */
+
+#define  ADC_SMPR1_SMP12                     ((uint32_t)0x000001C0)        /*!< SMP12[2:0] bits (Channel 12 Sample time selection) */
+#define  ADC_SMPR1_SMP12_0                   ((uint32_t)0x00000040)        /*!< Bit 0 */
+#define  ADC_SMPR1_SMP12_1                   ((uint32_t)0x00000080)        /*!< Bit 1 */
+#define  ADC_SMPR1_SMP12_2                   ((uint32_t)0x00000100)        /*!< Bit 2 */
+
+#define  ADC_SMPR1_SMP13                     ((uint32_t)0x00000E00)        /*!< SMP13[2:0] bits (Channel 13 Sample time selection) */
+#define  ADC_SMPR1_SMP13_0                   ((uint32_t)0x00000200)        /*!< Bit 0 */
+#define  ADC_SMPR1_SMP13_1                   ((uint32_t)0x00000400)        /*!< Bit 1 */
+#define  ADC_SMPR1_SMP13_2                   ((uint32_t)0x00000800)        /*!< Bit 2 */
+
+#define  ADC_SMPR1_SMP14                     ((uint32_t)0x00007000)        /*!< SMP14[2:0] bits (Channel 14 Sample time selection) */
+#define  ADC_SMPR1_SMP14_0                   ((uint32_t)0x00001000)        /*!< Bit 0 */
+#define  ADC_SMPR1_SMP14_1                   ((uint32_t)0x00002000)        /*!< Bit 1 */
+#define  ADC_SMPR1_SMP14_2                   ((uint32_t)0x00004000)        /*!< Bit 2 */
+
+#define  ADC_SMPR1_SMP15                     ((uint32_t)0x00038000)        /*!< SMP15[2:0] bits (Channel 15 Sample time selection) */
+#define  ADC_SMPR1_SMP15_0                   ((uint32_t)0x00008000)        /*!< Bit 0 */
+#define  ADC_SMPR1_SMP15_1                   ((uint32_t)0x00010000)        /*!< Bit 1 */
+#define  ADC_SMPR1_SMP15_2                   ((uint32_t)0x00020000)        /*!< Bit 2 */
+
+#define  ADC_SMPR1_SMP16                     ((uint32_t)0x001C0000)        /*!< SMP16[2:0] bits (Channel 16 Sample time selection) */
+#define  ADC_SMPR1_SMP16_0                   ((uint32_t)0x00040000)        /*!< Bit 0 */
+#define  ADC_SMPR1_SMP16_1                   ((uint32_t)0x00080000)        /*!< Bit 1 */
+#define  ADC_SMPR1_SMP16_2                   ((uint32_t)0x00100000)        /*!< Bit 2 */
+
+#define  ADC_SMPR1_SMP17                     ((uint32_t)0x00E00000)        /*!< SMP17[2:0] bits (Channel 17 Sample time selection) */
+#define  ADC_SMPR1_SMP17_0                   ((uint32_t)0x00200000)        /*!< Bit 0 */
+#define  ADC_SMPR1_SMP17_1                   ((uint32_t)0x00400000)        /*!< Bit 1 */
+#define  ADC_SMPR1_SMP17_2                   ((uint32_t)0x00800000)        /*!< Bit 2 */
+
+/******************  Bit definition for ADC_SMPR2 register  *******************/
+#define  ADC_SMPR2_SMP0                      ((uint32_t)0x00000007)        /*!< SMP0[2:0] bits (Channel 0 Sample time selection) */
+#define  ADC_SMPR2_SMP0_0                    ((uint32_t)0x00000001)        /*!< Bit 0 */
+#define  ADC_SMPR2_SMP0_1                    ((uint32_t)0x00000002)        /*!< Bit 1 */
+#define  ADC_SMPR2_SMP0_2                    ((uint32_t)0x00000004)        /*!< Bit 2 */
+
+#define  ADC_SMPR2_SMP1                      ((uint32_t)0x00000038)        /*!< SMP1[2:0] bits (Channel 1 Sample time selection) */
+#define  ADC_SMPR2_SMP1_0                    ((uint32_t)0x00000008)        /*!< Bit 0 */
+#define  ADC_SMPR2_SMP1_1                    ((uint32_t)0x00000010)        /*!< Bit 1 */
+#define  ADC_SMPR2_SMP1_2                    ((uint32_t)0x00000020)        /*!< Bit 2 */
+
+#define  ADC_SMPR2_SMP2                      ((uint32_t)0x000001C0)        /*!< SMP2[2:0] bits (Channel 2 Sample time selection) */
+#define  ADC_SMPR2_SMP2_0                    ((uint32_t)0x00000040)        /*!< Bit 0 */
+#define  ADC_SMPR2_SMP2_1                    ((uint32_t)0x00000080)        /*!< Bit 1 */
+#define  ADC_SMPR2_SMP2_2                    ((uint32_t)0x00000100)        /*!< Bit 2 */
+
+#define  ADC_SMPR2_SMP3                      ((uint32_t)0x00000E00)        /*!< SMP3[2:0] bits (Channel 3 Sample time selection) */
+#define  ADC_SMPR2_SMP3_0                    ((uint32_t)0x00000200)        /*!< Bit 0 */
+#define  ADC_SMPR2_SMP3_1                    ((uint32_t)0x00000400)        /*!< Bit 1 */
+#define  ADC_SMPR2_SMP3_2                    ((uint32_t)0x00000800)        /*!< Bit 2 */
+
+#define  ADC_SMPR2_SMP4                      ((uint32_t)0x00007000)        /*!< SMP4[2:0] bits (Channel 4 Sample time selection) */
+#define  ADC_SMPR2_SMP4_0                    ((uint32_t)0x00001000)        /*!< Bit 0 */
+#define  ADC_SMPR2_SMP4_1                    ((uint32_t)0x00002000)        /*!< Bit 1 */
+#define  ADC_SMPR2_SMP4_2                    ((uint32_t)0x00004000)        /*!< Bit 2 */
+
+#define  ADC_SMPR2_SMP5                      ((uint32_t)0x00038000)        /*!< SMP5[2:0] bits (Channel 5 Sample time selection) */
+#define  ADC_SMPR2_SMP5_0                    ((uint32_t)0x00008000)        /*!< Bit 0 */
+#define  ADC_SMPR2_SMP5_1                    ((uint32_t)0x00010000)        /*!< Bit 1 */
+#define  ADC_SMPR2_SMP5_2                    ((uint32_t)0x00020000)        /*!< Bit 2 */
+
+#define  ADC_SMPR2_SMP6                      ((uint32_t)0x001C0000)        /*!< SMP6[2:0] bits (Channel 6 Sample time selection) */
+#define  ADC_SMPR2_SMP6_0                    ((uint32_t)0x00040000)        /*!< Bit 0 */
+#define  ADC_SMPR2_SMP6_1                    ((uint32_t)0x00080000)        /*!< Bit 1 */
+#define  ADC_SMPR2_SMP6_2                    ((uint32_t)0x00100000)        /*!< Bit 2 */
+
+#define  ADC_SMPR2_SMP7                      ((uint32_t)0x00E00000)        /*!< SMP7[2:0] bits (Channel 7 Sample time selection) */
+#define  ADC_SMPR2_SMP7_0                    ((uint32_t)0x00200000)        /*!< Bit 0 */
+#define  ADC_SMPR2_SMP7_1                    ((uint32_t)0x00400000)        /*!< Bit 1 */
+#define  ADC_SMPR2_SMP7_2                    ((uint32_t)0x00800000)        /*!< Bit 2 */
+
+#define  ADC_SMPR2_SMP8                      ((uint32_t)0x07000000)        /*!< SMP8[2:0] bits (Channel 8 Sample time selection) */
+#define  ADC_SMPR2_SMP8_0                    ((uint32_t)0x01000000)        /*!< Bit 0 */
+#define  ADC_SMPR2_SMP8_1                    ((uint32_t)0x02000000)        /*!< Bit 1 */
+#define  ADC_SMPR2_SMP8_2                    ((uint32_t)0x04000000)        /*!< Bit 2 */
+
+#define  ADC_SMPR2_SMP9                      ((uint32_t)0x38000000)        /*!< SMP9[2:0] bits (Channel 9 Sample time selection) */
+#define  ADC_SMPR2_SMP9_0                    ((uint32_t)0x08000000)        /*!< Bit 0 */
+#define  ADC_SMPR2_SMP9_1                    ((uint32_t)0x10000000)        /*!< Bit 1 */
+#define  ADC_SMPR2_SMP9_2                    ((uint32_t)0x20000000)        /*!< Bit 2 */
+
+/******************  Bit definition for ADC_JOFR1 register  *******************/
+#define  ADC_JOFR1_JOFFSET1                  ((uint16_t)0x0FFF)            /*!< Data offset for injected channel 1 */
+
+/******************  Bit definition for ADC_JOFR2 register  *******************/
+#define  ADC_JOFR2_JOFFSET2                  ((uint16_t)0x0FFF)            /*!< Data offset for injected channel 2 */
+
+/******************  Bit definition for ADC_JOFR3 register  *******************/
+#define  ADC_JOFR3_JOFFSET3                  ((uint16_t)0x0FFF)            /*!< Data offset for injected channel 3 */
+
+/******************  Bit definition for ADC_JOFR4 register  *******************/
+#define  ADC_JOFR4_JOFFSET4                  ((uint16_t)0x0FFF)            /*!< Data offset for injected channel 4 */
+
+/*******************  Bit definition for ADC_HTR register  ********************/
+#define  ADC_HTR_HT                          ((uint16_t)0x0FFF)            /*!< Analog watchdog high threshold */
+
+/*******************  Bit definition for ADC_LTR register  ********************/
+#define  ADC_LTR_LT                          ((uint16_t)0x0FFF)            /*!< Analog watchdog low threshold */
+
+/*******************  Bit definition for ADC_SQR1 register  *******************/
+#define  ADC_SQR1_SQ13                       ((uint32_t)0x0000001F)        /*!< SQ13[4:0] bits (13th conversion in regular sequence) */
+#define  ADC_SQR1_SQ13_0                     ((uint32_t)0x00000001)        /*!< Bit 0 */
+#define  ADC_SQR1_SQ13_1                     ((uint32_t)0x00000002)        /*!< Bit 1 */
+#define  ADC_SQR1_SQ13_2                     ((uint32_t)0x00000004)        /*!< Bit 2 */
+#define  ADC_SQR1_SQ13_3                     ((uint32_t)0x00000008)        /*!< Bit 3 */
+#define  ADC_SQR1_SQ13_4                     ((uint32_t)0x00000010)        /*!< Bit 4 */
+
+#define  ADC_SQR1_SQ14                       ((uint32_t)0x000003E0)        /*!< SQ14[4:0] bits (14th conversion in regular sequence) */
+#define  ADC_SQR1_SQ14_0                     ((uint32_t)0x00000020)        /*!< Bit 0 */
+#define  ADC_SQR1_SQ14_1                     ((uint32_t)0x00000040)        /*!< Bit 1 */
+#define  ADC_SQR1_SQ14_2                     ((uint32_t)0x00000080)        /*!< Bit 2 */
+#define  ADC_SQR1_SQ14_3                     ((uint32_t)0x00000100)        /*!< Bit 3 */
+#define  ADC_SQR1_SQ14_4                     ((uint32_t)0x00000200)        /*!< Bit 4 */
+
+#define  ADC_SQR1_SQ15                       ((uint32_t)0x00007C00)        /*!< SQ15[4:0] bits (15th conversion in regular sequence) */
+#define  ADC_SQR1_SQ15_0                     ((uint32_t)0x00000400)        /*!< Bit 0 */
+#define  ADC_SQR1_SQ15_1                     ((uint32_t)0x00000800)        /*!< Bit 1 */
+#define  ADC_SQR1_SQ15_2                     ((uint32_t)0x00001000)        /*!< Bit 2 */
+#define  ADC_SQR1_SQ15_3                     ((uint32_t)0x00002000)        /*!< Bit 3 */
+#define  ADC_SQR1_SQ15_4                     ((uint32_t)0x00004000)        /*!< Bit 4 */
+
+#define  ADC_SQR1_SQ16                       ((uint32_t)0x000F8000)        /*!< SQ16[4:0] bits (16th conversion in regular sequence) */
+#define  ADC_SQR1_SQ16_0                     ((uint32_t)0x00008000)        /*!< Bit 0 */
+#define  ADC_SQR1_SQ16_1                     ((uint32_t)0x00010000)        /*!< Bit 1 */
+#define  ADC_SQR1_SQ16_2                     ((uint32_t)0x00020000)        /*!< Bit 2 */
+#define  ADC_SQR1_SQ16_3                     ((uint32_t)0x00040000)        /*!< Bit 3 */
+#define  ADC_SQR1_SQ16_4                     ((uint32_t)0x00080000)        /*!< Bit 4 */
+
+#define  ADC_SQR1_L                          ((uint32_t)0x00F00000)        /*!< L[3:0] bits (Regular channel sequence length) */
+#define  ADC_SQR1_L_0                        ((uint32_t)0x00100000)        /*!< Bit 0 */
+#define  ADC_SQR1_L_1                        ((uint32_t)0x00200000)        /*!< Bit 1 */
+#define  ADC_SQR1_L_2                        ((uint32_t)0x00400000)        /*!< Bit 2 */
+#define  ADC_SQR1_L_3                        ((uint32_t)0x00800000)        /*!< Bit 3 */
+
+/*******************  Bit definition for ADC_SQR2 register  *******************/
+#define  ADC_SQR2_SQ7                        ((uint32_t)0x0000001F)        /*!< SQ7[4:0] bits (7th conversion in regular sequence) */
+#define  ADC_SQR2_SQ7_0                      ((uint32_t)0x00000001)        /*!< Bit 0 */
+#define  ADC_SQR2_SQ7_1                      ((uint32_t)0x00000002)        /*!< Bit 1 */
+#define  ADC_SQR2_SQ7_2                      ((uint32_t)0x00000004)        /*!< Bit 2 */
+#define  ADC_SQR2_SQ7_3                      ((uint32_t)0x00000008)        /*!< Bit 3 */
+#define  ADC_SQR2_SQ7_4                      ((uint32_t)0x00000010)        /*!< Bit 4 */
+
+#define  ADC_SQR2_SQ8                        ((uint32_t)0x000003E0)        /*!< SQ8[4:0] bits (8th conversion in regular sequence) */
+#define  ADC_SQR2_SQ8_0                      ((uint32_t)0x00000020)        /*!< Bit 0 */
+#define  ADC_SQR2_SQ8_1                      ((uint32_t)0x00000040)        /*!< Bit 1 */
+#define  ADC_SQR2_SQ8_2                      ((uint32_t)0x00000080)        /*!< Bit 2 */
+#define  ADC_SQR2_SQ8_3                      ((uint32_t)0x00000100)        /*!< Bit 3 */
+#define  ADC_SQR2_SQ8_4                      ((uint32_t)0x00000200)        /*!< Bit 4 */
+
+#define  ADC_SQR2_SQ9                        ((uint32_t)0x00007C00)        /*!< SQ9[4:0] bits (9th conversion in regular sequence) */
+#define  ADC_SQR2_SQ9_0                      ((uint32_t)0x00000400)        /*!< Bit 0 */
+#define  ADC_SQR2_SQ9_1                      ((uint32_t)0x00000800)        /*!< Bit 1 */
+#define  ADC_SQR2_SQ9_2                      ((uint32_t)0x00001000)        /*!< Bit 2 */
+#define  ADC_SQR2_SQ9_3                      ((uint32_t)0x00002000)        /*!< Bit 3 */
+#define  ADC_SQR2_SQ9_4                      ((uint32_t)0x00004000)        /*!< Bit 4 */
+
+#define  ADC_SQR2_SQ10                       ((uint32_t)0x000F8000)        /*!< SQ10[4:0] bits (10th conversion in regular sequence) */
+#define  ADC_SQR2_SQ10_0                     ((uint32_t)0x00008000)        /*!< Bit 0 */
+#define  ADC_SQR2_SQ10_1                     ((uint32_t)0x00010000)        /*!< Bit 1 */
+#define  ADC_SQR2_SQ10_2                     ((uint32_t)0x00020000)        /*!< Bit 2 */
+#define  ADC_SQR2_SQ10_3                     ((uint32_t)0x00040000)        /*!< Bit 3 */
+#define  ADC_SQR2_SQ10_4                     ((uint32_t)0x00080000)        /*!< Bit 4 */
+
+#define  ADC_SQR2_SQ11                       ((uint32_t)0x01F00000)        /*!< SQ11[4:0] bits (11th conversion in regular sequence) */
+#define  ADC_SQR2_SQ11_0                     ((uint32_t)0x00100000)        /*!< Bit 0 */
+#define  ADC_SQR2_SQ11_1                     ((uint32_t)0x00200000)        /*!< Bit 1 */
+#define  ADC_SQR2_SQ11_2                     ((uint32_t)0x00400000)        /*!< Bit 2 */
+#define  ADC_SQR2_SQ11_3                     ((uint32_t)0x00800000)        /*!< Bit 3 */
+#define  ADC_SQR2_SQ11_4                     ((uint32_t)0x01000000)        /*!< Bit 4 */
+
+#define  ADC_SQR2_SQ12                       ((uint32_t)0x3E000000)        /*!< SQ12[4:0] bits (12th conversion in regular sequence) */
+#define  ADC_SQR2_SQ12_0                     ((uint32_t)0x02000000)        /*!< Bit 0 */
+#define  ADC_SQR2_SQ12_1                     ((uint32_t)0x04000000)        /*!< Bit 1 */
+#define  ADC_SQR2_SQ12_2                     ((uint32_t)0x08000000)        /*!< Bit 2 */
+#define  ADC_SQR2_SQ12_3                     ((uint32_t)0x10000000)        /*!< Bit 3 */
+#define  ADC_SQR2_SQ12_4                     ((uint32_t)0x20000000)        /*!< Bit 4 */
+
+/*******************  Bit definition for ADC_SQR3 register  *******************/
+#define  ADC_SQR3_SQ1                        ((uint32_t)0x0000001F)        /*!< SQ1[4:0] bits (1st conversion in regular sequence) */
+#define  ADC_SQR3_SQ1_0                      ((uint32_t)0x00000001)        /*!< Bit 0 */
+#define  ADC_SQR3_SQ1_1                      ((uint32_t)0x00000002)        /*!< Bit 1 */
+#define  ADC_SQR3_SQ1_2                      ((uint32_t)0x00000004)        /*!< Bit 2 */
+#define  ADC_SQR3_SQ1_3                      ((uint32_t)0x00000008)        /*!< Bit 3 */
+#define  ADC_SQR3_SQ1_4                      ((uint32_t)0x00000010)        /*!< Bit 4 */
+
+#define  ADC_SQR3_SQ2                        ((uint32_t)0x000003E0)        /*!< SQ2[4:0] bits (2nd conversion in regular sequence) */
+#define  ADC_SQR3_SQ2_0                      ((uint32_t)0x00000020)        /*!< Bit 0 */
+#define  ADC_SQR3_SQ2_1                      ((uint32_t)0x00000040)        /*!< Bit 1 */
+#define  ADC_SQR3_SQ2_2                      ((uint32_t)0x00000080)        /*!< Bit 2 */
+#define  ADC_SQR3_SQ2_3                      ((uint32_t)0x00000100)        /*!< Bit 3 */
+#define  ADC_SQR3_SQ2_4                      ((uint32_t)0x00000200)        /*!< Bit 4 */
+
+#define  ADC_SQR3_SQ3                        ((uint32_t)0x00007C00)        /*!< SQ3[4:0] bits (3rd conversion in regular sequence) */
+#define  ADC_SQR3_SQ3_0                      ((uint32_t)0x00000400)        /*!< Bit 0 */
+#define  ADC_SQR3_SQ3_1                      ((uint32_t)0x00000800)        /*!< Bit 1 */
+#define  ADC_SQR3_SQ3_2                      ((uint32_t)0x00001000)        /*!< Bit 2 */
+#define  ADC_SQR3_SQ3_3                      ((uint32_t)0x00002000)        /*!< Bit 3 */
+#define  ADC_SQR3_SQ3_4                      ((uint32_t)0x00004000)        /*!< Bit 4 */
+
+#define  ADC_SQR3_SQ4                        ((uint32_t)0x000F8000)        /*!< SQ4[4:0] bits (4th conversion in regular sequence) */
+#define  ADC_SQR3_SQ4_0                      ((uint32_t)0x00008000)        /*!< Bit 0 */
+#define  ADC_SQR3_SQ4_1                      ((uint32_t)0x00010000)        /*!< Bit 1 */
+#define  ADC_SQR3_SQ4_2                      ((uint32_t)0x00020000)        /*!< Bit 2 */
+#define  ADC_SQR3_SQ4_3                      ((uint32_t)0x00040000)        /*!< Bit 3 */
+#define  ADC_SQR3_SQ4_4                      ((uint32_t)0x00080000)        /*!< Bit 4 */
+
+#define  ADC_SQR3_SQ5                        ((uint32_t)0x01F00000)        /*!< SQ5[4:0] bits (5th conversion in regular sequence) */
+#define  ADC_SQR3_SQ5_0                      ((uint32_t)0x00100000)        /*!< Bit 0 */
+#define  ADC_SQR3_SQ5_1                      ((uint32_t)0x00200000)        /*!< Bit 1 */
+#define  ADC_SQR3_SQ5_2                      ((uint32_t)0x00400000)        /*!< Bit 2 */
+#define  ADC_SQR3_SQ5_3                      ((uint32_t)0x00800000)        /*!< Bit 3 */
+#define  ADC_SQR3_SQ5_4                      ((uint32_t)0x01000000)        /*!< Bit 4 */
+
+#define  ADC_SQR3_SQ6                        ((uint32_t)0x3E000000)        /*!< SQ6[4:0] bits (6th conversion in regular sequence) */
+#define  ADC_SQR3_SQ6_0                      ((uint32_t)0x02000000)        /*!< Bit 0 */
+#define  ADC_SQR3_SQ6_1                      ((uint32_t)0x04000000)        /*!< Bit 1 */
+#define  ADC_SQR3_SQ6_2                      ((uint32_t)0x08000000)        /*!< Bit 2 */
+#define  ADC_SQR3_SQ6_3                      ((uint32_t)0x10000000)        /*!< Bit 3 */
+#define  ADC_SQR3_SQ6_4                      ((uint32_t)0x20000000)        /*!< Bit 4 */
+
+/*******************  Bit definition for ADC_JSQR register  *******************/
+#define  ADC_JSQR_JSQ1                       ((uint32_t)0x0000001F)        /*!< JSQ1[4:0] bits (1st conversion in injected sequence) */  
+#define  ADC_JSQR_JSQ1_0                     ((uint32_t)0x00000001)        /*!< Bit 0 */
+#define  ADC_JSQR_JSQ1_1                     ((uint32_t)0x00000002)        /*!< Bit 1 */
+#define  ADC_JSQR_JSQ1_2                     ((uint32_t)0x00000004)        /*!< Bit 2 */
+#define  ADC_JSQR_JSQ1_3                     ((uint32_t)0x00000008)        /*!< Bit 3 */
+#define  ADC_JSQR_JSQ1_4                     ((uint32_t)0x00000010)        /*!< Bit 4 */
+
+#define  ADC_JSQR_JSQ2                       ((uint32_t)0x000003E0)        /*!< JSQ2[4:0] bits (2nd conversion in injected sequence) */
+#define  ADC_JSQR_JSQ2_0                     ((uint32_t)0x00000020)        /*!< Bit 0 */
+#define  ADC_JSQR_JSQ2_1                     ((uint32_t)0x00000040)        /*!< Bit 1 */
+#define  ADC_JSQR_JSQ2_2                     ((uint32_t)0x00000080)        /*!< Bit 2 */
+#define  ADC_JSQR_JSQ2_3                     ((uint32_t)0x00000100)        /*!< Bit 3 */
+#define  ADC_JSQR_JSQ2_4                     ((uint32_t)0x00000200)        /*!< Bit 4 */
+
+#define  ADC_JSQR_JSQ3                       ((uint32_t)0x00007C00)        /*!< JSQ3[4:0] bits (3rd conversion in injected sequence) */
+#define  ADC_JSQR_JSQ3_0                     ((uint32_t)0x00000400)        /*!< Bit 0 */
+#define  ADC_JSQR_JSQ3_1                     ((uint32_t)0x00000800)        /*!< Bit 1 */
+#define  ADC_JSQR_JSQ3_2                     ((uint32_t)0x00001000)        /*!< Bit 2 */
+#define  ADC_JSQR_JSQ3_3                     ((uint32_t)0x00002000)        /*!< Bit 3 */
+#define  ADC_JSQR_JSQ3_4                     ((uint32_t)0x00004000)        /*!< Bit 4 */
+
+#define  ADC_JSQR_JSQ4                       ((uint32_t)0x000F8000)        /*!< JSQ4[4:0] bits (4th conversion in injected sequence) */
+#define  ADC_JSQR_JSQ4_0                     ((uint32_t)0x00008000)        /*!< Bit 0 */
+#define  ADC_JSQR_JSQ4_1                     ((uint32_t)0x00010000)        /*!< Bit 1 */
+#define  ADC_JSQR_JSQ4_2                     ((uint32_t)0x00020000)        /*!< Bit 2 */
+#define  ADC_JSQR_JSQ4_3                     ((uint32_t)0x00040000)        /*!< Bit 3 */
+#define  ADC_JSQR_JSQ4_4                     ((uint32_t)0x00080000)        /*!< Bit 4 */
+
+#define  ADC_JSQR_JL                         ((uint32_t)0x00300000)        /*!< JL[1:0] bits (Injected Sequence length) */
+#define  ADC_JSQR_JL_0                       ((uint32_t)0x00100000)        /*!< Bit 0 */
+#define  ADC_JSQR_JL_1                       ((uint32_t)0x00200000)        /*!< Bit 1 */
+
+/*******************  Bit definition for ADC_JDR1 register  *******************/
+#define  ADC_JDR1_JDATA                      ((uint16_t)0xFFFF)            /*!< Injected data */
+
+/*******************  Bit definition for ADC_JDR2 register  *******************/
+#define  ADC_JDR2_JDATA                      ((uint16_t)0xFFFF)            /*!< Injected data */
+
+/*******************  Bit definition for ADC_JDR3 register  *******************/
+#define  ADC_JDR3_JDATA                      ((uint16_t)0xFFFF)            /*!< Injected data */
+
+/*******************  Bit definition for ADC_JDR4 register  *******************/
+#define  ADC_JDR4_JDATA                      ((uint16_t)0xFFFF)            /*!< Injected data */
+
+/********************  Bit definition for ADC_DR register  ********************/
+#define  ADC_DR_DATA                         ((uint32_t)0x0000FFFF)        /*!< Regular data */
+#define  ADC_DR_ADC2DATA                     ((uint32_t)0xFFFF0000)        /*!< ADC2 data */
+
+/******************************************************************************/
+/*                                                                            */
+/*                      Digital to Analog Converter                           */
+/*                                                                            */
+/******************************************************************************/
+
+/********************  Bit definition for DAC_CR register  ********************/
+#define  DAC_CR_EN1                          ((uint32_t)0x00000001)        /*!< DAC channel1 enable */
+#define  DAC_CR_BOFF1                        ((uint32_t)0x00000002)        /*!< DAC channel1 output buffer disable */
+#define  DAC_CR_TEN1                         ((uint32_t)0x00000004)        /*!< DAC channel1 Trigger enable */
+
+#define  DAC_CR_TSEL1                        ((uint32_t)0x00000038)        /*!< TSEL1[2:0] (DAC channel1 Trigger selection) */
+#define  DAC_CR_TSEL1_0                      ((uint32_t)0x00000008)        /*!< Bit 0 */
+#define  DAC_CR_TSEL1_1                      ((uint32_t)0x00000010)        /*!< Bit 1 */
+#define  DAC_CR_TSEL1_2                      ((uint32_t)0x00000020)        /*!< Bit 2 */
+
+#define  DAC_CR_WAVE1                        ((uint32_t)0x000000C0)        /*!< WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */
+#define  DAC_CR_WAVE1_0                      ((uint32_t)0x00000040)        /*!< Bit 0 */
+#define  DAC_CR_WAVE1_1                      ((uint32_t)0x00000080)        /*!< Bit 1 */
+
+#define  DAC_CR_MAMP1                        ((uint32_t)0x00000F00)        /*!< MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
+#define  DAC_CR_MAMP1_0                      ((uint32_t)0x00000100)        /*!< Bit 0 */
+#define  DAC_CR_MAMP1_1                      ((uint32_t)0x00000200)        /*!< Bit 1 */
+#define  DAC_CR_MAMP1_2                      ((uint32_t)0x00000400)        /*!< Bit 2 */
+#define  DAC_CR_MAMP1_3                      ((uint32_t)0x00000800)        /*!< Bit 3 */
+
+#define  DAC_CR_DMAEN1                       ((uint32_t)0x00001000)        /*!< DAC channel1 DMA enable */
+#define  DAC_CR_EN2                          ((uint32_t)0x00010000)        /*!< DAC channel2 enable */
+#define  DAC_CR_BOFF2                        ((uint32_t)0x00020000)        /*!< DAC channel2 output buffer disable */
+#define  DAC_CR_TEN2                         ((uint32_t)0x00040000)        /*!< DAC channel2 Trigger enable */
+
+#define  DAC_CR_TSEL2                        ((uint32_t)0x00380000)        /*!< TSEL2[2:0] (DAC channel2 Trigger selection) */
+#define  DAC_CR_TSEL2_0                      ((uint32_t)0x00080000)        /*!< Bit 0 */
+#define  DAC_CR_TSEL2_1                      ((uint32_t)0x00100000)        /*!< Bit 1 */
+#define  DAC_CR_TSEL2_2                      ((uint32_t)0x00200000)        /*!< Bit 2 */
+
+#define  DAC_CR_WAVE2                        ((uint32_t)0x00C00000)        /*!< WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */
+#define  DAC_CR_WAVE2_0                      ((uint32_t)0x00400000)        /*!< Bit 0 */
+#define  DAC_CR_WAVE2_1                      ((uint32_t)0x00800000)        /*!< Bit 1 */
+
+#define  DAC_CR_MAMP2                        ((uint32_t)0x0F000000)        /*!< MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */
+#define  DAC_CR_MAMP2_0                      ((uint32_t)0x01000000)        /*!< Bit 0 */
+#define  DAC_CR_MAMP2_1                      ((uint32_t)0x02000000)        /*!< Bit 1 */
+#define  DAC_CR_MAMP2_2                      ((uint32_t)0x04000000)        /*!< Bit 2 */
+#define  DAC_CR_MAMP2_3                      ((uint32_t)0x08000000)        /*!< Bit 3 */
+
+#define  DAC_CR_DMAEN2                       ((uint32_t)0x10000000)        /*!< DAC channel2 DMA enabled */
+
+/*****************  Bit definition for DAC_SWTRIGR register  ******************/
+#define  DAC_SWTRIGR_SWTRIG1                 ((uint8_t)0x01)               /*!< DAC channel1 software trigger */
+#define  DAC_SWTRIGR_SWTRIG2                 ((uint8_t)0x02)               /*!< DAC channel2 software trigger */
+
+/*****************  Bit definition for DAC_DHR12R1 register  ******************/
+#define  DAC_DHR12R1_DACC1DHR                ((uint16_t)0x0FFF)            /*!< DAC channel1 12-bit Right aligned data */
+
+/*****************  Bit definition for DAC_DHR12L1 register  ******************/
+#define  DAC_DHR12L1_DACC1DHR                ((uint16_t)0xFFF0)            /*!< DAC channel1 12-bit Left aligned data */
+
+/******************  Bit definition for DAC_DHR8R1 register  ******************/
+#define  DAC_DHR8R1_DACC1DHR                 ((uint8_t)0xFF)               /*!< DAC channel1 8-bit Right aligned data */
+
+/*****************  Bit definition for DAC_DHR12R2 register  ******************/
+#define  DAC_DHR12R2_DACC2DHR                ((uint16_t)0x0FFF)            /*!< DAC channel2 12-bit Right aligned data */
+
+/*****************  Bit definition for DAC_DHR12L2 register  ******************/
+#define  DAC_DHR12L2_DACC2DHR                ((uint16_t)0xFFF0)            /*!< DAC channel2 12-bit Left aligned data */
+
+/******************  Bit definition for DAC_DHR8R2 register  ******************/
+#define  DAC_DHR8R2_DACC2DHR                 ((uint8_t)0xFF)               /*!< DAC channel2 8-bit Right aligned data */
+
+/*****************  Bit definition for DAC_DHR12RD register  ******************/
+#define  DAC_DHR12RD_DACC1DHR                ((uint32_t)0x00000FFF)        /*!< DAC channel1 12-bit Right aligned data */
+#define  DAC_DHR12RD_DACC2DHR                ((uint32_t)0x0FFF0000)        /*!< DAC channel2 12-bit Right aligned data */
+
+/*****************  Bit definition for DAC_DHR12LD register  ******************/
+#define  DAC_DHR12LD_DACC1DHR                ((uint32_t)0x0000FFF0)        /*!< DAC channel1 12-bit Left aligned data */
+#define  DAC_DHR12LD_DACC2DHR                ((uint32_t)0xFFF00000)        /*!< DAC channel2 12-bit Left aligned data */
+
+/******************  Bit definition for DAC_DHR8RD register  ******************/
+#define  DAC_DHR8RD_DACC1DHR                 ((uint16_t)0x00FF)            /*!< DAC channel1 8-bit Right aligned data */
+#define  DAC_DHR8RD_DACC2DHR                 ((uint16_t)0xFF00)            /*!< DAC channel2 8-bit Right aligned data */
+
+/*******************  Bit definition for DAC_DOR1 register  *******************/
+#define  DAC_DOR1_DACC1DOR                   ((uint16_t)0x0FFF)            /*!< DAC channel1 data output */
+
+/*******************  Bit definition for DAC_DOR2 register  *******************/
+#define  DAC_DOR2_DACC2DOR                   ((uint16_t)0x0FFF)            /*!< DAC channel2 data output */
+
+/********************  Bit definition for DAC_SR register  ********************/
+#define  DAC_SR_DMAUDR1                      ((uint32_t)0x00002000)        /*!< DAC channel1 DMA underrun flag */
+#define  DAC_SR_DMAUDR2                      ((uint32_t)0x20000000)        /*!< DAC channel2 DMA underrun flag */
+
+/******************************************************************************/
+/*                                                                            */
+/*                                    CEC                                     */
+/*                                                                            */
+/******************************************************************************/
+/********************  Bit definition for CEC_CFGR register  ******************/
+#define  CEC_CFGR_PE              ((uint16_t)0x0001)     /*!<  Peripheral Enable */
+#define  CEC_CFGR_IE              ((uint16_t)0x0002)     /*!<  Interrupt Enable */
+#define  CEC_CFGR_BTEM            ((uint16_t)0x0004)     /*!<  Bit Timing Error Mode */
+#define  CEC_CFGR_BPEM            ((uint16_t)0x0008)     /*!<  Bit Period Error Mode */
+
+/********************  Bit definition for CEC_OAR register  ******************/
+#define  CEC_OAR_OA               ((uint16_t)0x000F)     /*!<  OA[3:0]: Own Address */
+#define  CEC_OAR_OA_0             ((uint16_t)0x0001)     /*!<  Bit 0 */
+#define  CEC_OAR_OA_1             ((uint16_t)0x0002)     /*!<  Bit 1 */
+#define  CEC_OAR_OA_2             ((uint16_t)0x0004)     /*!<  Bit 2 */
+#define  CEC_OAR_OA_3             ((uint16_t)0x0008)     /*!<  Bit 3 */
+
+/********************  Bit definition for CEC_PRES register  ******************/
+#define  CEC_PRES_PRES            ((uint16_t)0x3FFF)   /*!<  Prescaler Counter Value */
+
+/********************  Bit definition for CEC_ESR register  ******************/
+#define  CEC_ESR_BTE              ((uint16_t)0x0001)     /*!<  Bit Timing Error */
+#define  CEC_ESR_BPE              ((uint16_t)0x0002)     /*!<  Bit Period Error */
+#define  CEC_ESR_RBTFE            ((uint16_t)0x0004)     /*!<  Rx Block Transfer Finished Error */
+#define  CEC_ESR_SBE              ((uint16_t)0x0008)     /*!<  Start Bit Error */
+#define  CEC_ESR_ACKE             ((uint16_t)0x0010)     /*!<  Block Acknowledge Error */
+#define  CEC_ESR_LINE             ((uint16_t)0x0020)     /*!<  Line Error */
+#define  CEC_ESR_TBTFE            ((uint16_t)0x0040)     /*!<  Tx Block Transfer Finished Error */
+
+/********************  Bit definition for CEC_CSR register  ******************/
+#define  CEC_CSR_TSOM             ((uint16_t)0x0001)     /*!<  Tx Start Of Message */
+#define  CEC_CSR_TEOM             ((uint16_t)0x0002)     /*!<  Tx End Of Message */
+#define  CEC_CSR_TERR             ((uint16_t)0x0004)     /*!<  Tx Error */
+#define  CEC_CSR_TBTRF            ((uint16_t)0x0008)     /*!<  Tx Byte Transfer Request or Block Transfer Finished */
+#define  CEC_CSR_RSOM             ((uint16_t)0x0010)     /*!<  Rx Start Of Message */
+#define  CEC_CSR_REOM             ((uint16_t)0x0020)     /*!<  Rx End Of Message */
+#define  CEC_CSR_RERR             ((uint16_t)0x0040)     /*!<  Rx Error */
+#define  CEC_CSR_RBTF             ((uint16_t)0x0080)     /*!<  Rx Block Transfer Finished */
+
+/********************  Bit definition for CEC_TXD register  ******************/
+#define  CEC_TXD_TXD              ((uint16_t)0x00FF)     /*!<  Tx Data register */
+
+/********************  Bit definition for CEC_RXD register  ******************/
+#define  CEC_RXD_RXD              ((uint16_t)0x00FF)     /*!<  Rx Data register */
+
+/******************************************************************************/
+/*                                                                            */
+/*                                    TIM                                     */
+/*                                                                            */
+/******************************************************************************/
+
+/*******************  Bit definition for TIM_CR1 register  ********************/
+#define  TIM_CR1_CEN                         ((uint16_t)0x0001)            /*!< Counter enable */
+#define  TIM_CR1_UDIS                        ((uint16_t)0x0002)            /*!< Update disable */
+#define  TIM_CR1_URS                         ((uint16_t)0x0004)            /*!< Update request source */
+#define  TIM_CR1_OPM                         ((uint16_t)0x0008)            /*!< One pulse mode */
+#define  TIM_CR1_DIR                         ((uint16_t)0x0010)            /*!< Direction */
+
+#define  TIM_CR1_CMS                         ((uint16_t)0x0060)            /*!< CMS[1:0] bits (Center-aligned mode selection) */
+#define  TIM_CR1_CMS_0                       ((uint16_t)0x0020)            /*!< Bit 0 */
+#define  TIM_CR1_CMS_1                       ((uint16_t)0x0040)            /*!< Bit 1 */
+
+#define  TIM_CR1_ARPE                        ((uint16_t)0x0080)            /*!< Auto-reload preload enable */
+
+#define  TIM_CR1_CKD                         ((uint16_t)0x0300)            /*!< CKD[1:0] bits (clock division) */
+#define  TIM_CR1_CKD_0                       ((uint16_t)0x0100)            /*!< Bit 0 */
+#define  TIM_CR1_CKD_1                       ((uint16_t)0x0200)            /*!< Bit 1 */
+
+/*******************  Bit definition for TIM_CR2 register  ********************/
+#define  TIM_CR2_CCPC                        ((uint16_t)0x0001)            /*!< Capture/Compare Preloaded Control */
+#define  TIM_CR2_CCUS                        ((uint16_t)0x0004)            /*!< Capture/Compare Control Update Selection */
+#define  TIM_CR2_CCDS                        ((uint16_t)0x0008)            /*!< Capture/Compare DMA Selection */
+
+#define  TIM_CR2_MMS                         ((uint16_t)0x0070)            /*!< MMS[2:0] bits (Master Mode Selection) */
+#define  TIM_CR2_MMS_0                       ((uint16_t)0x0010)            /*!< Bit 0 */
+#define  TIM_CR2_MMS_1                       ((uint16_t)0x0020)            /*!< Bit 1 */
+#define  TIM_CR2_MMS_2                       ((uint16_t)0x0040)            /*!< Bit 2 */
+
+#define  TIM_CR2_TI1S                        ((uint16_t)0x0080)            /*!< TI1 Selection */
+#define  TIM_CR2_OIS1                        ((uint16_t)0x0100)            /*!< Output Idle state 1 (OC1 output) */
+#define  TIM_CR2_OIS1N                       ((uint16_t)0x0200)            /*!< Output Idle state 1 (OC1N output) */
+#define  TIM_CR2_OIS2                        ((uint16_t)0x0400)            /*!< Output Idle state 2 (OC2 output) */
+#define  TIM_CR2_OIS2N                       ((uint16_t)0x0800)            /*!< Output Idle state 2 (OC2N output) */
+#define  TIM_CR2_OIS3                        ((uint16_t)0x1000)            /*!< Output Idle state 3 (OC3 output) */
+#define  TIM_CR2_OIS3N                       ((uint16_t)0x2000)            /*!< Output Idle state 3 (OC3N output) */
+#define  TIM_CR2_OIS4                        ((uint16_t)0x4000)            /*!< Output Idle state 4 (OC4 output) */
+
+/*******************  Bit definition for TIM_SMCR register  *******************/
+#define  TIM_SMCR_SMS                        ((uint16_t)0x0007)            /*!< SMS[2:0] bits (Slave mode selection) */
+#define  TIM_SMCR_SMS_0                      ((uint16_t)0x0001)            /*!< Bit 0 */
+#define  TIM_SMCR_SMS_1                      ((uint16_t)0x0002)            /*!< Bit 1 */
+#define  TIM_SMCR_SMS_2                      ((uint16_t)0x0004)            /*!< Bit 2 */
+
+#define  TIM_SMCR_TS                         ((uint16_t)0x0070)            /*!< TS[2:0] bits (Trigger selection) */
+#define  TIM_SMCR_TS_0                       ((uint16_t)0x0010)            /*!< Bit 0 */
+#define  TIM_SMCR_TS_1                       ((uint16_t)0x0020)            /*!< Bit 1 */
+#define  TIM_SMCR_TS_2                       ((uint16_t)0x0040)            /*!< Bit 2 */
+
+#define  TIM_SMCR_MSM                        ((uint16_t)0x0080)            /*!< Master/slave mode */
+
+#define  TIM_SMCR_ETF                        ((uint16_t)0x0F00)            /*!< ETF[3:0] bits (External trigger filter) */
+#define  TIM_SMCR_ETF_0                      ((uint16_t)0x0100)            /*!< Bit 0 */
+#define  TIM_SMCR_ETF_1                      ((uint16_t)0x0200)            /*!< Bit 1 */
+#define  TIM_SMCR_ETF_2                      ((uint16_t)0x0400)            /*!< Bit 2 */
+#define  TIM_SMCR_ETF_3                      ((uint16_t)0x0800)            /*!< Bit 3 */
+
+#define  TIM_SMCR_ETPS                       ((uint16_t)0x3000)            /*!< ETPS[1:0] bits (External trigger prescaler) */
+#define  TIM_SMCR_ETPS_0                     ((uint16_t)0x1000)            /*!< Bit 0 */
+#define  TIM_SMCR_ETPS_1                     ((uint16_t)0x2000)            /*!< Bit 1 */
+
+#define  TIM_SMCR_ECE                        ((uint16_t)0x4000)            /*!< External clock enable */
+#define  TIM_SMCR_ETP                        ((uint16_t)0x8000)            /*!< External trigger polarity */
+
+/*******************  Bit definition for TIM_DIER register  *******************/
+#define  TIM_DIER_UIE                        ((uint16_t)0x0001)            /*!< Update interrupt enable */
+#define  TIM_DIER_CC1IE                      ((uint16_t)0x0002)            /*!< Capture/Compare 1 interrupt enable */
+#define  TIM_DIER_CC2IE                      ((uint16_t)0x0004)            /*!< Capture/Compare 2 interrupt enable */
+#define  TIM_DIER_CC3IE                      ((uint16_t)0x0008)            /*!< Capture/Compare 3 interrupt enable */
+#define  TIM_DIER_CC4IE                      ((uint16_t)0x0010)            /*!< Capture/Compare 4 interrupt enable */
+#define  TIM_DIER_COMIE                      ((uint16_t)0x0020)            /*!< COM interrupt enable */
+#define  TIM_DIER_TIE                        ((uint16_t)0x0040)            /*!< Trigger interrupt enable */
+#define  TIM_DIER_BIE                        ((uint16_t)0x0080)            /*!< Break interrupt enable */
+#define  TIM_DIER_UDE                        ((uint16_t)0x0100)            /*!< Update DMA request enable */
+#define  TIM_DIER_CC1DE                      ((uint16_t)0x0200)            /*!< Capture/Compare 1 DMA request enable */
+#define  TIM_DIER_CC2DE                      ((uint16_t)0x0400)            /*!< Capture/Compare 2 DMA request enable */
+#define  TIM_DIER_CC3DE                      ((uint16_t)0x0800)            /*!< Capture/Compare 3 DMA request enable */
+#define  TIM_DIER_CC4DE                      ((uint16_t)0x1000)            /*!< Capture/Compare 4 DMA request enable */
+#define  TIM_DIER_COMDE                      ((uint16_t)0x2000)            /*!< COM DMA request enable */
+#define  TIM_DIER_TDE                        ((uint16_t)0x4000)            /*!< Trigger DMA request enable */
+
+/********************  Bit definition for TIM_SR register  ********************/
+#define  TIM_SR_UIF                          ((uint16_t)0x0001)            /*!< Update interrupt Flag */
+#define  TIM_SR_CC1IF                        ((uint16_t)0x0002)            /*!< Capture/Compare 1 interrupt Flag */
+#define  TIM_SR_CC2IF                        ((uint16_t)0x0004)            /*!< Capture/Compare 2 interrupt Flag */
+#define  TIM_SR_CC3IF                        ((uint16_t)0x0008)            /*!< Capture/Compare 3 interrupt Flag */
+#define  TIM_SR_CC4IF                        ((uint16_t)0x0010)            /*!< Capture/Compare 4 interrupt Flag */
+#define  TIM_SR_COMIF                        ((uint16_t)0x0020)            /*!< COM interrupt Flag */
+#define  TIM_SR_TIF                          ((uint16_t)0x0040)            /*!< Trigger interrupt Flag */
+#define  TIM_SR_BIF                          ((uint16_t)0x0080)            /*!< Break interrupt Flag */
+#define  TIM_SR_CC1OF                        ((uint16_t)0x0200)            /*!< Capture/Compare 1 Overcapture Flag */
+#define  TIM_SR_CC2OF                        ((uint16_t)0x0400)            /*!< Capture/Compare 2 Overcapture Flag */
+#define  TIM_SR_CC3OF                        ((uint16_t)0x0800)            /*!< Capture/Compare 3 Overcapture Flag */
+#define  TIM_SR_CC4OF                        ((uint16_t)0x1000)            /*!< Capture/Compare 4 Overcapture Flag */
+
+/*******************  Bit definition for TIM_EGR register  ********************/
+#define  TIM_EGR_UG                          ((uint8_t)0x01)               /*!< Update Generation */
+#define  TIM_EGR_CC1G                        ((uint8_t)0x02)               /*!< Capture/Compare 1 Generation */
+#define  TIM_EGR_CC2G                        ((uint8_t)0x04)               /*!< Capture/Compare 2 Generation */
+#define  TIM_EGR_CC3G                        ((uint8_t)0x08)               /*!< Capture/Compare 3 Generation */
+#define  TIM_EGR_CC4G                        ((uint8_t)0x10)               /*!< Capture/Compare 4 Generation */
+#define  TIM_EGR_COMG                        ((uint8_t)0x20)               /*!< Capture/Compare Control Update Generation */
+#define  TIM_EGR_TG                          ((uint8_t)0x40)               /*!< Trigger Generation */
+#define  TIM_EGR_BG                          ((uint8_t)0x80)               /*!< Break Generation */
+
+/******************  Bit definition for TIM_CCMR1 register  *******************/
+#define  TIM_CCMR1_CC1S                      ((uint16_t)0x0003)            /*!< CC1S[1:0] bits (Capture/Compare 1 Selection) */
+#define  TIM_CCMR1_CC1S_0                    ((uint16_t)0x0001)            /*!< Bit 0 */
+#define  TIM_CCMR1_CC1S_1                    ((uint16_t)0x0002)            /*!< Bit 1 */
+
+#define  TIM_CCMR1_OC1FE                     ((uint16_t)0x0004)            /*!< Output Compare 1 Fast enable */
+#define  TIM_CCMR1_OC1PE                     ((uint16_t)0x0008)            /*!< Output Compare 1 Preload enable */
+
+#define  TIM_CCMR1_OC1M                      ((uint16_t)0x0070)            /*!< OC1M[2:0] bits (Output Compare 1 Mode) */
+#define  TIM_CCMR1_OC1M_0                    ((uint16_t)0x0010)            /*!< Bit 0 */
+#define  TIM_CCMR1_OC1M_1                    ((uint16_t)0x0020)            /*!< Bit 1 */
+#define  TIM_CCMR1_OC1M_2                    ((uint16_t)0x0040)            /*!< Bit 2 */
+
+#define  TIM_CCMR1_OC1CE                     ((uint16_t)0x0080)            /*!< Output Compare 1Clear Enable */
+
+#define  TIM_CCMR1_CC2S                      ((uint16_t)0x0300)            /*!< CC2S[1:0] bits (Capture/Compare 2 Selection) */
+#define  TIM_CCMR1_CC2S_0                    ((uint16_t)0x0100)            /*!< Bit 0 */
+#define  TIM_CCMR1_CC2S_1                    ((uint16_t)0x0200)            /*!< Bit 1 */
+
+#define  TIM_CCMR1_OC2FE                     ((uint16_t)0x0400)            /*!< Output Compare 2 Fast enable */
+#define  TIM_CCMR1_OC2PE                     ((uint16_t)0x0800)            /*!< Output Compare 2 Preload enable */
+
+#define  TIM_CCMR1_OC2M                      ((uint16_t)0x7000)            /*!< OC2M[2:0] bits (Output Compare 2 Mode) */
+#define  TIM_CCMR1_OC2M_0                    ((uint16_t)0x1000)            /*!< Bit 0 */
+#define  TIM_CCMR1_OC2M_1                    ((uint16_t)0x2000)            /*!< Bit 1 */
+#define  TIM_CCMR1_OC2M_2                    ((uint16_t)0x4000)            /*!< Bit 2 */
+
+#define  TIM_CCMR1_OC2CE                     ((uint16_t)0x8000)            /*!< Output Compare 2 Clear Enable */
+
+/*----------------------------------------------------------------------------*/
+
+#define  TIM_CCMR1_IC1PSC                    ((uint16_t)0x000C)            /*!< IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
+#define  TIM_CCMR1_IC1PSC_0                  ((uint16_t)0x0004)            /*!< Bit 0 */
+#define  TIM_CCMR1_IC1PSC_1                  ((uint16_t)0x0008)            /*!< Bit 1 */
+
+#define  TIM_CCMR1_IC1F                      ((uint16_t)0x00F0)            /*!< IC1F[3:0] bits (Input Capture 1 Filter) */
+#define  TIM_CCMR1_IC1F_0                    ((uint16_t)0x0010)            /*!< Bit 0 */
+#define  TIM_CCMR1_IC1F_1                    ((uint16_t)0x0020)            /*!< Bit 1 */
+#define  TIM_CCMR1_IC1F_2                    ((uint16_t)0x0040)            /*!< Bit 2 */
+#define  TIM_CCMR1_IC1F_3                    ((uint16_t)0x0080)            /*!< Bit 3 */
+
+#define  TIM_CCMR1_IC2PSC                    ((uint16_t)0x0C00)            /*!< IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
+#define  TIM_CCMR1_IC2PSC_0                  ((uint16_t)0x0400)            /*!< Bit 0 */
+#define  TIM_CCMR1_IC2PSC_1                  ((uint16_t)0x0800)            /*!< Bit 1 */
+
+#define  TIM_CCMR1_IC2F                      ((uint16_t)0xF000)            /*!< IC2F[3:0] bits (Input Capture 2 Filter) */
+#define  TIM_CCMR1_IC2F_0                    ((uint16_t)0x1000)            /*!< Bit 0 */
+#define  TIM_CCMR1_IC2F_1                    ((uint16_t)0x2000)            /*!< Bit 1 */
+#define  TIM_CCMR1_IC2F_2                    ((uint16_t)0x4000)            /*!< Bit 2 */
+#define  TIM_CCMR1_IC2F_3                    ((uint16_t)0x8000)            /*!< Bit 3 */
+
+/******************  Bit definition for TIM_CCMR2 register  *******************/
+#define  TIM_CCMR2_CC3S                      ((uint16_t)0x0003)            /*!< CC3S[1:0] bits (Capture/Compare 3 Selection) */
+#define  TIM_CCMR2_CC3S_0                    ((uint16_t)0x0001)            /*!< Bit 0 */
+#define  TIM_CCMR2_CC3S_1                    ((uint16_t)0x0002)            /*!< Bit 1 */
+
+#define  TIM_CCMR2_OC3FE                     ((uint16_t)0x0004)            /*!< Output Compare 3 Fast enable */
+#define  TIM_CCMR2_OC3PE                     ((uint16_t)0x0008)            /*!< Output Compare 3 Preload enable */
+
+#define  TIM_CCMR2_OC3M                      ((uint16_t)0x0070)            /*!< OC3M[2:0] bits (Output Compare 3 Mode) */
+#define  TIM_CCMR2_OC3M_0                    ((uint16_t)0x0010)            /*!< Bit 0 */
+#define  TIM_CCMR2_OC3M_1                    ((uint16_t)0x0020)            /*!< Bit 1 */
+#define  TIM_CCMR2_OC3M_2                    ((uint16_t)0x0040)            /*!< Bit 2 */
+
+#define  TIM_CCMR2_OC3CE                     ((uint16_t)0x0080)            /*!< Output Compare 3 Clear Enable */
+
+#define  TIM_CCMR2_CC4S                      ((uint16_t)0x0300)            /*!< CC4S[1:0] bits (Capture/Compare 4 Selection) */
+#define  TIM_CCMR2_CC4S_0                    ((uint16_t)0x0100)            /*!< Bit 0 */
+#define  TIM_CCMR2_CC4S_1                    ((uint16_t)0x0200)            /*!< Bit 1 */
+
+#define  TIM_CCMR2_OC4FE                     ((uint16_t)0x0400)            /*!< Output Compare 4 Fast enable */
+#define  TIM_CCMR2_OC4PE                     ((uint16_t)0x0800)            /*!< Output Compare 4 Preload enable */
+
+#define  TIM_CCMR2_OC4M                      ((uint16_t)0x7000)            /*!< OC4M[2:0] bits (Output Compare 4 Mode) */
+#define  TIM_CCMR2_OC4M_0                    ((uint16_t)0x1000)            /*!< Bit 0 */
+#define  TIM_CCMR2_OC4M_1                    ((uint16_t)0x2000)            /*!< Bit 1 */
+#define  TIM_CCMR2_OC4M_2                    ((uint16_t)0x4000)            /*!< Bit 2 */
+
+#define  TIM_CCMR2_OC4CE                     ((uint16_t)0x8000)            /*!< Output Compare 4 Clear Enable */
+
+/*----------------------------------------------------------------------------*/
+
+#define  TIM_CCMR2_IC3PSC                    ((uint16_t)0x000C)            /*!< IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
+#define  TIM_CCMR2_IC3PSC_0                  ((uint16_t)0x0004)            /*!< Bit 0 */
+#define  TIM_CCMR2_IC3PSC_1                  ((uint16_t)0x0008)            /*!< Bit 1 */
+
+#define  TIM_CCMR2_IC3F                      ((uint16_t)0x00F0)            /*!< IC3F[3:0] bits (Input Capture 3 Filter) */
+#define  TIM_CCMR2_IC3F_0                    ((uint16_t)0x0010)            /*!< Bit 0 */
+#define  TIM_CCMR2_IC3F_1                    ((uint16_t)0x0020)            /*!< Bit 1 */
+#define  TIM_CCMR2_IC3F_2                    ((uint16_t)0x0040)            /*!< Bit 2 */
+#define  TIM_CCMR2_IC3F_3                    ((uint16_t)0x0080)            /*!< Bit 3 */
+
+#define  TIM_CCMR2_IC4PSC                    ((uint16_t)0x0C00)            /*!< IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
+#define  TIM_CCMR2_IC4PSC_0                  ((uint16_t)0x0400)            /*!< Bit 0 */
+#define  TIM_CCMR2_IC4PSC_1                  ((uint16_t)0x0800)            /*!< Bit 1 */
+
+#define  TIM_CCMR2_IC4F                      ((uint16_t)0xF000)            /*!< IC4F[3:0] bits (Input Capture 4 Filter) */
+#define  TIM_CCMR2_IC4F_0                    ((uint16_t)0x1000)            /*!< Bit 0 */
+#define  TIM_CCMR2_IC4F_1                    ((uint16_t)0x2000)            /*!< Bit 1 */
+#define  TIM_CCMR2_IC4F_2                    ((uint16_t)0x4000)            /*!< Bit 2 */
+#define  TIM_CCMR2_IC4F_3                    ((uint16_t)0x8000)            /*!< Bit 3 */
+
+/*******************  Bit definition for TIM_CCER register  *******************/
+#define  TIM_CCER_CC1E                       ((uint16_t)0x0001)            /*!< Capture/Compare 1 output enable */
+#define  TIM_CCER_CC1P                       ((uint16_t)0x0002)            /*!< Capture/Compare 1 output Polarity */
+#define  TIM_CCER_CC1NE                      ((uint16_t)0x0004)            /*!< Capture/Compare 1 Complementary output enable */
+#define  TIM_CCER_CC1NP                      ((uint16_t)0x0008)            /*!< Capture/Compare 1 Complementary output Polarity */
+#define  TIM_CCER_CC2E                       ((uint16_t)0x0010)            /*!< Capture/Compare 2 output enable */
+#define  TIM_CCER_CC2P                       ((uint16_t)0x0020)            /*!< Capture/Compare 2 output Polarity */
+#define  TIM_CCER_CC2NE                      ((uint16_t)0x0040)            /*!< Capture/Compare 2 Complementary output enable */
+#define  TIM_CCER_CC2NP                      ((uint16_t)0x0080)            /*!< Capture/Compare 2 Complementary output Polarity */
+#define  TIM_CCER_CC3E                       ((uint16_t)0x0100)            /*!< Capture/Compare 3 output enable */
+#define  TIM_CCER_CC3P                       ((uint16_t)0x0200)            /*!< Capture/Compare 3 output Polarity */
+#define  TIM_CCER_CC3NE                      ((uint16_t)0x0400)            /*!< Capture/Compare 3 Complementary output enable */
+#define  TIM_CCER_CC3NP                      ((uint16_t)0x0800)            /*!< Capture/Compare 3 Complementary output Polarity */
+#define  TIM_CCER_CC4E                       ((uint16_t)0x1000)            /*!< Capture/Compare 4 output enable */
+#define  TIM_CCER_CC4P                       ((uint16_t)0x2000)            /*!< Capture/Compare 4 output Polarity */
+#define  TIM_CCER_CC4NP                      ((uint16_t)0x8000)            /*!< Capture/Compare 4 Complementary output Polarity */
+
+/*******************  Bit definition for TIM_CNT register  ********************/
+#define  TIM_CNT_CNT                         ((uint16_t)0xFFFF)            /*!< Counter Value */
+
+/*******************  Bit definition for TIM_PSC register  ********************/
+#define  TIM_PSC_PSC                         ((uint16_t)0xFFFF)            /*!< Prescaler Value */
+
+/*******************  Bit definition for TIM_ARR register  ********************/
+#define  TIM_ARR_ARR                         ((uint16_t)0xFFFF)            /*!< actual auto-reload Value */
+
+/*******************  Bit definition for TIM_RCR register  ********************/
+#define  TIM_RCR_REP                         ((uint8_t)0xFF)               /*!< Repetition Counter Value */
+
+/*******************  Bit definition for TIM_CCR1 register  *******************/
+#define  TIM_CCR1_CCR1                       ((uint16_t)0xFFFF)            /*!< Capture/Compare 1 Value */
+
+/*******************  Bit definition for TIM_CCR2 register  *******************/
+#define  TIM_CCR2_CCR2                       ((uint16_t)0xFFFF)            /*!< Capture/Compare 2 Value */
+
+/*******************  Bit definition for TIM_CCR3 register  *******************/
+#define  TIM_CCR3_CCR3                       ((uint16_t)0xFFFF)            /*!< Capture/Compare 3 Value */
+
+/*******************  Bit definition for TIM_CCR4 register  *******************/
+#define  TIM_CCR4_CCR4                       ((uint16_t)0xFFFF)            /*!< Capture/Compare 4 Value */
+
+/*******************  Bit definition for TIM_BDTR register  *******************/
+#define  TIM_BDTR_DTG                        ((uint16_t)0x00FF)            /*!< DTG[0:7] bits (Dead-Time Generator set-up) */
+#define  TIM_BDTR_DTG_0                      ((uint16_t)0x0001)            /*!< Bit 0 */
+#define  TIM_BDTR_DTG_1                      ((uint16_t)0x0002)            /*!< Bit 1 */
+#define  TIM_BDTR_DTG_2                      ((uint16_t)0x0004)            /*!< Bit 2 */
+#define  TIM_BDTR_DTG_3                      ((uint16_t)0x0008)            /*!< Bit 3 */
+#define  TIM_BDTR_DTG_4                      ((uint16_t)0x0010)            /*!< Bit 4 */
+#define  TIM_BDTR_DTG_5                      ((uint16_t)0x0020)            /*!< Bit 5 */
+#define  TIM_BDTR_DTG_6                      ((uint16_t)0x0040)            /*!< Bit 6 */
+#define  TIM_BDTR_DTG_7                      ((uint16_t)0x0080)            /*!< Bit 7 */
+
+#define  TIM_BDTR_LOCK                       ((uint16_t)0x0300)            /*!< LOCK[1:0] bits (Lock Configuration) */
+#define  TIM_BDTR_LOCK_0                     ((uint16_t)0x0100)            /*!< Bit 0 */
+#define  TIM_BDTR_LOCK_1                     ((uint16_t)0x0200)            /*!< Bit 1 */
+
+#define  TIM_BDTR_OSSI                       ((uint16_t)0x0400)            /*!< Off-State Selection for Idle mode */
+#define  TIM_BDTR_OSSR                       ((uint16_t)0x0800)            /*!< Off-State Selection for Run mode */
+#define  TIM_BDTR_BKE                        ((uint16_t)0x1000)            /*!< Break enable */
+#define  TIM_BDTR_BKP                        ((uint16_t)0x2000)            /*!< Break Polarity */
+#define  TIM_BDTR_AOE                        ((uint16_t)0x4000)            /*!< Automatic Output enable */
+#define  TIM_BDTR_MOE                        ((uint16_t)0x8000)            /*!< Main Output enable */
+
+/*******************  Bit definition for TIM_DCR register  ********************/
+#define  TIM_DCR_DBA                         ((uint16_t)0x001F)            /*!< DBA[4:0] bits (DMA Base Address) */
+#define  TIM_DCR_DBA_0                       ((uint16_t)0x0001)            /*!< Bit 0 */
+#define  TIM_DCR_DBA_1                       ((uint16_t)0x0002)            /*!< Bit 1 */
+#define  TIM_DCR_DBA_2                       ((uint16_t)0x0004)            /*!< Bit 2 */
+#define  TIM_DCR_DBA_3                       ((uint16_t)0x0008)            /*!< Bit 3 */
+#define  TIM_DCR_DBA_4                       ((uint16_t)0x0010)            /*!< Bit 4 */
+
+#define  TIM_DCR_DBL                         ((uint16_t)0x1F00)            /*!< DBL[4:0] bits (DMA Burst Length) */
+#define  TIM_DCR_DBL_0                       ((uint16_t)0x0100)            /*!< Bit 0 */
+#define  TIM_DCR_DBL_1                       ((uint16_t)0x0200)            /*!< Bit 1 */
+#define  TIM_DCR_DBL_2                       ((uint16_t)0x0400)            /*!< Bit 2 */
+#define  TIM_DCR_DBL_3                       ((uint16_t)0x0800)            /*!< Bit 3 */
+#define  TIM_DCR_DBL_4                       ((uint16_t)0x1000)            /*!< Bit 4 */
+
+/*******************  Bit definition for TIM_DMAR register  *******************/
+#define  TIM_DMAR_DMAB                       ((uint16_t)0xFFFF)            /*!< DMA register for burst accesses */
+
+/******************************************************************************/
+/*                                                                            */
+/*                             Real-Time Clock                                */
+/*                                                                            */
+/******************************************************************************/
+
+/*******************  Bit definition for RTC_CRH register  ********************/
+#define  RTC_CRH_SECIE                       ((uint8_t)0x01)               /*!< Second Interrupt Enable */
+#define  RTC_CRH_ALRIE                       ((uint8_t)0x02)               /*!< Alarm Interrupt Enable */
+#define  RTC_CRH_OWIE                        ((uint8_t)0x04)               /*!< OverfloW Interrupt Enable */
+
+/*******************  Bit definition for RTC_CRL register  ********************/
+#define  RTC_CRL_SECF                        ((uint8_t)0x01)               /*!< Second Flag */
+#define  RTC_CRL_ALRF                        ((uint8_t)0x02)               /*!< Alarm Flag */
+#define  RTC_CRL_OWF                         ((uint8_t)0x04)               /*!< OverfloW Flag */
+#define  RTC_CRL_RSF                         ((uint8_t)0x08)               /*!< Registers Synchronized Flag */
+#define  RTC_CRL_CNF                         ((uint8_t)0x10)               /*!< Configuration Flag */
+#define  RTC_CRL_RTOFF                       ((uint8_t)0x20)               /*!< RTC operation OFF */
+
+/*******************  Bit definition for RTC_PRLH register  *******************/
+#define  RTC_PRLH_PRL                        ((uint16_t)0x000F)            /*!< RTC Prescaler Reload Value High */
+
+/*******************  Bit definition for RTC_PRLL register  *******************/
+#define  RTC_PRLL_PRL                        ((uint16_t)0xFFFF)            /*!< RTC Prescaler Reload Value Low */
+
+/*******************  Bit definition for RTC_DIVH register  *******************/
+#define  RTC_DIVH_RTC_DIV                    ((uint16_t)0x000F)            /*!< RTC Clock Divider High */
+
+/*******************  Bit definition for RTC_DIVL register  *******************/
+#define  RTC_DIVL_RTC_DIV                    ((uint16_t)0xFFFF)            /*!< RTC Clock Divider Low */
+
+/*******************  Bit definition for RTC_CNTH register  *******************/
+#define  RTC_CNTH_RTC_CNT                    ((uint16_t)0xFFFF)            /*!< RTC Counter High */
+
+/*******************  Bit definition for RTC_CNTL register  *******************/
+#define  RTC_CNTL_RTC_CNT                    ((uint16_t)0xFFFF)            /*!< RTC Counter Low */
+
+/*******************  Bit definition for RTC_ALRH register  *******************/
+#define  RTC_ALRH_RTC_ALR                    ((uint16_t)0xFFFF)            /*!< RTC Alarm High */
+
+/*******************  Bit definition for RTC_ALRL register  *******************/
+#define  RTC_ALRL_RTC_ALR                    ((uint16_t)0xFFFF)            /*!< RTC Alarm Low */
+
+/******************************************************************************/
+/*                                                                            */
+/*                           Independent WATCHDOG                             */
+/*                                                                            */
+/******************************************************************************/
+
+/*******************  Bit definition for IWDG_KR register  ********************/
+#define  IWDG_KR_KEY                         ((uint16_t)0xFFFF)            /*!< Key value (write only, read 0000h) */
+
+/*******************  Bit definition for IWDG_PR register  ********************/
+#define  IWDG_PR_PR                          ((uint8_t)0x07)               /*!< PR[2:0] (Prescaler divider) */
+#define  IWDG_PR_PR_0                        ((uint8_t)0x01)               /*!< Bit 0 */
+#define  IWDG_PR_PR_1                        ((uint8_t)0x02)               /*!< Bit 1 */
+#define  IWDG_PR_PR_2                        ((uint8_t)0x04)               /*!< Bit 2 */
+
+/*******************  Bit definition for IWDG_RLR register  *******************/
+#define  IWDG_RLR_RL                         ((uint16_t)0x0FFF)            /*!< Watchdog counter reload value */
+
+/*******************  Bit definition for IWDG_SR register  ********************/
+#define  IWDG_SR_PVU                         ((uint8_t)0x01)               /*!< Watchdog prescaler value update */
+#define  IWDG_SR_RVU                         ((uint8_t)0x02)               /*!< Watchdog counter reload value update */
+
+/******************************************************************************/
+/*                                                                            */
+/*                            Window WATCHDOG                                 */
+/*                                                                            */
+/******************************************************************************/
+
+/*******************  Bit definition for WWDG_CR register  ********************/
+#define  WWDG_CR_T                           ((uint8_t)0x7F)               /*!< T[6:0] bits (7-Bit counter (MSB to LSB)) */
+#define  WWDG_CR_T0                          ((uint8_t)0x01)               /*!< Bit 0 */
+#define  WWDG_CR_T1                          ((uint8_t)0x02)               /*!< Bit 1 */
+#define  WWDG_CR_T2                          ((uint8_t)0x04)               /*!< Bit 2 */
+#define  WWDG_CR_T3                          ((uint8_t)0x08)               /*!< Bit 3 */
+#define  WWDG_CR_T4                          ((uint8_t)0x10)               /*!< Bit 4 */
+#define  WWDG_CR_T5                          ((uint8_t)0x20)               /*!< Bit 5 */
+#define  WWDG_CR_T6                          ((uint8_t)0x40)               /*!< Bit 6 */
+
+#define  WWDG_CR_WDGA                        ((uint8_t)0x80)               /*!< Activation bit */
+
+/*******************  Bit definition for WWDG_CFR register  *******************/
+#define  WWDG_CFR_W                          ((uint16_t)0x007F)            /*!< W[6:0] bits (7-bit window value) */
+#define  WWDG_CFR_W0                         ((uint16_t)0x0001)            /*!< Bit 0 */
+#define  WWDG_CFR_W1                         ((uint16_t)0x0002)            /*!< Bit 1 */
+#define  WWDG_CFR_W2                         ((uint16_t)0x0004)            /*!< Bit 2 */
+#define  WWDG_CFR_W3                         ((uint16_t)0x0008)            /*!< Bit 3 */
+#define  WWDG_CFR_W4                         ((uint16_t)0x0010)            /*!< Bit 4 */
+#define  WWDG_CFR_W5                         ((uint16_t)0x0020)            /*!< Bit 5 */
+#define  WWDG_CFR_W6                         ((uint16_t)0x0040)            /*!< Bit 6 */
+
+#define  WWDG_CFR_WDGTB                      ((uint16_t)0x0180)            /*!< WDGTB[1:0] bits (Timer Base) */
+#define  WWDG_CFR_WDGTB0                     ((uint16_t)0x0080)            /*!< Bit 0 */
+#define  WWDG_CFR_WDGTB1                     ((uint16_t)0x0100)            /*!< Bit 1 */
+
+#define  WWDG_CFR_EWI                        ((uint16_t)0x0200)            /*!< Early Wakeup Interrupt */
+
+/*******************  Bit definition for WWDG_SR register  ********************/
+#define  WWDG_SR_EWIF                        ((uint8_t)0x01)               /*!< Early Wakeup Interrupt Flag */
+
+/******************************************************************************/
+/*                                                                            */
+/*                       Flexible Static Memory Controller                    */
+/*                                                                            */
+/******************************************************************************/
+
+/******************  Bit definition for FSMC_BCR1 register  *******************/
+#define  FSMC_BCR1_MBKEN                     ((uint32_t)0x00000001)        /*!< Memory bank enable bit */
+#define  FSMC_BCR1_MUXEN                     ((uint32_t)0x00000002)        /*!< Address/data multiplexing enable bit */
+
+#define  FSMC_BCR1_MTYP                      ((uint32_t)0x0000000C)        /*!< MTYP[1:0] bits (Memory type) */
+#define  FSMC_BCR1_MTYP_0                    ((uint32_t)0x00000004)        /*!< Bit 0 */
+#define  FSMC_BCR1_MTYP_1                    ((uint32_t)0x00000008)        /*!< Bit 1 */
+
+#define  FSMC_BCR1_MWID                      ((uint32_t)0x00000030)        /*!< MWID[1:0] bits (Memory data bus width) */
+#define  FSMC_BCR1_MWID_0                    ((uint32_t)0x00000010)        /*!< Bit 0 */
+#define  FSMC_BCR1_MWID_1                    ((uint32_t)0x00000020)        /*!< Bit 1 */
+
+#define  FSMC_BCR1_FACCEN                    ((uint32_t)0x00000040)        /*!< Flash access enable */
+#define  FSMC_BCR1_BURSTEN                   ((uint32_t)0x00000100)        /*!< Burst enable bit */
+#define  FSMC_BCR1_WAITPOL                   ((uint32_t)0x00000200)        /*!< Wait signal polarity bit */
+#define  FSMC_BCR1_WRAPMOD                   ((uint32_t)0x00000400)        /*!< Wrapped burst mode support */
+#define  FSMC_BCR1_WAITCFG                   ((uint32_t)0x00000800)        /*!< Wait timing configuration */
+#define  FSMC_BCR1_WREN                      ((uint32_t)0x00001000)        /*!< Write enable bit */
+#define  FSMC_BCR1_WAITEN                    ((uint32_t)0x00002000)        /*!< Wait enable bit */
+#define  FSMC_BCR1_EXTMOD                    ((uint32_t)0x00004000)        /*!< Extended mode enable */
+#define  FSMC_BCR1_ASYNCWAIT                 ((uint32_t)0x00008000)       /*!< Asynchronous wait */
+#define  FSMC_BCR1_CBURSTRW                  ((uint32_t)0x00080000)        /*!< Write burst enable */
+
+/******************  Bit definition for FSMC_BCR2 register  *******************/
+#define  FSMC_BCR2_MBKEN                     ((uint32_t)0x00000001)        /*!< Memory bank enable bit */
+#define  FSMC_BCR2_MUXEN                     ((uint32_t)0x00000002)        /*!< Address/data multiplexing enable bit */
+
+#define  FSMC_BCR2_MTYP                      ((uint32_t)0x0000000C)        /*!< MTYP[1:0] bits (Memory type) */
+#define  FSMC_BCR2_MTYP_0                    ((uint32_t)0x00000004)        /*!< Bit 0 */
+#define  FSMC_BCR2_MTYP_1                    ((uint32_t)0x00000008)        /*!< Bit 1 */
+
+#define  FSMC_BCR2_MWID                      ((uint32_t)0x00000030)        /*!< MWID[1:0] bits (Memory data bus width) */
+#define  FSMC_BCR2_MWID_0                    ((uint32_t)0x00000010)        /*!< Bit 0 */
+#define  FSMC_BCR2_MWID_1                    ((uint32_t)0x00000020)        /*!< Bit 1 */
+
+#define  FSMC_BCR2_FACCEN                    ((uint32_t)0x00000040)        /*!< Flash access enable */
+#define  FSMC_BCR2_BURSTEN                   ((uint32_t)0x00000100)        /*!< Burst enable bit */
+#define  FSMC_BCR2_WAITPOL                   ((uint32_t)0x00000200)        /*!< Wait signal polarity bit */
+#define  FSMC_BCR2_WRAPMOD                   ((uint32_t)0x00000400)        /*!< Wrapped burst mode support */
+#define  FSMC_BCR2_WAITCFG                   ((uint32_t)0x00000800)        /*!< Wait timing configuration */
+#define  FSMC_BCR2_WREN                      ((uint32_t)0x00001000)        /*!< Write enable bit */
+#define  FSMC_BCR2_WAITEN                    ((uint32_t)0x00002000)        /*!< Wait enable bit */
+#define  FSMC_BCR2_EXTMOD                    ((uint32_t)0x00004000)        /*!< Extended mode enable */
+#define  FSMC_BCR2_ASYNCWAIT                 ((uint32_t)0x00008000)       /*!< Asynchronous wait */
+#define  FSMC_BCR2_CBURSTRW                  ((uint32_t)0x00080000)        /*!< Write burst enable */
+
+/******************  Bit definition for FSMC_BCR3 register  *******************/
+#define  FSMC_BCR3_MBKEN                     ((uint32_t)0x00000001)        /*!< Memory bank enable bit */
+#define  FSMC_BCR3_MUXEN                     ((uint32_t)0x00000002)        /*!< Address/data multiplexing enable bit */
+
+#define  FSMC_BCR3_MTYP                      ((uint32_t)0x0000000C)        /*!< MTYP[1:0] bits (Memory type) */
+#define  FSMC_BCR3_MTYP_0                    ((uint32_t)0x00000004)        /*!< Bit 0 */
+#define  FSMC_BCR3_MTYP_1                    ((uint32_t)0x00000008)        /*!< Bit 1 */
+
+#define  FSMC_BCR3_MWID                      ((uint32_t)0x00000030)        /*!< MWID[1:0] bits (Memory data bus width) */
+#define  FSMC_BCR3_MWID_0                    ((uint32_t)0x00000010)        /*!< Bit 0 */
+#define  FSMC_BCR3_MWID_1                    ((uint32_t)0x00000020)        /*!< Bit 1 */
+
+#define  FSMC_BCR3_FACCEN                    ((uint32_t)0x00000040)        /*!< Flash access enable */
+#define  FSMC_BCR3_BURSTEN                   ((uint32_t)0x00000100)        /*!< Burst enable bit */
+#define  FSMC_BCR3_WAITPOL                   ((uint32_t)0x00000200)        /*!< Wait signal polarity bit. */
+#define  FSMC_BCR3_WRAPMOD                   ((uint32_t)0x00000400)        /*!< Wrapped burst mode support */
+#define  FSMC_BCR3_WAITCFG                   ((uint32_t)0x00000800)        /*!< Wait timing configuration */
+#define  FSMC_BCR3_WREN                      ((uint32_t)0x00001000)        /*!< Write enable bit */
+#define  FSMC_BCR3_WAITEN                    ((uint32_t)0x00002000)        /*!< Wait enable bit */
+#define  FSMC_BCR3_EXTMOD                    ((uint32_t)0x00004000)        /*!< Extended mode enable */
+#define  FSMC_BCR3_ASYNCWAIT                 ((uint32_t)0x00008000)       /*!< Asynchronous wait */
+#define  FSMC_BCR3_CBURSTRW                  ((uint32_t)0x00080000)        /*!< Write burst enable */
+
+/******************  Bit definition for FSMC_BCR4 register  *******************/
+#define  FSMC_BCR4_MBKEN                     ((uint32_t)0x00000001)        /*!< Memory bank enable bit */
+#define  FSMC_BCR4_MUXEN                     ((uint32_t)0x00000002)        /*!< Address/data multiplexing enable bit */
+
+#define  FSMC_BCR4_MTYP                      ((uint32_t)0x0000000C)        /*!< MTYP[1:0] bits (Memory type) */
+#define  FSMC_BCR4_MTYP_0                    ((uint32_t)0x00000004)        /*!< Bit 0 */
+#define  FSMC_BCR4_MTYP_1                    ((uint32_t)0x00000008)        /*!< Bit 1 */
+
+#define  FSMC_BCR4_MWID                      ((uint32_t)0x00000030)        /*!< MWID[1:0] bits (Memory data bus width) */
+#define  FSMC_BCR4_MWID_0                    ((uint32_t)0x00000010)        /*!< Bit 0 */
+#define  FSMC_BCR4_MWID_1                    ((uint32_t)0x00000020)        /*!< Bit 1 */
+
+#define  FSMC_BCR4_FACCEN                    ((uint32_t)0x00000040)        /*!< Flash access enable */
+#define  FSMC_BCR4_BURSTEN                   ((uint32_t)0x00000100)        /*!< Burst enable bit */
+#define  FSMC_BCR4_WAITPOL                   ((uint32_t)0x00000200)        /*!< Wait signal polarity bit */
+#define  FSMC_BCR4_WRAPMOD                   ((uint32_t)0x00000400)        /*!< Wrapped burst mode support */
+#define  FSMC_BCR4_WAITCFG                   ((uint32_t)0x00000800)        /*!< Wait timing configuration */
+#define  FSMC_BCR4_WREN                      ((uint32_t)0x00001000)        /*!< Write enable bit */
+#define  FSMC_BCR4_WAITEN                    ((uint32_t)0x00002000)        /*!< Wait enable bit */
+#define  FSMC_BCR4_EXTMOD                    ((uint32_t)0x00004000)        /*!< Extended mode enable */
+#define  FSMC_BCR4_ASYNCWAIT                 ((uint32_t)0x00008000)       /*!< Asynchronous wait */
+#define  FSMC_BCR4_CBURSTRW                  ((uint32_t)0x00080000)        /*!< Write burst enable */
+
+/******************  Bit definition for FSMC_BTR1 register  ******************/
+#define  FSMC_BTR1_ADDSET                    ((uint32_t)0x0000000F)        /*!< ADDSET[3:0] bits (Address setup phase duration) */
+#define  FSMC_BTR1_ADDSET_0                  ((uint32_t)0x00000001)        /*!< Bit 0 */
+#define  FSMC_BTR1_ADDSET_1                  ((uint32_t)0x00000002)        /*!< Bit 1 */
+#define  FSMC_BTR1_ADDSET_2                  ((uint32_t)0x00000004)        /*!< Bit 2 */
+#define  FSMC_BTR1_ADDSET_3                  ((uint32_t)0x00000008)        /*!< Bit 3 */
+
+#define  FSMC_BTR1_ADDHLD                    ((uint32_t)0x000000F0)        /*!< ADDHLD[3:0] bits (Address-hold phase duration) */
+#define  FSMC_BTR1_ADDHLD_0                  ((uint32_t)0x00000010)        /*!< Bit 0 */
+#define  FSMC_BTR1_ADDHLD_1                  ((uint32_t)0x00000020)        /*!< Bit 1 */
+#define  FSMC_BTR1_ADDHLD_2                  ((uint32_t)0x00000040)        /*!< Bit 2 */
+#define  FSMC_BTR1_ADDHLD_3                  ((uint32_t)0x00000080)        /*!< Bit 3 */
+
+#define  FSMC_BTR1_DATAST                    ((uint32_t)0x0000FF00)        /*!< DATAST [3:0] bits (Data-phase duration) */
+#define  FSMC_BTR1_DATAST_0                  ((uint32_t)0x00000100)        /*!< Bit 0 */
+#define  FSMC_BTR1_DATAST_1                  ((uint32_t)0x00000200)        /*!< Bit 1 */
+#define  FSMC_BTR1_DATAST_2                  ((uint32_t)0x00000400)        /*!< Bit 2 */
+#define  FSMC_BTR1_DATAST_3                  ((uint32_t)0x00000800)        /*!< Bit 3 */
+
+#define  FSMC_BTR1_BUSTURN                   ((uint32_t)0x000F0000)        /*!< BUSTURN[3:0] bits (Bus turnaround phase duration) */
+#define  FSMC_BTR1_BUSTURN_0                 ((uint32_t)0x00010000)        /*!< Bit 0 */
+#define  FSMC_BTR1_BUSTURN_1                 ((uint32_t)0x00020000)        /*!< Bit 1 */
+#define  FSMC_BTR1_BUSTURN_2                 ((uint32_t)0x00040000)        /*!< Bit 2 */
+#define  FSMC_BTR1_BUSTURN_3                 ((uint32_t)0x00080000)        /*!< Bit 3 */
+
+#define  FSMC_BTR1_CLKDIV                    ((uint32_t)0x00F00000)        /*!< CLKDIV[3:0] bits (Clock divide ratio) */
+#define  FSMC_BTR1_CLKDIV_0                  ((uint32_t)0x00100000)        /*!< Bit 0 */
+#define  FSMC_BTR1_CLKDIV_1                  ((uint32_t)0x00200000)        /*!< Bit 1 */
+#define  FSMC_BTR1_CLKDIV_2                  ((uint32_t)0x00400000)        /*!< Bit 2 */
+#define  FSMC_BTR1_CLKDIV_3                  ((uint32_t)0x00800000)        /*!< Bit 3 */
+
+#define  FSMC_BTR1_DATLAT                    ((uint32_t)0x0F000000)        /*!< DATLA[3:0] bits (Data latency) */
+#define  FSMC_BTR1_DATLAT_0                  ((uint32_t)0x01000000)        /*!< Bit 0 */
+#define  FSMC_BTR1_DATLAT_1                  ((uint32_t)0x02000000)        /*!< Bit 1 */
+#define  FSMC_BTR1_DATLAT_2                  ((uint32_t)0x04000000)        /*!< Bit 2 */
+#define  FSMC_BTR1_DATLAT_3                  ((uint32_t)0x08000000)        /*!< Bit 3 */
+
+#define  FSMC_BTR1_ACCMOD                    ((uint32_t)0x30000000)        /*!< ACCMOD[1:0] bits (Access mode) */
+#define  FSMC_BTR1_ACCMOD_0                  ((uint32_t)0x10000000)        /*!< Bit 0 */
+#define  FSMC_BTR1_ACCMOD_1                  ((uint32_t)0x20000000)        /*!< Bit 1 */
+
+/******************  Bit definition for FSMC_BTR2 register  *******************/
+#define  FSMC_BTR2_ADDSET                    ((uint32_t)0x0000000F)        /*!< ADDSET[3:0] bits (Address setup phase duration) */
+#define  FSMC_BTR2_ADDSET_0                  ((uint32_t)0x00000001)        /*!< Bit 0 */
+#define  FSMC_BTR2_ADDSET_1                  ((uint32_t)0x00000002)        /*!< Bit 1 */
+#define  FSMC_BTR2_ADDSET_2                  ((uint32_t)0x00000004)        /*!< Bit 2 */
+#define  FSMC_BTR2_ADDSET_3                  ((uint32_t)0x00000008)        /*!< Bit 3 */
+
+#define  FSMC_BTR2_ADDHLD                    ((uint32_t)0x000000F0)        /*!< ADDHLD[3:0] bits (Address-hold phase duration) */
+#define  FSMC_BTR2_ADDHLD_0                  ((uint32_t)0x00000010)        /*!< Bit 0 */
+#define  FSMC_BTR2_ADDHLD_1                  ((uint32_t)0x00000020)        /*!< Bit 1 */
+#define  FSMC_BTR2_ADDHLD_2                  ((uint32_t)0x00000040)        /*!< Bit 2 */
+#define  FSMC_BTR2_ADDHLD_3                  ((uint32_t)0x00000080)        /*!< Bit 3 */
+
+#define  FSMC_BTR2_DATAST                    ((uint32_t)0x0000FF00)        /*!< DATAST [3:0] bits (Data-phase duration) */
+#define  FSMC_BTR2_DATAST_0                  ((uint32_t)0x00000100)        /*!< Bit 0 */
+#define  FSMC_BTR2_DATAST_1                  ((uint32_t)0x00000200)        /*!< Bit 1 */
+#define  FSMC_BTR2_DATAST_2                  ((uint32_t)0x00000400)        /*!< Bit 2 */
+#define  FSMC_BTR2_DATAST_3                  ((uint32_t)0x00000800)        /*!< Bit 3 */
+
+#define  FSMC_BTR2_BUSTURN                   ((uint32_t)0x000F0000)        /*!< BUSTURN[3:0] bits (Bus turnaround phase duration) */
+#define  FSMC_BTR2_BUSTURN_0                 ((uint32_t)0x00010000)        /*!< Bit 0 */
+#define  FSMC_BTR2_BUSTURN_1                 ((uint32_t)0x00020000)        /*!< Bit 1 */
+#define  FSMC_BTR2_BUSTURN_2                 ((uint32_t)0x00040000)        /*!< Bit 2 */
+#define  FSMC_BTR2_BUSTURN_3                 ((uint32_t)0x00080000)        /*!< Bit 3 */
+
+#define  FSMC_BTR2_CLKDIV                    ((uint32_t)0x00F00000)        /*!< CLKDIV[3:0] bits (Clock divide ratio) */
+#define  FSMC_BTR2_CLKDIV_0                  ((uint32_t)0x00100000)        /*!< Bit 0 */
+#define  FSMC_BTR2_CLKDIV_1                  ((uint32_t)0x00200000)        /*!< Bit 1 */
+#define  FSMC_BTR2_CLKDIV_2                  ((uint32_t)0x00400000)        /*!< Bit 2 */
+#define  FSMC_BTR2_CLKDIV_3                  ((uint32_t)0x00800000)        /*!< Bit 3 */
+
+#define  FSMC_BTR2_DATLAT                    ((uint32_t)0x0F000000)        /*!< DATLA[3:0] bits (Data latency) */
+#define  FSMC_BTR2_DATLAT_0                  ((uint32_t)0x01000000)        /*!< Bit 0 */
+#define  FSMC_BTR2_DATLAT_1                  ((uint32_t)0x02000000)        /*!< Bit 1 */
+#define  FSMC_BTR2_DATLAT_2                  ((uint32_t)0x04000000)        /*!< Bit 2 */
+#define  FSMC_BTR2_DATLAT_3                  ((uint32_t)0x08000000)        /*!< Bit 3 */
+
+#define  FSMC_BTR2_ACCMOD                    ((uint32_t)0x30000000)        /*!< ACCMOD[1:0] bits (Access mode) */
+#define  FSMC_BTR2_ACCMOD_0                  ((uint32_t)0x10000000)        /*!< Bit 0 */
+#define  FSMC_BTR2_ACCMOD_1                  ((uint32_t)0x20000000)        /*!< Bit 1 */
+
+/*******************  Bit definition for FSMC_BTR3 register  *******************/
+#define  FSMC_BTR3_ADDSET                    ((uint32_t)0x0000000F)        /*!< ADDSET[3:0] bits (Address setup phase duration) */
+#define  FSMC_BTR3_ADDSET_0                  ((uint32_t)0x00000001)        /*!< Bit 0 */
+#define  FSMC_BTR3_ADDSET_1                  ((uint32_t)0x00000002)        /*!< Bit 1 */
+#define  FSMC_BTR3_ADDSET_2                  ((uint32_t)0x00000004)        /*!< Bit 2 */
+#define  FSMC_BTR3_ADDSET_3                  ((uint32_t)0x00000008)        /*!< Bit 3 */
+
+#define  FSMC_BTR3_ADDHLD                    ((uint32_t)0x000000F0)        /*!< ADDHLD[3:0] bits (Address-hold phase duration) */
+#define  FSMC_BTR3_ADDHLD_0                  ((uint32_t)0x00000010)        /*!< Bit 0 */
+#define  FSMC_BTR3_ADDHLD_1                  ((uint32_t)0x00000020)        /*!< Bit 1 */
+#define  FSMC_BTR3_ADDHLD_2                  ((uint32_t)0x00000040)        /*!< Bit 2 */
+#define  FSMC_BTR3_ADDHLD_3                  ((uint32_t)0x00000080)        /*!< Bit 3 */
+
+#define  FSMC_BTR3_DATAST                    ((uint32_t)0x0000FF00)        /*!< DATAST [3:0] bits (Data-phase duration) */
+#define  FSMC_BTR3_DATAST_0                  ((uint32_t)0x00000100)        /*!< Bit 0 */
+#define  FSMC_BTR3_DATAST_1                  ((uint32_t)0x00000200)        /*!< Bit 1 */
+#define  FSMC_BTR3_DATAST_2                  ((uint32_t)0x00000400)        /*!< Bit 2 */
+#define  FSMC_BTR3_DATAST_3                  ((uint32_t)0x00000800)        /*!< Bit 3 */
+
+#define  FSMC_BTR3_BUSTURN                   ((uint32_t)0x000F0000)        /*!< BUSTURN[3:0] bits (Bus turnaround phase duration) */
+#define  FSMC_BTR3_BUSTURN_0                 ((uint32_t)0x00010000)        /*!< Bit 0 */
+#define  FSMC_BTR3_BUSTURN_1                 ((uint32_t)0x00020000)        /*!< Bit 1 */
+#define  FSMC_BTR3_BUSTURN_2                 ((uint32_t)0x00040000)        /*!< Bit 2 */
+#define  FSMC_BTR3_BUSTURN_3                 ((uint32_t)0x00080000)        /*!< Bit 3 */
+
+#define  FSMC_BTR3_CLKDIV                    ((uint32_t)0x00F00000)        /*!< CLKDIV[3:0] bits (Clock divide ratio) */
+#define  FSMC_BTR3_CLKDIV_0                  ((uint32_t)0x00100000)        /*!< Bit 0 */
+#define  FSMC_BTR3_CLKDIV_1                  ((uint32_t)0x00200000)        /*!< Bit 1 */
+#define  FSMC_BTR3_CLKDIV_2                  ((uint32_t)0x00400000)        /*!< Bit 2 */
+#define  FSMC_BTR3_CLKDIV_3                  ((uint32_t)0x00800000)        /*!< Bit 3 */
+
+#define  FSMC_BTR3_DATLAT                    ((uint32_t)0x0F000000)        /*!< DATLA[3:0] bits (Data latency) */
+#define  FSMC_BTR3_DATLAT_0                  ((uint32_t)0x01000000)        /*!< Bit 0 */
+#define  FSMC_BTR3_DATLAT_1                  ((uint32_t)0x02000000)        /*!< Bit 1 */
+#define  FSMC_BTR3_DATLAT_2                  ((uint32_t)0x04000000)        /*!< Bit 2 */
+#define  FSMC_BTR3_DATLAT_3                  ((uint32_t)0x08000000)        /*!< Bit 3 */
+
+#define  FSMC_BTR3_ACCMOD                    ((uint32_t)0x30000000)        /*!< ACCMOD[1:0] bits (Access mode) */
+#define  FSMC_BTR3_ACCMOD_0                  ((uint32_t)0x10000000)        /*!< Bit 0 */
+#define  FSMC_BTR3_ACCMOD_1                  ((uint32_t)0x20000000)        /*!< Bit 1 */
+
+/******************  Bit definition for FSMC_BTR4 register  *******************/
+#define  FSMC_BTR4_ADDSET                    ((uint32_t)0x0000000F)        /*!< ADDSET[3:0] bits (Address setup phase duration) */
+#define  FSMC_BTR4_ADDSET_0                  ((uint32_t)0x00000001)        /*!< Bit 0 */
+#define  FSMC_BTR4_ADDSET_1                  ((uint32_t)0x00000002)        /*!< Bit 1 */
+#define  FSMC_BTR4_ADDSET_2                  ((uint32_t)0x00000004)        /*!< Bit 2 */
+#define  FSMC_BTR4_ADDSET_3                  ((uint32_t)0x00000008)        /*!< Bit 3 */
+
+#define  FSMC_BTR4_ADDHLD                    ((uint32_t)0x000000F0)        /*!< ADDHLD[3:0] bits (Address-hold phase duration) */
+#define  FSMC_BTR4_ADDHLD_0                  ((uint32_t)0x00000010)        /*!< Bit 0 */
+#define  FSMC_BTR4_ADDHLD_1                  ((uint32_t)0x00000020)        /*!< Bit 1 */
+#define  FSMC_BTR4_ADDHLD_2                  ((uint32_t)0x00000040)        /*!< Bit 2 */
+#define  FSMC_BTR4_ADDHLD_3                  ((uint32_t)0x00000080)        /*!< Bit 3 */
+
+#define  FSMC_BTR4_DATAST                    ((uint32_t)0x0000FF00)        /*!< DATAST [3:0] bits (Data-phase duration) */
+#define  FSMC_BTR4_DATAST_0                  ((uint32_t)0x00000100)        /*!< Bit 0 */
+#define  FSMC_BTR4_DATAST_1                  ((uint32_t)0x00000200)        /*!< Bit 1 */
+#define  FSMC_BTR4_DATAST_2                  ((uint32_t)0x00000400)        /*!< Bit 2 */
+#define  FSMC_BTR4_DATAST_3                  ((uint32_t)0x00000800)        /*!< Bit 3 */
+
+#define  FSMC_BTR4_BUSTURN                   ((uint32_t)0x000F0000)        /*!< BUSTURN[3:0] bits (Bus turnaround phase duration) */
+#define  FSMC_BTR4_BUSTURN_0                 ((uint32_t)0x00010000)        /*!< Bit 0 */
+#define  FSMC_BTR4_BUSTURN_1                 ((uint32_t)0x00020000)        /*!< Bit 1 */
+#define  FSMC_BTR4_BUSTURN_2                 ((uint32_t)0x00040000)        /*!< Bit 2 */
+#define  FSMC_BTR4_BUSTURN_3                 ((uint32_t)0x00080000)        /*!< Bit 3 */
+
+#define  FSMC_BTR4_CLKDIV                    ((uint32_t)0x00F00000)        /*!< CLKDIV[3:0] bits (Clock divide ratio) */
+#define  FSMC_BTR4_CLKDIV_0                  ((uint32_t)0x00100000)        /*!< Bit 0 */
+#define  FSMC_BTR4_CLKDIV_1                  ((uint32_t)0x00200000)        /*!< Bit 1 */
+#define  FSMC_BTR4_CLKDIV_2                  ((uint32_t)0x00400000)        /*!< Bit 2 */
+#define  FSMC_BTR4_CLKDIV_3                  ((uint32_t)0x00800000)        /*!< Bit 3 */
+
+#define  FSMC_BTR4_DATLAT                    ((uint32_t)0x0F000000)        /*!< DATLA[3:0] bits (Data latency) */
+#define  FSMC_BTR4_DATLAT_0                  ((uint32_t)0x01000000)        /*!< Bit 0 */
+#define  FSMC_BTR4_DATLAT_1                  ((uint32_t)0x02000000)        /*!< Bit 1 */
+#define  FSMC_BTR4_DATLAT_2                  ((uint32_t)0x04000000)        /*!< Bit 2 */
+#define  FSMC_BTR4_DATLAT_3                  ((uint32_t)0x08000000)        /*!< Bit 3 */
+
+#define  FSMC_BTR4_ACCMOD                    ((uint32_t)0x30000000)        /*!< ACCMOD[1:0] bits (Access mode) */
+#define  FSMC_BTR4_ACCMOD_0                  ((uint32_t)0x10000000)        /*!< Bit 0 */
+#define  FSMC_BTR4_ACCMOD_1                  ((uint32_t)0x20000000)        /*!< Bit 1 */
+
+/******************  Bit definition for FSMC_BWTR1 register  ******************/
+#define  FSMC_BWTR1_ADDSET                   ((uint32_t)0x0000000F)        /*!< ADDSET[3:0] bits (Address setup phase duration) */
+#define  FSMC_BWTR1_ADDSET_0                 ((uint32_t)0x00000001)        /*!< Bit 0 */
+#define  FSMC_BWTR1_ADDSET_1                 ((uint32_t)0x00000002)        /*!< Bit 1 */
+#define  FSMC_BWTR1_ADDSET_2                 ((uint32_t)0x00000004)        /*!< Bit 2 */
+#define  FSMC_BWTR1_ADDSET_3                 ((uint32_t)0x00000008)        /*!< Bit 3 */
+
+#define  FSMC_BWTR1_ADDHLD                   ((uint32_t)0x000000F0)        /*!< ADDHLD[3:0] bits (Address-hold phase duration) */
+#define  FSMC_BWTR1_ADDHLD_0                 ((uint32_t)0x00000010)        /*!< Bit 0 */
+#define  FSMC_BWTR1_ADDHLD_1                 ((uint32_t)0x00000020)        /*!< Bit 1 */
+#define  FSMC_BWTR1_ADDHLD_2                 ((uint32_t)0x00000040)        /*!< Bit 2 */
+#define  FSMC_BWTR1_ADDHLD_3                 ((uint32_t)0x00000080)        /*!< Bit 3 */
+
+#define  FSMC_BWTR1_DATAST                   ((uint32_t)0x0000FF00)        /*!< DATAST [3:0] bits (Data-phase duration) */
+#define  FSMC_BWTR1_DATAST_0                 ((uint32_t)0x00000100)        /*!< Bit 0 */
+#define  FSMC_BWTR1_DATAST_1                 ((uint32_t)0x00000200)        /*!< Bit 1 */
+#define  FSMC_BWTR1_DATAST_2                 ((uint32_t)0x00000400)        /*!< Bit 2 */
+#define  FSMC_BWTR1_DATAST_3                 ((uint32_t)0x00000800)        /*!< Bit 3 */
+
+#define  FSMC_BWTR1_CLKDIV                   ((uint32_t)0x00F00000)        /*!< CLKDIV[3:0] bits (Clock divide ratio) */
+#define  FSMC_BWTR1_CLKDIV_0                 ((uint32_t)0x00100000)        /*!< Bit 0 */
+#define  FSMC_BWTR1_CLKDIV_1                 ((uint32_t)0x00200000)        /*!< Bit 1 */
+#define  FSMC_BWTR1_CLKDIV_2                 ((uint32_t)0x00400000)        /*!< Bit 2 */
+#define  FSMC_BWTR1_CLKDIV_3                 ((uint32_t)0x00800000)        /*!< Bit 3 */
+
+#define  FSMC_BWTR1_DATLAT                   ((uint32_t)0x0F000000)        /*!< DATLA[3:0] bits (Data latency) */
+#define  FSMC_BWTR1_DATLAT_0                 ((uint32_t)0x01000000)        /*!< Bit 0 */
+#define  FSMC_BWTR1_DATLAT_1                 ((uint32_t)0x02000000)        /*!< Bit 1 */
+#define  FSMC_BWTR1_DATLAT_2                 ((uint32_t)0x04000000)        /*!< Bit 2 */
+#define  FSMC_BWTR1_DATLAT_3                 ((uint32_t)0x08000000)        /*!< Bit 3 */
+
+#define  FSMC_BWTR1_ACCMOD                   ((uint32_t)0x30000000)        /*!< ACCMOD[1:0] bits (Access mode) */
+#define  FSMC_BWTR1_ACCMOD_0                 ((uint32_t)0x10000000)        /*!< Bit 0 */
+#define  FSMC_BWTR1_ACCMOD_1                 ((uint32_t)0x20000000)        /*!< Bit 1 */
+
+/******************  Bit definition for FSMC_BWTR2 register  ******************/
+#define  FSMC_BWTR2_ADDSET                   ((uint32_t)0x0000000F)        /*!< ADDSET[3:0] bits (Address setup phase duration) */
+#define  FSMC_BWTR2_ADDSET_0                 ((uint32_t)0x00000001)        /*!< Bit 0 */
+#define  FSMC_BWTR2_ADDSET_1                 ((uint32_t)0x00000002)        /*!< Bit 1 */
+#define  FSMC_BWTR2_ADDSET_2                 ((uint32_t)0x00000004)        /*!< Bit 2 */
+#define  FSMC_BWTR2_ADDSET_3                 ((uint32_t)0x00000008)        /*!< Bit 3 */
+
+#define  FSMC_BWTR2_ADDHLD                   ((uint32_t)0x000000F0)        /*!< ADDHLD[3:0] bits (Address-hold phase duration) */
+#define  FSMC_BWTR2_ADDHLD_0                 ((uint32_t)0x00000010)        /*!< Bit 0 */
+#define  FSMC_BWTR2_ADDHLD_1                 ((uint32_t)0x00000020)        /*!< Bit 1 */
+#define  FSMC_BWTR2_ADDHLD_2                 ((uint32_t)0x00000040)        /*!< Bit 2 */
+#define  FSMC_BWTR2_ADDHLD_3                 ((uint32_t)0x00000080)        /*!< Bit 3 */
+
+#define  FSMC_BWTR2_DATAST                   ((uint32_t)0x0000FF00)        /*!< DATAST [3:0] bits (Data-phase duration) */
+#define  FSMC_BWTR2_DATAST_0                 ((uint32_t)0x00000100)        /*!< Bit 0 */
+#define  FSMC_BWTR2_DATAST_1                 ((uint32_t)0x00000200)        /*!< Bit 1 */
+#define  FSMC_BWTR2_DATAST_2                 ((uint32_t)0x00000400)        /*!< Bit 2 */
+#define  FSMC_BWTR2_DATAST_3                 ((uint32_t)0x00000800)        /*!< Bit 3 */
+
+#define  FSMC_BWTR2_CLKDIV                   ((uint32_t)0x00F00000)        /*!< CLKDIV[3:0] bits (Clock divide ratio) */
+#define  FSMC_BWTR2_CLKDIV_0                 ((uint32_t)0x00100000)        /*!< Bit 0 */
+#define  FSMC_BWTR2_CLKDIV_1                 ((uint32_t)0x00200000)        /*!< Bit 1*/
+#define  FSMC_BWTR2_CLKDIV_2                 ((uint32_t)0x00400000)        /*!< Bit 2 */
+#define  FSMC_BWTR2_CLKDIV_3                 ((uint32_t)0x00800000)        /*!< Bit 3 */
+
+#define  FSMC_BWTR2_DATLAT                   ((uint32_t)0x0F000000)        /*!< DATLA[3:0] bits (Data latency) */
+#define  FSMC_BWTR2_DATLAT_0                 ((uint32_t)0x01000000)        /*!< Bit 0 */
+#define  FSMC_BWTR2_DATLAT_1                 ((uint32_t)0x02000000)        /*!< Bit 1 */
+#define  FSMC_BWTR2_DATLAT_2                 ((uint32_t)0x04000000)        /*!< Bit 2 */
+#define  FSMC_BWTR2_DATLAT_3                 ((uint32_t)0x08000000)        /*!< Bit 3 */
+
+#define  FSMC_BWTR2_ACCMOD                   ((uint32_t)0x30000000)        /*!< ACCMOD[1:0] bits (Access mode) */
+#define  FSMC_BWTR2_ACCMOD_0                 ((uint32_t)0x10000000)        /*!< Bit 0 */
+#define  FSMC_BWTR2_ACCMOD_1                 ((uint32_t)0x20000000)        /*!< Bit 1 */
+
+/******************  Bit definition for FSMC_BWTR3 register  ******************/
+#define  FSMC_BWTR3_ADDSET                   ((uint32_t)0x0000000F)        /*!< ADDSET[3:0] bits (Address setup phase duration) */
+#define  FSMC_BWTR3_ADDSET_0                 ((uint32_t)0x00000001)        /*!< Bit 0 */
+#define  FSMC_BWTR3_ADDSET_1                 ((uint32_t)0x00000002)        /*!< Bit 1 */
+#define  FSMC_BWTR3_ADDSET_2                 ((uint32_t)0x00000004)        /*!< Bit 2 */
+#define  FSMC_BWTR3_ADDSET_3                 ((uint32_t)0x00000008)        /*!< Bit 3 */
+
+#define  FSMC_BWTR3_ADDHLD                   ((uint32_t)0x000000F0)        /*!< ADDHLD[3:0] bits (Address-hold phase duration) */
+#define  FSMC_BWTR3_ADDHLD_0                 ((uint32_t)0x00000010)        /*!< Bit 0 */
+#define  FSMC_BWTR3_ADDHLD_1                 ((uint32_t)0x00000020)        /*!< Bit 1 */
+#define  FSMC_BWTR3_ADDHLD_2                 ((uint32_t)0x00000040)        /*!< Bit 2 */
+#define  FSMC_BWTR3_ADDHLD_3                 ((uint32_t)0x00000080)        /*!< Bit 3 */
+
+#define  FSMC_BWTR3_DATAST                   ((uint32_t)0x0000FF00)        /*!< DATAST [3:0] bits (Data-phase duration) */
+#define  FSMC_BWTR3_DATAST_0                 ((uint32_t)0x00000100)        /*!< Bit 0 */
+#define  FSMC_BWTR3_DATAST_1                 ((uint32_t)0x00000200)        /*!< Bit 1 */
+#define  FSMC_BWTR3_DATAST_2                 ((uint32_t)0x00000400)        /*!< Bit 2 */
+#define  FSMC_BWTR3_DATAST_3                 ((uint32_t)0x00000800)        /*!< Bit 3 */
+
+#define  FSMC_BWTR3_CLKDIV                   ((uint32_t)0x00F00000)        /*!< CLKDIV[3:0] bits (Clock divide ratio) */
+#define  FSMC_BWTR3_CLKDIV_0                 ((uint32_t)0x00100000)        /*!< Bit 0 */
+#define  FSMC_BWTR3_CLKDIV_1                 ((uint32_t)0x00200000)        /*!< Bit 1 */
+#define  FSMC_BWTR3_CLKDIV_2                 ((uint32_t)0x00400000)        /*!< Bit 2 */
+#define  FSMC_BWTR3_CLKDIV_3                 ((uint32_t)0x00800000)        /*!< Bit 3 */
+
+#define  FSMC_BWTR3_DATLAT                   ((uint32_t)0x0F000000)        /*!< DATLA[3:0] bits (Data latency) */
+#define  FSMC_BWTR3_DATLAT_0                 ((uint32_t)0x01000000)        /*!< Bit 0 */
+#define  FSMC_BWTR3_DATLAT_1                 ((uint32_t)0x02000000)        /*!< Bit 1 */
+#define  FSMC_BWTR3_DATLAT_2                 ((uint32_t)0x04000000)        /*!< Bit 2 */
+#define  FSMC_BWTR3_DATLAT_3                 ((uint32_t)0x08000000)        /*!< Bit 3 */
+
+#define  FSMC_BWTR3_ACCMOD                   ((uint32_t)0x30000000)        /*!< ACCMOD[1:0] bits (Access mode) */
+#define  FSMC_BWTR3_ACCMOD_0                 ((uint32_t)0x10000000)        /*!< Bit 0 */
+#define  FSMC_BWTR3_ACCMOD_1                 ((uint32_t)0x20000000)        /*!< Bit 1 */
+
+/******************  Bit definition for FSMC_BWTR4 register  ******************/
+#define  FSMC_BWTR4_ADDSET                   ((uint32_t)0x0000000F)        /*!< ADDSET[3:0] bits (Address setup phase duration) */
+#define  FSMC_BWTR4_ADDSET_0                 ((uint32_t)0x00000001)        /*!< Bit 0 */
+#define  FSMC_BWTR4_ADDSET_1                 ((uint32_t)0x00000002)        /*!< Bit 1 */
+#define  FSMC_BWTR4_ADDSET_2                 ((uint32_t)0x00000004)        /*!< Bit 2 */
+#define  FSMC_BWTR4_ADDSET_3                 ((uint32_t)0x00000008)        /*!< Bit 3 */
+
+#define  FSMC_BWTR4_ADDHLD                   ((uint32_t)0x000000F0)        /*!< ADDHLD[3:0] bits (Address-hold phase duration) */
+#define  FSMC_BWTR4_ADDHLD_0                 ((uint32_t)0x00000010)        /*!< Bit 0 */
+#define  FSMC_BWTR4_ADDHLD_1                 ((uint32_t)0x00000020)        /*!< Bit 1 */
+#define  FSMC_BWTR4_ADDHLD_2                 ((uint32_t)0x00000040)        /*!< Bit 2 */
+#define  FSMC_BWTR4_ADDHLD_3                 ((uint32_t)0x00000080)        /*!< Bit 3 */
+
+#define  FSMC_BWTR4_DATAST                   ((uint32_t)0x0000FF00)        /*!< DATAST [3:0] bits (Data-phase duration) */
+#define  FSMC_BWTR4_DATAST_0                 ((uint32_t)0x00000100)        /*!< Bit 0 */
+#define  FSMC_BWTR4_DATAST_1                 ((uint32_t)0x00000200)        /*!< Bit 1 */
+#define  FSMC_BWTR4_DATAST_2                 ((uint32_t)0x00000400)        /*!< Bit 2 */
+#define  FSMC_BWTR4_DATAST_3                 ((uint32_t)0x00000800)        /*!< Bit 3 */
+
+#define  FSMC_BWTR4_CLKDIV                   ((uint32_t)0x00F00000)        /*!< CLKDIV[3:0] bits (Clock divide ratio) */
+#define  FSMC_BWTR4_CLKDIV_0                 ((uint32_t)0x00100000)        /*!< Bit 0 */
+#define  FSMC_BWTR4_CLKDIV_1                 ((uint32_t)0x00200000)        /*!< Bit 1 */
+#define  FSMC_BWTR4_CLKDIV_2                 ((uint32_t)0x00400000)        /*!< Bit 2 */
+#define  FSMC_BWTR4_CLKDIV_3                 ((uint32_t)0x00800000)        /*!< Bit 3 */
+
+#define  FSMC_BWTR4_DATLAT                   ((uint32_t)0x0F000000)        /*!< DATLA[3:0] bits (Data latency) */
+#define  FSMC_BWTR4_DATLAT_0                 ((uint32_t)0x01000000)        /*!< Bit 0 */
+#define  FSMC_BWTR4_DATLAT_1                 ((uint32_t)0x02000000)        /*!< Bit 1 */
+#define  FSMC_BWTR4_DATLAT_2                 ((uint32_t)0x04000000)        /*!< Bit 2 */
+#define  FSMC_BWTR4_DATLAT_3                 ((uint32_t)0x08000000)        /*!< Bit 3 */
+
+#define  FSMC_BWTR4_ACCMOD                   ((uint32_t)0x30000000)        /*!< ACCMOD[1:0] bits (Access mode) */
+#define  FSMC_BWTR4_ACCMOD_0                 ((uint32_t)0x10000000)        /*!< Bit 0 */
+#define  FSMC_BWTR4_ACCMOD_1                 ((uint32_t)0x20000000)        /*!< Bit 1 */
+
+/******************  Bit definition for FSMC_PCR2 register  *******************/
+#define  FSMC_PCR2_PWAITEN                   ((uint32_t)0x00000002)        /*!< Wait feature enable bit */
+#define  FSMC_PCR2_PBKEN                     ((uint32_t)0x00000004)        /*!< PC Card/NAND Flash memory bank enable bit */
+#define  FSMC_PCR2_PTYP                      ((uint32_t)0x00000008)        /*!< Memory type */
+
+#define  FSMC_PCR2_PWID                      ((uint32_t)0x00000030)        /*!< PWID[1:0] bits (NAND Flash databus width) */
+#define  FSMC_PCR2_PWID_0                    ((uint32_t)0x00000010)        /*!< Bit 0 */
+#define  FSMC_PCR2_PWID_1                    ((uint32_t)0x00000020)        /*!< Bit 1 */
+
+#define  FSMC_PCR2_ECCEN                     ((uint32_t)0x00000040)        /*!< ECC computation logic enable bit */
+
+#define  FSMC_PCR2_TCLR                      ((uint32_t)0x00001E00)        /*!< TCLR[3:0] bits (CLE to RE delay) */
+#define  FSMC_PCR2_TCLR_0                    ((uint32_t)0x00000200)        /*!< Bit 0 */
+#define  FSMC_PCR2_TCLR_1                    ((uint32_t)0x00000400)        /*!< Bit 1 */
+#define  FSMC_PCR2_TCLR_2                    ((uint32_t)0x00000800)        /*!< Bit 2 */
+#define  FSMC_PCR2_TCLR_3                    ((uint32_t)0x00001000)        /*!< Bit 3 */
+
+#define  FSMC_PCR2_TAR                       ((uint32_t)0x0001E000)        /*!< TAR[3:0] bits (ALE to RE delay) */
+#define  FSMC_PCR2_TAR_0                     ((uint32_t)0x00002000)        /*!< Bit 0 */
+#define  FSMC_PCR2_TAR_1                     ((uint32_t)0x00004000)        /*!< Bit 1 */
+#define  FSMC_PCR2_TAR_2                     ((uint32_t)0x00008000)        /*!< Bit 2 */
+#define  FSMC_PCR2_TAR_3                     ((uint32_t)0x00010000)        /*!< Bit 3 */
+
+#define  FSMC_PCR2_ECCPS                     ((uint32_t)0x000E0000)        /*!< ECCPS[1:0] bits (ECC page size) */
+#define  FSMC_PCR2_ECCPS_0                   ((uint32_t)0x00020000)        /*!< Bit 0 */
+#define  FSMC_PCR2_ECCPS_1                   ((uint32_t)0x00040000)        /*!< Bit 1 */
+#define  FSMC_PCR2_ECCPS_2                   ((uint32_t)0x00080000)        /*!< Bit 2 */
+
+/******************  Bit definition for FSMC_PCR3 register  *******************/
+#define  FSMC_PCR3_PWAITEN                   ((uint32_t)0x00000002)        /*!< Wait feature enable bit */
+#define  FSMC_PCR3_PBKEN                     ((uint32_t)0x00000004)        /*!< PC Card/NAND Flash memory bank enable bit */
+#define  FSMC_PCR3_PTYP                      ((uint32_t)0x00000008)        /*!< Memory type */
+
+#define  FSMC_PCR3_PWID                      ((uint32_t)0x00000030)        /*!< PWID[1:0] bits (NAND Flash databus width) */
+#define  FSMC_PCR3_PWID_0                    ((uint32_t)0x00000010)        /*!< Bit 0 */
+#define  FSMC_PCR3_PWID_1                    ((uint32_t)0x00000020)        /*!< Bit 1 */
+
+#define  FSMC_PCR3_ECCEN                     ((uint32_t)0x00000040)        /*!< ECC computation logic enable bit */
+
+#define  FSMC_PCR3_TCLR                      ((uint32_t)0x00001E00)        /*!< TCLR[3:0] bits (CLE to RE delay) */
+#define  FSMC_PCR3_TCLR_0                    ((uint32_t)0x00000200)        /*!< Bit 0 */
+#define  FSMC_PCR3_TCLR_1                    ((uint32_t)0x00000400)        /*!< Bit 1 */
+#define  FSMC_PCR3_TCLR_2                    ((uint32_t)0x00000800)        /*!< Bit 2 */
+#define  FSMC_PCR3_TCLR_3                    ((uint32_t)0x00001000)        /*!< Bit 3 */
+
+#define  FSMC_PCR3_TAR                       ((uint32_t)0x0001E000)        /*!< TAR[3:0] bits (ALE to RE delay) */
+#define  FSMC_PCR3_TAR_0                     ((uint32_t)0x00002000)        /*!< Bit 0 */
+#define  FSMC_PCR3_TAR_1                     ((uint32_t)0x00004000)        /*!< Bit 1 */
+#define  FSMC_PCR3_TAR_2                     ((uint32_t)0x00008000)        /*!< Bit 2 */
+#define  FSMC_PCR3_TAR_3                     ((uint32_t)0x00010000)        /*!< Bit 3 */
+
+#define  FSMC_PCR3_ECCPS                     ((uint32_t)0x000E0000)        /*!< ECCPS[2:0] bits (ECC page size) */
+#define  FSMC_PCR3_ECCPS_0                   ((uint32_t)0x00020000)        /*!< Bit 0 */
+#define  FSMC_PCR3_ECCPS_1                   ((uint32_t)0x00040000)        /*!< Bit 1 */
+#define  FSMC_PCR3_ECCPS_2                   ((uint32_t)0x00080000)        /*!< Bit 2 */
+
+/******************  Bit definition for FSMC_PCR4 register  *******************/
+#define  FSMC_PCR4_PWAITEN                   ((uint32_t)0x00000002)        /*!< Wait feature enable bit */
+#define  FSMC_PCR4_PBKEN                     ((uint32_t)0x00000004)        /*!< PC Card/NAND Flash memory bank enable bit */
+#define  FSMC_PCR4_PTYP                      ((uint32_t)0x00000008)        /*!< Memory type */
+
+#define  FSMC_PCR4_PWID                      ((uint32_t)0x00000030)        /*!< PWID[1:0] bits (NAND Flash databus width) */
+#define  FSMC_PCR4_PWID_0                    ((uint32_t)0x00000010)        /*!< Bit 0 */
+#define  FSMC_PCR4_PWID_1                    ((uint32_t)0x00000020)        /*!< Bit 1 */
+
+#define  FSMC_PCR4_ECCEN                     ((uint32_t)0x00000040)        /*!< ECC computation logic enable bit */
+
+#define  FSMC_PCR4_TCLR                      ((uint32_t)0x00001E00)        /*!< TCLR[3:0] bits (CLE to RE delay) */
+#define  FSMC_PCR4_TCLR_0                    ((uint32_t)0x00000200)        /*!< Bit 0 */
+#define  FSMC_PCR4_TCLR_1                    ((uint32_t)0x00000400)        /*!< Bit 1 */
+#define  FSMC_PCR4_TCLR_2                    ((uint32_t)0x00000800)        /*!< Bit 2 */
+#define  FSMC_PCR4_TCLR_3                    ((uint32_t)0x00001000)        /*!< Bit 3 */
+
+#define  FSMC_PCR4_TAR                       ((uint32_t)0x0001E000)        /*!< TAR[3:0] bits (ALE to RE delay) */
+#define  FSMC_PCR4_TAR_0                     ((uint32_t)0x00002000)        /*!< Bit 0 */
+#define  FSMC_PCR4_TAR_1                     ((uint32_t)0x00004000)        /*!< Bit 1 */
+#define  FSMC_PCR4_TAR_2                     ((uint32_t)0x00008000)        /*!< Bit 2 */
+#define  FSMC_PCR4_TAR_3                     ((uint32_t)0x00010000)        /*!< Bit 3 */
+
+#define  FSMC_PCR4_ECCPS                     ((uint32_t)0x000E0000)        /*!< ECCPS[2:0] bits (ECC page size) */
+#define  FSMC_PCR4_ECCPS_0                   ((uint32_t)0x00020000)        /*!< Bit 0 */
+#define  FSMC_PCR4_ECCPS_1                   ((uint32_t)0x00040000)        /*!< Bit 1 */
+#define  FSMC_PCR4_ECCPS_2                   ((uint32_t)0x00080000)        /*!< Bit 2 */
+
+/*******************  Bit definition for FSMC_SR2 register  *******************/
+#define  FSMC_SR2_IRS                        ((uint8_t)0x01)               /*!< Interrupt Rising Edge status */
+#define  FSMC_SR2_ILS                        ((uint8_t)0x02)               /*!< Interrupt Level status */
+#define  FSMC_SR2_IFS                        ((uint8_t)0x04)               /*!< Interrupt Falling Edge status */
+#define  FSMC_SR2_IREN                       ((uint8_t)0x08)               /*!< Interrupt Rising Edge detection Enable bit */
+#define  FSMC_SR2_ILEN                       ((uint8_t)0x10)               /*!< Interrupt Level detection Enable bit */
+#define  FSMC_SR2_IFEN                       ((uint8_t)0x20)               /*!< Interrupt Falling Edge detection Enable bit */
+#define  FSMC_SR2_FEMPT                      ((uint8_t)0x40)               /*!< FIFO empty */
+
+/*******************  Bit definition for FSMC_SR3 register  *******************/
+#define  FSMC_SR3_IRS                        ((uint8_t)0x01)               /*!< Interrupt Rising Edge status */
+#define  FSMC_SR3_ILS                        ((uint8_t)0x02)               /*!< Interrupt Level status */
+#define  FSMC_SR3_IFS                        ((uint8_t)0x04)               /*!< Interrupt Falling Edge status */
+#define  FSMC_SR3_IREN                       ((uint8_t)0x08)               /*!< Interrupt Rising Edge detection Enable bit */
+#define  FSMC_SR3_ILEN                       ((uint8_t)0x10)               /*!< Interrupt Level detection Enable bit */
+#define  FSMC_SR3_IFEN                       ((uint8_t)0x20)               /*!< Interrupt Falling Edge detection Enable bit */
+#define  FSMC_SR3_FEMPT                      ((uint8_t)0x40)               /*!< FIFO empty */
+
+/*******************  Bit definition for FSMC_SR4 register  *******************/
+#define  FSMC_SR4_IRS                        ((uint8_t)0x01)               /*!< Interrupt Rising Edge status */
+#define  FSMC_SR4_ILS                        ((uint8_t)0x02)               /*!< Interrupt Level status */
+#define  FSMC_SR4_IFS                        ((uint8_t)0x04)               /*!< Interrupt Falling Edge status */
+#define  FSMC_SR4_IREN                       ((uint8_t)0x08)               /*!< Interrupt Rising Edge detection Enable bit */
+#define  FSMC_SR4_ILEN                       ((uint8_t)0x10)               /*!< Interrupt Level detection Enable bit */
+#define  FSMC_SR4_IFEN                       ((uint8_t)0x20)               /*!< Interrupt Falling Edge detection Enable bit */
+#define  FSMC_SR4_FEMPT                      ((uint8_t)0x40)               /*!< FIFO empty */
+
+/******************  Bit definition for FSMC_PMEM2 register  ******************/
+#define  FSMC_PMEM2_MEMSET2                  ((uint32_t)0x000000FF)        /*!< MEMSET2[7:0] bits (Common memory 2 setup time) */
+#define  FSMC_PMEM2_MEMSET2_0                ((uint32_t)0x00000001)        /*!< Bit 0 */
+#define  FSMC_PMEM2_MEMSET2_1                ((uint32_t)0x00000002)        /*!< Bit 1 */
+#define  FSMC_PMEM2_MEMSET2_2                ((uint32_t)0x00000004)        /*!< Bit 2 */
+#define  FSMC_PMEM2_MEMSET2_3                ((uint32_t)0x00000008)        /*!< Bit 3 */
+#define  FSMC_PMEM2_MEMSET2_4                ((uint32_t)0x00000010)        /*!< Bit 4 */
+#define  FSMC_PMEM2_MEMSET2_5                ((uint32_t)0x00000020)        /*!< Bit 5 */
+#define  FSMC_PMEM2_MEMSET2_6                ((uint32_t)0x00000040)        /*!< Bit 6 */
+#define  FSMC_PMEM2_MEMSET2_7                ((uint32_t)0x00000080)        /*!< Bit 7 */
+
+#define  FSMC_PMEM2_MEMWAIT2                 ((uint32_t)0x0000FF00)        /*!< MEMWAIT2[7:0] bits (Common memory 2 wait time) */
+#define  FSMC_PMEM2_MEMWAIT2_0               ((uint32_t)0x00000100)        /*!< Bit 0 */
+#define  FSMC_PMEM2_MEMWAIT2_1               ((uint32_t)0x00000200)        /*!< Bit 1 */
+#define  FSMC_PMEM2_MEMWAIT2_2               ((uint32_t)0x00000400)        /*!< Bit 2 */
+#define  FSMC_PMEM2_MEMWAIT2_3               ((uint32_t)0x00000800)        /*!< Bit 3 */
+#define  FSMC_PMEM2_MEMWAIT2_4               ((uint32_t)0x00001000)        /*!< Bit 4 */
+#define  FSMC_PMEM2_MEMWAIT2_5               ((uint32_t)0x00002000)        /*!< Bit 5 */
+#define  FSMC_PMEM2_MEMWAIT2_6               ((uint32_t)0x00004000)        /*!< Bit 6 */
+#define  FSMC_PMEM2_MEMWAIT2_7               ((uint32_t)0x00008000)        /*!< Bit 7 */
+
+#define  FSMC_PMEM2_MEMHOLD2                 ((uint32_t)0x00FF0000)        /*!< MEMHOLD2[7:0] bits (Common memory 2 hold time) */
+#define  FSMC_PMEM2_MEMHOLD2_0               ((uint32_t)0x00010000)        /*!< Bit 0 */
+#define  FSMC_PMEM2_MEMHOLD2_1               ((uint32_t)0x00020000)        /*!< Bit 1 */
+#define  FSMC_PMEM2_MEMHOLD2_2               ((uint32_t)0x00040000)        /*!< Bit 2 */
+#define  FSMC_PMEM2_MEMHOLD2_3               ((uint32_t)0x00080000)        /*!< Bit 3 */
+#define  FSMC_PMEM2_MEMHOLD2_4               ((uint32_t)0x00100000)        /*!< Bit 4 */
+#define  FSMC_PMEM2_MEMHOLD2_5               ((uint32_t)0x00200000)        /*!< Bit 5 */
+#define  FSMC_PMEM2_MEMHOLD2_6               ((uint32_t)0x00400000)        /*!< Bit 6 */
+#define  FSMC_PMEM2_MEMHOLD2_7               ((uint32_t)0x00800000)        /*!< Bit 7 */
+
+#define  FSMC_PMEM2_MEMHIZ2                  ((uint32_t)0xFF000000)        /*!< MEMHIZ2[7:0] bits (Common memory 2 databus HiZ time) */
+#define  FSMC_PMEM2_MEMHIZ2_0                ((uint32_t)0x01000000)        /*!< Bit 0 */
+#define  FSMC_PMEM2_MEMHIZ2_1                ((uint32_t)0x02000000)        /*!< Bit 1 */
+#define  FSMC_PMEM2_MEMHIZ2_2                ((uint32_t)0x04000000)        /*!< Bit 2 */
+#define  FSMC_PMEM2_MEMHIZ2_3                ((uint32_t)0x08000000)        /*!< Bit 3 */
+#define  FSMC_PMEM2_MEMHIZ2_4                ((uint32_t)0x10000000)        /*!< Bit 4 */
+#define  FSMC_PMEM2_MEMHIZ2_5                ((uint32_t)0x20000000)        /*!< Bit 5 */
+#define  FSMC_PMEM2_MEMHIZ2_6                ((uint32_t)0x40000000)        /*!< Bit 6 */
+#define  FSMC_PMEM2_MEMHIZ2_7                ((uint32_t)0x80000000)        /*!< Bit 7 */
+
+/******************  Bit definition for FSMC_PMEM3 register  ******************/
+#define  FSMC_PMEM3_MEMSET3                  ((uint32_t)0x000000FF)        /*!< MEMSET3[7:0] bits (Common memory 3 setup time) */
+#define  FSMC_PMEM3_MEMSET3_0                ((uint32_t)0x00000001)        /*!< Bit 0 */
+#define  FSMC_PMEM3_MEMSET3_1                ((uint32_t)0x00000002)        /*!< Bit 1 */
+#define  FSMC_PMEM3_MEMSET3_2                ((uint32_t)0x00000004)        /*!< Bit 2 */
+#define  FSMC_PMEM3_MEMSET3_3                ((uint32_t)0x00000008)        /*!< Bit 3 */
+#define  FSMC_PMEM3_MEMSET3_4                ((uint32_t)0x00000010)        /*!< Bit 4 */
+#define  FSMC_PMEM3_MEMSET3_5                ((uint32_t)0x00000020)        /*!< Bit 5 */
+#define  FSMC_PMEM3_MEMSET3_6                ((uint32_t)0x00000040)        /*!< Bit 6 */
+#define  FSMC_PMEM3_MEMSET3_7                ((uint32_t)0x00000080)        /*!< Bit 7 */
+
+#define  FSMC_PMEM3_MEMWAIT3                 ((uint32_t)0x0000FF00)        /*!< MEMWAIT3[7:0] bits (Common memory 3 wait time) */
+#define  FSMC_PMEM3_MEMWAIT3_0               ((uint32_t)0x00000100)        /*!< Bit 0 */
+#define  FSMC_PMEM3_MEMWAIT3_1               ((uint32_t)0x00000200)        /*!< Bit 1 */
+#define  FSMC_PMEM3_MEMWAIT3_2               ((uint32_t)0x00000400)        /*!< Bit 2 */
+#define  FSMC_PMEM3_MEMWAIT3_3               ((uint32_t)0x00000800)        /*!< Bit 3 */
+#define  FSMC_PMEM3_MEMWAIT3_4               ((uint32_t)0x00001000)        /*!< Bit 4 */
+#define  FSMC_PMEM3_MEMWAIT3_5               ((uint32_t)0x00002000)        /*!< Bit 5 */
+#define  FSMC_PMEM3_MEMWAIT3_6               ((uint32_t)0x00004000)        /*!< Bit 6 */
+#define  FSMC_PMEM3_MEMWAIT3_7               ((uint32_t)0x00008000)        /*!< Bit 7 */
+
+#define  FSMC_PMEM3_MEMHOLD3                 ((uint32_t)0x00FF0000)        /*!< MEMHOLD3[7:0] bits (Common memory 3 hold time) */
+#define  FSMC_PMEM3_MEMHOLD3_0               ((uint32_t)0x00010000)        /*!< Bit 0 */
+#define  FSMC_PMEM3_MEMHOLD3_1               ((uint32_t)0x00020000)        /*!< Bit 1 */
+#define  FSMC_PMEM3_MEMHOLD3_2               ((uint32_t)0x00040000)        /*!< Bit 2 */
+#define  FSMC_PMEM3_MEMHOLD3_3               ((uint32_t)0x00080000)        /*!< Bit 3 */
+#define  FSMC_PMEM3_MEMHOLD3_4               ((uint32_t)0x00100000)        /*!< Bit 4 */
+#define  FSMC_PMEM3_MEMHOLD3_5               ((uint32_t)0x00200000)        /*!< Bit 5 */
+#define  FSMC_PMEM3_MEMHOLD3_6               ((uint32_t)0x00400000)        /*!< Bit 6 */
+#define  FSMC_PMEM3_MEMHOLD3_7               ((uint32_t)0x00800000)        /*!< Bit 7 */
+
+#define  FSMC_PMEM3_MEMHIZ3                  ((uint32_t)0xFF000000)        /*!< MEMHIZ3[7:0] bits (Common memory 3 databus HiZ time) */
+#define  FSMC_PMEM3_MEMHIZ3_0                ((uint32_t)0x01000000)        /*!< Bit 0 */
+#define  FSMC_PMEM3_MEMHIZ3_1                ((uint32_t)0x02000000)        /*!< Bit 1 */
+#define  FSMC_PMEM3_MEMHIZ3_2                ((uint32_t)0x04000000)        /*!< Bit 2 */
+#define  FSMC_PMEM3_MEMHIZ3_3                ((uint32_t)0x08000000)        /*!< Bit 3 */
+#define  FSMC_PMEM3_MEMHIZ3_4                ((uint32_t)0x10000000)        /*!< Bit 4 */
+#define  FSMC_PMEM3_MEMHIZ3_5                ((uint32_t)0x20000000)        /*!< Bit 5 */
+#define  FSMC_PMEM3_MEMHIZ3_6                ((uint32_t)0x40000000)        /*!< Bit 6 */
+#define  FSMC_PMEM3_MEMHIZ3_7                ((uint32_t)0x80000000)        /*!< Bit 7 */
+
+/******************  Bit definition for FSMC_PMEM4 register  ******************/
+#define  FSMC_PMEM4_MEMSET4                  ((uint32_t)0x000000FF)        /*!< MEMSET4[7:0] bits (Common memory 4 setup time) */
+#define  FSMC_PMEM4_MEMSET4_0                ((uint32_t)0x00000001)        /*!< Bit 0 */
+#define  FSMC_PMEM4_MEMSET4_1                ((uint32_t)0x00000002)        /*!< Bit 1 */
+#define  FSMC_PMEM4_MEMSET4_2                ((uint32_t)0x00000004)        /*!< Bit 2 */
+#define  FSMC_PMEM4_MEMSET4_3                ((uint32_t)0x00000008)        /*!< Bit 3 */
+#define  FSMC_PMEM4_MEMSET4_4                ((uint32_t)0x00000010)        /*!< Bit 4 */
+#define  FSMC_PMEM4_MEMSET4_5                ((uint32_t)0x00000020)        /*!< Bit 5 */
+#define  FSMC_PMEM4_MEMSET4_6                ((uint32_t)0x00000040)        /*!< Bit 6 */
+#define  FSMC_PMEM4_MEMSET4_7                ((uint32_t)0x00000080)        /*!< Bit 7 */
+
+#define  FSMC_PMEM4_MEMWAIT4                 ((uint32_t)0x0000FF00)        /*!< MEMWAIT4[7:0] bits (Common memory 4 wait time) */
+#define  FSMC_PMEM4_MEMWAIT4_0               ((uint32_t)0x00000100)        /*!< Bit 0 */
+#define  FSMC_PMEM4_MEMWAIT4_1               ((uint32_t)0x00000200)        /*!< Bit 1 */
+#define  FSMC_PMEM4_MEMWAIT4_2               ((uint32_t)0x00000400)        /*!< Bit 2 */
+#define  FSMC_PMEM4_MEMWAIT4_3               ((uint32_t)0x00000800)        /*!< Bit 3 */
+#define  FSMC_PMEM4_MEMWAIT4_4               ((uint32_t)0x00001000)        /*!< Bit 4 */
+#define  FSMC_PMEM4_MEMWAIT4_5               ((uint32_t)0x00002000)        /*!< Bit 5 */
+#define  FSMC_PMEM4_MEMWAIT4_6               ((uint32_t)0x00004000)        /*!< Bit 6 */
+#define  FSMC_PMEM4_MEMWAIT4_7               ((uint32_t)0x00008000)        /*!< Bit 7 */
+
+#define  FSMC_PMEM4_MEMHOLD4                 ((uint32_t)0x00FF0000)        /*!< MEMHOLD4[7:0] bits (Common memory 4 hold time) */
+#define  FSMC_PMEM4_MEMHOLD4_0               ((uint32_t)0x00010000)        /*!< Bit 0 */
+#define  FSMC_PMEM4_MEMHOLD4_1               ((uint32_t)0x00020000)        /*!< Bit 1 */
+#define  FSMC_PMEM4_MEMHOLD4_2               ((uint32_t)0x00040000)        /*!< Bit 2 */
+#define  FSMC_PMEM4_MEMHOLD4_3               ((uint32_t)0x00080000)        /*!< Bit 3 */
+#define  FSMC_PMEM4_MEMHOLD4_4               ((uint32_t)0x00100000)        /*!< Bit 4 */
+#define  FSMC_PMEM4_MEMHOLD4_5               ((uint32_t)0x00200000)        /*!< Bit 5 */
+#define  FSMC_PMEM4_MEMHOLD4_6               ((uint32_t)0x00400000)        /*!< Bit 6 */
+#define  FSMC_PMEM4_MEMHOLD4_7               ((uint32_t)0x00800000)        /*!< Bit 7 */
+
+#define  FSMC_PMEM4_MEMHIZ4                  ((uint32_t)0xFF000000)        /*!< MEMHIZ4[7:0] bits (Common memory 4 databus HiZ time) */
+#define  FSMC_PMEM4_MEMHIZ4_0                ((uint32_t)0x01000000)        /*!< Bit 0 */
+#define  FSMC_PMEM4_MEMHIZ4_1                ((uint32_t)0x02000000)        /*!< Bit 1 */
+#define  FSMC_PMEM4_MEMHIZ4_2                ((uint32_t)0x04000000)        /*!< Bit 2 */
+#define  FSMC_PMEM4_MEMHIZ4_3                ((uint32_t)0x08000000)        /*!< Bit 3 */
+#define  FSMC_PMEM4_MEMHIZ4_4                ((uint32_t)0x10000000)        /*!< Bit 4 */
+#define  FSMC_PMEM4_MEMHIZ4_5                ((uint32_t)0x20000000)        /*!< Bit 5 */
+#define  FSMC_PMEM4_MEMHIZ4_6                ((uint32_t)0x40000000)        /*!< Bit 6 */
+#define  FSMC_PMEM4_MEMHIZ4_7                ((uint32_t)0x80000000)        /*!< Bit 7 */
+
+/******************  Bit definition for FSMC_PATT2 register  ******************/
+#define  FSMC_PATT2_ATTSET2                  ((uint32_t)0x000000FF)        /*!< ATTSET2[7:0] bits (Attribute memory 2 setup time) */
+#define  FSMC_PATT2_ATTSET2_0                ((uint32_t)0x00000001)        /*!< Bit 0 */
+#define  FSMC_PATT2_ATTSET2_1                ((uint32_t)0x00000002)        /*!< Bit 1 */
+#define  FSMC_PATT2_ATTSET2_2                ((uint32_t)0x00000004)        /*!< Bit 2 */
+#define  FSMC_PATT2_ATTSET2_3                ((uint32_t)0x00000008)        /*!< Bit 3 */
+#define  FSMC_PATT2_ATTSET2_4                ((uint32_t)0x00000010)        /*!< Bit 4 */
+#define  FSMC_PATT2_ATTSET2_5                ((uint32_t)0x00000020)        /*!< Bit 5 */
+#define  FSMC_PATT2_ATTSET2_6                ((uint32_t)0x00000040)        /*!< Bit 6 */
+#define  FSMC_PATT2_ATTSET2_7                ((uint32_t)0x00000080)        /*!< Bit 7 */
+
+#define  FSMC_PATT2_ATTWAIT2                 ((uint32_t)0x0000FF00)        /*!< ATTWAIT2[7:0] bits (Attribute memory 2 wait time) */
+#define  FSMC_PATT2_ATTWAIT2_0               ((uint32_t)0x00000100)        /*!< Bit 0 */
+#define  FSMC_PATT2_ATTWAIT2_1               ((uint32_t)0x00000200)        /*!< Bit 1 */
+#define  FSMC_PATT2_ATTWAIT2_2               ((uint32_t)0x00000400)        /*!< Bit 2 */
+#define  FSMC_PATT2_ATTWAIT2_3               ((uint32_t)0x00000800)        /*!< Bit 3 */
+#define  FSMC_PATT2_ATTWAIT2_4               ((uint32_t)0x00001000)        /*!< Bit 4 */
+#define  FSMC_PATT2_ATTWAIT2_5               ((uint32_t)0x00002000)        /*!< Bit 5 */
+#define  FSMC_PATT2_ATTWAIT2_6               ((uint32_t)0x00004000)        /*!< Bit 6 */
+#define  FSMC_PATT2_ATTWAIT2_7               ((uint32_t)0x00008000)        /*!< Bit 7 */
+
+#define  FSMC_PATT2_ATTHOLD2                 ((uint32_t)0x00FF0000)        /*!< ATTHOLD2[7:0] bits (Attribute memory 2 hold time) */
+#define  FSMC_PATT2_ATTHOLD2_0               ((uint32_t)0x00010000)        /*!< Bit 0 */
+#define  FSMC_PATT2_ATTHOLD2_1               ((uint32_t)0x00020000)        /*!< Bit 1 */
+#define  FSMC_PATT2_ATTHOLD2_2               ((uint32_t)0x00040000)        /*!< Bit 2 */
+#define  FSMC_PATT2_ATTHOLD2_3               ((uint32_t)0x00080000)        /*!< Bit 3 */
+#define  FSMC_PATT2_ATTHOLD2_4               ((uint32_t)0x00100000)        /*!< Bit 4 */
+#define  FSMC_PATT2_ATTHOLD2_5               ((uint32_t)0x00200000)        /*!< Bit 5 */
+#define  FSMC_PATT2_ATTHOLD2_6               ((uint32_t)0x00400000)        /*!< Bit 6 */
+#define  FSMC_PATT2_ATTHOLD2_7               ((uint32_t)0x00800000)        /*!< Bit 7 */
+
+#define  FSMC_PATT2_ATTHIZ2                  ((uint32_t)0xFF000000)        /*!< ATTHIZ2[7:0] bits (Attribute memory 2 databus HiZ time) */
+#define  FSMC_PATT2_ATTHIZ2_0                ((uint32_t)0x01000000)        /*!< Bit 0 */
+#define  FSMC_PATT2_ATTHIZ2_1                ((uint32_t)0x02000000)        /*!< Bit 1 */
+#define  FSMC_PATT2_ATTHIZ2_2                ((uint32_t)0x04000000)        /*!< Bit 2 */
+#define  FSMC_PATT2_ATTHIZ2_3                ((uint32_t)0x08000000)        /*!< Bit 3 */
+#define  FSMC_PATT2_ATTHIZ2_4                ((uint32_t)0x10000000)        /*!< Bit 4 */
+#define  FSMC_PATT2_ATTHIZ2_5                ((uint32_t)0x20000000)        /*!< Bit 5 */
+#define  FSMC_PATT2_ATTHIZ2_6                ((uint32_t)0x40000000)        /*!< Bit 6 */
+#define  FSMC_PATT2_ATTHIZ2_7                ((uint32_t)0x80000000)        /*!< Bit 7 */
+
+/******************  Bit definition for FSMC_PATT3 register  ******************/
+#define  FSMC_PATT3_ATTSET3                  ((uint32_t)0x000000FF)        /*!< ATTSET3[7:0] bits (Attribute memory 3 setup time) */
+#define  FSMC_PATT3_ATTSET3_0                ((uint32_t)0x00000001)        /*!< Bit 0 */
+#define  FSMC_PATT3_ATTSET3_1                ((uint32_t)0x00000002)        /*!< Bit 1 */
+#define  FSMC_PATT3_ATTSET3_2                ((uint32_t)0x00000004)        /*!< Bit 2 */
+#define  FSMC_PATT3_ATTSET3_3                ((uint32_t)0x00000008)        /*!< Bit 3 */
+#define  FSMC_PATT3_ATTSET3_4                ((uint32_t)0x00000010)        /*!< Bit 4 */
+#define  FSMC_PATT3_ATTSET3_5                ((uint32_t)0x00000020)        /*!< Bit 5 */
+#define  FSMC_PATT3_ATTSET3_6                ((uint32_t)0x00000040)        /*!< Bit 6 */
+#define  FSMC_PATT3_ATTSET3_7                ((uint32_t)0x00000080)        /*!< Bit 7 */
+
+#define  FSMC_PATT3_ATTWAIT3                 ((uint32_t)0x0000FF00)        /*!< ATTWAIT3[7:0] bits (Attribute memory 3 wait time) */
+#define  FSMC_PATT3_ATTWAIT3_0               ((uint32_t)0x00000100)        /*!< Bit 0 */
+#define  FSMC_PATT3_ATTWAIT3_1               ((uint32_t)0x00000200)        /*!< Bit 1 */
+#define  FSMC_PATT3_ATTWAIT3_2               ((uint32_t)0x00000400)        /*!< Bit 2 */
+#define  FSMC_PATT3_ATTWAIT3_3               ((uint32_t)0x00000800)        /*!< Bit 3 */
+#define  FSMC_PATT3_ATTWAIT3_4               ((uint32_t)0x00001000)        /*!< Bit 4 */
+#define  FSMC_PATT3_ATTWAIT3_5               ((uint32_t)0x00002000)        /*!< Bit 5 */
+#define  FSMC_PATT3_ATTWAIT3_6               ((uint32_t)0x00004000)        /*!< Bit 6 */
+#define  FSMC_PATT3_ATTWAIT3_7               ((uint32_t)0x00008000)        /*!< Bit 7 */
+
+#define  FSMC_PATT3_ATTHOLD3                 ((uint32_t)0x00FF0000)        /*!< ATTHOLD3[7:0] bits (Attribute memory 3 hold time) */
+#define  FSMC_PATT3_ATTHOLD3_0               ((uint32_t)0x00010000)        /*!< Bit 0 */
+#define  FSMC_PATT3_ATTHOLD3_1               ((uint32_t)0x00020000)        /*!< Bit 1 */
+#define  FSMC_PATT3_ATTHOLD3_2               ((uint32_t)0x00040000)        /*!< Bit 2 */
+#define  FSMC_PATT3_ATTHOLD3_3               ((uint32_t)0x00080000)        /*!< Bit 3 */
+#define  FSMC_PATT3_ATTHOLD3_4               ((uint32_t)0x00100000)        /*!< Bit 4 */
+#define  FSMC_PATT3_ATTHOLD3_5               ((uint32_t)0x00200000)        /*!< Bit 5 */
+#define  FSMC_PATT3_ATTHOLD3_6               ((uint32_t)0x00400000)        /*!< Bit 6 */
+#define  FSMC_PATT3_ATTHOLD3_7               ((uint32_t)0x00800000)        /*!< Bit 7 */
+
+#define  FSMC_PATT3_ATTHIZ3                  ((uint32_t)0xFF000000)        /*!< ATTHIZ3[7:0] bits (Attribute memory 3 databus HiZ time) */
+#define  FSMC_PATT3_ATTHIZ3_0                ((uint32_t)0x01000000)        /*!< Bit 0 */
+#define  FSMC_PATT3_ATTHIZ3_1                ((uint32_t)0x02000000)        /*!< Bit 1 */
+#define  FSMC_PATT3_ATTHIZ3_2                ((uint32_t)0x04000000)        /*!< Bit 2 */
+#define  FSMC_PATT3_ATTHIZ3_3                ((uint32_t)0x08000000)        /*!< Bit 3 */
+#define  FSMC_PATT3_ATTHIZ3_4                ((uint32_t)0x10000000)        /*!< Bit 4 */
+#define  FSMC_PATT3_ATTHIZ3_5                ((uint32_t)0x20000000)        /*!< Bit 5 */
+#define  FSMC_PATT3_ATTHIZ3_6                ((uint32_t)0x40000000)        /*!< Bit 6 */
+#define  FSMC_PATT3_ATTHIZ3_7                ((uint32_t)0x80000000)        /*!< Bit 7 */
+
+/******************  Bit definition for FSMC_PATT4 register  ******************/
+#define  FSMC_PATT4_ATTSET4                  ((uint32_t)0x000000FF)        /*!< ATTSET4[7:0] bits (Attribute memory 4 setup time) */
+#define  FSMC_PATT4_ATTSET4_0                ((uint32_t)0x00000001)        /*!< Bit 0 */
+#define  FSMC_PATT4_ATTSET4_1                ((uint32_t)0x00000002)        /*!< Bit 1 */
+#define  FSMC_PATT4_ATTSET4_2                ((uint32_t)0x00000004)        /*!< Bit 2 */
+#define  FSMC_PATT4_ATTSET4_3                ((uint32_t)0x00000008)        /*!< Bit 3 */
+#define  FSMC_PATT4_ATTSET4_4                ((uint32_t)0x00000010)        /*!< Bit 4 */
+#define  FSMC_PATT4_ATTSET4_5                ((uint32_t)0x00000020)        /*!< Bit 5 */
+#define  FSMC_PATT4_ATTSET4_6                ((uint32_t)0x00000040)        /*!< Bit 6 */
+#define  FSMC_PATT4_ATTSET4_7                ((uint32_t)0x00000080)        /*!< Bit 7 */
+
+#define  FSMC_PATT4_ATTWAIT4                 ((uint32_t)0x0000FF00)        /*!< ATTWAIT4[7:0] bits (Attribute memory 4 wait time) */
+#define  FSMC_PATT4_ATTWAIT4_0               ((uint32_t)0x00000100)        /*!< Bit 0 */
+#define  FSMC_PATT4_ATTWAIT4_1               ((uint32_t)0x00000200)        /*!< Bit 1 */
+#define  FSMC_PATT4_ATTWAIT4_2               ((uint32_t)0x00000400)        /*!< Bit 2 */
+#define  FSMC_PATT4_ATTWAIT4_3               ((uint32_t)0x00000800)        /*!< Bit 3 */
+#define  FSMC_PATT4_ATTWAIT4_4               ((uint32_t)0x00001000)        /*!< Bit 4 */
+#define  FSMC_PATT4_ATTWAIT4_5               ((uint32_t)0x00002000)        /*!< Bit 5 */
+#define  FSMC_PATT4_ATTWAIT4_6               ((uint32_t)0x00004000)        /*!< Bit 6 */
+#define  FSMC_PATT4_ATTWAIT4_7               ((uint32_t)0x00008000)        /*!< Bit 7 */
+
+#define  FSMC_PATT4_ATTHOLD4                 ((uint32_t)0x00FF0000)        /*!< ATTHOLD4[7:0] bits (Attribute memory 4 hold time) */
+#define  FSMC_PATT4_ATTHOLD4_0               ((uint32_t)0x00010000)        /*!< Bit 0 */
+#define  FSMC_PATT4_ATTHOLD4_1               ((uint32_t)0x00020000)        /*!< Bit 1 */
+#define  FSMC_PATT4_ATTHOLD4_2               ((uint32_t)0x00040000)        /*!< Bit 2 */
+#define  FSMC_PATT4_ATTHOLD4_3               ((uint32_t)0x00080000)        /*!< Bit 3 */
+#define  FSMC_PATT4_ATTHOLD4_4               ((uint32_t)0x00100000)        /*!< Bit 4 */
+#define  FSMC_PATT4_ATTHOLD4_5               ((uint32_t)0x00200000)        /*!< Bit 5 */
+#define  FSMC_PATT4_ATTHOLD4_6               ((uint32_t)0x00400000)        /*!< Bit 6 */
+#define  FSMC_PATT4_ATTHOLD4_7               ((uint32_t)0x00800000)        /*!< Bit 7 */
+
+#define  FSMC_PATT4_ATTHIZ4                  ((uint32_t)0xFF000000)        /*!< ATTHIZ4[7:0] bits (Attribute memory 4 databus HiZ time) */
+#define  FSMC_PATT4_ATTHIZ4_0                ((uint32_t)0x01000000)        /*!< Bit 0 */
+#define  FSMC_PATT4_ATTHIZ4_1                ((uint32_t)0x02000000)        /*!< Bit 1 */
+#define  FSMC_PATT4_ATTHIZ4_2                ((uint32_t)0x04000000)        /*!< Bit 2 */
+#define  FSMC_PATT4_ATTHIZ4_3                ((uint32_t)0x08000000)        /*!< Bit 3 */
+#define  FSMC_PATT4_ATTHIZ4_4                ((uint32_t)0x10000000)        /*!< Bit 4 */
+#define  FSMC_PATT4_ATTHIZ4_5                ((uint32_t)0x20000000)        /*!< Bit 5 */
+#define  FSMC_PATT4_ATTHIZ4_6                ((uint32_t)0x40000000)        /*!< Bit 6 */
+#define  FSMC_PATT4_ATTHIZ4_7                ((uint32_t)0x80000000)        /*!< Bit 7 */
+
+/******************  Bit definition for FSMC_PIO4 register  *******************/
+#define  FSMC_PIO4_IOSET4                    ((uint32_t)0x000000FF)        /*!< IOSET4[7:0] bits (I/O 4 setup time) */
+#define  FSMC_PIO4_IOSET4_0                  ((uint32_t)0x00000001)        /*!< Bit 0 */
+#define  FSMC_PIO4_IOSET4_1                  ((uint32_t)0x00000002)        /*!< Bit 1 */
+#define  FSMC_PIO4_IOSET4_2                  ((uint32_t)0x00000004)        /*!< Bit 2 */
+#define  FSMC_PIO4_IOSET4_3                  ((uint32_t)0x00000008)        /*!< Bit 3 */
+#define  FSMC_PIO4_IOSET4_4                  ((uint32_t)0x00000010)        /*!< Bit 4 */
+#define  FSMC_PIO4_IOSET4_5                  ((uint32_t)0x00000020)        /*!< Bit 5 */
+#define  FSMC_PIO4_IOSET4_6                  ((uint32_t)0x00000040)        /*!< Bit 6 */
+#define  FSMC_PIO4_IOSET4_7                  ((uint32_t)0x00000080)        /*!< Bit 7 */
+
+#define  FSMC_PIO4_IOWAIT4                   ((uint32_t)0x0000FF00)        /*!< IOWAIT4[7:0] bits (I/O 4 wait time) */
+#define  FSMC_PIO4_IOWAIT4_0                 ((uint32_t)0x00000100)        /*!< Bit 0 */
+#define  FSMC_PIO4_IOWAIT4_1                 ((uint32_t)0x00000200)        /*!< Bit 1 */
+#define  FSMC_PIO4_IOWAIT4_2                 ((uint32_t)0x00000400)        /*!< Bit 2 */
+#define  FSMC_PIO4_IOWAIT4_3                 ((uint32_t)0x00000800)        /*!< Bit 3 */
+#define  FSMC_PIO4_IOWAIT4_4                 ((uint32_t)0x00001000)        /*!< Bit 4 */
+#define  FSMC_PIO4_IOWAIT4_5                 ((uint32_t)0x00002000)        /*!< Bit 5 */
+#define  FSMC_PIO4_IOWAIT4_6                 ((uint32_t)0x00004000)        /*!< Bit 6 */
+#define  FSMC_PIO4_IOWAIT4_7                 ((uint32_t)0x00008000)        /*!< Bit 7 */
+
+#define  FSMC_PIO4_IOHOLD4                   ((uint32_t)0x00FF0000)        /*!< IOHOLD4[7:0] bits (I/O 4 hold time) */
+#define  FSMC_PIO4_IOHOLD4_0                 ((uint32_t)0x00010000)        /*!< Bit 0 */
+#define  FSMC_PIO4_IOHOLD4_1                 ((uint32_t)0x00020000)        /*!< Bit 1 */
+#define  FSMC_PIO4_IOHOLD4_2                 ((uint32_t)0x00040000)        /*!< Bit 2 */
+#define  FSMC_PIO4_IOHOLD4_3                 ((uint32_t)0x00080000)        /*!< Bit 3 */
+#define  FSMC_PIO4_IOHOLD4_4                 ((uint32_t)0x00100000)        /*!< Bit 4 */
+#define  FSMC_PIO4_IOHOLD4_5                 ((uint32_t)0x00200000)        /*!< Bit 5 */
+#define  FSMC_PIO4_IOHOLD4_6                 ((uint32_t)0x00400000)        /*!< Bit 6 */
+#define  FSMC_PIO4_IOHOLD4_7                 ((uint32_t)0x00800000)        /*!< Bit 7 */
+
+#define  FSMC_PIO4_IOHIZ4                    ((uint32_t)0xFF000000)        /*!< IOHIZ4[7:0] bits (I/O 4 databus HiZ time) */
+#define  FSMC_PIO4_IOHIZ4_0                  ((uint32_t)0x01000000)        /*!< Bit 0 */
+#define  FSMC_PIO4_IOHIZ4_1                  ((uint32_t)0x02000000)        /*!< Bit 1 */
+#define  FSMC_PIO4_IOHIZ4_2                  ((uint32_t)0x04000000)        /*!< Bit 2 */
+#define  FSMC_PIO4_IOHIZ4_3                  ((uint32_t)0x08000000)        /*!< Bit 3 */
+#define  FSMC_PIO4_IOHIZ4_4                  ((uint32_t)0x10000000)        /*!< Bit 4 */
+#define  FSMC_PIO4_IOHIZ4_5                  ((uint32_t)0x20000000)        /*!< Bit 5 */
+#define  FSMC_PIO4_IOHIZ4_6                  ((uint32_t)0x40000000)        /*!< Bit 6 */
+#define  FSMC_PIO4_IOHIZ4_7                  ((uint32_t)0x80000000)        /*!< Bit 7 */
+
+/******************  Bit definition for FSMC_ECCR2 register  ******************/
+#define  FSMC_ECCR2_ECC2                     ((uint32_t)0xFFFFFFFF)        /*!< ECC result */
+
+/******************  Bit definition for FSMC_ECCR3 register  ******************/
+#define  FSMC_ECCR3_ECC3                     ((uint32_t)0xFFFFFFFF)        /*!< ECC result */
+
+/******************************************************************************/
+/*                                                                            */
+/*                          SD host Interface                                 */
+/*                                                                            */
+/******************************************************************************/
+
+/******************  Bit definition for SDIO_POWER register  ******************/
+#define  SDIO_POWER_PWRCTRL                  ((uint8_t)0x03)               /*!< PWRCTRL[1:0] bits (Power supply control bits) */
+#define  SDIO_POWER_PWRCTRL_0                ((uint8_t)0x01)               /*!< Bit 0 */
+#define  SDIO_POWER_PWRCTRL_1                ((uint8_t)0x02)               /*!< Bit 1 */
+
+/******************  Bit definition for SDIO_CLKCR register  ******************/
+#define  SDIO_CLKCR_CLKDIV                   ((uint16_t)0x00FF)            /*!< Clock divide factor */
+#define  SDIO_CLKCR_CLKEN                    ((uint16_t)0x0100)            /*!< Clock enable bit */
+#define  SDIO_CLKCR_PWRSAV                   ((uint16_t)0x0200)            /*!< Power saving configuration bit */
+#define  SDIO_CLKCR_BYPASS                   ((uint16_t)0x0400)            /*!< Clock divider bypass enable bit */
+
+#define  SDIO_CLKCR_WIDBUS                   ((uint16_t)0x1800)            /*!< WIDBUS[1:0] bits (Wide bus mode enable bit) */
+#define  SDIO_CLKCR_WIDBUS_0                 ((uint16_t)0x0800)            /*!< Bit 0 */
+#define  SDIO_CLKCR_WIDBUS_1                 ((uint16_t)0x1000)            /*!< Bit 1 */
+
+#define  SDIO_CLKCR_NEGEDGE                  ((uint16_t)0x2000)            /*!< SDIO_CK dephasing selection bit */
+#define  SDIO_CLKCR_HWFC_EN                  ((uint16_t)0x4000)            /*!< HW Flow Control enable */
+
+/*******************  Bit definition for SDIO_ARG register  *******************/
+#define  SDIO_ARG_CMDARG                     ((uint32_t)0xFFFFFFFF)            /*!< Command argument */
+
+/*******************  Bit definition for SDIO_CMD register  *******************/
+#define  SDIO_CMD_CMDINDEX                   ((uint16_t)0x003F)            /*!< Command Index */
+
+#define  SDIO_CMD_WAITRESP                   ((uint16_t)0x00C0)            /*!< WAITRESP[1:0] bits (Wait for response bits) */
+#define  SDIO_CMD_WAITRESP_0                 ((uint16_t)0x0040)            /*!<  Bit 0 */
+#define  SDIO_CMD_WAITRESP_1                 ((uint16_t)0x0080)            /*!<  Bit 1 */
+
+#define  SDIO_CMD_WAITINT                    ((uint16_t)0x0100)            /*!< CPSM Waits for Interrupt Request */
+#define  SDIO_CMD_WAITPEND                   ((uint16_t)0x0200)            /*!< CPSM Waits for ends of data transfer (CmdPend internal signal) */
+#define  SDIO_CMD_CPSMEN                     ((uint16_t)0x0400)            /*!< Command path state machine (CPSM) Enable bit */
+#define  SDIO_CMD_SDIOSUSPEND                ((uint16_t)0x0800)            /*!< SD I/O suspend command */
+#define  SDIO_CMD_ENCMDCOMPL                 ((uint16_t)0x1000)            /*!< Enable CMD completion */
+#define  SDIO_CMD_NIEN                       ((uint16_t)0x2000)            /*!< Not Interrupt Enable */
+#define  SDIO_CMD_CEATACMD                   ((uint16_t)0x4000)            /*!< CE-ATA command */
+
+/*****************  Bit definition for SDIO_RESPCMD register  *****************/
+#define  SDIO_RESPCMD_RESPCMD                ((uint8_t)0x3F)               /*!< Response command index */
+
+/******************  Bit definition for SDIO_RESP0 register  ******************/
+#define  SDIO_RESP0_CARDSTATUS0              ((uint32_t)0xFFFFFFFF)        /*!< Card Status */
+
+/******************  Bit definition for SDIO_RESP1 register  ******************/
+#define  SDIO_RESP1_CARDSTATUS1              ((uint32_t)0xFFFFFFFF)        /*!< Card Status */
+
+/******************  Bit definition for SDIO_RESP2 register  ******************/
+#define  SDIO_RESP2_CARDSTATUS2              ((uint32_t)0xFFFFFFFF)        /*!< Card Status */
+
+/******************  Bit definition for SDIO_RESP3 register  ******************/
+#define  SDIO_RESP3_CARDSTATUS3              ((uint32_t)0xFFFFFFFF)        /*!< Card Status */
+
+/******************  Bit definition for SDIO_RESP4 register  ******************/
+#define  SDIO_RESP4_CARDSTATUS4              ((uint32_t)0xFFFFFFFF)        /*!< Card Status */
+
+/******************  Bit definition for SDIO_DTIMER register  *****************/
+#define  SDIO_DTIMER_DATATIME                ((uint32_t)0xFFFFFFFF)        /*!< Data timeout period. */
+
+/******************  Bit definition for SDIO_DLEN register  *******************/
+#define  SDIO_DLEN_DATALENGTH                ((uint32_t)0x01FFFFFF)        /*!< Data length value */
+
+/******************  Bit definition for SDIO_DCTRL register  ******************/
+#define  SDIO_DCTRL_DTEN                     ((uint16_t)0x0001)            /*!< Data transfer enabled bit */
+#define  SDIO_DCTRL_DTDIR                    ((uint16_t)0x0002)            /*!< Data transfer direction selection */
+#define  SDIO_DCTRL_DTMODE                   ((uint16_t)0x0004)            /*!< Data transfer mode selection */
+#define  SDIO_DCTRL_DMAEN                    ((uint16_t)0x0008)            /*!< DMA enabled bit */
+
+#define  SDIO_DCTRL_DBLOCKSIZE               ((uint16_t)0x00F0)            /*!< DBLOCKSIZE[3:0] bits (Data block size) */
+#define  SDIO_DCTRL_DBLOCKSIZE_0             ((uint16_t)0x0010)            /*!< Bit 0 */
+#define  SDIO_DCTRL_DBLOCKSIZE_1             ((uint16_t)0x0020)            /*!< Bit 1 */
+#define  SDIO_DCTRL_DBLOCKSIZE_2             ((uint16_t)0x0040)            /*!< Bit 2 */
+#define  SDIO_DCTRL_DBLOCKSIZE_3             ((uint16_t)0x0080)            /*!< Bit 3 */
+
+#define  SDIO_DCTRL_RWSTART                  ((uint16_t)0x0100)            /*!< Read wait start */
+#define  SDIO_DCTRL_RWSTOP                   ((uint16_t)0x0200)            /*!< Read wait stop */
+#define  SDIO_DCTRL_RWMOD                    ((uint16_t)0x0400)            /*!< Read wait mode */
+#define  SDIO_DCTRL_SDIOEN                   ((uint16_t)0x0800)            /*!< SD I/O enable functions */
+
+/******************  Bit definition for SDIO_DCOUNT register  *****************/
+#define  SDIO_DCOUNT_DATACOUNT               ((uint32_t)0x01FFFFFF)        /*!< Data count value */
+
+/******************  Bit definition for SDIO_STA register  ********************/
+#define  SDIO_STA_CCRCFAIL                   ((uint32_t)0x00000001)        /*!< Command response received (CRC check failed) */
+#define  SDIO_STA_DCRCFAIL                   ((uint32_t)0x00000002)        /*!< Data block sent/received (CRC check failed) */
+#define  SDIO_STA_CTIMEOUT                   ((uint32_t)0x00000004)        /*!< Command response timeout */
+#define  SDIO_STA_DTIMEOUT                   ((uint32_t)0x00000008)        /*!< Data timeout */
+#define  SDIO_STA_TXUNDERR                   ((uint32_t)0x00000010)        /*!< Transmit FIFO underrun error */
+#define  SDIO_STA_RXOVERR                    ((uint32_t)0x00000020)        /*!< Received FIFO overrun error */
+#define  SDIO_STA_CMDREND                    ((uint32_t)0x00000040)        /*!< Command response received (CRC check passed) */
+#define  SDIO_STA_CMDSENT                    ((uint32_t)0x00000080)        /*!< Command sent (no response required) */
+#define  SDIO_STA_DATAEND                    ((uint32_t)0x00000100)        /*!< Data end (data counter, SDIDCOUNT, is zero) */
+#define  SDIO_STA_STBITERR                   ((uint32_t)0x00000200)        /*!< Start bit not detected on all data signals in wide bus mode */
+#define  SDIO_STA_DBCKEND                    ((uint32_t)0x00000400)        /*!< Data block sent/received (CRC check passed) */
+#define  SDIO_STA_CMDACT                     ((uint32_t)0x00000800)        /*!< Command transfer in progress */
+#define  SDIO_STA_TXACT                      ((uint32_t)0x00001000)        /*!< Data transmit in progress */
+#define  SDIO_STA_RXACT                      ((uint32_t)0x00002000)        /*!< Data receive in progress */
+#define  SDIO_STA_TXFIFOHE                   ((uint32_t)0x00004000)        /*!< Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */
+#define  SDIO_STA_RXFIFOHF                   ((uint32_t)0x00008000)        /*!< Receive FIFO Half Full: there are at least 8 words in the FIFO */
+#define  SDIO_STA_TXFIFOF                    ((uint32_t)0x00010000)        /*!< Transmit FIFO full */
+#define  SDIO_STA_RXFIFOF                    ((uint32_t)0x00020000)        /*!< Receive FIFO full */
+#define  SDIO_STA_TXFIFOE                    ((uint32_t)0x00040000)        /*!< Transmit FIFO empty */
+#define  SDIO_STA_RXFIFOE                    ((uint32_t)0x00080000)        /*!< Receive FIFO empty */
+#define  SDIO_STA_TXDAVL                     ((uint32_t)0x00100000)        /*!< Data available in transmit FIFO */
+#define  SDIO_STA_RXDAVL                     ((uint32_t)0x00200000)        /*!< Data available in receive FIFO */
+#define  SDIO_STA_SDIOIT                     ((uint32_t)0x00400000)        /*!< SDIO interrupt received */
+#define  SDIO_STA_CEATAEND                   ((uint32_t)0x00800000)        /*!< CE-ATA command completion signal received for CMD61 */
+
+/*******************  Bit definition for SDIO_ICR register  *******************/
+#define  SDIO_ICR_CCRCFAILC                  ((uint32_t)0x00000001)        /*!< CCRCFAIL flag clear bit */
+#define  SDIO_ICR_DCRCFAILC                  ((uint32_t)0x00000002)        /*!< DCRCFAIL flag clear bit */
+#define  SDIO_ICR_CTIMEOUTC                  ((uint32_t)0x00000004)        /*!< CTIMEOUT flag clear bit */
+#define  SDIO_ICR_DTIMEOUTC                  ((uint32_t)0x00000008)        /*!< DTIMEOUT flag clear bit */
+#define  SDIO_ICR_TXUNDERRC                  ((uint32_t)0x00000010)        /*!< TXUNDERR flag clear bit */
+#define  SDIO_ICR_RXOVERRC                   ((uint32_t)0x00000020)        /*!< RXOVERR flag clear bit */
+#define  SDIO_ICR_CMDRENDC                   ((uint32_t)0x00000040)        /*!< CMDREND flag clear bit */
+#define  SDIO_ICR_CMDSENTC                   ((uint32_t)0x00000080)        /*!< CMDSENT flag clear bit */
+#define  SDIO_ICR_DATAENDC                   ((uint32_t)0x00000100)        /*!< DATAEND flag clear bit */
+#define  SDIO_ICR_STBITERRC                  ((uint32_t)0x00000200)        /*!< STBITERR flag clear bit */
+#define  SDIO_ICR_DBCKENDC                   ((uint32_t)0x00000400)        /*!< DBCKEND flag clear bit */
+#define  SDIO_ICR_SDIOITC                    ((uint32_t)0x00400000)        /*!< SDIOIT flag clear bit */
+#define  SDIO_ICR_CEATAENDC                  ((uint32_t)0x00800000)        /*!< CEATAEND flag clear bit */
+
+/******************  Bit definition for SDIO_MASK register  *******************/
+#define  SDIO_MASK_CCRCFAILIE                ((uint32_t)0x00000001)        /*!< Command CRC Fail Interrupt Enable */
+#define  SDIO_MASK_DCRCFAILIE                ((uint32_t)0x00000002)        /*!< Data CRC Fail Interrupt Enable */
+#define  SDIO_MASK_CTIMEOUTIE                ((uint32_t)0x00000004)        /*!< Command TimeOut Interrupt Enable */
+#define  SDIO_MASK_DTIMEOUTIE                ((uint32_t)0x00000008)        /*!< Data TimeOut Interrupt Enable */
+#define  SDIO_MASK_TXUNDERRIE                ((uint32_t)0x00000010)        /*!< Tx FIFO UnderRun Error Interrupt Enable */
+#define  SDIO_MASK_RXOVERRIE                 ((uint32_t)0x00000020)        /*!< Rx FIFO OverRun Error Interrupt Enable */
+#define  SDIO_MASK_CMDRENDIE                 ((uint32_t)0x00000040)        /*!< Command Response Received Interrupt Enable */
+#define  SDIO_MASK_CMDSENTIE                 ((uint32_t)0x00000080)        /*!< Command Sent Interrupt Enable */
+#define  SDIO_MASK_DATAENDIE                 ((uint32_t)0x00000100)        /*!< Data End Interrupt Enable */
+#define  SDIO_MASK_STBITERRIE                ((uint32_t)0x00000200)        /*!< Start Bit Error Interrupt Enable */
+#define  SDIO_MASK_DBCKENDIE                 ((uint32_t)0x00000400)        /*!< Data Block End Interrupt Enable */
+#define  SDIO_MASK_CMDACTIE                  ((uint32_t)0x00000800)        /*!< Command Acting Interrupt Enable */
+#define  SDIO_MASK_TXACTIE                   ((uint32_t)0x00001000)        /*!< Data Transmit Acting Interrupt Enable */
+#define  SDIO_MASK_RXACTIE                   ((uint32_t)0x00002000)        /*!< Data receive acting interrupt enabled */
+#define  SDIO_MASK_TXFIFOHEIE                ((uint32_t)0x00004000)        /*!< Tx FIFO Half Empty interrupt Enable */
+#define  SDIO_MASK_RXFIFOHFIE                ((uint32_t)0x00008000)        /*!< Rx FIFO Half Full interrupt Enable */
+#define  SDIO_MASK_TXFIFOFIE                 ((uint32_t)0x00010000)        /*!< Tx FIFO Full interrupt Enable */
+#define  SDIO_MASK_RXFIFOFIE                 ((uint32_t)0x00020000)        /*!< Rx FIFO Full interrupt Enable */
+#define  SDIO_MASK_TXFIFOEIE                 ((uint32_t)0x00040000)        /*!< Tx FIFO Empty interrupt Enable */
+#define  SDIO_MASK_RXFIFOEIE                 ((uint32_t)0x00080000)        /*!< Rx FIFO Empty interrupt Enable */
+#define  SDIO_MASK_TXDAVLIE                  ((uint32_t)0x00100000)        /*!< Data available in Tx FIFO interrupt Enable */
+#define  SDIO_MASK_RXDAVLIE                  ((uint32_t)0x00200000)        /*!< Data available in Rx FIFO interrupt Enable */
+#define  SDIO_MASK_SDIOITIE                  ((uint32_t)0x00400000)        /*!< SDIO Mode Interrupt Received interrupt Enable */
+#define  SDIO_MASK_CEATAENDIE                ((uint32_t)0x00800000)        /*!< CE-ATA command completion signal received Interrupt Enable */
+
+/*****************  Bit definition for SDIO_FIFOCNT register  *****************/
+#define  SDIO_FIFOCNT_FIFOCOUNT              ((uint32_t)0x00FFFFFF)        /*!< Remaining number of words to be written to or read from the FIFO */
+
+/******************  Bit definition for SDIO_FIFO register  *******************/
+#define  SDIO_FIFO_FIFODATA                  ((uint32_t)0xFFFFFFFF)        /*!< Receive and transmit FIFO data */
+
+/******************************************************************************/
+/*                                                                            */
+/*                                   USB Device FS                            */
+/*                                                                            */
+/******************************************************************************/
+
+/*!< Endpoint-specific registers */
+/*******************  Bit definition for USB_EP0R register  *******************/
+#define  USB_EP0R_EA                         ((uint16_t)0x000F)            /*!< Endpoint Address */
+
+#define  USB_EP0R_STAT_TX                    ((uint16_t)0x0030)            /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */
+#define  USB_EP0R_STAT_TX_0                  ((uint16_t)0x0010)            /*!< Bit 0 */
+#define  USB_EP0R_STAT_TX_1                  ((uint16_t)0x0020)            /*!< Bit 1 */
+
+#define  USB_EP0R_DTOG_TX                    ((uint16_t)0x0040)            /*!< Data Toggle, for transmission transfers */
+#define  USB_EP0R_CTR_TX                     ((uint16_t)0x0080)            /*!< Correct Transfer for transmission */
+#define  USB_EP0R_EP_KIND                    ((uint16_t)0x0100)            /*!< Endpoint Kind */
+
+#define  USB_EP0R_EP_TYPE                    ((uint16_t)0x0600)            /*!< EP_TYPE[1:0] bits (Endpoint type) */
+#define  USB_EP0R_EP_TYPE_0                  ((uint16_t)0x0200)            /*!< Bit 0 */
+#define  USB_EP0R_EP_TYPE_1                  ((uint16_t)0x0400)            /*!< Bit 1 */
+
+#define  USB_EP0R_SETUP                      ((uint16_t)0x0800)            /*!< Setup transaction completed */
+
+#define  USB_EP0R_STAT_RX                    ((uint16_t)0x3000)            /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */
+#define  USB_EP0R_STAT_RX_0                  ((uint16_t)0x1000)            /*!< Bit 0 */
+#define  USB_EP0R_STAT_RX_1                  ((uint16_t)0x2000)            /*!< Bit 1 */
+
+#define  USB_EP0R_DTOG_RX                    ((uint16_t)0x4000)            /*!< Data Toggle, for reception transfers */
+#define  USB_EP0R_CTR_RX                     ((uint16_t)0x8000)            /*!< Correct Transfer for reception */
+
+/*******************  Bit definition for USB_EP1R register  *******************/
+#define  USB_EP1R_EA                         ((uint16_t)0x000F)            /*!< Endpoint Address */
+
+#define  USB_EP1R_STAT_TX                    ((uint16_t)0x0030)            /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */
+#define  USB_EP1R_STAT_TX_0                  ((uint16_t)0x0010)            /*!< Bit 0 */
+#define  USB_EP1R_STAT_TX_1                  ((uint16_t)0x0020)            /*!< Bit 1 */
+
+#define  USB_EP1R_DTOG_TX                    ((uint16_t)0x0040)            /*!< Data Toggle, for transmission transfers */
+#define  USB_EP1R_CTR_TX                     ((uint16_t)0x0080)            /*!< Correct Transfer for transmission */
+#define  USB_EP1R_EP_KIND                    ((uint16_t)0x0100)            /*!< Endpoint Kind */
+
+#define  USB_EP1R_EP_TYPE                    ((uint16_t)0x0600)            /*!< EP_TYPE[1:0] bits (Endpoint type) */
+#define  USB_EP1R_EP_TYPE_0                  ((uint16_t)0x0200)            /*!< Bit 0 */
+#define  USB_EP1R_EP_TYPE_1                  ((uint16_t)0x0400)            /*!< Bit 1 */
+
+#define  USB_EP1R_SETUP                      ((uint16_t)0x0800)            /*!< Setup transaction completed */
+
+#define  USB_EP1R_STAT_RX                    ((uint16_t)0x3000)            /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */
+#define  USB_EP1R_STAT_RX_0                  ((uint16_t)0x1000)            /*!< Bit 0 */
+#define  USB_EP1R_STAT_RX_1                  ((uint16_t)0x2000)            /*!< Bit 1 */
+
+#define  USB_EP1R_DTOG_RX                    ((uint16_t)0x4000)            /*!< Data Toggle, for reception transfers */
+#define  USB_EP1R_CTR_RX                     ((uint16_t)0x8000)            /*!< Correct Transfer for reception */
+
+/*******************  Bit definition for USB_EP2R register  *******************/
+#define  USB_EP2R_EA                         ((uint16_t)0x000F)            /*!< Endpoint Address */
+
+#define  USB_EP2R_STAT_TX                    ((uint16_t)0x0030)            /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */
+#define  USB_EP2R_STAT_TX_0                  ((uint16_t)0x0010)            /*!< Bit 0 */
+#define  USB_EP2R_STAT_TX_1                  ((uint16_t)0x0020)            /*!< Bit 1 */
+
+#define  USB_EP2R_DTOG_TX                    ((uint16_t)0x0040)            /*!< Data Toggle, for transmission transfers */
+#define  USB_EP2R_CTR_TX                     ((uint16_t)0x0080)            /*!< Correct Transfer for transmission */
+#define  USB_EP2R_EP_KIND                    ((uint16_t)0x0100)            /*!< Endpoint Kind */
+
+#define  USB_EP2R_EP_TYPE                    ((uint16_t)0x0600)            /*!< EP_TYPE[1:0] bits (Endpoint type) */
+#define  USB_EP2R_EP_TYPE_0                  ((uint16_t)0x0200)            /*!< Bit 0 */
+#define  USB_EP2R_EP_TYPE_1                  ((uint16_t)0x0400)            /*!< Bit 1 */
+
+#define  USB_EP2R_SETUP                      ((uint16_t)0x0800)            /*!< Setup transaction completed */
+
+#define  USB_EP2R_STAT_RX                    ((uint16_t)0x3000)            /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */
+#define  USB_EP2R_STAT_RX_0                  ((uint16_t)0x1000)            /*!< Bit 0 */
+#define  USB_EP2R_STAT_RX_1                  ((uint16_t)0x2000)            /*!< Bit 1 */
+
+#define  USB_EP2R_DTOG_RX                    ((uint16_t)0x4000)            /*!< Data Toggle, for reception transfers */
+#define  USB_EP2R_CTR_RX                     ((uint16_t)0x8000)            /*!< Correct Transfer for reception */
+
+/*******************  Bit definition for USB_EP3R register  *******************/
+#define  USB_EP3R_EA                         ((uint16_t)0x000F)            /*!< Endpoint Address */
+
+#define  USB_EP3R_STAT_TX                    ((uint16_t)0x0030)            /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */
+#define  USB_EP3R_STAT_TX_0                  ((uint16_t)0x0010)            /*!< Bit 0 */
+#define  USB_EP3R_STAT_TX_1                  ((uint16_t)0x0020)            /*!< Bit 1 */
+
+#define  USB_EP3R_DTOG_TX                    ((uint16_t)0x0040)            /*!< Data Toggle, for transmission transfers */
+#define  USB_EP3R_CTR_TX                     ((uint16_t)0x0080)            /*!< Correct Transfer for transmission */
+#define  USB_EP3R_EP_KIND                    ((uint16_t)0x0100)            /*!< Endpoint Kind */
+
+#define  USB_EP3R_EP_TYPE                    ((uint16_t)0x0600)            /*!< EP_TYPE[1:0] bits (Endpoint type) */
+#define  USB_EP3R_EP_TYPE_0                  ((uint16_t)0x0200)            /*!< Bit 0 */
+#define  USB_EP3R_EP_TYPE_1                  ((uint16_t)0x0400)            /*!< Bit 1 */
+
+#define  USB_EP3R_SETUP                      ((uint16_t)0x0800)            /*!< Setup transaction completed */
+
+#define  USB_EP3R_STAT_RX                    ((uint16_t)0x3000)            /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */
+#define  USB_EP3R_STAT_RX_0                  ((uint16_t)0x1000)            /*!< Bit 0 */
+#define  USB_EP3R_STAT_RX_1                  ((uint16_t)0x2000)            /*!< Bit 1 */
+
+#define  USB_EP3R_DTOG_RX                    ((uint16_t)0x4000)            /*!< Data Toggle, for reception transfers */
+#define  USB_EP3R_CTR_RX                     ((uint16_t)0x8000)            /*!< Correct Transfer for reception */
+
+/*******************  Bit definition for USB_EP4R register  *******************/
+#define  USB_EP4R_EA                         ((uint16_t)0x000F)            /*!< Endpoint Address */
+
+#define  USB_EP4R_STAT_TX                    ((uint16_t)0x0030)            /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */
+#define  USB_EP4R_STAT_TX_0                  ((uint16_t)0x0010)            /*!< Bit 0 */
+#define  USB_EP4R_STAT_TX_1                  ((uint16_t)0x0020)            /*!< Bit 1 */
+
+#define  USB_EP4R_DTOG_TX                    ((uint16_t)0x0040)            /*!< Data Toggle, for transmission transfers */
+#define  USB_EP4R_CTR_TX                     ((uint16_t)0x0080)            /*!< Correct Transfer for transmission */
+#define  USB_EP4R_EP_KIND                    ((uint16_t)0x0100)            /*!< Endpoint Kind */
+
+#define  USB_EP4R_EP_TYPE                    ((uint16_t)0x0600)            /*!< EP_TYPE[1:0] bits (Endpoint type) */
+#define  USB_EP4R_EP_TYPE_0                  ((uint16_t)0x0200)            /*!< Bit 0 */
+#define  USB_EP4R_EP_TYPE_1                  ((uint16_t)0x0400)            /*!< Bit 1 */
+
+#define  USB_EP4R_SETUP                      ((uint16_t)0x0800)            /*!< Setup transaction completed */
+
+#define  USB_EP4R_STAT_RX                    ((uint16_t)0x3000)            /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */
+#define  USB_EP4R_STAT_RX_0                  ((uint16_t)0x1000)            /*!< Bit 0 */
+#define  USB_EP4R_STAT_RX_1                  ((uint16_t)0x2000)            /*!< Bit 1 */
+
+#define  USB_EP4R_DTOG_RX                    ((uint16_t)0x4000)            /*!< Data Toggle, for reception transfers */
+#define  USB_EP4R_CTR_RX                     ((uint16_t)0x8000)            /*!< Correct Transfer for reception */
+
+/*******************  Bit definition for USB_EP5R register  *******************/
+#define  USB_EP5R_EA                         ((uint16_t)0x000F)            /*!< Endpoint Address */
+
+#define  USB_EP5R_STAT_TX                    ((uint16_t)0x0030)            /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */
+#define  USB_EP5R_STAT_TX_0                  ((uint16_t)0x0010)            /*!< Bit 0 */
+#define  USB_EP5R_STAT_TX_1                  ((uint16_t)0x0020)            /*!< Bit 1 */
+
+#define  USB_EP5R_DTOG_TX                    ((uint16_t)0x0040)            /*!< Data Toggle, for transmission transfers */
+#define  USB_EP5R_CTR_TX                     ((uint16_t)0x0080)            /*!< Correct Transfer for transmission */
+#define  USB_EP5R_EP_KIND                    ((uint16_t)0x0100)            /*!< Endpoint Kind */
+
+#define  USB_EP5R_EP_TYPE                    ((uint16_t)0x0600)            /*!< EP_TYPE[1:0] bits (Endpoint type) */
+#define  USB_EP5R_EP_TYPE_0                  ((uint16_t)0x0200)            /*!< Bit 0 */
+#define  USB_EP5R_EP_TYPE_1                  ((uint16_t)0x0400)            /*!< Bit 1 */
+
+#define  USB_EP5R_SETUP                      ((uint16_t)0x0800)            /*!< Setup transaction completed */
+
+#define  USB_EP5R_STAT_RX                    ((uint16_t)0x3000)            /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */
+#define  USB_EP5R_STAT_RX_0                  ((uint16_t)0x1000)            /*!< Bit 0 */
+#define  USB_EP5R_STAT_RX_1                  ((uint16_t)0x2000)            /*!< Bit 1 */
+
+#define  USB_EP5R_DTOG_RX                    ((uint16_t)0x4000)            /*!< Data Toggle, for reception transfers */
+#define  USB_EP5R_CTR_RX                     ((uint16_t)0x8000)            /*!< Correct Transfer for reception */
+
+/*******************  Bit definition for USB_EP6R register  *******************/
+#define  USB_EP6R_EA                         ((uint16_t)0x000F)            /*!< Endpoint Address */
+
+#define  USB_EP6R_STAT_TX                    ((uint16_t)0x0030)            /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */
+#define  USB_EP6R_STAT_TX_0                  ((uint16_t)0x0010)            /*!< Bit 0 */
+#define  USB_EP6R_STAT_TX_1                  ((uint16_t)0x0020)            /*!< Bit 1 */
+
+#define  USB_EP6R_DTOG_TX                    ((uint16_t)0x0040)            /*!< Data Toggle, for transmission transfers */
+#define  USB_EP6R_CTR_TX                     ((uint16_t)0x0080)            /*!< Correct Transfer for transmission */
+#define  USB_EP6R_EP_KIND                    ((uint16_t)0x0100)            /*!< Endpoint Kind */
+
+#define  USB_EP6R_EP_TYPE                    ((uint16_t)0x0600)            /*!< EP_TYPE[1:0] bits (Endpoint type) */
+#define  USB_EP6R_EP_TYPE_0                  ((uint16_t)0x0200)            /*!< Bit 0 */
+#define  USB_EP6R_EP_TYPE_1                  ((uint16_t)0x0400)            /*!< Bit 1 */
+
+#define  USB_EP6R_SETUP                      ((uint16_t)0x0800)            /*!< Setup transaction completed */
+
+#define  USB_EP6R_STAT_RX                    ((uint16_t)0x3000)            /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */
+#define  USB_EP6R_STAT_RX_0                  ((uint16_t)0x1000)            /*!< Bit 0 */
+#define  USB_EP6R_STAT_RX_1                  ((uint16_t)0x2000)            /*!< Bit 1 */
+
+#define  USB_EP6R_DTOG_RX                    ((uint16_t)0x4000)            /*!< Data Toggle, for reception transfers */
+#define  USB_EP6R_CTR_RX                     ((uint16_t)0x8000)            /*!< Correct Transfer for reception */
+
+/*******************  Bit definition for USB_EP7R register  *******************/
+#define  USB_EP7R_EA                         ((uint16_t)0x000F)            /*!< Endpoint Address */
+
+#define  USB_EP7R_STAT_TX                    ((uint16_t)0x0030)            /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */
+#define  USB_EP7R_STAT_TX_0                  ((uint16_t)0x0010)            /*!< Bit 0 */
+#define  USB_EP7R_STAT_TX_1                  ((uint16_t)0x0020)            /*!< Bit 1 */
+
+#define  USB_EP7R_DTOG_TX                    ((uint16_t)0x0040)            /*!< Data Toggle, for transmission transfers */
+#define  USB_EP7R_CTR_TX                     ((uint16_t)0x0080)            /*!< Correct Transfer for transmission */
+#define  USB_EP7R_EP_KIND                    ((uint16_t)0x0100)            /*!< Endpoint Kind */
+
+#define  USB_EP7R_EP_TYPE                    ((uint16_t)0x0600)            /*!< EP_TYPE[1:0] bits (Endpoint type) */
+#define  USB_EP7R_EP_TYPE_0                  ((uint16_t)0x0200)            /*!< Bit 0 */
+#define  USB_EP7R_EP_TYPE_1                  ((uint16_t)0x0400)            /*!< Bit 1 */
+
+#define  USB_EP7R_SETUP                      ((uint16_t)0x0800)            /*!< Setup transaction completed */
+
+#define  USB_EP7R_STAT_RX                    ((uint16_t)0x3000)            /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */
+#define  USB_EP7R_STAT_RX_0                  ((uint16_t)0x1000)            /*!< Bit 0 */
+#define  USB_EP7R_STAT_RX_1                  ((uint16_t)0x2000)            /*!< Bit 1 */
+
+#define  USB_EP7R_DTOG_RX                    ((uint16_t)0x4000)            /*!< Data Toggle, for reception transfers */
+#define  USB_EP7R_CTR_RX                     ((uint16_t)0x8000)            /*!< Correct Transfer for reception */
+
+/*!< Common registers */
+/*******************  Bit definition for USB_CNTR register  *******************/
+#define  USB_CNTR_FRES                       ((uint16_t)0x0001)            /*!< Force USB Reset */
+#define  USB_CNTR_PDWN                       ((uint16_t)0x0002)            /*!< Power down */
+#define  USB_CNTR_LP_MODE                    ((uint16_t)0x0004)            /*!< Low-power mode */
+#define  USB_CNTR_FSUSP                      ((uint16_t)0x0008)            /*!< Force suspend */
+#define  USB_CNTR_RESUME                     ((uint16_t)0x0010)            /*!< Resume request */
+#define  USB_CNTR_ESOFM                      ((uint16_t)0x0100)            /*!< Expected Start Of Frame Interrupt Mask */
+#define  USB_CNTR_SOFM                       ((uint16_t)0x0200)            /*!< Start Of Frame Interrupt Mask */
+#define  USB_CNTR_RESETM                     ((uint16_t)0x0400)            /*!< RESET Interrupt Mask */
+#define  USB_CNTR_SUSPM                      ((uint16_t)0x0800)            /*!< Suspend mode Interrupt Mask */
+#define  USB_CNTR_WKUPM                      ((uint16_t)0x1000)            /*!< Wakeup Interrupt Mask */
+#define  USB_CNTR_ERRM                       ((uint16_t)0x2000)            /*!< Error Interrupt Mask */
+#define  USB_CNTR_PMAOVRM                    ((uint16_t)0x4000)            /*!< Packet Memory Area Over / Underrun Interrupt Mask */
+#define  USB_CNTR_CTRM                       ((uint16_t)0x8000)            /*!< Correct Transfer Interrupt Mask */
+
+/*******************  Bit definition for USB_ISTR register  *******************/
+#define  USB_ISTR_EP_ID                      ((uint16_t)0x000F)            /*!< Endpoint Identifier */
+#define  USB_ISTR_DIR                        ((uint16_t)0x0010)            /*!< Direction of transaction */
+#define  USB_ISTR_ESOF                       ((uint16_t)0x0100)            /*!< Expected Start Of Frame */
+#define  USB_ISTR_SOF                        ((uint16_t)0x0200)            /*!< Start Of Frame */
+#define  USB_ISTR_RESET                      ((uint16_t)0x0400)            /*!< USB RESET request */
+#define  USB_ISTR_SUSP                       ((uint16_t)0x0800)            /*!< Suspend mode request */
+#define  USB_ISTR_WKUP                       ((uint16_t)0x1000)            /*!< Wake up */
+#define  USB_ISTR_ERR                        ((uint16_t)0x2000)            /*!< Error */
+#define  USB_ISTR_PMAOVR                     ((uint16_t)0x4000)            /*!< Packet Memory Area Over / Underrun */
+#define  USB_ISTR_CTR                        ((uint16_t)0x8000)            /*!< Correct Transfer */
+
+/*******************  Bit definition for USB_FNR register  ********************/
+#define  USB_FNR_FN                          ((uint16_t)0x07FF)            /*!< Frame Number */
+#define  USB_FNR_LSOF                        ((uint16_t)0x1800)            /*!< Lost SOF */
+#define  USB_FNR_LCK                         ((uint16_t)0x2000)            /*!< Locked */
+#define  USB_FNR_RXDM                        ((uint16_t)0x4000)            /*!< Receive Data - Line Status */
+#define  USB_FNR_RXDP                        ((uint16_t)0x8000)            /*!< Receive Data + Line Status */
+
+/******************  Bit definition for USB_DADDR register  *******************/
+#define  USB_DADDR_ADD                       ((uint8_t)0x7F)               /*!< ADD[6:0] bits (Device Address) */
+#define  USB_DADDR_ADD0                      ((uint8_t)0x01)               /*!< Bit 0 */
+#define  USB_DADDR_ADD1                      ((uint8_t)0x02)               /*!< Bit 1 */
+#define  USB_DADDR_ADD2                      ((uint8_t)0x04)               /*!< Bit 2 */
+#define  USB_DADDR_ADD3                      ((uint8_t)0x08)               /*!< Bit 3 */
+#define  USB_DADDR_ADD4                      ((uint8_t)0x10)               /*!< Bit 4 */
+#define  USB_DADDR_ADD5                      ((uint8_t)0x20)               /*!< Bit 5 */
+#define  USB_DADDR_ADD6                      ((uint8_t)0x40)               /*!< Bit 6 */
+
+#define  USB_DADDR_EF                        ((uint8_t)0x80)               /*!< Enable Function */
+
+/******************  Bit definition for USB_BTABLE register  ******************/    
+#define  USB_BTABLE_BTABLE                   ((uint16_t)0xFFF8)            /*!< Buffer Table */
+
+/*!< Buffer descriptor table */
+/*****************  Bit definition for USB_ADDR0_TX register  *****************/
+#define  USB_ADDR0_TX_ADDR0_TX               ((uint16_t)0xFFFE)            /*!< Transmission Buffer Address 0 */
+
+/*****************  Bit definition for USB_ADDR1_TX register  *****************/
+#define  USB_ADDR1_TX_ADDR1_TX               ((uint16_t)0xFFFE)            /*!< Transmission Buffer Address 1 */
+
+/*****************  Bit definition for USB_ADDR2_TX register  *****************/
+#define  USB_ADDR2_TX_ADDR2_TX               ((uint16_t)0xFFFE)            /*!< Transmission Buffer Address 2 */
+
+/*****************  Bit definition for USB_ADDR3_TX register  *****************/
+#define  USB_ADDR3_TX_ADDR3_TX               ((uint16_t)0xFFFE)            /*!< Transmission Buffer Address 3 */
+
+/*****************  Bit definition for USB_ADDR4_TX register  *****************/
+#define  USB_ADDR4_TX_ADDR4_TX               ((uint16_t)0xFFFE)            /*!< Transmission Buffer Address 4 */
+
+/*****************  Bit definition for USB_ADDR5_TX register  *****************/
+#define  USB_ADDR5_TX_ADDR5_TX               ((uint16_t)0xFFFE)            /*!< Transmission Buffer Address 5 */
+
+/*****************  Bit definition for USB_ADDR6_TX register  *****************/
+#define  USB_ADDR6_TX_ADDR6_TX               ((uint16_t)0xFFFE)            /*!< Transmission Buffer Address 6 */
+
+/*****************  Bit definition for USB_ADDR7_TX register  *****************/
+#define  USB_ADDR7_TX_ADDR7_TX               ((uint16_t)0xFFFE)            /*!< Transmission Buffer Address 7 */
+
+/*----------------------------------------------------------------------------*/
+
+/*****************  Bit definition for USB_COUNT0_TX register  ****************/
+#define  USB_COUNT0_TX_COUNT0_TX             ((uint16_t)0x03FF)            /*!< Transmission Byte Count 0 */
+
+/*****************  Bit definition for USB_COUNT1_TX register  ****************/
+#define  USB_COUNT1_TX_COUNT1_TX             ((uint16_t)0x03FF)            /*!< Transmission Byte Count 1 */
+
+/*****************  Bit definition for USB_COUNT2_TX register  ****************/
+#define  USB_COUNT2_TX_COUNT2_TX             ((uint16_t)0x03FF)            /*!< Transmission Byte Count 2 */
+
+/*****************  Bit definition for USB_COUNT3_TX register  ****************/
+#define  USB_COUNT3_TX_COUNT3_TX             ((uint16_t)0x03FF)            /*!< Transmission Byte Count 3 */
+
+/*****************  Bit definition for USB_COUNT4_TX register  ****************/
+#define  USB_COUNT4_TX_COUNT4_TX             ((uint16_t)0x03FF)            /*!< Transmission Byte Count 4 */
+
+/*****************  Bit definition for USB_COUNT5_TX register  ****************/
+#define  USB_COUNT5_TX_COUNT5_TX             ((uint16_t)0x03FF)            /*!< Transmission Byte Count 5 */
+
+/*****************  Bit definition for USB_COUNT6_TX register  ****************/
+#define  USB_COUNT6_TX_COUNT6_TX             ((uint16_t)0x03FF)            /*!< Transmission Byte Count 6 */
+
+/*****************  Bit definition for USB_COUNT7_TX register  ****************/
+#define  USB_COUNT7_TX_COUNT7_TX             ((uint16_t)0x03FF)            /*!< Transmission Byte Count 7 */
+
+/*----------------------------------------------------------------------------*/
+
+/****************  Bit definition for USB_COUNT0_TX_0 register  ***************/
+#define  USB_COUNT0_TX_0_COUNT0_TX_0         ((uint32_t)0x000003FF)        /*!< Transmission Byte Count 0 (low) */
+
+/****************  Bit definition for USB_COUNT0_TX_1 register  ***************/
+#define  USB_COUNT0_TX_1_COUNT0_TX_1         ((uint32_t)0x03FF0000)        /*!< Transmission Byte Count 0 (high) */
+
+/****************  Bit definition for USB_COUNT1_TX_0 register  ***************/
+#define  USB_COUNT1_TX_0_COUNT1_TX_0          ((uint32_t)0x000003FF)        /*!< Transmission Byte Count 1 (low) */
+
+/****************  Bit definition for USB_COUNT1_TX_1 register  ***************/
+#define  USB_COUNT1_TX_1_COUNT1_TX_1          ((uint32_t)0x03FF0000)        /*!< Transmission Byte Count 1 (high) */
+
+/****************  Bit definition for USB_COUNT2_TX_0 register  ***************/
+#define  USB_COUNT2_TX_0_COUNT2_TX_0         ((uint32_t)0x000003FF)        /*!< Transmission Byte Count 2 (low) */
+
+/****************  Bit definition for USB_COUNT2_TX_1 register  ***************/
+#define  USB_COUNT2_TX_1_COUNT2_TX_1         ((uint32_t)0x03FF0000)        /*!< Transmission Byte Count 2 (high) */
+
+/****************  Bit definition for USB_COUNT3_TX_0 register  ***************/
+#define  USB_COUNT3_TX_0_COUNT3_TX_0         ((uint16_t)0x000003FF)        /*!< Transmission Byte Count 3 (low) */
+
+/****************  Bit definition for USB_COUNT3_TX_1 register  ***************/
+#define  USB_COUNT3_TX_1_COUNT3_TX_1         ((uint16_t)0x03FF0000)        /*!< Transmission Byte Count 3 (high) */
+
+/****************  Bit definition for USB_COUNT4_TX_0 register  ***************/
+#define  USB_COUNT4_TX_0_COUNT4_TX_0         ((uint32_t)0x000003FF)        /*!< Transmission Byte Count 4 (low) */
+
+/****************  Bit definition for USB_COUNT4_TX_1 register  ***************/
+#define  USB_COUNT4_TX_1_COUNT4_TX_1         ((uint32_t)0x03FF0000)        /*!< Transmission Byte Count 4 (high) */
+
+/****************  Bit definition for USB_COUNT5_TX_0 register  ***************/
+#define  USB_COUNT5_TX_0_COUNT5_TX_0         ((uint32_t)0x000003FF)        /*!< Transmission Byte Count 5 (low) */
+
+/****************  Bit definition for USB_COUNT5_TX_1 register  ***************/
+#define  USB_COUNT5_TX_1_COUNT5_TX_1         ((uint32_t)0x03FF0000)        /*!< Transmission Byte Count 5 (high) */
+
+/****************  Bit definition for USB_COUNT6_TX_0 register  ***************/
+#define  USB_COUNT6_TX_0_COUNT6_TX_0         ((uint32_t)0x000003FF)        /*!< Transmission Byte Count 6 (low) */
+
+/****************  Bit definition for USB_COUNT6_TX_1 register  ***************/
+#define  USB_COUNT6_TX_1_COUNT6_TX_1         ((uint32_t)0x03FF0000)        /*!< Transmission Byte Count 6 (high) */
+
+/****************  Bit definition for USB_COUNT7_TX_0 register  ***************/
+#define  USB_COUNT7_TX_0_COUNT7_TX_0         ((uint32_t)0x000003FF)        /*!< Transmission Byte Count 7 (low) */
+
+/****************  Bit definition for USB_COUNT7_TX_1 register  ***************/
+#define  USB_COUNT7_TX_1_COUNT7_TX_1         ((uint32_t)0x03FF0000)        /*!< Transmission Byte Count 7 (high) */
+
+/*----------------------------------------------------------------------------*/
+
+/*****************  Bit definition for USB_ADDR0_RX register  *****************/
+#define  USB_ADDR0_RX_ADDR0_RX               ((uint16_t)0xFFFE)            /*!< Reception Buffer Address 0 */
+
+/*****************  Bit definition for USB_ADDR1_RX register  *****************/
+#define  USB_ADDR1_RX_ADDR1_RX               ((uint16_t)0xFFFE)            /*!< Reception Buffer Address 1 */
+
+/*****************  Bit definition for USB_ADDR2_RX register  *****************/
+#define  USB_ADDR2_RX_ADDR2_RX               ((uint16_t)0xFFFE)            /*!< Reception Buffer Address 2 */
+
+/*****************  Bit definition for USB_ADDR3_RX register  *****************/
+#define  USB_ADDR3_RX_ADDR3_RX               ((uint16_t)0xFFFE)            /*!< Reception Buffer Address 3 */
+
+/*****************  Bit definition for USB_ADDR4_RX register  *****************/
+#define  USB_ADDR4_RX_ADDR4_RX               ((uint16_t)0xFFFE)            /*!< Reception Buffer Address 4 */
+
+/*****************  Bit definition for USB_ADDR5_RX register  *****************/
+#define  USB_ADDR5_RX_ADDR5_RX               ((uint16_t)0xFFFE)            /*!< Reception Buffer Address 5 */
+
+/*****************  Bit definition for USB_ADDR6_RX register  *****************/
+#define  USB_ADDR6_RX_ADDR6_RX               ((uint16_t)0xFFFE)            /*!< Reception Buffer Address 6 */
+
+/*****************  Bit definition for USB_ADDR7_RX register  *****************/
+#define  USB_ADDR7_RX_ADDR7_RX               ((uint16_t)0xFFFE)            /*!< Reception Buffer Address 7 */
+
+/*----------------------------------------------------------------------------*/
+
+/*****************  Bit definition for USB_COUNT0_RX register  ****************/
+#define  USB_COUNT0_RX_COUNT0_RX             ((uint16_t)0x03FF)            /*!< Reception Byte Count */
+
+#define  USB_COUNT0_RX_NUM_BLOCK             ((uint16_t)0x7C00)            /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
+#define  USB_COUNT0_RX_NUM_BLOCK_0           ((uint16_t)0x0400)            /*!< Bit 0 */
+#define  USB_COUNT0_RX_NUM_BLOCK_1           ((uint16_t)0x0800)            /*!< Bit 1 */
+#define  USB_COUNT0_RX_NUM_BLOCK_2           ((uint16_t)0x1000)            /*!< Bit 2 */
+#define  USB_COUNT0_RX_NUM_BLOCK_3           ((uint16_t)0x2000)            /*!< Bit 3 */
+#define  USB_COUNT0_RX_NUM_BLOCK_4           ((uint16_t)0x4000)            /*!< Bit 4 */
+
+#define  USB_COUNT0_RX_BLSIZE                ((uint16_t)0x8000)            /*!< BLock SIZE */
+
+/*****************  Bit definition for USB_COUNT1_RX register  ****************/
+#define  USB_COUNT1_RX_COUNT1_RX             ((uint16_t)0x03FF)            /*!< Reception Byte Count */
+
+#define  USB_COUNT1_RX_NUM_BLOCK             ((uint16_t)0x7C00)            /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
+#define  USB_COUNT1_RX_NUM_BLOCK_0           ((uint16_t)0x0400)            /*!< Bit 0 */
+#define  USB_COUNT1_RX_NUM_BLOCK_1           ((uint16_t)0x0800)            /*!< Bit 1 */
+#define  USB_COUNT1_RX_NUM_BLOCK_2           ((uint16_t)0x1000)            /*!< Bit 2 */
+#define  USB_COUNT1_RX_NUM_BLOCK_3           ((uint16_t)0x2000)            /*!< Bit 3 */
+#define  USB_COUNT1_RX_NUM_BLOCK_4           ((uint16_t)0x4000)            /*!< Bit 4 */
+
+#define  USB_COUNT1_RX_BLSIZE                ((uint16_t)0x8000)            /*!< BLock SIZE */
+
+/*****************  Bit definition for USB_COUNT2_RX register  ****************/
+#define  USB_COUNT2_RX_COUNT2_RX             ((uint16_t)0x03FF)            /*!< Reception Byte Count */
+
+#define  USB_COUNT2_RX_NUM_BLOCK             ((uint16_t)0x7C00)            /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
+#define  USB_COUNT2_RX_NUM_BLOCK_0           ((uint16_t)0x0400)            /*!< Bit 0 */
+#define  USB_COUNT2_RX_NUM_BLOCK_1           ((uint16_t)0x0800)            /*!< Bit 1 */
+#define  USB_COUNT2_RX_NUM_BLOCK_2           ((uint16_t)0x1000)            /*!< Bit 2 */
+#define  USB_COUNT2_RX_NUM_BLOCK_3           ((uint16_t)0x2000)            /*!< Bit 3 */
+#define  USB_COUNT2_RX_NUM_BLOCK_4           ((uint16_t)0x4000)            /*!< Bit 4 */
+
+#define  USB_COUNT2_RX_BLSIZE                ((uint16_t)0x8000)            /*!< BLock SIZE */
+
+/*****************  Bit definition for USB_COUNT3_RX register  ****************/
+#define  USB_COUNT3_RX_COUNT3_RX             ((uint16_t)0x03FF)            /*!< Reception Byte Count */
+
+#define  USB_COUNT3_RX_NUM_BLOCK             ((uint16_t)0x7C00)            /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
+#define  USB_COUNT3_RX_NUM_BLOCK_0           ((uint16_t)0x0400)            /*!< Bit 0 */
+#define  USB_COUNT3_RX_NUM_BLOCK_1           ((uint16_t)0x0800)            /*!< Bit 1 */
+#define  USB_COUNT3_RX_NUM_BLOCK_2           ((uint16_t)0x1000)            /*!< Bit 2 */
+#define  USB_COUNT3_RX_NUM_BLOCK_3           ((uint16_t)0x2000)            /*!< Bit 3 */
+#define  USB_COUNT3_RX_NUM_BLOCK_4           ((uint16_t)0x4000)            /*!< Bit 4 */
+
+#define  USB_COUNT3_RX_BLSIZE                ((uint16_t)0x8000)            /*!< BLock SIZE */
+
+/*****************  Bit definition for USB_COUNT4_RX register  ****************/
+#define  USB_COUNT4_RX_COUNT4_RX             ((uint16_t)0x03FF)            /*!< Reception Byte Count */
+
+#define  USB_COUNT4_RX_NUM_BLOCK             ((uint16_t)0x7C00)            /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
+#define  USB_COUNT4_RX_NUM_BLOCK_0           ((uint16_t)0x0400)            /*!< Bit 0 */
+#define  USB_COUNT4_RX_NUM_BLOCK_1           ((uint16_t)0x0800)            /*!< Bit 1 */
+#define  USB_COUNT4_RX_NUM_BLOCK_2           ((uint16_t)0x1000)            /*!< Bit 2 */
+#define  USB_COUNT4_RX_NUM_BLOCK_3           ((uint16_t)0x2000)            /*!< Bit 3 */
+#define  USB_COUNT4_RX_NUM_BLOCK_4           ((uint16_t)0x4000)            /*!< Bit 4 */
+
+#define  USB_COUNT4_RX_BLSIZE                ((uint16_t)0x8000)            /*!< BLock SIZE */
+
+/*****************  Bit definition for USB_COUNT5_RX register  ****************/
+#define  USB_COUNT5_RX_COUNT5_RX             ((uint16_t)0x03FF)            /*!< Reception Byte Count */
+
+#define  USB_COUNT5_RX_NUM_BLOCK             ((uint16_t)0x7C00)            /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
+#define  USB_COUNT5_RX_NUM_BLOCK_0           ((uint16_t)0x0400)            /*!< Bit 0 */
+#define  USB_COUNT5_RX_NUM_BLOCK_1           ((uint16_t)0x0800)            /*!< Bit 1 */
+#define  USB_COUNT5_RX_NUM_BLOCK_2           ((uint16_t)0x1000)            /*!< Bit 2 */
+#define  USB_COUNT5_RX_NUM_BLOCK_3           ((uint16_t)0x2000)            /*!< Bit 3 */
+#define  USB_COUNT5_RX_NUM_BLOCK_4           ((uint16_t)0x4000)            /*!< Bit 4 */
+
+#define  USB_COUNT5_RX_BLSIZE                ((uint16_t)0x8000)            /*!< BLock SIZE */
+
+/*****************  Bit definition for USB_COUNT6_RX register  ****************/
+#define  USB_COUNT6_RX_COUNT6_RX             ((uint16_t)0x03FF)            /*!< Reception Byte Count */
+
+#define  USB_COUNT6_RX_NUM_BLOCK             ((uint16_t)0x7C00)            /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
+#define  USB_COUNT6_RX_NUM_BLOCK_0           ((uint16_t)0x0400)            /*!< Bit 0 */
+#define  USB_COUNT6_RX_NUM_BLOCK_1           ((uint16_t)0x0800)            /*!< Bit 1 */
+#define  USB_COUNT6_RX_NUM_BLOCK_2           ((uint16_t)0x1000)            /*!< Bit 2 */
+#define  USB_COUNT6_RX_NUM_BLOCK_3           ((uint16_t)0x2000)            /*!< Bit 3 */
+#define  USB_COUNT6_RX_NUM_BLOCK_4           ((uint16_t)0x4000)            /*!< Bit 4 */
+
+#define  USB_COUNT6_RX_BLSIZE                ((uint16_t)0x8000)            /*!< BLock SIZE */
+
+/*****************  Bit definition for USB_COUNT7_RX register  ****************/
+#define  USB_COUNT7_RX_COUNT7_RX             ((uint16_t)0x03FF)            /*!< Reception Byte Count */
+
+#define  USB_COUNT7_RX_NUM_BLOCK             ((uint16_t)0x7C00)            /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
+#define  USB_COUNT7_RX_NUM_BLOCK_0           ((uint16_t)0x0400)            /*!< Bit 0 */
+#define  USB_COUNT7_RX_NUM_BLOCK_1           ((uint16_t)0x0800)            /*!< Bit 1 */
+#define  USB_COUNT7_RX_NUM_BLOCK_2           ((uint16_t)0x1000)            /*!< Bit 2 */
+#define  USB_COUNT7_RX_NUM_BLOCK_3           ((uint16_t)0x2000)            /*!< Bit 3 */
+#define  USB_COUNT7_RX_NUM_BLOCK_4           ((uint16_t)0x4000)            /*!< Bit 4 */
+
+#define  USB_COUNT7_RX_BLSIZE                ((uint16_t)0x8000)            /*!< BLock SIZE */
+
+/*----------------------------------------------------------------------------*/
+
+/****************  Bit definition for USB_COUNT0_RX_0 register  ***************/
+#define  USB_COUNT0_RX_0_COUNT0_RX_0         ((uint32_t)0x000003FF)        /*!< Reception Byte Count (low) */
+
+#define  USB_COUNT0_RX_0_NUM_BLOCK_0         ((uint32_t)0x00007C00)        /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
+#define  USB_COUNT0_RX_0_NUM_BLOCK_0_0       ((uint32_t)0x00000400)        /*!< Bit 0 */
+#define  USB_COUNT0_RX_0_NUM_BLOCK_0_1       ((uint32_t)0x00000800)        /*!< Bit 1 */
+#define  USB_COUNT0_RX_0_NUM_BLOCK_0_2       ((uint32_t)0x00001000)        /*!< Bit 2 */
+#define  USB_COUNT0_RX_0_NUM_BLOCK_0_3       ((uint32_t)0x00002000)        /*!< Bit 3 */
+#define  USB_COUNT0_RX_0_NUM_BLOCK_0_4       ((uint32_t)0x00004000)        /*!< Bit 4 */
+
+#define  USB_COUNT0_RX_0_BLSIZE_0            ((uint32_t)0x00008000)        /*!< BLock SIZE (low) */
+
+/****************  Bit definition for USB_COUNT0_RX_1 register  ***************/
+#define  USB_COUNT0_RX_1_COUNT0_RX_1         ((uint32_t)0x03FF0000)        /*!< Reception Byte Count (high) */
+
+#define  USB_COUNT0_RX_1_NUM_BLOCK_1         ((uint32_t)0x7C000000)        /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
+#define  USB_COUNT0_RX_1_NUM_BLOCK_1_0       ((uint32_t)0x04000000)        /*!< Bit 1 */
+#define  USB_COUNT0_RX_1_NUM_BLOCK_1_1       ((uint32_t)0x08000000)        /*!< Bit 1 */
+#define  USB_COUNT0_RX_1_NUM_BLOCK_1_2       ((uint32_t)0x10000000)        /*!< Bit 2 */
+#define  USB_COUNT0_RX_1_NUM_BLOCK_1_3       ((uint32_t)0x20000000)        /*!< Bit 3 */
+#define  USB_COUNT0_RX_1_NUM_BLOCK_1_4       ((uint32_t)0x40000000)        /*!< Bit 4 */
+
+#define  USB_COUNT0_RX_1_BLSIZE_1            ((uint32_t)0x80000000)        /*!< BLock SIZE (high) */
+
+/****************  Bit definition for USB_COUNT1_RX_0 register  ***************/
+#define  USB_COUNT1_RX_0_COUNT1_RX_0         ((uint32_t)0x000003FF)        /*!< Reception Byte Count (low) */
+
+#define  USB_COUNT1_RX_0_NUM_BLOCK_0         ((uint32_t)0x00007C00)        /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
+#define  USB_COUNT1_RX_0_NUM_BLOCK_0_0       ((uint32_t)0x00000400)        /*!< Bit 0 */
+#define  USB_COUNT1_RX_0_NUM_BLOCK_0_1       ((uint32_t)0x00000800)        /*!< Bit 1 */
+#define  USB_COUNT1_RX_0_NUM_BLOCK_0_2       ((uint32_t)0x00001000)        /*!< Bit 2 */
+#define  USB_COUNT1_RX_0_NUM_BLOCK_0_3       ((uint32_t)0x00002000)        /*!< Bit 3 */
+#define  USB_COUNT1_RX_0_NUM_BLOCK_0_4       ((uint32_t)0x00004000)        /*!< Bit 4 */
+
+#define  USB_COUNT1_RX_0_BLSIZE_0            ((uint32_t)0x00008000)        /*!< BLock SIZE (low) */
+
+/****************  Bit definition for USB_COUNT1_RX_1 register  ***************/
+#define  USB_COUNT1_RX_1_COUNT1_RX_1         ((uint32_t)0x03FF0000)        /*!< Reception Byte Count (high) */
+
+#define  USB_COUNT1_RX_1_NUM_BLOCK_1         ((uint32_t)0x7C000000)        /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
+#define  USB_COUNT1_RX_1_NUM_BLOCK_1_0       ((uint32_t)0x04000000)        /*!< Bit 0 */
+#define  USB_COUNT1_RX_1_NUM_BLOCK_1_1       ((uint32_t)0x08000000)        /*!< Bit 1 */
+#define  USB_COUNT1_RX_1_NUM_BLOCK_1_2       ((uint32_t)0x10000000)        /*!< Bit 2 */
+#define  USB_COUNT1_RX_1_NUM_BLOCK_1_3       ((uint32_t)0x20000000)        /*!< Bit 3 */
+#define  USB_COUNT1_RX_1_NUM_BLOCK_1_4       ((uint32_t)0x40000000)        /*!< Bit 4 */
+
+#define  USB_COUNT1_RX_1_BLSIZE_1            ((uint32_t)0x80000000)        /*!< BLock SIZE (high) */
+
+/****************  Bit definition for USB_COUNT2_RX_0 register  ***************/
+#define  USB_COUNT2_RX_0_COUNT2_RX_0         ((uint32_t)0x000003FF)        /*!< Reception Byte Count (low) */
+
+#define  USB_COUNT2_RX_0_NUM_BLOCK_0         ((uint32_t)0x00007C00)        /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
+#define  USB_COUNT2_RX_0_NUM_BLOCK_0_0       ((uint32_t)0x00000400)        /*!< Bit 0 */
+#define  USB_COUNT2_RX_0_NUM_BLOCK_0_1       ((uint32_t)0x00000800)        /*!< Bit 1 */
+#define  USB_COUNT2_RX_0_NUM_BLOCK_0_2       ((uint32_t)0x00001000)        /*!< Bit 2 */
+#define  USB_COUNT2_RX_0_NUM_BLOCK_0_3       ((uint32_t)0x00002000)        /*!< Bit 3 */
+#define  USB_COUNT2_RX_0_NUM_BLOCK_0_4       ((uint32_t)0x00004000)        /*!< Bit 4 */
+
+#define  USB_COUNT2_RX_0_BLSIZE_0            ((uint32_t)0x00008000)        /*!< BLock SIZE (low) */
+
+/****************  Bit definition for USB_COUNT2_RX_1 register  ***************/
+#define  USB_COUNT2_RX_1_COUNT2_RX_1         ((uint32_t)0x03FF0000)        /*!< Reception Byte Count (high) */
+
+#define  USB_COUNT2_RX_1_NUM_BLOCK_1         ((uint32_t)0x7C000000)        /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
+#define  USB_COUNT2_RX_1_NUM_BLOCK_1_0       ((uint32_t)0x04000000)        /*!< Bit 0 */
+#define  USB_COUNT2_RX_1_NUM_BLOCK_1_1       ((uint32_t)0x08000000)        /*!< Bit 1 */
+#define  USB_COUNT2_RX_1_NUM_BLOCK_1_2       ((uint32_t)0x10000000)        /*!< Bit 2 */
+#define  USB_COUNT2_RX_1_NUM_BLOCK_1_3       ((uint32_t)0x20000000)        /*!< Bit 3 */
+#define  USB_COUNT2_RX_1_NUM_BLOCK_1_4       ((uint32_t)0x40000000)        /*!< Bit 4 */
+
+#define  USB_COUNT2_RX_1_BLSIZE_1            ((uint32_t)0x80000000)        /*!< BLock SIZE (high) */
+
+/****************  Bit definition for USB_COUNT3_RX_0 register  ***************/
+#define  USB_COUNT3_RX_0_COUNT3_RX_0         ((uint32_t)0x000003FF)        /*!< Reception Byte Count (low) */
+
+#define  USB_COUNT3_RX_0_NUM_BLOCK_0         ((uint32_t)0x00007C00)        /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
+#define  USB_COUNT3_RX_0_NUM_BLOCK_0_0       ((uint32_t)0x00000400)        /*!< Bit 0 */
+#define  USB_COUNT3_RX_0_NUM_BLOCK_0_1       ((uint32_t)0x00000800)        /*!< Bit 1 */
+#define  USB_COUNT3_RX_0_NUM_BLOCK_0_2       ((uint32_t)0x00001000)        /*!< Bit 2 */
+#define  USB_COUNT3_RX_0_NUM_BLOCK_0_3       ((uint32_t)0x00002000)        /*!< Bit 3 */
+#define  USB_COUNT3_RX_0_NUM_BLOCK_0_4       ((uint32_t)0x00004000)        /*!< Bit 4 */
+
+#define  USB_COUNT3_RX_0_BLSIZE_0            ((uint32_t)0x00008000)        /*!< BLock SIZE (low) */
+
+/****************  Bit definition for USB_COUNT3_RX_1 register  ***************/
+#define  USB_COUNT3_RX_1_COUNT3_RX_1         ((uint32_t)0x03FF0000)        /*!< Reception Byte Count (high) */
+
+#define  USB_COUNT3_RX_1_NUM_BLOCK_1         ((uint32_t)0x7C000000)        /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
+#define  USB_COUNT3_RX_1_NUM_BLOCK_1_0       ((uint32_t)0x04000000)        /*!< Bit 0 */
+#define  USB_COUNT3_RX_1_NUM_BLOCK_1_1       ((uint32_t)0x08000000)        /*!< Bit 1 */
+#define  USB_COUNT3_RX_1_NUM_BLOCK_1_2       ((uint32_t)0x10000000)        /*!< Bit 2 */
+#define  USB_COUNT3_RX_1_NUM_BLOCK_1_3       ((uint32_t)0x20000000)        /*!< Bit 3 */
+#define  USB_COUNT3_RX_1_NUM_BLOCK_1_4       ((uint32_t)0x40000000)        /*!< Bit 4 */
+
+#define  USB_COUNT3_RX_1_BLSIZE_1            ((uint32_t)0x80000000)        /*!< BLock SIZE (high) */
+
+/****************  Bit definition for USB_COUNT4_RX_0 register  ***************/
+#define  USB_COUNT4_RX_0_COUNT4_RX_0         ((uint32_t)0x000003FF)        /*!< Reception Byte Count (low) */
+
+#define  USB_COUNT4_RX_0_NUM_BLOCK_0         ((uint32_t)0x00007C00)        /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
+#define  USB_COUNT4_RX_0_NUM_BLOCK_0_0      ((uint32_t)0x00000400)        /*!< Bit 0 */
+#define  USB_COUNT4_RX_0_NUM_BLOCK_0_1      ((uint32_t)0x00000800)        /*!< Bit 1 */
+#define  USB_COUNT4_RX_0_NUM_BLOCK_0_2      ((uint32_t)0x00001000)        /*!< Bit 2 */
+#define  USB_COUNT4_RX_0_NUM_BLOCK_0_3      ((uint32_t)0x00002000)        /*!< Bit 3 */
+#define  USB_COUNT4_RX_0_NUM_BLOCK_0_4      ((uint32_t)0x00004000)        /*!< Bit 4 */
+
+#define  USB_COUNT4_RX_0_BLSIZE_0            ((uint32_t)0x00008000)        /*!< BLock SIZE (low) */
+
+/****************  Bit definition for USB_COUNT4_RX_1 register  ***************/
+#define  USB_COUNT4_RX_1_COUNT4_RX_1         ((uint32_t)0x03FF0000)        /*!< Reception Byte Count (high) */
+
+#define  USB_COUNT4_RX_1_NUM_BLOCK_1         ((uint32_t)0x7C000000)        /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
+#define  USB_COUNT4_RX_1_NUM_BLOCK_1_0       ((uint32_t)0x04000000)        /*!< Bit 0 */
+#define  USB_COUNT4_RX_1_NUM_BLOCK_1_1       ((uint32_t)0x08000000)        /*!< Bit 1 */
+#define  USB_COUNT4_RX_1_NUM_BLOCK_1_2       ((uint32_t)0x10000000)        /*!< Bit 2 */
+#define  USB_COUNT4_RX_1_NUM_BLOCK_1_3       ((uint32_t)0x20000000)        /*!< Bit 3 */
+#define  USB_COUNT4_RX_1_NUM_BLOCK_1_4       ((uint32_t)0x40000000)        /*!< Bit 4 */
+
+#define  USB_COUNT4_RX_1_BLSIZE_1            ((uint32_t)0x80000000)        /*!< BLock SIZE (high) */
+
+/****************  Bit definition for USB_COUNT5_RX_0 register  ***************/
+#define  USB_COUNT5_RX_0_COUNT5_RX_0         ((uint32_t)0x000003FF)        /*!< Reception Byte Count (low) */
+
+#define  USB_COUNT5_RX_0_NUM_BLOCK_0         ((uint32_t)0x00007C00)        /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
+#define  USB_COUNT5_RX_0_NUM_BLOCK_0_0       ((uint32_t)0x00000400)        /*!< Bit 0 */
+#define  USB_COUNT5_RX_0_NUM_BLOCK_0_1       ((uint32_t)0x00000800)        /*!< Bit 1 */
+#define  USB_COUNT5_RX_0_NUM_BLOCK_0_2       ((uint32_t)0x00001000)        /*!< Bit 2 */
+#define  USB_COUNT5_RX_0_NUM_BLOCK_0_3       ((uint32_t)0x00002000)        /*!< Bit 3 */
+#define  USB_COUNT5_RX_0_NUM_BLOCK_0_4       ((uint32_t)0x00004000)        /*!< Bit 4 */
+
+#define  USB_COUNT5_RX_0_BLSIZE_0            ((uint32_t)0x00008000)        /*!< BLock SIZE (low) */
+
+/****************  Bit definition for USB_COUNT5_RX_1 register  ***************/
+#define  USB_COUNT5_RX_1_COUNT5_RX_1         ((uint32_t)0x03FF0000)        /*!< Reception Byte Count (high) */
+
+#define  USB_COUNT5_RX_1_NUM_BLOCK_1         ((uint32_t)0x7C000000)        /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
+#define  USB_COUNT5_RX_1_NUM_BLOCK_1_0       ((uint32_t)0x04000000)        /*!< Bit 0 */
+#define  USB_COUNT5_RX_1_NUM_BLOCK_1_1       ((uint32_t)0x08000000)        /*!< Bit 1 */
+#define  USB_COUNT5_RX_1_NUM_BLOCK_1_2       ((uint32_t)0x10000000)        /*!< Bit 2 */
+#define  USB_COUNT5_RX_1_NUM_BLOCK_1_3       ((uint32_t)0x20000000)        /*!< Bit 3 */
+#define  USB_COUNT5_RX_1_NUM_BLOCK_1_4       ((uint32_t)0x40000000)        /*!< Bit 4 */
+
+#define  USB_COUNT5_RX_1_BLSIZE_1            ((uint32_t)0x80000000)        /*!< BLock SIZE (high) */
+
+/***************  Bit definition for USB_COUNT6_RX_0  register  ***************/
+#define  USB_COUNT6_RX_0_COUNT6_RX_0         ((uint32_t)0x000003FF)        /*!< Reception Byte Count (low) */
+
+#define  USB_COUNT6_RX_0_NUM_BLOCK_0         ((uint32_t)0x00007C00)        /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
+#define  USB_COUNT6_RX_0_NUM_BLOCK_0_0       ((uint32_t)0x00000400)        /*!< Bit 0 */
+#define  USB_COUNT6_RX_0_NUM_BLOCK_0_1       ((uint32_t)0x00000800)        /*!< Bit 1 */
+#define  USB_COUNT6_RX_0_NUM_BLOCK_0_2       ((uint32_t)0x00001000)        /*!< Bit 2 */
+#define  USB_COUNT6_RX_0_NUM_BLOCK_0_3       ((uint32_t)0x00002000)        /*!< Bit 3 */
+#define  USB_COUNT6_RX_0_NUM_BLOCK_0_4       ((uint32_t)0x00004000)        /*!< Bit 4 */
+
+#define  USB_COUNT6_RX_0_BLSIZE_0            ((uint32_t)0x00008000)        /*!< BLock SIZE (low) */
+
+/****************  Bit definition for USB_COUNT6_RX_1 register  ***************/
+#define  USB_COUNT6_RX_1_COUNT6_RX_1         ((uint32_t)0x03FF0000)        /*!< Reception Byte Count (high) */
+
+#define  USB_COUNT6_RX_1_NUM_BLOCK_1         ((uint32_t)0x7C000000)        /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
+#define  USB_COUNT6_RX_1_NUM_BLOCK_1_0       ((uint32_t)0x04000000)        /*!< Bit 0 */
+#define  USB_COUNT6_RX_1_NUM_BLOCK_1_1       ((uint32_t)0x08000000)        /*!< Bit 1 */
+#define  USB_COUNT6_RX_1_NUM_BLOCK_1_2       ((uint32_t)0x10000000)        /*!< Bit 2 */
+#define  USB_COUNT6_RX_1_NUM_BLOCK_1_3       ((uint32_t)0x20000000)        /*!< Bit 3 */
+#define  USB_COUNT6_RX_1_NUM_BLOCK_1_4       ((uint32_t)0x40000000)        /*!< Bit 4 */
+
+#define  USB_COUNT6_RX_1_BLSIZE_1            ((uint32_t)0x80000000)        /*!< BLock SIZE (high) */
+
+/***************  Bit definition for USB_COUNT7_RX_0 register  ****************/
+#define  USB_COUNT7_RX_0_COUNT7_RX_0         ((uint32_t)0x000003FF)        /*!< Reception Byte Count (low) */
+
+#define  USB_COUNT7_RX_0_NUM_BLOCK_0         ((uint32_t)0x00007C00)        /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
+#define  USB_COUNT7_RX_0_NUM_BLOCK_0_0       ((uint32_t)0x00000400)        /*!< Bit 0 */
+#define  USB_COUNT7_RX_0_NUM_BLOCK_0_1       ((uint32_t)0x00000800)        /*!< Bit 1 */
+#define  USB_COUNT7_RX_0_NUM_BLOCK_0_2       ((uint32_t)0x00001000)        /*!< Bit 2 */
+#define  USB_COUNT7_RX_0_NUM_BLOCK_0_3       ((uint32_t)0x00002000)        /*!< Bit 3 */
+#define  USB_COUNT7_RX_0_NUM_BLOCK_0_4       ((uint32_t)0x00004000)        /*!< Bit 4 */
+
+#define  USB_COUNT7_RX_0_BLSIZE_0            ((uint32_t)0x00008000)        /*!< BLock SIZE (low) */
+
+/***************  Bit definition for USB_COUNT7_RX_1 register  ****************/
+#define  USB_COUNT7_RX_1_COUNT7_RX_1         ((uint32_t)0x03FF0000)        /*!< Reception Byte Count (high) */
+
+#define  USB_COUNT7_RX_1_NUM_BLOCK_1         ((uint32_t)0x7C000000)        /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
+#define  USB_COUNT7_RX_1_NUM_BLOCK_1_0       ((uint32_t)0x04000000)        /*!< Bit 0 */
+#define  USB_COUNT7_RX_1_NUM_BLOCK_1_1       ((uint32_t)0x08000000)        /*!< Bit 1 */
+#define  USB_COUNT7_RX_1_NUM_BLOCK_1_2       ((uint32_t)0x10000000)        /*!< Bit 2 */
+#define  USB_COUNT7_RX_1_NUM_BLOCK_1_3       ((uint32_t)0x20000000)        /*!< Bit 3 */
+#define  USB_COUNT7_RX_1_NUM_BLOCK_1_4       ((uint32_t)0x40000000)        /*!< Bit 4 */
+
+#define  USB_COUNT7_RX_1_BLSIZE_1            ((uint32_t)0x80000000)        /*!< BLock SIZE (high) */
+
+/******************************************************************************/
+/*                                                                            */
+/*                         Controller Area Network                            */
+/*                                                                            */
+/******************************************************************************/
+
+/*!< CAN control and status registers */
+/*******************  Bit definition for CAN_MCR register  ********************/
+#define  CAN_MCR_INRQ                        ((uint16_t)0x0001)            /*!< Initialization Request */
+#define  CAN_MCR_SLEEP                       ((uint16_t)0x0002)            /*!< Sleep Mode Request */
+#define  CAN_MCR_TXFP                        ((uint16_t)0x0004)            /*!< Transmit FIFO Priority */
+#define  CAN_MCR_RFLM                        ((uint16_t)0x0008)            /*!< Receive FIFO Locked Mode */
+#define  CAN_MCR_NART                        ((uint16_t)0x0010)            /*!< No Automatic Retransmission */
+#define  CAN_MCR_AWUM                        ((uint16_t)0x0020)            /*!< Automatic Wakeup Mode */
+#define  CAN_MCR_ABOM                        ((uint16_t)0x0040)            /*!< Automatic Bus-Off Management */
+#define  CAN_MCR_TTCM                        ((uint16_t)0x0080)            /*!< Time Triggered Communication Mode */
+#define  CAN_MCR_RESET                       ((uint16_t)0x8000)            /*!< CAN software master reset */
+
+/*******************  Bit definition for CAN_MSR register  ********************/
+#define  CAN_MSR_INAK                        ((uint16_t)0x0001)            /*!< Initialization Acknowledge */
+#define  CAN_MSR_SLAK                        ((uint16_t)0x0002)            /*!< Sleep Acknowledge */
+#define  CAN_MSR_ERRI                        ((uint16_t)0x0004)            /*!< Error Interrupt */
+#define  CAN_MSR_WKUI                        ((uint16_t)0x0008)            /*!< Wakeup Interrupt */
+#define  CAN_MSR_SLAKI                       ((uint16_t)0x0010)            /*!< Sleep Acknowledge Interrupt */
+#define  CAN_MSR_TXM                         ((uint16_t)0x0100)            /*!< Transmit Mode */
+#define  CAN_MSR_RXM                         ((uint16_t)0x0200)            /*!< Receive Mode */
+#define  CAN_MSR_SAMP                        ((uint16_t)0x0400)            /*!< Last Sample Point */
+#define  CAN_MSR_RX                          ((uint16_t)0x0800)            /*!< CAN Rx Signal */
+
+/*******************  Bit definition for CAN_TSR register  ********************/
+#define  CAN_TSR_RQCP0                       ((uint32_t)0x00000001)        /*!< Request Completed Mailbox0 */
+#define  CAN_TSR_TXOK0                       ((uint32_t)0x00000002)        /*!< Transmission OK of Mailbox0 */
+#define  CAN_TSR_ALST0                       ((uint32_t)0x00000004)        /*!< Arbitration Lost for Mailbox0 */
+#define  CAN_TSR_TERR0                       ((uint32_t)0x00000008)        /*!< Transmission Error of Mailbox0 */
+#define  CAN_TSR_ABRQ0                       ((uint32_t)0x00000080)        /*!< Abort Request for Mailbox0 */
+#define  CAN_TSR_RQCP1                       ((uint32_t)0x00000100)        /*!< Request Completed Mailbox1 */
+#define  CAN_TSR_TXOK1                       ((uint32_t)0x00000200)        /*!< Transmission OK of Mailbox1 */
+#define  CAN_TSR_ALST1                       ((uint32_t)0x00000400)        /*!< Arbitration Lost for Mailbox1 */
+#define  CAN_TSR_TERR1                       ((uint32_t)0x00000800)        /*!< Transmission Error of Mailbox1 */
+#define  CAN_TSR_ABRQ1                       ((uint32_t)0x00008000)        /*!< Abort Request for Mailbox 1 */
+#define  CAN_TSR_RQCP2                       ((uint32_t)0x00010000)        /*!< Request Completed Mailbox2 */
+#define  CAN_TSR_TXOK2                       ((uint32_t)0x00020000)        /*!< Transmission OK of Mailbox 2 */
+#define  CAN_TSR_ALST2                       ((uint32_t)0x00040000)        /*!< Arbitration Lost for mailbox 2 */
+#define  CAN_TSR_TERR2                       ((uint32_t)0x00080000)        /*!< Transmission Error of Mailbox 2 */
+#define  CAN_TSR_ABRQ2                       ((uint32_t)0x00800000)        /*!< Abort Request for Mailbox 2 */
+#define  CAN_TSR_CODE                        ((uint32_t)0x03000000)        /*!< Mailbox Code */
+
+#define  CAN_TSR_TME                         ((uint32_t)0x1C000000)        /*!< TME[2:0] bits */
+#define  CAN_TSR_TME0                        ((uint32_t)0x04000000)        /*!< Transmit Mailbox 0 Empty */
+#define  CAN_TSR_TME1                        ((uint32_t)0x08000000)        /*!< Transmit Mailbox 1 Empty */
+#define  CAN_TSR_TME2                        ((uint32_t)0x10000000)        /*!< Transmit Mailbox 2 Empty */
+
+#define  CAN_TSR_LOW                         ((uint32_t)0xE0000000)        /*!< LOW[2:0] bits */
+#define  CAN_TSR_LOW0                        ((uint32_t)0x20000000)        /*!< Lowest Priority Flag for Mailbox 0 */
+#define  CAN_TSR_LOW1                        ((uint32_t)0x40000000)        /*!< Lowest Priority Flag for Mailbox 1 */
+#define  CAN_TSR_LOW2                        ((uint32_t)0x80000000)        /*!< Lowest Priority Flag for Mailbox 2 */
+
+/*******************  Bit definition for CAN_RF0R register  *******************/
+#define  CAN_RF0R_FMP0                       ((uint8_t)0x03)               /*!< FIFO 0 Message Pending */
+#define  CAN_RF0R_FULL0                      ((uint8_t)0x08)               /*!< FIFO 0 Full */
+#define  CAN_RF0R_FOVR0                      ((uint8_t)0x10)               /*!< FIFO 0 Overrun */
+#define  CAN_RF0R_RFOM0                      ((uint8_t)0x20)               /*!< Release FIFO 0 Output Mailbox */
+
+/*******************  Bit definition for CAN_RF1R register  *******************/
+#define  CAN_RF1R_FMP1                       ((uint8_t)0x03)               /*!< FIFO 1 Message Pending */
+#define  CAN_RF1R_FULL1                      ((uint8_t)0x08)               /*!< FIFO 1 Full */
+#define  CAN_RF1R_FOVR1                      ((uint8_t)0x10)               /*!< FIFO 1 Overrun */
+#define  CAN_RF1R_RFOM1                      ((uint8_t)0x20)               /*!< Release FIFO 1 Output Mailbox */
+
+/********************  Bit definition for CAN_IER register  *******************/
+#define  CAN_IER_TMEIE                       ((uint32_t)0x00000001)        /*!< Transmit Mailbox Empty Interrupt Enable */
+#define  CAN_IER_FMPIE0                      ((uint32_t)0x00000002)        /*!< FIFO Message Pending Interrupt Enable */
+#define  CAN_IER_FFIE0                       ((uint32_t)0x00000004)        /*!< FIFO Full Interrupt Enable */
+#define  CAN_IER_FOVIE0                      ((uint32_t)0x00000008)        /*!< FIFO Overrun Interrupt Enable */
+#define  CAN_IER_FMPIE1                      ((uint32_t)0x00000010)        /*!< FIFO Message Pending Interrupt Enable */
+#define  CAN_IER_FFIE1                       ((uint32_t)0x00000020)        /*!< FIFO Full Interrupt Enable */
+#define  CAN_IER_FOVIE1                      ((uint32_t)0x00000040)        /*!< FIFO Overrun Interrupt Enable */
+#define  CAN_IER_EWGIE                       ((uint32_t)0x00000100)        /*!< Error Warning Interrupt Enable */
+#define  CAN_IER_EPVIE                       ((uint32_t)0x00000200)        /*!< Error Passive Interrupt Enable */
+#define  CAN_IER_BOFIE                       ((uint32_t)0x00000400)        /*!< Bus-Off Interrupt Enable */
+#define  CAN_IER_LECIE                       ((uint32_t)0x00000800)        /*!< Last Error Code Interrupt Enable */
+#define  CAN_IER_ERRIE                       ((uint32_t)0x00008000)        /*!< Error Interrupt Enable */
+#define  CAN_IER_WKUIE                       ((uint32_t)0x00010000)        /*!< Wakeup Interrupt Enable */
+#define  CAN_IER_SLKIE                       ((uint32_t)0x00020000)        /*!< Sleep Interrupt Enable */
+
+/********************  Bit definition for CAN_ESR register  *******************/
+#define  CAN_ESR_EWGF                        ((uint32_t)0x00000001)        /*!< Error Warning Flag */
+#define  CAN_ESR_EPVF                        ((uint32_t)0x00000002)        /*!< Error Passive Flag */
+#define  CAN_ESR_BOFF                        ((uint32_t)0x00000004)        /*!< Bus-Off Flag */
+
+#define  CAN_ESR_LEC                         ((uint32_t)0x00000070)        /*!< LEC[2:0] bits (Last Error Code) */
+#define  CAN_ESR_LEC_0                       ((uint32_t)0x00000010)        /*!< Bit 0 */
+#define  CAN_ESR_LEC_1                       ((uint32_t)0x00000020)        /*!< Bit 1 */
+#define  CAN_ESR_LEC_2                       ((uint32_t)0x00000040)        /*!< Bit 2 */
+
+#define  CAN_ESR_TEC                         ((uint32_t)0x00FF0000)        /*!< Least significant byte of the 9-bit Transmit Error Counter */
+#define  CAN_ESR_REC                         ((uint32_t)0xFF000000)        /*!< Receive Error Counter */
+
+/*******************  Bit definition for CAN_BTR register  ********************/
+#define  CAN_BTR_BRP                         ((uint32_t)0x000003FF)        /*!< Baud Rate Prescaler */
+#define  CAN_BTR_TS1                         ((uint32_t)0x000F0000)        /*!< Time Segment 1 */
+#define  CAN_BTR_TS2                         ((uint32_t)0x00700000)        /*!< Time Segment 2 */
+#define  CAN_BTR_SJW                         ((uint32_t)0x03000000)        /*!< Resynchronization Jump Width */
+#define  CAN_BTR_LBKM                        ((uint32_t)0x40000000)        /*!< Loop Back Mode (Debug) */
+#define  CAN_BTR_SILM                        ((uint32_t)0x80000000)        /*!< Silent Mode */
+
+/*!< Mailbox registers */
+/******************  Bit definition for CAN_TI0R register  ********************/
+#define  CAN_TI0R_TXRQ                       ((uint32_t)0x00000001)        /*!< Transmit Mailbox Request */
+#define  CAN_TI0R_RTR                        ((uint32_t)0x00000002)        /*!< Remote Transmission Request */
+#define  CAN_TI0R_IDE                        ((uint32_t)0x00000004)        /*!< Identifier Extension */
+#define  CAN_TI0R_EXID                       ((uint32_t)0x001FFFF8)        /*!< Extended Identifier */
+#define  CAN_TI0R_STID                       ((uint32_t)0xFFE00000)        /*!< Standard Identifier or Extended Identifier */
+
+/******************  Bit definition for CAN_TDT0R register  *******************/
+#define  CAN_TDT0R_DLC                       ((uint32_t)0x0000000F)        /*!< Data Length Code */
+#define  CAN_TDT0R_TGT                       ((uint32_t)0x00000100)        /*!< Transmit Global Time */
+#define  CAN_TDT0R_TIME                      ((uint32_t)0xFFFF0000)        /*!< Message Time Stamp */
+
+/******************  Bit definition for CAN_TDL0R register  *******************/
+#define  CAN_TDL0R_DATA0                     ((uint32_t)0x000000FF)        /*!< Data byte 0 */
+#define  CAN_TDL0R_DATA1                     ((uint32_t)0x0000FF00)        /*!< Data byte 1 */
+#define  CAN_TDL0R_DATA2                     ((uint32_t)0x00FF0000)        /*!< Data byte 2 */
+#define  CAN_TDL0R_DATA3                     ((uint32_t)0xFF000000)        /*!< Data byte 3 */
+
+/******************  Bit definition for CAN_TDH0R register  *******************/
+#define  CAN_TDH0R_DATA4                     ((uint32_t)0x000000FF)        /*!< Data byte 4 */
+#define  CAN_TDH0R_DATA5                     ((uint32_t)0x0000FF00)        /*!< Data byte 5 */
+#define  CAN_TDH0R_DATA6                     ((uint32_t)0x00FF0000)        /*!< Data byte 6 */
+#define  CAN_TDH0R_DATA7                     ((uint32_t)0xFF000000)        /*!< Data byte 7 */
+
+/*******************  Bit definition for CAN_TI1R register  *******************/
+#define  CAN_TI1R_TXRQ                       ((uint32_t)0x00000001)        /*!< Transmit Mailbox Request */
+#define  CAN_TI1R_RTR                        ((uint32_t)0x00000002)        /*!< Remote Transmission Request */
+#define  CAN_TI1R_IDE                        ((uint32_t)0x00000004)        /*!< Identifier Extension */
+#define  CAN_TI1R_EXID                       ((uint32_t)0x001FFFF8)        /*!< Extended Identifier */
+#define  CAN_TI1R_STID                       ((uint32_t)0xFFE00000)        /*!< Standard Identifier or Extended Identifier */
+
+/*******************  Bit definition for CAN_TDT1R register  ******************/
+#define  CAN_TDT1R_DLC                       ((uint32_t)0x0000000F)        /*!< Data Length Code */
+#define  CAN_TDT1R_TGT                       ((uint32_t)0x00000100)        /*!< Transmit Global Time */
+#define  CAN_TDT1R_TIME                      ((uint32_t)0xFFFF0000)        /*!< Message Time Stamp */
+
+/*******************  Bit definition for CAN_TDL1R register  ******************/
+#define  CAN_TDL1R_DATA0                     ((uint32_t)0x000000FF)        /*!< Data byte 0 */
+#define  CAN_TDL1R_DATA1                     ((uint32_t)0x0000FF00)        /*!< Data byte 1 */
+#define  CAN_TDL1R_DATA2                     ((uint32_t)0x00FF0000)        /*!< Data byte 2 */
+#define  CAN_TDL1R_DATA3                     ((uint32_t)0xFF000000)        /*!< Data byte 3 */
+
+/*******************  Bit definition for CAN_TDH1R register  ******************/
+#define  CAN_TDH1R_DATA4                     ((uint32_t)0x000000FF)        /*!< Data byte 4 */
+#define  CAN_TDH1R_DATA5                     ((uint32_t)0x0000FF00)        /*!< Data byte 5 */
+#define  CAN_TDH1R_DATA6                     ((uint32_t)0x00FF0000)        /*!< Data byte 6 */
+#define  CAN_TDH1R_DATA7                     ((uint32_t)0xFF000000)        /*!< Data byte 7 */
+
+/*******************  Bit definition for CAN_TI2R register  *******************/
+#define  CAN_TI2R_TXRQ                       ((uint32_t)0x00000001)        /*!< Transmit Mailbox Request */
+#define  CAN_TI2R_RTR                        ((uint32_t)0x00000002)        /*!< Remote Transmission Request */
+#define  CAN_TI2R_IDE                        ((uint32_t)0x00000004)        /*!< Identifier Extension */
+#define  CAN_TI2R_EXID                       ((uint32_t)0x001FFFF8)        /*!< Extended identifier */
+#define  CAN_TI2R_STID                       ((uint32_t)0xFFE00000)        /*!< Standard Identifier or Extended Identifier */
+
+/*******************  Bit definition for CAN_TDT2R register  ******************/  
+#define  CAN_TDT2R_DLC                       ((uint32_t)0x0000000F)        /*!< Data Length Code */
+#define  CAN_TDT2R_TGT                       ((uint32_t)0x00000100)        /*!< Transmit Global Time */
+#define  CAN_TDT2R_TIME                      ((uint32_t)0xFFFF0000)        /*!< Message Time Stamp */
+
+/*******************  Bit definition for CAN_TDL2R register  ******************/
+#define  CAN_TDL2R_DATA0                     ((uint32_t)0x000000FF)        /*!< Data byte 0 */
+#define  CAN_TDL2R_DATA1                     ((uint32_t)0x0000FF00)        /*!< Data byte 1 */
+#define  CAN_TDL2R_DATA2                     ((uint32_t)0x00FF0000)        /*!< Data byte 2 */
+#define  CAN_TDL2R_DATA3                     ((uint32_t)0xFF000000)        /*!< Data byte 3 */
+
+/*******************  Bit definition for CAN_TDH2R register  ******************/
+#define  CAN_TDH2R_DATA4                     ((uint32_t)0x000000FF)        /*!< Data byte 4 */
+#define  CAN_TDH2R_DATA5                     ((uint32_t)0x0000FF00)        /*!< Data byte 5 */
+#define  CAN_TDH2R_DATA6                     ((uint32_t)0x00FF0000)        /*!< Data byte 6 */
+#define  CAN_TDH2R_DATA7                     ((uint32_t)0xFF000000)        /*!< Data byte 7 */
+
+/*******************  Bit definition for CAN_RI0R register  *******************/
+#define  CAN_RI0R_RTR                        ((uint32_t)0x00000002)        /*!< Remote Transmission Request */
+#define  CAN_RI0R_IDE                        ((uint32_t)0x00000004)        /*!< Identifier Extension */
+#define  CAN_RI0R_EXID                       ((uint32_t)0x001FFFF8)        /*!< Extended Identifier */
+#define  CAN_RI0R_STID                       ((uint32_t)0xFFE00000)        /*!< Standard Identifier or Extended Identifier */
+
+/*******************  Bit definition for CAN_RDT0R register  ******************/
+#define  CAN_RDT0R_DLC                       ((uint32_t)0x0000000F)        /*!< Data Length Code */
+#define  CAN_RDT0R_FMI                       ((uint32_t)0x0000FF00)        /*!< Filter Match Index */
+#define  CAN_RDT0R_TIME                      ((uint32_t)0xFFFF0000)        /*!< Message Time Stamp */
+
+/*******************  Bit definition for CAN_RDL0R register  ******************/
+#define  CAN_RDL0R_DATA0                     ((uint32_t)0x000000FF)        /*!< Data byte 0 */
+#define  CAN_RDL0R_DATA1                     ((uint32_t)0x0000FF00)        /*!< Data byte 1 */
+#define  CAN_RDL0R_DATA2                     ((uint32_t)0x00FF0000)        /*!< Data byte 2 */
+#define  CAN_RDL0R_DATA3                     ((uint32_t)0xFF000000)        /*!< Data byte 3 */
+
+/*******************  Bit definition for CAN_RDH0R register  ******************/
+#define  CAN_RDH0R_DATA4                     ((uint32_t)0x000000FF)        /*!< Data byte 4 */
+#define  CAN_RDH0R_DATA5                     ((uint32_t)0x0000FF00)        /*!< Data byte 5 */
+#define  CAN_RDH0R_DATA6                     ((uint32_t)0x00FF0000)        /*!< Data byte 6 */
+#define  CAN_RDH0R_DATA7                     ((uint32_t)0xFF000000)        /*!< Data byte 7 */
+
+/*******************  Bit definition for CAN_RI1R register  *******************/
+#define  CAN_RI1R_RTR                        ((uint32_t)0x00000002)        /*!< Remote Transmission Request */
+#define  CAN_RI1R_IDE                        ((uint32_t)0x00000004)        /*!< Identifier Extension */
+#define  CAN_RI1R_EXID                       ((uint32_t)0x001FFFF8)        /*!< Extended identifier */
+#define  CAN_RI1R_STID                       ((uint32_t)0xFFE00000)        /*!< Standard Identifier or Extended Identifier */
+
+/*******************  Bit definition for CAN_RDT1R register  ******************/
+#define  CAN_RDT1R_DLC                       ((uint32_t)0x0000000F)        /*!< Data Length Code */
+#define  CAN_RDT1R_FMI                       ((uint32_t)0x0000FF00)        /*!< Filter Match Index */
+#define  CAN_RDT1R_TIME                      ((uint32_t)0xFFFF0000)        /*!< Message Time Stamp */
+
+/*******************  Bit definition for CAN_RDL1R register  ******************/
+#define  CAN_RDL1R_DATA0                     ((uint32_t)0x000000FF)        /*!< Data byte 0 */
+#define  CAN_RDL1R_DATA1                     ((uint32_t)0x0000FF00)        /*!< Data byte 1 */
+#define  CAN_RDL1R_DATA2                     ((uint32_t)0x00FF0000)        /*!< Data byte 2 */
+#define  CAN_RDL1R_DATA3                     ((uint32_t)0xFF000000)        /*!< Data byte 3 */
+
+/*******************  Bit definition for CAN_RDH1R register  ******************/
+#define  CAN_RDH1R_DATA4                     ((uint32_t)0x000000FF)        /*!< Data byte 4 */
+#define  CAN_RDH1R_DATA5                     ((uint32_t)0x0000FF00)        /*!< Data byte 5 */
+#define  CAN_RDH1R_DATA6                     ((uint32_t)0x00FF0000)        /*!< Data byte 6 */
+#define  CAN_RDH1R_DATA7                     ((uint32_t)0xFF000000)        /*!< Data byte 7 */
+
+/*!< CAN filter registers */
+/*******************  Bit definition for CAN_FMR register  ********************/
+#define  CAN_FMR_FINIT                       ((uint8_t)0x01)               /*!< Filter Init Mode */
+
+/*******************  Bit definition for CAN_FM1R register  *******************/
+#define  CAN_FM1R_FBM                        ((uint16_t)0x3FFF)            /*!< Filter Mode */
+#define  CAN_FM1R_FBM0                       ((uint16_t)0x0001)            /*!< Filter Init Mode bit 0 */
+#define  CAN_FM1R_FBM1                       ((uint16_t)0x0002)            /*!< Filter Init Mode bit 1 */
+#define  CAN_FM1R_FBM2                       ((uint16_t)0x0004)            /*!< Filter Init Mode bit 2 */
+#define  CAN_FM1R_FBM3                       ((uint16_t)0x0008)            /*!< Filter Init Mode bit 3 */
+#define  CAN_FM1R_FBM4                       ((uint16_t)0x0010)            /*!< Filter Init Mode bit 4 */
+#define  CAN_FM1R_FBM5                       ((uint16_t)0x0020)            /*!< Filter Init Mode bit 5 */
+#define  CAN_FM1R_FBM6                       ((uint16_t)0x0040)            /*!< Filter Init Mode bit 6 */
+#define  CAN_FM1R_FBM7                       ((uint16_t)0x0080)            /*!< Filter Init Mode bit 7 */
+#define  CAN_FM1R_FBM8                       ((uint16_t)0x0100)            /*!< Filter Init Mode bit 8 */
+#define  CAN_FM1R_FBM9                       ((uint16_t)0x0200)            /*!< Filter Init Mode bit 9 */
+#define  CAN_FM1R_FBM10                      ((uint16_t)0x0400)            /*!< Filter Init Mode bit 10 */
+#define  CAN_FM1R_FBM11                      ((uint16_t)0x0800)            /*!< Filter Init Mode bit 11 */
+#define  CAN_FM1R_FBM12                      ((uint16_t)0x1000)            /*!< Filter Init Mode bit 12 */
+#define  CAN_FM1R_FBM13                      ((uint16_t)0x2000)            /*!< Filter Init Mode bit 13 */
+
+/*******************  Bit definition for CAN_FS1R register  *******************/
+#define  CAN_FS1R_FSC                        ((uint16_t)0x3FFF)            /*!< Filter Scale Configuration */
+#define  CAN_FS1R_FSC0                       ((uint16_t)0x0001)            /*!< Filter Scale Configuration bit 0 */
+#define  CAN_FS1R_FSC1                       ((uint16_t)0x0002)            /*!< Filter Scale Configuration bit 1 */
+#define  CAN_FS1R_FSC2                       ((uint16_t)0x0004)            /*!< Filter Scale Configuration bit 2 */
+#define  CAN_FS1R_FSC3                       ((uint16_t)0x0008)            /*!< Filter Scale Configuration bit 3 */
+#define  CAN_FS1R_FSC4                       ((uint16_t)0x0010)            /*!< Filter Scale Configuration bit 4 */
+#define  CAN_FS1R_FSC5                       ((uint16_t)0x0020)            /*!< Filter Scale Configuration bit 5 */
+#define  CAN_FS1R_FSC6                       ((uint16_t)0x0040)            /*!< Filter Scale Configuration bit 6 */
+#define  CAN_FS1R_FSC7                       ((uint16_t)0x0080)            /*!< Filter Scale Configuration bit 7 */
+#define  CAN_FS1R_FSC8                       ((uint16_t)0x0100)            /*!< Filter Scale Configuration bit 8 */
+#define  CAN_FS1R_FSC9                       ((uint16_t)0x0200)            /*!< Filter Scale Configuration bit 9 */
+#define  CAN_FS1R_FSC10                      ((uint16_t)0x0400)            /*!< Filter Scale Configuration bit 10 */
+#define  CAN_FS1R_FSC11                      ((uint16_t)0x0800)            /*!< Filter Scale Configuration bit 11 */
+#define  CAN_FS1R_FSC12                      ((uint16_t)0x1000)            /*!< Filter Scale Configuration bit 12 */
+#define  CAN_FS1R_FSC13                      ((uint16_t)0x2000)            /*!< Filter Scale Configuration bit 13 */
+
+/******************  Bit definition for CAN_FFA1R register  *******************/
+#define  CAN_FFA1R_FFA                       ((uint16_t)0x3FFF)            /*!< Filter FIFO Assignment */
+#define  CAN_FFA1R_FFA0                      ((uint16_t)0x0001)            /*!< Filter FIFO Assignment for Filter 0 */
+#define  CAN_FFA1R_FFA1                      ((uint16_t)0x0002)            /*!< Filter FIFO Assignment for Filter 1 */
+#define  CAN_FFA1R_FFA2                      ((uint16_t)0x0004)            /*!< Filter FIFO Assignment for Filter 2 */
+#define  CAN_FFA1R_FFA3                      ((uint16_t)0x0008)            /*!< Filter FIFO Assignment for Filter 3 */
+#define  CAN_FFA1R_FFA4                      ((uint16_t)0x0010)            /*!< Filter FIFO Assignment for Filter 4 */
+#define  CAN_FFA1R_FFA5                      ((uint16_t)0x0020)            /*!< Filter FIFO Assignment for Filter 5 */
+#define  CAN_FFA1R_FFA6                      ((uint16_t)0x0040)            /*!< Filter FIFO Assignment for Filter 6 */
+#define  CAN_FFA1R_FFA7                      ((uint16_t)0x0080)            /*!< Filter FIFO Assignment for Filter 7 */
+#define  CAN_FFA1R_FFA8                      ((uint16_t)0x0100)            /*!< Filter FIFO Assignment for Filter 8 */
+#define  CAN_FFA1R_FFA9                      ((uint16_t)0x0200)            /*!< Filter FIFO Assignment for Filter 9 */
+#define  CAN_FFA1R_FFA10                     ((uint16_t)0x0400)            /*!< Filter FIFO Assignment for Filter 10 */
+#define  CAN_FFA1R_FFA11                     ((uint16_t)0x0800)            /*!< Filter FIFO Assignment for Filter 11 */
+#define  CAN_FFA1R_FFA12                     ((uint16_t)0x1000)            /*!< Filter FIFO Assignment for Filter 12 */
+#define  CAN_FFA1R_FFA13                     ((uint16_t)0x2000)            /*!< Filter FIFO Assignment for Filter 13 */
+
+/*******************  Bit definition for CAN_FA1R register  *******************/
+#define  CAN_FA1R_FACT                       ((uint16_t)0x3FFF)            /*!< Filter Active */
+#define  CAN_FA1R_FACT0                      ((uint16_t)0x0001)            /*!< Filter 0 Active */
+#define  CAN_FA1R_FACT1                      ((uint16_t)0x0002)            /*!< Filter 1 Active */
+#define  CAN_FA1R_FACT2                      ((uint16_t)0x0004)            /*!< Filter 2 Active */
+#define  CAN_FA1R_FACT3                      ((uint16_t)0x0008)            /*!< Filter 3 Active */
+#define  CAN_FA1R_FACT4                      ((uint16_t)0x0010)            /*!< Filter 4 Active */
+#define  CAN_FA1R_FACT5                      ((uint16_t)0x0020)            /*!< Filter 5 Active */
+#define  CAN_FA1R_FACT6                      ((uint16_t)0x0040)            /*!< Filter 6 Active */
+#define  CAN_FA1R_FACT7                      ((uint16_t)0x0080)            /*!< Filter 7 Active */
+#define  CAN_FA1R_FACT8                      ((uint16_t)0x0100)            /*!< Filter 8 Active */
+#define  CAN_FA1R_FACT9                      ((uint16_t)0x0200)            /*!< Filter 9 Active */
+#define  CAN_FA1R_FACT10                     ((uint16_t)0x0400)            /*!< Filter 10 Active */
+#define  CAN_FA1R_FACT11                     ((uint16_t)0x0800)            /*!< Filter 11 Active */
+#define  CAN_FA1R_FACT12                     ((uint16_t)0x1000)            /*!< Filter 12 Active */
+#define  CAN_FA1R_FACT13                     ((uint16_t)0x2000)            /*!< Filter 13 Active */
+
+/*******************  Bit definition for CAN_F0R1 register  *******************/
+#define  CAN_F0R1_FB0                        ((uint32_t)0x00000001)        /*!< Filter bit 0 */
+#define  CAN_F0R1_FB1                        ((uint32_t)0x00000002)        /*!< Filter bit 1 */
+#define  CAN_F0R1_FB2                        ((uint32_t)0x00000004)        /*!< Filter bit 2 */
+#define  CAN_F0R1_FB3                        ((uint32_t)0x00000008)        /*!< Filter bit 3 */
+#define  CAN_F0R1_FB4                        ((uint32_t)0x00000010)        /*!< Filter bit 4 */
+#define  CAN_F0R1_FB5                        ((uint32_t)0x00000020)        /*!< Filter bit 5 */
+#define  CAN_F0R1_FB6                        ((uint32_t)0x00000040)        /*!< Filter bit 6 */
+#define  CAN_F0R1_FB7                        ((uint32_t)0x00000080)        /*!< Filter bit 7 */
+#define  CAN_F0R1_FB8                        ((uint32_t)0x00000100)        /*!< Filter bit 8 */
+#define  CAN_F0R1_FB9                        ((uint32_t)0x00000200)        /*!< Filter bit 9 */
+#define  CAN_F0R1_FB10                       ((uint32_t)0x00000400)        /*!< Filter bit 10 */
+#define  CAN_F0R1_FB11                       ((uint32_t)0x00000800)        /*!< Filter bit 11 */
+#define  CAN_F0R1_FB12                       ((uint32_t)0x00001000)        /*!< Filter bit 12 */
+#define  CAN_F0R1_FB13                       ((uint32_t)0x00002000)        /*!< Filter bit 13 */
+#define  CAN_F0R1_FB14                       ((uint32_t)0x00004000)        /*!< Filter bit 14 */
+#define  CAN_F0R1_FB15                       ((uint32_t)0x00008000)        /*!< Filter bit 15 */
+#define  CAN_F0R1_FB16                       ((uint32_t)0x00010000)        /*!< Filter bit 16 */
+#define  CAN_F0R1_FB17                       ((uint32_t)0x00020000)        /*!< Filter bit 17 */
+#define  CAN_F0R1_FB18                       ((uint32_t)0x00040000)        /*!< Filter bit 18 */
+#define  CAN_F0R1_FB19                       ((uint32_t)0x00080000)        /*!< Filter bit 19 */
+#define  CAN_F0R1_FB20                       ((uint32_t)0x00100000)        /*!< Filter bit 20 */
+#define  CAN_F0R1_FB21                       ((uint32_t)0x00200000)        /*!< Filter bit 21 */
+#define  CAN_F0R1_FB22                       ((uint32_t)0x00400000)        /*!< Filter bit 22 */
+#define  CAN_F0R1_FB23                       ((uint32_t)0x00800000)        /*!< Filter bit 23 */
+#define  CAN_F0R1_FB24                       ((uint32_t)0x01000000)        /*!< Filter bit 24 */
+#define  CAN_F0R1_FB25                       ((uint32_t)0x02000000)        /*!< Filter bit 25 */
+#define  CAN_F0R1_FB26                       ((uint32_t)0x04000000)        /*!< Filter bit 26 */
+#define  CAN_F0R1_FB27                       ((uint32_t)0x08000000)        /*!< Filter bit 27 */
+#define  CAN_F0R1_FB28                       ((uint32_t)0x10000000)        /*!< Filter bit 28 */
+#define  CAN_F0R1_FB29                       ((uint32_t)0x20000000)        /*!< Filter bit 29 */
+#define  CAN_F0R1_FB30                       ((uint32_t)0x40000000)        /*!< Filter bit 30 */
+#define  CAN_F0R1_FB31                       ((uint32_t)0x80000000)        /*!< Filter bit 31 */
+
+/*******************  Bit definition for CAN_F1R1 register  *******************/
+#define  CAN_F1R1_FB0                        ((uint32_t)0x00000001)        /*!< Filter bit 0 */
+#define  CAN_F1R1_FB1                        ((uint32_t)0x00000002)        /*!< Filter bit 1 */
+#define  CAN_F1R1_FB2                        ((uint32_t)0x00000004)        /*!< Filter bit 2 */
+#define  CAN_F1R1_FB3                        ((uint32_t)0x00000008)        /*!< Filter bit 3 */
+#define  CAN_F1R1_FB4                        ((uint32_t)0x00000010)        /*!< Filter bit 4 */
+#define  CAN_F1R1_FB5                        ((uint32_t)0x00000020)        /*!< Filter bit 5 */
+#define  CAN_F1R1_FB6                        ((uint32_t)0x00000040)        /*!< Filter bit 6 */
+#define  CAN_F1R1_FB7                        ((uint32_t)0x00000080)        /*!< Filter bit 7 */
+#define  CAN_F1R1_FB8                        ((uint32_t)0x00000100)        /*!< Filter bit 8 */
+#define  CAN_F1R1_FB9                        ((uint32_t)0x00000200)        /*!< Filter bit 9 */
+#define  CAN_F1R1_FB10                       ((uint32_t)0x00000400)        /*!< Filter bit 10 */
+#define  CAN_F1R1_FB11                       ((uint32_t)0x00000800)        /*!< Filter bit 11 */
+#define  CAN_F1R1_FB12                       ((uint32_t)0x00001000)        /*!< Filter bit 12 */
+#define  CAN_F1R1_FB13                       ((uint32_t)0x00002000)        /*!< Filter bit 13 */
+#define  CAN_F1R1_FB14                       ((uint32_t)0x00004000)        /*!< Filter bit 14 */
+#define  CAN_F1R1_FB15                       ((uint32_t)0x00008000)        /*!< Filter bit 15 */
+#define  CAN_F1R1_FB16                       ((uint32_t)0x00010000)        /*!< Filter bit 16 */
+#define  CAN_F1R1_FB17                       ((uint32_t)0x00020000)        /*!< Filter bit 17 */
+#define  CAN_F1R1_FB18                       ((uint32_t)0x00040000)        /*!< Filter bit 18 */
+#define  CAN_F1R1_FB19                       ((uint32_t)0x00080000)        /*!< Filter bit 19 */
+#define  CAN_F1R1_FB20                       ((uint32_t)0x00100000)        /*!< Filter bit 20 */
+#define  CAN_F1R1_FB21                       ((uint32_t)0x00200000)        /*!< Filter bit 21 */
+#define  CAN_F1R1_FB22                       ((uint32_t)0x00400000)        /*!< Filter bit 22 */
+#define  CAN_F1R1_FB23                       ((uint32_t)0x00800000)        /*!< Filter bit 23 */
+#define  CAN_F1R1_FB24                       ((uint32_t)0x01000000)        /*!< Filter bit 24 */
+#define  CAN_F1R1_FB25                       ((uint32_t)0x02000000)        /*!< Filter bit 25 */
+#define  CAN_F1R1_FB26                       ((uint32_t)0x04000000)        /*!< Filter bit 26 */
+#define  CAN_F1R1_FB27                       ((uint32_t)0x08000000)        /*!< Filter bit 27 */
+#define  CAN_F1R1_FB28                       ((uint32_t)0x10000000)        /*!< Filter bit 28 */
+#define  CAN_F1R1_FB29                       ((uint32_t)0x20000000)        /*!< Filter bit 29 */
+#define  CAN_F1R1_FB30                       ((uint32_t)0x40000000)        /*!< Filter bit 30 */
+#define  CAN_F1R1_FB31                       ((uint32_t)0x80000000)        /*!< Filter bit 31 */
+
+/*******************  Bit definition for CAN_F2R1 register  *******************/
+#define  CAN_F2R1_FB0                        ((uint32_t)0x00000001)        /*!< Filter bit 0 */
+#define  CAN_F2R1_FB1                        ((uint32_t)0x00000002)        /*!< Filter bit 1 */
+#define  CAN_F2R1_FB2                        ((uint32_t)0x00000004)        /*!< Filter bit 2 */
+#define  CAN_F2R1_FB3                        ((uint32_t)0x00000008)        /*!< Filter bit 3 */
+#define  CAN_F2R1_FB4                        ((uint32_t)0x00000010)        /*!< Filter bit 4 */
+#define  CAN_F2R1_FB5                        ((uint32_t)0x00000020)        /*!< Filter bit 5 */
+#define  CAN_F2R1_FB6                        ((uint32_t)0x00000040)        /*!< Filter bit 6 */
+#define  CAN_F2R1_FB7                        ((uint32_t)0x00000080)        /*!< Filter bit 7 */
+#define  CAN_F2R1_FB8                        ((uint32_t)0x00000100)        /*!< Filter bit 8 */
+#define  CAN_F2R1_FB9                        ((uint32_t)0x00000200)        /*!< Filter bit 9 */
+#define  CAN_F2R1_FB10                       ((uint32_t)0x00000400)        /*!< Filter bit 10 */
+#define  CAN_F2R1_FB11                       ((uint32_t)0x00000800)        /*!< Filter bit 11 */
+#define  CAN_F2R1_FB12                       ((uint32_t)0x00001000)        /*!< Filter bit 12 */
+#define  CAN_F2R1_FB13                       ((uint32_t)0x00002000)        /*!< Filter bit 13 */
+#define  CAN_F2R1_FB14                       ((uint32_t)0x00004000)        /*!< Filter bit 14 */
+#define  CAN_F2R1_FB15                       ((uint32_t)0x00008000)        /*!< Filter bit 15 */
+#define  CAN_F2R1_FB16                       ((uint32_t)0x00010000)        /*!< Filter bit 16 */
+#define  CAN_F2R1_FB17                       ((uint32_t)0x00020000)        /*!< Filter bit 17 */
+#define  CAN_F2R1_FB18                       ((uint32_t)0x00040000)        /*!< Filter bit 18 */
+#define  CAN_F2R1_FB19                       ((uint32_t)0x00080000)        /*!< Filter bit 19 */
+#define  CAN_F2R1_FB20                       ((uint32_t)0x00100000)        /*!< Filter bit 20 */
+#define  CAN_F2R1_FB21                       ((uint32_t)0x00200000)        /*!< Filter bit 21 */
+#define  CAN_F2R1_FB22                       ((uint32_t)0x00400000)        /*!< Filter bit 22 */
+#define  CAN_F2R1_FB23                       ((uint32_t)0x00800000)        /*!< Filter bit 23 */
+#define  CAN_F2R1_FB24                       ((uint32_t)0x01000000)        /*!< Filter bit 24 */
+#define  CAN_F2R1_FB25                       ((uint32_t)0x02000000)        /*!< Filter bit 25 */
+#define  CAN_F2R1_FB26                       ((uint32_t)0x04000000)        /*!< Filter bit 26 */
+#define  CAN_F2R1_FB27                       ((uint32_t)0x08000000)        /*!< Filter bit 27 */
+#define  CAN_F2R1_FB28                       ((uint32_t)0x10000000)        /*!< Filter bit 28 */
+#define  CAN_F2R1_FB29                       ((uint32_t)0x20000000)        /*!< Filter bit 29 */
+#define  CAN_F2R1_FB30                       ((uint32_t)0x40000000)        /*!< Filter bit 30 */
+#define  CAN_F2R1_FB31                       ((uint32_t)0x80000000)        /*!< Filter bit 31 */
+
+/*******************  Bit definition for CAN_F3R1 register  *******************/
+#define  CAN_F3R1_FB0                        ((uint32_t)0x00000001)        /*!< Filter bit 0 */
+#define  CAN_F3R1_FB1                        ((uint32_t)0x00000002)        /*!< Filter bit 1 */
+#define  CAN_F3R1_FB2                        ((uint32_t)0x00000004)        /*!< Filter bit 2 */
+#define  CAN_F3R1_FB3                        ((uint32_t)0x00000008)        /*!< Filter bit 3 */
+#define  CAN_F3R1_FB4                        ((uint32_t)0x00000010)        /*!< Filter bit 4 */
+#define  CAN_F3R1_FB5                        ((uint32_t)0x00000020)        /*!< Filter bit 5 */
+#define  CAN_F3R1_FB6                        ((uint32_t)0x00000040)        /*!< Filter bit 6 */
+#define  CAN_F3R1_FB7                        ((uint32_t)0x00000080)        /*!< Filter bit 7 */
+#define  CAN_F3R1_FB8                        ((uint32_t)0x00000100)        /*!< Filter bit 8 */
+#define  CAN_F3R1_FB9                        ((uint32_t)0x00000200)        /*!< Filter bit 9 */
+#define  CAN_F3R1_FB10                       ((uint32_t)0x00000400)        /*!< Filter bit 10 */
+#define  CAN_F3R1_FB11                       ((uint32_t)0x00000800)        /*!< Filter bit 11 */
+#define  CAN_F3R1_FB12                       ((uint32_t)0x00001000)        /*!< Filter bit 12 */
+#define  CAN_F3R1_FB13                       ((uint32_t)0x00002000)        /*!< Filter bit 13 */
+#define  CAN_F3R1_FB14                       ((uint32_t)0x00004000)        /*!< Filter bit 14 */
+#define  CAN_F3R1_FB15                       ((uint32_t)0x00008000)        /*!< Filter bit 15 */
+#define  CAN_F3R1_FB16                       ((uint32_t)0x00010000)        /*!< Filter bit 16 */
+#define  CAN_F3R1_FB17                       ((uint32_t)0x00020000)        /*!< Filter bit 17 */
+#define  CAN_F3R1_FB18                       ((uint32_t)0x00040000)        /*!< Filter bit 18 */
+#define  CAN_F3R1_FB19                       ((uint32_t)0x00080000)        /*!< Filter bit 19 */
+#define  CAN_F3R1_FB20                       ((uint32_t)0x00100000)        /*!< Filter bit 20 */
+#define  CAN_F3R1_FB21                       ((uint32_t)0x00200000)        /*!< Filter bit 21 */
+#define  CAN_F3R1_FB22                       ((uint32_t)0x00400000)        /*!< Filter bit 22 */
+#define  CAN_F3R1_FB23                       ((uint32_t)0x00800000)        /*!< Filter bit 23 */
+#define  CAN_F3R1_FB24                       ((uint32_t)0x01000000)        /*!< Filter bit 24 */
+#define  CAN_F3R1_FB25                       ((uint32_t)0x02000000)        /*!< Filter bit 25 */
+#define  CAN_F3R1_FB26                       ((uint32_t)0x04000000)        /*!< Filter bit 26 */
+#define  CAN_F3R1_FB27                       ((uint32_t)0x08000000)        /*!< Filter bit 27 */
+#define  CAN_F3R1_FB28                       ((uint32_t)0x10000000)        /*!< Filter bit 28 */
+#define  CAN_F3R1_FB29                       ((uint32_t)0x20000000)        /*!< Filter bit 29 */
+#define  CAN_F3R1_FB30                       ((uint32_t)0x40000000)        /*!< Filter bit 30 */
+#define  CAN_F3R1_FB31                       ((uint32_t)0x80000000)        /*!< Filter bit 31 */
+
+/*******************  Bit definition for CAN_F4R1 register  *******************/
+#define  CAN_F4R1_FB0                        ((uint32_t)0x00000001)        /*!< Filter bit 0 */
+#define  CAN_F4R1_FB1                        ((uint32_t)0x00000002)        /*!< Filter bit 1 */
+#define  CAN_F4R1_FB2                        ((uint32_t)0x00000004)        /*!< Filter bit 2 */
+#define  CAN_F4R1_FB3                        ((uint32_t)0x00000008)        /*!< Filter bit 3 */
+#define  CAN_F4R1_FB4                        ((uint32_t)0x00000010)        /*!< Filter bit 4 */
+#define  CAN_F4R1_FB5                        ((uint32_t)0x00000020)        /*!< Filter bit 5 */
+#define  CAN_F4R1_FB6                        ((uint32_t)0x00000040)        /*!< Filter bit 6 */
+#define  CAN_F4R1_FB7                        ((uint32_t)0x00000080)        /*!< Filter bit 7 */
+#define  CAN_F4R1_FB8                        ((uint32_t)0x00000100)        /*!< Filter bit 8 */
+#define  CAN_F4R1_FB9                        ((uint32_t)0x00000200)        /*!< Filter bit 9 */
+#define  CAN_F4R1_FB10                       ((uint32_t)0x00000400)        /*!< Filter bit 10 */
+#define  CAN_F4R1_FB11                       ((uint32_t)0x00000800)        /*!< Filter bit 11 */
+#define  CAN_F4R1_FB12                       ((uint32_t)0x00001000)        /*!< Filter bit 12 */
+#define  CAN_F4R1_FB13                       ((uint32_t)0x00002000)        /*!< Filter bit 13 */
+#define  CAN_F4R1_FB14                       ((uint32_t)0x00004000)        /*!< Filter bit 14 */
+#define  CAN_F4R1_FB15                       ((uint32_t)0x00008000)        /*!< Filter bit 15 */
+#define  CAN_F4R1_FB16                       ((uint32_t)0x00010000)        /*!< Filter bit 16 */
+#define  CAN_F4R1_FB17                       ((uint32_t)0x00020000)        /*!< Filter bit 17 */
+#define  CAN_F4R1_FB18                       ((uint32_t)0x00040000)        /*!< Filter bit 18 */
+#define  CAN_F4R1_FB19                       ((uint32_t)0x00080000)        /*!< Filter bit 19 */
+#define  CAN_F4R1_FB20                       ((uint32_t)0x00100000)        /*!< Filter bit 20 */
+#define  CAN_F4R1_FB21                       ((uint32_t)0x00200000)        /*!< Filter bit 21 */
+#define  CAN_F4R1_FB22                       ((uint32_t)0x00400000)        /*!< Filter bit 22 */
+#define  CAN_F4R1_FB23                       ((uint32_t)0x00800000)        /*!< Filter bit 23 */
+#define  CAN_F4R1_FB24                       ((uint32_t)0x01000000)        /*!< Filter bit 24 */
+#define  CAN_F4R1_FB25                       ((uint32_t)0x02000000)        /*!< Filter bit 25 */
+#define  CAN_F4R1_FB26                       ((uint32_t)0x04000000)        /*!< Filter bit 26 */
+#define  CAN_F4R1_FB27                       ((uint32_t)0x08000000)        /*!< Filter bit 27 */
+#define  CAN_F4R1_FB28                       ((uint32_t)0x10000000)        /*!< Filter bit 28 */
+#define  CAN_F4R1_FB29                       ((uint32_t)0x20000000)        /*!< Filter bit 29 */
+#define  CAN_F4R1_FB30                       ((uint32_t)0x40000000)        /*!< Filter bit 30 */
+#define  CAN_F4R1_FB31                       ((uint32_t)0x80000000)        /*!< Filter bit 31 */
+
+/*******************  Bit definition for CAN_F5R1 register  *******************/
+#define  CAN_F5R1_FB0                        ((uint32_t)0x00000001)        /*!< Filter bit 0 */
+#define  CAN_F5R1_FB1                        ((uint32_t)0x00000002)        /*!< Filter bit 1 */
+#define  CAN_F5R1_FB2                        ((uint32_t)0x00000004)        /*!< Filter bit 2 */
+#define  CAN_F5R1_FB3                        ((uint32_t)0x00000008)        /*!< Filter bit 3 */
+#define  CAN_F5R1_FB4                        ((uint32_t)0x00000010)        /*!< Filter bit 4 */
+#define  CAN_F5R1_FB5                        ((uint32_t)0x00000020)        /*!< Filter bit 5 */
+#define  CAN_F5R1_FB6                        ((uint32_t)0x00000040)        /*!< Filter bit 6 */
+#define  CAN_F5R1_FB7                        ((uint32_t)0x00000080)        /*!< Filter bit 7 */
+#define  CAN_F5R1_FB8                        ((uint32_t)0x00000100)        /*!< Filter bit 8 */
+#define  CAN_F5R1_FB9                        ((uint32_t)0x00000200)        /*!< Filter bit 9 */
+#define  CAN_F5R1_FB10                       ((uint32_t)0x00000400)        /*!< Filter bit 10 */
+#define  CAN_F5R1_FB11                       ((uint32_t)0x00000800)        /*!< Filter bit 11 */
+#define  CAN_F5R1_FB12                       ((uint32_t)0x00001000)        /*!< Filter bit 12 */
+#define  CAN_F5R1_FB13                       ((uint32_t)0x00002000)        /*!< Filter bit 13 */
+#define  CAN_F5R1_FB14                       ((uint32_t)0x00004000)        /*!< Filter bit 14 */
+#define  CAN_F5R1_FB15                       ((uint32_t)0x00008000)        /*!< Filter bit 15 */
+#define  CAN_F5R1_FB16                       ((uint32_t)0x00010000)        /*!< Filter bit 16 */
+#define  CAN_F5R1_FB17                       ((uint32_t)0x00020000)        /*!< Filter bit 17 */
+#define  CAN_F5R1_FB18                       ((uint32_t)0x00040000)        /*!< Filter bit 18 */
+#define  CAN_F5R1_FB19                       ((uint32_t)0x00080000)        /*!< Filter bit 19 */
+#define  CAN_F5R1_FB20                       ((uint32_t)0x00100000)        /*!< Filter bit 20 */
+#define  CAN_F5R1_FB21                       ((uint32_t)0x00200000)        /*!< Filter bit 21 */
+#define  CAN_F5R1_FB22                       ((uint32_t)0x00400000)        /*!< Filter bit 22 */
+#define  CAN_F5R1_FB23                       ((uint32_t)0x00800000)        /*!< Filter bit 23 */
+#define  CAN_F5R1_FB24                       ((uint32_t)0x01000000)        /*!< Filter bit 24 */
+#define  CAN_F5R1_FB25                       ((uint32_t)0x02000000)        /*!< Filter bit 25 */
+#define  CAN_F5R1_FB26                       ((uint32_t)0x04000000)        /*!< Filter bit 26 */
+#define  CAN_F5R1_FB27                       ((uint32_t)0x08000000)        /*!< Filter bit 27 */
+#define  CAN_F5R1_FB28                       ((uint32_t)0x10000000)        /*!< Filter bit 28 */
+#define  CAN_F5R1_FB29                       ((uint32_t)0x20000000)        /*!< Filter bit 29 */
+#define  CAN_F5R1_FB30                       ((uint32_t)0x40000000)        /*!< Filter bit 30 */
+#define  CAN_F5R1_FB31                       ((uint32_t)0x80000000)        /*!< Filter bit 31 */
+
+/*******************  Bit definition for CAN_F6R1 register  *******************/
+#define  CAN_F6R1_FB0                        ((uint32_t)0x00000001)        /*!< Filter bit 0 */
+#define  CAN_F6R1_FB1                        ((uint32_t)0x00000002)        /*!< Filter bit 1 */
+#define  CAN_F6R1_FB2                        ((uint32_t)0x00000004)        /*!< Filter bit 2 */
+#define  CAN_F6R1_FB3                        ((uint32_t)0x00000008)        /*!< Filter bit 3 */
+#define  CAN_F6R1_FB4                        ((uint32_t)0x00000010)        /*!< Filter bit 4 */
+#define  CAN_F6R1_FB5                        ((uint32_t)0x00000020)        /*!< Filter bit 5 */
+#define  CAN_F6R1_FB6                        ((uint32_t)0x00000040)        /*!< Filter bit 6 */
+#define  CAN_F6R1_FB7                        ((uint32_t)0x00000080)        /*!< Filter bit 7 */
+#define  CAN_F6R1_FB8                        ((uint32_t)0x00000100)        /*!< Filter bit 8 */
+#define  CAN_F6R1_FB9                        ((uint32_t)0x00000200)        /*!< Filter bit 9 */
+#define  CAN_F6R1_FB10                       ((uint32_t)0x00000400)        /*!< Filter bit 10 */
+#define  CAN_F6R1_FB11                       ((uint32_t)0x00000800)        /*!< Filter bit 11 */
+#define  CAN_F6R1_FB12                       ((uint32_t)0x00001000)        /*!< Filter bit 12 */
+#define  CAN_F6R1_FB13                       ((uint32_t)0x00002000)        /*!< Filter bit 13 */
+#define  CAN_F6R1_FB14                       ((uint32_t)0x00004000)        /*!< Filter bit 14 */
+#define  CAN_F6R1_FB15                       ((uint32_t)0x00008000)        /*!< Filter bit 15 */
+#define  CAN_F6R1_FB16                       ((uint32_t)0x00010000)        /*!< Filter bit 16 */
+#define  CAN_F6R1_FB17                       ((uint32_t)0x00020000)        /*!< Filter bit 17 */
+#define  CAN_F6R1_FB18                       ((uint32_t)0x00040000)        /*!< Filter bit 18 */
+#define  CAN_F6R1_FB19                       ((uint32_t)0x00080000)        /*!< Filter bit 19 */
+#define  CAN_F6R1_FB20                       ((uint32_t)0x00100000)        /*!< Filter bit 20 */
+#define  CAN_F6R1_FB21                       ((uint32_t)0x00200000)        /*!< Filter bit 21 */
+#define  CAN_F6R1_FB22                       ((uint32_t)0x00400000)        /*!< Filter bit 22 */
+#define  CAN_F6R1_FB23                       ((uint32_t)0x00800000)        /*!< Filter bit 23 */
+#define  CAN_F6R1_FB24                       ((uint32_t)0x01000000)        /*!< Filter bit 24 */
+#define  CAN_F6R1_FB25                       ((uint32_t)0x02000000)        /*!< Filter bit 25 */
+#define  CAN_F6R1_FB26                       ((uint32_t)0x04000000)        /*!< Filter bit 26 */
+#define  CAN_F6R1_FB27                       ((uint32_t)0x08000000)        /*!< Filter bit 27 */
+#define  CAN_F6R1_FB28                       ((uint32_t)0x10000000)        /*!< Filter bit 28 */
+#define  CAN_F6R1_FB29                       ((uint32_t)0x20000000)        /*!< Filter bit 29 */
+#define  CAN_F6R1_FB30                       ((uint32_t)0x40000000)        /*!< Filter bit 30 */
+#define  CAN_F6R1_FB31                       ((uint32_t)0x80000000)        /*!< Filter bit 31 */
+
+/*******************  Bit definition for CAN_F7R1 register  *******************/
+#define  CAN_F7R1_FB0                        ((uint32_t)0x00000001)        /*!< Filter bit 0 */
+#define  CAN_F7R1_FB1                        ((uint32_t)0x00000002)        /*!< Filter bit 1 */
+#define  CAN_F7R1_FB2                        ((uint32_t)0x00000004)        /*!< Filter bit 2 */
+#define  CAN_F7R1_FB3                        ((uint32_t)0x00000008)        /*!< Filter bit 3 */
+#define  CAN_F7R1_FB4                        ((uint32_t)0x00000010)        /*!< Filter bit 4 */
+#define  CAN_F7R1_FB5                        ((uint32_t)0x00000020)        /*!< Filter bit 5 */
+#define  CAN_F7R1_FB6                        ((uint32_t)0x00000040)        /*!< Filter bit 6 */
+#define  CAN_F7R1_FB7                        ((uint32_t)0x00000080)        /*!< Filter bit 7 */
+#define  CAN_F7R1_FB8                        ((uint32_t)0x00000100)        /*!< Filter bit 8 */
+#define  CAN_F7R1_FB9                        ((uint32_t)0x00000200)        /*!< Filter bit 9 */
+#define  CAN_F7R1_FB10                       ((uint32_t)0x00000400)        /*!< Filter bit 10 */
+#define  CAN_F7R1_FB11                       ((uint32_t)0x00000800)        /*!< Filter bit 11 */
+#define  CAN_F7R1_FB12                       ((uint32_t)0x00001000)        /*!< Filter bit 12 */
+#define  CAN_F7R1_FB13                       ((uint32_t)0x00002000)        /*!< Filter bit 13 */
+#define  CAN_F7R1_FB14                       ((uint32_t)0x00004000)        /*!< Filter bit 14 */
+#define  CAN_F7R1_FB15                       ((uint32_t)0x00008000)        /*!< Filter bit 15 */
+#define  CAN_F7R1_FB16                       ((uint32_t)0x00010000)        /*!< Filter bit 16 */
+#define  CAN_F7R1_FB17                       ((uint32_t)0x00020000)        /*!< Filter bit 17 */
+#define  CAN_F7R1_FB18                       ((uint32_t)0x00040000)        /*!< Filter bit 18 */
+#define  CAN_F7R1_FB19                       ((uint32_t)0x00080000)        /*!< Filter bit 19 */
+#define  CAN_F7R1_FB20                       ((uint32_t)0x00100000)        /*!< Filter bit 20 */
+#define  CAN_F7R1_FB21                       ((uint32_t)0x00200000)        /*!< Filter bit 21 */
+#define  CAN_F7R1_FB22                       ((uint32_t)0x00400000)        /*!< Filter bit 22 */
+#define  CAN_F7R1_FB23                       ((uint32_t)0x00800000)        /*!< Filter bit 23 */
+#define  CAN_F7R1_FB24                       ((uint32_t)0x01000000)        /*!< Filter bit 24 */
+#define  CAN_F7R1_FB25                       ((uint32_t)0x02000000)        /*!< Filter bit 25 */
+#define  CAN_F7R1_FB26                       ((uint32_t)0x04000000)        /*!< Filter bit 26 */
+#define  CAN_F7R1_FB27                       ((uint32_t)0x08000000)        /*!< Filter bit 27 */
+#define  CAN_F7R1_FB28                       ((uint32_t)0x10000000)        /*!< Filter bit 28 */
+#define  CAN_F7R1_FB29                       ((uint32_t)0x20000000)        /*!< Filter bit 29 */
+#define  CAN_F7R1_FB30                       ((uint32_t)0x40000000)        /*!< Filter bit 30 */
+#define  CAN_F7R1_FB31                       ((uint32_t)0x80000000)        /*!< Filter bit 31 */
+
+/*******************  Bit definition for CAN_F8R1 register  *******************/
+#define  CAN_F8R1_FB0                        ((uint32_t)0x00000001)        /*!< Filter bit 0 */
+#define  CAN_F8R1_FB1                        ((uint32_t)0x00000002)        /*!< Filter bit 1 */
+#define  CAN_F8R1_FB2                        ((uint32_t)0x00000004)        /*!< Filter bit 2 */
+#define  CAN_F8R1_FB3                        ((uint32_t)0x00000008)        /*!< Filter bit 3 */
+#define  CAN_F8R1_FB4                        ((uint32_t)0x00000010)        /*!< Filter bit 4 */
+#define  CAN_F8R1_FB5                        ((uint32_t)0x00000020)        /*!< Filter bit 5 */
+#define  CAN_F8R1_FB6                        ((uint32_t)0x00000040)        /*!< Filter bit 6 */
+#define  CAN_F8R1_FB7                        ((uint32_t)0x00000080)        /*!< Filter bit 7 */
+#define  CAN_F8R1_FB8                        ((uint32_t)0x00000100)        /*!< Filter bit 8 */
+#define  CAN_F8R1_FB9                        ((uint32_t)0x00000200)        /*!< Filter bit 9 */
+#define  CAN_F8R1_FB10                       ((uint32_t)0x00000400)        /*!< Filter bit 10 */
+#define  CAN_F8R1_FB11                       ((uint32_t)0x00000800)        /*!< Filter bit 11 */
+#define  CAN_F8R1_FB12                       ((uint32_t)0x00001000)        /*!< Filter bit 12 */
+#define  CAN_F8R1_FB13                       ((uint32_t)0x00002000)        /*!< Filter bit 13 */
+#define  CAN_F8R1_FB14                       ((uint32_t)0x00004000)        /*!< Filter bit 14 */
+#define  CAN_F8R1_FB15                       ((uint32_t)0x00008000)        /*!< Filter bit 15 */
+#define  CAN_F8R1_FB16                       ((uint32_t)0x00010000)        /*!< Filter bit 16 */
+#define  CAN_F8R1_FB17                       ((uint32_t)0x00020000)        /*!< Filter bit 17 */
+#define  CAN_F8R1_FB18                       ((uint32_t)0x00040000)        /*!< Filter bit 18 */
+#define  CAN_F8R1_FB19                       ((uint32_t)0x00080000)        /*!< Filter bit 19 */
+#define  CAN_F8R1_FB20                       ((uint32_t)0x00100000)        /*!< Filter bit 20 */
+#define  CAN_F8R1_FB21                       ((uint32_t)0x00200000)        /*!< Filter bit 21 */
+#define  CAN_F8R1_FB22                       ((uint32_t)0x00400000)        /*!< Filter bit 22 */
+#define  CAN_F8R1_FB23                       ((uint32_t)0x00800000)        /*!< Filter bit 23 */
+#define  CAN_F8R1_FB24                       ((uint32_t)0x01000000)        /*!< Filter bit 24 */
+#define  CAN_F8R1_FB25                       ((uint32_t)0x02000000)        /*!< Filter bit 25 */
+#define  CAN_F8R1_FB26                       ((uint32_t)0x04000000)        /*!< Filter bit 26 */
+#define  CAN_F8R1_FB27                       ((uint32_t)0x08000000)        /*!< Filter bit 27 */
+#define  CAN_F8R1_FB28                       ((uint32_t)0x10000000)        /*!< Filter bit 28 */
+#define  CAN_F8R1_FB29                       ((uint32_t)0x20000000)        /*!< Filter bit 29 */
+#define  CAN_F8R1_FB30                       ((uint32_t)0x40000000)        /*!< Filter bit 30 */
+#define  CAN_F8R1_FB31                       ((uint32_t)0x80000000)        /*!< Filter bit 31 */
+
+/*******************  Bit definition for CAN_F9R1 register  *******************/
+#define  CAN_F9R1_FB0                        ((uint32_t)0x00000001)        /*!< Filter bit 0 */
+#define  CAN_F9R1_FB1                        ((uint32_t)0x00000002)        /*!< Filter bit 1 */
+#define  CAN_F9R1_FB2                        ((uint32_t)0x00000004)        /*!< Filter bit 2 */
+#define  CAN_F9R1_FB3                        ((uint32_t)0x00000008)        /*!< Filter bit 3 */
+#define  CAN_F9R1_FB4                        ((uint32_t)0x00000010)        /*!< Filter bit 4 */
+#define  CAN_F9R1_FB5                        ((uint32_t)0x00000020)        /*!< Filter bit 5 */
+#define  CAN_F9R1_FB6                        ((uint32_t)0x00000040)        /*!< Filter bit 6 */
+#define  CAN_F9R1_FB7                        ((uint32_t)0x00000080)        /*!< Filter bit 7 */
+#define  CAN_F9R1_FB8                        ((uint32_t)0x00000100)        /*!< Filter bit 8 */
+#define  CAN_F9R1_FB9                        ((uint32_t)0x00000200)        /*!< Filter bit 9 */
+#define  CAN_F9R1_FB10                       ((uint32_t)0x00000400)        /*!< Filter bit 10 */
+#define  CAN_F9R1_FB11                       ((uint32_t)0x00000800)        /*!< Filter bit 11 */
+#define  CAN_F9R1_FB12                       ((uint32_t)0x00001000)        /*!< Filter bit 12 */
+#define  CAN_F9R1_FB13                       ((uint32_t)0x00002000)        /*!< Filter bit 13 */
+#define  CAN_F9R1_FB14                       ((uint32_t)0x00004000)        /*!< Filter bit 14 */
+#define  CAN_F9R1_FB15                       ((uint32_t)0x00008000)        /*!< Filter bit 15 */
+#define  CAN_F9R1_FB16                       ((uint32_t)0x00010000)        /*!< Filter bit 16 */
+#define  CAN_F9R1_FB17                       ((uint32_t)0x00020000)        /*!< Filter bit 17 */
+#define  CAN_F9R1_FB18                       ((uint32_t)0x00040000)        /*!< Filter bit 18 */
+#define  CAN_F9R1_FB19                       ((uint32_t)0x00080000)        /*!< Filter bit 19 */
+#define  CAN_F9R1_FB20                       ((uint32_t)0x00100000)        /*!< Filter bit 20 */
+#define  CAN_F9R1_FB21                       ((uint32_t)0x00200000)        /*!< Filter bit 21 */
+#define  CAN_F9R1_FB22                       ((uint32_t)0x00400000)        /*!< Filter bit 22 */
+#define  CAN_F9R1_FB23                       ((uint32_t)0x00800000)        /*!< Filter bit 23 */
+#define  CAN_F9R1_FB24                       ((uint32_t)0x01000000)        /*!< Filter bit 24 */
+#define  CAN_F9R1_FB25                       ((uint32_t)0x02000000)        /*!< Filter bit 25 */
+#define  CAN_F9R1_FB26                       ((uint32_t)0x04000000)        /*!< Filter bit 26 */
+#define  CAN_F9R1_FB27                       ((uint32_t)0x08000000)        /*!< Filter bit 27 */
+#define  CAN_F9R1_FB28                       ((uint32_t)0x10000000)        /*!< Filter bit 28 */
+#define  CAN_F9R1_FB29                       ((uint32_t)0x20000000)        /*!< Filter bit 29 */
+#define  CAN_F9R1_FB30                       ((uint32_t)0x40000000)        /*!< Filter bit 30 */
+#define  CAN_F9R1_FB31                       ((uint32_t)0x80000000)        /*!< Filter bit 31 */
+
+/*******************  Bit definition for CAN_F10R1 register  ******************/
+#define  CAN_F10R1_FB0                       ((uint32_t)0x00000001)        /*!< Filter bit 0 */
+#define  CAN_F10R1_FB1                       ((uint32_t)0x00000002)        /*!< Filter bit 1 */
+#define  CAN_F10R1_FB2                       ((uint32_t)0x00000004)        /*!< Filter bit 2 */
+#define  CAN_F10R1_FB3                       ((uint32_t)0x00000008)        /*!< Filter bit 3 */
+#define  CAN_F10R1_FB4                       ((uint32_t)0x00000010)        /*!< Filter bit 4 */
+#define  CAN_F10R1_FB5                       ((uint32_t)0x00000020)        /*!< Filter bit 5 */
+#define  CAN_F10R1_FB6                       ((uint32_t)0x00000040)        /*!< Filter bit 6 */
+#define  CAN_F10R1_FB7                       ((uint32_t)0x00000080)        /*!< Filter bit 7 */
+#define  CAN_F10R1_FB8                       ((uint32_t)0x00000100)        /*!< Filter bit 8 */
+#define  CAN_F10R1_FB9                       ((uint32_t)0x00000200)        /*!< Filter bit 9 */
+#define  CAN_F10R1_FB10                      ((uint32_t)0x00000400)        /*!< Filter bit 10 */
+#define  CAN_F10R1_FB11                      ((uint32_t)0x00000800)        /*!< Filter bit 11 */
+#define  CAN_F10R1_FB12                      ((uint32_t)0x00001000)        /*!< Filter bit 12 */
+#define  CAN_F10R1_FB13                      ((uint32_t)0x00002000)        /*!< Filter bit 13 */
+#define  CAN_F10R1_FB14                      ((uint32_t)0x00004000)        /*!< Filter bit 14 */
+#define  CAN_F10R1_FB15                      ((uint32_t)0x00008000)        /*!< Filter bit 15 */
+#define  CAN_F10R1_FB16                      ((uint32_t)0x00010000)        /*!< Filter bit 16 */
+#define  CAN_F10R1_FB17                      ((uint32_t)0x00020000)        /*!< Filter bit 17 */
+#define  CAN_F10R1_FB18                      ((uint32_t)0x00040000)        /*!< Filter bit 18 */
+#define  CAN_F10R1_FB19                      ((uint32_t)0x00080000)        /*!< Filter bit 19 */
+#define  CAN_F10R1_FB20                      ((uint32_t)0x00100000)        /*!< Filter bit 20 */
+#define  CAN_F10R1_FB21                      ((uint32_t)0x00200000)        /*!< Filter bit 21 */
+#define  CAN_F10R1_FB22                      ((uint32_t)0x00400000)        /*!< Filter bit 22 */
+#define  CAN_F10R1_FB23                      ((uint32_t)0x00800000)        /*!< Filter bit 23 */
+#define  CAN_F10R1_FB24                      ((uint32_t)0x01000000)        /*!< Filter bit 24 */
+#define  CAN_F10R1_FB25                      ((uint32_t)0x02000000)        /*!< Filter bit 25 */
+#define  CAN_F10R1_FB26                      ((uint32_t)0x04000000)        /*!< Filter bit 26 */
+#define  CAN_F10R1_FB27                      ((uint32_t)0x08000000)        /*!< Filter bit 27 */
+#define  CAN_F10R1_FB28                      ((uint32_t)0x10000000)        /*!< Filter bit 28 */
+#define  CAN_F10R1_FB29                      ((uint32_t)0x20000000)        /*!< Filter bit 29 */
+#define  CAN_F10R1_FB30                      ((uint32_t)0x40000000)        /*!< Filter bit 30 */
+#define  CAN_F10R1_FB31                      ((uint32_t)0x80000000)        /*!< Filter bit 31 */
+
+/*******************  Bit definition for CAN_F11R1 register  ******************/
+#define  CAN_F11R1_FB0                       ((uint32_t)0x00000001)        /*!< Filter bit 0 */
+#define  CAN_F11R1_FB1                       ((uint32_t)0x00000002)        /*!< Filter bit 1 */
+#define  CAN_F11R1_FB2                       ((uint32_t)0x00000004)        /*!< Filter bit 2 */
+#define  CAN_F11R1_FB3                       ((uint32_t)0x00000008)        /*!< Filter bit 3 */
+#define  CAN_F11R1_FB4                       ((uint32_t)0x00000010)        /*!< Filter bit 4 */
+#define  CAN_F11R1_FB5                       ((uint32_t)0x00000020)        /*!< Filter bit 5 */
+#define  CAN_F11R1_FB6                       ((uint32_t)0x00000040)        /*!< Filter bit 6 */
+#define  CAN_F11R1_FB7                       ((uint32_t)0x00000080)        /*!< Filter bit 7 */
+#define  CAN_F11R1_FB8                       ((uint32_t)0x00000100)        /*!< Filter bit 8 */
+#define  CAN_F11R1_FB9                       ((uint32_t)0x00000200)        /*!< Filter bit 9 */
+#define  CAN_F11R1_FB10                      ((uint32_t)0x00000400)        /*!< Filter bit 10 */
+#define  CAN_F11R1_FB11                      ((uint32_t)0x00000800)        /*!< Filter bit 11 */
+#define  CAN_F11R1_FB12                      ((uint32_t)0x00001000)        /*!< Filter bit 12 */
+#define  CAN_F11R1_FB13                      ((uint32_t)0x00002000)        /*!< Filter bit 13 */
+#define  CAN_F11R1_FB14                      ((uint32_t)0x00004000)        /*!< Filter bit 14 */
+#define  CAN_F11R1_FB15                      ((uint32_t)0x00008000)        /*!< Filter bit 15 */
+#define  CAN_F11R1_FB16                      ((uint32_t)0x00010000)        /*!< Filter bit 16 */
+#define  CAN_F11R1_FB17                      ((uint32_t)0x00020000)        /*!< Filter bit 17 */
+#define  CAN_F11R1_FB18                      ((uint32_t)0x00040000)        /*!< Filter bit 18 */
+#define  CAN_F11R1_FB19                      ((uint32_t)0x00080000)        /*!< Filter bit 19 */
+#define  CAN_F11R1_FB20                      ((uint32_t)0x00100000)        /*!< Filter bit 20 */
+#define  CAN_F11R1_FB21                      ((uint32_t)0x00200000)        /*!< Filter bit 21 */
+#define  CAN_F11R1_FB22                      ((uint32_t)0x00400000)        /*!< Filter bit 22 */
+#define  CAN_F11R1_FB23                      ((uint32_t)0x00800000)        /*!< Filter bit 23 */
+#define  CAN_F11R1_FB24                      ((uint32_t)0x01000000)        /*!< Filter bit 24 */
+#define  CAN_F11R1_FB25                      ((uint32_t)0x02000000)        /*!< Filter bit 25 */
+#define  CAN_F11R1_FB26                      ((uint32_t)0x04000000)        /*!< Filter bit 26 */
+#define  CAN_F11R1_FB27                      ((uint32_t)0x08000000)        /*!< Filter bit 27 */
+#define  CAN_F11R1_FB28                      ((uint32_t)0x10000000)        /*!< Filter bit 28 */
+#define  CAN_F11R1_FB29                      ((uint32_t)0x20000000)        /*!< Filter bit 29 */
+#define  CAN_F11R1_FB30                      ((uint32_t)0x40000000)        /*!< Filter bit 30 */
+#define  CAN_F11R1_FB31                      ((uint32_t)0x80000000)        /*!< Filter bit 31 */
+
+/*******************  Bit definition for CAN_F12R1 register  ******************/
+#define  CAN_F12R1_FB0                       ((uint32_t)0x00000001)        /*!< Filter bit 0 */
+#define  CAN_F12R1_FB1                       ((uint32_t)0x00000002)        /*!< Filter bit 1 */
+#define  CAN_F12R1_FB2                       ((uint32_t)0x00000004)        /*!< Filter bit 2 */
+#define  CAN_F12R1_FB3                       ((uint32_t)0x00000008)        /*!< Filter bit 3 */
+#define  CAN_F12R1_FB4                       ((uint32_t)0x00000010)        /*!< Filter bit 4 */
+#define  CAN_F12R1_FB5                       ((uint32_t)0x00000020)        /*!< Filter bit 5 */
+#define  CAN_F12R1_FB6                       ((uint32_t)0x00000040)        /*!< Filter bit 6 */
+#define  CAN_F12R1_FB7                       ((uint32_t)0x00000080)        /*!< Filter bit 7 */
+#define  CAN_F12R1_FB8                       ((uint32_t)0x00000100)        /*!< Filter bit 8 */
+#define  CAN_F12R1_FB9                       ((uint32_t)0x00000200)        /*!< Filter bit 9 */
+#define  CAN_F12R1_FB10                      ((uint32_t)0x00000400)        /*!< Filter bit 10 */
+#define  CAN_F12R1_FB11                      ((uint32_t)0x00000800)        /*!< Filter bit 11 */
+#define  CAN_F12R1_FB12                      ((uint32_t)0x00001000)        /*!< Filter bit 12 */
+#define  CAN_F12R1_FB13                      ((uint32_t)0x00002000)        /*!< Filter bit 13 */
+#define  CAN_F12R1_FB14                      ((uint32_t)0x00004000)        /*!< Filter bit 14 */
+#define  CAN_F12R1_FB15                      ((uint32_t)0x00008000)        /*!< Filter bit 15 */
+#define  CAN_F12R1_FB16                      ((uint32_t)0x00010000)        /*!< Filter bit 16 */
+#define  CAN_F12R1_FB17                      ((uint32_t)0x00020000)        /*!< Filter bit 17 */
+#define  CAN_F12R1_FB18                      ((uint32_t)0x00040000)        /*!< Filter bit 18 */
+#define  CAN_F12R1_FB19                      ((uint32_t)0x00080000)        /*!< Filter bit 19 */
+#define  CAN_F12R1_FB20                      ((uint32_t)0x00100000)        /*!< Filter bit 20 */
+#define  CAN_F12R1_FB21                      ((uint32_t)0x00200000)        /*!< Filter bit 21 */
+#define  CAN_F12R1_FB22                      ((uint32_t)0x00400000)        /*!< Filter bit 22 */
+#define  CAN_F12R1_FB23                      ((uint32_t)0x00800000)        /*!< Filter bit 23 */
+#define  CAN_F12R1_FB24                      ((uint32_t)0x01000000)        /*!< Filter bit 24 */
+#define  CAN_F12R1_FB25                      ((uint32_t)0x02000000)        /*!< Filter bit 25 */
+#define  CAN_F12R1_FB26                      ((uint32_t)0x04000000)        /*!< Filter bit 26 */
+#define  CAN_F12R1_FB27                      ((uint32_t)0x08000000)        /*!< Filter bit 27 */
+#define  CAN_F12R1_FB28                      ((uint32_t)0x10000000)        /*!< Filter bit 28 */
+#define  CAN_F12R1_FB29                      ((uint32_t)0x20000000)        /*!< Filter bit 29 */
+#define  CAN_F12R1_FB30                      ((uint32_t)0x40000000)        /*!< Filter bit 30 */
+#define  CAN_F12R1_FB31                      ((uint32_t)0x80000000)        /*!< Filter bit 31 */
+
+/*******************  Bit definition for CAN_F13R1 register  ******************/
+#define  CAN_F13R1_FB0                       ((uint32_t)0x00000001)        /*!< Filter bit 0 */
+#define  CAN_F13R1_FB1                       ((uint32_t)0x00000002)        /*!< Filter bit 1 */
+#define  CAN_F13R1_FB2                       ((uint32_t)0x00000004)        /*!< Filter bit 2 */
+#define  CAN_F13R1_FB3                       ((uint32_t)0x00000008)        /*!< Filter bit 3 */
+#define  CAN_F13R1_FB4                       ((uint32_t)0x00000010)        /*!< Filter bit 4 */
+#define  CAN_F13R1_FB5                       ((uint32_t)0x00000020)        /*!< Filter bit 5 */
+#define  CAN_F13R1_FB6                       ((uint32_t)0x00000040)        /*!< Filter bit 6 */
+#define  CAN_F13R1_FB7                       ((uint32_t)0x00000080)        /*!< Filter bit 7 */
+#define  CAN_F13R1_FB8                       ((uint32_t)0x00000100)        /*!< Filter bit 8 */
+#define  CAN_F13R1_FB9                       ((uint32_t)0x00000200)        /*!< Filter bit 9 */
+#define  CAN_F13R1_FB10                      ((uint32_t)0x00000400)        /*!< Filter bit 10 */
+#define  CAN_F13R1_FB11                      ((uint32_t)0x00000800)        /*!< Filter bit 11 */
+#define  CAN_F13R1_FB12                      ((uint32_t)0x00001000)        /*!< Filter bit 12 */
+#define  CAN_F13R1_FB13                      ((uint32_t)0x00002000)        /*!< Filter bit 13 */
+#define  CAN_F13R1_FB14                      ((uint32_t)0x00004000)        /*!< Filter bit 14 */
+#define  CAN_F13R1_FB15                      ((uint32_t)0x00008000)        /*!< Filter bit 15 */
+#define  CAN_F13R1_FB16                      ((uint32_t)0x00010000)        /*!< Filter bit 16 */
+#define  CAN_F13R1_FB17                      ((uint32_t)0x00020000)        /*!< Filter bit 17 */
+#define  CAN_F13R1_FB18                      ((uint32_t)0x00040000)        /*!< Filter bit 18 */
+#define  CAN_F13R1_FB19                      ((uint32_t)0x00080000)        /*!< Filter bit 19 */
+#define  CAN_F13R1_FB20                      ((uint32_t)0x00100000)        /*!< Filter bit 20 */
+#define  CAN_F13R1_FB21                      ((uint32_t)0x00200000)        /*!< Filter bit 21 */
+#define  CAN_F13R1_FB22                      ((uint32_t)0x00400000)        /*!< Filter bit 22 */
+#define  CAN_F13R1_FB23                      ((uint32_t)0x00800000)        /*!< Filter bit 23 */
+#define  CAN_F13R1_FB24                      ((uint32_t)0x01000000)        /*!< Filter bit 24 */
+#define  CAN_F13R1_FB25                      ((uint32_t)0x02000000)        /*!< Filter bit 25 */
+#define  CAN_F13R1_FB26                      ((uint32_t)0x04000000)        /*!< Filter bit 26 */
+#define  CAN_F13R1_FB27                      ((uint32_t)0x08000000)        /*!< Filter bit 27 */
+#define  CAN_F13R1_FB28                      ((uint32_t)0x10000000)        /*!< Filter bit 28 */
+#define  CAN_F13R1_FB29                      ((uint32_t)0x20000000)        /*!< Filter bit 29 */
+#define  CAN_F13R1_FB30                      ((uint32_t)0x40000000)        /*!< Filter bit 30 */
+#define  CAN_F13R1_FB31                      ((uint32_t)0x80000000)        /*!< Filter bit 31 */
+
+/*******************  Bit definition for CAN_F0R2 register  *******************/
+#define  CAN_F0R2_FB0                        ((uint32_t)0x00000001)        /*!< Filter bit 0 */
+#define  CAN_F0R2_FB1                        ((uint32_t)0x00000002)        /*!< Filter bit 1 */
+#define  CAN_F0R2_FB2                        ((uint32_t)0x00000004)        /*!< Filter bit 2 */
+#define  CAN_F0R2_FB3                        ((uint32_t)0x00000008)        /*!< Filter bit 3 */
+#define  CAN_F0R2_FB4                        ((uint32_t)0x00000010)        /*!< Filter bit 4 */
+#define  CAN_F0R2_FB5                        ((uint32_t)0x00000020)        /*!< Filter bit 5 */
+#define  CAN_F0R2_FB6                        ((uint32_t)0x00000040)        /*!< Filter bit 6 */
+#define  CAN_F0R2_FB7                        ((uint32_t)0x00000080)        /*!< Filter bit 7 */
+#define  CAN_F0R2_FB8                        ((uint32_t)0x00000100)        /*!< Filter bit 8 */
+#define  CAN_F0R2_FB9                        ((uint32_t)0x00000200)        /*!< Filter bit 9 */
+#define  CAN_F0R2_FB10                       ((uint32_t)0x00000400)        /*!< Filter bit 10 */
+#define  CAN_F0R2_FB11                       ((uint32_t)0x00000800)        /*!< Filter bit 11 */
+#define  CAN_F0R2_FB12                       ((uint32_t)0x00001000)        /*!< Filter bit 12 */
+#define  CAN_F0R2_FB13                       ((uint32_t)0x00002000)        /*!< Filter bit 13 */
+#define  CAN_F0R2_FB14                       ((uint32_t)0x00004000)        /*!< Filter bit 14 */
+#define  CAN_F0R2_FB15                       ((uint32_t)0x00008000)        /*!< Filter bit 15 */
+#define  CAN_F0R2_FB16                       ((uint32_t)0x00010000)        /*!< Filter bit 16 */
+#define  CAN_F0R2_FB17                       ((uint32_t)0x00020000)        /*!< Filter bit 17 */
+#define  CAN_F0R2_FB18                       ((uint32_t)0x00040000)        /*!< Filter bit 18 */
+#define  CAN_F0R2_FB19                       ((uint32_t)0x00080000)        /*!< Filter bit 19 */
+#define  CAN_F0R2_FB20                       ((uint32_t)0x00100000)        /*!< Filter bit 20 */
+#define  CAN_F0R2_FB21                       ((uint32_t)0x00200000)        /*!< Filter bit 21 */
+#define  CAN_F0R2_FB22                       ((uint32_t)0x00400000)        /*!< Filter bit 22 */
+#define  CAN_F0R2_FB23                       ((uint32_t)0x00800000)        /*!< Filter bit 23 */
+#define  CAN_F0R2_FB24                       ((uint32_t)0x01000000)        /*!< Filter bit 24 */
+#define  CAN_F0R2_FB25                       ((uint32_t)0x02000000)        /*!< Filter bit 25 */
+#define  CAN_F0R2_FB26                       ((uint32_t)0x04000000)        /*!< Filter bit 26 */
+#define  CAN_F0R2_FB27                       ((uint32_t)0x08000000)        /*!< Filter bit 27 */
+#define  CAN_F0R2_FB28                       ((uint32_t)0x10000000)        /*!< Filter bit 28 */
+#define  CAN_F0R2_FB29                       ((uint32_t)0x20000000)        /*!< Filter bit 29 */
+#define  CAN_F0R2_FB30                       ((uint32_t)0x40000000)        /*!< Filter bit 30 */
+#define  CAN_F0R2_FB31                       ((uint32_t)0x80000000)        /*!< Filter bit 31 */
+
+/*******************  Bit definition for CAN_F1R2 register  *******************/
+#define  CAN_F1R2_FB0                        ((uint32_t)0x00000001)        /*!< Filter bit 0 */
+#define  CAN_F1R2_FB1                        ((uint32_t)0x00000002)        /*!< Filter bit 1 */
+#define  CAN_F1R2_FB2                        ((uint32_t)0x00000004)        /*!< Filter bit 2 */
+#define  CAN_F1R2_FB3                        ((uint32_t)0x00000008)        /*!< Filter bit 3 */
+#define  CAN_F1R2_FB4                        ((uint32_t)0x00000010)        /*!< Filter bit 4 */
+#define  CAN_F1R2_FB5                        ((uint32_t)0x00000020)        /*!< Filter bit 5 */
+#define  CAN_F1R2_FB6                        ((uint32_t)0x00000040)        /*!< Filter bit 6 */
+#define  CAN_F1R2_FB7                        ((uint32_t)0x00000080)        /*!< Filter bit 7 */
+#define  CAN_F1R2_FB8                        ((uint32_t)0x00000100)        /*!< Filter bit 8 */
+#define  CAN_F1R2_FB9                        ((uint32_t)0x00000200)        /*!< Filter bit 9 */
+#define  CAN_F1R2_FB10                       ((uint32_t)0x00000400)        /*!< Filter bit 10 */
+#define  CAN_F1R2_FB11                       ((uint32_t)0x00000800)        /*!< Filter bit 11 */
+#define  CAN_F1R2_FB12                       ((uint32_t)0x00001000)        /*!< Filter bit 12 */
+#define  CAN_F1R2_FB13                       ((uint32_t)0x00002000)        /*!< Filter bit 13 */
+#define  CAN_F1R2_FB14                       ((uint32_t)0x00004000)        /*!< Filter bit 14 */
+#define  CAN_F1R2_FB15                       ((uint32_t)0x00008000)        /*!< Filter bit 15 */
+#define  CAN_F1R2_FB16                       ((uint32_t)0x00010000)        /*!< Filter bit 16 */
+#define  CAN_F1R2_FB17                       ((uint32_t)0x00020000)        /*!< Filter bit 17 */
+#define  CAN_F1R2_FB18                       ((uint32_t)0x00040000)        /*!< Filter bit 18 */
+#define  CAN_F1R2_FB19                       ((uint32_t)0x00080000)        /*!< Filter bit 19 */
+#define  CAN_F1R2_FB20                       ((uint32_t)0x00100000)        /*!< Filter bit 20 */
+#define  CAN_F1R2_FB21                       ((uint32_t)0x00200000)        /*!< Filter bit 21 */
+#define  CAN_F1R2_FB22                       ((uint32_t)0x00400000)        /*!< Filter bit 22 */
+#define  CAN_F1R2_FB23                       ((uint32_t)0x00800000)        /*!< Filter bit 23 */
+#define  CAN_F1R2_FB24                       ((uint32_t)0x01000000)        /*!< Filter bit 24 */
+#define  CAN_F1R2_FB25                       ((uint32_t)0x02000000)        /*!< Filter bit 25 */
+#define  CAN_F1R2_FB26                       ((uint32_t)0x04000000)        /*!< Filter bit 26 */
+#define  CAN_F1R2_FB27                       ((uint32_t)0x08000000)        /*!< Filter bit 27 */
+#define  CAN_F1R2_FB28                       ((uint32_t)0x10000000)        /*!< Filter bit 28 */
+#define  CAN_F1R2_FB29                       ((uint32_t)0x20000000)        /*!< Filter bit 29 */
+#define  CAN_F1R2_FB30                       ((uint32_t)0x40000000)        /*!< Filter bit 30 */
+#define  CAN_F1R2_FB31                       ((uint32_t)0x80000000)        /*!< Filter bit 31 */
+
+/*******************  Bit definition for CAN_F2R2 register  *******************/
+#define  CAN_F2R2_FB0                        ((uint32_t)0x00000001)        /*!< Filter bit 0 */
+#define  CAN_F2R2_FB1                        ((uint32_t)0x00000002)        /*!< Filter bit 1 */
+#define  CAN_F2R2_FB2                        ((uint32_t)0x00000004)        /*!< Filter bit 2 */
+#define  CAN_F2R2_FB3                        ((uint32_t)0x00000008)        /*!< Filter bit 3 */
+#define  CAN_F2R2_FB4                        ((uint32_t)0x00000010)        /*!< Filter bit 4 */
+#define  CAN_F2R2_FB5                        ((uint32_t)0x00000020)        /*!< Filter bit 5 */
+#define  CAN_F2R2_FB6                        ((uint32_t)0x00000040)        /*!< Filter bit 6 */
+#define  CAN_F2R2_FB7                        ((uint32_t)0x00000080)        /*!< Filter bit 7 */
+#define  CAN_F2R2_FB8                        ((uint32_t)0x00000100)        /*!< Filter bit 8 */
+#define  CAN_F2R2_FB9                        ((uint32_t)0x00000200)        /*!< Filter bit 9 */
+#define  CAN_F2R2_FB10                       ((uint32_t)0x00000400)        /*!< Filter bit 10 */
+#define  CAN_F2R2_FB11                       ((uint32_t)0x00000800)        /*!< Filter bit 11 */
+#define  CAN_F2R2_FB12                       ((uint32_t)0x00001000)        /*!< Filter bit 12 */
+#define  CAN_F2R2_FB13                       ((uint32_t)0x00002000)        /*!< Filter bit 13 */
+#define  CAN_F2R2_FB14                       ((uint32_t)0x00004000)        /*!< Filter bit 14 */
+#define  CAN_F2R2_FB15                       ((uint32_t)0x00008000)        /*!< Filter bit 15 */
+#define  CAN_F2R2_FB16                       ((uint32_t)0x00010000)        /*!< Filter bit 16 */
+#define  CAN_F2R2_FB17                       ((uint32_t)0x00020000)        /*!< Filter bit 17 */
+#define  CAN_F2R2_FB18                       ((uint32_t)0x00040000)        /*!< Filter bit 18 */
+#define  CAN_F2R2_FB19                       ((uint32_t)0x00080000)        /*!< Filter bit 19 */
+#define  CAN_F2R2_FB20                       ((uint32_t)0x00100000)        /*!< Filter bit 20 */
+#define  CAN_F2R2_FB21                       ((uint32_t)0x00200000)        /*!< Filter bit 21 */
+#define  CAN_F2R2_FB22                       ((uint32_t)0x00400000)        /*!< Filter bit 22 */
+#define  CAN_F2R2_FB23                       ((uint32_t)0x00800000)        /*!< Filter bit 23 */
+#define  CAN_F2R2_FB24                       ((uint32_t)0x01000000)        /*!< Filter bit 24 */
+#define  CAN_F2R2_FB25                       ((uint32_t)0x02000000)        /*!< Filter bit 25 */
+#define  CAN_F2R2_FB26                       ((uint32_t)0x04000000)        /*!< Filter bit 26 */
+#define  CAN_F2R2_FB27                       ((uint32_t)0x08000000)        /*!< Filter bit 27 */
+#define  CAN_F2R2_FB28                       ((uint32_t)0x10000000)        /*!< Filter bit 28 */
+#define  CAN_F2R2_FB29                       ((uint32_t)0x20000000)        /*!< Filter bit 29 */
+#define  CAN_F2R2_FB30                       ((uint32_t)0x40000000)        /*!< Filter bit 30 */
+#define  CAN_F2R2_FB31                       ((uint32_t)0x80000000)        /*!< Filter bit 31 */
+
+/*******************  Bit definition for CAN_F3R2 register  *******************/
+#define  CAN_F3R2_FB0                        ((uint32_t)0x00000001)        /*!< Filter bit 0 */
+#define  CAN_F3R2_FB1                        ((uint32_t)0x00000002)        /*!< Filter bit 1 */
+#define  CAN_F3R2_FB2                        ((uint32_t)0x00000004)        /*!< Filter bit 2 */
+#define  CAN_F3R2_FB3                        ((uint32_t)0x00000008)        /*!< Filter bit 3 */
+#define  CAN_F3R2_FB4                        ((uint32_t)0x00000010)        /*!< Filter bit 4 */
+#define  CAN_F3R2_FB5                        ((uint32_t)0x00000020)        /*!< Filter bit 5 */
+#define  CAN_F3R2_FB6                        ((uint32_t)0x00000040)        /*!< Filter bit 6 */
+#define  CAN_F3R2_FB7                        ((uint32_t)0x00000080)        /*!< Filter bit 7 */
+#define  CAN_F3R2_FB8                        ((uint32_t)0x00000100)        /*!< Filter bit 8 */
+#define  CAN_F3R2_FB9                        ((uint32_t)0x00000200)        /*!< Filter bit 9 */
+#define  CAN_F3R2_FB10                       ((uint32_t)0x00000400)        /*!< Filter bit 10 */
+#define  CAN_F3R2_FB11                       ((uint32_t)0x00000800)        /*!< Filter bit 11 */
+#define  CAN_F3R2_FB12                       ((uint32_t)0x00001000)        /*!< Filter bit 12 */
+#define  CAN_F3R2_FB13                       ((uint32_t)0x00002000)        /*!< Filter bit 13 */
+#define  CAN_F3R2_FB14                       ((uint32_t)0x00004000)        /*!< Filter bit 14 */
+#define  CAN_F3R2_FB15                       ((uint32_t)0x00008000)        /*!< Filter bit 15 */
+#define  CAN_F3R2_FB16                       ((uint32_t)0x00010000)        /*!< Filter bit 16 */
+#define  CAN_F3R2_FB17                       ((uint32_t)0x00020000)        /*!< Filter bit 17 */
+#define  CAN_F3R2_FB18                       ((uint32_t)0x00040000)        /*!< Filter bit 18 */
+#define  CAN_F3R2_FB19                       ((uint32_t)0x00080000)        /*!< Filter bit 19 */
+#define  CAN_F3R2_FB20                       ((uint32_t)0x00100000)        /*!< Filter bit 20 */
+#define  CAN_F3R2_FB21                       ((uint32_t)0x00200000)        /*!< Filter bit 21 */
+#define  CAN_F3R2_FB22                       ((uint32_t)0x00400000)        /*!< Filter bit 22 */
+#define  CAN_F3R2_FB23                       ((uint32_t)0x00800000)        /*!< Filter bit 23 */
+#define  CAN_F3R2_FB24                       ((uint32_t)0x01000000)        /*!< Filter bit 24 */
+#define  CAN_F3R2_FB25                       ((uint32_t)0x02000000)        /*!< Filter bit 25 */
+#define  CAN_F3R2_FB26                       ((uint32_t)0x04000000)        /*!< Filter bit 26 */
+#define  CAN_F3R2_FB27                       ((uint32_t)0x08000000)        /*!< Filter bit 27 */
+#define  CAN_F3R2_FB28                       ((uint32_t)0x10000000)        /*!< Filter bit 28 */
+#define  CAN_F3R2_FB29                       ((uint32_t)0x20000000)        /*!< Filter bit 29 */
+#define  CAN_F3R2_FB30                       ((uint32_t)0x40000000)        /*!< Filter bit 30 */
+#define  CAN_F3R2_FB31                       ((uint32_t)0x80000000)        /*!< Filter bit 31 */
+
+/*******************  Bit definition for CAN_F4R2 register  *******************/
+#define  CAN_F4R2_FB0                        ((uint32_t)0x00000001)        /*!< Filter bit 0 */
+#define  CAN_F4R2_FB1                        ((uint32_t)0x00000002)        /*!< Filter bit 1 */
+#define  CAN_F4R2_FB2                        ((uint32_t)0x00000004)        /*!< Filter bit 2 */
+#define  CAN_F4R2_FB3                        ((uint32_t)0x00000008)        /*!< Filter bit 3 */
+#define  CAN_F4R2_FB4                        ((uint32_t)0x00000010)        /*!< Filter bit 4 */
+#define  CAN_F4R2_FB5                        ((uint32_t)0x00000020)        /*!< Filter bit 5 */
+#define  CAN_F4R2_FB6                        ((uint32_t)0x00000040)        /*!< Filter bit 6 */
+#define  CAN_F4R2_FB7                        ((uint32_t)0x00000080)        /*!< Filter bit 7 */
+#define  CAN_F4R2_FB8                        ((uint32_t)0x00000100)        /*!< Filter bit 8 */
+#define  CAN_F4R2_FB9                        ((uint32_t)0x00000200)        /*!< Filter bit 9 */
+#define  CAN_F4R2_FB10                       ((uint32_t)0x00000400)        /*!< Filter bit 10 */
+#define  CAN_F4R2_FB11                       ((uint32_t)0x00000800)        /*!< Filter bit 11 */
+#define  CAN_F4R2_FB12                       ((uint32_t)0x00001000)        /*!< Filter bit 12 */
+#define  CAN_F4R2_FB13                       ((uint32_t)0x00002000)        /*!< Filter bit 13 */
+#define  CAN_F4R2_FB14                       ((uint32_t)0x00004000)        /*!< Filter bit 14 */
+#define  CAN_F4R2_FB15                       ((uint32_t)0x00008000)        /*!< Filter bit 15 */
+#define  CAN_F4R2_FB16                       ((uint32_t)0x00010000)        /*!< Filter bit 16 */
+#define  CAN_F4R2_FB17                       ((uint32_t)0x00020000)        /*!< Filter bit 17 */
+#define  CAN_F4R2_FB18                       ((uint32_t)0x00040000)        /*!< Filter bit 18 */
+#define  CAN_F4R2_FB19                       ((uint32_t)0x00080000)        /*!< Filter bit 19 */
+#define  CAN_F4R2_FB20                       ((uint32_t)0x00100000)        /*!< Filter bit 20 */
+#define  CAN_F4R2_FB21                       ((uint32_t)0x00200000)        /*!< Filter bit 21 */
+#define  CAN_F4R2_FB22                       ((uint32_t)0x00400000)        /*!< Filter bit 22 */
+#define  CAN_F4R2_FB23                       ((uint32_t)0x00800000)        /*!< Filter bit 23 */
+#define  CAN_F4R2_FB24                       ((uint32_t)0x01000000)        /*!< Filter bit 24 */
+#define  CAN_F4R2_FB25                       ((uint32_t)0x02000000)        /*!< Filter bit 25 */
+#define  CAN_F4R2_FB26                       ((uint32_t)0x04000000)        /*!< Filter bit 26 */
+#define  CAN_F4R2_FB27                       ((uint32_t)0x08000000)        /*!< Filter bit 27 */
+#define  CAN_F4R2_FB28                       ((uint32_t)0x10000000)        /*!< Filter bit 28 */
+#define  CAN_F4R2_FB29                       ((uint32_t)0x20000000)        /*!< Filter bit 29 */
+#define  CAN_F4R2_FB30                       ((uint32_t)0x40000000)        /*!< Filter bit 30 */
+#define  CAN_F4R2_FB31                       ((uint32_t)0x80000000)        /*!< Filter bit 31 */
+
+/*******************  Bit definition for CAN_F5R2 register  *******************/
+#define  CAN_F5R2_FB0                        ((uint32_t)0x00000001)        /*!< Filter bit 0 */
+#define  CAN_F5R2_FB1                        ((uint32_t)0x00000002)        /*!< Filter bit 1 */
+#define  CAN_F5R2_FB2                        ((uint32_t)0x00000004)        /*!< Filter bit 2 */
+#define  CAN_F5R2_FB3                        ((uint32_t)0x00000008)        /*!< Filter bit 3 */
+#define  CAN_F5R2_FB4                        ((uint32_t)0x00000010)        /*!< Filter bit 4 */
+#define  CAN_F5R2_FB5                        ((uint32_t)0x00000020)        /*!< Filter bit 5 */
+#define  CAN_F5R2_FB6                        ((uint32_t)0x00000040)        /*!< Filter bit 6 */
+#define  CAN_F5R2_FB7                        ((uint32_t)0x00000080)        /*!< Filter bit 7 */
+#define  CAN_F5R2_FB8                        ((uint32_t)0x00000100)        /*!< Filter bit 8 */
+#define  CAN_F5R2_FB9                        ((uint32_t)0x00000200)        /*!< Filter bit 9 */
+#define  CAN_F5R2_FB10                       ((uint32_t)0x00000400)        /*!< Filter bit 10 */
+#define  CAN_F5R2_FB11                       ((uint32_t)0x00000800)        /*!< Filter bit 11 */
+#define  CAN_F5R2_FB12                       ((uint32_t)0x00001000)        /*!< Filter bit 12 */
+#define  CAN_F5R2_FB13                       ((uint32_t)0x00002000)        /*!< Filter bit 13 */
+#define  CAN_F5R2_FB14                       ((uint32_t)0x00004000)        /*!< Filter bit 14 */
+#define  CAN_F5R2_FB15                       ((uint32_t)0x00008000)        /*!< Filter bit 15 */
+#define  CAN_F5R2_FB16                       ((uint32_t)0x00010000)        /*!< Filter bit 16 */
+#define  CAN_F5R2_FB17                       ((uint32_t)0x00020000)        /*!< Filter bit 17 */
+#define  CAN_F5R2_FB18                       ((uint32_t)0x00040000)        /*!< Filter bit 18 */
+#define  CAN_F5R2_FB19                       ((uint32_t)0x00080000)        /*!< Filter bit 19 */
+#define  CAN_F5R2_FB20                       ((uint32_t)0x00100000)        /*!< Filter bit 20 */
+#define  CAN_F5R2_FB21                       ((uint32_t)0x00200000)        /*!< Filter bit 21 */
+#define  CAN_F5R2_FB22                       ((uint32_t)0x00400000)        /*!< Filter bit 22 */
+#define  CAN_F5R2_FB23                       ((uint32_t)0x00800000)        /*!< Filter bit 23 */
+#define  CAN_F5R2_FB24                       ((uint32_t)0x01000000)        /*!< Filter bit 24 */
+#define  CAN_F5R2_FB25                       ((uint32_t)0x02000000)        /*!< Filter bit 25 */
+#define  CAN_F5R2_FB26                       ((uint32_t)0x04000000)        /*!< Filter bit 26 */
+#define  CAN_F5R2_FB27                       ((uint32_t)0x08000000)        /*!< Filter bit 27 */
+#define  CAN_F5R2_FB28                       ((uint32_t)0x10000000)        /*!< Filter bit 28 */
+#define  CAN_F5R2_FB29                       ((uint32_t)0x20000000)        /*!< Filter bit 29 */
+#define  CAN_F5R2_FB30                       ((uint32_t)0x40000000)        /*!< Filter bit 30 */
+#define  CAN_F5R2_FB31                       ((uint32_t)0x80000000)        /*!< Filter bit 31 */
+
+/*******************  Bit definition for CAN_F6R2 register  *******************/
+#define  CAN_F6R2_FB0                        ((uint32_t)0x00000001)        /*!< Filter bit 0 */
+#define  CAN_F6R2_FB1                        ((uint32_t)0x00000002)        /*!< Filter bit 1 */
+#define  CAN_F6R2_FB2                        ((uint32_t)0x00000004)        /*!< Filter bit 2 */
+#define  CAN_F6R2_FB3                        ((uint32_t)0x00000008)        /*!< Filter bit 3 */
+#define  CAN_F6R2_FB4                        ((uint32_t)0x00000010)        /*!< Filter bit 4 */
+#define  CAN_F6R2_FB5                        ((uint32_t)0x00000020)        /*!< Filter bit 5 */
+#define  CAN_F6R2_FB6                        ((uint32_t)0x00000040)        /*!< Filter bit 6 */
+#define  CAN_F6R2_FB7                        ((uint32_t)0x00000080)        /*!< Filter bit 7 */
+#define  CAN_F6R2_FB8                        ((uint32_t)0x00000100)        /*!< Filter bit 8 */
+#define  CAN_F6R2_FB9                        ((uint32_t)0x00000200)        /*!< Filter bit 9 */
+#define  CAN_F6R2_FB10                       ((uint32_t)0x00000400)        /*!< Filter bit 10 */
+#define  CAN_F6R2_FB11                       ((uint32_t)0x00000800)        /*!< Filter bit 11 */
+#define  CAN_F6R2_FB12                       ((uint32_t)0x00001000)        /*!< Filter bit 12 */
+#define  CAN_F6R2_FB13                       ((uint32_t)0x00002000)        /*!< Filter bit 13 */
+#define  CAN_F6R2_FB14                       ((uint32_t)0x00004000)        /*!< Filter bit 14 */
+#define  CAN_F6R2_FB15                       ((uint32_t)0x00008000)        /*!< Filter bit 15 */
+#define  CAN_F6R2_FB16                       ((uint32_t)0x00010000)        /*!< Filter bit 16 */
+#define  CAN_F6R2_FB17                       ((uint32_t)0x00020000)        /*!< Filter bit 17 */
+#define  CAN_F6R2_FB18                       ((uint32_t)0x00040000)        /*!< Filter bit 18 */
+#define  CAN_F6R2_FB19                       ((uint32_t)0x00080000)        /*!< Filter bit 19 */
+#define  CAN_F6R2_FB20                       ((uint32_t)0x00100000)        /*!< Filter bit 20 */
+#define  CAN_F6R2_FB21                       ((uint32_t)0x00200000)        /*!< Filter bit 21 */
+#define  CAN_F6R2_FB22                       ((uint32_t)0x00400000)        /*!< Filter bit 22 */
+#define  CAN_F6R2_FB23                       ((uint32_t)0x00800000)        /*!< Filter bit 23 */
+#define  CAN_F6R2_FB24                       ((uint32_t)0x01000000)        /*!< Filter bit 24 */
+#define  CAN_F6R2_FB25                       ((uint32_t)0x02000000)        /*!< Filter bit 25 */
+#define  CAN_F6R2_FB26                       ((uint32_t)0x04000000)        /*!< Filter bit 26 */
+#define  CAN_F6R2_FB27                       ((uint32_t)0x08000000)        /*!< Filter bit 27 */
+#define  CAN_F6R2_FB28                       ((uint32_t)0x10000000)        /*!< Filter bit 28 */
+#define  CAN_F6R2_FB29                       ((uint32_t)0x20000000)        /*!< Filter bit 29 */
+#define  CAN_F6R2_FB30                       ((uint32_t)0x40000000)        /*!< Filter bit 30 */
+#define  CAN_F6R2_FB31                       ((uint32_t)0x80000000)        /*!< Filter bit 31 */
+
+/*******************  Bit definition for CAN_F7R2 register  *******************/
+#define  CAN_F7R2_FB0                        ((uint32_t)0x00000001)        /*!< Filter bit 0 */
+#define  CAN_F7R2_FB1                        ((uint32_t)0x00000002)        /*!< Filter bit 1 */
+#define  CAN_F7R2_FB2                        ((uint32_t)0x00000004)        /*!< Filter bit 2 */
+#define  CAN_F7R2_FB3                        ((uint32_t)0x00000008)        /*!< Filter bit 3 */
+#define  CAN_F7R2_FB4                        ((uint32_t)0x00000010)        /*!< Filter bit 4 */
+#define  CAN_F7R2_FB5                        ((uint32_t)0x00000020)        /*!< Filter bit 5 */
+#define  CAN_F7R2_FB6                        ((uint32_t)0x00000040)        /*!< Filter bit 6 */
+#define  CAN_F7R2_FB7                        ((uint32_t)0x00000080)        /*!< Filter bit 7 */
+#define  CAN_F7R2_FB8                        ((uint32_t)0x00000100)        /*!< Filter bit 8 */
+#define  CAN_F7R2_FB9                        ((uint32_t)0x00000200)        /*!< Filter bit 9 */
+#define  CAN_F7R2_FB10                       ((uint32_t)0x00000400)        /*!< Filter bit 10 */
+#define  CAN_F7R2_FB11                       ((uint32_t)0x00000800)        /*!< Filter bit 11 */
+#define  CAN_F7R2_FB12                       ((uint32_t)0x00001000)        /*!< Filter bit 12 */
+#define  CAN_F7R2_FB13                       ((uint32_t)0x00002000)        /*!< Filter bit 13 */
+#define  CAN_F7R2_FB14                       ((uint32_t)0x00004000)        /*!< Filter bit 14 */
+#define  CAN_F7R2_FB15                       ((uint32_t)0x00008000)        /*!< Filter bit 15 */
+#define  CAN_F7R2_FB16                       ((uint32_t)0x00010000)        /*!< Filter bit 16 */
+#define  CAN_F7R2_FB17                       ((uint32_t)0x00020000)        /*!< Filter bit 17 */
+#define  CAN_F7R2_FB18                       ((uint32_t)0x00040000)        /*!< Filter bit 18 */
+#define  CAN_F7R2_FB19                       ((uint32_t)0x00080000)        /*!< Filter bit 19 */
+#define  CAN_F7R2_FB20                       ((uint32_t)0x00100000)        /*!< Filter bit 20 */
+#define  CAN_F7R2_FB21                       ((uint32_t)0x00200000)        /*!< Filter bit 21 */
+#define  CAN_F7R2_FB22                       ((uint32_t)0x00400000)        /*!< Filter bit 22 */
+#define  CAN_F7R2_FB23                       ((uint32_t)0x00800000)        /*!< Filter bit 23 */
+#define  CAN_F7R2_FB24                       ((uint32_t)0x01000000)        /*!< Filter bit 24 */
+#define  CAN_F7R2_FB25                       ((uint32_t)0x02000000)        /*!< Filter bit 25 */
+#define  CAN_F7R2_FB26                       ((uint32_t)0x04000000)        /*!< Filter bit 26 */
+#define  CAN_F7R2_FB27                       ((uint32_t)0x08000000)        /*!< Filter bit 27 */
+#define  CAN_F7R2_FB28                       ((uint32_t)0x10000000)        /*!< Filter bit 28 */
+#define  CAN_F7R2_FB29                       ((uint32_t)0x20000000)        /*!< Filter bit 29 */
+#define  CAN_F7R2_FB30                       ((uint32_t)0x40000000)        /*!< Filter bit 30 */
+#define  CAN_F7R2_FB31                       ((uint32_t)0x80000000)        /*!< Filter bit 31 */
+
+/*******************  Bit definition for CAN_F8R2 register  *******************/
+#define  CAN_F8R2_FB0                        ((uint32_t)0x00000001)        /*!< Filter bit 0 */
+#define  CAN_F8R2_FB1                        ((uint32_t)0x00000002)        /*!< Filter bit 1 */
+#define  CAN_F8R2_FB2                        ((uint32_t)0x00000004)        /*!< Filter bit 2 */
+#define  CAN_F8R2_FB3                        ((uint32_t)0x00000008)        /*!< Filter bit 3 */
+#define  CAN_F8R2_FB4                        ((uint32_t)0x00000010)        /*!< Filter bit 4 */
+#define  CAN_F8R2_FB5                        ((uint32_t)0x00000020)        /*!< Filter bit 5 */
+#define  CAN_F8R2_FB6                        ((uint32_t)0x00000040)        /*!< Filter bit 6 */
+#define  CAN_F8R2_FB7                        ((uint32_t)0x00000080)        /*!< Filter bit 7 */
+#define  CAN_F8R2_FB8                        ((uint32_t)0x00000100)        /*!< Filter bit 8 */
+#define  CAN_F8R2_FB9                        ((uint32_t)0x00000200)        /*!< Filter bit 9 */
+#define  CAN_F8R2_FB10                       ((uint32_t)0x00000400)        /*!< Filter bit 10 */
+#define  CAN_F8R2_FB11                       ((uint32_t)0x00000800)        /*!< Filter bit 11 */
+#define  CAN_F8R2_FB12                       ((uint32_t)0x00001000)        /*!< Filter bit 12 */
+#define  CAN_F8R2_FB13                       ((uint32_t)0x00002000)        /*!< Filter bit 13 */
+#define  CAN_F8R2_FB14                       ((uint32_t)0x00004000)        /*!< Filter bit 14 */
+#define  CAN_F8R2_FB15                       ((uint32_t)0x00008000)        /*!< Filter bit 15 */
+#define  CAN_F8R2_FB16                       ((uint32_t)0x00010000)        /*!< Filter bit 16 */
+#define  CAN_F8R2_FB17                       ((uint32_t)0x00020000)        /*!< Filter bit 17 */
+#define  CAN_F8R2_FB18                       ((uint32_t)0x00040000)        /*!< Filter bit 18 */
+#define  CAN_F8R2_FB19                       ((uint32_t)0x00080000)        /*!< Filter bit 19 */
+#define  CAN_F8R2_FB20                       ((uint32_t)0x00100000)        /*!< Filter bit 20 */
+#define  CAN_F8R2_FB21                       ((uint32_t)0x00200000)        /*!< Filter bit 21 */
+#define  CAN_F8R2_FB22                       ((uint32_t)0x00400000)        /*!< Filter bit 22 */
+#define  CAN_F8R2_FB23                       ((uint32_t)0x00800000)        /*!< Filter bit 23 */
+#define  CAN_F8R2_FB24                       ((uint32_t)0x01000000)        /*!< Filter bit 24 */
+#define  CAN_F8R2_FB25                       ((uint32_t)0x02000000)        /*!< Filter bit 25 */
+#define  CAN_F8R2_FB26                       ((uint32_t)0x04000000)        /*!< Filter bit 26 */
+#define  CAN_F8R2_FB27                       ((uint32_t)0x08000000)        /*!< Filter bit 27 */
+#define  CAN_F8R2_FB28                       ((uint32_t)0x10000000)        /*!< Filter bit 28 */
+#define  CAN_F8R2_FB29                       ((uint32_t)0x20000000)        /*!< Filter bit 29 */
+#define  CAN_F8R2_FB30                       ((uint32_t)0x40000000)        /*!< Filter bit 30 */
+#define  CAN_F8R2_FB31                       ((uint32_t)0x80000000)        /*!< Filter bit 31 */
+
+/*******************  Bit definition for CAN_F9R2 register  *******************/
+#define  CAN_F9R2_FB0                        ((uint32_t)0x00000001)        /*!< Filter bit 0 */
+#define  CAN_F9R2_FB1                        ((uint32_t)0x00000002)        /*!< Filter bit 1 */
+#define  CAN_F9R2_FB2                        ((uint32_t)0x00000004)        /*!< Filter bit 2 */
+#define  CAN_F9R2_FB3                        ((uint32_t)0x00000008)        /*!< Filter bit 3 */
+#define  CAN_F9R2_FB4                        ((uint32_t)0x00000010)        /*!< Filter bit 4 */
+#define  CAN_F9R2_FB5                        ((uint32_t)0x00000020)        /*!< Filter bit 5 */
+#define  CAN_F9R2_FB6                        ((uint32_t)0x00000040)        /*!< Filter bit 6 */
+#define  CAN_F9R2_FB7                        ((uint32_t)0x00000080)        /*!< Filter bit 7 */
+#define  CAN_F9R2_FB8                        ((uint32_t)0x00000100)        /*!< Filter bit 8 */
+#define  CAN_F9R2_FB9                        ((uint32_t)0x00000200)        /*!< Filter bit 9 */
+#define  CAN_F9R2_FB10                       ((uint32_t)0x00000400)        /*!< Filter bit 10 */
+#define  CAN_F9R2_FB11                       ((uint32_t)0x00000800)        /*!< Filter bit 11 */
+#define  CAN_F9R2_FB12                       ((uint32_t)0x00001000)        /*!< Filter bit 12 */
+#define  CAN_F9R2_FB13                       ((uint32_t)0x00002000)        /*!< Filter bit 13 */
+#define  CAN_F9R2_FB14                       ((uint32_t)0x00004000)        /*!< Filter bit 14 */
+#define  CAN_F9R2_FB15                       ((uint32_t)0x00008000)        /*!< Filter bit 15 */
+#define  CAN_F9R2_FB16                       ((uint32_t)0x00010000)        /*!< Filter bit 16 */
+#define  CAN_F9R2_FB17                       ((uint32_t)0x00020000)        /*!< Filter bit 17 */
+#define  CAN_F9R2_FB18                       ((uint32_t)0x00040000)        /*!< Filter bit 18 */
+#define  CAN_F9R2_FB19                       ((uint32_t)0x00080000)        /*!< Filter bit 19 */
+#define  CAN_F9R2_FB20                       ((uint32_t)0x00100000)        /*!< Filter bit 20 */
+#define  CAN_F9R2_FB21                       ((uint32_t)0x00200000)        /*!< Filter bit 21 */
+#define  CAN_F9R2_FB22                       ((uint32_t)0x00400000)        /*!< Filter bit 22 */
+#define  CAN_F9R2_FB23                       ((uint32_t)0x00800000)        /*!< Filter bit 23 */
+#define  CAN_F9R2_FB24                       ((uint32_t)0x01000000)        /*!< Filter bit 24 */
+#define  CAN_F9R2_FB25                       ((uint32_t)0x02000000)        /*!< Filter bit 25 */
+#define  CAN_F9R2_FB26                       ((uint32_t)0x04000000)        /*!< Filter bit 26 */
+#define  CAN_F9R2_FB27                       ((uint32_t)0x08000000)        /*!< Filter bit 27 */
+#define  CAN_F9R2_FB28                       ((uint32_t)0x10000000)        /*!< Filter bit 28 */
+#define  CAN_F9R2_FB29                       ((uint32_t)0x20000000)        /*!< Filter bit 29 */
+#define  CAN_F9R2_FB30                       ((uint32_t)0x40000000)        /*!< Filter bit 30 */
+#define  CAN_F9R2_FB31                       ((uint32_t)0x80000000)        /*!< Filter bit 31 */
+
+/*******************  Bit definition for CAN_F10R2 register  ******************/
+#define  CAN_F10R2_FB0                       ((uint32_t)0x00000001)        /*!< Filter bit 0 */
+#define  CAN_F10R2_FB1                       ((uint32_t)0x00000002)        /*!< Filter bit 1 */
+#define  CAN_F10R2_FB2                       ((uint32_t)0x00000004)        /*!< Filter bit 2 */
+#define  CAN_F10R2_FB3                       ((uint32_t)0x00000008)        /*!< Filter bit 3 */
+#define  CAN_F10R2_FB4                       ((uint32_t)0x00000010)        /*!< Filter bit 4 */
+#define  CAN_F10R2_FB5                       ((uint32_t)0x00000020)        /*!< Filter bit 5 */
+#define  CAN_F10R2_FB6                       ((uint32_t)0x00000040)        /*!< Filter bit 6 */
+#define  CAN_F10R2_FB7                       ((uint32_t)0x00000080)        /*!< Filter bit 7 */
+#define  CAN_F10R2_FB8                       ((uint32_t)0x00000100)        /*!< Filter bit 8 */
+#define  CAN_F10R2_FB9                       ((uint32_t)0x00000200)        /*!< Filter bit 9 */
+#define  CAN_F10R2_FB10                      ((uint32_t)0x00000400)        /*!< Filter bit 10 */
+#define  CAN_F10R2_FB11                      ((uint32_t)0x00000800)        /*!< Filter bit 11 */
+#define  CAN_F10R2_FB12                      ((uint32_t)0x00001000)        /*!< Filter bit 12 */
+#define  CAN_F10R2_FB13                      ((uint32_t)0x00002000)        /*!< Filter bit 13 */
+#define  CAN_F10R2_FB14                      ((uint32_t)0x00004000)        /*!< Filter bit 14 */
+#define  CAN_F10R2_FB15                      ((uint32_t)0x00008000)        /*!< Filter bit 15 */
+#define  CAN_F10R2_FB16                      ((uint32_t)0x00010000)        /*!< Filter bit 16 */
+#define  CAN_F10R2_FB17                      ((uint32_t)0x00020000)        /*!< Filter bit 17 */
+#define  CAN_F10R2_FB18                      ((uint32_t)0x00040000)        /*!< Filter bit 18 */
+#define  CAN_F10R2_FB19                      ((uint32_t)0x00080000)        /*!< Filter bit 19 */
+#define  CAN_F10R2_FB20                      ((uint32_t)0x00100000)        /*!< Filter bit 20 */
+#define  CAN_F10R2_FB21                      ((uint32_t)0x00200000)        /*!< Filter bit 21 */
+#define  CAN_F10R2_FB22                      ((uint32_t)0x00400000)        /*!< Filter bit 22 */
+#define  CAN_F10R2_FB23                      ((uint32_t)0x00800000)        /*!< Filter bit 23 */
+#define  CAN_F10R2_FB24                      ((uint32_t)0x01000000)        /*!< Filter bit 24 */
+#define  CAN_F10R2_FB25                      ((uint32_t)0x02000000)        /*!< Filter bit 25 */
+#define  CAN_F10R2_FB26                      ((uint32_t)0x04000000)        /*!< Filter bit 26 */
+#define  CAN_F10R2_FB27                      ((uint32_t)0x08000000)        /*!< Filter bit 27 */
+#define  CAN_F10R2_FB28                      ((uint32_t)0x10000000)        /*!< Filter bit 28 */
+#define  CAN_F10R2_FB29                      ((uint32_t)0x20000000)        /*!< Filter bit 29 */
+#define  CAN_F10R2_FB30                      ((uint32_t)0x40000000)        /*!< Filter bit 30 */
+#define  CAN_F10R2_FB31                      ((uint32_t)0x80000000)        /*!< Filter bit 31 */
+
+/*******************  Bit definition for CAN_F11R2 register  ******************/
+#define  CAN_F11R2_FB0                       ((uint32_t)0x00000001)        /*!< Filter bit 0 */
+#define  CAN_F11R2_FB1                       ((uint32_t)0x00000002)        /*!< Filter bit 1 */
+#define  CAN_F11R2_FB2                       ((uint32_t)0x00000004)        /*!< Filter bit 2 */
+#define  CAN_F11R2_FB3                       ((uint32_t)0x00000008)        /*!< Filter bit 3 */
+#define  CAN_F11R2_FB4                       ((uint32_t)0x00000010)        /*!< Filter bit 4 */
+#define  CAN_F11R2_FB5                       ((uint32_t)0x00000020)        /*!< Filter bit 5 */
+#define  CAN_F11R2_FB6                       ((uint32_t)0x00000040)        /*!< Filter bit 6 */
+#define  CAN_F11R2_FB7                       ((uint32_t)0x00000080)        /*!< Filter bit 7 */
+#define  CAN_F11R2_FB8                       ((uint32_t)0x00000100)        /*!< Filter bit 8 */
+#define  CAN_F11R2_FB9                       ((uint32_t)0x00000200)        /*!< Filter bit 9 */
+#define  CAN_F11R2_FB10                      ((uint32_t)0x00000400)        /*!< Filter bit 10 */
+#define  CAN_F11R2_FB11                      ((uint32_t)0x00000800)        /*!< Filter bit 11 */
+#define  CAN_F11R2_FB12                      ((uint32_t)0x00001000)        /*!< Filter bit 12 */
+#define  CAN_F11R2_FB13                      ((uint32_t)0x00002000)        /*!< Filter bit 13 */
+#define  CAN_F11R2_FB14                      ((uint32_t)0x00004000)        /*!< Filter bit 14 */
+#define  CAN_F11R2_FB15                      ((uint32_t)0x00008000)        /*!< Filter bit 15 */
+#define  CAN_F11R2_FB16                      ((uint32_t)0x00010000)        /*!< Filter bit 16 */
+#define  CAN_F11R2_FB17                      ((uint32_t)0x00020000)        /*!< Filter bit 17 */
+#define  CAN_F11R2_FB18                      ((uint32_t)0x00040000)        /*!< Filter bit 18 */
+#define  CAN_F11R2_FB19                      ((uint32_t)0x00080000)        /*!< Filter bit 19 */
+#define  CAN_F11R2_FB20                      ((uint32_t)0x00100000)        /*!< Filter bit 20 */
+#define  CAN_F11R2_FB21                      ((uint32_t)0x00200000)        /*!< Filter bit 21 */
+#define  CAN_F11R2_FB22                      ((uint32_t)0x00400000)        /*!< Filter bit 22 */
+#define  CAN_F11R2_FB23                      ((uint32_t)0x00800000)        /*!< Filter bit 23 */
+#define  CAN_F11R2_FB24                      ((uint32_t)0x01000000)        /*!< Filter bit 24 */
+#define  CAN_F11R2_FB25                      ((uint32_t)0x02000000)        /*!< Filter bit 25 */
+#define  CAN_F11R2_FB26                      ((uint32_t)0x04000000)        /*!< Filter bit 26 */
+#define  CAN_F11R2_FB27                      ((uint32_t)0x08000000)        /*!< Filter bit 27 */
+#define  CAN_F11R2_FB28                      ((uint32_t)0x10000000)        /*!< Filter bit 28 */
+#define  CAN_F11R2_FB29                      ((uint32_t)0x20000000)        /*!< Filter bit 29 */
+#define  CAN_F11R2_FB30                      ((uint32_t)0x40000000)        /*!< Filter bit 30 */
+#define  CAN_F11R2_FB31                      ((uint32_t)0x80000000)        /*!< Filter bit 31 */
+
+/*******************  Bit definition for CAN_F12R2 register  ******************/
+#define  CAN_F12R2_FB0                       ((uint32_t)0x00000001)        /*!< Filter bit 0 */
+#define  CAN_F12R2_FB1                       ((uint32_t)0x00000002)        /*!< Filter bit 1 */
+#define  CAN_F12R2_FB2                       ((uint32_t)0x00000004)        /*!< Filter bit 2 */
+#define  CAN_F12R2_FB3                       ((uint32_t)0x00000008)        /*!< Filter bit 3 */
+#define  CAN_F12R2_FB4                       ((uint32_t)0x00000010)        /*!< Filter bit 4 */
+#define  CAN_F12R2_FB5                       ((uint32_t)0x00000020)        /*!< Filter bit 5 */
+#define  CAN_F12R2_FB6                       ((uint32_t)0x00000040)        /*!< Filter bit 6 */
+#define  CAN_F12R2_FB7                       ((uint32_t)0x00000080)        /*!< Filter bit 7 */
+#define  CAN_F12R2_FB8                       ((uint32_t)0x00000100)        /*!< Filter bit 8 */
+#define  CAN_F12R2_FB9                       ((uint32_t)0x00000200)        /*!< Filter bit 9 */
+#define  CAN_F12R2_FB10                      ((uint32_t)0x00000400)        /*!< Filter bit 10 */
+#define  CAN_F12R2_FB11                      ((uint32_t)0x00000800)        /*!< Filter bit 11 */
+#define  CAN_F12R2_FB12                      ((uint32_t)0x00001000)        /*!< Filter bit 12 */
+#define  CAN_F12R2_FB13                      ((uint32_t)0x00002000)        /*!< Filter bit 13 */
+#define  CAN_F12R2_FB14                      ((uint32_t)0x00004000)        /*!< Filter bit 14 */
+#define  CAN_F12R2_FB15                      ((uint32_t)0x00008000)        /*!< Filter bit 15 */
+#define  CAN_F12R2_FB16                      ((uint32_t)0x00010000)        /*!< Filter bit 16 */
+#define  CAN_F12R2_FB17                      ((uint32_t)0x00020000)        /*!< Filter bit 17 */
+#define  CAN_F12R2_FB18                      ((uint32_t)0x00040000)        /*!< Filter bit 18 */
+#define  CAN_F12R2_FB19                      ((uint32_t)0x00080000)        /*!< Filter bit 19 */
+#define  CAN_F12R2_FB20                      ((uint32_t)0x00100000)        /*!< Filter bit 20 */
+#define  CAN_F12R2_FB21                      ((uint32_t)0x00200000)        /*!< Filter bit 21 */
+#define  CAN_F12R2_FB22                      ((uint32_t)0x00400000)        /*!< Filter bit 22 */
+#define  CAN_F12R2_FB23                      ((uint32_t)0x00800000)        /*!< Filter bit 23 */
+#define  CAN_F12R2_FB24                      ((uint32_t)0x01000000)        /*!< Filter bit 24 */
+#define  CAN_F12R2_FB25                      ((uint32_t)0x02000000)        /*!< Filter bit 25 */
+#define  CAN_F12R2_FB26                      ((uint32_t)0x04000000)        /*!< Filter bit 26 */
+#define  CAN_F12R2_FB27                      ((uint32_t)0x08000000)        /*!< Filter bit 27 */
+#define  CAN_F12R2_FB28                      ((uint32_t)0x10000000)        /*!< Filter bit 28 */
+#define  CAN_F12R2_FB29                      ((uint32_t)0x20000000)        /*!< Filter bit 29 */
+#define  CAN_F12R2_FB30                      ((uint32_t)0x40000000)        /*!< Filter bit 30 */
+#define  CAN_F12R2_FB31                      ((uint32_t)0x80000000)        /*!< Filter bit 31 */
+
+/*******************  Bit definition for CAN_F13R2 register  ******************/
+#define  CAN_F13R2_FB0                       ((uint32_t)0x00000001)        /*!< Filter bit 0 */
+#define  CAN_F13R2_FB1                       ((uint32_t)0x00000002)        /*!< Filter bit 1 */
+#define  CAN_F13R2_FB2                       ((uint32_t)0x00000004)        /*!< Filter bit 2 */
+#define  CAN_F13R2_FB3                       ((uint32_t)0x00000008)        /*!< Filter bit 3 */
+#define  CAN_F13R2_FB4                       ((uint32_t)0x00000010)        /*!< Filter bit 4 */
+#define  CAN_F13R2_FB5                       ((uint32_t)0x00000020)        /*!< Filter bit 5 */
+#define  CAN_F13R2_FB6                       ((uint32_t)0x00000040)        /*!< Filter bit 6 */
+#define  CAN_F13R2_FB7                       ((uint32_t)0x00000080)        /*!< Filter bit 7 */
+#define  CAN_F13R2_FB8                       ((uint32_t)0x00000100)        /*!< Filter bit 8 */
+#define  CAN_F13R2_FB9                       ((uint32_t)0x00000200)        /*!< Filter bit 9 */
+#define  CAN_F13R2_FB10                      ((uint32_t)0x00000400)        /*!< Filter bit 10 */
+#define  CAN_F13R2_FB11                      ((uint32_t)0x00000800)        /*!< Filter bit 11 */
+#define  CAN_F13R2_FB12                      ((uint32_t)0x00001000)        /*!< Filter bit 12 */
+#define  CAN_F13R2_FB13                      ((uint32_t)0x00002000)        /*!< Filter bit 13 */
+#define  CAN_F13R2_FB14                      ((uint32_t)0x00004000)        /*!< Filter bit 14 */
+#define  CAN_F13R2_FB15                      ((uint32_t)0x00008000)        /*!< Filter bit 15 */
+#define  CAN_F13R2_FB16                      ((uint32_t)0x00010000)        /*!< Filter bit 16 */
+#define  CAN_F13R2_FB17                      ((uint32_t)0x00020000)        /*!< Filter bit 17 */
+#define  CAN_F13R2_FB18                      ((uint32_t)0x00040000)        /*!< Filter bit 18 */
+#define  CAN_F13R2_FB19                      ((uint32_t)0x00080000)        /*!< Filter bit 19 */
+#define  CAN_F13R2_FB20                      ((uint32_t)0x00100000)        /*!< Filter bit 20 */
+#define  CAN_F13R2_FB21                      ((uint32_t)0x00200000)        /*!< Filter bit 21 */
+#define  CAN_F13R2_FB22                      ((uint32_t)0x00400000)        /*!< Filter bit 22 */
+#define  CAN_F13R2_FB23                      ((uint32_t)0x00800000)        /*!< Filter bit 23 */
+#define  CAN_F13R2_FB24                      ((uint32_t)0x01000000)        /*!< Filter bit 24 */
+#define  CAN_F13R2_FB25                      ((uint32_t)0x02000000)        /*!< Filter bit 25 */
+#define  CAN_F13R2_FB26                      ((uint32_t)0x04000000)        /*!< Filter bit 26 */
+#define  CAN_F13R2_FB27                      ((uint32_t)0x08000000)        /*!< Filter bit 27 */
+#define  CAN_F13R2_FB28                      ((uint32_t)0x10000000)        /*!< Filter bit 28 */
+#define  CAN_F13R2_FB29                      ((uint32_t)0x20000000)        /*!< Filter bit 29 */
+#define  CAN_F13R2_FB30                      ((uint32_t)0x40000000)        /*!< Filter bit 30 */
+#define  CAN_F13R2_FB31                      ((uint32_t)0x80000000)        /*!< Filter bit 31 */
+
+/******************************************************************************/
+/*                                                                            */
+/*                        Serial Peripheral Interface                         */
+/*                                                                            */
+/******************************************************************************/
+
+/*******************  Bit definition for SPI_CR1 register  ********************/
+#define  SPI_CR1_CPHA                        ((uint16_t)0x0001)            /*!< Clock Phase */
+#define  SPI_CR1_CPOL                        ((uint16_t)0x0002)            /*!< Clock Polarity */
+#define  SPI_CR1_MSTR                        ((uint16_t)0x0004)            /*!< Master Selection */
+
+#define  SPI_CR1_BR                          ((uint16_t)0x0038)            /*!< BR[2:0] bits (Baud Rate Control) */
+#define  SPI_CR1_BR_0                        ((uint16_t)0x0008)            /*!< Bit 0 */
+#define  SPI_CR1_BR_1                        ((uint16_t)0x0010)            /*!< Bit 1 */
+#define  SPI_CR1_BR_2                        ((uint16_t)0x0020)            /*!< Bit 2 */
+
+#define  SPI_CR1_SPE                         ((uint16_t)0x0040)            /*!< SPI Enable */
+#define  SPI_CR1_LSBFIRST                    ((uint16_t)0x0080)            /*!< Frame Format */
+#define  SPI_CR1_SSI                         ((uint16_t)0x0100)            /*!< Internal slave select */
+#define  SPI_CR1_SSM                         ((uint16_t)0x0200)            /*!< Software slave management */
+#define  SPI_CR1_RXONLY                      ((uint16_t)0x0400)            /*!< Receive only */
+#define  SPI_CR1_DFF                         ((uint16_t)0x0800)            /*!< Data Frame Format */
+#define  SPI_CR1_CRCNEXT                     ((uint16_t)0x1000)            /*!< Transmit CRC next */
+#define  SPI_CR1_CRCEN                       ((uint16_t)0x2000)            /*!< Hardware CRC calculation enable */
+#define  SPI_CR1_BIDIOE                      ((uint16_t)0x4000)            /*!< Output enable in bidirectional mode */
+#define  SPI_CR1_BIDIMODE                    ((uint16_t)0x8000)            /*!< Bidirectional data mode enable */
+
+/*******************  Bit definition for SPI_CR2 register  ********************/
+#define  SPI_CR2_RXDMAEN                     ((uint8_t)0x01)               /*!< Rx Buffer DMA Enable */
+#define  SPI_CR2_TXDMAEN                     ((uint8_t)0x02)               /*!< Tx Buffer DMA Enable */
+#define  SPI_CR2_SSOE                        ((uint8_t)0x04)               /*!< SS Output Enable */
+#define  SPI_CR2_ERRIE                       ((uint8_t)0x20)               /*!< Error Interrupt Enable */
+#define  SPI_CR2_RXNEIE                      ((uint8_t)0x40)               /*!< RX buffer Not Empty Interrupt Enable */
+#define  SPI_CR2_TXEIE                       ((uint8_t)0x80)               /*!< Tx buffer Empty Interrupt Enable */
+
+/********************  Bit definition for SPI_SR register  ********************/
+#define  SPI_SR_RXNE                         ((uint8_t)0x01)               /*!< Receive buffer Not Empty */
+#define  SPI_SR_TXE                          ((uint8_t)0x02)               /*!< Transmit buffer Empty */
+#define  SPI_SR_CHSIDE                       ((uint8_t)0x04)               /*!< Channel side */
+#define  SPI_SR_UDR                          ((uint8_t)0x08)               /*!< Underrun flag */
+#define  SPI_SR_CRCERR                       ((uint8_t)0x10)               /*!< CRC Error flag */
+#define  SPI_SR_MODF                         ((uint8_t)0x20)               /*!< Mode fault */
+#define  SPI_SR_OVR                          ((uint8_t)0x40)               /*!< Overrun flag */
+#define  SPI_SR_BSY                          ((uint8_t)0x80)               /*!< Busy flag */
+
+/********************  Bit definition for SPI_DR register  ********************/
+#define  SPI_DR_DR                           ((uint16_t)0xFFFF)            /*!< Data Register */
+
+/*******************  Bit definition for SPI_CRCPR register  ******************/
+#define  SPI_CRCPR_CRCPOLY                   ((uint16_t)0xFFFF)            /*!< CRC polynomial register */
+
+/******************  Bit definition for SPI_RXCRCR register  ******************/
+#define  SPI_RXCRCR_RXCRC                    ((uint16_t)0xFFFF)            /*!< Rx CRC Register */
+
+/******************  Bit definition for SPI_TXCRCR register  ******************/
+#define  SPI_TXCRCR_TXCRC                    ((uint16_t)0xFFFF)            /*!< Tx CRC Register */
+
+/******************  Bit definition for SPI_I2SCFGR register  *****************/
+#define  SPI_I2SCFGR_CHLEN                   ((uint16_t)0x0001)            /*!< Channel length (number of bits per audio channel) */
+
+#define  SPI_I2SCFGR_DATLEN                  ((uint16_t)0x0006)            /*!< DATLEN[1:0] bits (Data length to be transferred) */
+#define  SPI_I2SCFGR_DATLEN_0                ((uint16_t)0x0002)            /*!< Bit 0 */
+#define  SPI_I2SCFGR_DATLEN_1                ((uint16_t)0x0004)            /*!< Bit 1 */
+
+#define  SPI_I2SCFGR_CKPOL                   ((uint16_t)0x0008)            /*!< steady state clock polarity */
+
+#define  SPI_I2SCFGR_I2SSTD                  ((uint16_t)0x0030)            /*!< I2SSTD[1:0] bits (I2S standard selection) */
+#define  SPI_I2SCFGR_I2SSTD_0                ((uint16_t)0x0010)            /*!< Bit 0 */
+#define  SPI_I2SCFGR_I2SSTD_1                ((uint16_t)0x0020)            /*!< Bit 1 */
+
+#define  SPI_I2SCFGR_PCMSYNC                 ((uint16_t)0x0080)            /*!< PCM frame synchronization */
+
+#define  SPI_I2SCFGR_I2SCFG                  ((uint16_t)0x0300)            /*!< I2SCFG[1:0] bits (I2S configuration mode) */
+#define  SPI_I2SCFGR_I2SCFG_0                ((uint16_t)0x0100)            /*!< Bit 0 */
+#define  SPI_I2SCFGR_I2SCFG_1                ((uint16_t)0x0200)            /*!< Bit 1 */
+
+#define  SPI_I2SCFGR_I2SE                    ((uint16_t)0x0400)            /*!< I2S Enable */
+#define  SPI_I2SCFGR_I2SMOD                  ((uint16_t)0x0800)            /*!< I2S mode selection */
+
+/******************  Bit definition for SPI_I2SPR register  *******************/
+#define  SPI_I2SPR_I2SDIV                    ((uint16_t)0x00FF)            /*!< I2S Linear prescaler */
+#define  SPI_I2SPR_ODD                       ((uint16_t)0x0100)            /*!< Odd factor for the prescaler */
+#define  SPI_I2SPR_MCKOE                     ((uint16_t)0x0200)            /*!< Master Clock Output Enable */
+
+/******************************************************************************/
+/*                                                                            */
+/*                      Inter-integrated Circuit Interface                    */
+/*                                                                            */
+/******************************************************************************/
+
+/*******************  Bit definition for I2C_CR1 register  ********************/
+#define  I2C_CR1_PE                          ((uint16_t)0x0001)            /*!< Peripheral Enable */
+#define  I2C_CR1_SMBUS                       ((uint16_t)0x0002)            /*!< SMBus Mode */
+#define  I2C_CR1_SMBTYPE                     ((uint16_t)0x0008)            /*!< SMBus Type */
+#define  I2C_CR1_ENARP                       ((uint16_t)0x0010)            /*!< ARP Enable */
+#define  I2C_CR1_ENPEC                       ((uint16_t)0x0020)            /*!< PEC Enable */
+#define  I2C_CR1_ENGC                        ((uint16_t)0x0040)            /*!< General Call Enable */
+#define  I2C_CR1_NOSTRETCH                   ((uint16_t)0x0080)            /*!< Clock Stretching Disable (Slave mode) */
+#define  I2C_CR1_START                       ((uint16_t)0x0100)            /*!< Start Generation */
+#define  I2C_CR1_STOP                        ((uint16_t)0x0200)            /*!< Stop Generation */
+#define  I2C_CR1_ACK                         ((uint16_t)0x0400)            /*!< Acknowledge Enable */
+#define  I2C_CR1_POS                         ((uint16_t)0x0800)            /*!< Acknowledge/PEC Position (for data reception) */
+#define  I2C_CR1_PEC                         ((uint16_t)0x1000)            /*!< Packet Error Checking */
+#define  I2C_CR1_ALERT                       ((uint16_t)0x2000)            /*!< SMBus Alert */
+#define  I2C_CR1_SWRST                       ((uint16_t)0x8000)            /*!< Software Reset */
+
+/*******************  Bit definition for I2C_CR2 register  ********************/
+#define  I2C_CR2_FREQ                        ((uint16_t)0x003F)            /*!< FREQ[5:0] bits (Peripheral Clock Frequency) */
+#define  I2C_CR2_FREQ_0                      ((uint16_t)0x0001)            /*!< Bit 0 */
+#define  I2C_CR2_FREQ_1                      ((uint16_t)0x0002)            /*!< Bit 1 */
+#define  I2C_CR2_FREQ_2                      ((uint16_t)0x0004)            /*!< Bit 2 */
+#define  I2C_CR2_FREQ_3                      ((uint16_t)0x0008)            /*!< Bit 3 */
+#define  I2C_CR2_FREQ_4                      ((uint16_t)0x0010)            /*!< Bit 4 */
+#define  I2C_CR2_FREQ_5                      ((uint16_t)0x0020)            /*!< Bit 5 */
+
+#define  I2C_CR2_ITERREN                     ((uint16_t)0x0100)            /*!< Error Interrupt Enable */
+#define  I2C_CR2_ITEVTEN                     ((uint16_t)0x0200)            /*!< Event Interrupt Enable */
+#define  I2C_CR2_ITBUFEN                     ((uint16_t)0x0400)            /*!< Buffer Interrupt Enable */
+#define  I2C_CR2_DMAEN                       ((uint16_t)0x0800)            /*!< DMA Requests Enable */
+#define  I2C_CR2_LAST                        ((uint16_t)0x1000)            /*!< DMA Last Transfer */
+
+/*******************  Bit definition for I2C_OAR1 register  *******************/
+#define  I2C_OAR1_ADD1_7                     ((uint16_t)0x00FE)            /*!< Interface Address */
+#define  I2C_OAR1_ADD8_9                     ((uint16_t)0x0300)            /*!< Interface Address */
+
+#define  I2C_OAR1_ADD0                       ((uint16_t)0x0001)            /*!< Bit 0 */
+#define  I2C_OAR1_ADD1                       ((uint16_t)0x0002)            /*!< Bit 1 */
+#define  I2C_OAR1_ADD2                       ((uint16_t)0x0004)            /*!< Bit 2 */
+#define  I2C_OAR1_ADD3                       ((uint16_t)0x0008)            /*!< Bit 3 */
+#define  I2C_OAR1_ADD4                       ((uint16_t)0x0010)            /*!< Bit 4 */
+#define  I2C_OAR1_ADD5                       ((uint16_t)0x0020)            /*!< Bit 5 */
+#define  I2C_OAR1_ADD6                       ((uint16_t)0x0040)            /*!< Bit 6 */
+#define  I2C_OAR1_ADD7                       ((uint16_t)0x0080)            /*!< Bit 7 */
+#define  I2C_OAR1_ADD8                       ((uint16_t)0x0100)            /*!< Bit 8 */
+#define  I2C_OAR1_ADD9                       ((uint16_t)0x0200)            /*!< Bit 9 */
+
+#define  I2C_OAR1_ADDMODE                    ((uint16_t)0x8000)            /*!< Addressing Mode (Slave mode) */
+
+/*******************  Bit definition for I2C_OAR2 register  *******************/
+#define  I2C_OAR2_ENDUAL                     ((uint8_t)0x01)               /*!< Dual addressing mode enable */
+#define  I2C_OAR2_ADD2                       ((uint8_t)0xFE)               /*!< Interface address */
+
+/********************  Bit definition for I2C_DR register  ********************/
+#define  I2C_DR_DR                           ((uint8_t)0xFF)               /*!< 8-bit Data Register */
+
+/*******************  Bit definition for I2C_SR1 register  ********************/
+#define  I2C_SR1_SB                          ((uint16_t)0x0001)            /*!< Start Bit (Master mode) */
+#define  I2C_SR1_ADDR                        ((uint16_t)0x0002)            /*!< Address sent (master mode)/matched (slave mode) */
+#define  I2C_SR1_BTF                         ((uint16_t)0x0004)            /*!< Byte Transfer Finished */
+#define  I2C_SR1_ADD10                       ((uint16_t)0x0008)            /*!< 10-bit header sent (Master mode) */
+#define  I2C_SR1_STOPF                       ((uint16_t)0x0010)            /*!< Stop detection (Slave mode) */
+#define  I2C_SR1_RXNE                        ((uint16_t)0x0040)            /*!< Data Register not Empty (receivers) */
+#define  I2C_SR1_TXE                         ((uint16_t)0x0080)            /*!< Data Register Empty (transmitters) */
+#define  I2C_SR1_BERR                        ((uint16_t)0x0100)            /*!< Bus Error */
+#define  I2C_SR1_ARLO                        ((uint16_t)0x0200)            /*!< Arbitration Lost (master mode) */
+#define  I2C_SR1_AF                          ((uint16_t)0x0400)            /*!< Acknowledge Failure */
+#define  I2C_SR1_OVR                         ((uint16_t)0x0800)            /*!< Overrun/Underrun */
+#define  I2C_SR1_PECERR                      ((uint16_t)0x1000)            /*!< PEC Error in reception */
+#define  I2C_SR1_TIMEOUT                     ((uint16_t)0x4000)            /*!< Timeout or Tlow Error */
+#define  I2C_SR1_SMBALERT                    ((uint16_t)0x8000)            /*!< SMBus Alert */
+
+/*******************  Bit definition for I2C_SR2 register  ********************/
+#define  I2C_SR2_MSL                         ((uint16_t)0x0001)            /*!< Master/Slave */
+#define  I2C_SR2_BUSY                        ((uint16_t)0x0002)            /*!< Bus Busy */
+#define  I2C_SR2_TRA                         ((uint16_t)0x0004)            /*!< Transmitter/Receiver */
+#define  I2C_SR2_GENCALL                     ((uint16_t)0x0010)            /*!< General Call Address (Slave mode) */
+#define  I2C_SR2_SMBDEFAULT                  ((uint16_t)0x0020)            /*!< SMBus Device Default Address (Slave mode) */
+#define  I2C_SR2_SMBHOST                     ((uint16_t)0x0040)            /*!< SMBus Host Header (Slave mode) */
+#define  I2C_SR2_DUALF                       ((uint16_t)0x0080)            /*!< Dual Flag (Slave mode) */
+#define  I2C_SR2_PEC                         ((uint16_t)0xFF00)            /*!< Packet Error Checking Register */
+
+/*******************  Bit definition for I2C_CCR register  ********************/
+#define  I2C_CCR_CCR                         ((uint16_t)0x0FFF)            /*!< Clock Control Register in Fast/Standard mode (Master mode) */
+#define  I2C_CCR_DUTY                        ((uint16_t)0x4000)            /*!< Fast Mode Duty Cycle */
+#define  I2C_CCR_FS                          ((uint16_t)0x8000)            /*!< I2C Master Mode Selection */
+
+/******************  Bit definition for I2C_TRISE register  *******************/
+#define  I2C_TRISE_TRISE                     ((uint8_t)0x3F)               /*!< Maximum Rise Time in Fast/Standard mode (Master mode) */
+
+/******************************************************************************/
+/*                                                                            */
+/*         Universal Synchronous Asynchronous Receiver Transmitter            */
+/*                                                                            */
+/******************************************************************************/
+
+/*******************  Bit definition for USART_SR register  *******************/
+#define  USART_SR_PE                         ((uint16_t)0x0001)            /*!< Parity Error */
+#define  USART_SR_FE                         ((uint16_t)0x0002)            /*!< Framing Error */
+#define  USART_SR_NE                         ((uint16_t)0x0004)            /*!< Noise Error Flag */
+#define  USART_SR_ORE                        ((uint16_t)0x0008)            /*!< OverRun Error */
+#define  USART_SR_IDLE                       ((uint16_t)0x0010)            /*!< IDLE line detected */
+#define  USART_SR_RXNE                       ((uint16_t)0x0020)            /*!< Read Data Register Not Empty */
+#define  USART_SR_TC                         ((uint16_t)0x0040)            /*!< Transmission Complete */
+#define  USART_SR_TXE                        ((uint16_t)0x0080)            /*!< Transmit Data Register Empty */
+#define  USART_SR_LBD                        ((uint16_t)0x0100)            /*!< LIN Break Detection Flag */
+#define  USART_SR_CTS                        ((uint16_t)0x0200)            /*!< CTS Flag */
+
+/*******************  Bit definition for USART_DR register  *******************/
+#define  USART_DR_DR                         ((uint16_t)0x01FF)            /*!< Data value */
+
+/******************  Bit definition for USART_BRR register  *******************/
+#define  USART_BRR_DIV_Fraction              ((uint16_t)0x000F)            /*!< Fraction of USARTDIV */
+#define  USART_BRR_DIV_Mantissa              ((uint16_t)0xFFF0)            /*!< Mantissa of USARTDIV */
+
+/******************  Bit definition for USART_CR1 register  *******************/
+#define  USART_CR1_SBK                       ((uint16_t)0x0001)            /*!< Send Break */
+#define  USART_CR1_RWU                       ((uint16_t)0x0002)            /*!< Receiver wakeup */
+#define  USART_CR1_RE                        ((uint16_t)0x0004)            /*!< Receiver Enable */
+#define  USART_CR1_TE                        ((uint16_t)0x0008)            /*!< Transmitter Enable */
+#define  USART_CR1_IDLEIE                    ((uint16_t)0x0010)            /*!< IDLE Interrupt Enable */
+#define  USART_CR1_RXNEIE                    ((uint16_t)0x0020)            /*!< RXNE Interrupt Enable */
+#define  USART_CR1_TCIE                      ((uint16_t)0x0040)            /*!< Transmission Complete Interrupt Enable */
+#define  USART_CR1_TXEIE                     ((uint16_t)0x0080)            /*!< PE Interrupt Enable */
+#define  USART_CR1_PEIE                      ((uint16_t)0x0100)            /*!< PE Interrupt Enable */
+#define  USART_CR1_PS                        ((uint16_t)0x0200)            /*!< Parity Selection */
+#define  USART_CR1_PCE                       ((uint16_t)0x0400)            /*!< Parity Control Enable */
+#define  USART_CR1_WAKE                      ((uint16_t)0x0800)            /*!< Wakeup method */
+#define  USART_CR1_M                         ((uint16_t)0x1000)            /*!< Word length */
+#define  USART_CR1_UE                        ((uint16_t)0x2000)            /*!< USART Enable */
+#define  USART_CR1_OVER8                     ((uint16_t)0x8000)            /*!< USART Oversmapling 8-bits */
+
+/******************  Bit definition for USART_CR2 register  *******************/
+#define  USART_CR2_ADD                       ((uint16_t)0x000F)            /*!< Address of the USART node */
+#define  USART_CR2_LBDL                      ((uint16_t)0x0020)            /*!< LIN Break Detection Length */
+#define  USART_CR2_LBDIE                     ((uint16_t)0x0040)            /*!< LIN Break Detection Interrupt Enable */
+#define  USART_CR2_LBCL                      ((uint16_t)0x0100)            /*!< Last Bit Clock pulse */
+#define  USART_CR2_CPHA                      ((uint16_t)0x0200)            /*!< Clock Phase */
+#define  USART_CR2_CPOL                      ((uint16_t)0x0400)            /*!< Clock Polarity */
+#define  USART_CR2_CLKEN                     ((uint16_t)0x0800)            /*!< Clock Enable */
+
+#define  USART_CR2_STOP                      ((uint16_t)0x3000)            /*!< STOP[1:0] bits (STOP bits) */
+#define  USART_CR2_STOP_0                    ((uint16_t)0x1000)            /*!< Bit 0 */
+#define  USART_CR2_STOP_1                    ((uint16_t)0x2000)            /*!< Bit 1 */
+
+#define  USART_CR2_LINEN                     ((uint16_t)0x4000)            /*!< LIN mode enable */
+
+/******************  Bit definition for USART_CR3 register  *******************/
+#define  USART_CR3_EIE                       ((uint16_t)0x0001)            /*!< Error Interrupt Enable */
+#define  USART_CR3_IREN                      ((uint16_t)0x0002)            /*!< IrDA mode Enable */
+#define  USART_CR3_IRLP                      ((uint16_t)0x0004)            /*!< IrDA Low-Power */
+#define  USART_CR3_HDSEL                     ((uint16_t)0x0008)            /*!< Half-Duplex Selection */
+#define  USART_CR3_NACK                      ((uint16_t)0x0010)            /*!< Smartcard NACK enable */
+#define  USART_CR3_SCEN                      ((uint16_t)0x0020)            /*!< Smartcard mode enable */
+#define  USART_CR3_DMAR                      ((uint16_t)0x0040)            /*!< DMA Enable Receiver */
+#define  USART_CR3_DMAT                      ((uint16_t)0x0080)            /*!< DMA Enable Transmitter */
+#define  USART_CR3_RTSE                      ((uint16_t)0x0100)            /*!< RTS Enable */
+#define  USART_CR3_CTSE                      ((uint16_t)0x0200)            /*!< CTS Enable */
+#define  USART_CR3_CTSIE                     ((uint16_t)0x0400)            /*!< CTS Interrupt Enable */
+#define  USART_CR3_ONEBIT                    ((uint16_t)0x0800)            /*!< One Bit method */
+
+/******************  Bit definition for USART_GTPR register  ******************/
+#define  USART_GTPR_PSC                      ((uint16_t)0x00FF)            /*!< PSC[7:0] bits (Prescaler value) */
+#define  USART_GTPR_PSC_0                    ((uint16_t)0x0001)            /*!< Bit 0 */
+#define  USART_GTPR_PSC_1                    ((uint16_t)0x0002)            /*!< Bit 1 */
+#define  USART_GTPR_PSC_2                    ((uint16_t)0x0004)            /*!< Bit 2 */
+#define  USART_GTPR_PSC_3                    ((uint16_t)0x0008)            /*!< Bit 3 */
+#define  USART_GTPR_PSC_4                    ((uint16_t)0x0010)            /*!< Bit 4 */
+#define  USART_GTPR_PSC_5                    ((uint16_t)0x0020)            /*!< Bit 5 */
+#define  USART_GTPR_PSC_6                    ((uint16_t)0x0040)            /*!< Bit 6 */
+#define  USART_GTPR_PSC_7                    ((uint16_t)0x0080)            /*!< Bit 7 */
+
+#define  USART_GTPR_GT                       ((uint16_t)0xFF00)            /*!< Guard time value */
+
+/******************************************************************************/
+/*                                                                            */
+/*                                 Debug MCU                                  */
+/*                                                                            */
+/******************************************************************************/
+
+/****************  Bit definition for DBGMCU_IDCODE register  *****************/
+#define  DBGMCU_IDCODE_DEV_ID                ((uint32_t)0x00000FFF)        /*!< Device Identifier */
+
+#define  DBGMCU_IDCODE_REV_ID                ((uint32_t)0xFFFF0000)        /*!< REV_ID[15:0] bits (Revision Identifier) */
+#define  DBGMCU_IDCODE_REV_ID_0              ((uint32_t)0x00010000)        /*!< Bit 0 */
+#define  DBGMCU_IDCODE_REV_ID_1              ((uint32_t)0x00020000)        /*!< Bit 1 */
+#define  DBGMCU_IDCODE_REV_ID_2              ((uint32_t)0x00040000)        /*!< Bit 2 */
+#define  DBGMCU_IDCODE_REV_ID_3              ((uint32_t)0x00080000)        /*!< Bit 3 */
+#define  DBGMCU_IDCODE_REV_ID_4              ((uint32_t)0x00100000)        /*!< Bit 4 */
+#define  DBGMCU_IDCODE_REV_ID_5              ((uint32_t)0x00200000)        /*!< Bit 5 */
+#define  DBGMCU_IDCODE_REV_ID_6              ((uint32_t)0x00400000)        /*!< Bit 6 */
+#define  DBGMCU_IDCODE_REV_ID_7              ((uint32_t)0x00800000)        /*!< Bit 7 */
+#define  DBGMCU_IDCODE_REV_ID_8              ((uint32_t)0x01000000)        /*!< Bit 8 */
+#define  DBGMCU_IDCODE_REV_ID_9              ((uint32_t)0x02000000)        /*!< Bit 9 */
+#define  DBGMCU_IDCODE_REV_ID_10             ((uint32_t)0x04000000)        /*!< Bit 10 */
+#define  DBGMCU_IDCODE_REV_ID_11             ((uint32_t)0x08000000)        /*!< Bit 11 */
+#define  DBGMCU_IDCODE_REV_ID_12             ((uint32_t)0x10000000)        /*!< Bit 12 */
+#define  DBGMCU_IDCODE_REV_ID_13             ((uint32_t)0x20000000)        /*!< Bit 13 */
+#define  DBGMCU_IDCODE_REV_ID_14             ((uint32_t)0x40000000)        /*!< Bit 14 */
+#define  DBGMCU_IDCODE_REV_ID_15             ((uint32_t)0x80000000)        /*!< Bit 15 */
+
+/******************  Bit definition for DBGMCU_CR register  *******************/
+#define  DBGMCU_CR_DBG_SLEEP                 ((uint32_t)0x00000001)        /*!< Debug Sleep Mode */
+#define  DBGMCU_CR_DBG_STOP                  ((uint32_t)0x00000002)        /*!< Debug Stop Mode */
+#define  DBGMCU_CR_DBG_STANDBY               ((uint32_t)0x00000004)        /*!< Debug Standby mode */
+#define  DBGMCU_CR_TRACE_IOEN                ((uint32_t)0x00000020)        /*!< Trace Pin Assignment Control */
+
+#define  DBGMCU_CR_TRACE_MODE                ((uint32_t)0x000000C0)        /*!< TRACE_MODE[1:0] bits (Trace Pin Assignment Control) */
+#define  DBGMCU_CR_TRACE_MODE_0              ((uint32_t)0x00000040)        /*!< Bit 0 */
+#define  DBGMCU_CR_TRACE_MODE_1              ((uint32_t)0x00000080)        /*!< Bit 1 */
+
+#define  DBGMCU_CR_DBG_IWDG_STOP             ((uint32_t)0x00000100)        /*!< Debug Independent Watchdog stopped when Core is halted */
+#define  DBGMCU_CR_DBG_WWDG_STOP             ((uint32_t)0x00000200)        /*!< Debug Window Watchdog stopped when Core is halted */
+#define  DBGMCU_CR_DBG_TIM1_STOP             ((uint32_t)0x00000400)        /*!< TIM1 counter stopped when core is halted */
+#define  DBGMCU_CR_DBG_TIM2_STOP             ((uint32_t)0x00000800)        /*!< TIM2 counter stopped when core is halted */
+#define  DBGMCU_CR_DBG_TIM3_STOP             ((uint32_t)0x00001000)        /*!< TIM3 counter stopped when core is halted */
+#define  DBGMCU_CR_DBG_TIM4_STOP             ((uint32_t)0x00002000)        /*!< TIM4 counter stopped when core is halted */
+#define  DBGMCU_CR_DBG_CAN1_STOP             ((uint32_t)0x00004000)        /*!< Debug CAN1 stopped when Core is halted */
+#define  DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT    ((uint32_t)0x00008000)        /*!< SMBUS timeout mode stopped when Core is halted */
+#define  DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT    ((uint32_t)0x00010000)        /*!< SMBUS timeout mode stopped when Core is halted */
+#define  DBGMCU_CR_DBG_TIM8_STOP             ((uint32_t)0x00020000)        /*!< TIM8 counter stopped when core is halted */
+#define  DBGMCU_CR_DBG_TIM5_STOP             ((uint32_t)0x00040000)        /*!< TIM5 counter stopped when core is halted */
+#define  DBGMCU_CR_DBG_TIM6_STOP             ((uint32_t)0x00080000)        /*!< TIM6 counter stopped when core is halted */
+#define  DBGMCU_CR_DBG_TIM7_STOP             ((uint32_t)0x00100000)        /*!< TIM7 counter stopped when core is halted */
+#define  DBGMCU_CR_DBG_CAN2_STOP             ((uint32_t)0x00200000)        /*!< Debug CAN2 stopped when Core is halted */
+#define  DBGMCU_CR_DBG_TIM15_STOP            ((uint32_t)0x00400000)        /*!< Debug TIM15 stopped when Core is halted */
+#define  DBGMCU_CR_DBG_TIM16_STOP            ((uint32_t)0x00800000)        /*!< Debug TIM16 stopped when Core is halted */
+#define  DBGMCU_CR_DBG_TIM17_STOP            ((uint32_t)0x01000000)        /*!< Debug TIM17 stopped when Core is halted */
+#define  DBGMCU_CR_DBG_TIM12_STOP            ((uint32_t)0x02000000)        /*!< Debug TIM12 stopped when Core is halted */
+#define  DBGMCU_CR_DBG_TIM13_STOP            ((uint32_t)0x04000000)        /*!< Debug TIM13 stopped when Core is halted */
+#define  DBGMCU_CR_DBG_TIM14_STOP            ((uint32_t)0x08000000)        /*!< Debug TIM14 stopped when Core is halted */
+#define  DBGMCU_CR_DBG_TIM9_STOP             ((uint32_t)0x10000000)        /*!< Debug TIM9 stopped when Core is halted */
+#define  DBGMCU_CR_DBG_TIM10_STOP            ((uint32_t)0x20000000)        /*!< Debug TIM10 stopped when Core is halted */
+#define  DBGMCU_CR_DBG_TIM11_STOP            ((uint32_t)0x40000000)        /*!< Debug TIM11 stopped when Core is halted */
+
+/******************************************************************************/
+/*                                                                            */
+/*                      FLASH and Option Bytes Registers                      */
+/*                                                                            */
+/******************************************************************************/
+
+/*******************  Bit definition for FLASH_ACR register  ******************/
+#define  FLASH_ACR_LATENCY                   ((uint8_t)0x03)               /*!< LATENCY[2:0] bits (Latency) */
+#define  FLASH_ACR_LATENCY_0                 ((uint8_t)0x00)               /*!< Bit 0 */
+#define  FLASH_ACR_LATENCY_1                 ((uint8_t)0x01)               /*!< Bit 0 */
+#define  FLASH_ACR_LATENCY_2                 ((uint8_t)0x02)               /*!< Bit 1 */
+
+#define  FLASH_ACR_HLFCYA                    ((uint8_t)0x08)               /*!< Flash Half Cycle Access Enable */
+#define  FLASH_ACR_PRFTBE                    ((uint8_t)0x10)               /*!< Prefetch Buffer Enable */
+#define  FLASH_ACR_PRFTBS                    ((uint8_t)0x20)               /*!< Prefetch Buffer Status */
+
+/******************  Bit definition for FLASH_KEYR register  ******************/
+#define  FLASH_KEYR_FKEYR                    ((uint32_t)0xFFFFFFFF)        /*!< FPEC Key */
+
+/*****************  Bit definition for FLASH_OPTKEYR register  ****************/
+#define  FLASH_OPTKEYR_OPTKEYR               ((uint32_t)0xFFFFFFFF)        /*!< Option Byte Key */
+
+/******************  Bit definition for FLASH_SR register  *******************/
+#define  FLASH_SR_BSY                        ((uint8_t)0x01)               /*!< Busy */
+#define  FLASH_SR_PGERR                      ((uint8_t)0x04)               /*!< Programming Error */
+#define  FLASH_SR_WRPRTERR                   ((uint8_t)0x10)               /*!< Write Protection Error */
+#define  FLASH_SR_EOP                        ((uint8_t)0x20)               /*!< End of operation */
+
+/*******************  Bit definition for FLASH_CR register  *******************/
+#define  FLASH_CR_PG                         ((uint16_t)0x0001)            /*!< Programming */
+#define  FLASH_CR_PER                        ((uint16_t)0x0002)            /*!< Page Erase */
+#define  FLASH_CR_MER                        ((uint16_t)0x0004)            /*!< Mass Erase */
+#define  FLASH_CR_OPTPG                      ((uint16_t)0x0010)            /*!< Option Byte Programming */
+#define  FLASH_CR_OPTER                      ((uint16_t)0x0020)            /*!< Option Byte Erase */
+#define  FLASH_CR_STRT                       ((uint16_t)0x0040)            /*!< Start */
+#define  FLASH_CR_LOCK                       ((uint16_t)0x0080)            /*!< Lock */
+#define  FLASH_CR_OPTWRE                     ((uint16_t)0x0200)            /*!< Option Bytes Write Enable */
+#define  FLASH_CR_ERRIE                      ((uint16_t)0x0400)            /*!< Error Interrupt Enable */
+#define  FLASH_CR_EOPIE                      ((uint16_t)0x1000)            /*!< End of operation interrupt enable */
+
+/*******************  Bit definition for FLASH_AR register  *******************/
+#define  FLASH_AR_FAR                        ((uint32_t)0xFFFFFFFF)        /*!< Flash Address */
+
+/******************  Bit definition for FLASH_OBR register  *******************/
+#define  FLASH_OBR_OPTERR                    ((uint16_t)0x0001)            /*!< Option Byte Error */
+#define  FLASH_OBR_RDPRT                     ((uint16_t)0x0002)            /*!< Read protection */
+
+#define  FLASH_OBR_USER                      ((uint16_t)0x03FC)            /*!< User Option Bytes */
+#define  FLASH_OBR_WDG_SW                    ((uint16_t)0x0004)            /*!< WDG_SW */
+#define  FLASH_OBR_nRST_STOP                 ((uint16_t)0x0008)            /*!< nRST_STOP */
+#define  FLASH_OBR_nRST_STDBY                ((uint16_t)0x0010)            /*!< nRST_STDBY */
+#define  FLASH_OBR_BFB2                      ((uint16_t)0x0020)            /*!< BFB2 */
+
+/******************  Bit definition for FLASH_WRPR register  ******************/
+#define  FLASH_WRPR_WRP                        ((uint32_t)0xFFFFFFFF)        /*!< Write Protect */
+
+/*----------------------------------------------------------------------------*/
+
+/******************  Bit definition for FLASH_RDP register  *******************/
+#define  FLASH_RDP_RDP                       ((uint32_t)0x000000FF)        /*!< Read protection option byte */
+#define  FLASH_RDP_nRDP                      ((uint32_t)0x0000FF00)        /*!< Read protection complemented option byte */
+
+/******************  Bit definition for FLASH_USER register  ******************/
+#define  FLASH_USER_USER                     ((uint32_t)0x00FF0000)        /*!< User option byte */
+#define  FLASH_USER_nUSER                    ((uint32_t)0xFF000000)        /*!< User complemented option byte */
+
+/******************  Bit definition for FLASH_Data0 register  *****************/
+#define  FLASH_Data0_Data0                   ((uint32_t)0x000000FF)        /*!< User data storage option byte */
+#define  FLASH_Data0_nData0                  ((uint32_t)0x0000FF00)        /*!< User data storage complemented option byte */
+
+/******************  Bit definition for FLASH_Data1 register  *****************/
+#define  FLASH_Data1_Data1                   ((uint32_t)0x00FF0000)        /*!< User data storage option byte */
+#define  FLASH_Data1_nData1                  ((uint32_t)0xFF000000)        /*!< User data storage complemented option byte */
+
+/******************  Bit definition for FLASH_WRP0 register  ******************/
+#define  FLASH_WRP0_WRP0                     ((uint32_t)0x000000FF)        /*!< Flash memory write protection option bytes */
+#define  FLASH_WRP0_nWRP0                    ((uint32_t)0x0000FF00)        /*!< Flash memory write protection complemented option bytes */
+
+/******************  Bit definition for FLASH_WRP1 register  ******************/
+#define  FLASH_WRP1_WRP1                     ((uint32_t)0x00FF0000)        /*!< Flash memory write protection option bytes */
+#define  FLASH_WRP1_nWRP1                    ((uint32_t)0xFF000000)        /*!< Flash memory write protection complemented option bytes */
+
+/******************  Bit definition for FLASH_WRP2 register  ******************/
+#define  FLASH_WRP2_WRP2                     ((uint32_t)0x000000FF)        /*!< Flash memory write protection option bytes */
+#define  FLASH_WRP2_nWRP2                    ((uint32_t)0x0000FF00)        /*!< Flash memory write protection complemented option bytes */
+
+/******************  Bit definition for FLASH_WRP3 register  ******************/
+#define  FLASH_WRP3_WRP3                     ((uint32_t)0x00FF0000)        /*!< Flash memory write protection option bytes */
+#define  FLASH_WRP3_nWRP3                    ((uint32_t)0xFF000000)        /*!< Flash memory write protection complemented option bytes */
+
+#ifdef STM32F10X_CL
+/******************************************************************************/
+/*                Ethernet MAC Registers bits definitions                     */
+/******************************************************************************/
+/* Bit definition for Ethernet MAC Control Register register */
+#define ETH_MACCR_WD      ((uint32_t)0x00800000)  /* Watchdog disable */
+#define ETH_MACCR_JD      ((uint32_t)0x00400000)  /* Jabber disable */
+#define ETH_MACCR_IFG     ((uint32_t)0x000E0000)  /* Inter-frame gap */
+  #define ETH_MACCR_IFG_96Bit     ((uint32_t)0x00000000)  /* Minimum IFG between frames during transmission is 96Bit */
+  #define ETH_MACCR_IFG_88Bit     ((uint32_t)0x00020000)  /* Minimum IFG between frames during transmission is 88Bit */
+  #define ETH_MACCR_IFG_80Bit     ((uint32_t)0x00040000)  /* Minimum IFG between frames during transmission is 80Bit */
+  #define ETH_MACCR_IFG_72Bit     ((uint32_t)0x00060000)  /* Minimum IFG between frames during transmission is 72Bit */
+  #define ETH_MACCR_IFG_64Bit     ((uint32_t)0x00080000)  /* Minimum IFG between frames during transmission is 64Bit */        
+  #define ETH_MACCR_IFG_56Bit     ((uint32_t)0x000A0000)  /* Minimum IFG between frames during transmission is 56Bit */
+  #define ETH_MACCR_IFG_48Bit     ((uint32_t)0x000C0000)  /* Minimum IFG between frames during transmission is 48Bit */
+  #define ETH_MACCR_IFG_40Bit     ((uint32_t)0x000E0000)  /* Minimum IFG between frames during transmission is 40Bit */              
+#define ETH_MACCR_CSD     ((uint32_t)0x00010000)  /* Carrier sense disable (during transmission) */
+#define ETH_MACCR_FES     ((uint32_t)0x00004000)  /* Fast ethernet speed */
+#define ETH_MACCR_ROD     ((uint32_t)0x00002000)  /* Receive own disable */
+#define ETH_MACCR_LM      ((uint32_t)0x00001000)  /* loopback mode */
+#define ETH_MACCR_DM      ((uint32_t)0x00000800)  /* Duplex mode */
+#define ETH_MACCR_IPCO    ((uint32_t)0x00000400)  /* IP Checksum offload */
+#define ETH_MACCR_RD      ((uint32_t)0x00000200)  /* Retry disable */
+#define ETH_MACCR_APCS    ((uint32_t)0x00000080)  /* Automatic Pad/CRC stripping */
+#define ETH_MACCR_BL      ((uint32_t)0x00000060)  /* Back-off limit: random integer number (r) of slot time delays before rescheduling
+                                                       a transmission attempt during retries after a collision: 0 =< r <2^k */
+  #define ETH_MACCR_BL_10    ((uint32_t)0x00000000)  /* k = min (n, 10) */
+  #define ETH_MACCR_BL_8     ((uint32_t)0x00000020)  /* k = min (n, 8) */
+  #define ETH_MACCR_BL_4     ((uint32_t)0x00000040)  /* k = min (n, 4) */
+  #define ETH_MACCR_BL_1     ((uint32_t)0x00000060)  /* k = min (n, 1) */ 
+#define ETH_MACCR_DC      ((uint32_t)0x00000010)  /* Defferal check */
+#define ETH_MACCR_TE      ((uint32_t)0x00000008)  /* Transmitter enable */
+#define ETH_MACCR_RE      ((uint32_t)0x00000004)  /* Receiver enable */
+
+/* Bit definition for Ethernet MAC Frame Filter Register */
+#define ETH_MACFFR_RA     ((uint32_t)0x80000000)  /* Receive all */ 
+#define ETH_MACFFR_HPF    ((uint32_t)0x00000400)  /* Hash or perfect filter */ 
+#define ETH_MACFFR_SAF    ((uint32_t)0x00000200)  /* Source address filter enable */ 
+#define ETH_MACFFR_SAIF   ((uint32_t)0x00000100)  /* SA inverse filtering */ 
+#define ETH_MACFFR_PCF    ((uint32_t)0x000000C0)  /* Pass control frames: 3 cases */
+  #define ETH_MACFFR_PCF_BlockAll                ((uint32_t)0x00000040)  /* MAC filters all control frames from reaching the application */
+  #define ETH_MACFFR_PCF_ForwardAll              ((uint32_t)0x00000080)  /* MAC forwards all control frames to application even if they fail the Address Filter */
+  #define ETH_MACFFR_PCF_ForwardPassedAddrFilter ((uint32_t)0x000000C0)  /* MAC forwards control frames that pass the Address Filter. */ 
+#define ETH_MACFFR_BFD    ((uint32_t)0x00000020)  /* Broadcast frame disable */ 
+#define ETH_MACFFR_PAM 	  ((uint32_t)0x00000010)  /* Pass all mutlicast */ 
+#define ETH_MACFFR_DAIF   ((uint32_t)0x00000008)  /* DA Inverse filtering */ 
+#define ETH_MACFFR_HM     ((uint32_t)0x00000004)  /* Hash multicast */ 
+#define ETH_MACFFR_HU     ((uint32_t)0x00000002)  /* Hash unicast */
+#define ETH_MACFFR_PM     ((uint32_t)0x00000001)  /* Promiscuous mode */
+
+/* Bit definition for Ethernet MAC Hash Table High Register */
+#define ETH_MACHTHR_HTH   ((uint32_t)0xFFFFFFFF)  /* Hash table high */
+
+/* Bit definition for Ethernet MAC Hash Table Low Register */
+#define ETH_MACHTLR_HTL   ((uint32_t)0xFFFFFFFF)  /* Hash table low */
+
+/* Bit definition for Ethernet MAC MII Address Register */
+#define ETH_MACMIIAR_PA   ((uint32_t)0x0000F800)  /* Physical layer address */ 
+#define ETH_MACMIIAR_MR   ((uint32_t)0x000007C0)  /* MII register in the selected PHY */ 
+#define ETH_MACMIIAR_CR   ((uint32_t)0x0000001C)  /* CR clock range: 6 cases */ 
+  #define ETH_MACMIIAR_CR_Div42   ((uint32_t)0x00000000)  /* HCLK:60-72 MHz; MDC clock= HCLK/42 */
+  #define ETH_MACMIIAR_CR_Div16   ((uint32_t)0x00000008)  /* HCLK:20-35 MHz; MDC clock= HCLK/16 */
+  #define ETH_MACMIIAR_CR_Div26   ((uint32_t)0x0000000C)  /* HCLK:35-60 MHz; MDC clock= HCLK/26 */
+#define ETH_MACMIIAR_MW   ((uint32_t)0x00000002)  /* MII write */ 
+#define ETH_MACMIIAR_MB   ((uint32_t)0x00000001)  /* MII busy */ 
+  
+/* Bit definition for Ethernet MAC MII Data Register */
+#define ETH_MACMIIDR_MD   ((uint32_t)0x0000FFFF)  /* MII data: read/write data from/to PHY */
+
+/* Bit definition for Ethernet MAC Flow Control Register */
+#define ETH_MACFCR_PT     ((uint32_t)0xFFFF0000)  /* Pause time */
+#define ETH_MACFCR_ZQPD   ((uint32_t)0x00000080)  /* Zero-quanta pause disable */
+#define ETH_MACFCR_PLT    ((uint32_t)0x00000030)  /* Pause low threshold: 4 cases */
+  #define ETH_MACFCR_PLT_Minus4   ((uint32_t)0x00000000)  /* Pause time minus 4 slot times */
+  #define ETH_MACFCR_PLT_Minus28  ((uint32_t)0x00000010)  /* Pause time minus 28 slot times */
+  #define ETH_MACFCR_PLT_Minus144 ((uint32_t)0x00000020)  /* Pause time minus 144 slot times */
+  #define ETH_MACFCR_PLT_Minus256 ((uint32_t)0x00000030)  /* Pause time minus 256 slot times */      
+#define ETH_MACFCR_UPFD   ((uint32_t)0x00000008)  /* Unicast pause frame detect */
+#define ETH_MACFCR_RFCE   ((uint32_t)0x00000004)  /* Receive flow control enable */
+#define ETH_MACFCR_TFCE   ((uint32_t)0x00000002)  /* Transmit flow control enable */
+#define ETH_MACFCR_FCBBPA ((uint32_t)0x00000001)  /* Flow control busy/backpressure activate */
+
+/* Bit definition for Ethernet MAC VLAN Tag Register */
+#define ETH_MACVLANTR_VLANTC ((uint32_t)0x00010000)  /* 12-bit VLAN tag comparison */
+#define ETH_MACVLANTR_VLANTI ((uint32_t)0x0000FFFF)  /* VLAN tag identifier (for receive frames) */
+
+/* Bit definition for Ethernet MAC Remote Wake-UpFrame Filter Register */ 
+#define ETH_MACRWUFFR_D   ((uint32_t)0xFFFFFFFF)  /* Wake-up frame filter register data */
+/* Eight sequential Writes to this address (offset 0x28) will write all Wake-UpFrame Filter Registers.
+   Eight sequential Reads from this address (offset 0x28) will read all Wake-UpFrame Filter Registers. */
+/* Wake-UpFrame Filter Reg0 : Filter 0 Byte Mask
+   Wake-UpFrame Filter Reg1 : Filter 1 Byte Mask
+   Wake-UpFrame Filter Reg2 : Filter 2 Byte Mask
+   Wake-UpFrame Filter Reg3 : Filter 3 Byte Mask
+   Wake-UpFrame Filter Reg4 : RSVD - Filter3 Command - RSVD - Filter2 Command - 
+                              RSVD - Filter1 Command - RSVD - Filter0 Command
+   Wake-UpFrame Filter Re5 : Filter3 Offset - Filter2 Offset - Filter1 Offset - Filter0 Offset
+   Wake-UpFrame Filter Re6 : Filter1 CRC16 - Filter0 CRC16
+   Wake-UpFrame Filter Re7 : Filter3 CRC16 - Filter2 CRC16 */
+
+/* Bit definition for Ethernet MAC PMT Control and Status Register */ 
+#define ETH_MACPMTCSR_WFFRPR ((uint32_t)0x80000000)  /* Wake-Up Frame Filter Register Pointer Reset */
+#define ETH_MACPMTCSR_GU     ((uint32_t)0x00000200)  /* Global Unicast */
+#define ETH_MACPMTCSR_WFR    ((uint32_t)0x00000040)  /* Wake-Up Frame Received */
+#define ETH_MACPMTCSR_MPR    ((uint32_t)0x00000020)  /* Magic Packet Received */
+#define ETH_MACPMTCSR_WFE    ((uint32_t)0x00000004)  /* Wake-Up Frame Enable */
+#define ETH_MACPMTCSR_MPE    ((uint32_t)0x00000002)  /* Magic Packet Enable */
+#define ETH_MACPMTCSR_PD     ((uint32_t)0x00000001)  /* Power Down */
+
+/* Bit definition for Ethernet MAC Status Register */
+#define ETH_MACSR_TSTS      ((uint32_t)0x00000200)  /* Time stamp trigger status */
+#define ETH_MACSR_MMCTS     ((uint32_t)0x00000040)  /* MMC transmit status */
+#define ETH_MACSR_MMMCRS    ((uint32_t)0x00000020)  /* MMC receive status */
+#define ETH_MACSR_MMCS      ((uint32_t)0x00000010)  /* MMC status */
+#define ETH_MACSR_PMTS      ((uint32_t)0x00000008)  /* PMT status */
+
+/* Bit definition for Ethernet MAC Interrupt Mask Register */
+#define ETH_MACIMR_TSTIM     ((uint32_t)0x00000200)  /* Time stamp trigger interrupt mask */
+#define ETH_MACIMR_PMTIM     ((uint32_t)0x00000008)  /* PMT interrupt mask */
+
+/* Bit definition for Ethernet MAC Address0 High Register */
+#define ETH_MACA0HR_MACA0H   ((uint32_t)0x0000FFFF)  /* MAC address0 high */
+
+/* Bit definition for Ethernet MAC Address0 Low Register */
+#define ETH_MACA0LR_MACA0L   ((uint32_t)0xFFFFFFFF)  /* MAC address0 low */
+
+/* Bit definition for Ethernet MAC Address1 High Register */
+#define ETH_MACA1HR_AE       ((uint32_t)0x80000000)  /* Address enable */
+#define ETH_MACA1HR_SA       ((uint32_t)0x40000000)  /* Source address */
+#define ETH_MACA1HR_MBC      ((uint32_t)0x3F000000)  /* Mask byte control: bits to mask for comparison of the MAC Address bytes */
+  #define ETH_MACA1HR_MBC_HBits15_8    ((uint32_t)0x20000000)  /* Mask MAC Address high reg bits [15:8] */
+  #define ETH_MACA1HR_MBC_HBits7_0     ((uint32_t)0x10000000)  /* Mask MAC Address high reg bits [7:0] */
+  #define ETH_MACA1HR_MBC_LBits31_24   ((uint32_t)0x08000000)  /* Mask MAC Address low reg bits [31:24] */
+  #define ETH_MACA1HR_MBC_LBits23_16   ((uint32_t)0x04000000)  /* Mask MAC Address low reg bits [23:16] */
+  #define ETH_MACA1HR_MBC_LBits15_8    ((uint32_t)0x02000000)  /* Mask MAC Address low reg bits [15:8] */
+  #define ETH_MACA1HR_MBC_LBits7_0     ((uint32_t)0x01000000)  /* Mask MAC Address low reg bits [7:0] */ 
+#define ETH_MACA1HR_MACA1H   ((uint32_t)0x0000FFFF)  /* MAC address1 high */
+
+/* Bit definition for Ethernet MAC Address1 Low Register */
+#define ETH_MACA1LR_MACA1L   ((uint32_t)0xFFFFFFFF)  /* MAC address1 low */
+
+/* Bit definition for Ethernet MAC Address2 High Register */
+#define ETH_MACA2HR_AE       ((uint32_t)0x80000000)  /* Address enable */
+#define ETH_MACA2HR_SA       ((uint32_t)0x40000000)  /* Source address */
+#define ETH_MACA2HR_MBC      ((uint32_t)0x3F000000)  /* Mask byte control */
+  #define ETH_MACA2HR_MBC_HBits15_8    ((uint32_t)0x20000000)  /* Mask MAC Address high reg bits [15:8] */
+  #define ETH_MACA2HR_MBC_HBits7_0     ((uint32_t)0x10000000)  /* Mask MAC Address high reg bits [7:0] */
+  #define ETH_MACA2HR_MBC_LBits31_24   ((uint32_t)0x08000000)  /* Mask MAC Address low reg bits [31:24] */
+  #define ETH_MACA2HR_MBC_LBits23_16   ((uint32_t)0x04000000)  /* Mask MAC Address low reg bits [23:16] */
+  #define ETH_MACA2HR_MBC_LBits15_8    ((uint32_t)0x02000000)  /* Mask MAC Address low reg bits [15:8] */
+  #define ETH_MACA2HR_MBC_LBits7_0     ((uint32_t)0x01000000)  /* Mask MAC Address low reg bits [70] */
+#define ETH_MACA2HR_MACA2H   ((uint32_t)0x0000FFFF)  /* MAC address1 high */
+
+/* Bit definition for Ethernet MAC Address2 Low Register */
+#define ETH_MACA2LR_MACA2L   ((uint32_t)0xFFFFFFFF)  /* MAC address2 low */
+
+/* Bit definition for Ethernet MAC Address3 High Register */
+#define ETH_MACA3HR_AE       ((uint32_t)0x80000000)  /* Address enable */
+#define ETH_MACA3HR_SA       ((uint32_t)0x40000000)  /* Source address */
+#define ETH_MACA3HR_MBC      ((uint32_t)0x3F000000)  /* Mask byte control */
+  #define ETH_MACA3HR_MBC_HBits15_8    ((uint32_t)0x20000000)  /* Mask MAC Address high reg bits [15:8] */
+  #define ETH_MACA3HR_MBC_HBits7_0     ((uint32_t)0x10000000)  /* Mask MAC Address high reg bits [7:0] */
+  #define ETH_MACA3HR_MBC_LBits31_24   ((uint32_t)0x08000000)  /* Mask MAC Address low reg bits [31:24] */
+  #define ETH_MACA3HR_MBC_LBits23_16   ((uint32_t)0x04000000)  /* Mask MAC Address low reg bits [23:16] */
+  #define ETH_MACA3HR_MBC_LBits15_8    ((uint32_t)0x02000000)  /* Mask MAC Address low reg bits [15:8] */
+  #define ETH_MACA3HR_MBC_LBits7_0     ((uint32_t)0x01000000)  /* Mask MAC Address low reg bits [70] */
+#define ETH_MACA3HR_MACA3H   ((uint32_t)0x0000FFFF)  /* MAC address3 high */
+
+/* Bit definition for Ethernet MAC Address3 Low Register */
+#define ETH_MACA3LR_MACA3L   ((uint32_t)0xFFFFFFFF)  /* MAC address3 low */
+
+/******************************************************************************/
+/*                Ethernet MMC Registers bits definition                      */
+/******************************************************************************/
+
+/* Bit definition for Ethernet MMC Contol Register */
+#define ETH_MMCCR_MCF        ((uint32_t)0x00000008)  /* MMC Counter Freeze */
+#define ETH_MMCCR_ROR        ((uint32_t)0x00000004)  /* Reset on Read */
+#define ETH_MMCCR_CSR        ((uint32_t)0x00000002)  /* Counter Stop Rollover */
+#define ETH_MMCCR_CR         ((uint32_t)0x00000001)  /* Counters Reset */
+
+/* Bit definition for Ethernet MMC Receive Interrupt Register */
+#define ETH_MMCRIR_RGUFS     ((uint32_t)0x00020000)  /* Set when Rx good unicast frames counter reaches half the maximum value */
+#define ETH_MMCRIR_RFAES     ((uint32_t)0x00000040)  /* Set when Rx alignment error counter reaches half the maximum value */
+#define ETH_MMCRIR_RFCES     ((uint32_t)0x00000020)  /* Set when Rx crc error counter reaches half the maximum value */
+
+/* Bit definition for Ethernet MMC Transmit Interrupt Register */
+#define ETH_MMCTIR_TGFS      ((uint32_t)0x00200000)  /* Set when Tx good frame count counter reaches half the maximum value */
+#define ETH_MMCTIR_TGFMSCS   ((uint32_t)0x00008000)  /* Set when Tx good multi col counter reaches half the maximum value */
+#define ETH_MMCTIR_TGFSCS    ((uint32_t)0x00004000)  /* Set when Tx good single col counter reaches half the maximum value */
+
+/* Bit definition for Ethernet MMC Receive Interrupt Mask Register */
+#define ETH_MMCRIMR_RGUFM    ((uint32_t)0x00020000)  /* Mask the interrupt when Rx good unicast frames counter reaches half the maximum value */
+#define ETH_MMCRIMR_RFAEM    ((uint32_t)0x00000040)  /* Mask the interrupt when when Rx alignment error counter reaches half the maximum value */
+#define ETH_MMCRIMR_RFCEM    ((uint32_t)0x00000020)  /* Mask the interrupt when Rx crc error counter reaches half the maximum value */
+
+/* Bit definition for Ethernet MMC Transmit Interrupt Mask Register */
+#define ETH_MMCTIMR_TGFM     ((uint32_t)0x00200000)  /* Mask the interrupt when Tx good frame count counter reaches half the maximum value */
+#define ETH_MMCTIMR_TGFMSCM  ((uint32_t)0x00008000)  /* Mask the interrupt when Tx good multi col counter reaches half the maximum value */
+#define ETH_MMCTIMR_TGFSCM   ((uint32_t)0x00004000)  /* Mask the interrupt when Tx good single col counter reaches half the maximum value */
+
+/* Bit definition for Ethernet MMC Transmitted Good Frames after Single Collision Counter Register */
+#define ETH_MMCTGFSCCR_TGFSCC     ((uint32_t)0xFFFFFFFF)  /* Number of successfully transmitted frames after a single collision in Half-duplex mode. */
+
+/* Bit definition for Ethernet MMC Transmitted Good Frames after More than a Single Collision Counter Register */
+#define ETH_MMCTGFMSCCR_TGFMSCC   ((uint32_t)0xFFFFFFFF)  /* Number of successfully transmitted frames after more than a single collision in Half-duplex mode. */
+
+/* Bit definition for Ethernet MMC Transmitted Good Frames Counter Register */
+#define ETH_MMCTGFCR_TGFC    ((uint32_t)0xFFFFFFFF)  /* Number of good frames transmitted. */
+
+/* Bit definition for Ethernet MMC Received Frames with CRC Error Counter Register */
+#define ETH_MMCRFCECR_RFCEC  ((uint32_t)0xFFFFFFFF)  /* Number of frames received with CRC error. */
+
+/* Bit definition for Ethernet MMC Received Frames with Alignement Error Counter Register */
+#define ETH_MMCRFAECR_RFAEC  ((uint32_t)0xFFFFFFFF)  /* Number of frames received with alignment (dribble) error */
+
+/* Bit definition for Ethernet MMC Received Good Unicast Frames Counter Register */
+#define ETH_MMCRGUFCR_RGUFC  ((uint32_t)0xFFFFFFFF)  /* Number of good unicast frames received. */
+
+/******************************************************************************/
+/*               Ethernet PTP Registers bits definition                       */
+/******************************************************************************/
+
+/* Bit definition for Ethernet PTP Time Stamp Contol Register */
+#define ETH_PTPTSCR_TSARU    ((uint32_t)0x00000020)  /* Addend register update */
+#define ETH_PTPTSCR_TSITE    ((uint32_t)0x00000010)  /* Time stamp interrupt trigger enable */
+#define ETH_PTPTSCR_TSSTU    ((uint32_t)0x00000008)  /* Time stamp update */
+#define ETH_PTPTSCR_TSSTI    ((uint32_t)0x00000004)  /* Time stamp initialize */
+#define ETH_PTPTSCR_TSFCU    ((uint32_t)0x00000002)  /* Time stamp fine or coarse update */
+#define ETH_PTPTSCR_TSE      ((uint32_t)0x00000001)  /* Time stamp enable */
+
+/* Bit definition for Ethernet PTP Sub-Second Increment Register */
+#define ETH_PTPSSIR_STSSI    ((uint32_t)0x000000FF)  /* System time Sub-second increment value */
+
+/* Bit definition for Ethernet PTP Time Stamp High Register */
+#define ETH_PTPTSHR_STS      ((uint32_t)0xFFFFFFFF)  /* System Time second */
+
+/* Bit definition for Ethernet PTP Time Stamp Low Register */
+#define ETH_PTPTSLR_STPNS    ((uint32_t)0x80000000)  /* System Time Positive or negative time */
+#define ETH_PTPTSLR_STSS     ((uint32_t)0x7FFFFFFF)  /* System Time sub-seconds */
+
+/* Bit definition for Ethernet PTP Time Stamp High Update Register */
+#define ETH_PTPTSHUR_TSUS    ((uint32_t)0xFFFFFFFF)  /* Time stamp update seconds */
+
+/* Bit definition for Ethernet PTP Time Stamp Low Update Register */
+#define ETH_PTPTSLUR_TSUPNS  ((uint32_t)0x80000000)  /* Time stamp update Positive or negative time */
+#define ETH_PTPTSLUR_TSUSS   ((uint32_t)0x7FFFFFFF)  /* Time stamp update sub-seconds */
+
+/* Bit definition for Ethernet PTP Time Stamp Addend Register */
+#define ETH_PTPTSAR_TSA      ((uint32_t)0xFFFFFFFF)  /* Time stamp addend */
+
+/* Bit definition for Ethernet PTP Target Time High Register */
+#define ETH_PTPTTHR_TTSH     ((uint32_t)0xFFFFFFFF)  /* Target time stamp high */
+
+/* Bit definition for Ethernet PTP Target Time Low Register */
+#define ETH_PTPTTLR_TTSL     ((uint32_t)0xFFFFFFFF)  /* Target time stamp low */
+
+/******************************************************************************/
+/*                 Ethernet DMA Registers bits definition                     */
+/******************************************************************************/
+
+/* Bit definition for Ethernet DMA Bus Mode Register */
+#define ETH_DMABMR_AAB       ((uint32_t)0x02000000)  /* Address-Aligned beats */
+#define ETH_DMABMR_FPM        ((uint32_t)0x01000000)  /* 4xPBL mode */
+#define ETH_DMABMR_USP       ((uint32_t)0x00800000)  /* Use separate PBL */
+#define ETH_DMABMR_RDP       ((uint32_t)0x007E0000)  /* RxDMA PBL */
+  #define ETH_DMABMR_RDP_1Beat    ((uint32_t)0x00020000)  /* maximum number of beats to be transferred in one RxDMA transaction is 1 */
+  #define ETH_DMABMR_RDP_2Beat    ((uint32_t)0x00040000)  /* maximum number of beats to be transferred in one RxDMA transaction is 2 */
+  #define ETH_DMABMR_RDP_4Beat    ((uint32_t)0x00080000)  /* maximum number of beats to be transferred in one RxDMA transaction is 4 */
+  #define ETH_DMABMR_RDP_8Beat    ((uint32_t)0x00100000)  /* maximum number of beats to be transferred in one RxDMA transaction is 8 */
+  #define ETH_DMABMR_RDP_16Beat   ((uint32_t)0x00200000)  /* maximum number of beats to be transferred in one RxDMA transaction is 16 */
+  #define ETH_DMABMR_RDP_32Beat   ((uint32_t)0x00400000)  /* maximum number of beats to be transferred in one RxDMA transaction is 32 */                
+  #define ETH_DMABMR_RDP_4xPBL_4Beat   ((uint32_t)0x01020000)  /* maximum number of beats to be transferred in one RxDMA transaction is 4 */
+  #define ETH_DMABMR_RDP_4xPBL_8Beat   ((uint32_t)0x01040000)  /* maximum number of beats to be transferred in one RxDMA transaction is 8 */
+  #define ETH_DMABMR_RDP_4xPBL_16Beat  ((uint32_t)0x01080000)  /* maximum number of beats to be transferred in one RxDMA transaction is 16 */
+  #define ETH_DMABMR_RDP_4xPBL_32Beat  ((uint32_t)0x01100000)  /* maximum number of beats to be transferred in one RxDMA transaction is 32 */
+  #define ETH_DMABMR_RDP_4xPBL_64Beat  ((uint32_t)0x01200000)  /* maximum number of beats to be transferred in one RxDMA transaction is 64 */
+  #define ETH_DMABMR_RDP_4xPBL_128Beat ((uint32_t)0x01400000)  /* maximum number of beats to be transferred in one RxDMA transaction is 128 */  
+#define ETH_DMABMR_FB        ((uint32_t)0x00010000)  /* Fixed Burst */
+#define ETH_DMABMR_RTPR      ((uint32_t)0x0000C000)  /* Rx Tx priority ratio */
+  #define ETH_DMABMR_RTPR_1_1     ((uint32_t)0x00000000)  /* Rx Tx priority ratio */
+  #define ETH_DMABMR_RTPR_2_1     ((uint32_t)0x00004000)  /* Rx Tx priority ratio */
+  #define ETH_DMABMR_RTPR_3_1     ((uint32_t)0x00008000)  /* Rx Tx priority ratio */
+  #define ETH_DMABMR_RTPR_4_1     ((uint32_t)0x0000C000)  /* Rx Tx priority ratio */  
+#define ETH_DMABMR_PBL    ((uint32_t)0x00003F00)  /* Programmable burst length */
+  #define ETH_DMABMR_PBL_1Beat    ((uint32_t)0x00000100)  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 */
+  #define ETH_DMABMR_PBL_2Beat    ((uint32_t)0x00000200)  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 2 */
+  #define ETH_DMABMR_PBL_4Beat    ((uint32_t)0x00000400)  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
+  #define ETH_DMABMR_PBL_8Beat    ((uint32_t)0x00000800)  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
+  #define ETH_DMABMR_PBL_16Beat   ((uint32_t)0x00001000)  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
+  #define ETH_DMABMR_PBL_32Beat   ((uint32_t)0x00002000)  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */                
+  #define ETH_DMABMR_PBL_4xPBL_4Beat   ((uint32_t)0x01000100)  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
+  #define ETH_DMABMR_PBL_4xPBL_8Beat   ((uint32_t)0x01000200)  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
+  #define ETH_DMABMR_PBL_4xPBL_16Beat  ((uint32_t)0x01000400)  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
+  #define ETH_DMABMR_PBL_4xPBL_32Beat  ((uint32_t)0x01000800)  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
+  #define ETH_DMABMR_PBL_4xPBL_64Beat  ((uint32_t)0x01001000)  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 64 */
+  #define ETH_DMABMR_PBL_4xPBL_128Beat ((uint32_t)0x01002000)  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 128 */
+#define ETH_DMABMR_DSL       ((uint32_t)0x0000007C)  /* Descriptor Skip Length */
+#define ETH_DMABMR_DA        ((uint32_t)0x00000002)  /* DMA arbitration scheme */
+#define ETH_DMABMR_SR        ((uint32_t)0x00000001)  /* Software reset */
+
+/* Bit definition for Ethernet DMA Transmit Poll Demand Register */
+#define ETH_DMATPDR_TPD      ((uint32_t)0xFFFFFFFF)  /* Transmit poll demand */
+
+/* Bit definition for Ethernet DMA Receive Poll Demand Register */
+#define ETH_DMARPDR_RPD      ((uint32_t)0xFFFFFFFF)  /* Receive poll demand  */
+
+/* Bit definition for Ethernet DMA Receive Descriptor List Address Register */
+#define ETH_DMARDLAR_SRL     ((uint32_t)0xFFFFFFFF)  /* Start of receive list */
+
+/* Bit definition for Ethernet DMA Transmit Descriptor List Address Register */
+#define ETH_DMATDLAR_STL     ((uint32_t)0xFFFFFFFF)  /* Start of transmit list */
+
+/* Bit definition for Ethernet DMA Status Register */
+#define ETH_DMASR_TSTS       ((uint32_t)0x20000000)  /* Time-stamp trigger status */
+#define ETH_DMASR_PMTS       ((uint32_t)0x10000000)  /* PMT status */
+#define ETH_DMASR_MMCS       ((uint32_t)0x08000000)  /* MMC status */
+#define ETH_DMASR_EBS        ((uint32_t)0x03800000)  /* Error bits status */
+  /* combination with EBS[2:0] for GetFlagStatus function */
+  #define ETH_DMASR_EBS_DescAccess      ((uint32_t)0x02000000)  /* Error bits 0-data buffer, 1-desc. access */
+  #define ETH_DMASR_EBS_ReadTransf      ((uint32_t)0x01000000)  /* Error bits 0-write trnsf, 1-read transfr */
+  #define ETH_DMASR_EBS_DataTransfTx    ((uint32_t)0x00800000)  /* Error bits 0-Rx DMA, 1-Tx DMA */
+#define ETH_DMASR_TPS         ((uint32_t)0x00700000)  /* Transmit process state */
+  #define ETH_DMASR_TPS_Stopped         ((uint32_t)0x00000000)  /* Stopped - Reset or Stop Tx Command issued  */
+  #define ETH_DMASR_TPS_Fetching        ((uint32_t)0x00100000)  /* Running - fetching the Tx descriptor */
+  #define ETH_DMASR_TPS_Waiting         ((uint32_t)0x00200000)  /* Running - waiting for status */
+  #define ETH_DMASR_TPS_Reading         ((uint32_t)0x00300000)  /* Running - reading the data from host memory */
+  #define ETH_DMASR_TPS_Suspended       ((uint32_t)0x00600000)  /* Suspended - Tx Descriptor unavailabe */
+  #define ETH_DMASR_TPS_Closing         ((uint32_t)0x00700000)  /* Running - closing Rx descriptor */
+#define ETH_DMASR_RPS         ((uint32_t)0x000E0000)  /* Receive process state */
+  #define ETH_DMASR_RPS_Stopped         ((uint32_t)0x00000000)  /* Stopped - Reset or Stop Rx Command issued */
+  #define ETH_DMASR_RPS_Fetching        ((uint32_t)0x00020000)  /* Running - fetching the Rx descriptor */
+  #define ETH_DMASR_RPS_Waiting         ((uint32_t)0x00060000)  /* Running - waiting for packet */
+  #define ETH_DMASR_RPS_Suspended       ((uint32_t)0x00080000)  /* Suspended - Rx Descriptor unavailable */
+  #define ETH_DMASR_RPS_Closing         ((uint32_t)0x000A0000)  /* Running - closing descriptor */
+  #define ETH_DMASR_RPS_Queuing         ((uint32_t)0x000E0000)  /* Running - queuing the recieve frame into host memory */
+#define ETH_DMASR_NIS        ((uint32_t)0x00010000)  /* Normal interrupt summary */
+#define ETH_DMASR_AIS        ((uint32_t)0x00008000)  /* Abnormal interrupt summary */
+#define ETH_DMASR_ERS        ((uint32_t)0x00004000)  /* Early receive status */
+#define ETH_DMASR_FBES       ((uint32_t)0x00002000)  /* Fatal bus error status */
+#define ETH_DMASR_ETS        ((uint32_t)0x00000400)  /* Early transmit status */
+#define ETH_DMASR_RWTS       ((uint32_t)0x00000200)  /* Receive watchdog timeout status */
+#define ETH_DMASR_RPSS       ((uint32_t)0x00000100)  /* Receive process stopped status */
+#define ETH_DMASR_RBUS       ((uint32_t)0x00000080)  /* Receive buffer unavailable status */
+#define ETH_DMASR_RS         ((uint32_t)0x00000040)  /* Receive status */
+#define ETH_DMASR_TUS        ((uint32_t)0x00000020)  /* Transmit underflow status */
+#define ETH_DMASR_ROS        ((uint32_t)0x00000010)  /* Receive overflow status */
+#define ETH_DMASR_TJTS       ((uint32_t)0x00000008)  /* Transmit jabber timeout status */
+#define ETH_DMASR_TBUS       ((uint32_t)0x00000004)  /* Transmit buffer unavailable status */
+#define ETH_DMASR_TPSS       ((uint32_t)0x00000002)  /* Transmit process stopped status */
+#define ETH_DMASR_TS         ((uint32_t)0x00000001)  /* Transmit status */
+
+/* Bit definition for Ethernet DMA Operation Mode Register */
+#define ETH_DMAOMR_DTCEFD    ((uint32_t)0x04000000)  /* Disable Dropping of TCP/IP checksum error frames */
+#define ETH_DMAOMR_RSF       ((uint32_t)0x02000000)  /* Receive store and forward */
+#define ETH_DMAOMR_DFRF      ((uint32_t)0x01000000)  /* Disable flushing of received frames */
+#define ETH_DMAOMR_TSF       ((uint32_t)0x00200000)  /* Transmit store and forward */
+#define ETH_DMAOMR_FTF       ((uint32_t)0x00100000)  /* Flush transmit FIFO */
+#define ETH_DMAOMR_TTC       ((uint32_t)0x0001C000)  /* Transmit threshold control */
+  #define ETH_DMAOMR_TTC_64Bytes       ((uint32_t)0x00000000)  /* threshold level of the MTL Transmit FIFO is 64 Bytes */
+  #define ETH_DMAOMR_TTC_128Bytes      ((uint32_t)0x00004000)  /* threshold level of the MTL Transmit FIFO is 128 Bytes */
+  #define ETH_DMAOMR_TTC_192Bytes      ((uint32_t)0x00008000)  /* threshold level of the MTL Transmit FIFO is 192 Bytes */
+  #define ETH_DMAOMR_TTC_256Bytes      ((uint32_t)0x0000C000)  /* threshold level of the MTL Transmit FIFO is 256 Bytes */
+  #define ETH_DMAOMR_TTC_40Bytes       ((uint32_t)0x00010000)  /* threshold level of the MTL Transmit FIFO is 40 Bytes */
+  #define ETH_DMAOMR_TTC_32Bytes       ((uint32_t)0x00014000)  /* threshold level of the MTL Transmit FIFO is 32 Bytes */
+  #define ETH_DMAOMR_TTC_24Bytes       ((uint32_t)0x00018000)  /* threshold level of the MTL Transmit FIFO is 24 Bytes */
+  #define ETH_DMAOMR_TTC_16Bytes       ((uint32_t)0x0001C000)  /* threshold level of the MTL Transmit FIFO is 16 Bytes */
+#define ETH_DMAOMR_ST        ((uint32_t)0x00002000)  /* Start/stop transmission command */
+#define ETH_DMAOMR_FEF       ((uint32_t)0x00000080)  /* Forward error frames */
+#define ETH_DMAOMR_FUGF      ((uint32_t)0x00000040)  /* Forward undersized good frames */
+#define ETH_DMAOMR_RTC       ((uint32_t)0x00000018)  /* receive threshold control */
+  #define ETH_DMAOMR_RTC_64Bytes       ((uint32_t)0x00000000)  /* threshold level of the MTL Receive FIFO is 64 Bytes */
+  #define ETH_DMAOMR_RTC_32Bytes       ((uint32_t)0x00000008)  /* threshold level of the MTL Receive FIFO is 32 Bytes */
+  #define ETH_DMAOMR_RTC_96Bytes       ((uint32_t)0x00000010)  /* threshold level of the MTL Receive FIFO is 96 Bytes */
+  #define ETH_DMAOMR_RTC_128Bytes      ((uint32_t)0x00000018)  /* threshold level of the MTL Receive FIFO is 128 Bytes */
+#define ETH_DMAOMR_OSF       ((uint32_t)0x00000004)  /* operate on second frame */
+#define ETH_DMAOMR_SR        ((uint32_t)0x00000002)  /* Start/stop receive */
+
+/* Bit definition for Ethernet DMA Interrupt Enable Register */
+#define ETH_DMAIER_NISE      ((uint32_t)0x00010000)  /* Normal interrupt summary enable */
+#define ETH_DMAIER_AISE      ((uint32_t)0x00008000)  /* Abnormal interrupt summary enable */
+#define ETH_DMAIER_ERIE      ((uint32_t)0x00004000)  /* Early receive interrupt enable */
+#define ETH_DMAIER_FBEIE     ((uint32_t)0x00002000)  /* Fatal bus error interrupt enable */
+#define ETH_DMAIER_ETIE      ((uint32_t)0x00000400)  /* Early transmit interrupt enable */
+#define ETH_DMAIER_RWTIE     ((uint32_t)0x00000200)  /* Receive watchdog timeout interrupt enable */
+#define ETH_DMAIER_RPSIE     ((uint32_t)0x00000100)  /* Receive process stopped interrupt enable */
+#define ETH_DMAIER_RBUIE     ((uint32_t)0x00000080)  /* Receive buffer unavailable interrupt enable */
+#define ETH_DMAIER_RIE       ((uint32_t)0x00000040)  /* Receive interrupt enable */
+#define ETH_DMAIER_TUIE      ((uint32_t)0x00000020)  /* Transmit Underflow interrupt enable */
+#define ETH_DMAIER_ROIE      ((uint32_t)0x00000010)  /* Receive Overflow interrupt enable */
+#define ETH_DMAIER_TJTIE     ((uint32_t)0x00000008)  /* Transmit jabber timeout interrupt enable */
+#define ETH_DMAIER_TBUIE     ((uint32_t)0x00000004)  /* Transmit buffer unavailable interrupt enable */
+#define ETH_DMAIER_TPSIE     ((uint32_t)0x00000002)  /* Transmit process stopped interrupt enable */
+#define ETH_DMAIER_TIE       ((uint32_t)0x00000001)  /* Transmit interrupt enable */
+
+/* Bit definition for Ethernet DMA Missed Frame and Buffer Overflow Counter Register */
+#define ETH_DMAMFBOCR_OFOC   ((uint32_t)0x10000000)  /* Overflow bit for FIFO overflow counter */
+#define ETH_DMAMFBOCR_MFA    ((uint32_t)0x0FFE0000)  /* Number of frames missed by the application */
+#define ETH_DMAMFBOCR_OMFC   ((uint32_t)0x00010000)  /* Overflow bit for missed frame counter */
+#define ETH_DMAMFBOCR_MFC    ((uint32_t)0x0000FFFF)  /* Number of frames missed by the controller */
+
+/* Bit definition for Ethernet DMA Current Host Transmit Descriptor Register */
+#define ETH_DMACHTDR_HTDAP   ((uint32_t)0xFFFFFFFF)  /* Host transmit descriptor address pointer */
+
+/* Bit definition for Ethernet DMA Current Host Receive Descriptor Register */
+#define ETH_DMACHRDR_HRDAP   ((uint32_t)0xFFFFFFFF)  /* Host receive descriptor address pointer */
+
+/* Bit definition for Ethernet DMA Current Host Transmit Buffer Address Register */
+#define ETH_DMACHTBAR_HTBAP  ((uint32_t)0xFFFFFFFF)  /* Host transmit buffer address pointer */
+
+/* Bit definition for Ethernet DMA Current Host Receive Buffer Address Register */
+#define ETH_DMACHRBAR_HRBAP  ((uint32_t)0xFFFFFFFF)  /* Host receive buffer address pointer */
+#endif /* STM32F10X_CL */
+
+/**
+  * @}
+  */
+
+ /**
+  * @}
+  */ 
+
+#ifdef USE_STDPERIPH_DRIVER
+  #include "stm32f10x_conf.h"
+#endif
+
+/** @addtogroup Exported_macro
+  * @{
+  */
+
+#define SET_BIT(REG, BIT)     ((REG) |= (BIT))
+
+#define CLEAR_BIT(REG, BIT)   ((REG) &= ~(BIT))
+
+#define READ_BIT(REG, BIT)    ((REG) & (BIT))
+
+#define CLEAR_REG(REG)        ((REG) = (0x0))
+
+#define WRITE_REG(REG, VAL)   ((REG) = (VAL))
+
+#define READ_REG(REG)         ((REG))
+
+#define MODIFY_REG(REG, CLEARMASK, SETMASK)  WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK)))
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F10x_H */
+
+/**
+  * @}
+  */
+
+  /**
+  * @}
+  */
+
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/STM32_4路称重_Git提交精简工程/src/CMSIS/system_stm32f10x.c b/STM32_4路称重_Git提交精简工程/src/CMSIS/system_stm32f10x.c
new file mode 100755
index 0000000..c131ee8
--- /dev/null
+++ b/STM32_4路称重_Git提交精简工程/src/CMSIS/system_stm32f10x.c
@@ -0,0 +1,1094 @@
+/**
+  ******************************************************************************
+  * @file    GPIO/IOToggle/system_stm32f10x.c
+  * @author  MCD Application Team
+  * @version V3.5.0
+  * @date    08-April-2011
+  * @brief   CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.
+  * 
+  * 1.  This file provides two functions and one global variable to be called from 
+  *     user application:
+  *      - SystemInit(): Setups the system clock (System clock source, PLL Multiplier
+  *                      factors, AHB/APBx prescalers and Flash settings). 
+  *                      This function is called at startup just after reset and 
+  *                      before branch to main program. This call is made inside
+  *                      the "startup_stm32f10x_xx.s" file.
+  *
+  *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
+  *                                  by the user application to setup the SysTick 
+  *                                  timer or configure other parameters.
+  *                                     
+  *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
+  *                                 be called whenever the core clock is changed
+  *                                 during program execution.
+  *
+  * 2. After each device reset the HSI (8 MHz) is used as system clock source.
+  *    Then SystemInit() function is called, in "startup_stm32f10x_xx.s" file, to
+  *    configure the system clock before to branch to main program.
+  *
+  * 3. If the system clock source selected by user fails to startup, the SystemInit()
+  *    function will do nothing and HSI still used as system clock source. User can 
+  *    add some code to deal with this issue inside the SetSysClock() function.
+  *
+  * 4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depedning on
+  *    the product used), refer to "HSE_VALUE" define in "stm32f10x.h" file. 
+  *    When HSE is used as system clock source, directly or through PLL, and you
+  *    are using different crystal you have to adapt the HSE value to your own
+  *    configuration.
+  *        
+  ******************************************************************************
+  * @attention
+  *
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+  *
+  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
+  ******************************************************************************
+  */
+
+/** @addtogroup CMSIS
+  * @{
+  */
+
+/** @addtogroup stm32f10x_system
+  * @{
+  */  
+  
+/** @addtogroup STM32F10x_System_Private_Includes
+  * @{
+  */
+
+#include "stm32f10x.h"
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F10x_System_Private_TypesDefinitions
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F10x_System_Private_Defines
+  * @{
+  */
+
+/*!< Uncomment the line corresponding to the desired System clock (SYSCLK)
+   frequency (after reset the HSI is used as SYSCLK source)
+   
+   IMPORTANT NOTE:
+   ============== 
+   1. After each device reset the HSI is used as System clock source.
+
+   2. Please make sure that the selected System clock doesn't exceed your device's
+      maximum frequency.
+      
+   3. If none of the define below is enabled, the HSI is used as System clock
+    source.
+
+   4. The System clock configuration functions provided within this file assume that:
+        - For Low, Medium and High density Value line devices an external 8MHz 
+          crystal is used to drive the System clock.
+        - For Low, Medium and High density devices an external 8MHz crystal is
+          used to drive the System clock.
+        - For Connectivity line devices an external 25MHz crystal is used to drive
+          the System clock.
+     If you are using different crystal you have to adapt those functions accordingly.
+    */
+    
+#if defined (STM32F10X_LD_VL) || (defined STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
+/* #define SYSCLK_FREQ_HSE    HSE_VALUE */
+ #define SYSCLK_FREQ_24MHz  24000000
+#else
+/* #define SYSCLK_FREQ_HSE    HSE_VALUE */
+/* #define SYSCLK_FREQ_24MHz  24000000 */ 
+/* #define SYSCLK_FREQ_36MHz  36000000 */
+/* #define SYSCLK_FREQ_48MHz  48000000 */
+/* #define SYSCLK_FREQ_56MHz  56000000 */
+#define SYSCLK_FREQ_72MHz  72000000
+#endif
+
+/*!< Uncomment the following line if you need to use external SRAM mounted
+     on STM3210E-EVAL board (STM32 High density and XL-density devices) or on 
+     STM32100E-EVAL board (STM32 High-density value line devices) as data memory */ 
+#if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
+/* #define DATA_IN_ExtSRAM */
+#endif
+
+/*!< Uncomment the following line if you need to relocate your vector Table in
+     Internal SRAM. */ 
+/* #define VECT_TAB_SRAM */
+#define VECT_TAB_OFFSET  0x0 /*!< Vector Table base offset field. 
+                                  This value must be a multiple of 0x200. */
+
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F10x_System_Private_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F10x_System_Private_Variables
+  * @{
+  */
+
+/*******************************************************************************
+*  Clock Definitions
+*******************************************************************************/
+#ifdef SYSCLK_FREQ_HSE
+  uint32_t SystemCoreClock         = SYSCLK_FREQ_HSE;        /*!< System Clock Frequency (Core Clock) */
+#elif defined SYSCLK_FREQ_24MHz
+  uint32_t SystemCoreClock         = SYSCLK_FREQ_24MHz;        /*!< System Clock Frequency (Core Clock) */
+#elif defined SYSCLK_FREQ_36MHz
+  uint32_t SystemCoreClock         = SYSCLK_FREQ_36MHz;        /*!< System Clock Frequency (Core Clock) */
+#elif defined SYSCLK_FREQ_48MHz
+  uint32_t SystemCoreClock         = SYSCLK_FREQ_48MHz;        /*!< System Clock Frequency (Core Clock) */
+#elif defined SYSCLK_FREQ_56MHz
+  uint32_t SystemCoreClock         = SYSCLK_FREQ_56MHz;        /*!< System Clock Frequency (Core Clock) */
+#elif defined SYSCLK_FREQ_72MHz
+  uint32_t SystemCoreClock         = SYSCLK_FREQ_72MHz;        /*!< System Clock Frequency (Core Clock) */
+#else /*!< HSI Selected as System Clock source */
+  uint32_t SystemCoreClock         = HSI_VALUE;        /*!< System Clock Frequency (Core Clock) */
+#endif
+
+__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F10x_System_Private_FunctionPrototypes
+  * @{
+  */
+
+static void SetSysClock(void);
+
+#ifdef SYSCLK_FREQ_HSE
+  static void SetSysClockToHSE(void);
+#elif defined SYSCLK_FREQ_24MHz
+  static void SetSysClockTo24(void);
+#elif defined SYSCLK_FREQ_36MHz
+  static void SetSysClockTo36(void);
+#elif defined SYSCLK_FREQ_48MHz
+  static void SetSysClockTo48(void);
+#elif defined SYSCLK_FREQ_56MHz
+  static void SetSysClockTo56(void);  
+#elif defined SYSCLK_FREQ_72MHz
+  static void SetSysClockTo72(void);
+#endif
+
+#ifdef DATA_IN_ExtSRAM
+  static void SystemInit_ExtMemCtl(void); 
+#endif /* DATA_IN_ExtSRAM */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F10x_System_Private_Functions
+  * @{
+  */
+
+/**
+  * @brief  Setup the microcontroller system
+  *         Initialize the Embedded Flash Interface, the PLL and update the 
+  *         SystemCoreClock variable.
+  * @note   This function should be used only after reset.
+  * @param  None
+  * @retval None
+  */
+void SystemInit (void)
+{
+  /* Reset the RCC clock configuration to the default reset state(for debug purpose) */
+  /* Set HSION bit */
+  RCC->CR |= (uint32_t)0x00000001;
+
+  /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */
+#ifndef STM32F10X_CL
+  RCC->CFGR &= (uint32_t)0xF8FF0000;
+#else
+  RCC->CFGR &= (uint32_t)0xF0FF0000;
+#endif /* STM32F10X_CL */   
+  
+  /* Reset HSEON, CSSON and PLLON bits */
+  RCC->CR &= (uint32_t)0xFEF6FFFF;
+
+  /* Reset HSEBYP bit */
+  RCC->CR &= (uint32_t)0xFFFBFFFF;
+
+  /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */
+  RCC->CFGR &= (uint32_t)0xFF80FFFF;
+
+#ifdef STM32F10X_CL
+  /* Reset PLL2ON and PLL3ON bits */
+  RCC->CR &= (uint32_t)0xEBFFFFFF;
+
+  /* Disable all interrupts and clear pending bits  */
+  RCC->CIR = 0x00FF0000;
+
+  /* Reset CFGR2 register */
+  RCC->CFGR2 = 0x00000000;
+#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
+  /* Disable all interrupts and clear pending bits  */
+  RCC->CIR = 0x009F0000;
+
+  /* Reset CFGR2 register */
+  RCC->CFGR2 = 0x00000000;      
+#else
+  /* Disable all interrupts and clear pending bits  */
+  RCC->CIR = 0x009F0000;
+#endif /* STM32F10X_CL */
+    
+#if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
+  #ifdef DATA_IN_ExtSRAM
+    SystemInit_ExtMemCtl(); 
+  #endif /* DATA_IN_ExtSRAM */
+#endif 
+
+  /* Configure the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers */
+  /* Configure the Flash Latency cycles and enable prefetch buffer */
+  SetSysClock();
+
+#ifdef VECT_TAB_SRAM
+  SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
+#else
+  SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
+#endif 
+}
+
+/**
+  * @brief  Update SystemCoreClock variable according to Clock Register Values.
+  *         The SystemCoreClock variable contains the core clock (HCLK), it can
+  *         be used by the user application to setup the SysTick timer or configure
+  *         other parameters.
+  *           
+  * @note   Each time the core clock (HCLK) changes, this function must be called
+  *         to update SystemCoreClock variable value. Otherwise, any configuration
+  *         based on this variable will be incorrect.         
+  *     
+  * @note   - The system frequency computed by this function is not the real 
+  *           frequency in the chip. It is calculated based on the predefined 
+  *           constant and the selected clock source:
+  *             
+  *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
+  *                                              
+  *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
+  *                          
+  *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) 
+  *             or HSI_VALUE(*) multiplied by the PLL factors.
+  *         
+  *         (*) HSI_VALUE is a constant defined in stm32f1xx.h file (default value
+  *             8 MHz) but the real value may vary depending on the variations
+  *             in voltage and temperature.   
+  *    
+  *         (**) HSE_VALUE is a constant defined in stm32f1xx.h file (default value
+  *              8 MHz or 25 MHz, depedning on the product used), user has to ensure
+  *              that HSE_VALUE is same as the real frequency of the crystal used.
+  *              Otherwise, this function may have wrong result.
+  *                
+  *         - The result of this function could be not correct when using fractional
+  *           value for HSE crystal.
+  * @param  None
+  * @retval None
+  */
+void SystemCoreClockUpdate (void)
+{
+  uint32_t tmp = 0, pllmull = 0, pllsource = 0;
+
+#ifdef  STM32F10X_CL
+  uint32_t prediv1source = 0, prediv1factor = 0, prediv2factor = 0, pll2mull = 0;
+#endif /* STM32F10X_CL */
+
+#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
+  uint32_t prediv1factor = 0;
+#endif /* STM32F10X_LD_VL or STM32F10X_MD_VL or STM32F10X_HD_VL */
+    
+  /* Get SYSCLK source -------------------------------------------------------*/
+  tmp = RCC->CFGR & RCC_CFGR_SWS;
+  
+  switch (tmp)
+  {
+    case 0x00:  /* HSI used as system clock */
+      SystemCoreClock = HSI_VALUE;
+      break;
+    case 0x04:  /* HSE used as system clock */
+      SystemCoreClock = HSE_VALUE;
+      break;
+    case 0x08:  /* PLL used as system clock */
+
+      /* Get PLL clock source and multiplication factor ----------------------*/
+      pllmull = RCC->CFGR & RCC_CFGR_PLLMULL;
+      pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
+      
+#ifndef STM32F10X_CL      
+      pllmull = ( pllmull >> 18) + 2;
+      
+      if (pllsource == 0x00)
+      {
+        /* HSI oscillator clock divided by 2 selected as PLL clock entry */
+        SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
+      }
+      else
+      {
+ #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
+       prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
+       /* HSE oscillator clock selected as PREDIV1 clock entry */
+       SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull; 
+ #else
+        /* HSE selected as PLL clock entry */
+        if ((RCC->CFGR & RCC_CFGR_PLLXTPRE) != (uint32_t)RESET)
+        {/* HSE oscillator clock divided by 2 */
+          SystemCoreClock = (HSE_VALUE >> 1) * pllmull;
+        }
+        else
+        {
+          SystemCoreClock = HSE_VALUE * pllmull;
+        }
+ #endif
+      }
+#else
+      pllmull = pllmull >> 18;
+      
+      if (pllmull != 0x0D)
+      {
+         pllmull += 2;
+      }
+      else
+      { /* PLL multiplication factor = PLL input clock * 6.5 */
+        pllmull = 13 / 2; 
+      }
+            
+      if (pllsource == 0x00)
+      {
+        /* HSI oscillator clock divided by 2 selected as PLL clock entry */
+        SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
+      }
+      else
+      {/* PREDIV1 selected as PLL clock entry */
+        
+        /* Get PREDIV1 clock source and division factor */
+        prediv1source = RCC->CFGR2 & RCC_CFGR2_PREDIV1SRC;
+        prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
+        
+        if (prediv1source == 0)
+        { 
+          /* HSE oscillator clock selected as PREDIV1 clock entry */
+          SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;          
+        }
+        else
+        {/* PLL2 clock selected as PREDIV1 clock entry */
+          
+          /* Get PREDIV2 division factor and PLL2 multiplication factor */
+          prediv2factor = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> 4) + 1;
+          pll2mull = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> 8 ) + 2; 
+          SystemCoreClock = (((HSE_VALUE / prediv2factor) * pll2mull) / prediv1factor) * pllmull;                         
+        }
+      }
+#endif /* STM32F10X_CL */ 
+      break;
+
+    default:
+      SystemCoreClock = HSI_VALUE;
+      break;
+  }
+  
+  /* Compute HCLK clock frequency ----------------*/
+  /* Get HCLK prescaler */
+  tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
+  /* HCLK clock frequency */
+  SystemCoreClock >>= tmp;  
+}
+
+/**
+  * @brief  Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
+  * @param  None
+  * @retval None
+  */
+static void SetSysClock(void)
+{
+#ifdef SYSCLK_FREQ_HSE
+  SetSysClockToHSE();
+#elif defined SYSCLK_FREQ_24MHz
+  SetSysClockTo24();
+#elif defined SYSCLK_FREQ_36MHz
+  SetSysClockTo36();
+#elif defined SYSCLK_FREQ_48MHz
+  SetSysClockTo48();
+#elif defined SYSCLK_FREQ_56MHz
+  SetSysClockTo56();  
+#elif defined SYSCLK_FREQ_72MHz
+  SetSysClockTo72();
+#endif
+ 
+ /* If none of the define above is enabled, the HSI is used as System clock
+    source (default after reset) */ 
+}
+
+/**
+  * @brief  Setup the external memory controller. Called in startup_stm32f10x.s 
+  *          before jump to __main
+  * @param  None
+  * @retval None
+  */ 
+#ifdef DATA_IN_ExtSRAM
+/**
+  * @brief  Setup the external memory controller. 
+  *         Called in startup_stm32f10x_xx.s/.c before jump to main.
+  * 	      This function configures the external SRAM mounted on STM3210E-EVAL
+  *         board (STM32 High density devices). This SRAM will be used as program
+  *         data memory (including heap and stack).
+  * @param  None
+  * @retval None
+  */ 
+void SystemInit_ExtMemCtl(void) 
+{
+/*!< FSMC Bank1 NOR/SRAM3 is used for the STM3210E-EVAL, if another Bank is 
+  required, then adjust the Register Addresses */
+
+  /* Enable FSMC clock */
+  RCC->AHBENR = 0x00000114;
+  
+  /* Enable GPIOD, GPIOE, GPIOF and GPIOG clocks */  
+  RCC->APB2ENR = 0x000001E0;
+  
+/* ---------------  SRAM Data lines, NOE and NWE configuration ---------------*/
+/*----------------  SRAM Address lines configuration -------------------------*/
+/*----------------  NOE and NWE configuration --------------------------------*/  
+/*----------------  NE3 configuration ----------------------------------------*/
+/*----------------  NBL0, NBL1 configuration ---------------------------------*/
+  
+  GPIOD->CRL = 0x44BB44BB;  
+  GPIOD->CRH = 0xBBBBBBBB;
+
+  GPIOE->CRL = 0xB44444BB;  
+  GPIOE->CRH = 0xBBBBBBBB;
+
+  GPIOF->CRL = 0x44BBBBBB;  
+  GPIOF->CRH = 0xBBBB4444;
+
+  GPIOG->CRL = 0x44BBBBBB;  
+  GPIOG->CRH = 0x44444B44;
+   
+/*----------------  FSMC Configuration ---------------------------------------*/  
+/*----------------  Enable FSMC Bank1_SRAM Bank ------------------------------*/
+  
+  FSMC_Bank1->BTCR[4] = 0x00001011;
+  FSMC_Bank1->BTCR[5] = 0x00000200;
+}
+#endif /* DATA_IN_ExtSRAM */
+
+#ifdef SYSCLK_FREQ_HSE
+/**
+  * @brief  Selects HSE as System clock source and configure HCLK, PCLK2
+  *          and PCLK1 prescalers.
+  * @note   This function should be used only after reset.
+  * @param  None
+  * @retval None
+  */
+static void SetSysClockToHSE(void)
+{
+  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+  
+  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
+  /* Enable HSE */    
+  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
+ 
+  /* Wait till HSE is ready and if Time out is reached exit */
+  do
+  {
+    HSEStatus = RCC->CR & RCC_CR_HSERDY;
+    StartUpCounter++;  
+  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
+  {
+    HSEStatus = (uint32_t)0x01;
+  }
+  else
+  {
+    HSEStatus = (uint32_t)0x00;
+  }  
+
+  if (HSEStatus == (uint32_t)0x01)
+  {
+
+#if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL
+    /* Enable Prefetch Buffer */
+    FLASH->ACR |= FLASH_ACR_PRFTBE;
+
+    /* Flash 0 wait state */
+    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
+
+#ifndef STM32F10X_CL
+    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
+#else
+    if (HSE_VALUE <= 24000000)
+	{
+      FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
+	}
+	else
+	{
+      FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
+	}
+#endif /* STM32F10X_CL */
+#endif
+ 
+    /* HCLK = SYSCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
+      
+    /* PCLK2 = HCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
+    
+    /* PCLK1 = HCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
+    
+    /* Select HSE as system clock source */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
+    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_HSE;    
+
+    /* Wait till HSE is used as system clock source */
+    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x04)
+    {
+    }
+  }
+  else
+  { /* If HSE fails to start-up, the application will have wrong clock 
+         configuration. User can add here some code to deal with this error */
+  }  
+}
+#elif defined SYSCLK_FREQ_24MHz
+/**
+  * @brief  Sets System clock frequency to 24MHz and configure HCLK, PCLK2 
+  *          and PCLK1 prescalers.
+  * @note   This function should be used only after reset.
+  * @param  None
+  * @retval None
+  */
+static void SetSysClockTo24(void)
+{
+  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+  
+  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
+  /* Enable HSE */    
+  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
+ 
+  /* Wait till HSE is ready and if Time out is reached exit */
+  do
+  {
+    HSEStatus = RCC->CR & RCC_CR_HSERDY;
+    StartUpCounter++;  
+  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
+  {
+    HSEStatus = (uint32_t)0x01;
+  }
+  else
+  {
+    HSEStatus = (uint32_t)0x00;
+  }  
+
+  if (HSEStatus == (uint32_t)0x01)
+  {
+#if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL 
+    /* Enable Prefetch Buffer */
+    FLASH->ACR |= FLASH_ACR_PRFTBE;
+
+    /* Flash 0 wait state */
+    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
+    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;    
+#endif
+ 
+    /* HCLK = SYSCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
+      
+    /* PCLK2 = HCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
+    
+    /* PCLK1 = HCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
+    
+#ifdef STM32F10X_CL
+    /* Configure PLLs ------------------------------------------------------*/
+    /* PLL configuration: PLLCLK = PREDIV1 * 6 = 24 MHz */ 
+    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
+    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
+                            RCC_CFGR_PLLMULL6); 
+
+    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
+    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */       
+    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
+                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
+    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
+                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
+  
+    /* Enable PLL2 */
+    RCC->CR |= RCC_CR_PLL2ON;
+    /* Wait till PLL2 is ready */
+    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
+    {
+    }   
+#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
+    /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
+    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLXTPRE_PREDIV1_Div2 | RCC_CFGR_PLLMULL6);
+#else    
+    /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
+    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL6);
+#endif /* STM32F10X_CL */
+
+    /* Enable PLL */
+    RCC->CR |= RCC_CR_PLLON;
+
+    /* Wait till PLL is ready */
+    while((RCC->CR & RCC_CR_PLLRDY) == 0)
+    {
+    }
+
+    /* Select PLL as system clock source */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
+    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
+
+    /* Wait till PLL is used as system clock source */
+    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
+    {
+    }
+  }
+  else
+  { /* If HSE fails to start-up, the application will have wrong clock 
+         configuration. User can add here some code to deal with this error */
+  } 
+}
+#elif defined SYSCLK_FREQ_36MHz
+/**
+  * @brief  Sets System clock frequency to 36MHz and configure HCLK, PCLK2 
+  *          and PCLK1 prescalers. 
+  * @note   This function should be used only after reset.
+  * @param  None
+  * @retval None
+  */
+static void SetSysClockTo36(void)
+{
+  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+  
+  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
+  /* Enable HSE */    
+  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
+ 
+  /* Wait till HSE is ready and if Time out is reached exit */
+  do
+  {
+    HSEStatus = RCC->CR & RCC_CR_HSERDY;
+    StartUpCounter++;  
+  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
+  {
+    HSEStatus = (uint32_t)0x01;
+  }
+  else
+  {
+    HSEStatus = (uint32_t)0x00;
+  }  
+
+  if (HSEStatus == (uint32_t)0x01)
+  {
+    /* Enable Prefetch Buffer */
+    FLASH->ACR |= FLASH_ACR_PRFTBE;
+
+    /* Flash 1 wait state */
+    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
+    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;    
+ 
+    /* HCLK = SYSCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
+      
+    /* PCLK2 = HCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
+    
+    /* PCLK1 = HCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
+    
+#ifdef STM32F10X_CL
+    /* Configure PLLs ------------------------------------------------------*/
+    
+    /* PLL configuration: PLLCLK = PREDIV1 * 9 = 36 MHz */ 
+    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
+    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
+                            RCC_CFGR_PLLMULL9); 
+
+	/*!< PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
+    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */
+        
+    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
+                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
+    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
+                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
+  
+    /* Enable PLL2 */
+    RCC->CR |= RCC_CR_PLL2ON;
+    /* Wait till PLL2 is ready */
+    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
+    {
+    }
+    
+#else    
+    /*  PLL configuration: PLLCLK = (HSE / 2) * 9 = 36 MHz */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
+    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL9);
+#endif /* STM32F10X_CL */
+
+    /* Enable PLL */
+    RCC->CR |= RCC_CR_PLLON;
+
+    /* Wait till PLL is ready */
+    while((RCC->CR & RCC_CR_PLLRDY) == 0)
+    {
+    }
+
+    /* Select PLL as system clock source */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
+    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
+
+    /* Wait till PLL is used as system clock source */
+    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
+    {
+    }
+  }
+  else
+  { /* If HSE fails to start-up, the application will have wrong clock 
+         configuration. User can add here some code to deal with this error */
+  } 
+}
+#elif defined SYSCLK_FREQ_48MHz
+/**
+  * @brief  Sets System clock frequency to 48MHz and configure HCLK, PCLK2 
+  *          and PCLK1 prescalers. 
+  * @note   This function should be used only after reset.
+  * @param  None
+  * @retval None
+  */
+static void SetSysClockTo48(void)
+{
+  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+  
+  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
+  /* Enable HSE */    
+  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
+ 
+  /* Wait till HSE is ready and if Time out is reached exit */
+  do
+  {
+    HSEStatus = RCC->CR & RCC_CR_HSERDY;
+    StartUpCounter++;  
+  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
+  {
+    HSEStatus = (uint32_t)0x01;
+  }
+  else
+  {
+    HSEStatus = (uint32_t)0x00;
+  }  
+
+  if (HSEStatus == (uint32_t)0x01)
+  {
+    /* Enable Prefetch Buffer */
+    FLASH->ACR |= FLASH_ACR_PRFTBE;
+
+    /* Flash 1 wait state */
+    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
+    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;    
+ 
+    /* HCLK = SYSCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
+      
+    /* PCLK2 = HCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
+    
+    /* PCLK1 = HCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
+    
+#ifdef STM32F10X_CL
+    /* Configure PLLs ------------------------------------------------------*/
+    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
+    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
+        
+    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
+                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
+    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
+                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
+  
+    /* Enable PLL2 */
+    RCC->CR |= RCC_CR_PLL2ON;
+    /* Wait till PLL2 is ready */
+    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
+    {
+    }
+    
+   
+    /* PLL configuration: PLLCLK = PREDIV1 * 6 = 48 MHz */ 
+    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
+    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
+                            RCC_CFGR_PLLMULL6); 
+#else    
+    /*  PLL configuration: PLLCLK = HSE * 6 = 48 MHz */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
+    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL6);
+#endif /* STM32F10X_CL */
+
+    /* Enable PLL */
+    RCC->CR |= RCC_CR_PLLON;
+
+    /* Wait till PLL is ready */
+    while((RCC->CR & RCC_CR_PLLRDY) == 0)
+    {
+    }
+
+    /* Select PLL as system clock source */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
+    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
+
+    /* Wait till PLL is used as system clock source */
+    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
+    {
+    }
+  }
+  else
+  { /* If HSE fails to start-up, the application will have wrong clock 
+         configuration. User can add here some code to deal with this error */
+  } 
+}
+
+#elif defined SYSCLK_FREQ_56MHz
+/**
+  * @brief  Sets System clock frequency to 56MHz and configure HCLK, PCLK2 
+  *          and PCLK1 prescalers. 
+  * @note   This function should be used only after reset.
+  * @param  None
+  * @retval None
+  */
+static void SetSysClockTo56(void)
+{
+  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+  
+  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/   
+  /* Enable HSE */    
+  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
+ 
+  /* Wait till HSE is ready and if Time out is reached exit */
+  do
+  {
+    HSEStatus = RCC->CR & RCC_CR_HSERDY;
+    StartUpCounter++;  
+  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
+  {
+    HSEStatus = (uint32_t)0x01;
+  }
+  else
+  {
+    HSEStatus = (uint32_t)0x00;
+  }  
+
+  if (HSEStatus == (uint32_t)0x01)
+  {
+    /* Enable Prefetch Buffer */
+    FLASH->ACR |= FLASH_ACR_PRFTBE;
+
+    /* Flash 2 wait state */
+    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
+    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;    
+ 
+    /* HCLK = SYSCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
+      
+    /* PCLK2 = HCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
+    
+    /* PCLK1 = HCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
+
+#ifdef STM32F10X_CL
+    /* Configure PLLs ------------------------------------------------------*/
+    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
+    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
+        
+    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
+                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
+    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
+                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
+  
+    /* Enable PLL2 */
+    RCC->CR |= RCC_CR_PLL2ON;
+    /* Wait till PLL2 is ready */
+    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
+    {
+    }
+    
+   
+    /* PLL configuration: PLLCLK = PREDIV1 * 7 = 56 MHz */ 
+    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
+    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
+                            RCC_CFGR_PLLMULL7); 
+#else     
+    /* PLL configuration: PLLCLK = HSE * 7 = 56 MHz */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
+    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL7);
+
+#endif /* STM32F10X_CL */
+
+    /* Enable PLL */
+    RCC->CR |= RCC_CR_PLLON;
+
+    /* Wait till PLL is ready */
+    while((RCC->CR & RCC_CR_PLLRDY) == 0)
+    {
+    }
+
+    /* Select PLL as system clock source */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
+    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
+
+    /* Wait till PLL is used as system clock source */
+    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
+    {
+    }
+  }
+  else
+  { /* If HSE fails to start-up, the application will have wrong clock 
+         configuration. User can add here some code to deal with this error */
+  } 
+}
+
+#elif defined SYSCLK_FREQ_72MHz
+/**
+  * @brief  Sets System clock frequency to 72MHz and configure HCLK, PCLK2 
+  *          and PCLK1 prescalers. 
+  * @note   This function should be used only after reset.
+  * @param  None
+  * @retval None
+  */
+static void SetSysClockTo72(void)
+{
+  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+  
+  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
+  /* Enable HSE */    
+  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
+ 
+  /* Wait till HSE is ready and if Time out is reached exit */
+  do
+  {
+    HSEStatus = RCC->CR & RCC_CR_HSERDY;
+    StartUpCounter++;  
+  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
+  {
+    HSEStatus = (uint32_t)0x01;
+  }
+  else
+  {
+    HSEStatus = (uint32_t)0x00;
+  }  
+
+  if (HSEStatus == (uint32_t)0x01)
+  {
+    /* Enable Prefetch Buffer */
+    FLASH->ACR |= FLASH_ACR_PRFTBE;
+
+    /* Flash 2 wait state */
+    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
+    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;    
+
+ 
+    /* HCLK = SYSCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
+      
+    /* PCLK2 = HCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
+    
+    /* PCLK1 = HCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
+
+#ifdef STM32F10X_CL
+    /* Configure PLLs ------------------------------------------------------*/
+    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
+    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
+        
+    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
+                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
+    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
+                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
+  
+    /* Enable PLL2 */
+    RCC->CR |= RCC_CR_PLL2ON;
+    /* Wait till PLL2 is ready */
+    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
+    {
+    }
+    
+   
+    /* PLL configuration: PLLCLK = PREDIV1 * 9 = 72 MHz */ 
+    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
+    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
+                            RCC_CFGR_PLLMULL9); 
+#else    
+    /*  PLL configuration: PLLCLK = HSE * 9 = 72 MHz */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE |
+                                        RCC_CFGR_PLLMULL));
+    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL9);
+#endif /* STM32F10X_CL */
+
+    /* Enable PLL */
+    RCC->CR |= RCC_CR_PLLON;
+
+    /* Wait till PLL is ready */
+    while((RCC->CR & RCC_CR_PLLRDY) == 0)
+    {
+    }
+    
+    /* Select PLL as system clock source */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
+    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
+
+    /* Wait till PLL is used as system clock source */
+    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
+    {
+    }
+  }
+  else
+  { /* If HSE fails to start-up, the application will have wrong clock 
+         configuration. User can add here some code to deal with this error */
+  }
+}
+#endif
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+  
+/**
+  * @}
+  */    
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/STM32_4路称重_Git提交精简工程/src/CMSIS/system_stm32f10x.h b/STM32_4路称重_Git提交精简工程/src/CMSIS/system_stm32f10x.h
new file mode 100755
index 0000000..739f332
--- /dev/null
+++ b/STM32_4路称重_Git提交精简工程/src/CMSIS/system_stm32f10x.h
@@ -0,0 +1,98 @@
+/**
+  ******************************************************************************
+  * @file    system_stm32f10x.h
+  * @author  MCD Application Team
+  * @version V3.5.0
+  * @date    11-March-2011
+  * @brief   CMSIS Cortex-M3 Device Peripheral Access Layer System Header File.
+  ******************************************************************************
+  * @attention
+  *
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+  *
+  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
+  ******************************************************************************
+  */
+
+/** @addtogroup CMSIS
+  * @{
+  */
+
+/** @addtogroup stm32f10x_system
+  * @{
+  */  
+  
+/**
+  * @brief Define to prevent recursive inclusion
+  */
+#ifndef __SYSTEM_STM32F10X_H
+#define __SYSTEM_STM32F10X_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif 
+
+/** @addtogroup STM32F10x_System_Includes
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+
+/** @addtogroup STM32F10x_System_Exported_types
+  * @{
+  */
+
+extern uint32_t SystemCoreClock;          /*!< System Clock Frequency (Core Clock) */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F10x_System_Exported_Constants
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F10x_System_Exported_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F10x_System_Exported_Functions
+  * @{
+  */
+  
+extern void SystemInit(void);
+extern void SystemCoreClockUpdate(void);
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__SYSTEM_STM32F10X_H */
+
+/**
+  * @}
+  */
+  
+/**
+  * @}
+  */  
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/STM32_4路称重_Git提交精简工程/src/HARDWARE/AUDIO/bsp_WM8978.h b/STM32_4路称重_Git提交精简工程/src/HARDWARE/AUDIO/bsp_WM8978.h
new file mode 100755
index 0000000..a036748
--- /dev/null
+++ b/STM32_4路称重_Git提交精简工程/src/HARDWARE/AUDIO/bsp_WM8978.h
@@ -0,0 +1,79 @@
+/*
+*********************************************************************************************************
+*	                                  
+*	ģ������ : WM8978��ƵоƬ����ģ��
+*	�ļ����� : bsp_WM8978.h
+*	��    �� : V1.0
+*	˵    �� : ͷ�ļ�
+*	�޸ļ�¼ :
+*		�汾��  ����       ����    ˵��
+*		v0.1    2009-12-27 armfly  �������ļ���ST�̼���汾ΪV3.1.2
+*		v1.0    2011-09-04 armfly  ST�̼���������V3.5.0�汾��
+*
+*	Copyright (C), 2010-2011, ���������� www.armfly.com
+*
+*********************************************************************************************************
+*/
+
+#ifndef _BSP_WM8978_H
+#define _BSP_WM8978_H
+
+#include <inttypes.h>
+
+#define WM8978_SLAVE_ADDRESS    0x34	/* WM8978 I2C�ӻ���ַ */
+
+/* WM8978 ��Ƶ����ͨ������ѡ��, ����ѡ���·������ MIC_LEFT_ON | LINE_ON */
+typedef enum
+{
+	IN_PATH_OFF		= 0x00,	/* ������ */
+	MIC_LEFT_ON 	= 0x01,	/* LIN,LIP�ţ�MIC���������Ӱ�����ͷ�� */
+	MIC_RIGHT_ON	= 0x02,	/* RIN,RIP�ţ�MIC����������GPRSģ����Ƶ����� */
+	LINE_ON			= 0x04, /* L2,R2 ���������� */
+	AUX_ON			= 0x08,	/* AUXL,AUXR ���������� */
+	DAC_ON			= 0x10,	/* I2S����DAC (CPU������Ƶ�ź�) */
+	ADC_ON			= 0x20	/* �������Ƶ����WM8978�ڲ�ADC ��I2S¼��) */
+}IN_PATH_E;
+
+/* WM8978 ��Ƶ���ͨ������ѡ��, ����ѡ���· */
+typedef enum
+{
+	OUT_PATH_OFF	= 0x00,	/* ����� */
+	EAR_LEFT_ON 	= 0x01,	/* LOUT1 ���������� */
+	EAR_RIGHT_ON	= 0x02,	/* ROUT1 ���������� */
+	SPK_ON			= 0x04,		/* LOUT2��ROUT2�������������,�������� */
+	OUT3_4_ON		= 0x08,	/* OUT3 �� OUT4 �����������Ƶ�� ��GSMģ�����Ƶ���� */
+}OUT_PATH_E;
+
+/* ����������� */
+#define VOLUME_MAX		63		/* ������� */
+#define VOLUME_STEP		1		/* �������ڲ��� */
+
+/* �������MIC���� */
+#define GAIN_MAX		63		/* ������� */
+#define GAIN_STEP		1		/* ���沽�� */
+
+
+/* ���ⲿ���õĺ������� */
+uint8_t wm8978_Init(void);
+void wm8978_CfgAudioIF(uint16_t _usStandard, uint8_t _ucWordLen);
+void wm8978_OutMute(uint8_t _ucMute);
+void wm8978_PowerDown(void);
+
+void wm8978_CfgAudioPath(uint16_t _InPath, uint16_t _OutPath);
+
+void wm8978_SetMicGain(uint8_t _ucGain);
+void wm8978_SetLineGain(uint8_t _ucGain);
+void wm8978_SetSpkVolume(uint8_t _ucVolume);
+void wm8978_SetEarVolume(uint8_t _ucVolume);
+uint8_t wm8978_ReadEarVolume(void);
+uint8_t wm8978_ReadSpkVolume(void);
+
+void wm8978_NotchFilter(uint16_t _NFA0, uint16_t _NFA1);
+
+void I2S_CODEC_Init(void);
+void I2S_StartPlay(uint16_t _usStandard, uint16_t _usWordLen, uint16_t _usAudioFreq);
+void I2S_StartRecord(uint16_t _usStandard, uint16_t _usWordLen, uint16_t _usAudioFreq);
+void I2S_Stop(void);
+
+void wm8978_RegCash_Output(void);
+#endif
diff --git a/STM32_4路称重_Git提交精简工程/src/HARDWARE/AUDIO/bsp_i2c_gpio.c b/STM32_4路称重_Git提交精简工程/src/HARDWARE/AUDIO/bsp_i2c_gpio.c
new file mode 100755
index 0000000..7a4adae
--- /dev/null
+++ b/STM32_4路称重_Git提交精简工程/src/HARDWARE/AUDIO/bsp_i2c_gpio.c
@@ -0,0 +1,232 @@
+/*************************** (C) COPYRIGHT 2018 PING ****************************
+ *  �ļ���  ��bsp_i2c_gpio.h
+ *  ��  ��  ��IO��ģ��I2C����
+ *  ��  ��  ��V1.0
+ *  ��  ��  ��2018-01-11
+ *  ��  ��  ��XuZhongPing 
+ * ���¼�¼ ��
+*********************************************************************************/
+
+#include "stm32f10x.h"
+#include "bsp_i2c_gpio.h"
+#include "delay.h"
+
+/* ����I2C�������ӵ�GPIO�˿�, �û�ֻ��Ҫ�޸�����4�д��뼴������ı�SCL��SDA������ */
+#define GPIO_PORT_I2C	GPIOD			/* GPIO�˿� */
+#define RCC_I2C_PORT 	RCC_APB2Periph_GPIOD		/* GPIO�˿�ʱ�� */
+#define I2C_SCL_PIN		GPIO_Pin_10			/* ���ӵ�SCLʱ���ߵ�GPIO */
+#define I2C_SDA_PIN		GPIO_Pin_9			/* ���ӵ�SDA�����ߵ�GPIO */
+
+
+static void i2c_CfgGpio(void);
+
+/*
+*********************************************************************************************************
+*	�� �� ��: i2c_Start
+*	����˵��: CPU����I2C���������ź�
+*	��    �Σ���
+*	�� �� ֵ: ��
+*********************************************************************************************************
+*/
+void i2c_Start(void)
+{
+	SDA_OUT();     		//sda�����
+	IIC_SDA=1;	  	  
+	IIC_SCL=1;
+	delay_us(4);
+ 	IIC_SDA=0;				//START:when CLK is high,DATA change form high to low 
+	delay_us(4);
+	IIC_SCL=0;				//ǯסI2C���ߣ�׼�����ͻ�������� 
+}
+
+/*
+*********************************************************************************************************
+*	�� �� ��: i2c_Start
+*	����˵��: CPU����I2C����ֹͣ�ź�
+*	��    �Σ���
+*	�� �� ֵ: ��
+*********************************************************************************************************
+*/
+void i2c_Stop(void)
+{
+	SDA_OUT();//sda�����
+	IIC_SCL=0;
+	IIC_SDA=0;//STOP:when CLK is high DATA change form low to high
+ 	delay_us(4);
+	IIC_SCL=1; 
+	IIC_SDA=1;//����I2C���߽����ź�
+	delay_us(4);	
+}
+
+/*
+*********************************************************************************************************
+*	�� �� ��: i2c_SendByte
+*	����˵��: CPU��I2C�����豸����8bit����
+*	��    �Σ�_ucByte �� �ȴ����͵��ֽ�
+*	�� �� ֵ: ��
+*********************************************************************************************************
+*/
+void i2c_SendByte(uint8_t _ucByte)
+{
+	uint8_t t;   
+	
+	SDA_OUT(); 	    
+	IIC_SCL = 0;					//����ʱ�ӿ�ʼ���ݴ���
+	for(t=0; t<8; t++)
+	{              
+			//IIC_SDA=(txd&0x80)>>7;
+	if((_ucByte&0x80)>>7)
+		IIC_SDA=1;
+	else
+		IIC_SDA=0;
+	_ucByte<<=1; 	  
+	delay_us(2);   				//��TEA5767��������ʱ���Ǳ����
+	IIC_SCL=1;
+	delay_us(2); 
+	IIC_SCL=0;	
+	delay_us(2);
+	}	
+}
+
+/*
+*********************************************************************************************************
+*	�� �� ��: i2c_ReadByte
+*	����˵��: CPU��I2C�����豸��ȡ8bit����
+*	��    �Σ���
+*	�� �� ֵ: ����������
+*********************************************************************************************************
+*/
+uint8_t i2c_ReadByte(void)
+{
+// 	unsigned char i,receive=0;
+// 	SDA_IN();//SDA����Ϊ����
+//     for(i=0;i<8;i++ )
+// 	{
+//         IIC_SCL=0; 
+//         delay_us(2);
+// 		IIC_SCL=1;
+//         receive<<=1;
+//         if(READ_SDA)receive++;   
+// 		delay_us(1); 
+//     }					 
+//     if (!ack)
+//         IIC_NAck();//����nACK
+//     else
+//         IIC_Ack(); //����ACK   
+//     return receive;
+}
+
+/*
+*********************************************************************************************************
+*	�� �� ��: i2c_WaitAck
+*	����˵��: CPU����һ��ʱ�ӣ�����ȡ������ACKӦ���ź�
+*	��    �Σ���
+*	�� �� ֵ: ����0��ʾ��ȷӦ��1��ʾ��������Ӧ
+*********************************************************************************************************
+*/
+uint8_t i2c_WaitAck(void)
+{
+	uint8_t ucErrTime=0;
+	SDA_IN();      //SDA����Ϊ����  
+	IIC_SDA=1;delay_us(1);	   
+	IIC_SCL=1;delay_us(1);	 
+	while(READ_SDA)
+	{
+		ucErrTime++;
+		if(ucErrTime>250)
+		{
+			i2c_Stop();
+			return 1;
+		}
+	}
+	IIC_SCL=0;//ʱ�����0 	   
+	return 0;
+}
+
+/*
+*********************************************************************************************************
+*	�� �� ��: i2c_Ack
+*	����˵��: CPU����һ��ACK�ź�
+*	��    �Σ���
+*	�� �� ֵ: ��
+*********************************************************************************************************
+*/
+void i2c_Ack(void)
+{
+	IIC_SCL=0;
+	SDA_OUT();
+	IIC_SDA=0;
+	delay_us(2);
+	IIC_SCL=1;
+	delay_us(2);
+	IIC_SCL=0;
+}
+
+/*
+*********************************************************************************************************
+*	�� �� ��: i2c_NAck
+*	����˵��: CPU����1��NACK�ź�
+*	��    �Σ���
+*	�� �� ֵ: ��
+*********************************************************************************************************
+*/
+void i2c_NAck(void)
+{
+	IIC_SCL=0;
+	SDA_OUT();
+	IIC_SDA=1;
+	delay_us(2);
+	IIC_SCL=1;
+	delay_us(2);
+	IIC_SCL=0;
+}
+
+/*
+*********************************************************************************************************
+*	�� �� ��: i2c_CfgGpio
+*	����˵��: ����I2C���ߵ�GPIO������ģ��IO�ķ�ʽʵ��
+*	��    �Σ���
+*	�� �� ֵ: ��
+*********************************************************************************************************
+*/
+static void i2c_CfgGpio(void)
+{
+	GPIO_InitTypeDef GPIO_InitStructure;
+
+	RCC_APB2PeriphClockCmd(RCC_I2C_PORT, ENABLE);	/* ��GPIOʱ�� */
+
+	GPIO_InitStructure.GPIO_Pin = I2C_SCL_PIN | I2C_SDA_PIN;
+	GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
+	GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP;  	/* ��©��� GPIO_Mode_Out_PP GPIO_Mode_Out_OD*/
+	GPIO_Init(GPIO_PORT_I2C, &GPIO_InitStructure);
+	
+	GPIO_SetBits(GPIO_PORT_I2C, I2C_SCL_PIN | I2C_SDA_PIN);
+
+	/* ��һ��ֹͣ�ź�, ��λI2C�����ϵ������豸������ģʽ */
+	i2c_Stop();
+}
+
+/*
+*********************************************************************************************************
+*	�� �� ��: i2c_CheckDevice
+*	����˵��: ���I2C�����豸��CPU�����豸��ַ��Ȼ���ȡ�豸Ӧ�����жϸ��豸�Ƿ����
+*	��    �Σ�_Address���豸��I2C���ߵ�ַ
+*	�� �� ֵ: ����ֵ 0 ��ʾ��ȷ�� ����1��ʾδ̽�⵽
+*********************************************************************************************************
+*/
+uint8_t i2c_CheckDevice(uint8_t _Address)
+{
+	uint8_t ucAck;
+
+	i2c_CfgGpio();		/* ����GPIO */
+	
+	i2c_Start();		/* ���������ź� */
+
+	/* �����豸��ַ+��д����bit��0 = w�� 1 = r) bit7 �ȴ� */
+	i2c_SendByte(_Address | I2C_WR);
+	ucAck = i2c_WaitAck();	/* ����豸��ACKӦ�� */
+
+	i2c_Stop();			/* ����ֹͣ�ź� */
+
+	return ucAck;
+}
diff --git a/STM32_4路称重_Git提交精简工程/src/HARDWARE/AUDIO/bsp_i2c_gpio.h b/STM32_4路称重_Git提交精简工程/src/HARDWARE/AUDIO/bsp_i2c_gpio.h
new file mode 100755
index 0000000..ab9beeb
--- /dev/null
+++ b/STM32_4路称重_Git提交精简工程/src/HARDWARE/AUDIO/bsp_i2c_gpio.h
@@ -0,0 +1,44 @@
+/*
+*********************************************************************************************************
+*	                                  
+*	ģ������ : I2C��������ģ��
+*	�ļ����� : bsp_i2c_gpio.h
+*	��    �� : V1.0
+*	˵    �� : ͷ�ļ���
+*	�޸ļ�¼ :
+*		�汾��  ����       ����    ˵��
+*		v1.0    2011-08-21 armfly  ST�̼���������V3.5.0�汾��
+*
+*	Copyright (C), 2010-2011, ���������� www.armfly.com
+*
+*********************************************************************************************************
+*/
+
+#ifndef _BSP_I2C_GPIO_H
+#define _BSP_I2C_GPIO_H
+
+#include <inttypes.h>
+#include "stm32f10x.h"
+
+#define I2C_WR	0		/* д����bit */
+#define I2C_RD	1		/* ������bit */
+
+//IO��������
+#define SDA_IN()  {GPIOD->CRH&=0XFFFFFF0F;GPIOD->CRH|=8<<4;}
+#define SDA_OUT() {GPIOD->CRH&=0XFFFFFF0F;GPIOD->CRH|=3<<4;}
+
+//IO��������	 
+#define IIC_SCL    PDout(10) //SCL
+#define IIC_SDA    PDout(9) //SDA	 
+#define READ_SDA   PDin(9)  //����SDA 
+
+void i2c_Start(void);
+void i2c_Stop(void);
+void i2c_SendByte(uint8_t _ucByte);
+uint8_t i2c_ReadByte(void);
+uint8_t i2c_WaitAck(void);
+void i2c_Ack(void);
+void i2c_NAck(void);
+uint8_t i2c_CheckDevice(uint8_t _Address);
+
+#endif
diff --git a/STM32_4路称重_Git提交精简工程/src/HARDWARE/AUDIO/bsp_wm8978.c b/STM32_4路称重_Git提交精简工程/src/HARDWARE/AUDIO/bsp_wm8978.c
new file mode 100755
index 0000000..ed3db52
--- /dev/null
+++ b/STM32_4路称重_Git提交精简工程/src/HARDWARE/AUDIO/bsp_wm8978.c
@@ -0,0 +1,1103 @@
+/*
+*********************************************************************************************************
+*	                                  
+*	ģ������ : WM8978��ƵоƬ����ģ��
+*	�ļ����� : bsp_WM8978.c
+*	��    �� : V1.0
+*	˵    �� : WM8978��ƵоƬ��STM32 I2S�ײ��������ڰ�����STM32�������ϵ���ͨ����
+*	�޸ļ�¼ :
+*		�汾��  ����       ����    ˵��
+*		v0.1    2009-12-27 armfly  �������ļ���ST�̼���汾ΪV3.1.2
+*		v1.0    2011-09-11 armfly  ʵ��I2S������¼�����ã�ST�̼���������V3.5.0�汾��
+*
+*	Copyright (C), 2010-2011, ���������� www.armfly.com
+*
+*********************************************************************************************************
+*/
+
+#include "stm32f10x.h"
+#include "bsp_WM8978.h"
+#include "bsp_i2c_gpio.h"
+#include "usart.h"
+
+/*
+*********************************************************************************************************
+*
+*	��Ҫ��ʾ:
+*	1��wm8978_ ��ͷ�ĺ����ǲ���WM8978�Ĵ���������WM8978�Ĵ�����ͨ��I2Cģ�����߽��е�
+*	2��I2S_ ��ͷ�ĺ����ǲ���STM32  I2S��ؼĴ���
+*	3��ʵ��¼�������Ӧ�ã���Ҫͬʱ����WM8978��STM32��I2S��
+*	4�����ֺ����õ����βεĶ�����ST�̼����У����磺I2S_Standard_Phillips��I2S_Standard_MSB��I2S_Standard_LSB
+*			  I2S_MCLKOutput_Enable��I2S_MCLKOutput_Disable
+*			  I2S_AudioFreq_8K��I2S_AudioFreq_16K��I2S_AudioFreq_22K��I2S_AudioFreq_44K��I2S_AudioFreq_48
+*			  I2S_Mode_MasterTx��I2S_Mode_MasterRx
+*	5��ע���� pdf ָ���� wm8978.pdf �����ֲᣬwm8978de�Ĵ����ܶ࣬�õ��ļĴ�����ע��pdf�ļ���ҳ�룬���ڲ�ѯ
+*
+*********************************************************************************************************
+*/
+
+/* ���ڱ�ģ���ڲ�ʹ�õľֲ����� */
+static uint16_t wm8978_ReadReg(uint8_t _ucRegAddr);
+static uint8_t wm8978_WriteReg(uint8_t _ucRegAddr, uint16_t _usValue);
+static void I2S_GPIO_Config(void);
+static void I2S_Mode_Config(uint16_t _usStandard, uint16_t _usWordLen, uint16_t _usAudioFreq, uint16_t _usMode);
+static void I2S_NVIC_Config(void);
+static void wm8978_CfgInOut(uint8_t _ucDacEn, uint8_t _ucAuxEn, uint8_t _ucLineEn, uint8_t _ucSpkEn, uint8_t _ucEarEn);
+static void wm8978_CtrlGPIO1(uint8_t _ucValue);
+static void wm8978_Reset(void);
+static void wm8978_CfgAdc(uint8_t _ucMicEn, uint8_t _ucAuxEn, uint8_t _ucLineEn);
+
+/*
+	wm8978�Ĵ�������
+	����WM8978��I2C���߽ӿڲ�֧�ֶ�ȡ��������˼Ĵ���ֵ�������ڴ��У���д�Ĵ���ʱͬ�����»��棬���Ĵ���ʱ
+	ֱ�ӷ��ػ����е�ֵ��
+	�Ĵ���MAP ��WM8978.pdf �ĵ�67ҳ���Ĵ�����ַ��7bit�� �Ĵ���������9bit
+*/
+static uint16_t wm8978_RegCash[] = {
+	0x000, 0x000, 0x000, 0x000, 0x050, 0x000, 0x140, 0x000,
+	0x000, 0x000, 0x000, 0x0FF, 0x0FF, 0x000, 0x100, 0x0FF,
+	0x0FF, 0x000, 0x12C, 0x02C, 0x02C, 0x02C, 0x02C, 0x000,
+	0x032, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000,
+	0x038, 0x00B, 0x032, 0x000, 0x008, 0x00C, 0x093, 0x0E9,
+	0x000, 0x000, 0x000, 0x000, 0x003, 0x010, 0x010, 0x100,
+	0x100, 0x002, 0x001, 0x001, 0x039, 0x039, 0x039, 0x039,
+	0x001, 0x001
+};
+
+/*
+*********************************************************************************************************
+*	�� �� ��: wm8978_Init
+*	����˵��: ����I2C GPIO�������I2C�����ϵ�WM8978�Ƿ�����
+*	��    �Σ���
+*	�� �� ֵ: 1 ��ʾ��ʼ��������0��ʾ��ʼ��������
+*********************************************************************************************************
+*/
+uint8_t wm8978_Init(void)
+{
+	uint8_t re;
+	
+	if (i2c_CheckDevice(WM8978_SLAVE_ADDRESS) == 0)	/* �������������STM32��GPIO��������ģ��I2Cʱ�� */
+	{
+		re = 1;
+	}
+	else
+	{
+		re = 0;
+	}
+	wm8978_Reset();			/* Ӳ����λWM8978���мĴ�����ȱʡ״̬ */
+	return re;
+}
+
+/*
+*********************************************************************************************************
+*	�� �� ��: wm8978_SetEarVolume
+*	����˵��: �޸Ķ����������
+*	��    ��:  _ucLeftVolume ������������ֵ, 0-63
+*			  _ucLRightVolume : ����������ֵ,0-63
+*	�� �� ֵ: ��
+*********************************************************************************************************
+*/
+void wm8978_SetEarVolume(uint8_t _ucVolume)
+{
+	uint16_t regL;
+	uint16_t regR;
+
+	if (_ucVolume > 0x3F)
+	{
+		_ucVolume = 0x3F;
+	}
+
+	regL = _ucVolume;
+	regR = _ucVolume;
+
+	/*
+		R52	LOUT1 Volume control
+		R53	ROUT1 Volume control
+	*/
+	/* �ȸ�������������ֵ */
+	wm8978_WriteReg(52, regL | 0x00);
+
+	/* ��ͬ�������������������� */
+	wm8978_WriteReg(53, regR | 0x100);	/* 0x180��ʾ ������Ϊ0ʱ�ٸ��£���������������ֵġ����ա��� */
+}
+
+/*
+*********************************************************************************************************
+*	�� �� ��: wm8978_SetSpkVolume
+*	����˵��: �޸��������������
+*	��    ��:  _ucLeftVolume ������������ֵ, 0-63
+*			  _ucLRightVolume : ����������ֵ,0-63
+*	�� �� ֵ: ��
+*********************************************************************************************************
+*/
+void wm8978_SetSpkVolume(uint8_t _ucVolume)
+{
+	uint16_t regL;
+	uint16_t regR;
+
+	if (_ucVolume > 0x3F)
+	{
+		_ucVolume = 0x3F;
+	}
+
+	regL = _ucVolume;
+	regR = _ucVolume;
+
+	/*
+		R54	LOUT2 (SPK) Volume control
+		R55	ROUT2 (SPK) Volume control
+	*/
+	/* �ȸ�������������ֵ */
+	wm8978_WriteReg(54, regL | 0x00);
+
+	/* ��ͬ�������������������� */
+	wm8978_WriteReg(55, regR | 0x100);	/* ������Ϊ0ʱ�ٸ��£���������������ֵġ����ա��� */
+}
+
+/*
+*********************************************************************************************************
+*	�� �� ��: wm8978_ReadEarVolume
+*	����˵��: ���ض���ͨ��������.
+*	��    ��:  ��
+*	�� �� ֵ: ��ǰ����ֵ
+*********************************************************************************************************
+*/
+uint8_t wm8978_ReadEarVolume(void)
+{
+	return (uint8_t)(wm8978_ReadReg(52) & 0x3F );
+}
+
+/*
+*********************************************************************************************************
+*	�� �� ��: wm8978_ReadSpkVolume
+*	����˵��: ����������ͨ��������.
+*	��    ��:  ��
+*	�� �� ֵ: ��ǰ����ֵ
+*********************************************************************************************************
+*/
+uint8_t wm8978_ReadSpkVolume(void)
+{
+	return (uint8_t)(wm8978_ReadReg(54) & 0x3F );
+}
+
+/*
+*********************************************************************************************************
+*	�� �� ��: wm8978_OutMute
+*	����˵��: �������.
+*	��    ��:  _ucMute ��1�Ǿ�����0�ǲ�����.
+*	�� �� ֵ: ��ǰ����ֵ
+*********************************************************************************************************
+*/
+void wm8978_OutMute(uint8_t _ucMute)
+{
+	uint16_t usRegValue;
+
+	if (_ucMute == 1) /* ���� */
+	{
+		usRegValue = wm8978_ReadReg(52); /* Left Mixer Control */
+		usRegValue |= (1u << 6);
+		wm8978_WriteReg(52, usRegValue);
+
+		usRegValue = wm8978_ReadReg(53); /* Left Mixer Control */
+		usRegValue |= (1u << 6);
+		wm8978_WriteReg(53, usRegValue);
+
+		usRegValue = wm8978_ReadReg(54); /* Right Mixer Control */
+		usRegValue |= (1u << 6);
+		wm8978_WriteReg(54, usRegValue);
+
+		usRegValue = wm8978_ReadReg(55); /* Right Mixer Control */
+		usRegValue |= (1u << 6);
+		wm8978_WriteReg(55, usRegValue);
+	}
+	else	/* ȡ������ */
+	{
+		usRegValue = wm8978_ReadReg(52);
+		usRegValue &= ~(1u << 6);
+		wm8978_WriteReg(52, usRegValue);
+
+		usRegValue = wm8978_ReadReg(53); /* Left Mixer Control */
+		usRegValue &= ~(1u << 6);
+		wm8978_WriteReg(53, usRegValue);
+
+		usRegValue = wm8978_ReadReg(54);
+		usRegValue &= ~(1u << 6);
+		wm8978_WriteReg(54, usRegValue);
+
+		usRegValue = wm8978_ReadReg(55); /* Left Mixer Control */
+		usRegValue &= ~(1u << 6);
+		wm8978_WriteReg(55, usRegValue);
+	}
+}
+
+/*
+*********************************************************************************************************
+*	�� �� ��: wm8978_SetMicGain
+*	����˵��: ����MIC����
+*	��    ��:  _ucGain ������ֵ, 0-63
+*	�� �� ֵ: ��
+*********************************************************************************************************
+*/
+void wm8978_SetMicGain(uint8_t _ucGain)
+{
+	if (_ucGain > GAIN_MAX)
+	{
+		_ucGain = GAIN_MAX;
+	}
+
+	/* PGA ��������  R45�� R46   pdf 19ҳ
+		Bit8	INPPGAUPDATE
+		Bit7	INPPGAZCL		�����ٸ���
+		Bit6	INPPGAMUTEL		PGA����
+		Bit5:0	����ֵ��010000��0dB
+	*/
+	wm8978_WriteReg(45, _ucGain);
+	wm8978_WriteReg(46, _ucGain | (1 << 8));
+}
+
+/*
+*********************************************************************************************************
+*	�� �� ��: wm8978_SetLineGain
+*	����˵��: ����Line����ͨ��������
+*	��    ��:  _ucGain ������ֵ, 0-7. 7���0��С�� ��˥���ɷŴ�
+*	�� �� ֵ: ��
+*********************************************************************************************************
+*/
+void wm8978_SetLineGain(uint8_t _ucGain)
+{
+	uint16_t usRegValue;
+
+	if (_ucGain > 7)
+	{
+		_ucGain = 7;
+	}
+
+	/*
+		Mic �����ŵ��������� PGABOOSTL �� PGABOOSTR ����
+		Aux �����ŵ������������� AUXL2BOOSTVO[2:0] �� AUXR2BOOSTVO[2:0] ����
+		Line �����ŵ��������� LIP2BOOSTVOL[2:0] �� RIP2BOOSTVOL[2:0] ����
+	*/
+	/*	pdf 21ҳ��R47������������R48����������, MIC ������ƼĴ���
+		R47 (R48���������ͬ)
+		B8		PGABOOSTL	= 1,   0��ʾMIC�ź�ֱͨ�����棬1��ʾMIC�ź�+20dB���棨ͨ���Ծٵ�·��
+		B7		= 0�� ����
+		B6:4	L2_2BOOSTVOL = x�� 0��ʾ��ֹ��1-7��ʾ����-12dB ~ +6dB  ������˥��Ҳ���ԷŴ�
+		B3		= 0�� ����
+		B2:0`	AUXL2BOOSTVOL = x��0��ʾ��ֹ��1-7��ʾ����-12dB ~ +6dB  ������˥��Ҳ���ԷŴ�
+	*/
+
+	usRegValue = wm8978_ReadReg(47);
+	usRegValue &= 0x8F;/* ��Bit6:4��0   1000 1111*/
+	usRegValue |= (_ucGain << 4);
+	wm8978_WriteReg(47, usRegValue);	/* д����������������ƼĴ��� */
+
+	usRegValue = wm8978_ReadReg(48);
+	usRegValue &= 0x8F;/* ��Bit6:4��0   1000 1111*/
+	usRegValue |= (_ucGain << 4);
+	wm8978_WriteReg(48, usRegValue);	/* д����������������ƼĴ��� */
+}
+
+/*
+*********************************************************************************************************
+*	�� �� ��: wm8978_PowerDown
+*	����˵��: �ر�wm8978������͹���ģʽ
+*	��    ��:  ��
+*	�� �� ֵ: ��
+*********************************************************************************************************
+*/
+void wm8978_PowerDown(void)
+{
+	wm8978_Reset();			/* Ӳ����λWM8978���мĴ�����ȱʡ״̬ */
+}
+
+/*
+*********************************************************************************************************
+*	�� �� ��: wm8978_CfgAudioIF
+*	����˵��: ����WM8978����Ƶ�ӿ�(I2S)
+*	��    ��:
+*			  _usStandard : �ӿڱ�׼��I2S_Standard_Phillips, I2S_Standard_MSB �� I2S_Standard_LSB
+*			  _ucWordLen : �ֳ���16��24��32  �����������õ�20bit��ʽ��
+*			  _usMode : CPU I2S�Ĺ���ģʽ��I2S_Mode_MasterTx��I2S_Mode_MasterRx��
+*						������������Ӳ����֧�� I2S_Mode_SlaveTx��I2S_Mode_SlaveRx ģʽ������ҪWM8978����
+*						�ⲿ����
+*	�� �� ֵ: ��
+*********************************************************************************************************
+*/
+void wm8978_CfgAudioIF(uint16_t _usStandard, uint8_t _ucWordLen)
+{
+	uint16_t usReg;
+
+	/* pdf 67ҳ���Ĵ����б� */
+
+	/*	REG R4, ��Ƶ�ӿڿ��ƼĴ���
+		B8		BCP	 = X, BCLK���ԣ�0��ʾ������1��ʾ����
+		B7		LRCP = x, LRCʱ�Ӽ��ԣ�0��ʾ������1��ʾ����
+		B6:5	WL = x�� �ֳ���00=16bit��01=20bit��10=24bit��11=32bit ���Ҷ���ģʽֻ�ܲ��������24bit)
+		B4:3	FMT = x����Ƶ���ݸ�ʽ��00=�Ҷ��룬01=����룬10=I2S��ʽ��11=PCM
+		B2		DACLRSWAP = x, ����DAC���ݳ�����LRCʱ�ӵ���߻����ұ�
+		B1 		ADCLRSWAP = x������ADC���ݳ�����LRCʱ�ӵ���߻����ұ�
+		B0		MONO	= 0��0��ʾ��������1��ʾ������������������Ч
+	*/
+	usReg = 0;
+	if (_usStandard == I2S_Standard_Phillips)	/* I2S�����ֱ�׼ */
+	{
+		usReg |= (2 << 3);
+	}
+	else if (_usStandard == I2S_Standard_MSB)	/* MSB�����׼(�����) */
+	{
+		usReg |= (1 << 3);
+	}
+	else if (_usStandard == I2S_Standard_LSB)	/* LSB�����׼(�Ҷ���) */
+	{
+		usReg |= (0 << 3);
+	}
+	else	/* PCM��׼(16λͨ��֡�ϴ������֡ͬ������16λ����֡��չΪ32λͨ��֡) */
+	{
+		usReg |= (3 << 3);;
+	}
+
+	if (_ucWordLen == 24)
+	{
+		usReg |= (2 << 5);
+	}
+	else if (_ucWordLen == 32)
+	{
+		usReg |= (3 << 5);
+	}
+	else
+	{
+		usReg |= (0 << 5);		/* 16bit */
+	}
+	wm8978_WriteReg(4, usReg);
+
+	/* R5  pdf 57ҳ */
+
+
+	/*
+		R6��ʱ�Ӳ������ƼĴ���
+		MS = 0,  WM8978����ʱ�ӣ���MCU�ṩMCLKʱ��
+	*/
+	wm8978_WriteReg(6, 0x000);
+}
+
+/*
+*********************************************************************************************************
+*	�� �� ��: wm8978_ReadReg
+*	����˵��: ��cash�ж��ض���wm8978�Ĵ���
+*	��    �Σ�_ucRegAddr �� �Ĵ�����ַ
+*	�� �� ֵ: ��
+*********************************************************************************************************
+*/
+static uint16_t wm8978_ReadReg(uint8_t _ucRegAddr)
+{
+	return wm8978_RegCash[_ucRegAddr];
+}
+
+/*
+*********************************************************************************************************
+*	�� �� ��: wm8978_WriteReg
+*	����˵��: дwm8978�Ĵ���
+*	��    �Σ�_ucRegAddr �� �Ĵ�����ַ
+*			  _usValue ���Ĵ���ֵ
+*	�� �� ֵ: ��
+*********************************************************************************************************
+*/
+static uint8_t wm8978_WriteReg(uint8_t _ucRegAddr, uint16_t _usValue)
+{
+	uint8_t ucAck;
+
+	/* ������ʼλ */
+	i2c_Start();
+
+	/* �����豸��ַ+��д����bit��0 = w�� 1 = r) bit7 �ȴ� */
+	i2c_SendByte(WM8978_SLAVE_ADDRESS | I2C_WR);
+
+	/* ���ACK */
+	ucAck = i2c_WaitAck();
+	if (ucAck == 1)
+	{
+		return 0;
+	}
+
+	/* ���Ϳ����ֽ�1 */
+	i2c_SendByte(((_ucRegAddr << 1) & 0xFE) | ((_usValue >> 8) & 0x1));
+
+	/* ���ACK */
+	ucAck = i2c_WaitAck();
+	if (ucAck == 1)
+	{
+		return 0;
+	}
+
+	/* ���Ϳ����ֽ�2 */
+	i2c_SendByte(_usValue & 0xFF);
+
+	/* ���ACK */
+	ucAck = i2c_WaitAck();
+	if (ucAck == 1)
+	{
+		return 0;
+	}
+
+	/* ����STOP */
+	i2c_Stop();
+
+	wm8978_RegCash[_ucRegAddr] = _usValue;
+	return 1;
+}
+
+/*
+*********************************************************************************************************
+*	�� �� ��: wm8978_CfgInOut
+*	����˵��: ����wm8978��Ƶͨ��
+*	��    ��:
+*			_InPath : ��Ƶ����ͨ������
+*			_OutPath : ��Ƶ���ͨ������
+*	�� �� ֵ: ��
+*********************************************************************************************************
+*/
+void wm8978_CfgAudioPath(uint16_t _InPath, uint16_t _OutPath)
+{
+	uint16_t usReg;
+
+	/* �鿴WM8978�����ֲ�� REGISTER MAP �½ڣ� ��67ҳ */
+
+	if ((_InPath == IN_PATH_OFF) && (_OutPath == OUT_PATH_OFF))
+	{
+		wm8978_PowerDown();
+		return;
+	}
+
+	/* --------------------------- ��1������������ͨ���������üĴ��� -----------------------*/
+	/*
+		R1 �Ĵ��� Power manage 1
+		Bit8    BUFDCOPEN,  Output stage 1.5xAVDD/2 driver enable
+ 		Bit7    OUT4MIXEN, OUT4 mixer enable
+		Bit6    OUT3MIXEN, OUT3 mixer enable
+		Bit5    PLLEN	.����
+		Bit4    MICBEN	,Microphone Bias Enable (MICƫ�õ�·ʹ��)
+		Bit3    BIASEN	,Analogue amplifier bias control ��������Ϊ1ģ��Ŵ����Ź���
+		Bit2    BUFIOEN , Unused input/output tie off buffer enable
+		Bit1:0  VMIDSEL, ��������Ϊ��00ֵģ��Ŵ����Ź���
+	*/
+	usReg = (1 << 3) | (3 << 0);
+	if (_OutPath & OUT3_4_ON) 	/* OUT3��OUT4ʹ�������GSMģ�� */
+	{
+		usReg |= ((1 << 7) | (1 << 6));
+	}
+	if ((_InPath & MIC_LEFT_ON) || (_InPath & MIC_RIGHT_ON))
+	{
+		usReg |= (1 << 4);
+	}
+	wm8978_WriteReg(1, usReg);	/* д�Ĵ��� */
+
+	/*
+		R2 �Ĵ��� Power manage 2
+		Bit8	ROUT1EN,	ROUT1 output enable �������������ʹ��
+		Bit7	LOUT1EN,	LOUT1 output enable �������������ʹ��
+		Bit6	SLEEP, 		0 = Normal device operation   1 = Residual current reduced in device standby mode
+		Bit5	BOOSTENR,	Right channel Input BOOST enable ����ͨ���Ծٵ�·ʹ��. �õ�PGA�Ŵ���ʱ����ʹ��
+		Bit4	BOOSTENL,	Left channel Input BOOST enable
+		Bit3	INPGAENR,	Right channel input PGA enable ����������PGAʹ��
+		Bit2	INPGAENL,	Left channel input PGA enable
+		Bit1	ADCENR,		Enable ADC right channel
+		Bit0	ADCENL,		Enable ADC left channel
+	*/
+	usReg = 0;
+	if (_OutPath & EAR_LEFT_ON)
+	{
+		usReg |= (1 << 7);
+	}
+	if (_OutPath & EAR_RIGHT_ON)
+	{
+		usReg |= (1 << 8);
+	}
+	if (_InPath & MIC_LEFT_ON)
+	{
+		usReg |= ((1 << 4) | (1 << 2));
+	}
+	if (_InPath & MIC_RIGHT_ON)
+	{
+		usReg |= ((1 << 5) | (1 << 3));
+	}
+	if (_InPath & LINE_ON)
+	{
+		usReg |= ((1 << 4) | (1 << 5));
+	}
+	if (_InPath & MIC_RIGHT_ON)
+	{
+		usReg |= ((1 << 5) | (1 << 3));
+	}
+	if (_InPath & ADC_ON)
+	{
+		usReg |= ((1 << 1) | (1 << 0));
+	}
+	wm8978_WriteReg(2, usReg);	/* д�Ĵ��� */
+
+	/*
+		R3 �Ĵ��� Power manage 3
+		Bit8	OUT4EN,		OUT4 enable
+		Bit7	OUT3EN,		OUT3 enable
+		Bit6	LOUT2EN,	LOUT2 output enable
+		Bit5	ROUT2EN,	ROUT2 output enable
+		Bit4	0,
+		Bit3	RMIXEN,		Right mixer enable
+		Bit2	LMIXEN,		Left mixer enable
+		Bit1	DACENR,		Right channel DAC enable
+		Bit0	DACENL,		Left channel DAC enable
+	*/
+	usReg = 0;
+	if (_OutPath & OUT3_4_ON)
+	{
+		usReg |= ((1 << 8) | (1 << 7));
+	}
+	if (_OutPath & SPK_ON)
+	{
+		usReg |= ((1 << 6) | (1 << 5));
+	}
+	if (_OutPath != OUT_PATH_OFF)
+	{
+		usReg |= ((1 << 3) | (1 << 2));
+	}
+	if (_InPath & DAC_ON)
+	{
+		usReg |= ((1 << 1) | (1 << 0));
+	}
+	wm8978_WriteReg(3, usReg);	/* д�Ĵ��� */
+
+	/*
+		R44 �Ĵ��� Input ctrl
+
+		Bit8	MBVSEL, 		Microphone Bias Voltage Control   0 = 0.9 * AVDD   1 = 0.6 * AVDD
+		Bit7	0
+		Bit6	R2_2INPPGA,		Connect R2 pin to right channel input PGA positive terminal
+		Bit5	RIN2INPPGA,		Connect RIN pin to right channel input PGA negative terminal
+		Bit4	RIP2INPPGA,		Connect RIP pin to right channel input PGA amplifier positive terminal
+		Bit3	0
+		Bit2	L2_2INPPGA,		Connect L2 pin to left channel input PGA positive terminal
+		Bit1	LIN2INPPGA,		Connect LIN pin to left channel input PGA negative terminal
+		Bit0	LIP2INPPGA,		Connect LIP pin to left channel input PGA amplifier positive terminal
+	*/
+	usReg = 0 << 8;
+	if (_InPath & LINE_ON)
+	{
+		usReg |= ((1 << 6) | (1 << 2));
+	}
+	if (_InPath & MIC_RIGHT_ON)
+	{
+		usReg |= ((1 << 5) | (1 << 4));
+	}
+	if (_InPath & MIC_LEFT_ON)
+	{
+		usReg |= ((1 << 1) | (1 << 0));
+	}
+	wm8978_WriteReg(44, usReg);	/* д�Ĵ��� */
+
+
+	/*
+		R14 �Ĵ��� ADC Control
+		���ø�ͨ�˲�������ѡ�ģ� pdf 24��25ҳ,
+		Bit8 	HPFEN,	High Pass Filter Enable��ͨ�˲���ʹ�ܣ�0��ʾ��ֹ��1��ʾʹ��
+		BIt7 	HPFAPP,	Select audio mode or application mode ѡ����Ƶģʽ��Ӧ��ģʽ��0��ʾ��Ƶģʽ��
+		Bit6:4	HPFCUT��Application mode cut-off frequency  000-111ѡ��Ӧ��ģʽ�Ľ�ֹƵ��
+		Bit3 	ADCOSR,	ADC oversample rate select: 0=64x (lower power) 1=128x (best performance)
+		Bit2   	0
+		Bit1 	ADC right channel polarity adjust:  0=normal  1=inverted
+		Bit0 	ADC left channel polarity adjust:  0=normal 1=inverted
+	*/
+	if (_InPath & ADC_ON)
+	{
+		usReg = (1 << 3) | (0 << 8) | (4 << 0);		/* ��ֹADC��ͨ�˲���, ���ý���Ƶ�� */
+	}
+	else
+	{
+		usReg = 0;
+	}
+	wm8978_WriteReg(14, usReg);	/* д�Ĵ��� */
+
+	/* �����ݲ��˲�����notch filter������Ҫ�������ƻ�Ͳ����������������Х��.  ��ʱ�ر�
+		R27��R28��R29��R30 ���ڿ����޲��˲�����pdf 26ҳ
+		R7�� Bit7 NFEN = 0 ��ʾ��ֹ��1��ʾʹ��
+	*/
+	if (_InPath & ADC_ON)
+	{
+		usReg = (0 << 7);
+		wm8978_WriteReg(27, usReg);	/* д�Ĵ��� */
+		usReg = 0;
+		wm8978_WriteReg(28, usReg);	/* д�Ĵ���,��0����Ϊ�Ѿ���ֹ������Ҳ�ɲ��� */
+		wm8978_WriteReg(29, usReg);	/* д�Ĵ���,��0����Ϊ�Ѿ���ֹ������Ҳ�ɲ��� */
+		wm8978_WriteReg(30, usReg);	/* д�Ĵ���,��0����Ϊ�Ѿ���ֹ������Ҳ�ɲ��� */
+	}
+
+	/* �Զ�������� ALC, R32  - 34  pdf 19ҳ */
+	{
+		usReg = 0;		/* ��ֹ�Զ�������� */
+		wm8978_WriteReg(32, usReg);
+		wm8978_WriteReg(33, usReg);
+		wm8978_WriteReg(34, usReg);
+	}
+
+	/*  R35  ALC Noise Gate Control
+		Bit3	NGATEN, Noise gate function enable
+		Bit2:0	Noise gate threshold:
+	*/
+	usReg = (3 << 1) | (7 << 0);		/* ��ֹ�Զ�������� */
+	wm8978_WriteReg(35, usReg);
+
+	/*
+		Mic �����ŵ��������� PGABOOSTL �� PGABOOSTR ����
+		Aux �����ŵ������������� AUXL2BOOSTVO[2:0] �� AUXR2BOOSTVO[2:0] ����
+		Line �����ŵ��������� LIP2BOOSTVOL[2:0] �� RIP2BOOSTVOL[2:0] ����
+	*/
+	/*	pdf 21ҳ��R47������������R48����������, MIC ������ƼĴ���
+		R47 (R48���������ͬ)
+		B8		PGABOOSTL	= 1,   0��ʾMIC�ź�ֱͨ�����棬1��ʾMIC�ź�+20dB���棨ͨ���Ծٵ�·��
+		B7		= 0�� ����
+		B6:4	L2_2BOOSTVOL = x�� 0��ʾ��ֹ��1-7��ʾ����-12dB ~ +6dB  ������˥��Ҳ���ԷŴ�
+		B3		= 0�� ����
+		B2:0`	AUXL2BOOSTVOL = x��0��ʾ��ֹ��1-7��ʾ����-12dB ~ +6dB  ������˥��Ҳ���ԷŴ�
+	*/
+	usReg = 0;
+	if ((_InPath & MIC_LEFT_ON) || (_InPath & MIC_RIGHT_ON))
+	{
+		usReg |= (1 << 8);	/* MIC����ȡ+20dB */
+	}
+	if (_InPath & AUX_ON)
+	{
+		usReg |= (3 << 0);	/* Aux����̶�ȡ3���û��������е��� */
+	}
+	if (_InPath & LINE_ON)
+	{
+		usReg |= (3 << 4);	/* Line����̶�ȡ3���û��������е��� */
+	}
+	wm8978_WriteReg(47, usReg);	/* д����������������ƼĴ��� */
+	wm8978_WriteReg(48, usReg);	/* д����������������ƼĴ��� */
+
+	/* ����ADC�������ƣ�pdf 27ҳ
+		R15 ����������ADC������R16����������ADC����
+		Bit8 	ADCVU  = 1 ʱ�Ÿ��£�����ͬ����������������ADC����
+		Bit7:0 	����ѡ�� 0000 0000 = ����
+						   0000 0001 = -127dB
+						   0000 0010 = -12.5dB  ��0.5dB ������
+						   1111 1111 = 0dB  ����˥����
+	*/
+	usReg = 0xFF;
+	wm8978_WriteReg(15, usReg);	/* ѡ��0dB���Ȼ��������� */
+	usReg = 0x1FF;
+	wm8978_WriteReg(16, usReg);	/* ͬ�������������� */
+
+	/* ͨ�� wm8978_SetMicGain ��������mic PGA���� */
+
+	/*	R43 �Ĵ���  AUXR �C ROUT2 BEEP Mixer Function
+		B8:6 = 0
+
+		B5	 MUTERPGA2INV,	Mute input to INVROUT2 mixer
+		B4	 INVROUT2,  Invert ROUT2 output �����������������
+		B3:1 BEEPVOL = 7;	AUXR input to ROUT2 inverter gain
+		B0	 BEEPEN = 1;	Enable AUXR beep input
+
+	*/
+	usReg = 0;
+	if (_OutPath & SPK_ON)
+	{
+		usReg |= (1 << 4);	/* ROUT2 ����, �������������� */
+	}
+	if (_InPath & AUX_ON)
+	{
+		usReg |= ((7 << 1) | (1 << 0));
+	}
+	wm8978_WriteReg(43, usReg);
+
+	/* R49  Output ctrl
+		B8:7	0
+		B6		DACL2RMIX,	Left DAC output to right output mixer
+		B5		DACR2LMIX,	Right DAC output to left output
+		B4		OUT4BOOST,	0 = OUT4 output gain = -1; DC = AVDD / 2��1 = OUT4 output gain = +1.5��DC = 1.5 x AVDD / 2
+		B3		OUT3BOOST,	0 = OUT3 output gain = -1; DC = AVDD / 2��1 = OUT3 output gain = +1.5��DC = 1.5 x AVDD / 2
+		B2		SPKBOOST,	0 = Speaker gain = -1;  DC = AVDD / 2 ; 1 = Speaker gain = +1.5; DC = 1.5 x AVDD / 2
+		B1		TSDEN,   Thermal Shutdown Enable  �������ȱ���ʹ�ܣ�ȱʡ1��
+		B0		VROI,	Disabled Outputs to VREF Resistance
+	*/
+	usReg = 0;
+	if (_InPath & DAC_ON)
+	{
+		usReg |= ((1 << 6) | (1 << 5));
+	}
+	if (_OutPath & SPK_ON)
+	{
+		usReg |=  ((1 << 2) | (1 << 1));	/* SPK 1.5x����,  �ȱ���ʹ�� */
+	}
+	if (_OutPath & OUT3_4_ON)
+	{
+		usReg |=  ((1 << 4) | (1 << 3));	/* BOOT3  BOOT4  1.5x���� */
+	}
+	wm8978_WriteReg(49, usReg);
+
+	/*	REG 50    (50����������51�������������üĴ�������һ��) pdf 40ҳ
+		B8:6	AUXLMIXVOL = 111	AUX����FM�������ź�����
+		B5		AUXL2LMIX = 1		Left Auxilliary input to left channel
+		B4:2	BYPLMIXVOL			����
+		B1		BYPL2LMIX = 0;		Left bypass path (from the left channel input boost output) to left output mixer
+		B0		DACL2LMIX = 1;		Left DAC output to left output mixer
+	*/
+	usReg = 0;
+	if (_InPath & AUX_ON)
+	{
+		usReg |= ((7 << 6) | (1 << 5));
+	}
+	if ((_InPath & LINE_ON) || (_InPath & MIC_LEFT_ON) || (_InPath & MIC_RIGHT_ON))
+	{
+		usReg |= ((7 << 2) | (1 << 1));
+	}
+	if (_InPath & DAC_ON)
+	{
+		usReg |= (1 << 0);
+	}
+	wm8978_WriteReg(50, usReg);
+	wm8978_WriteReg(51, usReg);
+
+	/*	R56 �Ĵ���   OUT3 mixer ctrl
+		B8:7	0
+		B6		OUT3MUTE,  	0 = Output stage outputs OUT3 mixer;  1 = Output stage muted �C drives out VMID.
+		B5:4	0
+		B3		BYPL2OUT3,	OUT4 mixer output to OUT3  (����)
+		B4		0
+		B2		LMIX2OUT3,	Left ADC input to OUT3
+		B1		LDAC2OUT3,	Left DAC mixer to OUT3
+		B0		LDAC2OUT3,	Left DAC output to OUT3
+	*/
+	usReg = 0;
+	if (_OutPath & OUT3_4_ON)
+	{
+		usReg |= (1 << 3);
+	}
+	wm8978_WriteReg(56, usReg);
+
+	/* R57 �Ĵ���		OUT4 (MONO) mixer ctrl
+		B8:7	0
+		B6		OUT4MUTE,	0 = Output stage outputs OUT4 mixer  1 = Output stage muted �C drives outVMID.
+		B5		HALFSIG,	0 = OUT4 normal output	1 = OUT4 attenuated by 6dB
+		B4		LMIX2OUT4,	Left DAC mixer to OUT4
+		B3		LDAC2UT4,	Left DAC to OUT4
+		B2		BYPR2OUT4,	Right ADC input to OUT4
+		B1		RMIX2OUT4,	Right DAC mixer to OUT4
+		B0		RDAC2OUT4,	Right DAC output to OUT4
+	*/
+	usReg = 0;
+	if (_OutPath & OUT3_4_ON)
+	{
+		usReg |= ((1 << 4) |  (1 << 1));
+	}
+	wm8978_WriteReg(57, usReg);
+
+
+	/* R11, 12 �Ĵ��� DAC��������
+		R11		Left DAC Digital Volume
+		R12		Right DAC Digital Volume
+	*/
+	if (_InPath & DAC_ON)
+	{
+		wm8978_WriteReg(11, 255);
+		wm8978_WriteReg(12, 255 | 0x100);
+	}
+	else
+	{
+		wm8978_WriteReg(11, 0);
+		wm8978_WriteReg(12, 0 | 0x100);
+	}
+
+	/*	R10 �Ĵ��� DAC Control
+		B8	0
+		B7	0
+		B6	SOFTMUTE,	Softmute enable:
+		B5	0
+		B4	0
+		B3	DACOSR128,	DAC oversampling rate: 0=64x (lowest power) 1=128x (best performance)
+		B2	AMUTE,		Automute enable
+		B1	DACPOLR,	Right DAC output polarity
+		B0	DACPOLL,	Left DAC output polarity:
+	*/
+	if (_InPath & DAC_ON)
+	{
+		wm8978_WriteReg(10, 0);
+	}
+	;
+}
+
+/*
+*********************************************************************************************************
+*	�� �� ��: wm8978_NotchFilter
+*	����˵��: �����ݲ��˲�����notch filter������Ҫ�������ƻ�Ͳ����������������Х��
+*	��    ��:  NFA0[13:0] and NFA1[13:0]
+*	�� �� ֵ: ��
+*********************************************************************************************************
+*/
+void wm8978_NotchFilter(uint16_t _NFA0, uint16_t _NFA1)
+{
+	uint16_t usReg;
+
+	/*  page 26
+		A programmable notch filter is provided. This filter has a variable centre frequency and bandwidth,
+		programmable via two coefficients, a0 and a1. a0 and a1 are represented by the register bits
+		NFA0[13:0] and NFA1[13:0]. Because these coefficient values require four register writes to setup
+		there is an NFU (Notch Filter Update) flag which should be set only when all four registers are setup.
+	*/
+	usReg = (1 << 7) | (_NFA0 & 0x3F);
+	wm8978_WriteReg(27, usReg);	/* д�Ĵ��� */
+
+	usReg = ((_NFA0 >> 7) & 0x3F);
+	wm8978_WriteReg(28, usReg);	/* д�Ĵ��� */
+
+	usReg = (_NFA1 & 0x3F);
+	wm8978_WriteReg(29, usReg);	/* д�Ĵ��� */
+
+	usReg = (1 << 8) | ((_NFA1 >> 7) & 0x3F);
+	wm8978_WriteReg(30, usReg);	/* д�Ĵ��� */
+}
+
+/*
+*********************************************************************************************************
+*	�� �� ��: wm8978_CtrlGPIO1
+*	����˵��: ����WM8978��GPIO1�������0��1
+*	��    �Σ�_ucValue ��GPIO1���ֵ��0��1
+*	�� �� ֵ: ��ǰ����ֵ
+*********************************************************************************************************
+*/
+static void wm8978_CtrlGPIO1(uint8_t _ucValue)
+{
+	uint16_t usRegValue;
+
+	/* R8�� pdf 62ҳ */
+	if (_ucValue == 0) /* ���0 */
+	{
+		usRegValue = 6; /* B2:0 = 110 */
+	}
+	else
+	{
+		usRegValue = 7; /* B2:0 = 111 */	
+	}
+	wm8978_WriteReg(8, usRegValue);
+}
+
+/*
+*********************************************************************************************************
+*	�� �� ��: wm8978_Reset
+*	����˵��: ��λwm8978�����еļĴ���ֵ�ָ���ȱʡֵ
+*	��    �Σ���
+*	�� �� ֵ: ��
+*********************************************************************************************************
+*/
+static void wm8978_Reset(void)
+{
+	/* wm8978�Ĵ���ȱʡֵ */
+	const uint16_t reg_default[] = {
+	0x000, 0x000, 0x000, 0x000, 0x050, 0x000, 0x140, 0x000,
+	0x000, 0x000, 0x000, 0x0FF, 0x0FF, 0x000, 0x100, 0x0FF,
+	0x0FF, 0x000, 0x12C, 0x02C, 0x02C, 0x02C, 0x02C, 0x000,
+	0x032, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000,
+	0x038, 0x00B, 0x032, 0x000, 0x008, 0x00C, 0x093, 0x0E9,
+	0x000, 0x000, 0x000, 0x000, 0x003, 0x010, 0x010, 0x100,
+	0x100, 0x002, 0x001, 0x001, 0x039, 0x039, 0x039, 0x039,
+	0x001, 0x001
+	};
+	uint8_t i;
+
+	wm8978_WriteReg(0x00, 0);
+
+	for (i = 0; i < sizeof(reg_default) / 2; i++)
+	{
+		wm8978_RegCash[i] = reg_default[i];
+	}
+}
+
+/*
+*********************************************************************************************************
+*	                     ����Ĵ����Ǻ�STM32 I2SӲ����ص�
+*********************************************************************************************************
+*/
+
+/*
+*********************************************************************************************************
+*	�� �� ��: I2S_CODEC_Init
+*	����˵��: ����GPIO���ź��ж�ͨ������codecӦ��
+*	��    �Σ���
+*	�� �� ֵ: ��
+*********************************************************************************************************
+*/
+void I2S_CODEC_Init(void)
+{
+	/* ����I2S�ж�ͨ�� */
+	I2S_NVIC_Config(); 
+	
+	/* ����I2S2 GPIO���� */
+	I2S_GPIO_Config(); 
+
+	/* ��ֹI2S2 TXE�ж�(���ͻ�������)����Ҫʱ�ٴ� */ 
+	SPI_I2S_ITConfig(SPI2, SPI_I2S_IT_TXE, DISABLE);
+		
+	/* ��ֹI2S2 RXNE�ж�(���ղ���)����Ҫʱ�ٴ� */ 
+	SPI_I2S_ITConfig(SPI2, SPI_I2S_IT_RXNE, DISABLE);
+}
+
+/*
+*********************************************************************************************************
+*	�� �� ��: I2S_StartPlay
+*	����˵��: ����I2S����ģʽ������I2S���ͻ��������жϣ���ʼ����
+*	��    �Σ�_usStandard : �ӿڱ�׼��I2S_Standard_Phillips, I2S_Standard_MSB �� I2S_Standard_LSB
+*			  _usMCLKOutput : ��ʱ�������I2S_MCLKOutput_Enable or I2S_MCLKOutput_Disable
+*			  _usAudioFreq : ����Ƶ�ʣ�I2S_AudioFreq_8K��I2S_AudioFreq_16K��I2S_AudioFreq_22K��
+*							I2S_AudioFreq_44K��I2S_AudioFreq_48
+*	�� �� ֵ: ��
+*********************************************************************************************************
+*/
+void I2S_StartPlay(uint16_t _usStandard, uint16_t _usWordLen, uint16_t _usAudioFreq)
+{
+	/* ����I2SΪ������ģʽ����STM32�ṩ��ʱ�ӣ�I2S���ݿ��Ƿ��ͷ���(����) */
+	I2S_Mode_Config(_usStandard, _usWordLen, _usAudioFreq, I2S_Mode_MasterTx);
+
+	SPI_I2S_ITConfig(SPI2, SPI_I2S_IT_TXE, ENABLE);		/* ʹ�ܷ����ж� */
+}
+
+/*
+*********************************************************************************************************
+*	�� �� ��: I2S_Stop
+*	����˵��: ֹͣI2S����
+*	��    �Σ���
+*	�� �� ֵ: ��
+*********************************************************************************************************
+*/
+void I2S_Stop(void)
+{
+	/* ��ֹI2S2 TXE�ж�(���ͻ�������)����Ҫʱ�ٴ� */ 
+	SPI_I2S_ITConfig(SPI2, SPI_I2S_IT_TXE, DISABLE);
+		
+	/* ��ֹI2S2 RXNE�ж�(���ղ���)����Ҫʱ�ٴ� */ 
+	SPI_I2S_ITConfig(SPI2, SPI_I2S_IT_RXNE, DISABLE);
+		
+	/* ���� SPI2/I2S2 ���� */
+	I2S_Cmd(SPI2, DISABLE);
+
+	/* �ر� I2S2 APB1 ʱ�� */
+	RCC_APB1PeriphClockCmd(RCC_APB1Periph_SPI2, ENABLE);
+}
+
+
+/*
+*********************************************************************************************************
+*	�� �� ��: I2S_GPIO_Config
+*	����˵��: ����GPIO��������codecӦ��
+*	��    �Σ���
+*	�� �� ֵ: ��
+*********************************************************************************************************
+*/
+static void I2S_GPIO_Config(void)
+{
+	GPIO_InitTypeDef GPIO_InitStructure;
+	
+	/* Enable GPIOB, GPIOC and AFIO clock */
+	RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOB | RCC_APB2Periph_GPIOC | RCC_APB2Periph_GPIOG | 
+	                     RCC_APB2Periph_GPIOF | RCC_APB2Periph_AFIO, ENABLE);
+	
+	/* I2S2 SD, CK and WS pins configuration */
+	GPIO_InitStructure.GPIO_Pin = GPIO_Pin_12 | GPIO_Pin_13 | GPIO_Pin_15;
+	GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
+	GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
+	GPIO_Init(GPIOB, &GPIO_InitStructure);
+	
+	/* I2S2 MCK pin configuration */
+	GPIO_InitStructure.GPIO_Pin = GPIO_Pin_6;
+	GPIO_Init(GPIOC, &GPIO_InitStructure);
+}
+
+/*
+*********************************************************************************************************
+*	�� �� ��: I2S_Config
+*	����˵��: ����STM32��I2S���蹤��ģʽ
+*	��    �Σ�_usStandard : �ӿڱ�׼��I2S_Standard_Phillips, I2S_Standard_MSB �� I2S_Standard_LSB
+*			  _usMCLKOutput : ��ʱ�������I2S_MCLKOutput_Enable or I2S_MCLKOutput_Disable
+*			  _usAudioFreq : ����Ƶ�ʣ�I2S_AudioFreq_8K��I2S_AudioFreq_16K��I2S_AudioFreq_22K��
+*							I2S_AudioFreq_44K��I2S_AudioFreq_48
+*			  _usMode : CPU I2S�Ĺ���ģʽ��I2S_Mode_MasterTx��I2S_Mode_MasterRx��
+*						������������Ӳ����֧�� I2S_Mode_SlaveTx��I2S_Mode_SlaveRx ģʽ������ҪWM8978����
+*						�ⲿ����
+*	�� �� ֵ: ��
+*********************************************************************************************************
+*/
+static void I2S_Mode_Config(uint16_t _usStandard, uint16_t _usWordLen, uint16_t _usAudioFreq, uint16_t _usMode)
+{
+	I2S_InitTypeDef I2S_InitStructure; 
+
+	if ((_usMode == I2S_Mode_SlaveTx) && (_usMode == I2S_Mode_SlaveRx))
+	{
+		/* �����������岻֧����2��ģʽ */
+		return;
+	}
+
+	/* �� I2S2 APB1 ʱ�� */
+	RCC_APB1PeriphClockCmd(RCC_APB1Periph_SPI2, ENABLE);
+	
+	/* ��λ SPI2 ���赽ȱʡ״̬ */
+	SPI_I2S_DeInit(SPI2); 
+		
+	/* I2S2 �������� */
+	if (_usMode == I2S_Mode_MasterTx)
+	{
+		I2S_InitStructure.I2S_Mode = I2S_Mode_MasterTx;			/* ����I2S����ģʽ */
+		I2S_InitStructure.I2S_Standard = _usStandard;			/* �ӿڱ�׼ */
+		I2S_InitStructure.I2S_DataFormat = _usWordLen;			/* ���ݸ�ʽ��16bit */
+		I2S_InitStructure.I2S_MCLKOutput = I2S_MCLKOutput_Enable;	/* ��ʱ��ģʽ */
+		I2S_InitStructure.I2S_AudioFreq = _usAudioFreq;			/* ��Ƶ����Ƶ�� */
+		I2S_InitStructure.I2S_CPOL = I2S_CPOL_Low;  			
+		I2S_Init(SPI2, &I2S_InitStructure);
+	}
+	else if (_usMode == I2S_Mode_MasterRx)
+	{
+		I2S_InitStructure.I2S_Mode = I2S_Mode_MasterRx;			/* ����I2S����ģʽ */
+		I2S_InitStructure.I2S_Standard = _usStandard;			/* �ӿڱ�׼ */
+		I2S_InitStructure.I2S_DataFormat = _usWordLen;			/* ���ݸ�ʽ��16bit */
+		I2S_InitStructure.I2S_MCLKOutput = I2S_MCLKOutput_Enable;	/* ��ʱ��ģʽ */
+		I2S_InitStructure.I2S_AudioFreq = _usAudioFreq;			/* ��Ƶ����Ƶ�� */
+		I2S_InitStructure.I2S_CPOL = I2S_CPOL_Low;  			
+		I2S_Init(SPI2, &I2S_InitStructure);
+	}
+
+	/* ��ֹI2S2 TXE�ж�(���ͻ�������)����Ҫʱ�ٴ� */ 
+	SPI_I2S_ITConfig(SPI2, SPI_I2S_IT_TXE, DISABLE);
+		
+	/* ��ֹI2S2 RXNE�ж�(���ղ���)����Ҫʱ�ٴ� */ 
+	SPI_I2S_ITConfig(SPI2, SPI_I2S_IT_RXNE, DISABLE);
+	
+	/* ʹ�� SPI2/I2S2 ���� */
+	I2S_Cmd(SPI2, ENABLE);
+}
+
+/*
+*********************************************************************************************************
+*	�� �� ��: I2S_NVIC_Config
+*	����˵��: ����I2S NVICͨ��(�ж�ģʽ)���жϷ�����void SPI2_IRQHandler(void) ��stm32f10x_it.c
+*	��    �Σ���
+*	�� �� ֵ: ��
+*********************************************************************************************************
+*/
+static void I2S_NVIC_Config(void)
+{
+	NVIC_InitTypeDef NVIC_InitStructure;
+	
+	/* SPI2 IRQ ͨ������ */
+	NVIC_InitStructure.NVIC_IRQChannel = SPI2_IRQn;
+	NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 2;
+	NVIC_InitStructure.NVIC_IRQChannelSubPriority = 2;
+	NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
+	NVIC_Init(&NVIC_InitStructure);
+}
+
+void wm8978_RegCash_Output(void)
+{
+	uint8_t i;
+	for(i = 0; i < 58; i++)
+	{
+		printf("0x%04X, ", wm8978_RegCash[i]);
+	}
+}
+
+/***************************** (END OF FILE) *********************************/
diff --git a/STM32_4路称重_Git提交精简工程/src/HARDWARE/AUDIO/sound.c b/STM32_4路称重_Git提交精简工程/src/HARDWARE/AUDIO/sound.c
new file mode 100755
index 0000000..534b615
--- /dev/null
+++ b/STM32_4路称重_Git提交精简工程/src/HARDWARE/AUDIO/sound.c
@@ -0,0 +1,198 @@
+/*************************** (C) COPYRIGHT 2018 PING ****************************
+ *  �ļ���  ��sound.h
+ *  ��  ��  �������������Ƴ���
+ *  ��  ��  ��V1.0
+ *  ��  ��  ��2016-01-11
+ *  ��  ��  ��XuZhongPing 
+ * ���¼�¼ ��
+*********************************************************************************/
+#include "sound.h"
+#include "delay.h"
+#include "timer.h"
+#include "usart1.h"
+#include "stdio.h"
+#include "string.h"	
+
+#define SPEAKER_PORT_PeriphClock 		RCC_APB2Periph_GPIOB  | RCC_APB2Periph_AFIO
+#define SPEAKER_PORT								GPIOB
+#define SPEAKER_CTRL_PIN						GPIO_Pin_3
+
+uint8_t audioOutputMark = 0;							//��־�Ƿ��������
+uint8_t audioNum = 0;											//�������
+uint8_t audioOutputStatus = 0;						//��Ƶ���״̬
+
+/*
+***********************************************************************
+*	�� �� ��: SpeakerInit
+*	����˵��: ���������ƽӿڳ�ʼ��
+*	��    �Σ���
+*	�� �� ֵ: ��
+***********************************************************************
+*/
+void SpeakerInit(void)
+{
+ 	GPIO_InitTypeDef GPIO_InitStructure;
+ 	RCC_APB2PeriphClockCmd(SPEAKER_PORT_PeriphClock, ENABLE);				//ʹ��ʱ��
+
+	GPIO_PinRemapConfig(GPIO_Remap_SWJ_JTAGDisable , ENABLE);				//�ر�JTAG��PB3,PB4���ù���
+
+	GPIO_InitStructure.GPIO_Pin = SPEAKER_CTRL_PIN;				 				
+	GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP;
+	GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
+	GPIO_Init(SPEAKER_PORT, &GPIO_InitStructure);
+	
+	GPIO_ResetBits(SPEAKER_PORT, SPEAKER_CTRL_PIN);
+}
+
+/*
+***********************************************************************
+*	�� �� ��: AudioInit
+*	����˵��: ��Ƶ��س�ʼ��
+*	��    �Σ���
+*	�� �� ֵ: ��
+***********************************************************************
+*/
+void Audio_Init(void)
+{
+	SpeakerInit();
+	Audio_SetVolume(20);
+}
+
+/*
+***********************************************************************
+*	�� �� ��: Audio_OutputEnable
+*	����˵��: ��Ƶ���ʹ��
+*	��    �Σ���
+*	�� �� ֵ: ��
+***********************************************************************
+*/
+static void Audio_OutputEnable(void)
+{
+	GPIO_SetBits(SPEAKER_PORT, SPEAKER_CTRL_PIN);
+	audioOutputStatus = 1;
+}
+
+/*
+***********************************************************************
+*	�� �� ��: Audio_OutputDisable
+*	����˵��: ��Ƶ���ʧ��
+*	��    �Σ���
+*	�� �� ֵ: ��
+***********************************************************************
+*/
+static void Audio_OutputDisable(void)
+{
+	GPIO_ResetBits(SPEAKER_PORT, SPEAKER_CTRL_PIN);
+	audioOutputStatus = 0;
+}
+
+/*
+***********************************************************************
+*	�� �� ��: Audio_SetVolume
+*	����˵��: ������Ƶ����
+*	��    �Σ�val -> ����ֵ
+*	�� �� ֵ: ��
+***********************************************************************
+*/
+void Audio_SetVolume(uint8_t volume)
+{
+	char str[32];
+	
+	if (volume<=30 && volume>=1)
+	{
+		sprintf(str, "AF:%d", volume);
+		USART1_SendFrameData((uint8_t*)str, strlen(str));
+	}
+}
+
+/*
+***********************************************************************
+*	�� �� ��: Audio_Play
+*	����˵��: ����ָ����Ƶ
+*	��    �Σ�num -> �������
+*	�� �� ֵ: ��
+***********************************************************************
+*/
+void Audio_PlayOutput(uint8_t num)
+{
+	char str[32];
+	
+	sprintf(str, "A7:%05d", num);
+	Audio_OutputEnable();																//ʹ���������
+	USART1_SendFrameData((uint8_t*)str, strlen(str));
+}
+
+/*
+***********************************************************************
+*	�� �� ��: Audio_Play
+*	����˵��: ����ָ����Ƶ
+*	��    �Σ�num -> �������
+*	�� �� ֵ: ��
+***********************************************************************
+*/
+void Audio_Play(uint8_t num)
+{
+	audioOutputMark = 1;
+	audioNum = num;
+}
+
+/*
+***********************************************************************
+*	�� �� ��: Audio_Play
+*	����˵��: ����ָ����Ƶ
+*	��    �Σ�num -> �������
+*	�� �� ֵ: ��
+***********************************************************************
+*/
+void Audio_PlayTask(void)
+{
+	static uint8_t RunningStatus = 0x00;
+	
+	static timer waitingTimer;
+	static uint8_t timer_ok = 0;
+	
+	if(timer_ok == 0)
+	{
+		timer_ok = 1;
+		timer_set(&waitingTimer, CLOCK_SECOND*5);
+	}
+	
+	switch(RunningStatus)
+	{
+		case 0x00:
+			if(audioOutputMark == 1)
+			{
+				audioOutputMark = 0;
+				Audio_PlayOutput(audioNum);
+				timer_restart(&waitingTimer);
+				RunningStatus = 0x01;
+				break;
+			}
+			break;
+			
+		case 0x01:
+			if(audioOutputMark == 1)
+			{
+				RunningStatus = 0x00;
+				break;
+			}
+			
+			if(timer_expired(&waitingTimer))
+      {
+				printf("\r\nֹͣ���ţ�\r\n");
+				Audio_OutputDisable();								//�ر��������
+				RunningStatus = 0x00;
+				break;
+			}
+			break;
+			
+		case 0x02:
+			break;
+			
+		default:
+			RunningStatus = 0x00;
+			break;
+	}
+}
+
+/******************** (C) COPYRIGHT 2014 GLHF *****END OF FILE*******************/	 
diff --git a/STM32_4路称重_Git提交精简工程/src/HARDWARE/AUDIO/sound.h b/STM32_4路称重_Git提交精简工程/src/HARDWARE/AUDIO/sound.h
new file mode 100755
index 0000000..98a91a8
--- /dev/null
+++ b/STM32_4路称重_Git提交精简工程/src/HARDWARE/AUDIO/sound.h
@@ -0,0 +1,28 @@
+/*************************** (C) COPYRIGHT 2014 GLHF ****************************
+ *  �ļ���  ��sound.h
+ *  ��  ��  ��������������ͷ�ļ�
+ *  ��  ��  ��V1.0
+ *  ��  ��  ��2016-01-11
+ *  ��  ��  ��XuZhongPing 
+ * ���¼�¼ ��
+*********************************************************************************/
+#ifndef __SOUND_H
+#define __SOUND_H
+#include "stm32f10x.h"
+#include "stdio.h"
+
+extern uint8_t audioOutputMark;							//��־�Ƿ��������
+extern uint8_t audioNum;										//�������
+extern uint8_t audioOutputStatus;						//��Ƶ���״̬
+
+void AudioInit(void);
+void VoiceBroadcast (uint8_t number);  	
+
+void Audio_Init(void);
+void Audio_SetVolume(uint8_t volume);
+void Audio_Play(uint8_t num);
+void Audio_PlayTask(void);
+	 
+#endif
+
+/******************** (C) COPYRIGHT 2014 GLHF *****END OF FILE*******************/
diff --git a/STM32_4路称重_Git提交精简工程/src/HARDWARE/AUDIO/soundfilelists.h b/STM32_4路称重_Git提交精简工程/src/HARDWARE/AUDIO/soundfilelists.h
new file mode 100755
index 0000000..4d04992
--- /dev/null
+++ b/STM32_4路称重_Git提交精简工程/src/HARDWARE/AUDIO/soundfilelists.h
@@ -0,0 +1,15 @@
+#ifndef __SOUNDFILELIST_H
+#define __SOUNDFILELIST_H
+#include "stm32f10x.h"
+
+const uint32_t SOUND_FILE_LIST[5][2] = {
+	/*������ַ  ����*/
+	{0x00002C, 0x0088BC},				//00������Ϣ
+	{0x0088E8, 0x00F898},				//01������Ϣ
+	{0x018180, 0x0151F8},			//02������Ϣ
+	{0x02D378, 0x01701A},			//03������Ϣ
+	{0x044392, 0x032E5C}				//04������Ϣ
+};
+   																     		 
+#endif
+
diff --git a/STM32_4路称重_Git提交精简工程/src/HARDWARE/BUZZER/buzzer.c b/STM32_4路称重_Git提交精简工程/src/HARDWARE/BUZZER/buzzer.c
new file mode 100755
index 0000000..17cdc17
--- /dev/null
+++ b/STM32_4路称重_Git提交精简工程/src/HARDWARE/BUZZER/buzzer.c
@@ -0,0 +1,669 @@
+/*************************** (C) COPYRIGHT 2017 CXHY ****************************
+ * �ļ���  ��buzzer.c
+ * ��  ��  ����������������
+ * ��  ��  ��V1.0
+ * ��  ��  ��XuZhongPing
+ * ��  ��  ��2017/03/06 
+*********************************************************************************/
+#include "buzzer.h"
+#include "timer.h"
+
+#define BEEP_PeriphClock		RCC_APB2Periph_GPIOB
+#define BEEP_PORT						GPIOB
+#define BEEP_PIN						GPIO_Pin_2
+
+uint8_t beep_startUpMark = 0;										//������ʾ��־
+uint8_t beep_shortBeepMark = 0;									//�����������־
+uint8_t beep_longBeepMark = 0;									//�����������־
+uint8_t beep_closeDoorBeepMark = 0;							//�������������־
+uint8_t beep_warningBeepMark = 0;								//���������󾯸���ʾ���־
+uint8_t beep_contSlowBeepMark = 0;							//���������������־
+uint8_t beep_contFastBeepMark = 0;							//���������������־
+	
+/*
+***********************************************************************
+*	�� �� ��: KeyInit
+*	����˵��: ����IO�ڳ�ʼ��
+*	��    �Σ���
+*	�� �� ֵ: ��
+***********************************************************************
+*/
+void BeepInit(void)
+{ 
+ 	GPIO_InitTypeDef GPIO_InitStructure;
+ 	RCC_APB2PeriphClockCmd(BEEP_PeriphClock, ENABLE);	
+
+	
+	GPIO_InitStructure.GPIO_Pin = BEEP_PIN;			 				
+	GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP; 
+	GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;	
+	GPIO_Init(BEEP_PORT, &GPIO_InitStructure);
+	
+	GPIO_ResetBits(BEEP_PORT, BEEP_PIN);	
+	
+	beep_startUpMark = 1;						//��־���ڿ���������ʾ
+}
+
+/*
+***********************************************************************
+*	�� �� ��: SetBuzzerStatus
+*	����˵��: ���÷���������״̬
+*	��    �Σ�param -> ���õ�״̬��0�أ�1����
+*	�� �� ֵ: ��
+***********************************************************************
+*/
+void SetBuzzerStatus(uint8_t param)
+{
+	if(param)
+	{
+		GPIO_SetBits(BEEP_PORT, BEEP_PIN);	
+// 		printf("\r\n��������\r\n");
+	}else{
+		GPIO_ResetBits(BEEP_PORT, BEEP_PIN);
+// 		printf("\r\n�ط�����\r\n");
+	}
+}
+
+
+/*
+***********************************************************************
+*	�� �� ��: BEEP_ShortBeep
+*	����˵��: ����������
+*	��    �Σ���
+*	�� �� ֵ: ��
+***********************************************************************
+*/
+static void BEEP_ShortBeep(void)
+{
+	static uint8_t beepStatus = 0x00;
+	
+	static timer beepOnTimer;
+	static uint8_t timer_ok = 0;
+	
+	if(timer_ok == 0)
+	{
+		timer_ok = 1;
+		
+		timer_set(&beepOnTimer, 2);
+	}
+	
+	switch(beepStatus)
+	{
+		case 0x00:
+			if(beep_shortBeepMark == 1)
+			{
+				beep_shortBeepMark = 0;
+				SetBuzzerStatus(1);												//�򿪷�����
+				
+				timer_restart(&beepOnTimer);
+				beepStatus = 0x01;
+				break;
+			}
+			break;
+		
+		case 0x01:
+			if(timer_expired(&beepOnTimer))
+			{
+				SetBuzzerStatus(0);												//�رշ�����
+				beepStatus = 0x00;
+				break;
+			}
+			break;
+			
+		default:
+			SetBuzzerStatus(0);												//�رշ�����
+			beepStatus = 0x00;
+			break;
+	}
+}
+
+/*
+***********************************************************************
+*	�� �� ��: BEEP_LongBeep
+*	����˵��: ����������
+*	��    �Σ���
+*	�� �� ֵ: ��
+***********************************************************************
+*/
+static void BEEP_LongBeep(void)
+{
+	static uint8_t beepStatus = 0x00;
+	
+	static timer beepOnTimer;
+	static uint8_t timer_ok = 0;
+	
+	if(timer_ok == 0)
+	{
+		timer_ok = 1;
+		
+		timer_set(&beepOnTimer, 20);
+	}
+	
+	switch(beepStatus)
+	{
+		case 0x00:
+			if(beep_longBeepMark == 1)
+			{
+				beep_longBeepMark = 0;
+				SetBuzzerStatus(1);												//�򿪷�����
+				
+				timer_restart(&beepOnTimer);
+				beepStatus = 0x01;
+				break;
+			}
+			break;
+		
+		case 0x01:
+			if(timer_expired(&beepOnTimer))
+			{
+				SetBuzzerStatus(0);												//�رշ�����
+				beepStatus = 0x00;
+				break;
+			}
+			SetBuzzerStatus(1);												//�򿪷�����
+			break;
+			
+		default:
+			SetBuzzerStatus(0);												//�رշ�����
+			beepStatus = 0x00;
+			break;
+	}
+}
+
+/*
+***********************************************************************
+*	�� �� ��: BEEP_StartUpBeep
+*	����˵��: ������������ʾ��
+*	��    �Σ���
+*	�� �� ֵ: ��
+***********************************************************************
+*/
+static void BEEP_StartUpBeep(void)
+{
+	static uint8_t beepStatus = 0x00;
+	
+	static timer beepOnTimer1;
+	static timer beepOnTimer2;
+	static timer beepOffTimer1;
+	static timer beepOffTimer2;
+	
+	static uint8_t timer_ok = 0;
+	
+	if(timer_ok == 0)
+	{
+		timer_ok = 1;
+		
+		timer_set(&beepOnTimer1, 1);
+		timer_set(&beepOnTimer2, 2);
+		timer_set(&beepOffTimer1, 1);
+		timer_set(&beepOffTimer2, 2);
+	}
+	
+	switch(beepStatus)
+	{
+		case 0x00:
+			if(beep_startUpMark == 1)
+			{
+				beep_startUpMark = 0;
+				SetBuzzerStatus(1);												//�򿪷�����
+				timer_restart(&beepOnTimer1);
+				beepStatus = 0x01;
+				break;
+			}
+			break;
+		
+		case 0x01:
+			if(timer_expired(&beepOnTimer1))
+			{
+				SetBuzzerStatus(0);												//�رշ�����
+				timer_restart(&beepOffTimer1);
+				beepStatus = 0x02;
+				break;
+			}
+			break;
+			
+		case 0x02:
+			if(timer_expired(&beepOffTimer1))
+			{
+				SetBuzzerStatus(1);												//�򿪷�����
+				timer_restart(&beepOnTimer2);
+				beepStatus = 0x03;
+				break;
+			}
+			break;
+			
+		case 0x03:
+			if(timer_expired(&beepOnTimer2))
+			{
+				SetBuzzerStatus(0);												//�رշ�����
+				timer_restart(&beepOffTimer2);
+				beepStatus = 0x04;
+				break;
+			}
+			break;
+			
+		case 0x04:
+			if(timer_expired(&beepOffTimer2))
+			{
+				SetBuzzerStatus(1);	
+				timer_restart(&beepOnTimer2);
+				beepStatus = 0x05;
+				break;
+			}
+			break;
+			
+		case 0x05:
+			if(timer_expired(&beepOnTimer2))
+			{
+				SetBuzzerStatus(0);												//�رշ�����
+				beep_startUpMark = 0;
+				beepStatus = 0x00;
+				break;
+			}
+			break;
+			
+		default:
+			SetBuzzerStatus(0);												//�رշ�����
+			beepStatus = 0x00;
+			break;
+	}
+}
+
+/*
+***********************************************************************
+*	�� �� ��: BEEP_CloseDoorBeep
+*	����˵��: ������������ʾ��
+*	��    �Σ���
+*	�� �� ֵ: ��
+***********************************************************************
+*/
+static void BEEP_CloseDoorBeep(void)
+{
+	static uint8_t beepStatus = 0x00;
+	
+	static timer closeDoorBeepOnTimer;
+	static uint8_t timer_ok = 0;
+	
+	if(timer_ok == 0)
+	{
+		timer_ok = 1;
+		
+		timer_set(&closeDoorBeepOnTimer, 5);
+	}
+
+	switch(beepStatus)
+	{
+		case 0x00:
+			if(beep_closeDoorBeepMark == 1)
+			{
+				beep_closeDoorBeepMark = 0;
+				SetBuzzerStatus(1);												//�򿪷�����
+				timer_restart(&closeDoorBeepOnTimer);
+				beepStatus = 0x01;
+				break;
+			}
+			break;
+			
+		case 0x01:
+			if(timer_expired(&closeDoorBeepOnTimer))
+			{
+				SetBuzzerStatus(0);												//�رշ�����
+				timer_restart(&closeDoorBeepOnTimer);
+				beepStatus = 0x02;
+				break;
+			}
+			break;
+			
+		case 0x02:
+			if(timer_expired(&closeDoorBeepOnTimer))
+			{
+				SetBuzzerStatus(1);												//�򿪷�����
+				timer_restart(&closeDoorBeepOnTimer);
+				beepStatus = 0x03;
+				break;
+			}
+			break;
+			
+		case 0x03:
+			if(timer_expired(&closeDoorBeepOnTimer))
+			{
+				SetBuzzerStatus(0);												//�رշ�����
+				timer_restart(&closeDoorBeepOnTimer);
+				beepStatus = 0x04;
+				break;
+			}
+			break;
+			
+		case 0x04:
+			if(timer_expired(&closeDoorBeepOnTimer))
+			{
+				SetBuzzerStatus(1);												//�򿪷�����
+				timer_restart(&closeDoorBeepOnTimer);
+				beepStatus = 0x05;
+				break;
+			}
+			break;
+			
+		case 0x05:
+			if(timer_expired(&closeDoorBeepOnTimer))
+			{
+				SetBuzzerStatus(0);												//�رշ�����
+				beep_closeDoorBeepMark = 0;
+				beepStatus = 0x00;
+				break;
+			}
+			break;
+			
+		default:
+			SetBuzzerStatus(0);												//�رշ�����
+			beepStatus = 0x00;
+			break;
+	}
+}
+
+/*
+***********************************************************************
+*	�� �� ��: BEEP_WarningBeep
+*	����˵��: ������������ʾ��
+*	��    �Σ���
+*	�� �� ֵ: ��
+***********************************************************************
+*/
+static void BEEP_WarningBeep(void)
+{
+	static uint8_t beepStatus = 0x00;
+	
+	static timer warningBeepOnTimer;
+	static timer warningBeepOffTimer;
+	static uint8_t timer_ok = 0;
+	
+	if(timer_ok == 0)
+	{
+		timer_ok = 1;
+		
+		timer_set(&warningBeepOnTimer, 2);
+		timer_set(&warningBeepOffTimer, 2);
+	}
+	
+	switch(beepStatus)
+	{
+		case 0x00:
+			if(beep_warningBeepMark == 1)
+			{
+				beep_warningBeepMark = 0;
+				SetBuzzerStatus(1);												//�򿪷�����
+				timer_restart(&warningBeepOnTimer);
+				beepStatus = 0x01;
+				break;
+			}
+			break;
+			
+		case 0x01:
+			if(timer_expired(&warningBeepOnTimer))
+			{
+				SetBuzzerStatus(0);												//�رշ�����
+				timer_restart(&warningBeepOnTimer);
+				beepStatus = 0x02;
+				break;
+			}
+			break;
+			
+		case 0x02:
+			if(timer_expired(&warningBeepOnTimer))
+			{
+				SetBuzzerStatus(1);												//�򿪷�����
+				timer_restart(&warningBeepOnTimer);
+				beepStatus = 0x03;
+				break;
+			}
+			break;
+			
+		case 0x03:
+			if(timer_expired(&warningBeepOnTimer))
+			{
+				SetBuzzerStatus(0);												//�رշ�����
+				timer_restart(&warningBeepOnTimer);
+				beepStatus = 0x04;
+				break;
+			}
+			break;
+			
+		case 0x04:
+			if(timer_expired(&warningBeepOnTimer))
+			{
+				SetBuzzerStatus(1);												//�򿪷�����
+				timer_restart(&warningBeepOnTimer);
+				beepStatus = 0x05;
+				break;
+			}
+			break;
+			
+		case 0x05:
+			if(timer_expired(&warningBeepOnTimer))
+			{
+				SetBuzzerStatus(0);												//�رշ�����
+				timer_restart(&warningBeepOnTimer);
+				beepStatus = 0x06;
+				break;
+			}
+			break;
+			
+		case 0x06:
+			if(timer_expired(&warningBeepOnTimer))
+			{
+				SetBuzzerStatus(1);												//�򿪷�����
+				timer_restart(&warningBeepOnTimer);
+				beepStatus = 0x07;
+				break;
+			}
+			break;
+			
+		case 0x07:
+			if(timer_expired(&warningBeepOnTimer))
+			{
+				SetBuzzerStatus(0);												//�رշ�����
+				timer_restart(&warningBeepOnTimer);
+				beepStatus = 0x08;
+				break;
+			}
+			break;
+			
+		case 0x08:
+			if(timer_expired(&warningBeepOnTimer))
+			{
+				SetBuzzerStatus(1);												//�򿪷�����
+				timer_restart(&warningBeepOnTimer);
+				beepStatus = 0x09;
+				break;
+			}
+			break;
+			
+		case 0x09:
+			if(timer_expired(&warningBeepOnTimer))
+			{
+				SetBuzzerStatus(0);												//�رշ�����
+				beep_warningBeepMark = 0;
+				beepStatus = 0x00;
+			}
+			break;
+			
+		default:
+			SetBuzzerStatus(0);												//�رշ�����
+			beep_warningBeepMark = 0;
+			beepStatus = 0x00;
+			break;
+	}
+}
+
+/*
+***********************************************************************
+*	�� �� ��: BEEP_ContSlowBeep
+*	����˵��: ��������������
+*	��    �Σ���
+*	�� �� ֵ: ��
+***********************************************************************
+*/
+static void BEEP_ContSlowBeep(void)
+{
+	static uint8_t beepStatus = 0x00;
+	
+	static timer beepOnTimer;
+	static timer beepOffTimer;
+	static uint8_t timer_ok = 0;
+	
+	if(timer_ok == 0)
+	{
+		timer_ok = 1;
+		
+		timer_set(&beepOnTimer, 2);
+		timer_set(&beepOffTimer, 8);
+	}
+	
+	switch(beepStatus)
+	{
+		case 0x00:
+			if(beep_contSlowBeepMark == 1)
+			{
+				SetBuzzerStatus(1);												//�򿪷�����
+				
+				timer_restart(&beepOnTimer);
+				beepStatus = 0x01;
+				break;
+			}
+			break;
+		
+		case 0x01:
+			if(timer_expired(&beepOnTimer))
+			{
+				SetBuzzerStatus(0);												//�رշ�����
+				timer_restart(&beepOffTimer);
+				beepStatus = 0x02;
+				break;
+			}
+			
+			if(beep_contSlowBeepMark == 0)
+			{
+				SetBuzzerStatus(0);
+				beepStatus = 0x00;
+				break;
+			}
+			break;
+			
+		case 0x02:
+			if(timer_expired(&beepOffTimer))
+			{
+				beepStatus = 0x00;
+				break;
+			}
+			
+			if(beep_contSlowBeepMark == 0)
+			{
+				SetBuzzerStatus(0);
+				beepStatus = 0x00;
+				break;
+			}
+			break;
+			
+		default:
+			SetBuzzerStatus(0);												//�رշ�����
+			beepStatus = 0x00;
+			break;
+	}
+}
+
+/*
+***********************************************************************
+*	�� �� ��: BEEP_ContFastBeep
+*	����˵��: ��������������
+*	��    �Σ���
+*	�� �� ֵ: ��
+***********************************************************************
+*/
+static void BEEP_ContFastBeep(void)
+{
+	static uint8_t beepStatus = 0x00;
+	
+	static timer beepOnTimer;
+	static timer beepOffTimer;
+	static uint8_t timer_ok = 0;
+	
+	if(timer_ok == 0)
+	{
+		timer_ok = 1;
+		
+		timer_set(&beepOnTimer, 1);
+		timer_set(&beepOffTimer, 2);
+	}
+	
+	switch(beepStatus)
+	{
+		case 0x00:
+			if(beep_contFastBeepMark == 1)
+			{
+				SetBuzzerStatus(1);												//�򿪷�����
+				
+				timer_restart(&beepOnTimer);
+				beepStatus = 0x01;
+				break;
+			}
+			break;
+		
+		case 0x01:
+			if(timer_expired(&beepOnTimer))
+			{
+				SetBuzzerStatus(0);												//�رշ�����
+				timer_restart(&beepOffTimer);
+				beepStatus = 0x02;
+				break;
+			}
+			
+			if(beep_contFastBeepMark == 0)
+			{
+				SetBuzzerStatus(0);
+				beepStatus = 0x00;
+				break;
+			}
+			break;
+			
+		case 0x02:
+			if(timer_expired(&beepOffTimer))
+			{
+				beepStatus = 0x00;
+				break;
+			}
+			
+			if(beep_contFastBeepMark == 0)
+			{
+				SetBuzzerStatus(0);
+				beepStatus = 0x00;
+				break;
+			}
+			break;
+			
+		default:
+			SetBuzzerStatus(0);												//�رշ�����
+			beepStatus = 0x00;
+			break;
+	}
+}
+
+/*
+***********************************************************************
+*	�� �� ��: BeepTask
+*	����˵��: 
+*	��    �Σ���
+*	�� �� ֵ: ���ض�Ӧ���صļ�ֵ
+***********************************************************************
+*/
+void BeepTask(void)
+{
+	BEEP_ContSlowBeep();
+	BEEP_ContFastBeep();
+	BEEP_ShortBeep();
+	BEEP_LongBeep();
+	BEEP_StartUpBeep();
+	BEEP_CloseDoorBeep();
+	BEEP_WarningBeep();
+}
+
+/******************** (C) COPYRIGHT 2017 CXHY *****END OF FILE*******************/
diff --git a/STM32_4路称重_Git提交精简工程/src/HARDWARE/BUZZER/buzzer.h b/STM32_4路称重_Git提交精简工程/src/HARDWARE/BUZZER/buzzer.h
new file mode 100755
index 0000000..17c5651
--- /dev/null
+++ b/STM32_4路称重_Git提交精简工程/src/HARDWARE/BUZZER/buzzer.h
@@ -0,0 +1,26 @@
+/*************************** (C) COPYRIGHT 2017 CXHY ****************************
+ * �ļ���  ��buzzer.h
+ * ��  ��  �� ��������������
+ * ��  ��  ��V1.0
+ * ��  ��  ��XuZhongPing
+ * ��  ��  ��2017/03/06 
+*********************************************************************************/
+#ifndef __BUZZER_H
+#define __BUZZER_H	 
+
+#include "stm32f10x.h"
+
+extern uint8_t beep_startUpMark;										//������ʾ��־
+extern uint8_t beep_shortBeepMark;									//�����������־
+extern uint8_t beep_longBeepMark;										//�����������־
+extern uint8_t beep_closeDoorBeepMark;							//�������������־
+extern uint8_t beep_warningBeepMark;								//���������󾯸���ʾ���־
+extern uint8_t beep_contSlowBeepMark;								//���������������־
+extern uint8_t beep_contFastBeepMark;								//���������������־
+
+void BeepInit(void);
+void BeepTask(void);
+
+#endif
+
+/******************** (C) COPYRIGHT 2017 CXHY *****END OF FILE*******************/
diff --git a/STM32_4路称重_Git提交精简工程/src/HARDWARE/DEVICE/device.c b/STM32_4路称重_Git提交精简工程/src/HARDWARE/DEVICE/device.c
new file mode 100755
index 0000000..4502f57
--- /dev/null
+++ b/STM32_4路称重_Git提交精简工程/src/HARDWARE/DEVICE/device.c
@@ -0,0 +1,1387 @@
+/*************************** (C) COPYRIGHT 2017 CXHY ****************************
+ * �ļ���  ��device.c
+ * ��  ��  ���ⲿ�豸���Ƽ��
+ * ��  ��  ��V1.0
+ * ��  ��  ��XuZhongPing
+ * ��  ��  ��2017/09/04
+*********************************************************************************/
+#include "device.h"
+#include "deviceSet.h"
+#include "usart2.h"
+#include "delay.h"
+#include "timer.h"
+#include "data_typedef.h"	  
+#include "tcp_protocol.h"
+#include "lcd.h"  
+#include "display.h"
+#include "ec200x.h"
+#include "door_ctrl.h"
+#include "pc_protocol.h"
+#include "disinfection.h"
+
+/*
+***********************************************************************
+*	�� �� ��: show
+*	����˵��: ��ʮ��������ʾ�����������
+*	��    ��:	��
+*	�� �� ֵ: ��
+***********************************************************************
+*/
+void show(uint8_t num[], uint8_t n)
+{
+    uint8_t i;
+		printf("\r\n");
+    for(i=0; i<n; i++)
+		{
+      printf("0x%02X ",num[i]);
+		}
+		printf("\r\n");
+}
+
+/*
+***********************************************************************
+*	�� �� ��: DeviceConfigParamInit
+*	����˵��: �豸���ò�����ʼ��
+*	��    �Σ���
+*	�� �� ֵ: ��
+***********************************************************************
+*/
+void DeviceConfigParamInit(void)
+{
+	//ȡ������Ĳ���
+	if(GetDeviceConfig())			//û�б�����豸ϵͳ��������ΪĬ��ֵ
+	{
+		DeviceSetParamInit();								//�豸�����޸Ļ��������ʼ����Ϊ�˴ﵽ��ǰCur������������Set������ͬ��
+	}else{		//�б�������ݣ�����ݱ�����FLASH�еĲ�����������
+		printf("\r\n���ڳ�ʼ���豸ϵͳ������\r\n");		
+		DeviceParamInit();								//��flash�ж�ȡ������Set������ͬ������ǰCur������
+	}
+
+#ifdef FOUR_DROP_PORTS
+	//��Ͷ�ſ�ר�ù̼������ݾ�Flash�б������·�豸���͡�
+	deviceType = FOUR_CLASSIFICATION;
+	devChannelNumbers = 4;
+	setDeviceType = deviceType;
+	setDevChannelNumbers = devChannelNumbers;
+#endif
+}
+
+/*
+***********************************************************************
+*	�� �� ��: CalcOverflowStartPointParam
+*	����˵��: �������翪ʼ������Ĳ�������30%���²���������
+*	��    �Σ���
+*	�� �� ֵ: ��
+***********************************************************************
+*/
+void CalcOverflowStartPointParam(void)
+{
+	distanceParamAtStart = devChannel1DisMaxVal - ((devChannel1DisDepthVal*PerCentSetVal)/100);
+	printf("\r\nParamAtStart = %d\r\n", distanceParamAtStart);
+}
+
+/*
+***********************************************************************
+*	�� �� ��: DeviceInit
+*	����˵��: �豸��ʼ��
+*	��    �Σ���
+*	�� �� ֵ: ��
+***********************************************************************
+*/
+void DeviceInit(void)
+{
+	printf("\r\n�豸��ʼ��......\r\n");
+	sprintf(VersionStr, "�汾:%s", VersionNumber);
+	delay_ms(1000);										//ϵͳ�տ������ȴ������ȶ����ٲ���
+	LED_Init();			     							//LED�˿ڳ�ʼ��
+	BeepInit();												//���������Ƴ�ʼ��
+	KeyInit();												//������ʼ��
+	LCD_Init();	 											//12864��ʾ����ʼ��
+	Screen_SystemInit();							//��ʾ��ʼ������
+	ElectronicLock_Init();						//������ӿڳ�ʼ��
+	RFID_Init();											//RFID��Ʒ��ʼ��
+	LTE_Init();												//LTEͨѶģ���ʼ��
+	Audio_Init();											//��Ƶ���Ƴ�ʼ��
+	MotorInit();											//����ӿڳ�ʼ��
+	DeviceConfigParamInit();					//�豸���ò�����ʼ��
+	CalcOverflowStartPointParam();		//�������翪ʼ������Ĳ���
+	while(doorResetMark == 0)					//�Ÿ�λ����
+	{
+		DoorResetTask();
+	}
+	
+	DeviceInfoShow();
+	LCD_ShowSignal(0);
+	
+	deviceInitFlag = 1;								//��־�豸Ӳ����ʼ�����
+	printf("\r\n�豸��ʼ����ɣ�����\r\n");
+}
+
+/*
+***********************************************************************
+*	�� �� ��: DeviceTest
+*	����˵��: Ӳ������
+*	��    �Σ���
+*	�� �� ֵ: ��
+***********************************************************************
+*/
+void DeviceTest(void)
+{
+	printf("\r\nӲ�����ԣ�\r\n");
+	
+	printf("\r\n��������������\r\n");
+	StartUpSprayDisinfection();
+	delay_ms(1000);
+	StopSprayDisinfection();
+	delay_ms(1000);
+	
+	printf("\r\n�����������\r\n");
+	DoorClose(4);
+	delay_ms(1000);
+	DoorStop(4);
+	delay_ms(1000);
+	
+	printf("\r\n����UV������\r\n");
+	StartUpDisinfection();
+	delay_ms(1000);
+	StopDisinfection();
+	delay_ms(1000);
+	
+	printf("\r\n���������ȣ�\r\n");
+	Unlock(3);
+	Unlock(4);
+	delay_ms(1000);
+	Locked(3);
+	Locked(4);
+	
+	printf("\r\nӲ�����Խ�����\r\n");
+}
+
+/*
+***********************************************************************
+*	�� �� ��: ascii_to_hex
+*	����˵��: ascii�ַ���תʮ������
+*	��    �Σ���
+*	�� �� ֵ: ��
+***********************************************************************
+*/
+void ascii_to_hex(uint8_t* str, uint8_t* hex, uint16_t size)
+{
+	uint8_t deposit [64];
+	uint16_t i = 0;
+	uint16_t num = 0;
+
+	for(i=0; i<size; i++)
+	{
+		switch(str[i])
+		{
+			case '0':
+			  deposit[i]=0x00;
+				break;
+			case '1':
+			  deposit[i]=0x01;
+				break;
+			case '2':
+			  deposit[i]=0x02;
+				break;
+			case '3':
+			  deposit[i]=0x03;
+				break;
+			case '4':
+			  deposit[i]=0x04;
+				break;
+			case '5':
+			  deposit[i]=0x05;
+				break;
+			case '6':
+			  deposit[i]=0x06;
+				break;
+			case '7':
+				deposit[i]=0x07;
+				break;
+			case '8':
+				deposit[i]=0x08;
+				break;
+			case '9':
+				deposit[i]=0x09;
+				break;
+			case 'A':
+			case 'a':
+				deposit[i]=0x0A;
+				break;
+			case 'B':
+			case 'b':
+				deposit[i]=0x0B;
+				break;
+			case 'C':
+			case 'c':
+				deposit[i]=0x0C;
+				break;
+			case 'D':
+			case 'd':
+				deposit[i]=0x0D;
+				break;
+			case 'E':
+			case 'e':
+				deposit[i]=0x0E;
+				break;
+			case 'F':
+			case 'f':
+				deposit[i]=0x0F;
+				break;
+			default:
+				break;
+		}
+	}
+	
+	for(i=0; i<size/2; i++)
+	{
+		hex[i] = (deposit[i*2] << 4) | (deposit[i*2+1]);
+	}
+	
+	show(hex, 16);
+}
+
+/*
+***********************************************************************
+*	�� �� ��: DeviceScanning
+*	����˵��: �豸ɨ�裨������RFID-IC���Ͷ�ά��ɨ�裩
+*	��    �Σ���
+*	�� �� ֵ: ��
+***********************************************************************
+*/
+void DeviceScanning(void)
+{
+	uint8_t hexBuf[16];
+	
+	if(USART1_RX_STA & 0x8000)		//���յ�һ��������
+	{
+// 		if((USART1_RX_BUF[0] == 0x04) && (USART1_RX_BUF[1] == 0x16) && (USART1_RX_BUF[2] == 0x03))
+		if(((USART1_RX_STA & 0x7FFF) == 34) && ((USART1_RX_BUF[30] == '0') || (USART1_RX_BUF[30] == 'F')) && ((USART1_RX_BUF[31] == '0') || (USART1_RX_BUF[31] == 'F')))
+		{
+			printf("\r\nˢIC��\r\n");
+// 			show(USART4_RX_BUF, 64);
+			ascii_to_hex(USART1_RX_BUF, hexBuf, 32);
+			memcpy(RFID_ID, hexBuf, 16);									//����IC��������Ϣ
+			IC_CardDecode();
+		}else{
+			printf("\r\nɨ��ά��\r\n");
+			QR_CodeDecode((char*)USART1_RX_BUF);	
+		}
+		memset(USART1_RX_BUF, 0x00, 128);														//�����������
+		USART1_RX_STA = 0;
+	}
+}
+
+/*
+***********************************************************************
+*	�� �� ��: OpenDoorRequestTask
+*	����˵��: ������������
+*	��    �Σ���
+*	�� �� ֵ: ��
+***********************************************************************
+*/
+void OpenDoorRequestTask(void)
+{
+	static uint8_t controlSteps = 0;
+	
+	static timer waitingChooseTimer;						//����һ����ʱ��
+	static timer waitingPutInTimer;							//����һ����ʱ��
+	static timer waitingTimer1S;								//����һ����ʱ��
+	
+	static uint8_t timer_ok = 0;
+	
+	if(timer_ok == 0)
+	{
+		timer_ok = 1;
+		
+		timer_set(&waitingChooseTimer, CLOCK_SECOND*10);
+		timer_set(&waitingPutInTimer, CLOCK_SECOND*200);		//�ȴ�Ͷ�����ʱ��
+		timer_set(&waitingTimer1S, CLOCK_SECOND*1);
+	}
+	
+	switch(controlSteps)
+	{
+		case 0x00:		//��ʼ״̬
+			if(isOpenDoor == 1)		//�п�������
+			{
+				printf("\r\n----> �п��������豸���� <----\r\n");		
+				isOpenDoor = 0;
+				
+// 				swipingCardStatus = 1;										//������ʾ��			
+				
+// 				keyValue = 0;
+				exitMark = 0;
+				isOpenDoorRequest_1 = 0;
+				isOpenDoorRequest_2 = 0;
+				isOpenDoorRequest_3 = 0;
+				isOpenDoorRequest_4 = 0;
+				putInEndMark = 0;
+			
+				printf("\r\n�ȴ��û�Ͷ��\r\n");
+
+				timer_restart(&waitingPutInTimer);
+				controlSteps = 0x01;											//�п��������������ת������Ͷ�Ų�������
+			}
+			break;
+			
+		case 0x01:		//�ȴ��û�Ͷ��
+			if(timer_expired(&waitingPutInTimer))				//Ͷ�ų�ʱ
+			{
+				putInOKMark = 1;
+				
+				printf("\r\nͶ��ʱ�䵽�˳�\r\n");
+				controlSteps = 0x03;
+				break;
+			}
+			
+			//�Ƿ����ӳ�Ͷ��
+			if(delayCloseDoorStatus2 == 1)
+			{
+				delayCloseDoorStatus2 = 0;
+				timer_restart(&waitingPutInTimer);
+				printf("\r\nOpenDoorRequestTask�ӳ�!\r\n");
+			}
+			
+			if(openDoorNumber == 255)
+			{
+				openDoorNumber = 0;
+				
+				beep_shortBeepMark = 1;
+				
+				if(fullMark1 == 0) isOpenDoorRequest_1 = 1;
+				if(fullMark2 == 0) isOpenDoorRequest_2 = 1;
+				if(fullMark3 == 0) isOpenDoorRequest_3 = 1;
+				if(fullMark4 == 0) isOpenDoorRequest_4 = 1;
+			}
+			
+			if(openDoorNumber != 0)		//�û�ѡ����Ͷ������
+			{
+				beep_shortBeepMark = 1;
+				switch(openDoorNumber)
+				{
+					case 1:
+						if(fullMark1 == 0)
+						{
+							isOpenDoorRequest_1 = 1;					//��־1���豸��ʼ����
+							printf("\r\n1�Ű�������\r\n");
+						}else{
+							printf("\r\n1��������\r\n");
+						}
+						break;
+						
+					case 2:
+						if(fullMark2 == 0)
+						{
+							isOpenDoorRequest_2 = 1;					//��־1���豸��ʼ����
+							printf("\r\n2�Ű�������\r\n");
+						}else{
+							printf("\r\n2��������\r\n");
+						}
+						break;
+
+					case 3:
+						if(fullMark3 == 0)
+						{
+							isOpenDoorRequest_3 = 1;
+							printf("\r\n3�Ű�������\r\n");
+						}else{
+							printf("\r\n3��������\r\n");
+						}
+						break;
+
+					case 4:
+						if(fullMark4 == 0)
+						{
+							isOpenDoorRequest_4 = 1;
+							printf("\r\n4�Ű�������\r\n");
+						}else{
+							printf("\r\n4��������\r\n");
+						}
+						break;
+						
+					default:
+						break;
+				}
+				openDoorNumber = 0;
+			}
+			
+			//�ж��û�����Ͷ�ŵ������Ƿ������Ѿ�Ͷ�����
+			if(putInEndMark == 1)
+			{
+				putInEndMark = 0;
+				putInOKMark = 1;
+				printf("\r\n�û��Ѿ�Ͷ�����\r\n");
+				
+				controlSteps = 0x03;
+				break;
+			}
+			break;
+			
+		case 0x03:
+// 			SetKeyLedOFF(1);
+// 			SetKeyLedOFF(2);
+			
+			//�������������ʹ�õ��ı���Ϊ��һ����׼��
+			isOpenDoor = 0;
+			keyValue = 0;
+			isOpenDoorRequest_1 = 0;
+			isOpenDoorRequest_2 = 0;
+			isOpenDoorRequest_3 = 0;
+			isOpenDoorRequest_4 = 0;
+			
+			controlSteps = 0x00;
+			break;
+			
+		default:
+			break;
+	}
+}
+
+/*
+***********************************************************************
+*	�� �� ��: ClearDevCtrlVar
+*	����˵��: ����豸���ƹ�����ʹ�õı�����Ϊ��һ��������׼��
+*	��    �Σ���
+*	�� �� ֵ: ��
+***********************************************************************
+*/
+void ClearDevCtrlVar(void)
+{
+	keyValue = 0;																		//�����ť���±�־
+	
+	isOpenDoor = 0;																	//���������־
+	isOpenDoorRequest_1 = 0;
+	isOpenDoorRequest_2 = 0;
+	isOpenDoorRequest_3 = 0;
+	isOpenDoorRequest_4 = 0;
+}
+
+/*
+***********************************************************************
+*	�� �� ��: DeviceControl
+*	����˵��: �豸����
+*	��    �Σ���
+*	�� �� ֵ: �ޣ�����ȫ�ֱ���putInOK_State������ɲ�����Ϊ1�����ⲿ�����
+***********************************************************************
+*/
+void DeviceControlTask(void)
+{
+	static uint8_t controlSteps = 0;
+	uint16_t tempWeight = 0;
+	
+	static uint8_t currentOpenDoorStatus_1 = 0;
+	static uint8_t currentOpenDoorStatus_2 = 0;
+	static uint8_t currentOpenDoorStatus_3 = 0;
+	static uint8_t currentOpenDoorStatus_4 = 0;
+	
+	static uint8_t doorCloseOK_1 = 0;
+	static uint8_t doorCloseOK_2 = 0;
+	static uint8_t doorCloseOK_3 = 0;
+	static uint8_t doorCloseOK_4 = 0;
+	
+	static uint16_t preChangeWeight1 = 0;
+	static uint16_t preChangeWeight2 = 0;
+	static uint16_t preChangeWeight3 = 0;
+	static uint16_t preChangeWeight4 = 0;
+	
+	uint16_t tempData1 = 0;
+	uint16_t tempData2 = 0;
+	
+	static uint32_t startTimer = 0;									//�����ſ�ʼʱ��
+	static uint32_t endTimer = 0;										//�����Ž���ʱ��
+	
+	static uint32_t preRemainingTimer = 0;					//��һ�λ�ʣʱ��
+	
+	static timer waitingTimer_100ms;								//�ȴ�100ms��ʱ��
+	static timer waitingTimer_300ms;								//�ȴ�300ms��ʱ��
+	static timer waitingTimer_500ms;								//�ȴ�500ms��ʱ��
+	static timer waitingTimer_1S;										//�ȴ�1S��ʱ��
+	static timer openDoorTimer;											//���ڿ���ʱ������
+	static timer closeDoorTimer;										//���ڹ���ʱ������
+	static timer waitingLeaveTimer;									//�ȴ����뿪ʱ��
+	static timer waitingTimer_300S;									//5���Ӻ��Զ�����
+	static timer waitingGetWeight;
+	static timer waitingGetDis;
+	
+	static uint8_t timer_ok = 0;
+	
+	if(timer_ok == 0)
+	{
+		timer_ok = 1;
+		
+		timer_set(&waitingTimer_100ms, 1);
+		timer_set(&waitingTimer_300ms, 15);
+		timer_set(&waitingTimer_500ms, 5);
+		timer_set(&waitingTimer_1S, CLOCK_SECOND*1);
+		timer_set(&openDoorTimer, 16);											//����1����ʱ�������ڿ���ʱ������
+		timer_set(&closeDoorTimer, 60);											//����1����ʱ�������ڹ���ʱ������
+		timer_set(&waitingLeaveTimer, CLOCK_SECOND*180);			//����1����ʱ�������ڼ�����뿪
+		timer_set(&waitingTimer_300S, CLOCK_SECOND*300);		//����1����ʱ��������5���Ӻ��Զ�����
+		timer_set(&waitingGetWeight, CLOCK_SECOND*2);
+		timer_set(&waitingGetDis, CLOCK_SECOND*1);
+	}
+
+	switch(controlSteps)
+	{
+		case 0x00:			//��ʼ״̬
+			if((isOpenDoorRequest_1 == 1) || (isOpenDoorRequest_2 == 1) || (isOpenDoorRequest_3 == 1) || (isOpenDoorRequest_4 == 1))		//�п�������
+			{
+				printf("\r\n----> �п�������\r\n");
+				
+//				disinfectingMark = 2;											//����ǰ�ж�����
+//				sprayDisinfectingMark = 2;
+				
+				updateDistanceMark = 1;											//��־��ǰ����Ͷ�Ų���ȡ�������
+				
+				pcRequestClooseDoorMark = 0;
+				
+				isOpenDoor_1 = 0;
+				isOpenDoor_2 = 0;
+				isOpenDoor_3 = 0;
+				isOpenDoor_4 = 0;
+				
+				currentOpenDoorStatus_1 = 0;
+				currentOpenDoorStatus_2 = 0;
+				currentOpenDoorStatus_3 = 0;
+				currentOpenDoorStatus_4 = 0;
+				
+				doorCloseOK_1 = 0;
+				doorCloseOK_2 = 0;
+				doorCloseOK_3 = 0;
+				doorCloseOK_4 = 0;
+				
+				isCloseDoorMark_1 = 0;		
+				isCloseDoorMark_2 = 0;
+				isCloseDoorMark_3 = 0;
+				isCloseDoorMark_4 = 0;
+				
+				smallBottleCount = 0;											//Ͷ��ǰ�����ƿ�ӵ�����
+				bigBottleCount = 0;
+				cansCount = 0;
+				
+				getWeightBefore1 = weight1;								//ȡ������ǰ�������������ϴ���
+				getWeightBefore2 = weight2;
+				getWeightBefore3 = weight3;
+				getWeightBefore4 = weight4;
+				
+				preChangeWeight1 = weight1;								//ȡ����ǰ������������������жϳ�����û�б仯��
+				preChangeWeight2 = weight2;				
+				preChangeWeight3 = weight3;	
+				preChangeWeight4 = weight4;
+				
+				remainingTimer = 0;
+				
+				printf("\r\nȡ������ǰ��������");	
+				printf("W1 = %2.2f Kg, W2 = %2.2f Kg, W3 = %2.2f Kg, W4 = %2.2f Kg\r\n",
+							(float)getWeightBefore1/100,
+							(float)getWeightBefore2/100,
+							(float)getWeightBefore3/100,
+							(float)getWeightBefore4/100);
+				
+				timer_restart(&waitingTimer_100ms);
+				controlSteps = 0x01;											//�п��������������ת������Ͷ�Ų�������
+				break;
+			}
+			break;
+			
+		case 0x01:		
+			if(timer_expired(&waitingTimer_100ms))
+			{
+				if(isOpenDoorRequest_1 == 1)
+				{
+					isOpenDoorRequest_1 = 0;
+					isOpenDoor_1 = 1;
+					currentOpenDoorStatus_1 = 1;						//��־��1�д�
+				}
+				
+				if(isOpenDoorRequest_2 == 1)
+				{
+					isOpenDoorRequest_2 = 0;
+					isOpenDoor_2 = 1;
+					currentOpenDoorStatus_2 = 1;						//��־��2�д�
+				}
+				
+				if(isOpenDoorRequest_3 == 1)
+				{
+					isOpenDoorRequest_3 = 0;
+					isOpenDoor_3 = 1;
+					currentOpenDoorStatus_3 = 1;						//��־��3�д�
+				}
+				
+				if(isOpenDoorRequest_4 == 1)
+				{
+					isOpenDoorRequest_4 = 0;
+					isOpenDoor_4 = 1;
+					currentOpenDoorStatus_4 = 1;						//��־��4�д�
+				}
+				
+				timer_restart(&waitingTimer_300S);
+				controlSteps = 0x02;
+				break;
+			}
+			break;
+			
+		case 0x02:		//������Ƿ��Ѿ��뿪
+			if(timer_expired(&waitingTimer_300S))
+			{
+				printf("\r\n5���ӳ�ʱ�Զ�����\r\n");
+				controlSteps = 0x04;										//ת������
+				break;
+			}
+			
+			timer_restart(&waitingLeaveTimer);
+			timer_restart(&waitingTimer_300S);
+			controlSteps = 0x03;
+			break;
+			
+		case 0x03:		//ȷ�����뿪
+			if(timer_expired(&waitingTimer_300S))			//���5���Ӷ�ʱʱ�䵽�ˣ�����ֹͣ
+			{
+				controlSteps = 0x04;										//ת������
+				printf("\r\n5���ӳ�ʱ�Զ�����\r\n");
+				break;
+			}
+			
+			//�жϵȴ��������Ƿ��м�����������
+			if(isOpenDoorRequest_1 == 1)
+			{
+				isOpenDoorRequest_1 = 0;
+				isOpenDoor_1 = 1;
+				currentOpenDoorStatus_1 = 1;						//��־��1�д�
+				timer_restart(&waitingLeaveTimer);
+				delayCloseDoorStatus = 1;
+				delayCloseDoorStatus2 = 1;
+			}
+				
+			if(isOpenDoorRequest_2 == 1)
+			{
+				isOpenDoorRequest_2 = 0;
+				isOpenDoor_2 = 1;
+				currentOpenDoorStatus_2 = 1;						//��־��2�д�
+				timer_restart(&waitingLeaveTimer);
+				delayCloseDoorStatus = 1;
+				delayCloseDoorStatus2 = 1;
+			}
+			
+			if(isOpenDoorRequest_3 == 1)
+			{
+				isOpenDoorRequest_3 = 0;
+				isOpenDoor_3 = 1;
+				currentOpenDoorStatus_3 = 1;						//��־��3�д�
+				timer_restart(&waitingLeaveTimer);
+				delayCloseDoorStatus = 1;
+				delayCloseDoorStatus2 = 1;
+			}
+			
+			if(isOpenDoorRequest_4 == 1)
+			{
+				isOpenDoorRequest_4 = 0;
+				isOpenDoor_4 = 1;
+				currentOpenDoorStatus_4 = 1;						//��־��4�д�
+				timer_restart(&waitingLeaveTimer);
+				delayCloseDoorStatus = 1;
+				delayCloseDoorStatus2 = 1;
+			}
+			
+			//�ж��Ƿ���Ͷ�ţ���Ͷ�����ӳٹ���ʱ��
+			if(weight1 > preChangeWeight1)
+			{
+				if((weight1 - preChangeWeight1) >= 5)												//��Ͷ�Ŵ���50g
+				{
+					preChangeWeight1 = weight1;
+					timer_restart(&waitingLeaveTimer);			//�趨�ȴ�ʱ���ڼ�⵽����Ͷ�ţ���һֱ���ֿ���
+					delayCloseDoorStatus = 1;								//��־���ӳٹ��ţ��ÿ�������Ͷ�������ӳ�ͬ��
+					delayCloseDoorStatus2 = 1;
+					printf("\r\n�ӳٹ���1\r\n");
+				}
+			}
+			if(weight2 > preChangeWeight2)
+			{
+				if((weight2 - preChangeWeight2) >= 5)
+				{
+					preChangeWeight2 = weight2;
+					timer_restart(&waitingLeaveTimer);			//�趨�ȴ�ʱ���ڼ�⵽����Ͷ�ţ���һֱ���ֿ���
+					delayCloseDoorStatus = 1;								//��־���ӳٹ��ţ��ÿ�������Ͷ�������ӳ�ͬ��
+					delayCloseDoorStatus2 = 1;
+					printf("\r\n�ӳٹ���2\r\n");
+				}
+			}
+			if(weight3 > preChangeWeight3)
+			{
+				if((weight3 - preChangeWeight3) >= 5)
+				{
+					preChangeWeight3 = weight3;
+					timer_restart(&waitingLeaveTimer);
+					delayCloseDoorStatus = 1;
+					delayCloseDoorStatus2 = 1;
+					printf("\r\n�ӳٹ���3\r\n");
+				}
+			}
+			if(weight4 > preChangeWeight4)
+			{
+				if((weight4 - preChangeWeight4) >= 5)
+				{
+					preChangeWeight4 = weight4;
+					timer_restart(&waitingLeaveTimer);
+					delayCloseDoorStatus = 1;
+					delayCloseDoorStatus2 = 1;
+					printf("\r\n�ӳٹ���4\r\n");
+				}
+			}
+			
+			//ȡ��ʣ�����ʱ��
+			remainingTimer = timer_remaining(&waitingLeaveTimer)/10;
+			if(remainingTimer != preRemainingTimer)
+			{
+				preRemainingTimer = remainingTimer;
+				getRemainingTimerStatus = 1;
+				
+				if(remainingTimer == 3)
+				{
+					beep_closeDoorBeepMark = 1;
+				}
+// 				printf("\r\nʣ�����ʱ�� = %d\r\n", remainingTimer);
+			}
+			
+			if(timer_expired(&waitingLeaveTimer))				//�����ʱʱ�䵽�ˣ�����ֹͣ
+			{
+				printf("\r\n���Ѿ��뿪\r\n");
+				printf("\r\n����\r\n");
+				controlSteps = 0x04;
+				break;
+			}
+			
+			if(pcRequestClooseDoorMark == 1)
+			{
+				pcRequestClooseDoorMark = 0;
+				
+				printf("\r\n��λ������ر�Ͷ��\r\n");
+				printf("\r\n����\r\n");
+				controlSteps = 0x04;
+				break;
+			}
+			
+			break;
+			
+		case 0x04:			//����		
+			printf("\r\n����Ͷ�ţ����ڹ���\r\n");
+			isCloseDoorMark_1 = 1;																//����
+			isCloseDoorMark_2 = 1;
+			isCloseDoorMark_3 = 1;
+			isCloseDoorMark_4 = 1;
+			
+			controlSteps = 0x05;
+			timer_restart(&closeDoorTimer);							//�ӵ�ǰʱ�����¿�ʼn�붨ʱ��
+			break;
+			
+		case 0x05:			//���ż��
+			if(timer_expired(&closeDoorTimer))					//�����ʱʱ�䵽�ˣ������ֹͣ
+			{
+				controlSteps = 0x06;
+				printf("\r\n�ȴ�����ʱ�䵽\r\n");
+				timer_restart(&waitingGetWeight);
+				break;
+			}
+			
+			//�ж϶�Ӧ�����Ƿ��Ѿ��ر����
+			if(currentOpenDoorStatus_1 == 1)
+			{
+				if(openDoorCtrlEndMark_1 == 1)
+				{
+					doorCloseOK_1 = 1;
+				}
+			}else{
+				doorCloseOK_1 = 1;
+			}
+			
+			if(currentOpenDoorStatus_2 == 1)
+			{
+				if(openDoorCtrlEndMark_2 == 1)
+				{
+					doorCloseOK_2 = 1;
+				}
+			}else{
+				doorCloseOK_2 = 1;
+			}
+			
+			if(currentOpenDoorStatus_3 == 1)
+			{
+				if(openDoorCtrlEndMark_3 == 1)
+				{
+					doorCloseOK_3 = 1;
+				}
+			}else{
+				doorCloseOK_3 = 1;
+			}
+			
+			if(currentOpenDoorStatus_4 == 1)
+			{
+				if(openDoorCtrlEndMark_4 == 1)
+				{
+					doorCloseOK_4 = 1;
+				}
+			}else{
+				doorCloseOK_4 = 1;
+			}
+			
+			if((doorCloseOK_1 == 1) && (doorCloseOK_2 == 1) &&
+				 (doorCloseOK_3 == 1) && (doorCloseOK_4 == 1))
+			{
+				doorCloseOK_1 = 0;
+				doorCloseOK_2 = 0;
+				doorCloseOK_3 = 0;
+				doorCloseOK_4 = 0;
+				
+				timer_restart(&waitingGetWeight);
+				controlSteps = 0x06;
+				break;
+			}
+			break;
+			
+		case 0x06:		//�ȴ������ȶ���ȡ����������
+			if(timer_expired(&waitingGetWeight))
+			{
+				getWeightAfter1 = weight1;									//ȡ��Ͷ�ź������
+				getWeightAfter2 = weight2;
+				getWeightAfter3 = weight3;
+				getWeightAfter4 = weight4;
+				
+				updateDistanceMark = 0;											//��־���Ի�ȡ�������
+				restartGetDisDataMark = 1;									//���²ɼ�����������
+				
+				timer_restart(&waitingGetDis);
+				controlSteps = 0x50;
+				break;
+			}
+			break;
+			
+		case 0x50:
+			if(timer_expired(&waitingGetDis))
+			{
+				controlSteps = 0x07;
+				break;
+			}
+			break;
+
+		case 0x07:			//���㱾��Ͷ������
+			printf("\r\n���㱾��Ͷ������\r\n");
+			printf("\r\n��1����: %2.2f Kg -> %2.2f Kg\r\n", (float)getWeightBefore1/100, (float)getWeightAfter1/100);
+			printf("\r\n��2����: %2.2f Kg -> %2.2f Kg\r\n", (float)getWeightBefore2/100, (float)getWeightAfter2/100);
+			printf("\r\n��3����: %2.2f Kg -> %2.2f Kg\r\n", (float)getWeightBefore3/100, (float)getWeightAfter3/100);
+			printf("\r\n��4����: %2.2f Kg -> %2.2f Kg\r\n", (float)getWeightBefore4/100, (float)getWeightAfter4/100);
+
+			//��һ���������
+			if(getWeightAfter1 < getWeightBefore1)
+			{
+				getWeight1 = 0;
+			}else{
+				tempWeight = getWeightAfter1 - getWeightBefore1;		//��ǰ���� - ����ǰ������ = һ��Ͷ�ŵ�����
+				if(tempWeight >= 10)																//����������100gʱ�����ֵ
+				{
+					getWeight1 = tempWeight;
+				}else{
+					getWeight1 = 0;
+				}
+			}
+			
+			//�ڶ����������
+			if(getWeightAfter2 < getWeightBefore2)
+			{
+				getWeight2 = 0;
+			}else{
+				tempWeight = getWeightAfter2 - getWeightBefore2;		//��ǰ���� - ����ǰ������ = һ��Ͷ�ŵ�����
+				if(tempWeight >= 10)																//����������100gʱ�����ֵ
+				{
+					getWeight2 = tempWeight;
+				}else{
+					getWeight2 = 0;
+				}
+			}
+			
+			//�������������
+			if(getWeightAfter3 < getWeightBefore3)
+			{
+				getWeight3 = 0;
+			}else{
+				tempWeight = getWeightAfter3 - getWeightBefore3;
+				getWeight3 = (tempWeight >= 10) ? tempWeight : 0;
+			}
+			
+			//�������������
+			if(getWeightAfter4 < getWeightBefore4)
+			{
+				getWeight4 = 0;
+			}else{
+				tempWeight = getWeightAfter4 - getWeightBefore4;
+				getWeight4 = (tempWeight >= 10) ? tempWeight : 0;
+			}
+
+			printf("\r\n���ڻ�ȡ�������\r\n");
+			controlSteps = 0x11;											//ת����ȡ�������
+			break;
+			
+		case 0x11:			//��ȡ�������
+			printf("\r\n�����ݽ��л���\r\n");
+			controlSteps = 0x12;
+			break;
+		
+		case 0x12:			//�Ա���Ͷ������������ݻ���				
+// 			printf("\r\n---------> ����Ͷ���������£�\r\n");
+			
+			controlSteps = 0x13;
+			break;
+			
+		case 0x13:
+			printf("\r\n��־Ͷ�����������ɣ�\r\n");
+			putInEndMark = 1;											//��־Ͷ�Ų�������ɣ������ϴ�Ͷ������
+			
+//			disinfectingMark = 1;									//Ͷ�Ž�����������
+//			sprayDisinfectingMark = 1;
+			
+			//���ӿ��������쳣����
+// 			controlSteps = 0x40;
+			controlSteps = 0x14;
+// 			timer_restart(&waitingTimer_100ms);
+			break;
+			
+		case 0x40:
+
+			break;
+			
+		case 0x14:
+			ClearDevCtrlVar();										//���Ͷ�Ź�����ʹ�õı�����Ϣ��Ϊ��һ��Ͷ��׼��
+			
+			printf("\r\n---> Ͷ�ſ�����ɣ�\r\n");
+			controlSteps = 0x00;
+
+			break;
+			
+		case 0x15:		//Ͱ�Ѿ�װ���˳�����
+			printf("\r\n��MCU1����Ͱ������ֹ����ָ��\r\n");
+			ClearPutInInfo();											//���Ͷ�Ź�����ʹ�õı�����Ϣ��Ϊ��һ��Ͷ��׼��
+				
+// 			SetKeyLedOFF(1);
+// 			SetKeyLedOFF(2);
+			
+			printf("\r\n---------> ����Ͷ�ţ�����\r\n");
+			controlSteps = 0x00;
+			break;
+
+
+		
+		case 0x20:		//�豸�����˳���������λ����û�бպϣ�
+			printf("\r\n��MCU1�����豸����ָ��\r\n");
+// 			SendEquipmentFailureCMD();						//�����������豸����ָ��
+			ClearPutInInfo();											//���Ͷ�Ź�����ʹ�õı�����Ϣ��Ϊ��һ��Ͷ��׼��
+				
+			SetKeyLedOFF(1);
+			SetKeyLedOFF(2);
+			
+			faultLedFlashMark = 1;								//��־�豸���ϣ�������ʾ
+			deviceFault = 1;											//��־�豸���ϣ����쳣������������ϵͳ
+			
+			printf("\r\n---------> ����Ͷ�Ž���������\r\n");
+			controlSteps = 0x21;
+			break;
+			
+		case 0x21:
+			//��������λ�����쳣�ͻ����е��˴���ֱ���޸�
+			break;
+			
+		default:
+			controlSteps = 0x00;
+			break;
+	}
+}
+
+/*
+***********************************************************************
+*	�� �� ��: CleanHolding
+*	����˵��: ������Ч���ִ���
+*	��    �Σ���
+*	�� �� ֵ: ��
+***********************************************************************
+*/
+void CleanHolding(void)
+{
+	static uint8_t currentStatus = 0x00;
+	static uint8_t nextStatus = 0x00;
+	
+	static timer cleanHoldingTimer;									//���˹�����Ч����ʱ�䣨���ڿ���ˢ���˿�������Чʱ�����ǲ�ִ�����������ģ�
+	
+	static uint8_t timer_ok = 0;
+	if(timer_ok == 0)
+	{
+		timer_ok = 1;
+		
+ 		timer_set(&cleanHoldingTimer, CLOCK_SECOND*60*3);
+	}
+	
+	currentStatus = nextStatus;
+	switch(currentStatus)
+	{
+		case 0x00:
+			if((disinfectingMark == 2) || (sprayDisinfectingMark == 2))
+			{
+				printf("\r\n��ǰ�������ˣ�����һ��ʱ�䲻������\r\n");
+				timer_restart(&cleanHoldingTimer);
+				nextStatus = 0x01;
+				break;
+			}
+			break;
+		
+		case 0x01:
+			if(timer_expired(&cleanHoldingTimer))
+			{
+				printf("\r\n���˱���ʱ�䵽��\r\n");
+				disinfectingMark = 0;
+				sprayDisinfectingMark = 0;
+				nextStatus = 0x00;
+				break;
+			}
+			break;
+		
+		default: break;
+	}
+}
+
+/*
+***********************************************************************
+*	�� �� ��: CollectorLockCtrlTask
+*	����˵��: ��������������������
+*	��    �Σ���
+*	�� �� ֵ: ��
+***********************************************************************
+*/
+void CollectorLockCtrlTask(void)
+{
+	static uint8_t runningSteps = 0;
+
+	static timer eleLockUnlockingTimer;							//���������ʱ��
+	static timer waitingTimer;
+	
+	static uint8_t timer_ok = 0;
+	
+	if(timer_ok == 0)
+	{
+		timer_ok = 1;
+		timer_set(&eleLockUnlockingTimer, 2);
+		timer_set(&waitingTimer, 2);
+	}
+
+	switch(runningSteps)
+	{
+		case 0x00:		//��ʼ״̬
+			//ˢ���˿�����
+			if(boxOpenMark == 1)
+			{
+				boxOpenMark = 0; 
+				
+				disinfectingMark = 2;		 									//��������ʱ��ͣ����
+				sprayDisinfectingMark = 2;
+				
+				runningSteps = 0x01;
+				break;
+			}
+			break;
+			
+		case 0x01:		//�ϴ�������Ա������Ϣ
+			printf("\r\n�������ţ�\r\n");
+// 			Unlock(5);
+			Unlock(6);
+			timer_restart(&eleLockUnlockingTimer);
+			runningSteps = 0x02;
+			break;
+			
+		case 0x02:		//�����ȴ�
+			if(timer_expired(&eleLockUnlockingTimer))
+			{
+// 				Locked(5);
+				Locked(6);
+				timer_restart(&waitingTimer);
+				runningSteps = 0x03;
+				break;
+			}
+			break;
+			
+		case 0x03:		//�˳�
+			if(timer_expired(&waitingTimer))
+			{
+				boxOpenMark = 0;
+				runningSteps = 0x00;
+				break;
+			}
+			break;
+			
+		default:
+			break;
+	}
+	
+	CleanHolding();									//������Ч���ִ��������ڿ���ˢ���˿�������Чʱ�����ǲ�ִ������������
+}
+
+/*
+***********************************************************************
+*	�� �� ��: FillLightTask
+*	����˵��: ���ղ���ƴ�������
+*	��    ��:	��
+*	�� �� ֵ: ��
+***********************************************************************
+*/
+void FillLightTask(void)
+{
+  static uint8_t ledStatus = 0;
+  
+  static timer ledOnTimer;	
+  static timer ledOffTimer;	
+	static uint8_t timer_ok = 0;
+	
+	if(timer_ok == 0)
+	{
+		timer_ok = 1;
+		timer_set(&ledOnTimer, 150);
+	}
+  
+  switch(ledStatus)
+  {
+    case 0x00:
+      if(fillLightMask == 1)
+			{
+				Unlock(1);
+				Unlock(2);
+				printf("\r\n�򿪲���ƣ�\r\n");
+					
+				timer_restart(&ledOnTimer);
+				ledStatus = 0x01;
+				break;
+			}
+      break;
+      
+    case 0x01:
+      if(timer_expired(&ledOnTimer))
+      {
+				Locked(1);
+				Locked(2);
+				
+				printf("\r\n�رղ���ƣ�\r\n");
+					
+        fillLightMask = 0;
+        ledStatus = 0x00;
+      }
+      break;
+      
+    default:
+      ledStatus = 0x00;
+      break;
+  }
+}
+
+/*
+***********************************************************************
+*	�� �� ��: CoolingFanCtrlTask
+*	����˵��: ɢ�ȷ��ȿ�������
+*	��    �Σ���
+*	�� �� ֵ: ��
+***********************************************************************
+*/
+void CoolingFanCtrlTask(void)
+{
+	static uint8_t currentStatus = 0x00;
+	static uint8_t nextStatus = 0x00;
+	
+	static timer responseTimeout;
+	static uint8_t timer_ok = 0;
+	
+	if(timer_ok == 0)
+	{
+		timer_ok = 1;
+		timer_set(&responseTimeout, CLOCK_SECOND*10);
+	}
+	
+	currentStatus = nextStatus;
+	switch(currentStatus)
+	{
+		case 0x00:
+			if(temperature >= 40)
+			{
+				printf("\r\n�¶ȹ��ȣ�����ɢ�ȷ��ȣ�\r\n");
+				Unlock(3);
+				Unlock(4);
+				nextStatus = 0x01;
+				break;
+			}
+			break;
+			
+		case 0x01:
+			if(temperature <= 38)
+			{
+				printf("\r\n�¶Ȼָ�������\r\n");
+				Locked(3);
+				Locked(4);
+				nextStatus = 0x00;
+				break;
+			}
+			break;
+			
+		default:
+			break;
+	}
+}
+
+/*
+***********************************************************************
+*	�� �� ��: SprayCtrlTask
+*	����˵��: ���ܿ�������
+*	��    �Σ���
+*	�� �� ֵ: ��
+***********************************************************************
+*/
+void SprayCtrlTask(void)
+{
+	static uint8_t currentStatus = 0x00;
+	static uint8_t nextStatus = 0x00;
+	
+	static timer responseTimeout;
+	static uint8_t timer_ok = 0;
+	
+	if(timer_ok == 0)
+	{
+		timer_ok = 1;
+		timer_set(&responseTimeout, CLOCK_SECOND*10);
+	}
+	
+	currentStatus = nextStatus;
+	switch(currentStatus)
+	{
+		case 0x00:
+			if(LIMI_KEY3 == 0)
+			{
+				printf("\r\n������������⵽�쳣���������ܣ�\r\n");
+				DoorClose(4);
+				beep_warningBeepMark = 1;
+				
+				smokeAlarmStatus = 1;
+				PC_ProCommandSend(0x65);
+				nextStatus = 0x02;
+				break;
+			}
+			
+			if(temperature >= 80)
+			{
+				printf("\r\n�¶ȹ���(>80��)���������ܣ�\r\n");
+// 				DoorClose(4);
+				beep_warningBeepMark = 1;
+				nextStatus = 0x01;
+				break;
+			}
+			break;
+			
+		case 0x01:		//�¶ȹ��ȴ���
+			if(temperature <= 75)
+			{
+				printf("\r\n�¶�(<75��)�ָ�������\r\n");
+// 				DoorStop(4);
+				nextStatus = 0x00;
+				break;
+			}
+			beep_warningBeepMark = 1;
+			break;
+			
+		case 0x02:		//������������⵽�쳣����
+			if(LIMI_KEY3 == 1)
+			{
+				printf("\r\n�����������ָ�������\r\n");
+				DoorStop(4);
+				
+				smokeAlarmStatus = 0;
+				PC_ProCommandSend(0x65);
+				nextStatus = 0x00;
+			}
+			beep_warningBeepMark = 1;
+			break;
+			
+		default:
+			break;
+	}
+}
+
+/*
+***********************************************************************
+*	�� �� ��: SystemExceptionTask
+*	����˵��: ϵͳ�쳣��������
+*	��    �Σ���
+*	�� �� ֵ: ��λ��ɺ󷵻�1
+***********************************************************************
+*/
+void SystemExceptionTask(void)
+{
+	static uint8_t restartSteps = 0x00;
+	static uint8_t ledFlashStatus = 0;
+	
+	static timer restartTimer;
+	static timer ledFlashTimer;	
+	static uint8_t timer_ok = 0;
+	
+	if(timer_ok == 0)
+	{
+		timer_ok = 1;
+		timer_set(&restartTimer, CLOCK_SECOND*20);	
+		timer_set(&ledFlashTimer, 5);							//LED��˸ʱ��		
+	}
+	
+	switch(restartSteps)
+	{
+		case 0x00:
+			if(deviceFault == 1)		//�豸��⵽ϵͳ�쳣��������쳣����
+			{
+				restartSteps = 0x01;
+				timer_restart(&restartTimer);
+				break;
+			}
+			break;
+			
+		case 0x01:
+			if(timer_expired(&restartTimer))		//������ѭ���ÿ��Ź���λϵͳ
+			{
+				while(1);
+			}
+			break;
+			
+		default:
+			break;
+	}
+	
+	//�����쳣ʱָʾ����˸
+	switch(ledFlashStatus)
+	{
+		case 0x00:
+			if(faultLedFlashMark == 1)
+			{
+				SetKeyLedON(3);
+				SetKeyLedON(4);
+				if(timer_expired(&ledFlashTimer))
+				{
+					ledFlashStatus = 0x01;
+					timer_restart(&ledFlashTimer);
+				}
+			}
+			break;
+			
+		case 0x01:
+			SetKeyLedOFF(3);
+			SetKeyLedOFF(4);
+			if(timer_expired(&ledFlashTimer))
+			{
+				ledFlashStatus = 0x00;
+				timer_restart(&ledFlashTimer);
+			}
+			break;
+			
+		default:
+      ledFlashStatus = 0x00;
+      break;
+	}
+}
+
+/******************** (C) COPYRIGHT 2017 CXHY *****END OF FILE*******************/
diff --git a/STM32_4路称重_Git提交精简工程/src/HARDWARE/DEVICE/device.h b/STM32_4路称重_Git提交精简工程/src/HARDWARE/DEVICE/device.h
new file mode 100755
index 0000000..7f10d44
--- /dev/null
+++ b/STM32_4路称重_Git提交精简工程/src/HARDWARE/DEVICE/device.h
@@ -0,0 +1,72 @@
+/*************************** (C) COPYRIGHT 2017 CXHY ****************************
+ * �ļ���  ��device.h
+ * ��  ��  ���豸���Ƴ���
+ * ��  ��  ��V1.0
+ * ��  ��  ��XuZhongPing
+ * ��  ��  ��2017/03/06 
+*********************************************************************************/
+#ifndef __DEVICE_H
+#define __DEVICE_H
+
+//�ķ���+�к��������Ͷ��壨�ķ���һ�������Ҫ���˶���ע�͵���
+#define FOUR_CHANNEL_AND_HARMFUL
+#define FOUR_DROP_PORTS
+
+#include "stm32f10x.h"
+#include "usart1.h"
+#include "usart2.h"
+#include "usart3.h"
+#include "usart4.h"
+#include "usart5.h"
+
+#include "string.h" 
+#include "stdlib.h" 
+
+#include "led.h"
+#include "key.h"
+#include "opto_sw_key.h"
+#include "sw_key.h"
+#include "buzzer.h" 
+#include "scale.h"
+#include "ElectronicLock.h"
+#include "motor.h"
+#include "RFID_IC.h"
+#include "qr_code.h"
+#include "ntc.h"
+#include "sound.h"
+#include "spi.h"
+#include "flash.h" 
+#include "stmflash.h"
+#include "distancer.h"
+
+#include "ec200x.h"
+#include "disinfection.h"
+#include "door_ctrl.h"
+#include "m_s_comm.h"
+
+#define VersionNumber "V2.1_260709_4CH"
+
+void show(uint8_t num[], uint8_t n);
+void CalcOverflowStartPointParam(void);
+void DeviceInit(void);										//�豸��ʼ��
+void DeviceTest(void);										//Ӳ������
+void UserIdentificationTask(void);
+uint8_t GetPutInType(void);								//ȡ�ÿ���Ͷ������
+void ShowPutInTyep(uint8_t uType);
+void GetUserInfo(uint8_t inputType);			//���ݿ�������ʽ��ȡ���û��������Ϣ 
+void ClearPutInInfo(void);								//�����������
+
+
+void DeviceScanning(void);
+void PutInOpenDoorTask(void);
+void OpenDoorRequestTask(void);
+void DeviceControlTask(void);
+void CollectorLockCtrlTask(void);
+void FillLightTask(void);
+void CoolingFanCtrlTask(void);
+void SprayCtrlTask(void);
+void SystemExceptionTask(void);
+
+#endif
+
+/******************** (C) COPYRIGHT 2017 CXHY *****END OF FILE*******************/
diff --git a/STM32_4路称重_Git提交精简工程/src/HARDWARE/DEVICE/deviceSet.c b/STM32_4路称重_Git提交精简工程/src/HARDWARE/DEVICE/deviceSet.c
new file mode 100755
index 0000000..180fda8
--- /dev/null
+++ b/STM32_4路称重_Git提交精简工程/src/HARDWARE/DEVICE/deviceSet.c
@@ -0,0 +1,1694 @@
+/*************************** (C) COPYRIGHT 2017 CXHY ****************************
+ * �ļ���  ��device.c
+ * ��  ��  ���ⲿ�豸���Ƽ��
+ * ��  ��  ��V1.0
+ * ��  ��  ��XuZhongPing
+ * ��  ��  ��2017/09/04
+*********************************************************************************/
+#include "deviceSet.h"
+#include "device.h"
+#include "usart1.h"
+#include "usart2.h"
+#include "delay.h"
+#include "timer.h"
+#include "data_typedef.h"	  
+#include "tcp_protocol.h"
+#include "lcd.h"  
+#include "display.h"
+#include "stmflash.h"
+#include "qr_code.h"
+#include "scale.h"
+
+
+/*
+***********************************************************************
+*	�� �� ��: ShowRecyclingType
+*	����˵��: ��ʾ����������
+*	��    �Σ�type -> �ɻ���������
+*	�� �� ֵ: ��
+***********************************************************************
+*/
+void ShowRecyclingType(uint8_t type)
+{
+	switch(type)
+	{
+		case PAPER:
+			printf("ֽ��");
+			break;
+			
+		case PLASTIC:
+			printf("����");
+			break;
+			
+		case GLASS:
+			printf("����");
+			break;
+			
+		case METAL:
+			printf("����");
+			break;
+			
+		case RECYCLED:
+			printf("�ɻ�����");
+			break;
+			
+		case KITCHEN:
+			printf("����");
+			break;
+			
+		case SMALL_BOTTLE:
+			printf("С����ƿ��");
+			break;
+			
+		case BIG_BOTTLE:
+			printf("������ƿ��");
+			break;
+			
+		case CANS:
+			printf("������");
+			break;
+			
+		case BATTERY:
+			printf("���");
+			break;
+			
+		case FABRIC:
+			printf("֯��");
+			break;
+			
+		case BOOK:
+			printf("�鱾");
+			break;
+			
+		case NEWSPAPER:
+			printf("��ֽ");
+			break;
+			
+		case KITCHEN_1:
+			printf("����1");
+			break;
+			
+		case KITCHEN_2:
+			printf("����2");
+			break;
+			
+		case PLASTIC_2:
+			printf("����2");
+			break;
+			
+		case OTHER:
+			printf("����");
+			break;
+		
+		case HARMFUL:
+			printf("�к�");
+			break;
+			
+		case DRY_WASTES:
+			printf("������");
+			break;
+			
+		case WET_WASTES:
+			printf("ʪ����");
+			break;
+		
+		default:
+			printf("δ֪(%d)", type);
+			break;
+	}
+}
+
+/*
+***********************************************************************
+*	�� �� ��: DeviceInfoShow
+*	����˵��: �豸��Ϣ��ʾ
+*	��    �Σ���
+*	�� �� ֵ: ��
+***********************************************************************
+*/
+void DeviceInfoShow(void)
+{
+	printf("\r\n�豸��Ϣ��\r\n");
+	printf("------------\r\n");
+	
+	printf("����%s\r\n", VersionStr);
+	
+	switch(deviceType)
+	{
+		case SINGLE_CLASSIFICATION:
+			printf("�豸����: ��һ�����豸�� (");
+			ShowRecyclingType(devChannel1Type);
+			printf(")\r\n");
+			break;
+			
+		case DOUBLE_CLASSIFICATION:
+			printf("�豸����: ���������豸�� (");
+			ShowRecyclingType(devChannel1Type);
+			printf("��");
+			ShowRecyclingType(devChannel2Type);
+			printf(")\r\n");
+			break;
+			
+		case DOUBLE_CLASSIFICATION_BOTTLE:
+			printf("�豸����: ���������豸_��ƿ�ࡱ (");
+			ShowRecyclingType(devChannel1Type);
+			printf("��");
+			ShowRecyclingType(devChannel2Type);
+			printf(")\r\n");
+			break;
+			
+		case THREE_CLASSIFICATION:
+			printf("�豸����: ���������豸�� (");
+			ShowRecyclingType(devChannel1Type);
+			printf("��");
+			ShowRecyclingType(devChannel2Type);
+			printf("��");
+			ShowRecyclingType(devChannel3Type);
+			printf(")\r\n");
+			break;
+			
+		case FOUR_CLASSIFICATION:
+			printf("�豸����: ���ķ����豸�� (");
+			ShowRecyclingType(devChannel1Type);
+			printf("��");
+			ShowRecyclingType(devChannel2Type);
+			printf("��");
+			ShowRecyclingType(devChannel3Type);
+			printf("��");
+			ShowRecyclingType(devChannel4Type);
+			printf(")\r\n");
+			break;
+	}
+	
+	Screen_ShowDeviceInfo(VersionStr, devChannel1Type, devChannel2Type, devChannel3Type, devChannel4Type);
+
+	printf("---------------------------\r\n");
+}
+
+/*
+***********************************************************************
+*	�� �� ��: SetDefaultOverflowAlarmParam
+*	����˵��: �������籨��Ĭ�ϲ���
+*	��    �Σ���
+*	�� �� ֵ: ��
+***********************************************************************
+*/
+void SetDefaultOverflowAlarmParam(void)
+{
+	switch(deviceType)
+	{
+		case SINGLE_CLASSIFICATION:		//������
+			break;
+			
+		case DOUBLE_CLASSIFICATION:		//������
+			break;
+			
+		case DOUBLE_CLASSIFICATION_BOTTLE:		//�����ຬƿ��
+			break;
+			
+		default:
+			break;
+	}
+	
+// 	printf("\r\n����Ĭ���������: h1 = %d; H1 = %d; A1 = %d; h2 = %d; H2 = %d; A2 = %d;\r\n", 
+// 						setDistance_L_DepthVal, setDistance_L_MaxVal, setDistance_L_AlarmPercent,
+// 						setDistance_R_DepthVal, setDistance_R_MaxVal, setDistance_R_AlarmPercent);
+}
+
+/*
+***********************************************************************
+*	�� �� ��: DeviceSetParamInit
+*	����˵��: �豸���ò�����ʼ��
+*	��    �Σ���
+*	�� �� ֵ: ��
+***********************************************************************
+*/
+void DeviceSetParamInit(void)
+{	
+	setDeviceType = deviceType;
+	setDevChannelNumbers = devChannelNumbers;
+	setDevChannel1Type = devChannel1Type;
+	setDevChannel2Type = devChannel2Type;
+	setDevChannel3Type = devChannel3Type;
+	setDevChannel4Type = devChannel4Type;
+
+	setPassword = password;																	//Ҫ���õ��豸��������
+	setCustomerID = customerID;															//�ͻ��ţ����ڿ���˭���Դ����������ţ�
+
+	setDevChannel1DisDepthVal = devChannel1DisDepthVal;
+	setDevChannel1DisMaxVal = devChannel1DisMaxVal;
+	setDevChannel1DisAlarmPercent = devChannel1DisAlarmPercent;
+
+	setDevChannel2DisDepthVal = devChannel2DisDepthVal;
+	setDevChannel2DisMaxVal = devChannel2DisMaxVal;
+	setDevChannel2DisAlarmPercent = devChannel2DisAlarmPercent;
+	
+	setDevChannel3DisDepthVal = devChannel3DisDepthVal;
+	setDevChannel3DisMaxVal = devChannel3DisMaxVal;
+	setDevChannel3DisAlarmPercent = devChannel3DisAlarmPercent;
+	
+	setDevChannel4DisDepthVal = devChannel4DisDepthVal;
+	setDevChannel4DisMaxVal = devChannel4DisMaxVal;
+	setDevChannel4DisAlarmPercent = devChannel4DisAlarmPercent;
+	
+	setDisableICCardFunStatus = disableICCardFunStatus;				//���á�����IC���û������ܱ�־λ
+	setEnableCleanQRCodeStatus = enableCleanQRCodeStatus;			//���á��������˿���ά�뿪�š���־
+	
+	printf("\r\n�豸���ò�����ʼ����ɣ�����\r\n");
+	printf("\r\nSetParam:\r\n");
+	printf("P=%d; ID=%d; DevType=%d; Cnt=%d\r\n",
+						setPassword,
+						setCustomerID,
+						setDeviceType,
+						setDevChannelNumbers);
+					
+	printf("T1=%d, h1=%d, H1=%d, A1=%d\r\n",
+						setDevChannel1Type, setDevChannel1DisDepthVal, setDevChannel1DisMaxVal, setDevChannel1DisAlarmPercent);
+						
+	printf("T2=%d, h2=%d, H2=%d, A2=%d\r\n",
+						setDevChannel2Type, setDevChannel2DisDepthVal, setDevChannel2DisMaxVal, setDevChannel2DisAlarmPercent);
+		
+	printf("T3=%d, h3=%d, H3=%d, A3=%d\r\n",
+						setDevChannel3Type, setDevChannel3DisDepthVal, setDevChannel3DisMaxVal, setDevChannel3DisAlarmPercent);
+						
+	printf("T4=%d, h4=%d, H4=%d, A4=%d\r\n",
+						setDevChannel4Type, setDevChannel4DisDepthVal, setDevChannel4DisMaxVal, setDevChannel4DisAlarmPercent);
+					
+	printf("ICE=%d, ICQR=%d\r\n", setDisableICCardFunStatus, setEnableCleanQRCodeStatus);
+}
+
+/*
+***********************************************************************
+*	�� �� ��: DeviceParamInit
+*	����˵��: �豸������ʼ��
+*	��    �Σ���
+*	�� �� ֵ: ��
+***********************************************************************
+*/
+void DeviceParamInit(void)
+{	
+	password = setPassword;
+	customerID = setCustomerID;
+	
+	deviceType = setDeviceType;
+	devChannelNumbers = setDevChannelNumbers;
+	devChannel1Type = setDevChannel1Type;
+	devChannel2Type = setDevChannel2Type;
+	devChannel3Type = setDevChannel3Type;
+	devChannel4Type = setDevChannel4Type;
+
+#ifdef FOUR_DROP_PORTS
+	deviceType = FOUR_CLASSIFICATION;
+	devChannelNumbers = 4;
+	setDeviceType = deviceType;
+	setDevChannelNumbers = devChannelNumbers;
+#endif
+	
+	devChannel1DisDepthVal = setDevChannel1DisDepthVal;
+	devChannel1DisMaxVal = setDevChannel1DisMaxVal;
+	devChannel1DisAlarmPercent = setDevChannel1DisAlarmPercent;
+	
+	devChannel2DisDepthVal = setDevChannel2DisDepthVal;
+	devChannel2DisMaxVal = setDevChannel2DisMaxVal;
+	devChannel2DisAlarmPercent = setDevChannel2DisAlarmPercent;
+	
+	devChannel3DisDepthVal = setDevChannel3DisDepthVal;
+	devChannel3DisMaxVal = setDevChannel3DisMaxVal;
+	devChannel3DisAlarmPercent = setDevChannel3DisAlarmPercent;
+	
+	devChannel4DisDepthVal = setDevChannel4DisDepthVal;
+	devChannel4DisMaxVal = setDevChannel4DisMaxVal;
+	devChannel4DisAlarmPercent = setDevChannel4DisAlarmPercent;
+	
+	disableICCardFunStatus = setDisableICCardFunStatus;
+	enableCleanQRCodeStatus = setEnableCleanQRCodeStatus;
+					
+	printf("\r\nDevice Param Init OK������\r\n");
+	printf("\r\nCurParam:\r\n");
+	printf("P=%d; ID=%d; DevType=%d; Cnt=%d\r\n",
+						password,
+						customerID,
+						deviceType,
+						devChannelNumbers);
+					
+	printf("T1=%d, h1=%d, H1=%d, A1=%d\r\n",
+						devChannel1Type, devChannel1DisDepthVal, devChannel1DisMaxVal, devChannel1DisAlarmPercent);
+						
+	printf("T2=%d, h2=%d, H2=%d, A2=%d\r\n",
+						devChannel2Type, devChannel2DisDepthVal, devChannel2DisMaxVal, devChannel2DisAlarmPercent);
+		
+	printf("T3=%d, h3=%d, H3=%d, A3=%d\r\n",
+						devChannel3Type, devChannel3DisDepthVal, devChannel3DisMaxVal, devChannel3DisAlarmPercent);
+						
+	printf("T4=%d, h4=%d, H4=%d, A4=%d\r\n",
+						devChannel4Type, devChannel4DisDepthVal, devChannel4DisMaxVal, devChannel4DisAlarmPercent);
+					
+	printf("ICE=%d, ICQR=%d\r\n", disableICCardFunStatus, enableCleanQRCodeStatus);
+}
+
+
+//-----------------------------------------------------------------------------------
+//ͨ����ά�������豸����
+
+/*
+***********************************************************************
+*	�� �� ��: StrToInt
+*	����˵��: �ַ���ת�������ݣ�����ʽУ�飩
+*	��    �Σ�str -> ��ת�����ַ���
+*	�� �� ֵ: ת������������ݣ�����ʽ����ȷʱ����0xFFFFFFFF
+***********************************************************************
+*/
+uint32_t StrToInt(char *str)
+{
+	uint32_t res = 0xFFFFFFFF;
+	
+	if(strlen(str) < 10)		//Ҫת�������ݳ���С��10λ��
+	{
+		if(strspn(str, "0123456789") == strlen(str))		//У�������ǲ��Ƕ����������
+		{
+			res = atoi(str);
+		}else{
+			res = 0xFFFFFFFF;
+			printf("\r\n���ݸ�ʽ����\r\n");
+		}
+	}
+	return res;
+}
+
+/*
+***********************************************************************
+*	�� �� ��: StrArrToIntArr
+*	����˵��: �ַ�������ת������������
+*	��    �Σ�strArr -> ��ת�����ַ�������
+						intArr -> ת�������������
+						len -> Ҫת�����鳤��
+*	�� �� ֵ: ת���ɹ�����1��ʧ�ܷ�0
+***********************************************************************
+*/
+uint8_t StrArrToIntArr(char strArr[][16], uint32_t intArr[], uint8_t len)
+{
+	uint8_t i = 0;
+	uint32_t temp;
+	
+// 	printf("\r\nstrArr[i] = {", strArr[i]);
+	for(i = 0; i < len; i++)
+	{
+// 		printf("%s, ", strArr[i]);
+		temp = StrToInt(strArr[i]);										//���ַ���ת������������
+		if(temp != 0xFFFFFFFF)
+		{
+			intArr[i] = temp;
+		}else{
+			printf("\r\nwrong format��\r\n");
+			return 0;
+		}
+	}
+// 	printf("}\r\n");
+	
+	return 1;
+}
+
+/*
+***********************************************************************
+*	�� �� ��: StringSplit
+*	����˵��: �ַ������
+*	��    �Σ�str -> �������ַ���
+*	�� �� ֵ: �������뷵��1�����󷵻�0
+***********************************************************************
+*/
+uint8_t StringSplit(char *str)
+{
+	uint8_t res = 0;
+	uint8_t i = 0;
+	uint32_t temp = 0xFFFFFFFF;
+	static uint8_t preSetParamCmd = 0;							//��һ�ε�������
+	char *token;
+	
+	memset(setParamList, 0x00, 16*16);
+	
+	//�ֽ��������
+	printf("\r\n���������\r\n");
+
+	setParamCount = 0;
+	token = strtok(str, ",");
+	while (token != NULL)
+	{
+// 		printf("\r\nparam%d %s\r\n", setParamCount, token);
+		if(strlen(token) < 16)
+		{
+			strcpy(setParamList[setParamCount], token);
+			token = strtok(NULL, ",");
+			setParamCount++;
+		}else{
+			printf("\r\n����������������ȹ���\r\n");
+			return 0;
+		}
+	}
+	
+	printf("\r\nlen = %d, dataList: {", setParamCount);
+	for(i = 0; i < setParamCount; i++)
+	{
+		printf("%s, ", setParamList[i]);
+	}
+	printf("}\r\n");
+	
+	//�ֽ��������		
+	temp = StrToInt(setParamList[0]);							//���ַ���ת������������
+	if(temp != 0xFFFFFFFF)
+	{
+		setParamCmd = temp;													//�����������ָ����
+		res = 1;
+		printf("\r\ncmd = %d\r\n", setParamCmd);
+		
+		if((preSetParamCmd != setParamCmd) && (setParamCmd != 1))
+		{
+			if(setParamCmd != 1)
+			{
+				setParamChangeMark = 1;
+				printf("\r\nָ���б仯��\r\n");
+			}
+			preSetParamCmd = setParamCmd;
+		}
+	}else{
+		res = 0;
+		printf("\r\n�������\r\n");
+	}
+	
+	return res;
+}
+
+/*
+***********************************************************************
+*	�� �� ��: SetParamDecode
+*	����˵��: ���ò�������
+*	��    �Σ���
+*	�� �� ֵ: ��
+***********************************************************************
+*/
+void SetParamDecode(uint8_t *pSetParamStr)
+{
+	uint32_t temp = 0xFFFFFFFF;
+	char paramBuf[128];
+	uint32_t intDataArr[16];
+	uint8_t i = 0;
+	uint8_t len = 0;
+	uint8_t decodeOkMark = 0;
+	
+	char *p;
+	char *pParam;
+	char *token;
+	
+	p = (char*)strstr((const char*)pSetParamStr, ":");
+	pParam = p+1;
+	memset(paramBuf, 0x00, 128);
+	strcpy(paramBuf, pParam);												//�ȱ������õĲ�������
+	
+	decodeOkMark = StringSplit(paramBuf);						//��ֳ�������
+	
+	//�ж��Ƿ�Ϊ��������������
+	if(decodeOkMark == 1)
+	{
+		printf("\r\nsetCmd = %d\r\n", setParamCmd);
+		switch(setParamCmd)
+		{
+			case 1:		//��������ȷ��
+				printf("\r\nSET --> ��������ȷ�ϣ�\r\n");
+				printf("\r\nlist[1]��%s\r\n", setParamList[1]);
+				
+				temp = StrToInt(setParamList[1]);								//���ַ���ת������������
+				if(temp != 0xFFFFFFFF)
+				{
+					getConfirmPassword = temp;									
+					getConfirmPasswordMark = 1;										//��־�Ѿ�ȡ�ô�ȷ�ϵ�����
+					printf("\r\n����Ϊ��%d\r\n", getConfirmPassword);
+				}else{
+					getConfirmPasswordMark = 0;
+					printf("\r\nȷ���������ݸ�ʽ����\r\n");
+					break;
+				}
+				break;
+				
+			case 2:		//�����޸�
+				printf("\r\nSET --> �����޸ģ�\r\n");
+				printf("\r\nlist[1]��%s\r\n", setParamList[1]);
+				
+				temp = StrToInt(setParamList[1]);													//���ַ���ת������������
+				if(temp != 0xFFFFFFFF)
+				{
+					getPassword = temp;										
+					getPasswordMark = 1;													//��־�Ѿ�ȡ�ô�ȷ�ϵ�����
+					printf("\r\n����Ϊ��%d\r\n", getPassword);
+				}else{
+					getPasswordMark = 0;
+					printf("\r\n�����������ݸ�ʽ����\r\n");
+					break;
+				}
+				break;
+				
+			case 3:		//�豸��������
+				printf("\r\nSET --> �豸�������ã�\r\n");
+				
+				//�豸����
+				printf("\r\nlist[1]��%s\r\n", setParamList[1]);
+				temp = StrToInt(setParamList[1]);										//���ַ���ת������������
+				if(temp != 0xFFFFFFFF)
+				{
+					getDeviceType = temp;											
+					printf("\r\n�豸����Ϊ��%d\r\n", getDeviceType);
+				}else{
+					getDeviceTypeMark = 0;
+					printf("\r\n�����������ݸ�ʽ����\r\n");
+					break;
+				}
+				
+				//Ͷ��ͨ������
+				printf("\r\nlist[2]��%s\r\n", setParamList[2]);
+				temp = StrToInt(setParamList[2]);										//���ַ���ת������������
+				if(temp != 0xFFFFFFFF)
+				{
+					getDevChannelNumbers = temp;											
+					printf("\r\n�豸Ͷ��ͨ������Ϊ��%d\r\n", getDevChannelNumbers);
+				}else{
+					getDeviceTypeMark = 0;
+					printf("\r\n�豸Ͷ��ͨ���������ݸ�ʽ����\r\n");
+					break;
+				}
+				
+				temp = StrArrToIntArr(&setParamList[3], intDataArr, getDevChannelNumbers);
+				if(temp == 1)
+				{
+					if(getDevChannelNumbers == 1)		//1����
+					{
+						getDevChannel1Type = intDataArr[0];			
+						getDeviceTypeMark = 1;											//��Ͷ���豸���־����ɹ�
+						printf("\r\n��������1��%d\r\n", getDevChannel1Type);
+					}else if(getDevChannelNumbers == 2){		//2����
+						getDevChannel1Type = intDataArr[0];			
+						getDevChannel2Type = intDataArr[1];			
+						getDeviceTypeMark = 1;											//��־����ɹ�		
+						printf("\r\n��������2��%d, %d\r\n", getDevChannel1Type, getDevChannel2Type);
+					}else if(getDevChannelNumbers == 3){		//3����
+						getDevChannel1Type = intDataArr[0];			
+						getDevChannel2Type = intDataArr[1];
+						getDevChannel3Type = intDataArr[2];			
+						getDeviceTypeMark = 1;											//��־����ɹ�		
+						printf("\r\n��������3��%d, %d, %d\r\n", getDevChannel1Type, getDevChannel2Type, getDevChannel3Type);
+					}else if(getDevChannelNumbers == 4){		//4����
+						getDevChannel1Type = intDataArr[0];
+						getDevChannel2Type = intDataArr[1];
+						getDevChannel3Type = intDataArr[2];
+						getDevChannel4Type = intDataArr[3];			
+						getDeviceTypeMark = 1;											//��־����ɹ�		
+						printf("\r\n��������4��%d, %d, %d, %d\r\n", getDevChannel1Type, getDevChannel2Type, getDevChannel3Type, getDevChannel4Type);	
+					}else{}
+				}else{
+					getDeviceTypeMark = 0;
+					printf("\r\n���û����������ݸ�ʽ����\r\n");
+					break;
+				}
+				break;
+				
+			case 4:		//�豸�ͻ�������
+				printf("\r\nSET --> �豸�ͻ������ã�\r\n");
+				printf("\r\nlist[1]��%s\r\n", setParamList[1]);
+				
+				temp = StrToInt(setParamList[1]);									//���ַ���ת������������
+				if(temp != 0xFFFFFFFF)
+				{
+					getCustomerID = temp;	
+					getCustomerIDMark = 1;													//��־�Ѿ�ȡ�ô�ȷ�ϵ�����
+					printf("\r\n�ͻ���Ϊ��%d\r\n", getCustomerID);
+				}else{
+					getCustomerIDMark = 0;
+					printf("\r\n���ÿͻ������ݸ�ʽ����\r\n");
+				}
+				break;
+				
+			case 5:
+				break;
+				
+			case 6:		//����/ͣ�á����õ�IC�����ܿ��š���������
+				printf("\r\nSET -->�����õ�IC�����ܿ��ţ��������ã�\r\n");
+				printf("\r\nlist[1]��%s\r\n", setParamList[1]);
+				
+				temp = StrToInt(setParamList[1]);												//���ַ���ת������������
+				if(temp != 0xFFFFFFFF)
+				{
+					getDisableICCardFunStatus = temp;	
+					getDisableICCardFunMark = 1;													//��־�Ѿ�ȡ�ô�ȷ�ϵ�����
+					printf("\r\n״̬Ϊ��%d\r\n", getDisableICCardFunStatus);
+					break;
+				}else{
+					getDisableICCardFunMark = 0;
+					printf("\r\n���ã����õ�IC�����ܿ��ţ����ݸ�ʽ����\r\n");
+					break;
+				}
+				break;
+				
+			case 7:		//����/ͣ�á����˶�ά�뿪�š���������
+				printf("\r\nSET -->�����˶�ά�뿪�ţ��������ã�\r\n");
+				printf("\r\nlist[1]��%s\r\n", setParamList[1]);
+				
+				temp = StrToInt(setParamList[1]);												//���ַ���ת������������
+				if(temp != 0xFFFFFFFF)
+				{
+					getEnableCleanQRCodeStatus = temp;	
+					getEnableCleanQRCodeMark = 1;													//��־�Ѿ�ȡ�ô�ȷ�ϵ�����
+					printf("\r\n״̬Ϊ��%d\r\n", getEnableCleanQRCodeStatus);
+					break;
+				}else{
+					getEnableCleanQRCodeMark = 0;
+					printf("\r\n���ã����˶�ά�뿪�ţ����ݸ�ʽ����\r\n");
+					break;
+				}
+				break;
+				
+			case 13:		//���籨����������
+				printf("\r\nSET -->������������������ã�\r\n");
+				
+				//Ͷ��ͨ������
+				printf("\r\nlist[1]��%s\r\n", setParamList[1]);
+				temp = StrToInt(setParamList[1]);										//���ַ���ת������������
+				if(temp != 0xFFFFFFFF)
+				{
+					getDevChannelNumbers = temp;	
+					printf("\r\n�豸Ͷ��ͨ������Ϊ��%d\r\n", getDevChannelNumbers);
+				}else{
+					getDeviceTypeMark = 0;
+					printf("\r\n�豸Ͷ��ͨ���������ݸ�ʽ����\r\n");
+					break;
+				}
+				
+				temp = StrArrToIntArr(&setParamList[2], intDataArr, getDevChannelNumbers*3);
+				if(temp == 1)
+				{
+					if(getDevChannelNumbers == 1)		//1����
+					{
+						getDevChannel1DisDepthVal = intDataArr[0];
+						getDevChannel1DisMaxVal = intDataArr[1];
+						getDevChannel1DisAlarmPercent = intDataArr[2];
+						getOverflowSetMark = 1;											//��Ͷ���豸���־����ɹ�
+						printf("\r\nOF1: %d, %d, %d\r\n", getDevChannel1DisDepthVal, getDevChannel1DisMaxVal, getDevChannel1DisAlarmPercent);
+					}else if(getDevChannelNumbers == 2){		//2����
+						getDevChannel1DisDepthVal = intDataArr[0];
+						getDevChannel1DisMaxVal = intDataArr[1];
+						getDevChannel1DisAlarmPercent = intDataArr[2];
+						
+						getDevChannel2DisDepthVal = intDataArr[3];
+						getDevChannel2DisMaxVal = intDataArr[4];
+						getDevChannel2DisAlarmPercent = intDataArr[5];
+						
+						getOverflowSetMark = 1;											//��־����ɹ�		
+						printf("\r\nOF1: %d, %d, %d; OF2: %d, %d, %d\r\n", getDevChannel1DisDepthVal, getDevChannel1DisMaxVal, getDevChannel1DisAlarmPercent,
+									getDevChannel2DisDepthVal, getDevChannel2DisMaxVal, getDevChannel2DisAlarmPercent);
+					}else if(getDevChannelNumbers == 3){		//3����
+						getDevChannel1DisDepthVal = intDataArr[0];
+						getDevChannel1DisMaxVal = intDataArr[1];
+						getDevChannel1DisAlarmPercent = intDataArr[2];
+						
+						getDevChannel2DisDepthVal = intDataArr[3];
+						getDevChannel2DisMaxVal = intDataArr[4];
+						getDevChannel2DisAlarmPercent = intDataArr[5];
+						
+						getDevChannel3DisDepthVal = intDataArr[6];
+						getDevChannel3DisMaxVal = intDataArr[7];
+						getDevChannel3DisAlarmPercent = intDataArr[8];
+						
+						getOverflowSetMark = 1;											//��־����ɹ�		
+						printf("\r\nOF1: %d, %d, %d; OF2: %d, %d, %d; OF3: %d, %d, %d\r\n", 
+									getDevChannel1DisDepthVal, getDevChannel1DisMaxVal, getDevChannel1DisAlarmPercent,
+									getDevChannel2DisDepthVal, getDevChannel2DisMaxVal, getDevChannel2DisAlarmPercent,
+									getDevChannel3DisDepthVal, getDevChannel3DisMaxVal, getDevChannel3DisAlarmPercent);
+					}else if(getDevChannelNumbers == 4){		//4����
+						getDevChannel1DisDepthVal = intDataArr[0];
+						getDevChannel1DisMaxVal = intDataArr[1];
+						getDevChannel1DisAlarmPercent = intDataArr[2];
+						
+						getDevChannel2DisDepthVal = intDataArr[3];
+						getDevChannel2DisMaxVal = intDataArr[4];
+						getDevChannel2DisAlarmPercent = intDataArr[5];
+						
+						getDevChannel3DisDepthVal = intDataArr[6];
+						getDevChannel3DisMaxVal = intDataArr[7];
+						getDevChannel3DisAlarmPercent = intDataArr[8];
+						
+						getDevChannel4DisDepthVal = intDataArr[9];
+						getDevChannel4DisMaxVal = intDataArr[10];
+						getDevChannel4DisAlarmPercent = intDataArr[11];
+						
+						getOverflowSetMark = 1;											//��־����ɹ�		
+						printf("\r\nOF1: %d, %d, %d; OF2: %d, %d, %d; OF3: %d, %d, %d; OF4: %d, %d, %d\r\n", 
+									getDevChannel1DisDepthVal, getDevChannel1DisMaxVal, getDevChannel1DisAlarmPercent,
+									getDevChannel2DisDepthVal, getDevChannel2DisMaxVal, getDevChannel2DisAlarmPercent,
+									getDevChannel3DisDepthVal, getDevChannel3DisMaxVal, getDevChannel3DisAlarmPercent,
+									getDevChannel4DisDepthVal, getDevChannel4DisMaxVal, getDevChannel4DisAlarmPercent);	
+					}else{}
+				}else{
+					getDeviceTypeMark = 0;
+					printf("\r\n��������������ݸ�ʽ����\r\n");
+					break;
+				}
+				break;
+				
+			case 30:		//����У׼
+				printf("\r\nSET --> ����У׼��\r\n");
+				printf("\r\nlist[1]��%s\r\n", setParamList[1]);
+				
+				temp = StrToInt(setParamList[1]);									//���ַ���ת������������
+				if(temp != 0xFFFFFFFF)
+				{
+					getScaleNum = temp;									
+					getScaleCalibrationMark = 1;										//��־�Ѿ�ȡ�ô�ȷ�ϵ�����
+					printf("\r\n���̱��Ϊ��%d\r\n", getScaleNum);
+				}else{
+					getConfirmPasswordMark = 0;
+					printf("\r\nУ׼���̲������ݸ�ʽ����\r\n");
+					break;
+				}
+				break;
+				
+			case 31:		//��ʱ�����������Ŷ�ά��
+				printf("\r\nSET --> ��ʱ���ţ�\r\n");
+				printf("\r\nlist[1]��%s\r\n", setParamList[1]);
+				
+				temp = StrToInt(setParamList[1]);								//���ַ���ת������������
+				if(temp != 0xFFFFFFFF)
+				{							
+					getBoxOpenMark = 1;										//��־�Ѿ�ȡ�ô�ȷ�ϵ�����
+					printf("\r\n���ű��Ϊ��%d\r\n", getScaleNum);
+				}else{
+					getBoxOpenMark = 0;
+					printf("\r\n��ʱ���Ų������ݸ�ʽ����\r\n");
+					break;
+				}
+				break;
+				
+			case 56:		//����ǿ���޸�
+				printf("\r\nSET --> ����ǿ���޸ģ�\r\n");
+				printf("\r\nlist[1]��%s\r\n", setParamList[1]);
+				
+				temp = StrToInt(setParamList[1]);								//���ַ���ת������������
+				if(temp != 0xFFFFFFFF)
+				{
+					getPassword = temp;										
+					getForceChangeMark = 1;											//��־�Ѿ�ȡ�ô�ȷ�ϵ�����
+					printf("\r\n����Ϊ��%d\r\n", getPassword);
+				}else{
+					getForceChangeMark = 0;
+					printf("\r\nǿ�������������ݸ�ʽ����\r\n");
+					break;
+				}
+				break;
+				
+			case 100:		//�豸�����ָ���������
+				printf("\r\nSET --> �豸�����ָ��������ã�\r\n");
+				getDeviceParamResetMark = 1;
+				break;
+				
+			default:
+				break;
+		}
+	}
+}
+
+/*
+***********************************************************************
+*	�� �� ��: PasswordCheck
+*	����˵��: ����У��
+*	��    �Σ���
+*	�� �� ֵ: 1������ȷ�ϳɹ���0������δȷ��
+***********************************************************************
+*/
+uint8_t PasswordCheck(void)
+{
+	uint8_t res = 0;
+	
+	if(getConfirmPasswordMark == 1)
+	{
+		getConfirmPasswordMark = 0;
+		if(password == getConfirmPassword)
+		{
+			printf("\r\n����У����ȷ��\r\n");
+			res = 1;
+		}else{
+			printf("\r\n����У�����\r\n");
+			res = 0;
+		}
+	}
+	return res;
+}
+
+/*
+***********************************************************************
+*	�� �� ��: PasswordSetTask
+*	����˵��: �����޸���������
+*	��    �Σ���
+*	�� �� ֵ: ��
+***********************************************************************
+*/
+void PasswordSetTask(void)
+{
+	static uint8_t setStep = 0x00;
+	
+	switch(setStep)
+	{
+		case 0x00:
+			if(getPasswordMark == 1)
+			{
+				getPasswordMark = 0;
+				getConfirmPasswordMark = 0;
+				setParamChangeMark = 0;
+				setStep = 0x01;
+			}
+			break;
+			
+		case 0x01:
+			if(getConfirmPasswordMark == 1)
+			{
+				getConfirmPasswordMark = 0;
+				if(password == getConfirmPassword)
+				{
+					printf("\r\n����У����ȷ��\r\n");
+					setPassword = getPassword;
+					printf("\r\n�����޸ĳɹ���\r\n");
+					setParamSaveMark = 1;														//��־�в����������޸ģ���Ҫ���б���
+					setStep = 0x00;
+					break;
+				}else{
+					printf("\r\n����У�����\r\n");
+					break;
+				}
+			}
+			
+			if(setParamChangeMark == 1)
+			{
+				setParamChangeMark = 0;
+				setStep = 0x00;
+				printf("\r\n���������������л�����\r\n");
+				break;
+			}
+			break;
+			
+		default:
+			break;
+	}
+}
+
+/*
+***********************************************************************
+*	�� �� ��: PasswordCastSetTask
+*	����˵��: ����ǿ���޸���������
+*	��    �Σ���
+*	�� �� ֵ: ��
+***********************************************************************
+*/
+void PasswordCastSetTask(void)
+{
+	static uint8_t setStep = 0x00;
+	
+	switch(setStep)
+	{
+		case 0x00:
+			if(getForceChangeMark == 1)
+			{
+				getForceChangeMark = 0;
+				setPassword = getPassword;
+				setParamSaveMark = 1;														//��־�в����������޸ģ���Ҫ���б���
+				printf("\r\n����ǿ���޸ĳɹ���\r\n");
+				setStep = 0x00;
+			}
+			break;
+			
+		default:
+			break;
+	}
+}
+
+/*
+***********************************************************************
+*	�� �� ��: DeviceTypeSetTask
+*	����˵��: �豸������������
+*	��    �Σ���
+*	�� �� ֵ: ��
+***********************************************************************
+*/
+void DeviceTypeSetTask(void)
+{
+	static uint8_t setStep = 0x00;
+	
+	switch(setStep)
+	{
+		case 0x00:
+			if(getDeviceTypeMark == 1)
+			{
+				getDeviceTypeMark = 0;
+				getConfirmPasswordMark = 0;
+				setParamChangeMark = 0;
+				printf("\r\n��ȡ�����ͣ��ȴ�ȷ�����룡\r\n");
+				setStep = 0x01;
+			}
+			break;
+			
+		case 0x01:
+			if(getConfirmPasswordMark == 1)
+			{
+				getConfirmPasswordMark = 0;
+				if(password == getConfirmPassword)
+				{
+					printf("\r\n����У����ȷ��\r\n");
+					setDeviceType = getDeviceType;
+					setDevChannelNumbers = getDevChannelNumbers;
+					setDevChannel1Type = getDevChannel1Type;
+					setDevChannel2Type = getDevChannel2Type;
+					setDevChannel3Type = getDevChannel3Type;
+					setDevChannel4Type = getDevChannel4Type;
+// 					SetDefaultOverflowAlarmParam();									//���豸�����б仯ʱ��Ҫ�����������籨������
+					setParamSaveMark = 1;														//��־�в����������޸ģ���Ҫ���б���
+					setStep = 0x00;
+					break;
+				}else{
+					printf("\r\n����У�����\r\n");
+					break;
+				}
+			}
+			
+			if(setParamChangeMark == 1)
+			{
+				setParamChangeMark = 0;
+				setStep = 0x00;
+				printf("\r\n���������������л�����\r\n");
+				break;
+			}
+			break;
+			
+		default:
+			break;
+	}
+}
+
+/*
+***********************************************************************
+*	�� �� ��: CustomerIdSetTask
+*	����˵��: �豸�ͻ�����������
+*	��    �Σ���
+*	�� �� ֵ: ��
+***********************************************************************
+*/
+void CustomerIdSetTask(void)
+{
+	static uint8_t setStep = 0x00;
+	
+	switch(setStep)
+	{
+		case 0x00:
+			if(getCustomerIDMark == 1)
+			{
+				getCustomerIDMark = 0;
+				getConfirmPasswordMark = 0;
+				setParamChangeMark = 0;
+				setStep = 0x01;
+			}
+			break;
+			
+		case 0x01:
+			if(getConfirmPasswordMark == 1)
+			{
+				getConfirmPasswordMark = 0;
+				if(password == getConfirmPassword)
+				{
+					printf("\r\n����У����ȷ��\r\n");
+					setCustomerID = getCustomerID;
+					printf("\r\n�ͻ����޸ĳɹ���\r\n");
+					setParamSaveMark = 1;														//��־�в����������޸ģ���Ҫ���б���
+					setStep = 0x00;
+					break;
+				}else{
+					printf("\r\n����У�����\r\n");
+					break;
+				}
+			}
+			
+			if(setParamChangeMark == 1)
+			{
+				setParamChangeMark = 0;
+				setStep = 0x00;
+				printf("\r\n���������������л�����\r\n");
+				break;
+			}
+			break;
+			
+		default:
+			break;
+	}
+}
+
+/*
+***********************************************************************
+*	�� �� ��: DisableICCardFunSetTask
+*	����˵��: ����/ͣ�á����õ�IC�����ܿ��š���������
+*	��    �Σ���
+*	�� �� ֵ: ��
+***********************************************************************
+*/
+void DisableICCardFunSetTask(void)
+{
+	static uint8_t setStep = 0x00;
+	
+	switch(setStep)
+	{
+		case 0x00:
+			if(getDisableICCardFunMark == 1)
+			{
+				getDisableICCardFunMark = 0;
+				getConfirmPasswordMark = 0;
+				setParamChangeMark = 0;
+				setStep = 0x01;
+			}
+			break;
+			
+		case 0x01:
+			if(getConfirmPasswordMark == 1)
+			{
+				getConfirmPasswordMark = 0;
+				if(password == getConfirmPassword)
+				{
+					printf("\r\n����У����ȷ��\r\n");
+					setDisableICCardFunStatus = getDisableICCardFunStatus;
+					printf("\r\n�����õ�IC�����ܿ��š������޸ĳɹ���\r\n");
+					if(setDisableICCardFunStatus == 1)
+					{
+						printf("\r\nͣ�ã�\r\n");
+					}else{
+						printf("\r\n���ã�\r\n");
+					}
+					setParamSaveMark = 1;														//��־�в����������޸ģ���Ҫ���б���
+					setStep = 0x00;
+					break;
+				}else{
+					printf("\r\n����У�����\r\n");
+					break;
+				}
+			}
+			
+			if(setParamChangeMark == 1)
+			{
+				setParamChangeMark = 0;
+				setStep = 0x00;
+				printf("\r\n���������������л�����\r\n");
+				break;
+			}
+			break;
+			
+		default:
+			break;
+	}
+}
+
+/*
+***********************************************************************
+*	�� �� ��: DisableICCardFunSetTask
+*	����˵��: ����/ͣ�á����˶�ά�뿪�š���������
+*	��    �Σ���
+*	�� �� ֵ: ��
+***********************************************************************
+*/
+void EnableCleanQRCodeSetTask(void)
+{
+	static uint8_t setStep = 0x00;
+	
+	switch(setStep)
+	{
+		case 0x00:
+			if(getEnableCleanQRCodeMark == 1)
+			{
+				getEnableCleanQRCodeMark = 0;
+				getConfirmPasswordMark = 0;
+				setParamChangeMark = 0;
+				setStep = 0x01;
+			}
+			break;
+			
+		case 0x01:
+			if(getConfirmPasswordMark == 1)
+			{
+				getConfirmPasswordMark = 0;
+				if(password == getConfirmPassword)
+				{
+					printf("\r\n����У����ȷ��\r\n");
+					setEnableCleanQRCodeStatus = getEnableCleanQRCodeStatus;
+					printf("\r\n�����˶�ά�뿪�š������޸ĳɹ���\r\n");
+					if(setEnableCleanQRCodeStatus == 1)
+					{
+						printf("\r\n���ã�\r\n");
+					}else{
+						printf("\r\nͣ�ã�\r\n");
+					}
+					setParamSaveMark = 1;														//��־�в����������޸ģ���Ҫ���б���
+					setStep = 0x00;
+					break;
+				}else{
+					printf("\r\n����У�����\r\n");
+					break;
+				}
+			}
+			
+			if(setParamChangeMark == 1)
+			{
+				setParamChangeMark = 0;
+				setStep = 0x00;
+				printf("\r\n���������������л�����\r\n");
+				break;
+			}
+			break;
+			
+		default:
+			break;
+	}
+}
+
+/*
+***********************************************************************
+*	�� �� ��: OverflowSetTask
+*	����˵��: ���������������
+*	��    �Σ���
+*	�� �� ֵ: ��
+***********************************************************************
+*/
+void OverflowSetTask(void)
+{
+	static uint8_t setStep = 0x00;
+	
+	switch(setStep)
+	{
+		case 0x00:
+			if(getOverflowSetMark == 1)
+			{
+				getOverflowSetMark = 0;
+				getConfirmPasswordMark = 0;
+				setParamChangeMark = 0;
+				printf("\r\n��ȡ�����ͣ��ȴ�ȷ�����룡\r\n");
+				setStep = 0x01;
+			}
+			break;
+			
+		case 0x01:
+			if(getConfirmPasswordMark == 1)
+			{
+				getConfirmPasswordMark = 0;
+				if(password == getConfirmPassword)
+				{
+					printf("\r\n����У����ȷ��\r\n");
+					setDevChannel1DisDepthVal = getDevChannel1DisDepthVal;
+					setDevChannel1DisMaxVal = getDevChannel1DisMaxVal;
+					setDevChannel1DisAlarmPercent = getDevChannel1DisAlarmPercent;
+					
+					setDevChannel2DisDepthVal = getDevChannel2DisDepthVal;
+					setDevChannel2DisMaxVal = getDevChannel2DisMaxVal;
+					setDevChannel2DisAlarmPercent = getDevChannel2DisAlarmPercent;
+					
+					setDevChannel3DisDepthVal = getDevChannel3DisDepthVal;
+					setDevChannel3DisMaxVal = getDevChannel3DisMaxVal;
+					setDevChannel3DisAlarmPercent = getDevChannel3DisAlarmPercent;
+					
+					setDevChannel4DisDepthVal = getDevChannel4DisDepthVal;
+					setDevChannel4DisMaxVal = getDevChannel4DisMaxVal;
+					setDevChannel4DisAlarmPercent = getDevChannel4DisAlarmPercent;
+					
+// 					SetDefaultOverflowAlarmParam();									//���豸�����б仯ʱ��Ҫ�����������籨������
+					setParamSaveMark = 1;														//��־�в����������޸ģ���Ҫ���б���
+					setStep = 0x00;
+					break;
+				}else{
+					printf("\r\n����У�����\r\n");
+					break;
+				}
+			}
+			
+			if(setParamChangeMark == 1)
+			{
+				setParamChangeMark = 0;
+				setStep = 0x00;
+				printf("\r\n���������������л�����\r\n");
+				break;
+			}
+			break;
+			
+		default:
+			break;
+	}
+}
+
+/*
+***********************************************************************
+*	�� �� ��: ScaleCalibrationTask
+*	����˵��: ����У׼����
+*	��    �Σ���
+*	�� �� ֵ: ��
+***********************************************************************
+*/
+void ScaleCalibrationTask(void)
+{
+	static uint8_t setStep = 0x00;
+	static timer waitingTimer;
+	static timer waitingTimer1S;
+	static timer waitingExitTimer;
+	
+	static uint8_t timer_ok = 0;
+	
+	if(timer_ok == 0)
+	{
+		timer_ok = 1;
+		timer_set(&waitingTimer, CLOCK_SECOND*3);
+		timer_set(&waitingTimer1S, CLOCK_SECOND*1);
+		timer_set(&waitingExitTimer, CLOCK_SECOND*20);
+	}
+	
+	switch(setStep)
+	{
+		case 0x00:		//��ʼ״̬
+			if(getScaleCalibrationMark == 1)
+			{
+				getScaleCalibrationMark = 0;
+				getConfirmPasswordMark = 0;				//ȷ�������־����
+				setParamChangeMark = 0;						//ָ���л���־����
+				setStep = 0x01;
+			}
+			break;
+			
+		case 0x01:		//У������
+			if(getConfirmPasswordMark == 1)
+			{
+				getConfirmPasswordMark = 0;
+				if(password == getConfirmPassword)
+				{
+					printf("\r\n����У����ȷ��\r\n");
+					
+					printf("\r\n��������У׼��\r\n");
+					setStep = 0x02;
+					break;
+				}else{
+					printf("\r\n����У�����\r\n");
+					break;
+				}
+			}
+			
+			if(setParamChangeMark == 1)
+			{
+				setParamChangeMark = 0;
+				setStep = 0x00;
+				printf("\r\n���������������л�����\r\n");
+				break;
+			}
+			break;
+			
+		case 0x02:		//������������У׼
+			Screen_ScaleCalibraEnter(getScaleNum);		//��ʾ����У׼
+			
+			if(getScaleNum == 0)
+			{
+				if(deviceWorkStatus == 1)
+				{
+					Screen_Default();
+				}else{
+					Screen_DeviceDisable();
+				}
+				
+				setStep = 0x00;
+				break;
+			}
+			
+			scaleNum = getScaleNum;
+			getCalibraZeroMark1 = 0;
+			getCalibraZeroMark2 = 0;
+			
+			beep_contSlowBeepMark = 1;
+			M_S_CommandSend(0xA1);
+			timer_restart(&waitingExitTimer);
+			setStep = 0x03;
+			break;
+			
+		case 0x3:		//�ȴ�����ģ���Ӧȡ�����			
+			if(timer_expired(&waitingExitTimer))
+			{
+				printf("\r\nȡ��У׼��㳬ʱ�˳���\r\n");
+				
+				beep_contSlowBeepMark = 0;
+				setStep = 0x10;
+			}
+			
+			switch(getScaleNum)
+			{
+				case 1:		//����1
+					if(getCalibraZeroMark1 == 1)
+					{
+						printf("\r\n�յ���1У׼��㣡\r\n");
+						Screen_ScaleCalibraStart(getScaleNum);
+						getCalibraParamOkMark1 = 0;
+						
+						beep_contSlowBeepMark = 0;
+						beep_contFastBeepMark = 1;
+						
+						timer_restart(&waitingExitTimer);
+						setStep = 0x04;
+						break;
+					}
+					break;
+					
+				case 2:		//����2
+					if(getCalibraZeroMark2 == 1)
+					{
+						printf("\r\n�յ���2У׼��㣡\r\n");
+						Screen_ScaleCalibraStart(getScaleNum);
+						getCalibraParamOkMark2 = 0;
+						
+						beep_contSlowBeepMark = 0;
+						beep_contFastBeepMark = 1;
+						
+						timer_restart(&waitingExitTimer);
+						setStep = 0x04;
+						break;
+					}
+					break;
+					
+				default:
+					setStep = 0x00;
+					break;
+			}
+			break;
+			
+		case 0x04:		//�ȴ�У׼���
+			if(timer_expired(&waitingExitTimer))
+			{
+				printf("\r\nȡ��У׼��㳬ʱ�˳���\r\n");
+				
+				beep_contFastBeepMark = 0;
+				setStep = 0x10;
+				break;
+			}
+			
+			switch(getScaleNum)
+			{
+				case 1:		//����1
+					if(getCalibraParamOkMark1 == 1)
+					{
+						printf("\r\n�յ���1У׼��ɣ�\r\n");
+						Screen_ScaleCalibraFinish(getScaleNum);
+						
+						beep_contFastBeepMark = 0;
+						beep_longBeepMark = 1;
+						timer_restart(&waitingTimer);
+						setStep = 0x05;
+						break;
+					}
+					break;
+					
+				case 2:		//����2
+					if(getCalibraParamOkMark2 == 1)
+					{
+						printf("\r\n�յ���2У׼��ɣ�\r\n");
+						Screen_ScaleCalibraFinish(getScaleNum);
+						
+						beep_contFastBeepMark = 0;
+						beep_longBeepMark = 1;
+						timer_restart(&waitingTimer);
+						setStep = 0x05;
+						break;
+					}
+					break;
+					
+				default:
+					setStep = 0x00;
+					break;
+			}
+			break;
+			
+		case 0x05:		//�˳�
+			if(timer_expired(&waitingTimer))
+			{
+				beep_contSlowBeepMark = 0;
+				beep_contFastBeepMark = 0;
+				
+				if(deviceWorkStatus == 1)
+				{
+					Screen_Default();
+				}else{
+					Screen_DeviceDisable();
+				}
+				setStep = 0x00;
+			}
+			break;
+			
+		case 0x10:		//У׼ʧ����������ģ���Դ
+//			ScalePowerOFF(1);
+//			ScalePowerOFF(2);
+			M_S_CommandSend(0xA5);
+			timer_restart(&waitingTimer1S);
+			setStep = 0x11;
+			break;
+			
+		case 0x11:		//У׼ʧ����������ģ���Դ
+			if(timer_expired(&waitingTimer1S))
+			{
+//				ScalePowerON(1);
+//				ScalePowerON(2);
+				setStep = 0x05;
+			}
+			break;
+			
+		default:
+			break;
+	}
+}
+
+/*
+***********************************************************************
+*	�� �� ��: BoxOpenSetTask
+*	����˵��: ��ʱ�����������Ų�������
+*	��    �Σ���
+*	�� �� ֵ: ��
+***********************************************************************
+*/
+
+void BoxOpenSetTask(void)
+{
+	static uint8_t setStep = 0x00;
+	
+	switch(setStep)
+	{
+		case 0x00:
+			if(getBoxOpenMark == 1)
+			{
+				getBoxOpenMark = 0;
+				boxOpenMark = 1;
+				printf("\r\n׼���������ţ�\r\n");
+				setStep = 0x00;
+			}
+			break;
+			
+		default:
+			break;
+	}
+}
+
+// void BoxOpenSetTask(void)
+// {
+// 	static uint8_t setStep = 0x00;
+// 	
+// 	switch(setStep)
+// 	{
+// 		case 0x00:
+// 			if(getBoxOpenMark == 1)
+// 			{
+// 				getBoxOpenMark = 0;
+// 				getConfirmPasswordMark = 0;
+// 				setParamChangeMark = 0;
+// 				setStep = 0x01;
+// 			}
+// 			break;
+// 			
+// 		case 0x01:
+// 			if(getConfirmPasswordMark == 1)
+// 			{
+// 				getConfirmPasswordMark = 0;
+// 				if(password == getConfirmPassword)
+// 				{
+// 					printf("\r\n����У����ȷ��\r\n");
+// 					boxOpenMark = 1;
+// 					printf("\r\n׼���������ţ�\r\n");
+// 					setStep = 0x00;
+// 					break;
+// 				}else{
+// 					printf("\r\n����У�����\r\n");
+// 					break;
+// 				}
+// 			}
+// 			
+// 			if(setParamChangeMark == 1)
+// 			{
+// 				setParamChangeMark = 0;
+// 				setStep = 0x00;
+// 				printf("\r\n���������������л�����\r\n");
+// 				break;
+// 			}
+// 			break;
+// 			
+// 		default:
+// 			break;
+// 	}
+// }
+
+/*
+***********************************************************************
+*	�� �� ��: DeviceParamResetTask
+*	����˵��: �豸�����ָ���������
+*	��    �Σ���
+*	�� �� ֵ: ��
+***********************************************************************
+*/
+void DeviceParamResetTask(void)
+{
+	static uint8_t setStep = 0x00;
+	
+	switch(setStep)
+	{
+		case 0x00:
+			if(getDeviceParamResetMark == 1)
+			{
+				getDeviceParamResetMark = 0;
+				getConfirmPasswordMark = 0;
+				setParamChangeMark = 0;
+				setStep = 0x01;
+			}
+			break;
+			
+		case 0x01:
+			if(PasswordCheck() == 1)
+			{
+				printf("\r\n��ʼ�ָ��豸������\r\n");
+				ResetDeviceConfig();
+				beep_shortBeepMark = 1;
+//				DeviceConfigParamInit();					//�豸���ò�����ʼ��
+				
+				
+				getDeviceParamResetMark = 0;
+				setStep = 0x10;
+				break;
+			}
+			
+			if(setParamChangeMark == 1)
+			{
+				setParamChangeMark = 0;
+				
+				getDeviceParamResetMark = 0;
+				setStep = 0x00;
+				printf("\r\n���������������л�����\r\n");
+				break;
+			}
+			break;
+			
+		case 0x10:
+			while(1);													//�����ָ���ɺ�����ϵͳ
+			break;
+			
+		default:
+			break;
+	}
+}
+
+/*
+***********************************************************************
+*	�� �� ��: ParamSaveTask
+*	����˵��: �豸�������������в����޸�ȷ�ϣ�����Ҫ���б��棩
+*	��    �Σ���
+*	�� �� ֵ: ��
+***********************************************************************
+*/
+void ParamSaveTask(void)
+{
+	static uint8_t setStep = 0x00;
+	
+	static timer waitingTimer;
+	
+	static uint8_t timer_ok = 0;
+	
+	if(timer_ok == 0)
+	{
+		timer_ok = 1;
+		timer_set(&waitingTimer, CLOCK_SECOND*2);			//����1����ʱ�������ڵ��������ʱ�����
+	}
+	
+	switch(setStep)
+	{
+		case 0x00:
+			if(setParamSaveMark == 1)
+			{
+				setParamSaveMark = 0;
+					
+				SaveDeviceConfig();
+				DeviceParamInit();										//�����б䶯�������³�ʼ���豸����
+				CalcOverflowStartPointParam();
+				
+				DeviceInfoShow();
+				setStep = 0x01;
+				timer_restart(&waitingTimer);
+			}
+			break;
+			
+		case 0x01:
+			if(timer_expired(&waitingTimer))
+			{
+				if(deviceWorkStatus == 1)
+				{
+					Screen_Default();
+				}else{
+					Screen_DeviceDisable();
+				}
+				setStep = 0x00;
+			}
+			break;
+			
+		case 0x02:
+			break;
+			
+		default:
+			break;
+	}
+}
+
+/*
+***********************************************************************
+*	�� �� ��: ParamSetTask
+*	����˵��: ������������
+*	��    �Σ���
+*	�� �� ֵ: ��
+***********************************************************************
+*/
+void ParamSetTask(void)
+{
+	if(devSetQrCodeState == 1)
+	{
+		printf("\r\n����������ò���---->\r\n");
+		devSetQrCodeState = 0;
+		SetParamDecode(codeBuf);									//���ö�ά���������
+	}
+	
+	PasswordSetTask();												//�����޸�����
+	PasswordCastSetTask();										//ǿ���޸���������
+	DeviceTypeSetTask();											//�豸������������
+	CustomerIdSetTask();											//�ͻ�����������
+	
+	DisableICCardFunSetTask();								//����/ͣ�á����õ�IC�����ܿ��š�������������
+	EnableCleanQRCodeSetTask();								//����/ͣ�á����˶�ά�뿪�š�������������
+	
+	OverflowSetTask();												//���������������
+	
+	ScaleCalibrationTask();										//����У׼��������
+	BoxOpenSetTask();													//��ʱ�����������Ų�������
+	
+	DeviceParamResetTask();										//�豸�����ָ�������������
+	
+	ParamSaveTask();													//�豸������������
+}
+
+
+/******************** (C) COPYRIGHT 2017 CXHY *****END OF FILE*******************/
diff --git a/STM32_4路称重_Git提交精简工程/src/HARDWARE/DEVICE/deviceSet.h b/STM32_4路称重_Git提交精简工程/src/HARDWARE/DEVICE/deviceSet.h
new file mode 100755
index 0000000..083e05d
--- /dev/null
+++ b/STM32_4路称重_Git提交精简工程/src/HARDWARE/DEVICE/deviceSet.h
@@ -0,0 +1,36 @@
+/*************************** (C) COPYRIGHT 2017 CXHY ****************************
+ * �ļ���  ��deviceSet.h
+ * ��  ��  ���豸���ó���
+ * ��  ��  ��V1.0
+ * ��  ��  ��XuZhongPing
+ * ��  ��  ��2019/03/06 
+*********************************************************************************/
+#ifndef __DEVICE_SET_H
+#define __DEVICE_SET_H	 
+
+#include "stm32f10x.h"
+#include "string.h" 
+#include "stdlib.h" 
+
+#include "led.h"
+#include "key.h"
+#include "opto_sw_key.h"
+#include "sw_key.h"
+#include "usart5.h"
+
+#include "sound.h"
+#include "spi.h"
+#include "flash.h" 
+
+void DeviceInfoShow(void);
+void ShowRecyclingBinsType(uint8_t type);
+void DeviceTypeSet(uint8_t setkeyVal);
+void DeviceSetParamInit(void);
+void DeviceParamInit(void);
+void SetDefaultOverflowAlarmParam(void);
+
+void ParamSetTask(void);
+
+#endif
+
+/******************** (C) COPYRIGHT 2017 CXHY *****END OF FILE*******************/
diff --git a/STM32_4路称重_Git提交精简工程/src/HARDWARE/DEVICE/distancer.c b/STM32_4路称重_Git提交精简工程/src/HARDWARE/DEVICE/distancer.c
new file mode 100755
index 0000000..ce1cc4e
--- /dev/null
+++ b/STM32_4路称重_Git提交精简工程/src/HARDWARE/DEVICE/distancer.c
@@ -0,0 +1,387 @@
+/*************************** (C) COPYRIGHT 2017 CXHY ****************************
+ * �ļ���  ��distancer.c
+ * ��  ��  ��������     
+ * ��  ��  ��V1.0
+ * ��  ��  ��XuZhongPing
+ * ��  ��  ��2017/08/04 
+*********************************************************************************/
+#include "distancer.h"
+#include "timer.h"
+#include "delay.h"
+#include "my_math.h"
+#include "data_typedef.h"
+#include "key.h"
+#include "pc_protocol.h"
+
+uint16_t distanceCnt1 = 0;
+uint16_t distanceCnt2 = 0;
+
+uint8_t distanceBuf1[DISTANCE_CNT_MAX] = {0};						//�������ݻ���
+uint8_t distanceBuf2[DISTANCE_CNT_MAX] = {0};
+
+uint8_t outputDistance1 = 255;													//��β�����������Ĳ������
+uint8_t outputDistance2 = 255;
+uint8_t outputDistance3 = 255;
+uint8_t outputDistance4 = 255;
+
+uint8_t restartGetDisDataMark = 0;											//���¿�ʼ������־
+
+
+
+void showData(uint8_t num[], uint8_t n)
+{
+    uint8_t i;
+		printf("\r\n");
+    for(i=0; i<n; i++)
+		{
+      printf("%03d ",num[i]);
+		}
+		printf("\r\n");
+}
+
+/*
+***********************************************************************
+*	�� �� ��: DataSort
+*	����˵��: �����������������򣨴Ӵ�С���У�
+*	��    �Σ�
+*       		x[]:��Ҫ����������
+*						n:����ĳ���
+*	�� �� ֵ: ��
+***********************************************************************
+*/
+void DataSort(uint8_t x[], uint8_t n)
+{
+	uint8_t i,j,k,t;  
+	
+	for (i=0; i<n-1; i++)
+	{
+		k = i;
+		for(j=i+1; j<n; j++)
+		{
+			if(x[j] > x[k]) k = j;
+		}
+		if(k != i)
+		{
+			t = x[i];
+			x[i] = x[k];
+			x[k] = t;
+		}
+	}
+}
+
+/*
+***********************************************************************
+*	�� �� ��: uint average(uint *p,uchar n)
+*	����˵��: ȥ��������Сֵ����ƽ����
+*	��    �Σ�
+*       		x[]:��Ҫ����������
+*						n:����ĳ���
+*						discardVal:����ֵ����ͷ������������������
+*	�� �� ֵ: ������Ľ��
+***********************************************************************
+*/
+uint8_t Average(uint8_t x[], uint8_t n, uint8_t discardVal)
+{
+	uint8_t i = 0;
+	uint8_t aver = 0;
+	uint32_t sum = 0;
+	
+	for(i = discardVal; i < n-discardVal; i++)
+	{
+		sum = sum+x[i];
+	}
+	aver = sum/(n - discardVal*2);  
+	return aver;
+}
+
+/*
+***********************************************************************
+*	�� �� ��: DistanceDataUpdata
+*	����˵��: ��β������������ݴ�������
+*	��    �Σ���
+*	�� �� ֵ: ��
+***********************************************************************
+*/
+void DistanceDataUpdata(void)
+{
+	static uint8_t currentStatus = 0x00;
+	static uint8_t nextStatus = 0x00;
+
+	static timer waitingTimer;
+	
+	static uint8_t timer_ok = 0;
+	
+	if(timer_ok == 0)
+	{
+		timer_ok = 1;
+		
+		timer_set(&waitingTimer, CLOCK_SECOND*15);
+	}
+	
+	if(restartGetDisDataMark == 1)
+	{
+		restartGetDisDataMark = 0;
+		
+		distanceCnt1 = 0;
+		distanceCnt2 = 0;
+		
+		printf("\r\n���²ɼ��������ݣ�\r\n");
+		timer_restart(&waitingTimer);
+	}
+	
+	if(putInProgress == 0)
+	{
+		if(timer_expired(&waitingTimer))
+		{
+			timer_restart(&waitingTimer);
+			
+			printf("\r\n������ݴ�����\r\n");
+			
+			printf("\r\ndistanceCnt1 = %d\r\n", distanceCnt1);
+			showData(distanceBuf1, distanceCnt1);
+			DataSort(distanceBuf1, distanceCnt1);
+			showData(distanceBuf1, distanceCnt1);
+			outputDistance1 = Average(distanceBuf1, distanceCnt1, 10);
+			if((outputDistance1 > distanceParamAtStart) && (outputDistance1 != 255))
+			{
+				outputDistance1 = devChannel1DisMaxVal;
+			}
+			printf("\r\noutputDistance1 = %d\r\n", outputDistance1);
+			
+			printf("\r\ndistanceCnt2 = %d\r\n", distanceCnt2);
+			showData(distanceBuf2, distanceCnt2);
+			DataSort(distanceBuf2, distanceCnt2);
+			showData(distanceBuf2, distanceCnt2);
+			outputDistance2 = Average(distanceBuf2, distanceCnt2, 10);
+			if((outputDistance2 > distanceParamAtStart) && (outputDistance2 != 255))
+			{
+				outputDistance2 = devChannel2DisMaxVal;
+			}
+			printf("\r\noutputDistance2 = %d\r\n", outputDistance2);
+			
+			//��������������¿�ʼ
+			distanceCnt1 = 0;
+			distanceCnt2 = 0;
+			
+			PC_ProCommandSend(0x62);
+		}
+	}
+}
+
+/*
+***********************************************************************
+*	�� �� ��: OverflowDetectionTask
+*	����˵��: Ͱװ���������
+*	��    �Σ���
+*	�� �� ֵ: ��
+***********************************************************************
+*/
+void OverflowDetectionTask(void)
+{
+	uint8_t a1 = 0, a2 = 0, a3 = 0, a4 = 0;
+	uint8_t A1 = 0, A2 = 0, A3 = 0, A4 = 0;
+	
+	static uint8_t fullMarkPre1 = 0;
+	static uint8_t fullMarkPre2 = 0;
+	static uint8_t fullMarkPre3 = 0;
+	static uint8_t fullMarkPre4 = 0;
+	
+	static timer timer_60s;
+	static uint8_t timer_ok = 0;
+	
+	if(timer_ok == 0)
+	{
+		timer_ok = 1;
+		timer_set(&timer_60s, CLOCK_SECOND*10);
+	}
+
+	//�����趨�Ĳ����ж��Ƿ�װ��
+	//��1ͨ�������ж�
+	if((devChannel1DisDepthVal > 0) && (outputDistance1 <= devChannel1DisMaxVal))
+	{
+		a1 = devChannel1DisMaxVal - outputDistance1;
+		A1 = ((uint16_t)a1*100)/devChannel1DisDepthVal;
+		
+// 		printf("\r\nd1 = %d, a1 = %d, A1 = %d\r\n", getDistance1, a1, A1);
+		
+		if(A1 >= devChannel1DisAlarmPercent)
+		{
+			fullMark1 = 1;
+		}else{
+			fullMark1 = 0;
+		}
+	}else{		//��ǰ����õľ�����趨�İ�װ�߶�˵��Ϊ����
+		fullMark1 = 0;
+	}
+	
+	//��2ͨ�������ж�
+	if((devChannel2DisDepthVal > 0) && (outputDistance2 <= devChannel2DisMaxVal))
+	{
+		a2 = devChannel2DisMaxVal - outputDistance2;
+		A2 = ((uint16_t)a2*100)/devChannel2DisDepthVal;
+		
+// 		printf("\r\nd2 = %d, a2 = %d, A2 = %d\r\n", getDistance2, a2, A2);
+		
+		if(A2 >= devChannel2DisAlarmPercent)
+		{
+			fullMark2 = 1;
+		}else{
+			fullMark2 = 0;
+		}
+	}else{		//��ǰ����õľ�����趨�İ�װ�߶�˵��Ϊ����
+		fullMark2 = 0;
+	}
+
+	//��3ͨ�������ж�
+	if((devChannel3DisDepthVal > 0) && (outputDistance3 <= devChannel3DisMaxVal))
+	{
+		a3 = devChannel3DisMaxVal - outputDistance3;
+		A3 = ((uint16_t)a3*100)/devChannel3DisDepthVal;
+		fullMark3 = (A3 >= devChannel3DisAlarmPercent) ? 1 : 0;
+	}else{
+		fullMark3 = 0;
+	}
+
+	//��4ͨ�������ж�
+	if((devChannel4DisDepthVal > 0) && (outputDistance4 <= devChannel4DisMaxVal))
+	{
+		a4 = devChannel4DisMaxVal - outputDistance4;
+		A4 = ((uint16_t)a4*100)/devChannel4DisDepthVal;
+		fullMark4 = (A4 >= devChannel4DisAlarmPercent) ? 1 : 0;
+	}else{
+		fullMark4 = 0;
+	}
+	
+	//�������缰�����������ָʾ��
+	if((netStatus == 2) || (devRunnigStatus == 2))
+	{
+		//�����й���ʱ�ĵƹ���ɫ
+		SetKeyLedOFF(1);
+		SetKeyLedON(2);
+		SetKeyLedOFF(3);
+		SetKeyLedON(4);
+	}else{
+#ifdef FOUR_DROP_PORTS
+		//��Ͷ�ſ����ÿ��Ͷ�ſ�ʹ��һ������ָʾ�ơ�
+		if(fullMark1) SetKeyLedON(1); else SetKeyLedOFF(1);
+		if(fullMark2) SetKeyLedON(2); else SetKeyLedOFF(2);
+		if(fullMark3) SetKeyLedON(3); else SetKeyLedOFF(3);
+		if(fullMark4) SetKeyLedON(4); else SetKeyLedOFF(4);
+#else
+		//ͨ��1
+		if(fullMark1 == 1)
+		{
+			SetKeyLedOFF(1);
+			SetKeyLedON(2);	
+		}else{
+			SetKeyLedON(1);
+			SetKeyLedOFF(2);
+		}
+		
+		//ͨ��2
+		if(fullMark2 == 1)
+		{
+			SetKeyLedOFF(3);
+			SetKeyLedON(4);
+		}else{
+			SetKeyLedON(3);
+			SetKeyLedOFF(4);
+		}
+#endif
+	}
+	
+	
+	//��ӡ������Ϣ	
+	if((fullMarkPre1 != fullMark1) || (fullMarkPre2 != fullMark2) ||
+		 (fullMarkPre3 != fullMark3) || (fullMarkPre4 != fullMark4))
+	{
+		if(fullMark1 == 1)
+		{
+			printf("\r\nCH1װ��\r\n");
+		}else{
+			printf("\r\nCH1�����\r\n");
+		}
+		fullMarkPre1 = fullMark1;
+		printf("\r\nd1 = %d, a1 = %d, A1 = %d%%\r\n", outputDistance1, a1, A1);
+		
+		if(fullMark2 == 1)
+		{
+			printf("\r\nCH2װ��\r\n");
+		}else{
+			printf("\r\nCH2�����\r\n");
+		}
+		fullMarkPre2 = fullMark2;
+		
+		printf("\r\nd2 = %d, a2 = %d, A2 = %d%%\r\n", outputDistance2, a2, A2);
+
+		fullMarkPre3 = fullMark3;
+		fullMarkPre4 = fullMark4;
+		printf("\r\nd3 = %d, a3 = %d, A3 = %d%%\r\n", outputDistance3, a3, A3);
+		printf("\r\nd4 = %d, a4 = %d, A4 = %d%%\r\n", outputDistance4, a4, A4);
+		
+		PC_ProCommandSend(0x62);
+	}
+
+// 	//��ӡ������Ϣ	
+// 	if(fullMarkPre1 != fullMark1)
+// 	{
+// 		if(fullMark1 == 1)
+// 		{
+// 			printf("\r\nCH1װ��\r\n");
+// 		}else{
+// 			printf("\r\nCH1�����\r\n");
+// 		}
+// 		fullMarkPre1 = fullMark1;
+// 		printf("\r\nd1 = %d, a1 = %d, A1 = %d%%\r\n", getDistance1, a1, A1);
+// 	}
+// 	
+// 	if(fullMarkPre2 != fullMark2)
+// 	{
+// 		if(fullMark2 == 1)
+// 		{
+// 			printf("\r\nCH2װ��\r\n");
+// 		}else{
+// 			printf("\r\nCH2�����\r\n");
+// 		}
+// 		fullMarkPre2 = fullMark2;
+// 		
+// 		printf("\r\nd2 = %d, a2 = %d, A2 = %d%%\r\n", getDistance2, a2, A2);
+// 	}
+// 	
+// 	if(fullMarkPre3 != fullMark3)
+// 	{
+// 		if(fullMark3 == 1)
+// 		{
+// 			printf("\r\nCH3װ��\r\n");
+// 		}else{
+// 			printf("\r\nCH3�����\r\n");
+// 		}
+// 		fullMarkPre3 = fullMark3;
+// 		printf("\r\nd3 = %d, a3 = %d, A3 = %d%%\r\n", getDistance3, a3, A3);
+// 	}
+// 	
+// 	if(fullMarkPre4 != fullMark4)
+// 	{
+// 		if(fullMark4 == 1)
+// 		{
+// 			printf("\r\nCH4װ��\r\n");
+// 		}else{
+// 			printf("\r\nCH4�����\r\n");
+// 		}
+// 		fullMarkPre4 = fullMark4;
+// 		printf("\r\nd4 = %d, a4 = %d, A4 = %d%%\r\n", getDistance4, a4, A4);
+// 	}
+	
+	//װ����1���Ӵ�ӡһ��װ����ʾ
+	if(timer_expired(&timer_60s))
+	{
+		timer_restart(&timer_60s);
+		
+		printf("\r\nͨ��1��d1 = %d, a1 = %d, A1 = %d%%\r\n", outputDistance1, a1, A1);
+		printf("\r\nͨ��2��d2 = %d, a2 = %d, A2 = %d%%\r\n", outputDistance2, a2, A2);
+		printf("\r\nͨ��3��d3 = %d, a3 = %d, A3 = %d%%\r\n", outputDistance3, a3, A3);
+		printf("\r\nͨ��4��d4 = %d, a4 = %d, A4 = %d%%\r\n", outputDistance4, a4, A4);
+	}
+}
+
+/******************** (C) COPYRIGHT 2017 CXHY *****END OF FILE*******************/
diff --git a/STM32_4路称重_Git提交精简工程/src/HARDWARE/DEVICE/distancer.h b/STM32_4路称重_Git提交精简工程/src/HARDWARE/DEVICE/distancer.h
new file mode 100755
index 0000000..05e6323
--- /dev/null
+++ b/STM32_4路称重_Git提交精简工程/src/HARDWARE/DEVICE/distancer.h
@@ -0,0 +1,47 @@
+/*************************** (C) COPYRIGHT 2017 CXHY ****************************
+ * �ļ���  ��distancer.h
+ * ��  ��  ��������    
+ * ��  ��  ��V1.0
+ * ��  ��  ��XuZhongPing
+ * ��  ��  ��2017/08/04 
+*********************************************************************************/
+#ifndef __DISTANCER_H
+#define	__DISTANCER_H
+#include "stm32f10x.h"
+#include "IR_Distancer.h"
+#include "UltrasonicWave.h"
+
+
+// �豸����
+typedef enum
+{   
+	ULTRASONIC_DISTANCER = 1,						//���������
+	IR_DISTANCER 												//������
+}DistanceSensorDefine;
+
+extern uint8_t distancerTpye;					//��ഫ����������
+
+#define DISTANCE_CNT_MAX		120
+
+extern uint16_t distanceCnt1;
+extern uint16_t distanceCnt2;
+
+extern uint8_t distanceBuf1[DISTANCE_CNT_MAX];
+extern uint8_t distanceBuf2[DISTANCE_CNT_MAX];
+
+extern uint8_t restartGetDisDataMark;
+
+extern uint8_t outputDistance1;
+extern uint8_t outputDistance2;
+extern uint8_t outputDistance3;
+extern uint8_t outputDistance4;
+
+
+void GetDistanceTask(void);
+void OverflowDetectionTask(void);
+
+void DistanceDataUpdata(void);
+
+#endif
+
+/******************** (C) COPYRIGHT 2017 CXHY *****END OF FILE*******************/
diff --git a/STM32_4路称重_Git提交精简工程/src/HARDWARE/DEVICE/m_s_comm.c b/STM32_4路称重_Git提交精简工程/src/HARDWARE/DEVICE/m_s_comm.c
new file mode 100755
index 0000000..a796bf7
--- /dev/null
+++ b/STM32_4路称重_Git提交精简工程/src/HARDWARE/DEVICE/m_s_comm.c
@@ -0,0 +1,492 @@
+/*************************** (C) COPYRIGHT 2020 Ping ****************************
+ * �ļ���  ��m_s_comm.c
+ * ��  ��  ������MCUͨѶ��������
+ * ��  ��  ��V1.0
+ * ��  ��  ��XuZhongPing
+ * ��  ��  ��2020/03/31
+*********************************************************************************/
+#include "m_s_comm.h"
+#include "device.h"
+#include "data_typedef.h"
+//#include "distancer.h"
+
+uint8_t M_S_RX_BUF[M_S_RECV_LEN];     		//���ջ���
+uint8_t M_S_TX_BUF[M_S_SEND_LEN];					//���ͻ���
+
+static void M_S_DataDecode(uint8_t *pRxBuf, uint8_t *pTxBuf);
+
+static uint8_t CorrectOverflowDistance(uint8_t rawDistance, uint16_t channelWeight,
+																			uint8_t maxVal, uint8_t depthVal)
+{
+	uint16_t correctedDistance;
+	uint16_t measureStart;
+
+	if(rawDistance == 255)
+	{
+		return 255;
+	}
+
+	correctedDistance = (uint16_t)rawDistance + 15;
+	measureStart = maxVal - (((uint16_t)depthVal * PerCentSetVal) / 100);
+
+	if(correctedDistance > measureStart)
+	{
+		correctedDistance = maxVal;
+	}
+
+	if((channelWeight < 1700) && (correctedDistance < 75))
+	{
+		correctedDistance = maxVal;
+	}
+
+	return (uint8_t)correctedDistance;
+}
+
+/*
+***********************************************************************
+*	�� �� ��: M_S_DataPackingAndSend
+*	����˵��: ���ӻ�ͨѶ���ݴ��������
+*	��    ��:	*pdata -> ��Ҫ��������ݵ�ַ��dataLen -> ���ݳ���
+*	�� �� ֵ: ��
+***********************************************************************
+*/
+void M_S_DataPackingAndSend(uint8_t *pdata, uint16_t dataLen)
+{
+	uint8_t i;
+	uint8_t CS = 0x68;
+	uint8_t TX_Size = 0;
+	
+	uint8_t sendDataBuf[128];
+	uint8_t dataAddrIndex = 0;
+	uint8_t sendDataLen = 0;
+	
+	sendDataBuf[dataAddrIndex++] = 0xfe; 			//����ǰ���ֽ�
+	sendDataBuf[dataAddrIndex++] = 0xfe; 			
+	sendDataBuf[dataAddrIndex++] = 0xfe; 		
+	sendDataBuf[dataAddrIndex++] = 0x68; 			//����֡ͷ
+	
+	sendDataBuf[dataAddrIndex++] = *pdata; 		//���͵�ַ
+	CS += *pdata;
+	sendDataBuf[dataAddrIndex++] = 0x68; 			//����֡ͷ
+	CS += 0x68;
+	sendDataBuf[dataAddrIndex++] = *(pdata+1); 	//����֡����
+	CS += *(pdata+1);
+	TX_Size = *(pdata+2);											//ȡ��ͨѶ���ݳ���
+	sendDataBuf[dataAddrIndex++] = TX_Size; 	//�������ݳ���
+	CS += *(pdata+2);
+	for(i=0; i<TX_Size; i++) 									//���ط�������
+	{
+		sendDataBuf[dataAddrIndex++] = *(pdata+i+3);
+		CS += (*(pdata+i+3));
+	}
+	sendDataBuf[dataAddrIndex++] = CS; 				//����У���ֽ�
+	sendDataBuf[dataAddrIndex++] = 0x16; 			//����֡β
+	
+	sendDataLen = dataAddrIndex;
+	
+// 	showHex(sendDataBuf, sendDataLen);
+
+	USART2_SendFrameData(sendDataBuf, sendDataLen);
+}
+
+/*
+***********************************************************************
+*	�� �� ��: M_S_CommandSend
+*	����˵��: �ӻ���������������ͨѶ����
+*	��    ��:	comNum -> ָ���
+*	�� �� ֵ: ��
+***********************************************************************
+*/
+void M_S_CommandSend(uint8_t comNum)
+{
+	uint8_t dataLen = 0;												//������Э���ܳ���
+	uint8_t dataIndex = 0;											//���͵������±�����
+	
+	M_S_TX_BUF[0] = 0x00; 											//����ͨѶ��ַ
+	M_S_TX_BUF[1] = comNum;											//����������
+	
+	dataIndex += 3;															//�ӵ�ַ��������Ⱥ�ʼ����
+	
+	printf("\r\nM->S --> 0x%02X\r\n", comNum);
+	
+	switch(comNum)
+	{
+		case 0x01:
+
+			break;
+			
+		case 0xA1:		//��������У׼
+			M_S_TX_BUF[dataIndex++] = scaleNum;
+			break;
+			
+		case 0xA5:		//���ͳ���У׼ʧ��
+			break;
+		
+		default:
+			break;
+	}
+	
+	//����ͨ�����ݳ���
+	M_S_TX_BUF[2] = dataIndex - 3;									//����ͨѶ���ݳ����ֽ�
+	dataLen = dataIndex;
+	
+//	printf("\r\nlen = %d\r\n", dataLen);
+	M_S_DataPackingAndSend(M_S_TX_BUF, dataLen); 		//��ָ������������Ȼ����
+}
+
+/*
+***********************************************************************
+*	�� �� ��: OverflowDataCorrection1
+*	����˵��: ������������
+*	��    ��:	��
+*	�� �� ֵ: ��
+***********************************************************************
+*/
+static void OverflowDataCorrection1(void)
+{
+	static uint8_t currentStatus = 0x00;
+	static uint8_t nextStatus = 0x00;
+	
+	static uint16_t preweight = 0;
+	uint16_t tempDate = 0;
+	
+	currentStatus = nextStatus;
+	switch(currentStatus)
+	{
+		case 0x00:
+			if((weight1 > 2000) && (getDistance1) < 65)				//���糬��90%���������ﵽ10kg,��ǿ�о����ݽ���������ֱ����������Ϊ5kg����
+			{
+				printf("\r\nNo.1��ʼ����������\r\n");
+				
+				preweight = weight1;
+				getDistance1 = 55;
+				nextStatus = 0x01;
+				break;
+			}
+			break;
+			
+		case 0x01:
+			if(weight1 < preweight)
+			{
+				tempDate = preweight - weight1;
+			}else{
+				tempDate = 0;
+			}
+			
+			if(tempDate > 500)			//�������ᣨ������������Ͱ��
+			{
+				
+				printf("\r\nNo.1����ȡ��������\r\n");
+				nextStatus = 0x00;
+				break;
+			}else{
+				getDistance1 = 55;
+			}
+			break;
+			
+		default:
+			nextStatus = 0x00;
+			break;
+	}
+}
+
+/*
+***********************************************************************
+*	�� �� ��: OverflowDataCorrection1
+*	����˵��: ������������
+*	��    ��:	��
+*	�� �� ֵ: ��
+***********************************************************************
+*/
+static void OverflowDataCorrection2(void)
+{
+	static uint8_t currentStatus = 0x00;
+	static uint8_t nextStatus = 0x00;
+	
+	static uint16_t preweight = 0;
+	uint16_t tempDate = 0;
+	
+	currentStatus = nextStatus;
+	switch(currentStatus)
+	{
+		case 0x00:
+			if((weight2 > 2000) && (getDistance2) < 65)				//���糬��90%���������ﵽ10kg,��ǿ�о����ݽ���������ֱ����������Ϊ5kg����
+			{
+				printf("\r\nNo.2��ʼ����������\r\n");
+				
+				preweight = weight2;
+				getDistance2 = 55;
+				nextStatus = 0x01;
+				break;
+			}
+			break;
+			
+		case 0x01:
+			if(weight2 < preweight)
+			{
+				tempDate = preweight - weight2;
+			}else{
+				tempDate = 0;
+			}
+			
+			if(tempDate > 500)		//�������ᣨ������������Ͱ��
+			{
+				printf("\r\nNo.2����ȡ��������\r\n");
+				nextStatus = 0x00;
+				break;
+			}else{
+				getDistance2 = 55;
+			}
+			break;
+			
+		default:
+			nextStatus = 0x00;
+			break;
+	}
+}
+
+
+/*
+***********************************************************************
+*	�� �� ��: M_S_DataDecode
+*	����˵��: ���ӻ�ͨѶ���ݽ���
+*	��    ��:	*pRxBuf -> ���ջ���ĵ�ַ��*pTxBuf -> �������ݻ����ַ 
+*	�� �� ֵ: ��
+***********************************************************************
+*/
+static void M_S_DataDecode(uint8_t *pRxBuf, uint8_t *pTxBuf)
+{
+	uint8_t comNum = 0;							//���ӻ�ָ����
+	
+	comNum = *(pRxBuf+1);
+	
+// 	printf("\r\nS->M <-- 0x%02X\r\n", comNum);
+	switch(comNum)														//ͨѶ��������
+	{			
+		case 0x01:			//�յ��ӻ�MCU2���͹����ĳ��ء���ࡢ��翪��״̬����
+			weight1 = *(pRxBuf+3) << 8;
+			weight1 |= *(pRxBuf+4);
+		
+			weight2 = *(pRxBuf+5) << 8;
+			weight2 |= *(pRxBuf+6);
+		
+			weight3 = *(pRxBuf+7) << 8;
+			weight3 |= *(pRxBuf+8);
+		
+			weight4 = *(pRxBuf+9) << 8;
+			weight4 |= *(pRxBuf+10);
+			
+			//�������
+			//����Ӳ���ӿ�������˳�����ת��
+#ifdef FOUR_CHANNEL_AND_HARMFUL
+//------------------------------------------------------------------->			
+
+			if(updateDistanceMark == 0)		//Ͷ�Ź��̲����²��ֵ
+			{
+				getDistance1 = CorrectOverflowDistance(*(pRxBuf+11), weight1,
+																							 devChannel1DisMaxVal, devChannel1DisDepthVal);
+				getDistance2 = CorrectOverflowDistance(*(pRxBuf+12), weight2,
+																							 devChannel2DisMaxVal, devChannel2DisDepthVal);
+				getDistance3 = CorrectOverflowDistance(*(pRxBuf+13), weight3,
+																							 devChannel3DisMaxVal, devChannel3DisDepthVal);
+				getDistance4 = CorrectOverflowDistance(*(pRxBuf+14), weight4,
+																							 devChannel4DisMaxVal, devChannel4DisDepthVal);
+
+				outputDistance1 = getDistance1;
+				outputDistance2 = getDistance2;
+				outputDistance3 = getDistance3;
+				outputDistance4 = getDistance4;
+
+				printf("\r\nGet D1=%d, D2=%d, D3=%d, D4=%d\r\n",
+							 getDistance1, getDistance2, getDistance3, getDistance4);
+			}
+//<-------------------------------------------------------------------
+			
+			//������ݾ�������
+//			if(updateDistanceMark == 0)		//Ͷ�Ź��̲����²��ֵ
+//			{
+//				tempData1 = *(pRxBuf+11);
+//				tempData2 = *(pRxBuf+12);
+//				
+//				//ȡ����1·�������
+//				if(tempData1 == 255)
+//				{
+//					getDistance1 = 255;
+//				}else{
+//					tempData1 += 35;					//���ݰ�װ�߶Ȳ�������ֵ
+//					
+//					if(tempData1 > distanceParamAtStart)
+//					{
+//						getDistance1 = devChannel1DisMaxVal;
+//					}else{
+//						getDistance1 = tempData1;
+//					}
+//				}
+//				
+//				//20230727�޸ģ�������������
+//				OverflowDataCorrection1();
+//				
+//				if((weight1 < 1500) && (getDistance1) > 80)
+//				{
+//					getDistance1 = devChannel1DisMaxVal;
+//				}
+//				
+//				//20230524�޸ģ������⴫������������װ�߶Ȳ�����βɼ�����
+//				outputDistance1 = getDistance1;
+//				
+////				distanceBuf1[distanceCnt1++] = getDistance1;
+////				if(distanceCnt1 >= DISTANCE_CNT_MAX)
+////				{
+////					distanceCnt1 = DISTANCE_CNT_MAX - 1;
+////					printf("\r\nCnt1 >= MAX\r\n");
+////				}
+//				
+//				//ȡ����2·�������
+//				if(tempData2 == 255)
+//				{
+//					getDistance2 = 255;
+//				}else{
+//					tempData2 += 35;					//���ݰ�װ�߶Ȳ�������ֵ
+//					
+//					if(tempData2 > distanceParamAtStart)
+//					{
+//						getDistance2 = devChannel1DisMaxVal;
+//					}else{
+//						getDistance2 = tempData2;
+//					}
+//				}
+//				
+//				//20230727�޸ģ�������������
+//				OverflowDataCorrection2();
+//				
+//				if((weight2 < 1500) && (getDistance2) > 80)
+//				{
+//					getDistance2 = devChannel2DisMaxVal;
+//				}
+//				
+//				//20230524�޸ģ������⴫������������װ�߶Ȳ�����βɼ�����
+//				outputDistance2 = getDistance2;
+//				
+////				distanceBuf2[distanceCnt2++] = getDistance2;
+////				if(distanceCnt2 >= DISTANCE_CNT_MAX)
+////				{
+////					distanceCnt2 = DISTANCE_CNT_MAX - 1;
+////					printf("\r\nCnt2 >= MAX\r\n");
+////				}
+//				
+//				
+//				getDistance3 = *(pRxBuf+13);
+//				getDistance4 = *(pRxBuf+14);
+//				
+//				printf("\r\nGet D1=%d, D2=%d\r\n", getDistance1, getDistance2);
+//			}
+			
+//			getDistance1 = *(pRxBuf+11);
+//			getDistance2 = *(pRxBuf+12);
+//			getDistance3 = *(pRxBuf+13);
+//			getDistance4 = *(pRxBuf+14);
+#else
+			getDistance1 = *(pRxBuf+11);
+			getDistance4 = *(pRxBuf+12);
+			getDistance2 = *(pRxBuf+13);
+			getDistance3 = *(pRxBuf+14);
+#endif
+			
+			//�����¶�
+			temperature_C = *(pRxBuf+15);
+			
+			//������״̬
+			getRecycleClearDoorMark = *(pRxBuf+16);
+			
+			//�ⲿ�¶�
+			temperature_A = *(pRxBuf+17);
+			
+			//�ӽ�����״̬
+			switchKey1Status = *(pRxBuf+18);
+			switchKey2Status = *(pRxBuf+19);
+			
+			getMcu2SensorDataMark = 1;								//��־���յ����ݣ����ⲿ��ȡ�����
+			break;
+		
+		case 0x02:		//MCU2��⵽�Ĺ�翪��״̬���ݣ����ڵ�����ʹ�ã�
+			optoKeyStatus = *(pRxBuf+3);
+			break;
+			
+		case 0x03:		//GPS��λ��Ϣ
+			gpsConnectSta = *(pRxBuf+3);							//GPSģ��Ӳ������״̬
+			gpsStatus = *(pRxBuf+4);									//GPS��λ״̬
+			gpsEW = *(pRxBuf+5);											//���ȷ���0->E-��,W-����
+			gpsLon = *(pRxBuf+6) << 24;								//���ȣ��ѷŴ�1000000����
+			gpsLon |= *(pRxBuf+7) << 16;
+			gpsLon |= *(pRxBuf+8) << 8;
+			gpsLon |= *(pRxBuf+9);
+			gpsNS = *(pRxBuf+10);											//γ�ȷ���0->N-��,1->S-�ϣ�
+			gpsLat = *(pRxBuf+11) << 24;							//γ�ȣ��ѷŴ�1000000����
+			gpsLat |= *(pRxBuf+12) << 16;
+			gpsLat |= *(pRxBuf+13) << 8;
+			gpsLat |= *(pRxBuf+14);
+			
+			getGpsStatus = 1;
+			break;
+			
+		case 0xA2:		//ȡ��У׼���
+			receiveScaleNum = *(pRxBuf+3);
+			switch(receiveScaleNum)
+			{
+				case 1:
+					getCalibraZeroMark1 = 1;
+					break;
+					
+				case 2:
+					getCalibraZeroMark2 = 1;
+					break;
+					
+				default:
+					break;
+			}
+			
+			break;
+			
+		case 0xA3:		//У׼���
+			receiveScaleNum = *(pRxBuf+3);
+			switch(receiveScaleNum)
+			{
+				case 1:
+					getCalibraParamOkMark1 = 1;
+					break;
+					
+				case 2:
+					getCalibraParamOkMark2 = 1;
+					break;
+					
+				default:
+					break;
+			}
+			
+			break;
+			
+		default: 			//��������
+			break;
+	}
+}
+
+/*
+***********************************************************************
+*	�� �� ��: M_S_DataDecodeTask
+*	����˵��: ���ӻ�����ͨѶ������������
+*	��    ��:	��
+*	�� �� ֵ: ��
+***********************************************************************
+*/
+void M_S_DataDecodeTask(void)
+{
+	if(USART2_RX_STA == 0xfd)													//�н��յ��������͵�����
+	{
+		M_S_DataDecode(USART2_RX_BUF, USART2_TX_BUF); 	//���ͷ��ص�����
+		
+		memset(USART2_RX_BUF, 0x00, USART2_RECV_LEN);		//�����������
+		USART2_RX_STA = 0;
+	}
+}
+
+/******************** (C) COPYRIGHT 2017 CXHY *****END OF FILE*******************/ 
diff --git a/STM32_4路称重_Git提交精简工程/src/HARDWARE/DEVICE/m_s_comm.h b/STM32_4路称重_Git提交精简工程/src/HARDWARE/DEVICE/m_s_comm.h
new file mode 100755
index 0000000..9f718d3
--- /dev/null
+++ b/STM32_4路称重_Git提交精简工程/src/HARDWARE/DEVICE/m_s_comm.h
@@ -0,0 +1,16 @@
+#ifndef __M_S_COMM_H
+#define __M_S_COMM_H
+#include "stm32f10x.h"
+
+#define M_S_RECV_LEN		128												//�����ջ����ֽ���
+#define M_S_SEND_LEN		128												//����ͻ����ֽ���
+
+extern uint8_t M_S_RX_BUF[M_S_RECV_LEN];     			//���ջ���
+extern uint8_t M_S_TX_BUF[M_S_SEND_LEN];					//���ͻ���
+
+void M_S_CommandSend(uint8_t comNum);							//���ӻ����ݷ���
+void M_S_DataDecodeTask(void);										//���ӻ����ݽ���
+
+#endif
+
+/******************** (C) COPYRIGHT 2017 CXHY *****END OF FILE*******************/ 
diff --git a/STM32_4路称重_Git提交精简工程/src/HARDWARE/Disinfection/disinfection.c b/STM32_4路称重_Git提交精简工程/src/HARDWARE/Disinfection/disinfection.c
new file mode 100755
index 0000000..9df7896
--- /dev/null
+++ b/STM32_4路称重_Git提交精简工程/src/HARDWARE/Disinfection/disinfection.c
@@ -0,0 +1,308 @@
+/*************************** (C) COPYRIGHT 2017 YNHB ****************************
+ * �ļ���  ��disinfection.c
+ * ��  ��  ���������Ƴ���
+ * ��  ��  ��V1.0
+ * ��  ��  ��XuZhongPing
+ * ��  ��  ��2020/04/17
+*********************************************************************************/
+#include "disinfection.h"
+#include "timer.h"
+#include "ElectronicLock.h"
+#include "motor.h"
+
+uint8_t disinfectionStatus = 0;
+uint8_t disinfectingMark = 0;							//����״̬
+uint8_t sprayDisinfectionStatus = 0;
+uint8_t sprayDisinfectingMark = 0;				//��������״̬��־
+
+/*
+***********************************************************************
+*	�� �� ��: StartUpDisinfection
+*	����˵��: ��������
+*	��    �Σ���
+*	�� �� ֵ: ��
+***********************************************************************
+*/
+void StartUpDisinfection(void)
+{
+	Unlock(5);
+	
+	printf("\r\n��������������\r\n");
+	disinfectionStatus = 1;											//��־��ǰ��������״̬
+}
+
+/*
+***********************************************************************
+*	�� �� ��: StopDisinfection
+*	����˵��: ֹͣ����
+*	��    �Σ���
+*	�� �� ֵ: ��
+***********************************************************************
+*/
+void StopDisinfection(void)
+{
+	Locked(5);
+	
+	printf("\r\nֹͣ����������\r\n");
+	disinfectionStatus = 0;											//��־��ǰ��������ֹͣ״̬
+}
+
+/*
+***********************************************************************
+*	�� �� ��: DisinfectingTask
+*	����˵��: ������������
+*	��    �Σ���
+*	�� �� ֵ: ��
+***********************************************************************
+*/
+void DisinfectingTask(void)
+{
+	static uint8_t executeSteps = 0;
+
+	static timer disinfectingTimer;							//��������ʱ��
+	static timer sleepTimer;										//����װ������ʱ��
+	static timer waitingTimer;
+	
+	static uint8_t timer_ok = 0;
+	
+	if(timer_ok == 0)
+	{
+		timer_ok = 1;
+		timer_set(&disinfectingTimer, CLOCK_SECOND*60*30);		//��������ʱ�䶨ʱ��
+		timer_set(&sleepTimer, CLOCK_SECOND*60*30);						//����װ������ʱ��
+		timer_set(&waitingTimer, CLOCK_SECOND*2);							//����1����ʱ��
+	}
+	
+	
+	switch(executeSteps)
+	{
+		case 0x00:
+			if(disinfectingMark == 1)
+			{
+				StartUpDisinfection();
+				printf("\r\n����������\r\n");
+				timer_restart(&disinfectingTimer);
+				executeSteps = 0x01;
+				break;
+			}
+			break;
+		
+		case 0x01:		//����������
+			if(timer_expired(&disinfectingTimer))
+			{
+				StopDisinfection();													//����ʱ�䵽ֹͣ����
+				
+				printf("\r\n������ɣ�\r\n");
+				disinfectingMark = 0;
+				executeSteps = 0x03;
+				break;
+			}
+			
+			//���������������Ͷ�ţ�����ͣ����
+			if(disinfectingMark == 2)
+			{
+				StopDisinfection();
+				printf("\r\n��ͣ������\r\n");
+				executeSteps = 0x02;
+				break;
+			}
+			
+// 			//���������������Ͷ�Ż��ߴ������ţ����ж�����
+// 			if(disinfectingMark == 0)
+// 			{
+// 				StopDisinfection();
+// 				printf("\r\n�ж�������\r\n");
+// 				executeSteps = 0x03;
+// 				break;
+// 			}
+			break;
+			
+		case 0x02:		//��ͣ����
+			if(timer_expired(&disinfectingTimer))
+			{
+				StopDisinfection();													//����ʱ�䵽ֹͣ����
+				
+				printf("\r\n����ʱ�䵽��\r\n");
+				disinfectingMark = 0;
+				executeSteps = 0x03;
+				break;
+			}
+			
+			if(disinfectingMark == 1)
+			{
+				StartUpDisinfection();
+				printf("\r\n��������������\r\n");
+				executeSteps = 0x01;
+				break;
+			}
+			break;
+			
+		case 0x03:		//����װ���������߶�ʱ
+			printf("\r\n����װ�ý������ߣ�\r\n");
+			timer_restart(&sleepTimer);
+			executeSteps = 0x04;
+			break;
+			
+		case 0x04:		//����װ�ý�������
+			if(timer_expired(&sleepTimer))
+			{
+				printf("\r\n����װ������ʱ�䵽��\r\n");
+				executeSteps = 0x00;
+			}
+			break;
+			
+		default:
+			StopDisinfection();
+			disinfectingMark = 0;
+			executeSteps = 0x00;
+			break;
+	}
+}
+
+
+/*
+***********************************************************************
+*	�� �� ��: StartUpDisinfection
+*	����˵��: ��������
+*	��    �Σ���
+*	�� �� ֵ: ��
+***********************************************************************
+*/
+void StartUpSprayDisinfection(void)
+{
+	DoorClose(3);
+	
+	printf("\r\n������������������\r\n");
+	sprayDisinfectionStatus = 1;											//��־��ǰ��������״̬
+}
+
+/*
+***********************************************************************
+*	�� �� ��: StopDisinfection
+*	����˵��: ֹͣ����
+*	��    �Σ���
+*	�� �� ֵ: ��
+***********************************************************************
+*/
+void StopSprayDisinfection(void)
+{
+	DoorStop(3);
+	
+	printf("\r\nֹͣ��������������\r\n");
+	sprayDisinfectionStatus = 0;											//��־��ǰ��������ֹͣ״̬
+}
+
+/*
+***********************************************************************
+*	�� �� ��: SprayDisinfectingTask
+*	����˵��: ����������������
+*	��    �Σ���
+*	�� �� ֵ: ��
+***********************************************************************
+*/
+void SprayDisinfectingTask(void)
+{
+	static uint8_t executeSteps = 0;
+
+	static timer disinfectingTimer;							//��������ʱ��
+	static timer sleepTimer;										//����װ������ʱ��
+	static timer waitingTimer;
+	
+	static uint8_t timer_ok = 0;
+	
+	if(timer_ok == 0)
+	{
+		timer_ok = 1;
+		timer_set(&disinfectingTimer, CLOCK_SECOND*3);		//��������ʱ�䶨ʱ��
+// 		timer_set(&sleepTimer, CLOCK_SECOND*60*30);						//����װ������ʱ��
+		timer_set(&sleepTimer, CLOCK_SECOND*1);								//����װ������ʱ��
+		timer_set(&waitingTimer, CLOCK_SECOND*2);							//����1����ʱ��
+	}
+	
+	
+	switch(executeSteps)
+	{
+		case 0x00:
+			if(sprayDisinfectingMark == 1)
+			{
+				StartUpSprayDisinfection();
+				printf("\r\n����������\r\n");
+				timer_restart(&disinfectingTimer);
+				executeSteps = 0x01;
+				break;
+			}
+			break;
+		
+		case 0x01:		//����������
+			if(timer_expired(&disinfectingTimer))
+			{
+				StopSprayDisinfection();													//����ʱ�䵽ֹͣ����
+				
+				printf("\r\n������ɣ�\r\n");
+				sprayDisinfectingMark = 0;
+				executeSteps = 0x03;
+				break;
+			}
+			
+			//���������������Ͷ�ţ�����ͣ����
+			if(sprayDisinfectingMark == 2)
+			{
+				StopSprayDisinfection();
+				printf("\r\n��ͣ������\r\n");
+				executeSteps = 0x02;
+				break;
+			}
+			
+// 			//���������������Ͷ�Ż��ߴ������ţ����ж�����
+// 			if(disinfectingMark == 0)
+// 			{
+// 				StopDisinfection();
+// 				printf("\r\n�ж�������\r\n");
+// 				executeSteps = 0x03;
+// 				break;
+// 			}
+			break;
+			
+		case 0x02:		//��ͣ����
+			if(timer_expired(&disinfectingTimer))
+			{
+				StopSprayDisinfection();													//����ʱ�䵽ֹͣ����
+				
+				printf("\r\n����ʱ�䵽��\r\n");
+				sprayDisinfectingMark = 0;
+				executeSteps = 0x03;
+				break;
+			}
+			
+			if(sprayDisinfectingMark == 1)
+			{
+				StartUpSprayDisinfection();
+				printf("\r\n��������������\r\n");
+				executeSteps = 0x01;
+				break;
+			}
+			break;
+			
+		case 0x03:		//����װ���������߶�ʱ
+			printf("\r\n����װ�ý������ߣ�\r\n");
+			timer_restart(&sleepTimer);
+			executeSteps = 0x04;
+			break;
+			
+		case 0x04:		//����װ�ý�������
+			if(timer_expired(&sleepTimer))
+			{
+				printf("\r\n����װ������ʱ�䵽��\r\n");
+				executeSteps = 0x00;
+			}
+			break;
+			
+		default:
+			StopSprayDisinfection();
+			sprayDisinfectingMark = 0;
+			executeSteps = 0x00;
+			break;
+	}
+}
+
+/******************** (C) COPYRIGHT 2017 YNHB *****END OF FILE*******************/
diff --git a/STM32_4路称重_Git提交精简工程/src/HARDWARE/Disinfection/disinfection.h b/STM32_4路称重_Git提交精简工程/src/HARDWARE/Disinfection/disinfection.h
new file mode 100755
index 0000000..e0d7c39
--- /dev/null
+++ b/STM32_4路称重_Git提交精简工程/src/HARDWARE/Disinfection/disinfection.h
@@ -0,0 +1,28 @@
+/*************************** (C) COPYRIGHT 2017 CXHY ****************************
+ * �ļ���  ��disinfection.h
+ * ��  ��  ���������Ƴ���ͷ�ļ�
+ * ��  ��  ��V1.0
+ * ��  ��  ��XuZhongPing
+ * ��  ��  ��2020/04/17
+*********************************************************************************/
+#ifndef __DISINFECTION_H
+#define __DISINFECTION_H	 
+
+#include "stm32f10x.h"
+#include "stdio.h"
+
+extern uint8_t disinfectionStatus;
+extern uint8_t disinfectingMark;							//����״̬
+extern uint8_t sprayDisinfectingMark;					//��������״̬��־
+
+void StartUpDisinfection(void);								//������������
+void StopDisinfection(void);									//ֹͣ��������
+void DisinfectingTask(void);									//����������������
+
+void StartUpSprayDisinfection(void);					//������������
+void StopSprayDisinfection(void);							//ֹͣ��������
+void SprayDisinfectingTask(void);
+
+#endif
+
+/******************** (C) COPYRIGHT 2017 CXHY *****END OF FILE*******************/
diff --git a/STM32_4路称重_Git提交精简工程/src/HARDWARE/EXTI/exti.c b/STM32_4路称重_Git提交精简工程/src/HARDWARE/EXTI/exti.c
new file mode 100755
index 0000000..a34b970
--- /dev/null
+++ b/STM32_4路称重_Git提交精简工程/src/HARDWARE/EXTI/exti.c
@@ -0,0 +1,55 @@
+#include "exti.h"
+#include "led.h"
+#include "key.h"
+#include "delay.h"
+#include "usart.h"
+
+
+//�ⲿ�жϳ�ʼ������
+//��ʼ��PA0,PA13,PA15Ϊ�ж�����.
+void EXTIX_Init(void)
+{
+  	GPIO_InitTypeDef GPIO_InitStructure;
+ 	EXTI_InitTypeDef EXTI_InitStructure;
+ 	NVIC_InitTypeDef NVIC_InitStructure;
+
+
+  	GPIO_PinRemapConfig(GPIO_Remap_SWJ_JTAGDisable , ENABLE);	//�ر�jtag
+
+  	RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOC|RCC_APB2Periph_AFIO,ENABLE);
+
+ //init GPIOC.7	  ��������
+  	GPIO_InitStructure.GPIO_Pin  = GPIO_Pin_7;
+  	GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPD; 
+  	GPIO_Init(GPIOC, &GPIO_InitStructure);
+
+
+  //GPIOC.7
+ 	GPIO_EXTILineConfig(GPIO_PortSourceGPIOC,GPIO_PinSource7);
+
+  	EXTI_InitStructure.EXTI_Line=EXTI_Line7;
+  	EXTI_InitStructure.EXTI_Mode = EXTI_Mode_Interrupt;	
+  	EXTI_InitStructure.EXTI_Trigger = EXTI_Trigger_Rising;
+  	EXTI_InitStructure.EXTI_LineCmd = ENABLE;
+  	EXTI_Init(&EXTI_InitStructure);
+
+  
+  	NVIC_InitStructure.NVIC_IRQChannel = EXTI9_5_IRQn;			//ʹ�ܰ������ڵ��ⲿ�ж�ͨ��
+  	NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0x02;	//��ռ���ȼ�4λ,��16��
+  	NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0x02;					//��ռ���ȼ�0λ,�����ȼ�4λ
+  	NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;								//ʹ���ⲿ�ж�ͨ��
+  	NVIC_Init(&NVIC_InitStructure);  	
+}
+
+ 
+void EXTI9_5_IRQHandler(void)
+{
+    delay_ms(10);    //����
+  	if(EXTI_GetITStatus(EXTI_Line7) != RESET)	  //���ָ����EXTI7��·�������������
+	{	  
+		LED0=!LED0;
+		LED1=!LED1;	
+	}
+	EXTI_ClearITPendingBit(EXTI_Line7);  //���EXTI7��·����λ
+}
+ 
diff --git a/STM32_4路称重_Git提交精简工程/src/HARDWARE/EXTI/exti.h b/STM32_4路称重_Git提交精简工程/src/HARDWARE/EXTI/exti.h
new file mode 100755
index 0000000..0878cc8
--- /dev/null
+++ b/STM32_4路称重_Git提交精简工程/src/HARDWARE/EXTI/exti.h
@@ -0,0 +1,21 @@
+#ifndef __EXTI_H
+#define __EXIT_H	 
+#include "sys.h"
+//////////////////////////////////////////////////////////////////////////////////	 
+//������ֻ��ѧϰʹ�ã�δ���������ɣ��������������κ���;
+//Mini STM32������
+//�ⲿ�ж� ��������			   
+//����ԭ��@ALIENTEK
+//������̳:www.openedv.com
+//�޸�����:2010/12/01  
+//�汾��V1.0
+//��Ȩ���У�����ؾ���
+//Copyright(C) ����ԭ�� 2009-2019
+//All rights reserved	  
+////////////////////////////////////////////////////////////////////////////////// 	  
+						    
+	 
+void EXTIX_Init(void);//IO��ʼ��
+		 					    
+#endif
+
diff --git a/STM32_4路称重_Git提交精简工程/src/HARDWARE/ElectronicLock/ElectronicLock.c b/STM32_4路称重_Git提交精简工程/src/HARDWARE/ElectronicLock/ElectronicLock.c
new file mode 100755
index 0000000..c68c227
--- /dev/null
+++ b/STM32_4路称重_Git提交精简工程/src/HARDWARE/ElectronicLock/ElectronicLock.c
@@ -0,0 +1,270 @@
+/*************************** (C) COPYRIGHT 2017 CXHY ****************************
+ * �ļ���  ��ElectronicLock.c
+ * ��  ��  ��������������������
+ * ��  ��  ��V1.0
+ * ��  ��  ��XuZhongPing
+ * ��  ��  ��2017/05/06 
+*********************************************************************************/
+#include "ElectronicLock.h"
+#include "RFID_IC.h"
+#include "timer.h"
+
+#define ELE_LOCK1_PeriphClock		RCC_APB2Periph_GPIOC
+#define ELE_LOCK1_PORT					GPIOC
+#define ELE_LOCK1_PIN						GPIO_Pin_2
+
+#define ELE_LOCK2_PeriphClock		RCC_APB2Periph_GPIOC
+#define ELE_LOCK2_PORT					GPIOC
+#define ELE_LOCK2_PIN						GPIO_Pin_3
+
+#define ELE_LOCK3_PeriphClock		RCC_APB2Periph_GPIOA
+#define ELE_LOCK3_PORT					GPIOA
+#define ELE_LOCK3_PIN						GPIO_Pin_0
+
+#define ELE_LOCK4_PeriphClock		RCC_APB2Periph_GPIOA
+#define ELE_LOCK4_PORT					GPIOA
+#define ELE_LOCK4_PIN						GPIO_Pin_1
+
+#define ELE_LOCK5_PeriphClock		RCC_APB2Periph_GPIOB
+#define ELE_LOCK5_PORT					GPIOB
+#define ELE_LOCK5_PIN						GPIO_Pin_13
+
+#define ELE_LOCK6_PeriphClock		RCC_APB2Periph_GPIOB
+#define ELE_LOCK6_PORT					GPIOB
+#define ELE_LOCK6_PIN						GPIO_Pin_14
+
+
+uint8_t lockStatus_1 = 0;
+uint8_t lockStatus_2 = 0;
+uint8_t lockStatus_3 = 0;
+uint8_t lockStatus_4 = 0;
+uint8_t lockStatus_5 = 0;
+uint8_t lockStatus_6 = 0;
+
+uint8_t isUnlockingMark = 0;
+
+/*
+***********************************************************************
+*	�� �� ��: ElectronicLock_Init
+*	����˵��: ����������IO�ڳ�ʼ��
+*	��    �Σ���
+*	�� �� ֵ: ��
+***********************************************************************
+*/
+void ElectronicLock_Init(void)
+{
+ 	GPIO_InitTypeDef  GPIO_InitStructure;
+ 	
+ 	RCC_APB2PeriphClockCmd(ELE_LOCK1_PeriphClock, ENABLE);	 					//ʹ�ܶ˿�ʱ��
+	RCC_APB2PeriphClockCmd(ELE_LOCK2_PeriphClock, ENABLE);
+	RCC_APB2PeriphClockCmd(ELE_LOCK3_PeriphClock, ENABLE);
+	RCC_APB2PeriphClockCmd(ELE_LOCK4_PeriphClock, ENABLE);
+	RCC_APB2PeriphClockCmd(ELE_LOCK5_PeriphClock, ENABLE);
+	RCC_APB2PeriphClockCmd(ELE_LOCK6_PeriphClock, ENABLE);
+	
+	//��һ·�����IO������
+ 	GPIO_InitStructure.GPIO_Pin = ELE_LOCK1_PIN;							
+ 	GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP; 		 							
+ 	GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;		 							
+ 	GPIO_Init(ELE_LOCK1_PORT, &GPIO_InitStructure);					 					
+	
+ 	GPIO_ResetBits(ELE_LOCK1_PORT, ELE_LOCK1_PIN);	 	
+
+	//�ڶ�·�����IO������
+	GPIO_InitStructure.GPIO_Pin = ELE_LOCK2_PIN;							
+ 	GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP; 		 							
+ 	GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;		 							
+ 	GPIO_Init(ELE_LOCK2_PORT, &GPIO_InitStructure);	
+	
+	GPIO_ResetBits(ELE_LOCK2_PORT, ELE_LOCK2_PIN);
+	
+	//����·�����IO������
+	GPIO_InitStructure.GPIO_Pin = ELE_LOCK3_PIN;							
+ 	GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP; 		 							
+ 	GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;		 							
+ 	GPIO_Init(ELE_LOCK3_PORT, &GPIO_InitStructure);	
+	
+	GPIO_ResetBits(ELE_LOCK3_PORT, ELE_LOCK3_PIN);
+	
+	//����·�����IO������
+	GPIO_InitStructure.GPIO_Pin = ELE_LOCK4_PIN;							
+ 	GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP; 		 							
+ 	GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;		 							
+ 	GPIO_Init(ELE_LOCK4_PORT, &GPIO_InitStructure);	
+	
+	GPIO_ResetBits(ELE_LOCK4_PORT, ELE_LOCK4_PIN);
+	
+	//����·�����IO������
+	GPIO_InitStructure.GPIO_Pin = ELE_LOCK5_PIN;							
+ 	GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP; 		 							
+ 	GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;		 							
+ 	GPIO_Init(ELE_LOCK5_PORT, &GPIO_InitStructure);	
+	
+	GPIO_ResetBits(ELE_LOCK5_PORT, ELE_LOCK5_PIN);
+	
+	//����·�����IO������
+	GPIO_InitStructure.GPIO_Pin = ELE_LOCK6_PIN;							
+ 	GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP; 		 							
+ 	GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;		 							
+ 	GPIO_Init(ELE_LOCK6_PORT, &GPIO_InitStructure);	
+	
+	GPIO_ResetBits(ELE_LOCK6_PORT, ELE_LOCK6_PIN);
+}
+
+/*
+***********************************************************************
+*	�� �� ��: Unlock
+*	����˵��: ����
+*	��    �Σ�num -> ��һ·������
+*	�� �� ֵ: ��
+***********************************************************************
+*/
+void Unlock(uint8_t num)
+{
+	switch(num)
+	{
+		case 1:
+			GPIO_SetBits(ELE_LOCK1_PORT, ELE_LOCK1_PIN);
+			lockStatus_1 = 1;
+			break;
+			
+		case 2:
+			GPIO_SetBits(ELE_LOCK2_PORT, ELE_LOCK2_PIN);
+			lockStatus_2 = 1;
+			break;
+			
+		case 3:
+			GPIO_SetBits(ELE_LOCK3_PORT, ELE_LOCK3_PIN);
+			lockStatus_3 = 1;
+			break;
+			
+		case 4:
+			GPIO_SetBits(ELE_LOCK4_PORT, ELE_LOCK4_PIN);
+			lockStatus_4 = 1;
+			break;
+			
+		case 5:
+			GPIO_SetBits(ELE_LOCK5_PORT, ELE_LOCK5_PIN);
+			lockStatus_5 = 1;
+			break;
+			
+		case 6:
+			GPIO_SetBits(ELE_LOCK6_PORT, ELE_LOCK6_PIN);
+			lockStatus_6 = 1;
+			break;
+			
+		default:
+			printf("\r\nû�д�ͨ���������-> %d\r\n", num);
+			break;
+	}
+}
+
+/*
+***********************************************************************
+*	�� �� ��: Locked
+*	����˵��: ����
+*	��    �Σ�num -> ��һ·������
+*	�� �� ֵ: ��
+***********************************************************************
+*/
+void Locked(uint8_t num)
+{
+	switch(num)
+	{
+		case 1:
+			GPIO_ResetBits(ELE_LOCK1_PORT, ELE_LOCK1_PIN);
+			lockStatus_1 = 0;
+			break;
+			
+		case 2:
+			GPIO_ResetBits(ELE_LOCK2_PORT, ELE_LOCK2_PIN);
+			lockStatus_2 = 0;
+			break;
+			
+		case 3:
+			GPIO_ResetBits(ELE_LOCK3_PORT, ELE_LOCK3_PIN);
+			lockStatus_3 = 0;
+			break;
+			
+		case 4:
+			GPIO_ResetBits(ELE_LOCK4_PORT, ELE_LOCK4_PIN);
+			lockStatus_4 = 0;
+			break;
+			
+		case 5:
+			GPIO_ResetBits(ELE_LOCK5_PORT, ELE_LOCK5_PIN);
+			lockStatus_5 = 0;
+			break;
+			
+		case 6:
+			GPIO_ResetBits(ELE_LOCK6_PORT, ELE_LOCK6_PIN);
+			lockStatus_6 = 0;
+			break;
+			
+		default:
+			printf("\r\nû�д�ͨ���������-> %d\r\n", num);
+			break;
+	}
+}
+
+/*
+***********************************************************************
+*	�� �� ��: ElectronicLockCtrlTask
+*	����˵��: ��������������
+*	��    �Σ���
+*	�� �� ֵ: ��
+***********************************************************************
+*/
+void ElectronicLockCtrlTask(void)
+{
+	static uint8_t eleLockNum = 1;
+	static uint8_t EleLockStatus = 0x00;
+	
+	static timer waitingTimer;
+	static uint8_t timer_ok = 0;
+	
+	if(timer_ok == 0)
+	{
+		timer_ok = 1;
+		timer_set(&waitingTimer, 2);
+	}
+	
+	switch(EleLockStatus)
+	{
+		case 0x00:
+			if(timer_expired(&waitingTimer))
+			{
+				Unlock(eleLockNum);
+				
+				printf("\r\n���� -> %d\r\n", eleLockNum);
+				timer_restart(&waitingTimer);
+				EleLockStatus = 0x01;
+			}	
+			break;
+			
+		case 0x01:
+			if(timer_expired(&waitingTimer))
+			{
+				Locked(eleLockNum);
+				printf("\r\n���� -> %d\r\n", eleLockNum);
+				
+				eleLockNum++;
+				if(eleLockNum >= 7)
+				{
+					eleLockNum = 1;
+				}
+				timer_restart(&waitingTimer);
+				EleLockStatus = 0x00;
+				break;
+			}
+			break;
+			
+		default:
+			break;
+		
+	}
+}
+
+
+ 
+/******************** (C) COPYRIGHT 2017 CXHY *****END OF FILE*******************/ 
diff --git a/STM32_4路称重_Git提交精简工程/src/HARDWARE/ElectronicLock/ElectronicLock.h b/STM32_4路称重_Git提交精简工程/src/HARDWARE/ElectronicLock/ElectronicLock.h
new file mode 100755
index 0000000..ee1a768
--- /dev/null
+++ b/STM32_4路称重_Git提交精简工程/src/HARDWARE/ElectronicLock/ElectronicLock.h
@@ -0,0 +1,29 @@
+/*************************** (C) COPYRIGHT 2017 CXHY ****************************
+ * �ļ���  ��ElectronicLock.c
+ * ��  ��  ��������������������
+ * ��  ��  ��V1.0
+ * ��  ��  ��XuZhongPing
+ * ��  ��  ��2017/05/06 
+*********************************************************************************/
+#ifndef __ELE_LOCK_H
+#define __ELE_LOCK_H
+#include "stm32f10x.h"
+#include "stdio.h" 
+
+extern uint8_t lockStatus_1;
+extern uint8_t lockStatus_2;
+extern uint8_t lockStatus_3;
+extern uint8_t lockStatus_4;
+extern uint8_t lockStatus_5;
+extern uint8_t lockStatus_6;
+
+extern uint8_t isUnlockingMark;
+
+void ElectronicLock_Init(void);						//��ʼ��
+void Unlock(uint8_t num);
+void Locked(uint8_t num);
+void ElectronicLockCtrlTask(void);
+		 				    
+#endif
+
+/******************** (C) COPYRIGHT 2017 CXHY *****END OF FILE*******************/
diff --git a/STM32_4路称重_Git提交精简工程/src/HARDWARE/FLASH/flash.c b/STM32_4路称重_Git提交精简工程/src/HARDWARE/FLASH/flash.c
new file mode 100755
index 0000000..5895922
--- /dev/null
+++ b/STM32_4路称重_Git提交精简工程/src/HARDWARE/FLASH/flash.c
@@ -0,0 +1,257 @@
+#include "flash.h" 
+#include "spi.h"
+#include "delay.h"
+
+uint16_t SPI_FLASH_TYPE = W25Q64;		//Ĭ�Ͼ���25Q64
+
+//4KbytesΪһ��Sector
+//16������Ϊ1��Block
+//W25X16
+//����Ϊ2M�ֽ�,����32��Block,512��Sector 
+
+//��ʼ��SPI FLASH��IO��
+void SPI_Flash_Init(void)
+{	
+  GPIO_InitTypeDef GPIO_InitStructure;
+	RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOE, ENABLE);//PORTBʱ��ʹ�� 
+
+	GPIO_InitStructure.GPIO_Pin = GPIO_Pin_7;  // PA4 ���� 
+ 	GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP;  //�������
+	GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
+ 	GPIO_Init(GPIOE, &GPIO_InitStructure);
+ 	GPIO_SetBits(GPIOE, GPIO_Pin_7);
+
+// 	SPI1_Init();		   	//��ʼ��SPI
+// 	SPI_SetSpeed(SPI_BaudRatePrescaler_2);//����Ϊ18Mʱ��,����ģʽ
+	SPI_FLASH_TYPE = SPI_Flash_ReadID();//��ȡFLASH ID.  
+
+}  
+
+//��ȡSPI_FLASH��״̬�Ĵ���
+//BIT7  6   5   4   3   2   1   0
+//SPR   RV  TB BP2 BP1 BP0 WEL BUSY
+//SPR:Ĭ��0,״̬�Ĵ�������λ,���WPʹ��
+//TB,BP2,BP1,BP0:FLASH����д��������
+//WEL:дʹ������
+//BUSY:æ���λ(1,æ;0,����)
+//Ĭ��:0x00
+uint8_t SPI_Flash_ReadSR(void)   
+{  
+	uint8_t byte=0;   
+	SPI_FLASH_CS=0;                            //ʹ������   
+	SPI1_ReadWriteByte(W25X_ReadStatusReg);    //���Ͷ�ȡ״̬�Ĵ�������
+	byte=SPI1_ReadWriteByte(0Xff);             //��ȡһ���ֽ�  
+	SPI_FLASH_CS=1;                            //ȡ��Ƭѡ     
+	return byte;   
+} 
+//дSPI_FLASH״̬�Ĵ���
+//ֻ��SPR,TB,BP2,BP1,BP0(bit 7,5,4,3,2)����д!!!
+void SPI_FLASH_Write_SR(uint8_t sr)   
+{   
+	SPI_FLASH_CS=0;                            //ʹ������   
+	SPI1_ReadWriteByte(W25X_WriteStatusReg);   //����дȡ״̬�Ĵ�������    
+	SPI1_ReadWriteByte(sr);               //д��һ���ֽ�  
+	SPI_FLASH_CS=1;                            //ȡ��Ƭѡ     	      
+}   
+
+//SPI_FLASHдʹ��	
+//��WEL��λ   
+void SPI_FLASH_Write_Enable(void)   
+{
+	SPI_FLASH_CS=0;                            //ʹ������   
+    SPI1_ReadWriteByte(W25X_WriteEnable);      //����дʹ��  
+	SPI_FLASH_CS=1;                            //ȡ��Ƭѡ     	      
+} 
+
+//SPI_FLASHд��ֹ	
+//��WEL����  
+void SPI_FLASH_Write_Disable(void)   
+{  
+	SPI_FLASH_CS=0;                            //ʹ������   
+    SPI1_ReadWriteByte(W25X_WriteDisable);     //����д��ָֹ��    
+	SPI_FLASH_CS=1;                            //ȡ��Ƭѡ     	      
+} 			    
+//��ȡоƬID W25X16��ID:0XEF14
+uint16_t SPI_Flash_ReadID(void)
+{
+	uint16_t Temp = 0;	  
+	SPI_FLASH_CS=0;				    
+	SPI1_ReadWriteByte(0x90);//���Ͷ�ȡID����	    
+	SPI1_ReadWriteByte(0x00); 	    
+	SPI1_ReadWriteByte(0x00); 	    
+	SPI1_ReadWriteByte(0x00); 	 			   
+	Temp|=SPI1_ReadWriteByte(0xFF)<<8;  
+	Temp|=SPI1_ReadWriteByte(0xFF);	 
+	SPI_FLASH_CS=1;				    
+	return Temp;
+}   		    
+//��ȡSPI FLASH  
+//��ָ����ַ��ʼ��ȡָ�����ȵ�����
+//pBuffer:���ݴ洢��
+//ReadAddr:��ʼ��ȡ�ĵ�ַ(24bit)
+//NumByteToRead:Ҫ��ȡ���ֽ���(���65535)
+void SPI_Flash_Read(uint8_t* pBuffer, uint32_t ReadAddr, uint16_t NumByteToRead)   
+{ 
+	uint16_t i;    												    
+	SPI_FLASH_CS=0;                            //ʹ������   
+	SPI1_ReadWriteByte(W25X_ReadData);         //���Ͷ�ȡ����   
+	SPI1_ReadWriteByte((uint8_t)((ReadAddr)>>16));  //����24bit��ַ    
+	SPI1_ReadWriteByte((uint8_t)((ReadAddr)>>8));   
+	SPI1_ReadWriteByte((uint8_t)ReadAddr);   
+	for(i=0;i<NumByteToRead;i++)
+	{ 
+		pBuffer[i]=SPI1_ReadWriteByte(0XFF);   //ѭ������  
+	}
+		SPI_FLASH_CS=1;                            //ȡ��Ƭѡ     	      
+}  
+
+//SPI��һҳ(0~65535)��д������256���ֽڵ�����
+//��ָ����ַ��ʼд�����256�ֽڵ�����
+//pBuffer:���ݴ洢��
+//WriteAddr:��ʼд��ĵ�ַ(24bit)
+//NumByteToWrite:Ҫд����ֽ���(���256),������Ӧ�ó�����ҳ��ʣ���ֽ���!!!	 
+void SPI_Flash_Write_Page(uint8_t* pBuffer,uint32_t WriteAddr,uint16_t NumByteToWrite)
+{
+ 	uint16_t i;  
+	SPI_FLASH_Write_Enable();                  //SET WEL 
+	SPI_FLASH_CS=0;                            //ʹ������   
+	SPI1_ReadWriteByte(W25X_PageProgram);      //����дҳ����   
+	SPI1_ReadWriteByte((uint8_t)((WriteAddr)>>16)); //����24bit��ַ    
+	SPI1_ReadWriteByte((uint8_t)((WriteAddr)>>8));   
+	SPI1_ReadWriteByte((uint8_t)WriteAddr);   
+	for(i=0;i<NumByteToWrite;i++)SPI1_ReadWriteByte(pBuffer[i]);//ѭ��д��  
+	SPI_FLASH_CS=1;                            //ȡ��Ƭѡ 
+	SPI_Flash_Wait_Busy();					   //�ȴ�д�����
+} 
+//�޼���дSPI FLASH 
+//����ȷ����д�ĵ�ַ��Χ�ڵ�����ȫ��Ϊ0XFF,�����ڷ�0XFF��д������ݽ�ʧ��!
+//�����Զ���ҳ���� 
+//��ָ����ַ��ʼд��ָ�����ȵ�����,����Ҫȷ����ַ��Խ��!
+//pBuffer:���ݴ洢��
+//WriteAddr:��ʼд��ĵ�ַ(24bit)
+//NumByteToWrite:Ҫд����ֽ���(���65535)
+//CHECK OK
+void SPI_Flash_Write_NoCheck(uint8_t* pBuffer,uint32_t WriteAddr,uint16_t NumByteToWrite)   
+{ 			 		 
+	uint16_t pageremain;	   
+	pageremain=256-WriteAddr%256; //��ҳʣ����ֽ���		 	    
+	if(NumByteToWrite<=pageremain)pageremain=NumByteToWrite;//������256���ֽ�
+	while(1)
+	{	   
+		SPI_Flash_Write_Page(pBuffer,WriteAddr,pageremain);
+		if(NumByteToWrite==pageremain)break;//д�������
+	 	else //NumByteToWrite>pageremain
+		{
+			pBuffer+=pageremain;
+			WriteAddr+=pageremain;	
+
+			NumByteToWrite-=pageremain;			  //��ȥ�Ѿ�д���˵��ֽ���
+			if(NumByteToWrite>256)pageremain=256; //һ�ο���д��256���ֽ�
+			else pageremain=NumByteToWrite; 	  //����256���ֽ���
+		}
+	};	    
+} 
+//дSPI FLASH  
+//��ָ����ַ��ʼд��ָ�����ȵ�����
+//�ú�������������!
+//pBuffer:���ݴ洢��
+//WriteAddr:��ʼд��ĵ�ַ(24bit)
+//NumByteToWrite:Ҫд����ֽ���(���65535)  		   
+uint8_t SPI_FLASH_BUF[4096];
+void SPI_Flash_Write(uint8_t* pBuffer,uint32_t WriteAddr,uint16_t NumByteToWrite)   
+{ 
+	uint32_t secpos;
+	uint16_t secoff;
+	uint16_t secremain;	   
+ 	uint16_t i;    
+
+	secpos=WriteAddr/4096;//������ַ 0~511 for w25x16
+	secoff=WriteAddr%4096;//�������ڵ�ƫ��
+	secremain=4096-secoff;//����ʣ��ռ��С   
+
+	if(NumByteToWrite<=secremain)secremain=NumByteToWrite;//������4096���ֽ�
+	while(1) 
+	{	
+		SPI_Flash_Read(SPI_FLASH_BUF,secpos*4096,4096);//������������������
+		for(i=0;i<secremain;i++)//У������
+		{
+			if(SPI_FLASH_BUF[secoff+i]!=0XFF)break;//��Ҫ����  	  
+		}
+		if(i<secremain)//��Ҫ����
+		{
+			SPI_Flash_Erase_Sector(secpos);//�����������
+			for(i=0;i<secremain;i++)	   //����
+			{
+				SPI_FLASH_BUF[i+secoff]=pBuffer[i];	  
+			}
+			SPI_Flash_Write_NoCheck(SPI_FLASH_BUF,secpos*4096,4096);//д����������  
+
+		}else SPI_Flash_Write_NoCheck(pBuffer,WriteAddr,secremain);//д�Ѿ������˵�,ֱ��д������ʣ������. 				   
+		if(NumByteToWrite==secremain)break;//д�������
+		else//д��δ����
+		{
+			secpos++;//������ַ��1
+			secoff=0;//ƫ��λ��Ϊ0 	 
+
+			pBuffer+=secremain;  //ָ��ƫ��
+			WriteAddr+=secremain;//д��ַƫ��	   
+			NumByteToWrite-=secremain;				//�ֽ����ݼ�
+			if(NumByteToWrite>4096)secremain=4096;	//��һ����������д����
+			else secremain=NumByteToWrite;			//��һ����������д����
+		}	 
+	};	 	 
+}
+//��������оƬ
+//��Ƭ����ʱ��:
+//W25X16:25s 
+//W25X32:40s 
+//W25X64:40s 
+//�ȴ�ʱ�䳬��...
+void SPI_Flash_Erase_Chip(void)   
+{                                             
+	SPI_FLASH_Write_Enable();                  //SET WEL 
+	SPI_Flash_Wait_Busy();   
+	SPI_FLASH_CS=0;                            //ʹ������   
+	SPI1_ReadWriteByte(W25X_ChipErase);        //����Ƭ��������  
+	SPI_FLASH_CS=1;                            //ȡ��Ƭѡ     	      
+	SPI_Flash_Wait_Busy();   				   //�ȴ�оƬ��������
+}   
+//����һ������
+//Dst_Addr:������ַ 0~511 for w25x16
+//����һ��ɽ��������ʱ��:150ms
+void SPI_Flash_Erase_Sector(uint32_t Dst_Addr)   
+{   
+	Dst_Addr*=4096;
+	SPI_FLASH_Write_Enable();                  //SET WEL 	 
+	SPI_Flash_Wait_Busy();   
+	SPI_FLASH_CS=0;                            //ʹ������   
+	SPI1_ReadWriteByte(W25X_SectorErase);      //������������ָ�� 
+	SPI1_ReadWriteByte((uint8_t)((Dst_Addr)>>16));  //����24bit��ַ    
+	SPI1_ReadWriteByte((uint8_t)((Dst_Addr)>>8));   
+	SPI1_ReadWriteByte((uint8_t)Dst_Addr);  
+	SPI_FLASH_CS=1;                            //ȡ��Ƭѡ     	      
+  SPI_Flash_Wait_Busy();   				   //�ȴ��������
+}  
+//�ȴ�����
+void SPI_Flash_Wait_Busy(void)   
+{   
+	while ((SPI_Flash_ReadSR()&0x01)==0x01);   // �ȴ�BUSYλ���
+}  
+//�������ģʽ
+void SPI_Flash_PowerDown(void)   
+{ 
+	SPI_FLASH_CS=0;                            //ʹ������   
+	SPI1_ReadWriteByte(W25X_PowerDown);        //���͵�������  
+	SPI_FLASH_CS=1;                            //ȡ��Ƭѡ     	      
+	delay_us(3);                               //�ȴ�TPD  
+}   
+//����
+void SPI_Flash_WAKEUP(void)   
+{  
+	SPI_FLASH_CS=0;                            //ʹ������   
+	SPI1_ReadWriteByte(W25X_ReleasePowerDown);   //  send W25X_PowerDown command 0xAB    
+	SPI_FLASH_CS=1;                            //ȡ��Ƭѡ     	      
+	delay_us(3);                               //�ȴ�TRES1
+}   
+
+
diff --git a/STM32_4路称重_Git提交精简工程/src/HARDWARE/FLASH/flash.h b/STM32_4路称重_Git提交精简工程/src/HARDWARE/FLASH/flash.h
new file mode 100755
index 0000000..aded2df
--- /dev/null
+++ b/STM32_4路称重_Git提交精简工程/src/HARDWARE/FLASH/flash.h
@@ -0,0 +1,81 @@
+#ifndef __FLASH_H
+#define __FLASH_H			    
+#include "stm32f10x.h"
+//////////////////////////////////////////////////////////////////////////////////	 
+//������ֻ��ѧϰʹ�ã�δ���������ɣ��������������κ���;
+//ALIENTEKս��STM32������
+//W25Q64 ����	   
+//����ԭ��@ALIENTEK
+//������̳:www.openedv.com
+//�޸�����:2012/9/9
+//�汾��V1.0
+//��Ȩ���У�����ؾ���
+//Copyright(C) �������������ӿƼ����޹�˾ 2009-2019
+//All rights reserved									  
+//////////////////////////////////////////////////////////////////////////////////
+	  
+//W25Xϵ��/Qϵ��оƬ�б�	   
+//W25Q80 ID  0XEF13
+//W25Q16 ID  0XEF14
+//W25Q32 ID  0XEF15
+//W25Q32 ID  0XEF16	
+#define W25Q80 	0XEF13 	
+#define W25Q16 	0XEF14
+#define W25Q32 	0XEF15
+#define W25Q64 	0XEF16
+
+extern u16 SPI_FLASH_TYPE;//��������ʹ�õ�flashоƬ�ͺ�
+
+#define	SPI_FLASH_CS PEout(7)  //ѡ��FLASH	
+				 
+////////////////////////////////////////////////////////////////////////////
+ 
+//ָ���
+#define W25X_WriteEnable			0x06 
+#define W25X_WriteDisable			0x04 
+#define W25X_ReadStatusReg		0x05 
+#define W25X_WriteStatusReg		0x01 
+#define W25X_ReadData					0x03 
+#define W25X_FastReadData			0x0B 
+#define W25X_FastReadDual			0x3B 
+#define W25X_PageProgram			0x02 
+#define W25X_BlockErase				0xD8 
+#define W25X_SectorErase			0x20 
+#define W25X_ChipErase				0xC7 
+#define W25X_PowerDown				0xB9 
+#define W25X_ReleasePowerDown	0xAB 
+#define W25X_DeviceID					0xAB 
+#define W25X_ManufactDeviceID	0x90 
+#define W25X_JedecDeviceID		0x9F 
+
+void SPI_Flash_Init(void);
+u16  SPI_Flash_ReadID(void);  	    //��ȡFLASH ID
+u8	 SPI_Flash_ReadSR(void);        //��ȡ״̬�Ĵ��� 
+void SPI_FLASH_Write_SR(u8 sr);  	//д״̬�Ĵ���
+void SPI_FLASH_Write_Enable(void);  //дʹ�� 
+void SPI_FLASH_Write_Disable(void);	//д����
+void SPI_Flash_Write_NoCheck(u8* pBuffer,u32 WriteAddr,u16 NumByteToWrite);
+void SPI_Flash_Read(u8* pBuffer,u32 ReadAddr,u16 NumByteToRead);   //��ȡflash
+void SPI_Flash_Write(u8* pBuffer,u32 WriteAddr,u16 NumByteToWrite);//д��flash
+void SPI_Flash_Erase_Chip(void);    	  //��Ƭ����
+void SPI_Flash_Erase_Sector(u32 Dst_Addr);//��������
+void SPI_Flash_Wait_Busy(void);           //�ȴ�����
+void SPI_Flash_PowerDown(void);           //�������ģʽ
+void SPI_Flash_WAKEUP(void);			  //����
+#endif
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
diff --git a/STM32_4路称重_Git提交精简工程/src/HARDWARE/GPS/gps.c b/STM32_4路称重_Git提交精简工程/src/HARDWARE/GPS/gps.c
new file mode 100755
index 0000000..89bfb27
--- /dev/null
+++ b/STM32_4路称重_Git提交精简工程/src/HARDWARE/GPS/gps.c
@@ -0,0 +1,265 @@
+/*************************** (C) COPYRIGHT 2017 CXHY ****************************
+ * �ļ���  ��gps.c
+ * ��  ��  ��GPS��������     
+ * ��  ��  ��V1.0
+ * ��  ��  ��XuZhongPing
+ * ��  ��  ��2017/03/05 
+*********************************************************************************/
+#include "gps.h" 
+#include "delay.h" 							   
+#include "usart4.h" 								   
+#include "stdio.h"	 
+#include "stdarg.h"	 
+#include "string.h"	 
+#include "math.h"
+
+nmea_msg gpsx; 											//GPS��Ϣ
+__align(4) u8 dtbuf[50];   					//��ӡ������
+      
+/*
+***********************************************************************
+*	�� �� ��: NMEA_Comma_Pos
+*	����˵��: ��buf����õ���cx���������ڵ�λ��
+*	��    ��: buf,���ݻ���
+*						cx,�ڼ����������ڵ�λ��
+*	�� �� ֵ: 0~0XFE,������������λ�õ�ƫ��
+*						0XFF,���������ڵ�cx������		
+***********************************************************************
+*/					  
+u8 NMEA_Comma_Pos(u8 *buf, u8 cx)
+{	 		    
+	u8 *p = buf;
+	while(cx)
+	{		 
+		if((*buf == '*') || (*buf < ' ') || (*buf > 'z')) return 0XFF;	//����'*'���߷Ƿ��ַ�,�򲻴��ڵ�cx������
+		if(*buf == ',') cx--;
+		buf++;
+	}
+	return buf - p;	 
+}
+
+/*
+***********************************************************************
+*	�� �� ��: NMEA_Pow
+*	����˵��: m^n����
+*	��    ��: m,����
+*						n,ָ��
+*	�� �� ֵ: �����Ľ��
+***********************************************************************
+*/	
+u32 NMEA_Pow(u8 m, u8 n)
+{
+	u32 result = 1;	 
+	while(n--)result *= m;    
+	return result;
+}
+
+/*
+***********************************************************************
+*	�� �� ��: NMEA_Str2num
+*	����˵��: strת��Ϊ����,��','����'*'����
+*	��    ��: buf:���ִ洢��
+*						dx:С����λ��,���ظ����ú���
+*	�� �� ֵ: ת����Ľ��
+***********************************************************************
+*/
+int NMEA_Str2num(u8 *buf, u8 *dx)
+{
+	u8 *p = buf;
+	u32 ires = 0, fres = 0;
+	u8 ilen = 0, flen = 0, i;
+	u8 mask = 0;
+	int res;
+	while(1) //�õ�������С���ĳ���
+	{
+		if(*p == '-'){mask |= 0X02; p++;}//�Ǹ���
+		if(*p == ',' || (*p == '*'))break;//����������
+		if(*p == '.'){mask |= 0X01; p++;}//����С������
+		else if((*p > '9') || (*p < '0'))	//�зǷ��ַ�
+		{	
+			ilen = 0;
+			flen = 0;
+			break;
+		}	
+		if(mask & 0X01)flen++;
+		else ilen++;
+		p++;
+	}
+	if(mask & 0X02)buf++;			//ȥ������
+	for(i = 0; i<ilen; i++)		//�õ�������������
+	{  
+		ires += NMEA_Pow(10, ilen-1-i) * (buf[i]-'0');
+	}
+	if(flen > 5)flen = 5;			//���ȡ5λС��
+	*dx = flen;	 							//С����λ��
+	for(i = 0; i<flen; i++)		//�õ�С����������
+	{  
+		fres += NMEA_Pow(10, flen-1-i) * (buf[ilen+1+i] - '0');
+	} 
+	res = ires * NMEA_Pow(10, flen) + fres;
+	if(mask & 0X02)res=-res;		   
+	return res;
+}	
+
+/*
+***********************************************************************
+*	�� �� ��: gps_control
+*	����˵��: ����GPGGA��Ϣ��GPS��λ��Ϣ��
+*	��    ��: *gpsx:nmea��Ϣ�ṹ�壨�����ȫ�ֱ�����
+*						*buf:���յ���GPS���ݻ������׵�ַ
+*	�� �� ֵ: ��
+***********************************************************************
+*/
+void gps_control(void)
+{
+ 
+ GPIO_InitTypeDef  GPIO_InitStructure;
+ 	
+ RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOA , ENABLE);	 	//ʹ��PB�˿�ʱ��
+	
+ GPIO_InitStructure.GPIO_Pin = GPIO_Pin_4;				 				
+ GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP; 		 		//�������
+ GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;		 		//IO���ٶ�Ϊ50MHz
+ GPIO_Init(GPIOA, &GPIO_InitStructure);					 					//�����趨������ʼ��
+	
+ GPIO_SetBits(GPIOA, GPIO_Pin_4);
+}
+
+void open_gps(void)
+{
+	 GPIO_SetBits(GPIOA, GPIO_Pin_4);
+}
+
+void close_gps(void)
+{
+	 GPIO_ResetBits(GPIOA, GPIO_Pin_4);
+}
+
+
+  							 
+/*
+***********************************************************************
+*	�� �� ��: NMEA_GPGGA_Analysis
+*	����˵��: ����GPGGA��Ϣ��GPS��λ��Ϣ��
+*	��    ��: *gpsx:nmea��Ϣ�ṹ�壨�����ȫ�ֱ�����
+*						*buf:���յ���GPS���ݻ������׵�ַ
+*	�� �� ֵ: ��
+***********************************************************************
+*/
+void NMEA_GPGGA_Analysis(nmea_msg *gpsx, u8 *buf)
+{
+	u8 *p1, dx;			 
+	u8 posx;    
+	p1 = (u8*)strstr((const char *)buf, "$GPGGA");
+	
+	posx = NMEA_Comma_Pos(p1, 6);								//�õ�GPS״̬
+	if(posx != 0XFF)gpsx->gpssta = NMEA_Str2num(p1+posx, &dx);	
+	
+	posx = NMEA_Comma_Pos(p1, 7);								//�õ����ڶ�λ��������
+	if(posx != 0XFF)gpsx->posslnum = NMEA_Str2num(p1+posx, &dx); 
+	
+	posx = NMEA_Comma_Pos(p1, 9);								//�õ����θ߶�
+	if(posx != 0XFF)gpsx->altitude = NMEA_Str2num(p1+posx, &dx);  
+	gpsx->altitude *= 1000;
+}
+
+
+/*
+***********************************************************************
+*	�� �� ��: NMEA_GPRMC_Analysis
+*	����˵��: ����GPRMC��Ϣ��GPS�Ƽ���λ��Ϣ��
+*	��    ��: *gpsx:nmea��Ϣ�ṹ�壨�����ȫ�ֱ�����
+*						*buf:���յ���GPS���ݻ������׵�ַ
+*	�� �� ֵ: ��
+***********************************************************************
+*/
+void NMEA_GPRMC_Analysis(nmea_msg *gpsx, u8 *buf)
+{
+	u8 *p1,dx;			 
+	u8 posx;     
+	u32 temp;	   
+	float rs;  
+	p1 = (u8*)strstr((const char *)buf, "$GPRMC");
+	posx = NMEA_Comma_Pos(p1, 1);								//�õ�UTCʱ��
+	if(posx != 0XFF)
+	{
+		temp = NMEA_Str2num(p1+posx, &dx)/NMEA_Pow(10,dx);	 	//�õ�UTCʱ��,ȥ��ms
+		gpsx->utc.hour = temp/10000;
+		gpsx->utc.min = (temp/100)%100;
+		gpsx->utc.sec = temp%100;	 	 
+	}
+	
+	posx = NMEA_Comma_Pos(p1,3);								//�õ�γ��
+	if(posx != 0XFF)
+	{
+		temp = NMEA_Str2num(p1+posx, &dx);		 	 
+		gpsx->latitude = temp/NMEA_Pow(10, dx+2);	//�õ���
+		rs = temp%NMEA_Pow(10, dx+2);							//�õ�'		 
+		gpsx->latitude = gpsx->latitude*NMEA_Pow(10, 5)+(rs*NMEA_Pow(10, 5-dx))/60;//ת��Ϊ�� 
+		gpsx->latitude /= 10;			//��С10�����ڴ��䣬���շŴ�10000��
+	}
+	
+	posx = NMEA_Comma_Pos(p1, 4);								//��γ���Ǳ�γ 
+	if(posx != 0XFF)gpsx->nshemi = *(p1 + posx);
+	
+ 	posx = NMEA_Comma_Pos(p1, 5);								//�õ�����
+	if(posx != 0XFF)
+	{												  
+		temp = NMEA_Str2num(p1+posx, &dx);		 	 
+		gpsx->longitude = temp/NMEA_Pow(10, dx+2);	//�õ���
+		rs = temp%NMEA_Pow(10, dx+2);								//�õ�'		 
+		gpsx->longitude = gpsx->longitude * NMEA_Pow(10, 5)+(rs * NMEA_Pow(10, 5-dx))/60;//ת��Ϊ�� 
+		gpsx->longitude /= 10;		//��С10�����ڴ��䣬���շŴ�10000��
+	}
+	
+	posx = NMEA_Comma_Pos(p1, 6);									//������������
+	if(posx != 0XFF)gpsx->ewhemi = *(p1 + posx);
+	
+	posx = NMEA_Comma_Pos(p1, 9);									//�õ�UTC����
+	if(posx != 0XFF)
+	{
+		temp = NMEA_Str2num(p1+posx, &dx);		 			//�õ�UTC����
+		gpsx->utc.date = temp/10000;
+		gpsx->utc.month = (temp/100)%100;
+		gpsx->utc.year = 2000 + temp%100;	 	 
+	} 
+}
+  
+/*
+***********************************************************************
+*	�� �� ��: GPS_Analysis
+*	����˵��: ��ȡNMEA-0183��Ϣ
+*	��    ��: *gpsx:nmea��Ϣ�ṹ�壨�����ȫ�ֱ�����
+*						*buf:���յ���GPS���ݻ������׵�ַ
+*	�� �� ֵ: ��
+***********************************************************************
+*/
+void GPS_Analysis(nmea_msg *gpsx, u8 *buf)
+{
+	NMEA_GPGGA_Analysis(gpsx, buf);	//GPGGA���� 	
+	NMEA_GPRMC_Analysis(gpsx, buf);	//GPRMC����
+}
+
+void PrinterfGpsInfo(void)
+{
+	float tp;		   
+	
+	printf("\r\n��λ״̬��%d\r\n", gpsx.gpssta);
+	if(gpsx.gpssta == 1)
+	{
+		printf("\r\n�Ѷ�λ\r\n");
+		
+		tp = gpsx.longitude;	   
+		printf("\r\n���ȣ�%.4f %1c\r\n", tp/=10000, gpsx.ewhemi);	//�õ������ַ���
+			 
+		tp = gpsx.latitude;	   
+		printf("\r\nγ�ȣ�%.4f %1c\r\n", tp/=10000, gpsx.nshemi);		//�õ�γ���ַ���
+		
+		tp = gpsx.altitude;	   
+		printf("\r\n�߶ȣ�%.4f\r\n", tp/=10000);		//�õ�γ���ַ���
+	}else{
+		printf("\r\nδ��λ\r\n");
+	}
+}
+
+/******************** (C) COPYRIGHT 2014 CHY *****END OF FILE*******************/
diff --git a/STM32_4路称重_Git提交精简工程/src/HARDWARE/GPS/gps.h b/STM32_4路称重_Git提交精简工程/src/HARDWARE/GPS/gps.h
new file mode 100755
index 0000000..4714cc0
--- /dev/null
+++ b/STM32_4路称重_Git提交精简工程/src/HARDWARE/GPS/gps.h
@@ -0,0 +1,54 @@
+/*************************** (C) COPYRIGHT 2017 CXHY ****************************
+ * �ļ���  ��gps.h
+ * ��  ��  ��GPSͷ�ļ���������     
+ * ��  ��  ��V1.0
+ * ��  ��  ��XuZhongPing
+ * ��  ��  ��2013/11/21 
+*********************************************************************************/
+#ifndef __GPS_H
+#define __GPS_H	 
+
+#include "stm32f10x.h" 
+ 									   						    
+//GPS NMEA-0183Э����Ҫ�����ṹ�嶨�� 
+
+//UTCʱ����Ϣ
+typedef struct  
+{										    
+ 	uint16_t 	year;	//���
+	uint8_t 	month;	//�·�
+	uint8_t 	date;	//����
+	uint8_t 	hour; 	//Сʱ
+	uint8_t 	min; 	//����
+	uint8_t		sec; 	//����
+}nmea_utc_time;   
+	   
+//NMEA 0183 Э����������ݴ�Žṹ��
+typedef struct  
+{										    
+	nmea_utc_time utc;				//UTCʱ��
+	uint32_t 	latitude;				//γ�� ������10000��,ʵ��Ҫ����10000
+	uint8_t 	nshemi;					//��γ/��γ,N:��γ;S:��γ				  
+	uint32_t	longitude;			//���� ������10000��,ʵ��Ҫ����10000
+	uint8_t 	ewhemi;					//����/����,E:����;W:����
+	uint8_t		gpssta;					//GPS״̬:0,δ��λ;1,�ǲ�ֶ�λ;2,��ֶ�λ;6,���ڹ���
+	uint8_t		posslnum;				//���ڶ�λ����������,0~12
+
+	uint32_t 	altitude;			 	//���θ߶�,�Ŵ���10000��,ʵ�ʳ���10000.��λ:0.1m	  
+}nmea_msg; 
+
+extern nmea_msg gpsx;
+
+void GPS_Analysis(nmea_msg *gpsx,uint8_t *buf);
+void NMEA_GPGGA_Analysis(nmea_msg *gpsx,uint8_t *buf);
+void NMEA_GPRMC_Analysis(nmea_msg *gpsx,uint8_t *buf);
+
+void PrinterfGpsInfo(void);		//��ʾGPS��λ��Ϣ
+
+void gps_control(void);
+void open_gps(void);
+void close_gps(void);
+
+#endif  
+
+/******************** (C) COPYRIGHT 2017 CXHY *****END OF FILE*******************/ 
diff --git a/STM32_4路称重_Git提交精简工程/src/HARDWARE/GSM/at_proc.c b/STM32_4路称重_Git提交精简工程/src/HARDWARE/GSM/at_proc.c
new file mode 100755
index 0000000..d6870b2
--- /dev/null
+++ b/STM32_4路称重_Git提交精简工程/src/HARDWARE/GSM/at_proc.c
@@ -0,0 +1,544 @@
+#include "at_proc.h"
+#include "gsm_uart.h"
+#include "gsm_uart_conf.h"
+#include "my_math.h"
+#include "ec200x.h"
+#include "data_typedef.h"
+
+char command_CIPSEND[16];
+	
+AT_CMD_PARAM at_cmd_table[]={
+	{AT_CMD_AT_NO, 						"AT", 																"OK",								"ERROR",					AT_CMD_UNKNOWN},
+	{AT_CMD_ATE0_NO, 					"ATE0",																"OK",								"ERROR",					AT_CMD_UNKNOWN},
+	{AT_CMD_CGSN_NO, 					"AT+CGSN", 														"OK", 							"ERROR",					AT_CMD_UNKNOWN},
+	{AT_CMD_CPIN_NO, 					"AT+CPIN?",														"+CPIN: READY", 		"ERROR", 					AT_CMD_UNKNOWN},
+	{AT_CMD_ICCID_NO, 				"AT+QCCID",														"+QCCID:", 					"ERROR", 					AT_CMD_UNKNOWN},
+	{AT_CMD_CSQ_NO, 					"AT+CSQ",															"+CSQ:", 						"ERROR", 					AT_CMD_UNKNOWN},
+	{AT_CMD_CREG_NO, 					"AT+CREG?", 													"+CREG: 0,1", 			"ERROR", 					AT_CMD_UNKNOWN},
+	{AT_CMD_CGREG_NO, 				"AT+CGREG?", 													"+CGREG: 0,1", 			"ERROR",					AT_CMD_UNKNOWN},
+	{AT_CMD_COPS_NO, 					"AT+COPS?", 													"OK", 							"ERROR",					AT_CMD_UNKNOWN},
+	{AT_CMD_QICSGP_NO, 				"AT+QICSGP=1,1,\"UNINET\","","",1", 	"OK", 							"ERROR", 					AT_CMD_UNKNOWN},
+	{AT_CMD_QIACT_NO,					"AT+QIACT=1",													"OK",								"ERROR",					AT_CMD_UNKNOWN},
+	{AT_CMD_QIDEACT_NO,				"AT+QIDEACT=1",												"OK",								"ERROR",					AT_CMD_UNKNOWN},
+	{AT_CMD_CHECK_QIACT_NO,		"AT+QIACT?",													"OK",								"ERROR",					AT_CMD_UNKNOWN},
+	{AT_CMD_QIOPEN,						TCP_IP_COM,														"+QIOPEN: 0,0",			"CONNECT FAIL",		AT_CMD_UNKNOWN},
+	{AT_CMD_QICLOSE_NO,				"AT+QICLOSE=0",												"OK",								"SEND FAIL",			AT_CMD_UNKNOWN},
+	{AT_CMD_QISEND,						"AT+QISEND=0,4",											">",								"SEND OK",				AT_CMD_UNKNOWN},
+	{AT_CMD_CHECK_QISEND_NO,	"AT+QISEND=0,0",											"+QISEND:",					"ERROR",					AT_CMD_UNKNOWN},
+	{AT_CMD_QIRD_NO,					"AT+QIRD=0,1500",											"+QIRD:",						"ERROR",					AT_CMD_UNKNOWN},
+	{AT_CMD_QNTP_NO,					"AT+QNTP",														"+QNTP:",						"ERROR",					AT_CMD_UNKNOWN},
+	{AT_CMD_CCLK_NO,					"AT+CCLK?",														"+CCLK:",						"+CME ERROR",			AT_CMD_UNKNOWN},
+};
+
+#define AT_RX_BUFFER  100
+ 
+uint8_t rx_buffer[AT_RX_BUFFER];
+uint8_t sendAtCmdNo=0;
+
+uint8_t networkIsReg=0;
+uint8_t receiveDataReady = 0;
+uint8_t receiveDataLen = 0;
+
+#define AT_COMMON_ERROR_STRING   "+CME ERROR:"
+
+
+
+void show_buf(uint8_t num[], uint8_t n)
+{
+    uint8_t i;
+		printf("\r\n");
+    for(i=0; i<n; i++)
+		{
+      printf("%02X ",num[i]);
+		}
+		printf("\r\n");
+}
+
+/*
+***********************************************************************
+*	�� �� ��: mem_cmp
+*	����˵��: �ַ����Ƚ�
+*	��    ��: src->ԭ�ַ���
+*           dst->Ŀ���ַ���
+*           len->�ַ����ĳ���
+*	�� �� ֵ: 0->��ͬ,1����ͬ
+***********************************************************************
+*/
+static uint8_t mem_cmp(uint8_t *src, uint8_t *dst, uint8_t len)
+{
+	uint8_t i = 0, ret = 0;
+  
+  while(i<len)
+  {
+    if(src[i] == 0 || dst[i] == 0 ||  src[i] != dst[i])
+		{
+			ret = 1;
+			break;
+		}  
+		i++;
+  }
+  return ret;
+}
+
+/*
+***********************************************************************
+*	�� �� ��: str_len
+*	����˵��: ȡ���ַ�������
+*	��    ��: string->��������ַ���
+*	�� �� ֵ: �ַ�������
+***********************************************************************
+*/
+static uint8_t str_len(uint8_t* string)
+{
+   uint8_t i=0;
+
+   while(string[i] != 0) 	i++;
+
+   return i;
+}
+
+/*
+***********************************************************************
+*	�� �� ��: GSM_SendAtCmd
+*	����˵��: GSMģ�鷢��ATָ��
+*	��    ��: cmd->���͵������ַ���
+*           atCmdNo->ATָ����
+*	�� �� ֵ: 0->���ͳɹ�(�õ����ڴ���Ӧ����)
+*             1->����ʧ��
+***********************************************************************
+*/
+void GSM_SendAtCmd(char *cmd, uint8_t atCmdNo)
+{
+	sendAtCmdNo = atCmdNo;
+	at_cmd_table[sendAtCmdNo-1].result = AT_CMD_UNKNOWN;
+	GSM_GPRS_printf("%s\r\n", cmd);				//��������
+}
+
+/*
+***********************************************************************
+*	�� �� ��: getCommand_CIPSEND
+*	����˵��: ���ݷ��͵����ݳ����Զ����ɶ�Ӧ��AT+CIPSEND=<?>����
+*	��    �Σ�msg
+*	�� �� ֵ: ��
+***********************************************************************
+*/
+void getCommand_CIPSEND(uint16_t len)
+{
+	char lenNum[4];
+	
+	sprintf((char*)command_CIPSEND, "AT+CIPSEND=");
+	sprintf((char*)lenNum, "%d", len);
+	strcat((char*)command_CIPSEND, lenNum);
+}
+
+/*
+***********************************************************************
+*	�� �� ��: IMEI_TO_HEX
+*	����˵��: ��IMEI��ת����HEX
+*	��    �Σ������ַ�����IMEI��	          
+*	�� �� ֵ: 
+***********************************************************************
+*/
+void IMEI_TO_HEX(char *pStrData)
+{
+	uint8_t i;
+	uint64_t imeiNum = 0;
+	uint32_t imeiNumH = 0;
+	uint32_t imeiNumL = 0;
+
+	for(i = 0; i < 15; i++){
+		imeiNum += ((*pStrData++) - 0x30) * Pow(10, 14-i);
+	}
+	imeiNumH = imeiNum/4294967296;
+	imeiNumL = (uint32_t)imeiNum;
+	
+// 	printf("\r\n%x \r\n", imeiNumH);
+// 	printf("\r\n%x \r\n", imeiNumL);
+	
+	gsm_msg.IMEI_HEX[0] = imeiNumH >> 24;
+	gsm_msg.IMEI_HEX[1] = imeiNumH >> 16;
+	gsm_msg.IMEI_HEX[2] = imeiNumH >> 8;
+	gsm_msg.IMEI_HEX[3] = imeiNumH;
+	
+	gsm_msg.IMEI_HEX[4] = imeiNumL >> 24;
+	gsm_msg.IMEI_HEX[5] = imeiNumL >> 16;
+	gsm_msg.IMEI_HEX[6] = imeiNumL >> 8;
+	gsm_msg.IMEI_HEX[7] = imeiNumL;
+	
+// 	for(i = 0; i < 8; i++){
+// 		printf("%x ", gsm_msg.IMEI_HEX[i]);
+// 	}
+}
+
+
+void AT_Protocol(uint8_t* pCdmStr, uint8_t length)
+{
+  uint8_t i = 0;
+	char *p;
+  uint8_t *pSuccStr;							//ATָ������ɹ���Ӧ���ַ���;
+  uint8_t succStrLen;							
+	
+	uint8_t *pFailedStr;						//ATָ�����ʧ�ܵ�Ӧ���ַ���;
+  uint8_t failedStrLen;
+	
+	if(length == 2) return; 				//���У�������
+	
+	if(sendAtCmdNo >= CMD_TABLE_LENGTH) return; 				//�ж��Ƿ���ǰ�淢�͹�at��Ҫ������
+
+  if(!((pCdmStr[length-2] == '\r') && (pCdmStr[length-1] == '\n')))		//���ǻس����У�"\r\n"����β
+	{
+		if(!((sendAtCmdNo == AT_CMD_QISEND) && (GPRS_RX_BUF[length - 1] == '>'))) return;		//����IPSENDָ���Ӧ��>��
+	}
+		
+	i = 0; 
+  while(*pCdmStr == '\0') 	//���˵�ǰ��Ŀո�
+	{
+		pCdmStr = pCdmStr++;
+		i++;
+		if(i >= length) break;
+	}
+
+  pSuccStr = at_cmd_table[sendAtCmdNo-1].success;
+  succStrLen = str_len(pSuccStr); 
+	
+	pFailedStr = at_cmd_table[sendAtCmdNo-1].failed;
+  failedStrLen = str_len(pFailedStr); 
+	
+	if((char*)strstr((const char*)pCdmStr, "+QIURC") != NULL)			//URC ATָ��
+	{
+		if((char*)strstr((const char*)pCdmStr, "recv") != NULL)			//���ݽ���URC
+		{
+			if(mem_cmp(pCdmStr, (uint8_t*)RECEIVE_SERVER_DATA, strlen(RECEIVE_SERVER_DATA)) == 0)
+			{
+				p = (char*)strstr((const char*)pCdmStr, ",");
+				p = (char*)strstr((const char*)p+1, ",");
+				recDataLen = atoi(p+1);
+				GSM_ReceiveType = 1;
+// 				printf("\r\n��������URC\r\n");
+// 				printf("\r\nlen=%d\r\n", recDataLen);
+			}
+		}else if((char*)strstr((const char*)pCdmStr, "closed") != NULL){					//���ӶϿ�URC
+			connectionClosedMark = 1;
+// 			printf("\r\n���ӶϿ�URC��\r\n");
+		}else if((char*)strstr((const char*)pCdmStr, "incoming full") != NULL){		//�ͻ�����������URC
+			printf("\r\n��������URC��\r\n");
+		}else if((char*)strstr((const char*)pCdmStr, "ncoming") != NULL){					//�ͻ�������URC
+			printf("\r\n�ͻ�������URC��\r\n");
+		}else if((char*)strstr((const char*)pCdmStr, "pdpdeact") != NULL){				//PDPȥ����URC
+			printf("\r\nPDPȥ����URC��\r\n");
+		}else{}
+	}else{																												//����ATָ��
+		switch(sendAtCmdNo)
+		{
+			case AT_CMD_AT_NO:		//AT
+				if(mem_cmp(pCdmStr, (uint8_t*)AT_CMD_AT_AT, strlen(AT_CMD_AT_AT)) == 0)
+				{
+					at_cmd_table[sendAtCmdNo-1].result = AT_CMD_SUCCESS;
+	// 				printf("\r\nat\r\n");
+					sendAtCmdNo = 0;
+				}else if(mem_cmp(pCdmStr, (uint8_t*)AT_CMD_AT_OK, strlen(AT_CMD_AT_OK)) == 0){
+					at_cmd_table[sendAtCmdNo-1].result = AT_CMD_SUCCESS;
+	// 				printf("\r\nok\r\n");
+					sendAtCmdNo = 0;
+				}else if(mem_cmp(pCdmStr, (uint8_t*)AT_COMMON_ERROR_STRING, strlen(AT_CMD_AT_ERROR)) == 0){
+					at_cmd_table[sendAtCmdNo-1].result = AT_CMD_FAILED;					 	 
+				}else{}
+				break;
+				
+			case AT_CMD_ATE0_NO:		//�رջ���
+				if(mem_cmp(pSuccStr, pCdmStr, succStrLen) == 0)
+				{
+					at_cmd_table[sendAtCmdNo-1].result = AT_CMD_SUCCESS;
+					sendAtCmdNo = 0;
+				}else if(mem_cmp(pCdmStr, (uint8_t*)AT_COMMON_ERROR_STRING, strlen(AT_CMD_AT_ERROR)) == 0){
+					at_cmd_table[sendAtCmdNo-1].result = AT_CMD_FAILED;					 	 
+				}else{}
+				break;
+			
+			case AT_CMD_CGSN_NO:	 //AT+CGSN ��ȡIMEI��
+				if(length == 17)
+				{
+					at_cmd_table[sendAtCmdNo-1].result = AT_CMD_SUCCESS; 				//���õ�ǰ��ATָ���������ɹ�
+					sendAtCmdNo = 0;																						//�������ATָ����
+					memcpy(gsm_msg.IMEI, pCdmStr, 15);
+					gsm_msg.IMEI[15] = '\0';																		
+					IMEI_TO_HEX(gsm_msg.IMEI);																	//���ַ�����IMEI��ת����HEX��ʽΪ���洫��
+				}
+				break;
+			
+			case AT_CMD_CPIN_NO:		//AT+CPIN?  ��ѯSIM��״̬
+				if(mem_cmp(pSuccStr, pCdmStr, succStrLen) == 0)
+				{
+					at_cmd_table[sendAtCmdNo-1].result = AT_CMD_SUCCESS;
+					sendAtCmdNo = 0;
+				}else if(mem_cmp(pCdmStr, (uint8_t*)AT_COMMON_ERROR_STRING, strlen(AT_CMD_AT_ERROR)) == 0){
+					at_cmd_table[sendAtCmdNo-1].result = AT_CMD_FAILED;					 	 
+				}else{}
+				break;
+				
+			case AT_CMD_ICCID_NO:		//AT+QCCID  ��ѯSIM����ICCID��
+				if(mem_cmp(pSuccStr, pCdmStr, succStrLen) == 0)
+				{
+					memcpy(gsm_msg.ICCID, pCdmStr+8, 20);
+					gsm_msg.ICCID[20] = '\0';		
+	// 				show_buf((uint8_t*)gsm_msg.ICCID, 20);
+					at_cmd_table[sendAtCmdNo-1].result = AT_CMD_SUCCESS;
+					sendAtCmdNo = 0;
+				}else if(mem_cmp(pCdmStr, (uint8_t*)AT_COMMON_ERROR_STRING, strlen(AT_CMD_AT_ERROR)) == 0){
+					at_cmd_table[sendAtCmdNo-1].result = AT_CMD_FAILED;					 	 
+				}else{}
+				break;
+				
+			case AT_CMD_CSQ_NO:		//AT+CSQ  ��ѯ�����ź�ǿ��
+	// 			printf("\r\ncsq = %s\r\n", pCdmStr);
+				if(mem_cmp(pSuccStr, pCdmStr, succStrLen) == 0)
+				{
+					at_cmd_table[sendAtCmdNo-1].result = AT_CMD_SUCCESS;
+					sendAtCmdNo = 0;
+					signal = atoi((const char *)(pCdmStr+6));
+	// 				printf("\r\nrssi = %d\r\n", signal);
+				}else if(mem_cmp(pCdmStr, (uint8_t*)AT_COMMON_ERROR_STRING, strlen(AT_CMD_AT_ERROR)) == 0){
+					at_cmd_table[sendAtCmdNo-1].result = AT_CMD_FAILED;					 	 
+				}else{}
+				break;
+			
+			case AT_CMD_CREG_NO:		//AT+CREG? ��ѯ����ע��״̬ 
+				if(mem_cmp(pSuccStr, pCdmStr, succStrLen) == 0)														//ע��ģ���������
+				{
+					at_cmd_table[sendAtCmdNo-1].result = AT_CMD_SUCCESS;
+					sendAtCmdNo = 0;
+				}else if(mem_cmp((uint8_t*)AT_CMD_AT_CREG, pCdmStr, succStrLen) == 0){		//ע��ģ�������
+					at_cmd_table[sendAtCmdNo-1].result = AT_CMD_SUCCESS;
+					sendAtCmdNo = 0;
+				}else if(mem_cmp(pCdmStr, (uint8_t*)AT_COMMON_ERROR_STRING, strlen(AT_CMD_AT_ERROR)) == 0){
+					at_cmd_table[sendAtCmdNo-1].result = AT_CMD_FAILED;					 	 
+				}else{}
+				break;
+			
+			case AT_CMD_CGREG_NO:		//AT+CGREG? ���GPRS����״̬
+				if(mem_cmp(pSuccStr, pCdmStr, succStrLen) == 0)														//ע��ģ���������
+				{
+					at_cmd_table[sendAtCmdNo-1].result = AT_CMD_SUCCESS;
+					sendAtCmdNo = 0;
+				}else if(mem_cmp((uint8_t*)AT_CMD_AT_CGREG, pCdmStr, succStrLen) == 0){		//ע��ģ�������
+					at_cmd_table[sendAtCmdNo-1].result = AT_CMD_SUCCESS;
+					sendAtCmdNo = 0;
+				}else if(mem_cmp(pCdmStr, (uint8_t*)AT_COMMON_ERROR_STRING, strlen(AT_CMD_AT_ERROR)) == 0){
+					at_cmd_table[sendAtCmdNo-1].result = AT_CMD_FAILED;					 	 
+				}else{}
+				break;
+				
+			case AT_CMD_COPS_NO:	//��ѯ������Ӫ��
+				if((char*)strstr((const char*)pCdmStr, "CHINA MOBILE") != NULL){
+					gsm_msg.OperatorType = 1;
+					memcpy(gsm_msg.Operator, "CHINA MOBILE", strlen("CHINA MOBILE"));
+				}else if((char*)strstr((const char*)pCdmStr, "CHN-UNICOM") != NULL){
+					gsm_msg.OperatorType = 2;
+					memcpy(gsm_msg.Operator, "CHN-UNICOM", strlen("CHN-UNICOM"));
+				}else{
+				}
+				
+				if(mem_cmp(pSuccStr, pCdmStr, succStrLen) == 0)
+				{
+					at_cmd_table[sendAtCmdNo-1].result = AT_CMD_SUCCESS;
+					sendAtCmdNo = 0;
+				}else if(mem_cmp(pFailedStr, pCdmStr, failedStrLen) == 0){
+					at_cmd_table[sendAtCmdNo-1].result = AT_CMD_FAILED;
+				}else if(mem_cmp(pCdmStr, (uint8_t*)AT_COMMON_ERROR_STRING, strlen(AT_CMD_AT_ERROR)) == 0){
+					at_cmd_table[sendAtCmdNo-1].result = AT_CMD_FAILED;					 	 
+				}else{}
+				break;
+			
+			case AT_CMD_QICSGP_NO:	//��ʼ��������APN
+				if(mem_cmp(pSuccStr, pCdmStr, succStrLen) == 0)
+				{
+					at_cmd_table[sendAtCmdNo-1].result = AT_CMD_SUCCESS;
+					sendAtCmdNo = 0;
+				}else if(mem_cmp(pFailedStr, pCdmStr, failedStrLen) == 0){
+					at_cmd_table[sendAtCmdNo-1].result = AT_CMD_FAILED;
+				}else if(mem_cmp(pCdmStr, (uint8_t*)AT_COMMON_ERROR_STRING, strlen(AT_CMD_AT_ERROR)) == 0){
+					at_cmd_table[sendAtCmdNo-1].result = AT_CMD_FAILED;					 	 
+				}else{}
+				break;
+				
+			case AT_CMD_QIDEACT_NO:		//������PDP
+				if(mem_cmp(pSuccStr, pCdmStr, succStrLen) == 0)
+				{
+					at_cmd_table[sendAtCmdNo-1].result = AT_CMD_SUCCESS;
+					sendAtCmdNo = 0;
+				}else if(mem_cmp(pFailedStr, pCdmStr, failedStrLen) == 0){
+					at_cmd_table[sendAtCmdNo-1].result = AT_CMD_FAILED;
+				}else if(mem_cmp(pCdmStr, (uint8_t*)AT_COMMON_ERROR_STRING, strlen(AT_CMD_AT_ERROR)) == 0){
+					at_cmd_table[sendAtCmdNo-1].result = AT_CMD_FAILED;					 	 
+				}else{}
+				break;
+			
+			case AT_CMD_QIACT_NO:	//����������·
+				if(mem_cmp(pSuccStr, pCdmStr, succStrLen) == 0)
+				{
+					at_cmd_table[sendAtCmdNo-1].result = AT_CMD_SUCCESS;
+					sendAtCmdNo = 0;
+				}else if(mem_cmp(pFailedStr, pCdmStr, failedStrLen) == 0){
+					at_cmd_table[sendAtCmdNo-1].result = AT_CMD_FAILED;
+				}else if(mem_cmp(pCdmStr, (uint8_t*)AT_COMMON_ERROR_STRING, strlen(AT_CMD_AT_ERROR)) == 0){
+					at_cmd_table[sendAtCmdNo-1].result = AT_CMD_FAILED;					 	 
+				}else{}
+				break;
+			
+			case AT_CMD_CHECK_QIACT_NO:	 //��ѯ��ǰ������IP
+				if(mem_cmp(pSuccStr, pCdmStr, succStrLen) == 0)
+				{
+					at_cmd_table[sendAtCmdNo-1].result = AT_CMD_SUCCESS;
+					sendAtCmdNo = 0;
+				}else if(mem_cmp(pFailedStr, pCdmStr, failedStrLen) == 0){
+					at_cmd_table[sendAtCmdNo-1].result = AT_CMD_FAILED;
+				}else if(mem_cmp(pCdmStr, (uint8_t*)AT_COMMON_ERROR_STRING, strlen(AT_CMD_AT_ERROR)) == 0){
+					at_cmd_table[sendAtCmdNo-1].result = AT_CMD_FAILED;					 	 
+				}
+				break;
+			
+			case AT_CMD_QIOPEN:	//��ʼ����Զ�˷�����
+				if(mem_cmp(pSuccStr, pCdmStr, succStrLen) == 0)
+				{
+					at_cmd_table[sendAtCmdNo-1].result = AT_CMD_SUCCESS;
+					sendAtCmdNo = 0;
+				}else if(mem_cmp(pFailedStr, pCdmStr, failedStrLen) == 0){
+					at_cmd_table[sendAtCmdNo-1].result = AT_CMD_FAILED;
+					sendAtCmdNo = 0;
+				}else if(mem_cmp(pCdmStr, (uint8_t*)AT_COMMON_ERROR_STRING, strlen(AT_CMD_AT_ERROR)) == 0){
+					at_cmd_table[sendAtCmdNo-1].result = AT_CMD_FAILED;					 	 
+				}
+				break;
+				
+			case AT_CMD_QISEND:		//��������
+				if(mem_cmp((uint8_t*)SEND_STATUS_READY, pCdmStr, 1) == 0)
+				{
+					at_cmd_table[sendAtCmdNo-1].result = AT_CMD_CIPSEND_READY;
+	// 				sendAtCmdNo = 0;
+				}
+				else if(mem_cmp((uint8_t*)SEND_STATUS_SEND_OK, pCdmStr, 7) == 0)
+				{
+					at_cmd_table[sendAtCmdNo-1].result = AT_CMD_CIPSEND_OK;
+					sendAtCmdNo = 0;
+				}
+				else if(mem_cmp((uint8_t*)SEND_STATUS_SEND_FAIL, pCdmStr, 9) == 0)
+				{
+					at_cmd_table[sendAtCmdNo-1].result = AT_CMD_SEND_FAIL;
+					sendAtCmdNo = 0;
+				}
+				else if(mem_cmp((uint8_t*)AT_CMD_AT_ERROR, pCdmStr, 5) == 0)
+				{
+					at_cmd_table[sendAtCmdNo-1].result = AT_CMD_SEND_FAIL;
+					sendAtCmdNo = 0;
+				}
+				else if(mem_cmp((uint8_t*)SEND_STATUS_CLOSED, pCdmStr, 6) == 0)
+				{
+					at_cmd_table[sendAtCmdNo-1].result = TCP_STATUS_CLOSED;
+					sendAtCmdNo = 0;
+				}
+				else if(mem_cmp((uint8_t*)AT_COMMON_ERROR_STRING, pCdmStr, strlen(AT_CMD_AT_ERROR)) == 0){
+					at_cmd_table[sendAtCmdNo-1].result = AT_CMD_SEND_FAIL;
+					sendAtCmdNo = 0;				
+				}else{}
+
+				break;
+				
+			case AT_CMD_CHECK_QISEND_NO:		//��ѯ���͵�����
+				if(mem_cmp(pSuccStr, pCdmStr, succStrLen) == 0)
+				{
+	// 				printf("\r\nbyt=%s\r\n", pCdmStr);
+					p = (char*)strstr((const char*)pCdmStr, ":");
+					if(p != NULL)
+					{
+						total_send_length = atoi((const char *)(p+2));
+	// 					printf("\r\nsendBytes = %d\r\n", total_send_length);
+					}
+					
+					p = (char*)strstr((const char*)pCdmStr, ",");
+					if(p != NULL)
+					{
+						ackedBytes = atoi((const char *)(p+1));
+	// 					printf("\r\nackedBytes = %d\r\n", ackedBytes);
+					}
+					
+					at_cmd_table[sendAtCmdNo-1].result = AT_CMD_SUCCESS;
+					sendAtCmdNo = 0;
+				}else if(mem_cmp(pFailedStr, pCdmStr, failedStrLen) == 0){
+					at_cmd_table[sendAtCmdNo-1].result = AT_CMD_FAILED;
+				}else if(mem_cmp(pCdmStr, (uint8_t*)AT_COMMON_ERROR_STRING, strlen(AT_CMD_AT_ERROR)) == 0){
+					at_cmd_table[sendAtCmdNo-1].result = AT_CMD_FAILED;					 	 
+				}else{}
+				break;
+				
+			case AT_CMD_QIRD_NO:		//��ȡ���յ�������
+				if(mem_cmp(pSuccStr, pCdmStr, succStrLen) == 0)
+				{
+					p = (char*)strstr((const char*)pCdmStr, ": ");
+					receiveDataLen = atoi((p+1));
+	// 				printf("\r\nlen=%d\r\n", receiveDataLen);
+					receiveDataReady = 1;
+				}else if(mem_cmp((uint8_t *)"OK", pCdmStr, 2) == 0){
+					at_cmd_table[sendAtCmdNo-1].result = AT_CMD_SUCCESS;
+					
+					receiveDataReady = 0;
+					sendAtCmdNo = 0;
+				}else if(mem_cmp(pFailedStr, pCdmStr, failedStrLen) == 0){
+					at_cmd_table[sendAtCmdNo-1].result = AT_CMD_FAILED;
+				}else if(mem_cmp(pCdmStr, (uint8_t*)AT_COMMON_ERROR_STRING, strlen(AT_CMD_AT_ERROR)) == 0){
+					at_cmd_table[sendAtCmdNo-1].result = AT_CMD_FAILED;					 	 
+				}else{}
+				break;
+				
+			case AT_CMD_QICLOSE_NO:		//"AT+CIPCLOSE=1" �ر�����
+				if(mem_cmp(pSuccStr, pCdmStr, succStrLen) == 0)
+				{
+					at_cmd_table[sendAtCmdNo-1].result = AT_CMD_SUCCESS;
+					sendAtCmdNo = 0;
+				}else if(mem_cmp(pFailedStr, pCdmStr, failedStrLen) == 0){
+					at_cmd_table[sendAtCmdNo-1].result = AT_CMD_FAILED;
+				}else if(mem_cmp(pCdmStr, (uint8_t*)AT_COMMON_ERROR_STRING, strlen(AT_CMD_AT_ERROR)) == 0){
+					at_cmd_table[sendAtCmdNo-1].result = AT_CMD_FAILED;					 	 
+				}else{}
+				break;
+				
+			case AT_CMD_QNTP_NO:		//ͬ��NTP������ʱ��
+			if(mem_cmp(pSuccStr, pCdmStr, succStrLen) == 0)
+			{
+				at_cmd_table[sendAtCmdNo-1].result = AT_CMD_SUCCESS;
+				sendAtCmdNo = 0;
+			}else if(mem_cmp(pFailedStr, pCdmStr, failedStrLen) == 0){
+				at_cmd_table[sendAtCmdNo-1].result = AT_CMD_FAILED;
+			}else if(mem_cmp(pCdmStr, (uint8_t*)AT_COMMON_ERROR_STRING, strlen(AT_CMD_AT_ERROR)) == 0){
+				at_cmd_table[sendAtCmdNo-1].result = AT_CMD_FAILED;					 	 
+			}else{}
+			break;
+			
+		case AT_CMD_CCLK_NO:		//��ѯʱ��
+// 			printf("\r\nT=%s\r\n", pCdmStr);
+			if(mem_cmp(pSuccStr, pCdmStr, succStrLen) == 0)
+			{
+				at_cmd_table[sendAtCmdNo-1].result = AT_CMD_SUCCESS;
+				sendAtCmdNo = 0;
+				
+				//���صĸ�ʽΪ��+CCLK: "20/08/26,08:42:39+32"
+				p = (char*)strstr((const char*)pCdmStr, "\"");
+				
+				GMT_Time.year = 2000 + (*(p+1)-'0')*10 + (*(p+2)-'0');
+				GMT_Time.month = (*(p+4)-'0')*10 + (*(p+5)-'0');
+				GMT_Time.day = (*(p+7)-'0')*10 + (*(p+8)-'0');
+				
+				GMT_Time.hour = (*(p+10)-'0')*10 + (*(p+11)-'0');
+				GMT_Time.minute = (*(p+13)-'0')*10 + (*(p+14)-'0');
+				GMT_Time.second = (*(p+16)-'0')*10 + (*(p+17)-'0');				
+			}else if(mem_cmp(pCdmStr, (uint8_t*)AT_COMMON_ERROR_STRING, strlen(AT_CMD_AT_ERROR)) == 0){
+				at_cmd_table[sendAtCmdNo-1].result = AT_CMD_FAILED;					 	 
+			}else{}
+			break;
+			
+			default:
+				break;
+		}
+	}
+}
+
+/******************** (C) COPYRIGHT 2017 CXHY *****END OF FILE*******************/ 
diff --git a/STM32_4路称重_Git提交精简工程/src/HARDWARE/GSM/at_proc.h b/STM32_4路称重_Git提交精简工程/src/HARDWARE/GSM/at_proc.h
new file mode 100755
index 0000000..490b870
--- /dev/null
+++ b/STM32_4路称重_Git提交精简工程/src/HARDWARE/GSM/at_proc.h
@@ -0,0 +1,126 @@
+/*************************** (C) COPYRIGHT 2017 CXHY ****************************
+ * �ļ���  ��at_proc.h
+ * ��  ��  ��GSM ATָ�����  
+ * ��  ��  ��V1.0
+ * ��  ��  ��XuZhongPing
+ * ��  ��  ��2017/02/05 
+*********************************************************************************/
+#ifndef  _AT_PROC_H_
+#define  _AT_PROC_H_
+
+#include "stm32f10x.h"
+#include "stdio.h" 
+
+#define AT_CMD_COMMON_ERROR  					"+CME ERROR:"
+
+#define AT_CMD_SEND_OK								"SEND OK"	
+#define AT_CMD_AT_OK									"OK"	
+#define AT_CMD_AT_AT									"AT"
+#define AT_CMD_AT_ATE0								"ATE0\r"
+#define AT_CMD_AT_CREG								"+CREG: 0,5"
+#define AT_CMD_AT_CGREG								"+CGREG: 0,5"
+#define AT_CMD_AT_ERROR								"ERROR"
+
+//GPRS���ݷ��͹���Ӧ���ַ�
+#define SEND_STATUS_READY							">"
+#define SEND_STATUS_SEND_OK						"SEND OK"
+#define SEND_STATUS_SEND_FAIL					"SEND FAIL"
+#define SEND_STATUS_CLOSED						"CLOSED"
+
+//GPRS����״̬
+#define CIPSTATUS_IP_INITIAL					"STATE: IP INITIAL"
+#define CIPSTATUS_IP_START						"STATE: IP START"
+#define CIPSTATUS_IP_CONFIG						"STATE: IP CONFIG"
+#define CIPSTATUS_IP_GPRSACT					"STATE: IP GPRSACT"
+#define CIPSTATUS_IP_STATUS						"STATE: IP STATUS"
+#define CIPSTATUS_TCP_CONNECTING			"STATE: TCP CONNECTING"
+#define CIPSTATUS_CONNECT_OK					"STATE: CONNECT OK"
+#define CIPSTATUS_TCP_CLOSING					"STATE: TCP CLOSING"
+#define CIPSTATUS_TCP_CLOSED					"STATE: TCP CLOSED"
+#define CIPSTATUS_PDP_DEACT						"STATE: PDP DEACT"
+
+//ģ���ϱ�URC
+#define RECEIVE_URC										"+QIURC: "							//ģ���ϱ�URC
+#define RECEIVE_SERVER_DATA						"+QIURC: \"recv\""			//���ݽ���URC
+
+typedef enum
+{
+	AT_CMD_AT_NO = 1,							//AT����ָ��
+  AT_CMD_ATE0_NO,								//��������ָ��
+  AT_CMD_CGSN_NO,								//IMEI�Ų�ѯָ��
+	AT_CMD_CPIN_NO,								//��ѯSIM��״̬
+  AT_CMD_ICCID_NO,							//��ѯSIM����ICCID����
+  AT_CMD_CSQ_NO,								//��ѯ�ź�ǿ��
+  AT_CMD_CREG_NO,								//��ѯ����ע��״̬			
+  AT_CMD_CGREG_NO,							//��ѯGPRS����״̬
+	AT_CMD_COPS_NO,								//��ѯ��Ӫ��
+  AT_CMD_QICSGP_NO,							//����TCP/IP��������
+  AT_CMD_QIACT_NO,							//����PDP����		
+  AT_CMD_QIDEACT_NO,						//������PDP����
+  AT_CMD_CHECK_QIACT_NO,				//��ѯPDP����״̬
+  AT_CMD_QIOPEN,								//����TCP�ͻ�������
+	AT_CMD_QICLOSE_NO,						//�ر�����
+  AT_CMD_QISEND,								//��������
+  AT_CMD_CHECK_QISEND_NO,				//��ѯ���ݷ���״̬
+  AT_CMD_QIRD_NO,								//��ȡ���յ�������
+	AT_CMD_QNTP_NO,								//ͬ��NTP������ʱ��
+	AT_CMD_CCLK_NO,								//��ѯʱ��
+}_AT_CMD_Number;
+
+
+//GPRS���������ģ��Ӧ��Ľ��
+typedef enum
+{    
+  AT_CMD_SUCCESS = 1,  
+	AT_CMD_CIPSEND_READY = 10,
+	AT_CMD_CIPSEND_OK = 11,
+	AT_CMD_SEND_FAIL = 12,
+	TCP_STATUS_CLOSED = 13,
+	
+  AT_CMD_FAILED = 100,
+  AT_CMD_TIMEOUE = 101,
+  AT_CMD_UNKNOWN = 255 
+
+}AT_CMD_RESULT;
+
+//GPRS����״̬
+typedef enum
+{    
+	GPRS_STATUS_IP_INITIAL = 20,
+	GPRS_STATUS_IP_START,
+	GPRS_STATUS_IP_CONFIG,
+	GPRS_STATUS_IP_GPRSACT,
+	GPRS_STATUS_IP_STATUS,
+	GPRS_STATUS_TCP_CONNECTING,
+	GPRS_STATUS_CONNECT_OK,
+	GPRS_STATUS_TCP_CLOSING,
+	GPRS_STATUS_TCP_CLOSED,
+	GPRS_STATUS_PDP_DEACT,
+}AT_CMD_RESULT_GPRS_STATUS;
+
+typedef struct
+{
+	uint8_t cmdNo;
+	uint8_t cmd[64];
+	uint8_t success[15];
+	uint8_t failed[15]; 
+	uint8_t result;
+}AT_CMD_PARAM;
+
+extern uint8_t sendAtCmdNo;
+extern  uint8_t networkIsReg;
+
+extern uint8_t receiveDataReady;
+extern uint8_t receiveDataLen;
+
+#define CMD_TABLE_LENGTH  30
+
+extern AT_CMD_PARAM at_cmd_table[CMD_TABLE_LENGTH];
+
+void GSM_SendAtCmd(char *cmd, uint8_t atCmdNo);
+void getCommand_CIPSEND(uint16_t len);
+void AT_Protocol(uint8_t* pCdmStr, uint8_t length);				//AT����ֵ��������
+
+
+#endif
+/******************** (C) COPYRIGHT 2017 CXHY *****END OF FILE*******************/ 
diff --git a/STM32_4路称重_Git提交精简工程/src/HARDWARE/GSM/ec200x.c b/STM32_4路称重_Git提交精简工程/src/HARDWARE/GSM/ec200x.c
new file mode 100755
index 0000000..849d527
--- /dev/null
+++ b/STM32_4路称重_Git提交精简工程/src/HARDWARE/GSM/ec200x.c
@@ -0,0 +1,1569 @@
+/*************************** (C) COPYRIGHT 2017 CXHY ****************************
+ * �ļ���  ��gsm_gprs.c
+ * ��  ��  ��gsm_gprs��������     
+ * ��  ��  ��V1.0
+ * ��  ��  ��XuZhongPing
+ * ��  ��  ��2017/06/12 
+*********************************************************************************/
+#include "ec200x.h"
+#include "gsm_uart.h"		
+#include "gsm_uart_conf.h"
+#include "delay.h"	
+#include "led.h"   	  	 	 	 	  
+#include "string.h" 
+#include "stdio.h"
+#include "stdlib.h"   
+
+#include "timer.h"
+#include "data_typedef.h"	
+#include "message.h"
+#include "tcp_protocol.h"
+#include "at_proc.h"
+#include "netwer_appcall.h"
+
+
+#define RCC_PeriphClock 	RCC_APB2Periph_GPIOB
+#define GSM_POW_KEY_Port 	GPIOB
+#define GSM_POW_KEY_Pin 	GPIO_Pin_12
+
+uint8_t GSM_isPowerON = 0x00;									//GSMģ���Ƿ��ڿ�����־
+uint8_t ConnectionStatus = OFFLINE;						//����״̬���������ݰ����ͳɹ�����λΪ����״̬��
+uint8_t connectionClosedMark = 0;							//���ӶϿ���־
+
+uint16_t networkConnectionCount = 0;					//�����������Ӵ���
+
+static uint8_t GSM_GPRS_Status = 0x00;				//GSM_GPRS�Ĺ���״̬
+static uint8_t GSM_GPRS_initStatus = 0x00;		//GSMģ�����ʱ�Ĺ�״̬
+
+static uint8_t GSM_GPRS_workingState = 0x00;	//GSMģ��TCP�ͻ��˵������շ���������״̬
+static uint8_t errorStatus = 0x00;						//GSMģ���쳣������״̬
+static uint8_t errorProcessCount = 0;					//����������
+static uint8_t sendFailureCount = 0;					//����ʧ�ܼ���
+static uint8_t seriousError = 0;							//���صĴ���
+
+uint8_t lteLoadCompletedFlag = 0;							//LTEģ�������ɱ�־
+uint8_t lteLoadResetFlag = 0;									//LTEģ����ع��̸�λ
+
+uint8_t lteCreateSocketOkFlag = 0;						//����Socket������ɱ�־
+uint8_t lteCreateSocketResetFlag = 0;					//����Socket���ӹ��̸�λ��־
+
+uint8_t lteHandlerResetFlag = 0;							//�����շ����̸�λ��־
+
+
+/*
+***********************************************************************
+*	�� �� ��: LTE_Init
+*	����˵��: LTEģ���ʼ��
+*	��    ��: ��
+*	�� �� ֵ: ��
+***********************************************************************
+*/
+void LTE_Init(void)
+{
+	GPIO_InitTypeDef  GPIO_InitStructure;
+ 	
+ 	RCC_APB2PeriphClockCmd(RCC_PeriphClock, ENABLE);	 			//ʹ��PB�˿�ʱ��
+	
+	//GSM���ػ��������ų�ʼ������
+ 	GPIO_InitStructure.GPIO_Pin = GSM_POW_KEY_Pin;	 				//�������˿�����
+ 	GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP; 		 		//�������
+ 	GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;				
+ 	GPIO_Init(GSM_POW_KEY_Port, &GPIO_InitStructure);				
+	GPIO_ResetBits(GSM_POW_KEY_Port, GSM_POW_KEY_Pin);			//Ĭ������ͣ��൱�ڿ���������û�а���״̬
+	
+	GSM_GPRS_Uart_Init();
+	gsm_msg.Running = 0;
+}
+
+/*
+***********************************************************************
+*	�� �� ��: LTE_StatusReset
+*	����˵��: LTEģ�������״̬��λ
+*	��    �Σ���
+*	�� �� ֵ: ��
+***********************************************************************
+*/
+void LTE_StatusReset(void)
+{
+	lteLoadResetFlag = 1;
+	lteCreateSocketResetFlag = 1;
+	GSM_GPRS_Status = 0x00;
+	errorStatus = 0x00;									//GSMģ���쳣����ʱ��״̬��λ
+}
+   
+/*
+***********************************************************************
+*	�� �� ��: GSM_PowerON
+*	����˵��: GSMģ�鿪��
+*	��    ��: ��
+*	�� �� ֵ: ����������1�����ڿ������0
+***********************************************************************
+*/
+uint8_t GSM_PowerON(void)
+{
+	uint8_t returnData = 0;
+	static timer pullDown_Time;
+	static timer pullUp_Time;
+	static uint8_t timer_ok = 0;
+	
+	static uint8_t powerOnStatus = 0x00;
+	
+	if(timer_ok == 0)
+	{
+		timer_ok = 1;
+		timer_set(&pullDown_Time, CLOCK_SECOND*3);  		//����1����ʱ�������ڼ�������Ϊ�͵�ƽʱ��
+		timer_set(&pullUp_Time, CLOCK_SECOND*8);  			//����1����ʱ�������ڼ�������Ϊ�ߵ�ƽʱ��
+	}
+	switch(powerOnStatus)
+	{
+		case 0x00:			//�������״̬
+			printf("\r\nGSMģ�����ڿ���\r\n");	
+			GPIO_SetBits(GSM_POW_KEY_Port, GSM_POW_KEY_Pin);	
+// 			GPIO_ResetBits(GSM_POW_KEY_Port, GSM_POW_KEY_Pin);
+			
+			timer_restart(&pullDown_Time);
+			powerOnStatus = 0x01;
+			break;
+			
+		case 0x01:			//��Լ�ȴ�2S�ӵ�ʱ�䣬power_key��������2S���ɿ�����ģ��		
+			if(timer_expired(&pullDown_Time))
+			{
+// 				GPIO_SetBits(GSM_POW_KEY_Port, GSM_POW_KEY_Pin);
+				GPIO_ResetBits(GSM_POW_KEY_Port, GSM_POW_KEY_Pin);
+
+				timer_restart(&pullUp_Time);
+				powerOnStatus = 0x02;
+				break;
+			}		
+			break;
+			
+		case 0x02:
+			if(timer_expired(&pullUp_Time))
+			{
+				returnData = 1;
+				powerOnStatus = 0x00;
+			}
+			break;
+			
+		default:break;
+	}
+	return returnData;
+}
+
+/*
+***********************************************************************
+*	�� �� ��: GSM_PowerOFF
+*	����˵��: GSMģ��ػ�
+*	��    ��: ��
+*	�� �� ֵ: ��
+***********************************************************************
+*/
+uint8_t GSM_PowerOFF(void)
+{
+	uint8_t returnData = 0;
+	
+	return returnData;
+}
+
+/*
+***********************************************************************
+*	�� �� ��: GSM_SignalCheck
+*	����˵��: ��ѯ�ź�����
+*	��    �Σ���
+*	�� �� ֵ: ��
+***********************************************************************
+*/
+void GSM_SignalCheck(void)
+{
+	uint8_t cnt = 0;
+	GSM_SendAtCmd("AT+CSQ", AT_CMD_CSQ_NO);
+	while((at_cmd_table[AT_CMD_CSQ_NO-1].result != AT_CMD_SUCCESS) && (cnt < 10))
+	{
+		delay_ms(1);
+		cnt++;
+	}
+	
+	if(at_cmd_table[AT_CMD_CSQ_NO-1].result == AT_CMD_SUCCESS)
+	{
+		if(signal > 0)
+		{
+			printf("\r\nGSM�ź�ǿ�� = %d\r\n", signal);
+			if(signal < 5)
+			{
+				printf("\r\nGSM�ź������������������Ƿ�����\r\n");
+			}
+		}else{
+			printf("\r\n��GSM�źţ�����\r\n");
+		}
+	}
+}
+
+/*
+***********************************************************************
+*	�� �� ��: GSM_GetHardInfo
+*	����˵��: ȡ��GSMģ���Ӳ����Ϣ��IMEI��
+*	��    ��: msg������GSMģ����Ϣ�ṹ��
+*	�� �� ֵ: ��
+***********************************************************************
+*/
+void GSM_GetHardInfo(_gsm_msg *msg)
+{
+}
+
+/*
+***********************************************************************
+*	�� �� ��: GPRS_OnlineCheck
+*	����˵��: GPRS���̨������������飨��������������⣩
+*	��    �Σ���
+*	�� �� ֵ: ��
+***********************************************************************
+*/
+static void GPRS_OnlineCheck(void)
+{
+	sendMsg.msgType = 1001;														//����
+	MessageSend(MSG_FIFO_PROTOCOL, sendMsg);
+}
+
+uint8_t startSyncNTP_Mark = 0;					//����ͬ��NTP��������־
+uint8_t syncNTP_SuccessMark = 0;				//ͬ��NTP�������ɹ���־
+typedef enum
+{
+	LTE_STA_NTP_INIT = 0,									//LTEģ��NTPʱ��ͬ����ʼ״̬
+	LTE_STA_NTP_QIACT,										//����PDP����
+	LTE_STA_NTP_QIACT_ACK,								//����PDP����Ӧ��
+	LTE_STA_NTP_QIDEACT,									//������PDP����
+	LTE_STA_NTP_QIDEACT_ACK,							//������PDP����Ӧ��
+	
+	LTE_STA_QNTP,													//ͬ��NTPʱ�������
+	LTE_STA_QNTP_ACK,											//ͬ��NTPʱ�������Ӧ��
+	LTE_STA_GET_CLK,											//��ȡ����ʱ��
+	LTE_STA_GET_CLK_ACK,									//��ȡ����ʱ��Ӧ��
+	
+	LTE_STA_NTP_OK,												//LTEģ��������״̬
+	LTE_STA_NTP_FAILURE,									//LTEģ�����ʧ��״̬
+}_LTE_NTP_Status;
+/*
+***********************************************************************
+*	�� �� ��: EC200X_NTP_SyncHandler
+*	����˵��: EC200Xģ��ͬ��NTPʱ���������������
+*	��    �Σ���
+*	�� �� ֵ: �ޣ�ͬ��ʱ��ɹ���ȫ�ֱ���syncNTP_SuccessMark = 1��
+***********************************************************************
+*/
+void EC200X_NTP_SyncHandler(void)
+{
+	static _LTE_NTP_Status currentStatus = LTE_STA_NTP_INIT;
+	static _LTE_NTP_Status nextStatus = LTE_STA_NTP_INIT;
+	
+	static uint8_t GSM_GPRS_initStatus = 0;
+	static uint8_t waitTimeOutCount = 0;
+	
+	static timer responseTimeout;
+	static uint8_t timer_ok = 0;
+	
+	if(timer_ok == 0)
+	{
+		timer_ok = 1;
+		timer_set(&responseTimeout, CLOCK_SECOND*10);  			//����1����ʱ�������ڷ���AT�����ȴ�Ӧ���ʱ��
+	}
+	
+	currentStatus = nextStatus;
+	switch(currentStatus)
+	{
+		case LTE_STA_NTP_INIT:		//��ʼ״̬
+			if(startSyncNTP_Mark == 1)
+			{
+				startSyncNTP_Mark = 0;
+				syncNTP_SuccessMark = 0;
+				printf("\r\n��ʼͬ��NTP������\r\n");
+				nextStatus = LTE_STA_NTP_QIACT;
+				break;
+			}
+			break;
+			
+		case LTE_STA_NTP_QIACT:		//����PDP
+			GSM_SendAtCmd("AT+QIACT=1", AT_CMD_QIACT_NO);
+			timer_restart(&responseTimeout);
+			nextStatus = LTE_STA_NTP_QIACT_ACK;
+			break;
+			
+		case LTE_STA_NTP_QIACT_ACK:		//�ȴ�����PDPӦ��
+			if(at_cmd_table[AT_CMD_QIACT_NO-1].result == AT_CMD_SUCCESS)
+			{
+				printf("\r\n����PDP OK\r\n");
+				nextStatus = LTE_STA_QNTP;
+				break;
+			}
+			if(at_cmd_table[AT_CMD_QIACT_NO-1].result == AT_CMD_FAILED)
+			{
+				printf("\r\n����PDP ERROR\r\n");
+				nextStatus = LTE_STA_NTP_FAILURE;
+				break;
+			}
+			
+			if(timer_expired(&responseTimeout))						//��ʱ��δ���յ�Ӧ��
+			{
+				printf("\r\nӦ��ʱ������PDPʧ��\r\n");
+				nextStatus = LTE_STA_NTP_FAILURE;	
+				break;
+			}
+			break;
+			
+		case LTE_STA_QNTP:		//ͬ��NTPʱ�������
+// 			printf("\r\nͬ��ʱ��\r\n");
+			GSM_SendAtCmd("AT+QNTP=1,\"202.112.10.36\",123", AT_CMD_QNTP_NO);
+			timer_restart(&responseTimeout);
+			nextStatus = LTE_STA_QNTP_ACK;
+			break;
+			
+		case LTE_STA_QNTP_ACK:		//�ȴ�ͬ��ʱ��Ӧ��
+			if(at_cmd_table[AT_CMD_QNTP_NO-1].result == AT_CMD_SUCCESS)
+			{
+				printf("\r\nʱ��ͬ��OK\r\n");
+				nextStatus = LTE_STA_GET_CLK;
+				break;
+			}
+			if(at_cmd_table[AT_CMD_QNTP_NO-1].result == AT_CMD_FAILED)
+			{
+				printf("\r\nʱ��ͬ�� ERROR\r\n");
+				nextStatus = LTE_STA_NTP_QIDEACT;
+				break;
+			}
+			
+			if(timer_expired(&responseTimeout))						//��ʱ��δ���յ�Ӧ��
+			{
+				printf("\r\nӦ��ʱ��ʱ��ͬ��ʧ��\r\n");
+				nextStatus = LTE_STA_NTP_QIDEACT;	
+				break;
+			}
+			break;
+			
+		case LTE_STA_GET_CLK:		//��ȡ����ʱ��
+			GSM_SendAtCmd("AT+CCLK?", AT_CMD_CCLK_NO);
+			timer_restart(&responseTimeout);
+			nextStatus = LTE_STA_GET_CLK_ACK;
+			break;
+			
+		case LTE_STA_GET_CLK_ACK:		//�ȴ���ȡ����ʱ��Ӧ��
+			if(at_cmd_table[AT_CMD_CCLK_NO-1].result == AT_CMD_SUCCESS)
+			{
+				GMT_To_Beijing(&GMT_Time);
+				printf("\r\nTime:%s\r\n", systemTime);
+				nextStatus = LTE_STA_NTP_QIDEACT;
+				break;
+			}
+			if(at_cmd_table[AT_CMD_CCLK_NO-1].result == AT_CMD_FAILED)
+			{
+				printf("\r\nGet Time ERROR\r\n");
+				nextStatus = LTE_STA_NTP_QIDEACT;
+				break;
+			}
+			
+			if(timer_expired(&responseTimeout))						//��ʱ��δ���յ�Ӧ��
+			{
+				printf("\r\nӦ��ʱ��Get Timeʧ��\r\n");
+				nextStatus = LTE_STA_NTP_QIDEACT;	
+				break;
+			}
+			break;
+			
+		case LTE_STA_NTP_QIDEACT:		//PDPȥ����
+			GSM_SendAtCmd("AT+QIDEACT=1", AT_CMD_QIDEACT_NO);
+			timer_restart(&responseTimeout);
+			nextStatus = LTE_STA_NTP_QIDEACT_ACK;
+			break;
+			
+		case LTE_STA_NTP_QIDEACT_ACK:		//�ȴ�PDPȥ����Ӧ��
+			if(at_cmd_table[AT_CMD_QIDEACT_NO-1].result == AT_CMD_SUCCESS)
+			{
+				printf("\r\nPDPȥ���� OK\r\n");
+				nextStatus = LTE_STA_NTP_OK;
+				break;
+			}
+			if(at_cmd_table[AT_CMD_QIDEACT_NO-1].result == AT_CMD_FAILED)
+			{
+				printf("\r\nPDPȥ���� ERROR\r\n");
+				nextStatus = LTE_STA_NTP_FAILURE;
+				break;
+			}
+			
+			if(timer_expired(&responseTimeout))						//��ʱ��δ���յ�Ӧ��
+			{
+				printf("\r\nӦ��ʱ��PDPȥ����ʧ��\r\n");
+				nextStatus = LTE_STA_NTP_FAILURE;	
+				break;
+			}
+			break;
+			
+		case LTE_STA_NTP_OK:
+			startSyncNTP_Mark = 0;
+			syncNTP_SuccessMark = 1;
+			printf("\r\nͬ��NTP��������ɣ�\r\n");
+			nextStatus = LTE_STA_NTP_INIT;
+			break;
+			
+		case LTE_STA_NTP_FAILURE:
+			startSyncNTP_Mark = 0;
+			syncNTP_SuccessMark = 0;
+			nextStatus = LTE_STA_NTP_INIT;
+			break;
+	}
+}
+
+typedef enum
+{
+	LTE_STA_LOADING_INIT = 0,						//LTEģ����س�ʼ״̬
+	LTE_STA_AT_TEST,										//����ATָ����LTEģ���Ƿ�����
+	LTE_STA_AT_TEST_ACK,								//����ATָ����LTEģ���Ƿ�����Ӧ��
+	LTE_STA_AT_ECHO,										//����ATָ�����ģʽ
+	LTE_STA_AT_ECHO_ACK,								//����ATָ�����ģʽӦ��
+	LTE_STA_CHECK_IMEI,									//��ѯIMEI��
+	LTE_STA_CHECK_IMEI_ACK,							//��ѯIMEI��Ӧ��
+	LTE_STA_CHECK_SIM,									//��ѯSIM��״̬
+	LTE_STA_CHECK_SIM_ACK,							//��ѯSIM��״̬Ӧ��
+	LTE_STA_CHECK_ICCID,								//��ѯSIM����ICCID����
+	LTE_STA_CHECK_ICCID_ACK,						//��ѯSIM����ICCID����Ӧ��
+	LTE_STA_CHECK_CSQ,									//��ѯ�ź�ǿ��
+	LTE_STA_CHECK_CSQ_ACK,							//��ѯ�ź�ǿ��Ӧ��
+	LTE_STA_CHECK_CREG,									//��ѯCSҵ��ע��״̬���Ƿ�ע�����磩
+	LTE_STA_CHECK_CREG_ACK,							//��ѯCSҵ��ע��״̬Ӧ��
+	LTE_STA_CHECK_CGREG,								//��ѯPSҵ��ע��״̬���Ƿ���GPRSҵ��
+	LTE_STA_CHECK_CGREG_ACK,						//��ѯPSҵ��ע��״̬Ӧ��
+	LTE_STA_QUERY_OPERATOR,							//��ѯ������Ӫ��
+	LTE_STA_QUERY_OPERATOR_ACK,					//��ѯ������Ӫ��Ӧ��
+	LTE_STA_SYNC_NTP,										//ͬ��NTPʱ�������
+	LTE_STA_SYNC_NTP_ACK,								//�ȴ�ͬ��NTPʱ�������Ӧ��
+	LTE_STA_LOADING_OK,									//LTEģ��������״̬
+	LTE_STA_LOADING_FAILURE,						//LTEģ�����ʧ��״̬
+	LTE_STA_LOADING_IDLE,								//LTEģ����п���״̬
+}_LTE_LoadingStatus;
+/*
+***********************************************************************
+*	�� �� ��: EC200X_Loading
+*	����˵��: EC200Xģ����أ���������ѯģ�������״̬��
+*	��    �Σ���
+*	�� �� ֵ: ��
+***********************************************************************
+*/
+void EC200X_Loading(void)
+{
+	static _LTE_LoadingStatus currentStatus = LTE_STA_LOADING_INIT;
+	static _LTE_LoadingStatus nextStatus = LTE_STA_LOADING_INIT;
+	
+	static uint8_t GSM_GPRS_initStatus = 0;
+	static uint8_t waitTimeOutCount = 0;
+	
+	static timer responseTimeout;
+	static timer queryTime;
+	static uint8_t timer_ok = 0;
+	
+	if(timer_ok == 0)
+	{
+		timer_ok = 1;
+		timer_set(&responseTimeout, CLOCK_SECOND*10);  			//����1����ʱ�������ڷ���AT�����ȴ�Ӧ���ʱ��
+		timer_set(&queryTime, CLOCK_SECOND*2);  						//����1����ʱ�������ڲ�ѯ����ע�����
+	}
+	
+	currentStatus = nextStatus;
+	switch(currentStatus)
+	{
+		case LTE_STA_LOADING_INIT:		//��ʼ״̬
+			if(GSM_PowerON())
+			{
+				lteLoadCompletedFlag = 0;
+				
+				signal = 0;
+				gsm_msg.simCardStatus = 0;												//δ֪״̬
+				nextStatus = LTE_STA_AT_TEST;
+				break;
+			}
+			break;
+			
+		case LTE_STA_AT_TEST:		//���ģ���Ƿ���������
+			printf("\r\n���ģ��\r\n");
+			GSM_SendAtCmd("AT", AT_CMD_AT_NO);
+			timer_restart(&responseTimeout);
+			nextStatus = LTE_STA_AT_TEST_ACK;
+			break;
+			
+		case LTE_STA_AT_TEST_ACK:		//�ȴ�ģ��Ӧ��OK��		
+			if(at_cmd_table[AT_CMD_AT_NO-1].result == AT_CMD_SUCCESS)
+			{
+				printf("\r\nģ������\r\n");
+				nextStatus = LTE_STA_AT_ECHO;
+				break;
+			}
+			
+			if(timer_expired(&responseTimeout))						//��ʱ��δ���յ�Ӧ��
+			{
+				printf("\r\n��ʱδ��ģ��Ӧ��\r\n");
+				nextStatus = LTE_STA_LOADING_FAILURE;		
+				break;
+			}
+			break;
+			
+		case LTE_STA_AT_ECHO:		//�رջ���
+			printf("\r\n�رջ���\r\n");
+			GSM_SendAtCmd("ATE0", AT_CMD_ATE0_NO);
+			timer_restart(&responseTimeout);							//�ӵ�ǰʱ�����¿�����ʱ��
+			nextStatus = LTE_STA_AT_ECHO_ACK;
+			break;
+			
+		case LTE_STA_AT_ECHO_ACK:		//�ȴ�ģ��Ӧ��OK��		
+			if(at_cmd_table[AT_CMD_ATE0_NO-1].result == AT_CMD_SUCCESS)
+			{
+// 				printf("\r\n�رջ���OK\r\n");
+				nextStatus = LTE_STA_CHECK_IMEI;									//���յ�Ӧ����ת��0x
+				break;
+			}
+			
+			if(timer_expired(&responseTimeout))						//��ʱ��δ���յ�Ӧ��
+			{
+				printf("\r\n�رջ��Գ�ʱδӦ��\r\n");
+				nextStatus = LTE_STA_LOADING_FAILURE;		
+				break;
+			}
+			break;
+			
+		case LTE_STA_CHECK_IMEI:		//��ȡģ��IMEI��
+			GSM_SendAtCmd("AT+CGSN", AT_CMD_CGSN_NO);
+			timer_restart(&responseTimeout);
+			nextStatus = LTE_STA_CHECK_IMEI_ACK;
+			break;
+			
+		case LTE_STA_CHECK_IMEI_ACK:			//�ȴ�ATָ��Ӧ��			
+			if(at_cmd_table[AT_CMD_CGSN_NO-1].result == AT_CMD_SUCCESS)
+			{
+				printf("\r\nIMEI = %s\r\n", gsm_msg.IMEI);
+				waitTimeOutCount = 0;
+				
+				gsm_msg.Running = 1;											//��־ģ���Ѿ�������GPRS
+				nextStatus = 0xFF;
+// 				nextStatus = LTE_STA_CHECK_SIM;
+				break;
+			}
+			
+			if(timer_expired(&responseTimeout))						//��ʱ��δ���յ�Ӧ��
+			{
+				printf("\r\n��ȡӲ����Ϣ��ʱ\r\n");
+				nextStatus = LTE_STA_LOADING_FAILURE;		
+				break;
+			}
+			break;
+			
+		case 0xFF:		//���еȴ�
+			break;
+			
+		case LTE_STA_CHECK_SIM:		//��ѯSIM��״̬
+			if(waitTimeOutCount > 5)											//��ʱ��δ��ѯ������ע��״̬
+			{
+				waitTimeOutCount = 0;
+				gsm_msg.simCardStatus = 4;												//û�м�⵽SIM��
+				printf("\r\n��ѯSIM��״̬��ʱ��SIM����Ч������\r\n");
+				nextStatus = LTE_STA_LOADING_FAILURE;									//���ص���ʼ״̬
+				break;
+			}
+			GSM_SendAtCmd("AT+CPIN?", AT_CMD_CPIN_NO);
+			nextStatus = LTE_STA_CHECK_SIM_ACK;
+			timer_restart(&queryTime);
+			break;	
+			
+		case LTE_STA_CHECK_SIM_ACK:		//�ȴ���ѯSIM��ATָ��Ӧ��
+			if(at_cmd_table[AT_CMD_CPIN_NO-1].result == AT_CMD_SUCCESS)
+			{
+				printf("\r\nSIM���Ѿ�����\r\n");
+				printf("\r\n��ѯICCID��\r\n");
+				waitTimeOutCount = 0;	
+				nextStatus = LTE_STA_CHECK_ICCID;
+				break;
+			}
+			
+			if(timer_expired(&queryTime))						//��ʱ��δ���յ�Ӧ��
+			{
+				waitTimeOutCount++;										//�ȴ���ʱ����+1
+				nextStatus = LTE_STA_CHECK_SIM;	
+				break;
+			}
+			break;
+			
+		case LTE_STA_CHECK_ICCID:		//��ѯSIM����ICCID����
+			GSM_SendAtCmd("AT+QCCID", AT_CMD_ICCID_NO);
+			timer_restart(&responseTimeout);
+			nextStatus = LTE_STA_CHECK_ICCID_ACK;
+			break;
+			
+		case LTE_STA_CHECK_ICCID_ACK:			//��ѯSIM����ICCID����Ӧ��
+			if(at_cmd_table[AT_CMD_ICCID_NO-1].result == AT_CMD_SUCCESS)
+			{
+				printf("\r\nICCID = %s\r\n", gsm_msg.ICCID);
+				nextStatus = LTE_STA_CHECK_CSQ;
+				break;
+			}
+			
+			if(timer_expired(&responseTimeout))						//��ʱ��δ���յ�Ӧ��
+			{
+				printf("\r\n��ȡSIM����ICCID��ʱ\r\n");
+				nextStatus = LTE_STA_LOADING_FAILURE;		
+				break;
+			}
+			break;
+			
+		case LTE_STA_CHECK_CSQ:		//��ѯ�����ź�ǿ��
+			if(waitTimeOutCount > 10)											//��ʱ��δ��ѯ������ע��״̬
+			{
+				waitTimeOutCount = 0;
+				gsm_msg.simCardStatus = 2;												//�޷�ע������
+				printf("\r\n��ѯ���������źţ�����\r\n");
+				nextStatus = LTE_STA_LOADING_FAILURE;
+				break;
+			}
+			GSM_SendAtCmd("AT+CSQ", AT_CMD_CSQ_NO);
+			timer_restart(&queryTime);							//�ӵ�ǰʱ�����¿�����ʱ��
+			nextStatus = LTE_STA_CHECK_CSQ_ACK;
+			break;
+			
+		case LTE_STA_CHECK_CSQ_ACK:		//�ȴ������ź�Ӧ������
+			if(at_cmd_table[AT_CMD_CSQ_NO-1].result == AT_CMD_SUCCESS)
+			{
+				if((signal > 0) && (signal != 99))
+				{
+					printf("\r\n�ź�ǿ������ = %d\r\n", signal);
+					printf("\r\n��ѯ����ע��״̬\r\n");
+					waitTimeOutCount = 0;											//�ȴ���ʱ��������
+					nextStatus = LTE_STA_CHECK_CREG;
+					break;
+				}
+			}
+			
+			if(timer_expired(&queryTime))						//��ʱ��δ���յ�Ӧ��
+			{
+				waitTimeOutCount++;										//�ȴ���ʱ����+1
+				nextStatus = LTE_STA_CHECK_CSQ;	
+				break;
+			}
+			break;
+			
+		case LTE_STA_CHECK_CREG:		//��ѯ����ע��״̬
+			if(waitTimeOutCount > 20)											//��ʱ��δ��ѯ������ע��״̬
+			{
+				waitTimeOutCount = 0;
+				gsm_msg.simCardStatus = 2;												//�޷�ע������
+				printf("\r\n�ȴ���ʱ����δע�����磡����\r\n");
+				nextStatus = LTE_STA_LOADING_FAILURE;
+				break;
+			}
+
+			GSM_SendAtCmd("AT+CREG?", AT_CMD_CREG_NO);
+			timer_restart(&queryTime);							//�ӵ�ǰʱ�����¿�����ʱ��
+			nextStatus = LTE_STA_CHECK_CREG_ACK;
+			break;
+			
+		case LTE_STA_CHECK_CREG_ACK:		//�ȴ�����ע��ɹ�			
+			if(at_cmd_table[AT_CMD_CREG_NO-1].result == AT_CMD_SUCCESS)
+			{
+				printf("\r\n�Ѿ�ע������\r\n");
+				printf("\r\n��ѯ�Ƿ���GPRSҵ��\r\n");
+				waitTimeOutCount = 0;											//�ȴ���ʱ��������
+				nextStatus = LTE_STA_CHECK_CGREG;
+				break;
+			}
+			
+			if(timer_expired(&queryTime))						//��ʱ��δ���յ�Ӧ��
+			{
+				waitTimeOutCount++;										//�ȴ���ʱ����+1
+				printf("\r\nCnt = %d\r\n", waitTimeOutCount);
+				nextStatus = LTE_STA_CHECK_CREG;	
+				break;
+			}
+			break;
+			
+		case LTE_STA_CHECK_CGREG:		//���GPRS����״̬
+			if(waitTimeOutCount > 10)											//��ʱ��δ��ѯ��GPRS����״̬
+			{
+				waitTimeOutCount = 0;
+				gsm_msg.simCardStatus = 3;									//SIM��û��GPRSҵ��
+				printf("\r\n�ȴ���ʱ����δ����GPRS\r\n");
+				nextStatus = LTE_STA_LOADING_FAILURE;
+				break;
+			}
+			GSM_SendAtCmd("AT+CGREG?", AT_CMD_CGREG_NO);	//���GPRS����״̬						
+			timer_restart(&queryTime);										//�ӵ�ǰʱ�����¿�����ʱ��
+			nextStatus = LTE_STA_CHECK_CGREG_ACK;
+			break;
+			
+		case LTE_STA_CHECK_CGREG_ACK:		//�ȴ�����GPRSҵ��		
+			if(at_cmd_table[AT_CMD_CGREG_NO-1].result == AT_CMD_SUCCESS)
+			{
+				gsm_msg.simCardStatus = 1;									//SIM������
+				printf("\r\n�Ѿ�����GPRSҵ��\r\n");
+				
+				nextStatus = LTE_STA_QUERY_OPERATOR;	
+				break;
+			}
+			
+			if(timer_expired(&queryTime))									//��ʱ��δ���յ�Ӧ��
+			{
+				waitTimeOutCount++;													//�ȴ���ʱ����+1
+				printf("\r\nCnt = %d\r\n", waitTimeOutCount);
+				nextStatus = LTE_STA_CHECK_CGREG;	
+				break;
+			}
+			break;
+			
+		case LTE_STA_QUERY_OPERATOR:		//��ѯ������Ӫ��
+			GSM_SendAtCmd("AT+COPS?", AT_CMD_COPS_NO);		//��ѯ��Ӫ��
+			timer_restart(&responseTimeout);
+			nextStatus = LTE_STA_QUERY_OPERATOR_ACK;
+			break;
+			
+		case LTE_STA_QUERY_OPERATOR_ACK:		//��ѯ������Ӫ��Ӧ��
+			if(at_cmd_table[AT_CMD_COPS_NO-1].result == AT_CMD_SUCCESS)
+			{
+				if(gsm_msg.OperatorType == 1)
+				{
+					printf("\r\n�й��ƶ�\r\n");
+				}else if(gsm_msg.OperatorType == 2){
+					printf("\r\n�й���ͨ\r\n");
+				}else{}
+				
+				nextStatus = LTE_STA_SYNC_NTP;
+// 				nextStatus = LTE_STA_LOADING_OK;
+				break;
+			}
+			
+			if(timer_expired(&responseTimeout))						//��ʱ��δ���յ�Ӧ��
+			{
+				printf("\r\nӦ��ʱ��\r\n");
+				nextStatus = LTE_STA_SYNC_NTP;
+// 				nextStatus = LTE_STA_LOADING_OK;				
+				break;
+			}
+			break;
+			
+		case LTE_STA_SYNC_NTP:		//����ͬ��NTP������
+			startSyncNTP_Mark = 1;
+			syncNTP_SuccessMark = 0;
+			timer_restart(&responseTimeout);
+			nextStatus = LTE_STA_SYNC_NTP_ACK;
+			break;
+			
+		case LTE_STA_SYNC_NTP_ACK:		//�ȴ�NTPͬ������ʱ�����
+			EC200X_NTP_SyncHandler();
+			if(syncNTP_SuccessMark == 1)
+			{
+				syncNTP_SuccessMark = 0;
+				nextStatus = LTE_STA_LOADING_OK;
+				break;
+			}
+			
+			if(timer_expired(&responseTimeout))						//��ʱ��δ���յ�Ӧ��
+			{
+				printf("\r\nNTP ͬ����ʱ��\r\n");
+				nextStatus = LTE_STA_LOADING_OK;				
+				break;
+			}
+			break;
+			
+		case LTE_STA_LOADING_OK:		//LTEģ���������سɹ�
+			waitTimeOutCount = 0;												//�ȴ���ʱ��������
+			lteLoadCompletedFlag = 1;										//��־LTEģ���Ѿ������������
+			nextStatus = LTE_STA_LOADING_IDLE;	
+			break;
+			
+		case LTE_STA_LOADING_FAILURE:		//LTEģ�����ʧ��
+			printf("\r\nģ�����ʧ�ܣ�\r\n");
+			nextStatus = LTE_STA_LOADING_INIT;
+			break;
+			
+		case LTE_STA_LOADING_IDLE:			//����״̬
+			if(lteLoadResetFlag == 1)
+			{
+				lteLoadResetFlag = 0;
+				lteLoadCompletedFlag = 0;
+				printf("\r\nģ����ع��̸�λ��\r\n");
+				nextStatus = LTE_STA_LOADING_INIT;
+				break;
+			}
+			break;
+			
+		default: 
+			nextStatus = LTE_STA_LOADING_FAILURE;
+			break;
+	}
+	
+	//���ع�����Ҫ��λ
+	if(lteLoadResetFlag == 1)
+	{
+		lteLoadResetFlag = 0;
+		lteLoadCompletedFlag = 0;
+		printf("\r\nģ����ع��̸�λ��\r\n");
+		nextStatus = LTE_STA_LOADING_INIT;
+	}
+}
+
+typedef enum
+{
+	LTE_STA_TCP_CREATE_INIT = 0,				//��ʼ״̬
+	LTE_STA_SET_PDP_CONTEXT,						//����TCP/IP��������
+	LTE_STA_SET_PDP_CONTEXT_ACK,				//����TCP/IP��������Ӧ��
+	LTE_STA_QIACT,											//����PDP����
+	LTE_STA_QIACT_ACK,									//����PDP����Ӧ��
+	LTE_STA_QIDEACT,										//������PDP����
+	LTE_STA_QIDEACT_ACK,								//������PDP����Ӧ��
+	LTE_STA_CHECK_QIACT,								//��ѯPDP����״̬
+	LTE_STA_CHECK_QIACT_ACK,						//��ѯPDP����״̬Ӧ��
+	LTE_STA_OPEN_SOCKET,								//��Socket����
+	LTE_STA_OPEN_SOCKET_ACK,						//��Socket����Ӧ��
+// 	LTE_STA_CLOSE_SOCKET,								//�ر�Socket����
+// 	LTE_STA_CLOSE_SOCKET_ACK,						//�ر�Socket����Ӧ��
+	LTE_STA_CREATE_OK,									//Socket�����������
+	LTE_STA_CREATE_FAILURE,							//Socket��������ʧ��
+	LTE_STA_CREATE_IDLE,								//Socket�������ӹ��̿���״̬
+}_LTE_TCP_CreateStatus;
+/*
+***********************************************************************
+*	�� �� ��: TCP_ClientCreate
+*	����˵��: ����TCP�ͻ���
+*	��    �Σ���
+*	�� �� ֵ: ��
+***********************************************************************
+*/
+void TCP_ClientCreate(void)
+{
+	static _LTE_TCP_CreateStatus currentStatus = LTE_STA_TCP_CREATE_INIT;
+	static _LTE_TCP_CreateStatus nextStatus = LTE_STA_TCP_CREATE_INIT;
+	
+	static timer responseTimeout;
+	static timer responseTimeout_3s;
+	static timer registrationTime;
+	static timer connectionWaitTime;
+	static timer waitingTime_2s;
+	static timer reconnectTimeout;
+	static uint8_t timer_ok = 0;
+	
+	if(timer_ok == 0)
+	{
+		timer_ok = 1;
+		timer_set(&responseTimeout, CLOCK_SECOND*3);  		//����1����ʱ�������ڷ���AT�����ȴ�Ӧ���ʱ��
+		timer_set(&responseTimeout_3s, CLOCK_SECOND*3);  	//����1����ʱ�������ڷ���AT�����ȴ�Ӧ���ʱ��
+		timer_set(&connectionWaitTime, CLOCK_SECOND*10);  //����1����ʱ�������ڽ������ӵȴ��ĳ�ʱʱ��
+		timer_set(&registrationTime, CLOCK_SECOND*10);  	//����1����ʱ�������ڼ������ע������ĵȴ���ʱʱ��
+		timer_set(&waitingTime_2s, CLOCK_SECOND*2);
+		timer_set(&reconnectTimeout, CLOCK_SECOND*20);
+	}
+	
+	currentStatus = nextStatus;
+	switch(currentStatus)
+	{	
+		case LTE_STA_TCP_CREATE_INIT:			//��ʼ����TCP����
+			if(lteLoadCompletedFlag == 1)
+			{
+				printf("\r\n׼������TCP/IP Socket!\r\n");
+				nextStatus = LTE_STA_SET_PDP_CONTEXT;
+				break;
+			}
+			break;
+			
+		case LTE_STA_SET_PDP_CONTEXT:
+			printf("\r\n��ʼ��������APN\r\n");
+			if(gsm_msg.OperatorType == 1)
+			{
+				GSM_SendAtCmd("AT+QICSGP=1,1,\"CMNET\","","",1", AT_CMD_QICSGP_NO);			//����APN���й��ƶ�
+			}else if(gsm_msg.OperatorType == 2){
+				GSM_SendAtCmd("AT+QICSGP=1,1,\"UNINET\","","",1", AT_CMD_QICSGP_NO);			//����APN���й���ͨ
+			}else{
+				GSM_SendAtCmd("AT+QICSGP=1,1,\"CMNET\","","",1", AT_CMD_QICSGP_NO);			//����APN���й��ƶ�
+			}	
+			timer_restart(&responseTimeout);							//�ӵ�ǰʱ�����¿���2�붨ʱ��
+			timer_restart(&reconnectTimeout);							//��ʼ���������ȳ�ʼ����ʱ���������ʱ�ˣ�����Ҫ���¿���
+			nextStatus = LTE_STA_SET_PDP_CONTEXT_ACK;
+			break;
+			
+		case LTE_STA_SET_PDP_CONTEXT_ACK:			//�ȴ�Ӧ��		
+			if(at_cmd_table[AT_CMD_QICSGP_NO-1].result == AT_CMD_SUCCESS)
+			{
+				printf("\r\n����APN OK\r\n");
+				nextStatus = LTE_STA_QIDEACT;
+				break;
+			}
+			if(at_cmd_table[AT_CMD_QICSGP_NO-1].result == AT_CMD_FAILED)
+			{
+				printf("\r\n����APN ERROR\r\n");
+				nextStatus = LTE_STA_CREATE_FAILURE;
+				break;
+			}
+			
+			if(timer_expired(&responseTimeout))						//��ʱ��δ���յ�Ӧ��
+			{
+				printf("\r\n�ȴ�Ӧ��ʱ������APN����\r\n");
+				nextStatus = LTE_STA_CREATE_FAILURE;	
+				break;
+			}
+			break;
+			
+		case LTE_STA_QIDEACT:
+			printf("\r\n������\r\n");
+			GSM_SendAtCmd("AT+QIDEACT=1", AT_CMD_QIDEACT_NO);		//����PDP������,��������Э��,��������Ϣ
+			timer_restart(&responseTimeout);
+			nextStatus = LTE_STA_QIDEACT_ACK;
+			break;
+			
+		case LTE_STA_QIDEACT_ACK:
+			if(at_cmd_table[AT_CMD_QIDEACT_NO-1].result == AT_CMD_SUCCESS)
+			{
+				printf("\r\n������OK\r\n");
+				nextStatus = LTE_STA_QIACT;
+				break;
+			}
+			if(at_cmd_table[AT_CMD_QIACT_NO-1].result == AT_CMD_FAILED)
+			{
+				printf("\r\n����������· ERROR\r\n");
+				nextStatus = LTE_STA_CREATE_FAILURE;
+				break;
+			}
+			
+			if(timer_expired(&responseTimeout))						//��ʱ��δ���յ�Ӧ��
+			{
+				printf("\r\nӦ��OK��ʱ������������·ʧ��\r\n");
+				nextStatus = LTE_STA_CREATE_FAILURE;	
+				break;
+			}
+			break;
+
+		case LTE_STA_QIACT:			//����PDP����
+			printf("\r\n����������·\r\n");
+			GSM_SendAtCmd("AT+QIACT=1", AT_CMD_QIACT_NO);
+			timer_restart(&responseTimeout);
+			nextStatus = LTE_STA_QIACT_ACK;
+			break;
+			
+		case LTE_STA_QIACT_ACK:			//�ȴ�Ӧ��				
+			if(at_cmd_table[AT_CMD_QIACT_NO-1].result == AT_CMD_SUCCESS)
+			{
+				printf("\r\n����������·OK\r\n");
+				nextStatus = LTE_STA_CHECK_QIACT;
+				break;
+			}
+			if(at_cmd_table[AT_CMD_QIACT_NO-1].result == AT_CMD_FAILED)
+			{
+				printf("\r\n����������· ERROR\r\n");
+				nextStatus = LTE_STA_CREATE_FAILURE;
+				break;
+			}
+			
+			if(timer_expired(&responseTimeout))						//��ʱ��δ���յ�Ӧ��
+			{
+				printf("\r\nӦ��OK��ʱ������������·ʧ��\r\n");
+				nextStatus = LTE_STA_CREATE_FAILURE;	
+				break;
+			}
+			break;
+			
+		case LTE_STA_CHECK_QIACT:
+			printf("\r\n��ñ���IP\r\n");
+			GSM_SendAtCmd("AT+QIACT?", AT_CMD_CHECK_QIACT_NO);
+			nextStatus = LTE_STA_CHECK_QIACT_ACK;
+			timer_restart(&responseTimeout);
+			break;
+			
+		case LTE_STA_CHECK_QIACT_ACK:
+			if(at_cmd_table[AT_CMD_CHECK_QIACT_NO-1].result == AT_CMD_SUCCESS)
+			{
+				printf("\r\n�ѻ��IP��ַ\r\n");
+				nextStatus = LTE_STA_OPEN_SOCKET;
+				break;
+			}
+			if(at_cmd_table[AT_CMD_CHECK_QIACT_NO-1].result == AT_CMD_FAILED)
+			{
+				printf("\r\n��ñ���IPʧ�� ERROR\r\n");
+				nextStatus = LTE_STA_CREATE_FAILURE;
+				break;
+			}
+			
+			if(timer_expired(&responseTimeout))						//��ʱ��δ���յ�Ӧ��
+			{
+				printf("\r\nӦ��OK��ʱ����ñ���IPʧ��\r\n");
+				nextStatus = LTE_STA_CREATE_FAILURE;	
+				break;
+			}
+			break;
+		
+		case LTE_STA_OPEN_SOCKET:			//��ʼ����Զ�˷�����		
+			printf("\r\n��ʼ����Զ�˷�����\r\n");
+			GSM_SendAtCmd(TCP_IP_COM, AT_CMD_QIOPEN);
+			nextStatus = LTE_STA_OPEN_SOCKET_ACK;
+			timer_restart(&connectionWaitTime);
+			break;	
+			
+		case LTE_STA_OPEN_SOCKET_ACK:			//�ȴ�Ӧ��CONNECT OK��								
+			if(at_cmd_table[AT_CMD_QIOPEN-1].result == AT_CMD_SUCCESS)
+			{
+				printf("\r\n���ӳɹ�\r\n");
+				nextStatus = LTE_STA_CREATE_OK;		
+				break;
+			}
+			
+			if(at_cmd_table[AT_CMD_QIOPEN-1].result == AT_CMD_FAILED)
+			{
+				printf("\r\n����ʧ��\r\n");
+				nextStatus = LTE_STA_CREATE_FAILURE;
+				break;
+			}
+			
+			if(timer_expired(&connectionWaitTime))				//��ʱ��δ���յ�Ӧ��
+			{
+				printf("\r\n���ӳ�ʱ!!!\r\n");		
+				nextStatus = LTE_STA_CREATE_FAILURE;
+				break;
+			}
+			break;
+			
+		case LTE_STA_CREATE_OK:		//����Socket���
+			ConnectionStatus = ONLINE;
+			lteCreateSocketOkFlag = 1;
+			
+			networkConnectionCount++;									//���罨���ɹ����������Ӵ���+1
+			if(networkConnectionCount >= 0xFFFF)
+			{
+				networkConnectionCount = 2;
+			}
+			printf("\r\nnetworkConnectionCount = %d\r\n", networkConnectionCount);
+			
+			//�������ʧ�ܼ����������Ӵ��������Ϊ�˷�ֹ�ڳ������й����г��ִ���������������ģ�鸴λ������
+			sendFailureCount = 0;
+			errorProcessCount = 0;
+										
+			gsm_msg.Running = 1;											//��־ģ���Ѿ�������GPRS
+			
+			nextStatus = LTE_STA_CREATE_IDLE;
+			break;
+			
+		case LTE_STA_CREATE_FAILURE:		//����Socketʧ��
+			printf("\r\n����Socketʧ�ܣ�\r\n");
+			errorProcessCount++;
+			printf("\r\n����Socketʧ�ܴ��� = %d\r\n", errorProcessCount);
+			nextStatus = LTE_STA_TCP_CREATE_INIT;
+			break;
+			
+		case LTE_STA_CREATE_IDLE:		//����Socket��ɺ�������״̬
+			if(lteCreateSocketResetFlag == 1)
+			{
+				lteCreateSocketResetFlag = 0;
+				printf("\r\n����Socket���̸�λ��\r\n");
+				
+				ConnectionStatus = OFFLINE;
+				lteCreateSocketOkFlag = 0;
+				gsm_msg.Running = 0;
+				
+				//�������ʧ�ܼ����������Ӵ������
+				sendFailureCount = 0;
+				errorProcessCount = 0;
+											
+				nextStatus = LTE_STA_TCP_CREATE_INIT;
+				break;
+			}
+			break;
+
+		default: 		//����״̬
+			printf("\r\nδ֪״̬������ģ�飡����\r\n");
+			LTE_StatusReset();							//GSMģ�鸴λ������
+			break;	
+	}
+	
+	if(lteCreateSocketResetFlag == 1)
+	{
+		lteCreateSocketResetFlag = 0;
+		printf("\r\n����Socket���̸�λ��\r\n");
+		
+		ConnectionStatus = OFFLINE;
+		lteCreateSocketOkFlag = 0;
+		gsm_msg.Running = 0;
+		
+		//�������ʧ�ܼ����������Ӵ������
+		sendFailureCount = 0;
+		errorProcessCount = 0;
+									
+		nextStatus = LTE_STA_TCP_CREATE_INIT;
+	}
+}
+
+typedef enum
+{
+	LTE_STA_Handler_INIT = 0,						//��ʼ״̬
+	LTE_STA_SEND_DATA,									//TCP��������
+	LTE_STA_LOAD_DATA_READY,						//�ȴ�ģ��Ӧ��">"��׼����������
+	LTE_STA_LOAD_DATA,									//����Ҫ���͵�����
+	LTE_STA_SEND_DATA_ACK,							//TCP��������Ӧ��
+	LTE_STA_WAITING_SEND_TIME,					//�ȴ�����ʱ��
+	LTE_STA_CHECK_SEND_DATA,						//���TCP���������Ƿ��Ѿ����������
+	LTE_STA_CHECK_SEND_DATA_ACK,				//���TCP���������Ƿ��Ѿ����������Ӧ��
+	LTE_STA_REPEAT_CHECK_SEND_DATA,			//���¼��TCP���������Ƿ��Ѿ����������
+	LTE_STA_CLOSE_SOCKET,								//�ر�Socket����
+	LTE_STA_CLOSE_SOCKET_ACK,						//�ر�Socket����Ӧ��
+	LTE_STA_WQITING_RECEIVE_DATA,				//�ȴ��������ظ�����
+	LTE_STA_READ_DATA,									//TCP��ȡ���յ�������
+	LTE_STA_READ_DATA_ACK,							//TCP��ȡ���յ�������Ӧ��
+	LTE_STA_SEND_DATA_OK,								//���ͳɹ�
+	LTE_STA_HANDLER_FAILURE,						//����ʧ��
+	LTE_STA_HANDLER_RESTART,						//���ݷ�������λ
+	LTE_STA_GET_SIGNAL,									//��ȡ�ź�
+	LTE_STA_GET_SIGNAL_ACK,							//��ȡ�ź�Ӧ��
+	LTE_STA_GET_DATE_TIME,							//��ȡ����ʱ��
+	LTE_STA_GET_DATE_TIME_ACK,					//��ȡ����ʱ��Ӧ��
+}_LTE_TCP_HandlerStatus;
+/*
+***********************************************************************
+*	�� �� ��: TCP_ClientHandler
+*	����˵��: TCP�ͻ��˵������շ�����
+*	��    �Σ���
+*	�� �� ֵ: ��
+***********************************************************************
+*/
+void TCP_ClientHandler(void)
+{
+	static _LTE_TCP_HandlerStatus currentStatus = LTE_STA_Handler_INIT;
+	static _LTE_TCP_HandlerStatus nextStatus = LTE_STA_Handler_INIT;
+
+	char atCmdBuf[32];															//ATָ���
+	static uint8_t waitTimeOutCount = 0;
+	
+	static timer getSignalTime;														//��ȡ�źż��ʱ��
+	static timer getDateTime;															//��ȡ����ʱ����ʱ��
+	static timer responseTimeout;													//Ӧ��ʱʱ����
+	static timer sendTimeout;															//���ͳ�ʱʱ����
+	static timer checkSendAckTimer;
+	static timer receiveTimer;
+	static timer waitingTimer;
+	
+	static uint8_t timer_ok = 0;
+	if(timer_ok == 0)
+	{
+		timer_ok = 1;
+		timer_set(&getSignalTime, CLOCK_SECOND*60);  		
+		timer_set(&getDateTime, CLOCK_SECOND*60); 		
+		timer_set(&responseTimeout, CLOCK_SECOND*3);
+		timer_set(&sendTimeout, CLOCK_SECOND*10);
+		timer_set(&receiveTimer, CLOCK_SECOND*20);
+		timer_set(&checkSendAckTimer, CLOCK_SECOND*5);
+		timer_set(&waitingTimer, CLOCK_SECOND*1);
+	}
+	
+	currentStatus = nextStatus;
+	switch(currentStatus)
+	{			
+		case LTE_STA_Handler_INIT:				//��ǰ������������������Ƿ�������Ҫ���ͣ��оͶ����ݽ��з���
+			if((isSendDataMark == 1) && (ConnectionStatus == ONLINE))
+			{
+				isSendDataMark = 0;
+				isReceiveDataMark = 0;
+				nextStatus = LTE_STA_SEND_DATA;
+				break;
+			}
+			
+			if(ConnectionStatus == ONLINE)
+			{
+				//��ȡ����ʱ��
+				if(timer_expired(&getDateTime))
+				{
+// 					printf("\r\n��ȡ����ʱ�䣡\r\n");
+					timer_restart(&getDateTime);
+					nextStatus = LTE_STA_GET_DATE_TIME;
+					break;
+				}
+				
+				//��ȡ�ź�ǿ��
+				if(timer_expired(&getSignalTime))
+				{
+					timer_restart(&getSignalTime);
+					nextStatus = LTE_STA_GET_SIGNAL;
+					break;
+				}
+			}
+			break;
+			
+		case LTE_STA_SEND_DATA:			//��������
+			sprintf(atCmdBuf, "AT+QISEND=0,%d", sendDataLen);
+// 			printf("\r\n%s\r\n", atCmdBuf);
+			
+			GSM_SendAtCmd(atCmdBuf, AT_CMD_QISEND);
+			timer_restart(&responseTimeout);
+			nextStatus = LTE_STA_LOAD_DATA_READY;
+			break;
+			
+		case LTE_STA_LOAD_DATA_READY:				//�ȴ�����Ӧ��>��	
+			if(at_cmd_table[AT_CMD_QISEND-1].result == AT_CMD_CIPSEND_READY)
+			{
+				printf("\r\nӦ�� > OK\r\n");
+				nextStatus = LTE_STA_LOAD_DATA;							//���յ�Ӧ��					
+				break;
+			}
+			
+			if(at_cmd_table[AT_CMD_QISEND-1].result == AT_CMD_SEND_FAIL)
+			{
+				printf("\r\nӦ��> ERROR\r\n");
+				seriousError = 1;
+// 				errorProcessCount ++;											//����ʧ��+1
+				printf("\r\n����ERROR���� = %d\r\n", errorProcessCount);
+				
+				nextStatus = LTE_STA_HANDLER_FAILURE;
+				break;
+			}
+			
+			if(at_cmd_table[AT_CMD_QISEND-1].result == TCP_STATUS_CLOSED)
+			{
+				printf("\r\n�����Ѿ��رգ�����ʧ��\r\n");
+				seriousError = 1;
+// 				errorProcessCount ++;											//����ʧ��+1
+				printf("\r\n����ERROR���� = %d\r\n", errorProcessCount);
+				
+				nextStatus = LTE_STA_HANDLER_FAILURE;				
+				break;
+			}
+			
+			if(timer_expired(&responseTimeout))						//��ʱ��δ���յ�Ӧ��
+			{
+				printf("\r\n��ʱδӦ��>ȡ������\r\n");	
+				errorProcessCount ++;												//����ʧ��+1
+				printf("\r\n����ERROR���� = %d\r\n", errorProcessCount);
+				
+				nextStatus = LTE_STA_HANDLER_FAILURE;
+				break;
+			}
+			break;
+			
+		case LTE_STA_LOAD_DATA:				//ͨ��������ģ�鷢��Ҫ���͵�����
+			receiveDataMark = 0;
+			memcpy(GPRS_TX_BUF, GPRS_DATA_BUF, sendDataLen);
+			GSM_GPRS_SendOne(GPRS_TX_BUF, sendDataLen);
+			printf("\r\n���ڷ�������......\r\n");
+// 			printf("\r\nStartTime = %d\r\n", time_value);
+			
+			timer_restart(&sendTimeout);
+			nextStatus = LTE_STA_SEND_DATA_ACK;
+			break;
+			
+		case LTE_STA_SEND_DATA_ACK:				//�ȴ�����Ӧ��SEND OK��		
+			if(at_cmd_table[AT_CMD_QISEND-1].result == AT_CMD_CIPSEND_OK)
+			{
+// 				printf("\r\nEndTime = %d\r\n", time_value);
+				printf("\r\n���ͼ��سɹ���\r\n");
+				
+				timer_restart(&waitingTimer);
+				nextStatus = LTE_STA_WAITING_SEND_TIME;
+				break;
+			}
+			
+			if(at_cmd_table[AT_CMD_QISEND-1].result == AT_CMD_SEND_FAIL)
+			{
+				printf("\r\nEndTime = %d\r\n", time_value);
+				printf("\r\n���ͼ���ʧ��\r\n");
+				
+				sendFailureCount ++;											//����ʧ��+1
+				printf("\r\n����ʧ�ܴ��� = %d\r\n", sendFailureCount);
+				
+				nextStatus = LTE_STA_HANDLER_FAILURE;							
+				break;
+			}
+			
+			if(timer_expired(&sendTimeout))							//��ʱ��δ���յ�Ӧ��
+			{
+				printf("\r\nEndTime = %d\r\n", time_value);
+				printf("\r\n��ʱ������δ����������ʧ��\r\n");
+				
+				sendFailureCount ++;											//����ʧ��+1
+				printf("\r\n����ʧ�ܴ��� = %d\r\n", sendFailureCount);
+				
+				nextStatus = LTE_STA_HANDLER_FAILURE;
+				break;
+			}
+			break;
+			
+		case LTE_STA_WAITING_SEND_TIME:		//�ȴ�һС��ʱ���ٲ�ѯ�����Ƿ��Ѿ��ɹ����͸��Է�
+			//����յ���̨��Ӧ�����ݣ���ת����ȡ����
+			if(receiveDataMark == 1)
+			{
+				receiveDataMark = 0;
+	
+				printf("\r\n�յ�server���ݣ�\r\n");
+				nextStatus = LTE_STA_SEND_DATA_OK;
+				break;
+			}
+			
+			if(timer_expired(&waitingTimer))							//��ʱ��δ���յ�Ӧ��
+			{
+				waitTimeOutCount = 0;
+				nextStatus = LTE_STA_CHECK_SEND_DATA;
+				break;
+			}
+			break;
+			
+		case LTE_STA_CHECK_SEND_DATA:		//��ѯ�����Ƿ��ѷ��͵��Է�
+			printf("\r\n��ѯ�����Ƿ��ѷ��ͳɹ���\r\n");
+			
+			if(waitTimeOutCount > 6)
+			{
+				printf("\r\n��������ʱ��������δ�ܷ�����\r\n");
+				sendFailureCount ++;											//����ʧ��+1
+				printf("\r\n����ʧ�ܴ��� = %d\r\n", sendFailureCount);
+				
+				nextStatus = LTE_STA_HANDLER_FAILURE;
+				break;
+			}
+			
+			total_send_length = 0;
+			ackedBytes = 0;
+			GSM_SendAtCmd("AT+QISEND=0,0", AT_CMD_CHECK_QISEND_NO);
+			timer_restart(&checkSendAckTimer);
+			nextStatus = LTE_STA_CHECK_SEND_DATA_ACK;
+			break;
+			
+		case LTE_STA_CHECK_SEND_DATA_ACK:
+			if(at_cmd_table[AT_CMD_CHECK_QISEND_NO-1].result == AT_CMD_SUCCESS)
+			{
+				at_cmd_table[AT_CMD_CHECK_QISEND_NO-1].result = AT_CMD_UNKNOWN;
+				printf("\r\nBytes: tx = %d, ack = %d\r\n", total_send_length, ackedBytes);
+				
+				if(total_send_length == ackedBytes)
+				{
+					printf("\r\n�����ѳɹ����͵��Է���\r\n");
+					timer_restart(&receiveTimer);
+					nextStatus = LTE_STA_WQITING_RECEIVE_DATA;
+					break;
+				}
+			}
+			
+			//����յ���̨��Ӧ�����ݣ���ת����ȡ����
+			if(receiveDataMark == 1)
+			{
+				receiveDataMark = 0;
+				
+				printf("\r\n�յ�server���ݣ�\r\n");
+				nextStatus = LTE_STA_SEND_DATA_OK;
+				break;
+			}
+			
+			if(timer_expired(&checkSendAckTimer))						//��ʱ��δ���յ�Ӧ��
+			{
+				printf("\r\n��ѯ���ݷ��ͳ�ʱ��\r\n");	
+				waitTimeOutCount++;
+				
+				nextStatus = LTE_STA_CHECK_SEND_DATA;								//���ص����ӳɹ�״̬
+				break;
+			}
+			break;
+			
+		case LTE_STA_WQITING_RECEIVE_DATA:		//�ȴ��������ظ�����
+			if(receiveDataMark == 1)
+			{
+				receiveDataMark = 0;
+				
+				printf("\r\n�յ�server���ݣ�\r\n");
+				nextStatus = LTE_STA_SEND_DATA_OK;
+				break;
+			}
+			
+			if(timer_expired(&receiveTimer))
+			{
+				dataSendOkButNoAckMark = 1;
+				printf("\r\n�����Ѿ����ͣ���û���յ��ظ���\r\n");
+				sendFailureCount ++;											//����ʧ��+1
+				printf("\r\n����ʧ�ܴ��� = %d\r\n", sendFailureCount);
+				nextStatus = LTE_STA_Handler_INIT;
+				break;
+			}
+			break;
+			
+		case LTE_STA_SEND_DATA_OK:		//���ݷ��ͳɹ�
+			isReceiveDataMark = 1;									//��־���յ�����
+			errorProcessCount = 0;
+			sendFailureCount = 0;
+			
+			nextStatus = LTE_STA_Handler_INIT;
+			break;
+			
+		case LTE_STA_GET_SIGNAL:		//��ѯ�����ź�ǿ��
+			GSM_SendAtCmd("AT+CSQ", AT_CMD_CSQ_NO);
+			timer_restart(&responseTimeout);
+			nextStatus = LTE_STA_GET_SIGNAL_ACK;
+			break;
+			
+		case LTE_STA_GET_SIGNAL_ACK:		//�ȴ������ź�Ӧ������
+			if(at_cmd_table[AT_CMD_CSQ_NO-1].result == AT_CMD_SUCCESS)
+			{
+				if((signal > 0) && (signal != 99))
+				{
+					printf("\r\n�ź�ǿ�� = %d\r\n", signal);
+					nextStatus = LTE_STA_Handler_INIT;
+					break;
+				}
+			}
+			
+			if(timer_expired(&responseTimeout))						//��ʱ��δ���յ�Ӧ��
+			{
+				nextStatus = LTE_STA_Handler_INIT;	
+				break;
+			}
+			break;
+			
+		case LTE_STA_GET_DATE_TIME:		//��ȡ����ʱ��
+			GSM_SendAtCmd("AT+CCLK?", AT_CMD_CCLK_NO);
+			timer_restart(&responseTimeout);
+			nextStatus = LTE_STA_GET_DATE_TIME_ACK;
+			break;
+			
+		case LTE_STA_GET_DATE_TIME_ACK:		//��ȡ����ʱ��Ӧ��
+			if(at_cmd_table[AT_CMD_CCLK_NO-1].result == AT_CMD_SUCCESS)
+			{
+				getDateTimeMark = 1;
+				GMT_To_Beijing(&GMT_Time);
+				printf("\r\nTime:%s\r\n", systemTime);
+				nextStatus = LTE_STA_Handler_INIT;
+				break;
+			}
+			if(at_cmd_table[AT_CMD_CCLK_NO-1].result == AT_CMD_FAILED)
+			{
+				printf("\r\nGet Time ERROR\r\n");
+				nextStatus = LTE_STA_Handler_INIT;
+				break;
+			}
+			
+			if(timer_expired(&responseTimeout))						//��ʱ��δ���յ�Ӧ��
+			{
+				printf("\r\nӦ��ʱ��Get Timeʧ��\r\n");
+				nextStatus = LTE_STA_Handler_INIT;	
+				break;
+			}
+			break;
+			
+		case LTE_STA_HANDLER_FAILURE:		//���ݷ���ʧ��
+			printf("\r\n���ݷ���ʧ�ܷ��أ�\r\n");
+			
+			dataSendFailureMark = 1;											//��־���ݷ���ʧ��
+			
+			nextStatus = LTE_STA_Handler_INIT;
+			break;
+			
+		default:		//δ֪״̬
+			printf("\r\nException_δ֪״̬������ģ�飡����\r\n");
+			nextStatus = LTE_STA_Handler_INIT;
+			break;		
+	}
+	
+	if(lteHandlerResetFlag == 1)
+	{
+		lteHandlerResetFlag = 0;
+		
+		printf("\r\n�����շ����̸�λ��\r\n");
+			
+		dataSendFailureMark = 1;											//��־���ݷ���ʧ��
+		
+		nextStatus = LTE_STA_Handler_INIT;
+	}
+}
+
+/*
+***********************************************************************
+*	�� �� ��: LTE_WorkingStatusReset
+*	����˵��: LTEͨ��ģ�鹤��״̬��λ
+*	��    �Σ���
+*	�� �� ֵ: ��
+***********************************************************************
+*/
+static void LTE_WorkingStatusReset(void)
+{
+	//ģ�鹤�����̸�λ
+	lteLoadResetFlag = 1;											//��־ģ����ع���Ҫ���¸�λ
+	lteCreateSocketResetFlag = 1;							//��־Socket��������Ҫ���¸�λ
+	lteLoadCompletedFlag = 0;									//ģ�������ɱ�־����
+	lteCreateSocketOkFlag = 0;								//ģ�鴴��Socket��ɱ�־����
+	lteHandlerResetFlag = 1;									//��־�����շ����̸�λ
+	
+	//ģ������״̬��־��λ
+	ConnectionStatus = OFFLINE;
+	gsm_msg.Running = 0;
+	
+	//���̱�������
+	seriousError = 0;
+	sendFailureCount = 0;
+	errorProcessCount = 0;
+	connectionClosedMark = 0;
+}
+
+typedef enum
+{
+	LTE_ER_STA_INIT = 0,									//LTEģ���쳣������ʼ״̬
+	LTE_ER_STA_HANDLER,										//LTEģ���쳣����״̬
+	LTE_ER_STA_IDLE,											//LTEģ���쳣��������״̬
+}_LTE_ErrorStatus;
+/*
+***********************************************************************
+*	�� �� ��: LTE_ErrorHandler
+*	����˵��: LTEͨ��ģ���쳣��������
+*	��    �Σ���
+*	�� �� ֵ: ��
+***********************************************************************
+*/
+void LTE_ErrorHandler(void)
+{
+	static _LTE_ErrorStatus currentStatus = LTE_ER_STA_INIT;
+	static _LTE_ErrorStatus nextStatus = LTE_ER_STA_INIT;
+	
+	static timer responseTimeout;													//Ӧ��ʱʱ����
+	static timer sendTimeout;															//���ͳ�ʱʱ����
+	static timer waitingTimer;
+	
+	static uint8_t timer_ok = 0;
+	if(timer_ok == 0)
+	{
+		timer_ok = 1;
+		timer_set(&responseTimeout, CLOCK_SECOND*3);
+		timer_set(&sendTimeout, CLOCK_SECOND*10);
+		timer_set(&waitingTimer, CLOCK_SECOND*1);
+	}
+	
+	if(seriousError == 1)
+	{
+		seriousError = 0;
+		printf("\r\n�������ش���-->������\r\n");
+		LTE_WorkingStatusReset();
+	}
+	
+	if(sendFailureCount >= 3)										//����ʧ�ܳ���3�Σ�������ͨѶģ��
+	{
+		sendFailureCount = 0;
+		printf("\r\n����ʧ�ܴ�������Ԥ��ֵ-->������\r\n");
+		LTE_WorkingStatusReset();
+	}
+	
+	if(errorProcessCount >= 3)									//����ʧ�ܳ���3�Σ�������ͨѶģ��
+	{
+		errorProcessCount = 0;
+		printf("\r\n���й���ERROR��������Ԥ��ֵ-->������\r\n");
+		LTE_WorkingStatusReset();
+	}
+
+	if(connectionClosedMark == 1)								//�����ѶϿ�
+	{
+		connectionClosedMark = 0;
+		printf("\r\n�����ѶϿ���\r\n");
+		LTE_WorkingStatusReset();
+	}
+}
+
+/*
+***********************************************************************
+*	�� �� ��: GSM_GPRS_Task
+*	����˵��: GSM_GPRSͨѶ����
+*	��    �Σ���
+*	�� �� ֵ: ��
+***********************************************************************
+*/
+void GSM_GPRS_Task(void)
+{
+	EC200X_Loading();
+	TCP_ClientCreate();
+	TCP_ClientHandler();
+	LTE_ErrorHandler();
+}
+
+/******************** (C) COPYRIGHT 2017 CXHY *****END OF FILE*******************/
diff --git a/STM32_4路称重_Git提交精简工程/src/HARDWARE/GSM/ec200x.h b/STM32_4路称重_Git提交精简工程/src/HARDWARE/GSM/ec200x.h
new file mode 100755
index 0000000..066b910
--- /dev/null
+++ b/STM32_4路称重_Git提交精简工程/src/HARDWARE/GSM/ec200x.h
@@ -0,0 +1,37 @@
+/*************************** (C) COPYRIGHT 2017 CXHY ****************************
+ * �ļ���  ��gsm_gprs.h
+ * ��  ��  ��SIM900A����ͷ�ļ�     
+ * ��  ��  ��V1.0
+ * ��  ��  ��XuZhongPing
+ * ��  ��  ��2013/11/21 
+*********************************************************************************/
+#ifndef __EC200X_H__
+#define __EC200X_H__	 
+#include "stm32f10x.h"
+#include "stdio.h" 
+#include "gsm_uart_conf.h"
+	
+#define GSM_PW_KEY PBout(12)
+
+//�豸����״̬
+typedef enum
+{    
+  OFFLINE = 0, 							//���� 
+	ONLINE = 1								//����	
+
+}_ConnectionStatus;
+
+extern uint8_t GSM_isPowerON;												//GSMģ���Ƿ��ڿ���
+extern uint8_t ConnectionStatus;										//����״̬���������ݰ����ͳɹ�����λΪ����״̬��
+extern uint8_t connectionClosedMark;								//���ӶϿ���־
+
+extern uint16_t networkConnectionCount;							//�����������Ӵ���
+
+void LTE_Init(void);
+uint8_t GSM_PowerON(void);
+uint8_t GSM_PowerOFF(void);
+
+void GSM_GPRS_Task(void);
+#endif
+
+/******************** (C) COPYRIGHT 2017 CXHY *****END OF FILE*******************/ 
diff --git a/STM32_4路称重_Git提交精简工程/src/HARDWARE/GSM/gsm_gprs.c b/STM32_4路称重_Git提交精简工程/src/HARDWARE/GSM/gsm_gprs.c
new file mode 100755
index 0000000..a6b7b11
--- /dev/null
+++ b/STM32_4路称重_Git提交精简工程/src/HARDWARE/GSM/gsm_gprs.c
@@ -0,0 +1,1356 @@
+/*************************** (C) COPYRIGHT 2017 CXHY ****************************
+ * �ļ���  ��gsm_gprs.c
+ * ��  ��  ��gsm_gprs��������     
+ * ��  ��  ��V1.0
+ * ��  ��  ��XuZhongPing
+ * ��  ��  ��2017/06/12 
+*********************************************************************************/
+#include "gsm_gprs.h"
+#include "gsm_uart.h"		
+#include "gsm_uart_conf.h"
+#include "delay.h"	
+#include "led.h"   	  	 	 	 	  
+#include "string.h" 
+#include "stdio.h"
+#include "stdlib.h"   
+
+#include "timer.h"
+#include "data_typedef.h"	
+#include "message.h"
+#include "tcp_protocol.h"
+#include "at_proc.h"
+
+
+#define RCC_PeriphClock 	RCC_APB2Periph_GPIOB
+#define GSM_POW_KEY_Port 	GPIOB
+#define GSM_POW_KEY_Pin 	GPIO_Pin_12
+
+uint8_t GSM_isPowerON = 0x00;									//GSMģ���Ƿ��ڿ�����־
+uint8_t ConnectionStatus = OFFLINE;						//����״̬���������ݰ����ͳɹ�����λΪ����״̬��
+
+static uint8_t GSM_GPRS_Status = 0x00;				//GSM_GPRS�Ĺ���״̬
+static uint8_t GSM_GPRS_initStatus = 0x00;		//GSMģ�����ʱ�Ĺ�״̬
+static uint8_t TCP_createStatus = 0x00;				//GSMģ�齨��TCP����ʱ�Ĺ���״̬
+static uint8_t GSM_GPRS_workingState = 0x00;	//GSMģ��TCP�ͻ��˵������շ���������״̬
+static uint8_t errorStatus = 0x00;						//GSMģ���쳣������״̬
+static uint8_t errorProcessCount = 0;					//����������
+static uint8_t sendFailureCount = 0;					//����ʧ�ܼ���
+static uint8_t connectionFailureCount = 0;		//����ʧ�ܼ���
+
+
+/*
+***********************************************************************
+*	�� �� ��: GSM_GPRS_Init
+*	����˵��: GSM_GPRSģ���ʼ��
+*	��    ��: ��
+*	�� �� ֵ: ��
+***********************************************************************
+*/
+void GSM_GPRS_Init(void)
+{
+	GPIO_InitTypeDef  GPIO_InitStructure;
+ 	
+ 	RCC_APB2PeriphClockCmd(RCC_PeriphClock, ENABLE);	 			//ʹ��PB�˿�ʱ��
+	
+	//GSM���ػ��������ų�ʼ������
+ 	GPIO_InitStructure.GPIO_Pin = GSM_POW_KEY_Pin;	 				//�������˿�����
+ 	GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP; 		 		//�������
+ 	GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;				
+ 	GPIO_Init(GSM_POW_KEY_Port, &GPIO_InitStructure);				
+	GPIO_ResetBits(GSM_POW_KEY_Port, GSM_POW_KEY_Pin);			//Ĭ������ͣ��൱�ڿ���������û�а���״̬
+	
+	GSM_GPRS_Uart_Init();
+	gsm_msg.Running = 0;
+}
+
+/*
+***********************************************************************
+*	�� �� ��: GSM_StatusReset
+*	����˵��: GSM������״̬��λ
+*	��    �Σ���
+*	�� �� ֵ: ��
+***********************************************************************
+*/
+void GSM_StatusReset(void)
+{
+	GSM_GPRS_Status = 0x00;							//GSMģ�������ʱ��״̬��λ
+	GSM_GPRS_initStatus = 0x00;					//GSMģ�����ʱ��״̬��λ
+	TCP_createStatus = 0x00;						//GSMģ�鴴��TCP�ͻ�������ʱ��״̬��λ
+	GSM_GPRS_workingState = 0x00;				//GSMģ��TCP�ͻ��˵������շ���������״̬��λ
+	errorStatus = 0x00;									//GSMģ���쳣����ʱ��״̬��λ
+}
+   
+/*
+***********************************************************************
+*	�� �� ��: GSM_PowerON
+*	����˵��: GSMģ�鿪��
+*	��    ��: ��
+*	�� �� ֵ: ����������1�����ڿ������0
+***********************************************************************
+*/
+uint8_t GSM_PowerON(void)
+{
+	uint8_t returnData = 0;
+	static timer pullDown_Time;
+	static timer pullUp_Time;
+	static uint8_t timer_ok = 0;
+	
+	static uint8_t powerOnStatus = 0x00;
+	
+	if(timer_ok == 0)
+	{
+		timer_ok = 1;
+		timer_set(&pullDown_Time, CLOCK_SECOND*2);  		//����1����ʱ�������ڼ�������Ϊ�͵�ƽʱ��
+		timer_set(&pullUp_Time, CLOCK_SECOND*5);  			//����1����ʱ�������ڼ�������Ϊ�ߵ�ƽʱ��
+	}
+	switch(powerOnStatus)
+	{
+		case 0x00:			//�������״̬
+			printf("\r\nGSMģ�����ڿ���\r\n");	
+			GPIO_SetBits(GSM_POW_KEY_Port, GSM_POW_KEY_Pin);		//GSMģ���power_key��������		
+			powerOnStatus = 0x01;
+			timer_restart(&pullDown_Time);							//�ӵ�ǰʱ�����¿�����ʱ�� 
+			break;
+		case 0x01:			//��Լ�ȴ�2S�ӵ�ʱ�䣬power_key��������2S���ɿ�����ģ��		
+			if(timer_expired(&pullDown_Time))
+			{
+				GPIO_ResetBits(GSM_POW_KEY_Port, GSM_POW_KEY_Pin);				//GSMģ���power_key��������
+				powerOnStatus = 0x02;
+				timer_restart(&pullUp_Time);							//�ӵ�ǰʱ�����¿�����ʱ��
+				break;
+			}		
+			break;
+		case 0x02:
+			if(timer_expired(&pullUp_Time))
+			{
+				powerOnStatus = 0x00;
+				returnData = 1;
+			}
+			break;
+		default:break;
+	}
+	return returnData;
+}
+
+/*
+***********************************************************************
+*	�� �� ��: GSM_PowerOFF
+*	����˵��: GSMģ��ػ�
+*	��    ��: ��
+*	�� �� ֵ: ��
+***********************************************************************
+*/
+// uint8_t GSM_PowerOFF(void)
+// {
+// 	uint8_t returnData = 0;
+// 	static timer pullDown_Time;
+// 	static timer pullUp_Time;
+// 	static timer responseTimeout;
+// 	static uint8_t timer_ok = 0;
+// 	
+// 	static uint8_t powerOffStatus = 0x00;
+// 	
+// 	if(timer_ok == 0)
+// 	{
+// 		timer_ok = 1;
+// 		timer_set(&pullDown_Time, CLOCK_SECOND*2);  		//����1����ʱ�������ڼ�������Ϊ�͵�ƽʱ��
+// 		timer_set(&pullUp_Time, CLOCK_SECOND*2);  			//����1����ʱ�������ڼ�������Ϊ�ߵ�ƽʱ��
+// 		timer_set(&responseTimeout, CLOCK_SECOND*2);
+// 	}
+// 	switch(powerOffStatus)
+// 	{
+// 		case 0x00:
+// 			printf("\r\nGSMģ�����ڹػ�\r\n");
+// 			GPIO_SetBits(GSM_POW_KEY_Port, GSM_POW_KEY_Pin);							//GSMģ���power_key��������				
+// 			powerOffStatus = 0x01;
+// 			timer_restart(&pullDown_Time);								//�ӵ�ǰʱ�����¿�����ʱ�� 
+// 			break;
+// 			
+// 		case 0x01:
+// 			if(timer_expired(&pullDown_Time))
+// 			{
+// 				GPIO_ResetBits(GSM_POW_KEY_Port, GSM_POW_KEY_Pin);					//GSMģ���power_key��������
+// 				powerOffStatus = 0x02;
+// 				timer_restart(&pullUp_Time);
+// 			}
+// 			break;
+// 		case 0x02:
+// 			if(timer_expired(&pullUp_Time))
+// 			{
+// 				GSM_SendCmd("AT", 0, 0);
+// 				powerOffStatus = 0x03;
+// 				timer_restart(&responseTimeout);							//�ӵ�ǰʱ�����¿�����ʱ�� 
+// 			}
+// 			break;
+// 			
+// 		case 0x03:			//�ȴ�ģ��Ӧ��OK��		
+// 			if(timer_expired(&responseTimeout))						//��ʱ��δ���յ�Ӧ��
+// 			{
+// 				printf("\r\nģ���ѹػ�������\r\n");
+// 				powerOffStatus = 0x00;	
+// 				GSM_StatusReset();													//��λ���ֹ���״̬
+// 				returnData = 1;
+// 				break;
+// 			}else{
+// 				if(GSM_CheckCmd("OK"))
+// 				{
+// 					printf("\r\nģ�黹������\r\n");
+// 					powerOffStatus = 0x00;
+// 					break;
+// 				}
+// 				if(GSM_CheckCmd("AT"))
+// 				{
+// 					printf("\r\nģ�黹������\r\n");
+// 					powerOffStatus = 0x00;
+// 					break;
+// 				}
+// 			}
+// 			break;
+// 	}
+// 	return returnData;
+// }
+
+/*
+***********************************************************************
+*	�� �� ��: GSM_SignalCheck
+*	����˵��: ��ѯ�ź�����
+*	��    �Σ���
+*	�� �� ֵ: ��
+***********************************************************************
+*/
+void GSM_SignalCheck(void)
+{
+	uint8_t cnt = 0;
+	GSM_SendAtCmd("AT+CSQ", AT_CMD_CSQ_NO);
+	while((at_cmd_table[AT_CMD_CSQ_NO-1].result != AT_CMD_SUCCESS) && (cnt < 10))
+	{
+		delay_ms(1);
+		cnt++;
+	}
+	
+	if(at_cmd_table[AT_CMD_CSQ_NO-1].result == AT_CMD_SUCCESS)
+	{
+		if(signal > 0)
+		{
+			printf("\r\nGSM�ź�ǿ�� = %d\r\n", signal);
+			if(signal < 5)
+			{
+				printf("\r\nGSM�ź������������������Ƿ�����\r\n");
+			}
+		}else{
+			printf("\r\n��GSM�źţ�����\r\n");
+		}
+	}
+}
+
+/*
+***********************************************************************
+*	�� �� ��: GSM_GetHardInfo
+*	����˵��: ȡ��GSMģ���Ӳ����Ϣ��IMEI��
+*	��    ��: msg������GSMģ����Ϣ�ṹ��
+*	�� �� ֵ: ��
+***********************************************************************
+*/
+void GSM_GetHardInfo(_gsm_msg *msg)
+{
+// 	uint8_t *p;
+// 	
+// 	printf("\r\n��ȡIMEI��\r\n");
+// 	if(GSM_SendCmd("AT+CGSN", "OK", 200) == 0)						//��ѯ��Ʒ���к�
+// 	{ 
+// 		p = (uint8_t*)strstr((const char*)(GPRS_RX_BUF+2),"\r\n");	//���һس�
+// 		p[0] = 0;//��������� 
+// 		sprintf(msg->IMEI, "%s", GPRS_RX_BUF+2);
+// 		IMEI_TO_HEX(msg->IMEI);																	//���ַ�����IMEI��ת����HEX��ʽΪ���洫��
+// // 		printf("\r\nIMEI:%s\r\n", msg->IMEI);
+// 	}
+}
+
+/*
+***********************************************************************
+*	�� �� ��: GSM_Check
+*	����˵��: GSMģ����
+*	��    �Σ���
+*	�� �� ֵ: ��������1������������0
+***********************************************************************
+*/
+// uint8_t GSM_Check(void)
+// {
+// 	if(GSM_SendCmd("AT", "OK", 500))
+// 	{
+// 		return 0;	
+// 	}else{
+// 		return 1;
+// 	}
+// }
+
+/*
+***********************************************************************
+*	�� �� ��: GPRS_OnlineCheck
+*	����˵��: GPRS���̨������������飨��������������⣩
+*	��    �Σ���
+*	�� �� ֵ: ��
+***********************************************************************
+*/
+static void GPRS_OnlineCheck(void)
+{
+	sendMsg.msgType = 1001;														//����
+	MessageSend(MSG_FIFO_PROTOCOL, sendMsg);
+}
+
+/*
+***********************************************************************
+*	�� �� ��: GSM_GPRS_Reset
+*	����˵��: GSMģ����ֹ���״̬��λ������
+*	��    �Σ���
+*	�� �� ֵ: ��
+***********************************************************************
+*/
+static void GSM_GPRS_Reset(void)
+{
+	GSM_GPRS_Status = 0x00;								//ת����ʼ״̬����ģ��
+	GSM_GPRS_initStatus = 0x00;
+	TCP_createStatus = 0x00;
+	GSM_GPRS_workingState = 0x00;
+	errorStatus = 0x00;
+	
+	sendFailureCount = 0;	
+	errorProcessCount = 0;
+	connectionFailureCount = 0;
+	
+	ConnectionStatus = OFFLINE;
+	signal = 0;
+}
+
+/*
+***********************************************************************
+*	�� �� ��: GSM_GPRS_Loading
+*	����˵��: GSM_GPRSģ����أ���������ѯģ�������״̬��
+*	��    �Σ���
+*	�� �� ֵ: ��
+***********************************************************************
+*/
+void GSM_GPRS_Loading(void)
+{
+// 	static uint8_t GSM_GPRS_initStatus = 0;
+	static uint8_t waitTimeOutCount = 0;
+	
+	static timer responseTimeout;
+	static timer queryTime;
+	static uint8_t timer_ok = 0;
+	
+	if(timer_ok == 0)
+	{
+		timer_ok = 1;
+		timer_set(&responseTimeout, 3);  						//����1����ʱ�������ڷ���AT�����ȴ�Ӧ���ʱ��
+		timer_set(&queryTime, CLOCK_SECOND*2);  		//����1����ʱ�������ڲ�ѯ����ע�����
+	}
+	
+	switch(GSM_GPRS_initStatus)
+	{
+		case 0x00:			//�������״̬
+			if(GSM_PowerON())
+			{
+				GSM_GPRS_initStatus = 0x01;
+			}
+			break;
+			
+		case 0x01:			//���ģ���Ƿ���������
+			printf("\r\n���ģ��\r\n");
+			GSM_SendAtCmd("AT", AT_CMD_AT_NO);
+			GSM_GPRS_initStatus = 0x02;
+			timer_restart(&responseTimeout);							//�ӵ�ǰʱ�����¿�����ʱ�� 
+			break;
+			
+		case 0x02:			//�ȴ�ģ��Ӧ��OK��		
+			if(at_cmd_table[AT_CMD_AT_NO-1].result == AT_CMD_SUCCESS)
+			{
+				printf("\r\nģ������\r\n");
+				GSM_GPRS_initStatus = 0x03;									//���յ�Ӧ����ת��0x
+				break;
+			}
+			
+			if(timer_expired(&responseTimeout))						//��ʱ��δ���յ�Ӧ��
+			{
+				printf("\r\n��ʱδ��ģ��Ӧ��\r\n");
+				GSM_GPRS_initStatus = 0x00;		
+				break;
+			}
+			break;
+			
+		case 0x03:			//���ò�����
+			printf("\r\n���ò�����\r\n");
+			GSM_SendAtCmd("ATE0", AT_CMD_ATE0_NO);				//������							
+			GSM_GPRS_initStatus = 0x04;
+			timer_restart(&responseTimeout);
+			break;
+			
+		case 0x04:			//�ȴ�ATָ��Ӧ��
+			if(at_cmd_table[AT_CMD_ATE0_NO-1].result == AT_CMD_SUCCESS)
+			{
+				GSM_GPRS_initStatus = 0x05;								//���յ�Ӧ����ת��0x
+				break;
+			}
+			
+			if(timer_expired(&responseTimeout))						//��ʱ��δ���յ�Ӧ��
+			{
+				printf("\r\n���ò�����ʧ��\r\n");
+				GSM_GPRS_initStatus = 0x00;		
+				break;
+			}
+			break;
+			
+		case 0x05:			//��ȡӲ����Ϣ
+			GSM_SendAtCmd("AT+CGSN", AT_CMD_CGSN_NO);
+			GSM_GPRS_initStatus = 0x06;
+			timer_restart(&responseTimeout);
+			break;
+			
+		case 0x06:			//�ȴ�ATָ��Ӧ��			
+			if(at_cmd_table[AT_CMD_CGSN_NO-1].result == AT_CMD_SUCCESS)
+			{
+				printf("\r\nIMEI = %s\r\n", gsm_msg.IMEI);
+				waitTimeOutCount = 0;
+				GSM_GPRS_initStatus = 0x07;
+				break;
+			}
+			
+			if(timer_expired(&responseTimeout))						//��ʱ��δ���յ�Ӧ��
+			{
+				printf("\r\n��ȡӲ����Ϣ��ʱ\r\n");
+				GSM_GPRS_initStatus = 0x00;		
+				break;
+			}
+			break;
+			
+		case 0x07:			//��ѯSIM��״̬
+			if(waitTimeOutCount > 3)											//��ʱ��δ��ѯ������ע��״̬
+			{
+				waitTimeOutCount = 0;
+				GSM_GPRS_initStatus = 0x00;									//���ص���ʼ״̬
+				printf("\r\n��ѯSIM��״̬��ʱ��SIM����Ч������\r\n");
+				break;
+			}
+			GSM_SendAtCmd("AT+CPIN?", AT_CMD_CPIN_NO);
+			GSM_GPRS_initStatus = 0x08;
+			timer_restart(&queryTime);
+			break;	
+			
+		case 0x08:			//�ȴ�ATָ��Ӧ��
+			if(at_cmd_table[AT_CMD_CPIN_NO-1].result == AT_CMD_SUCCESS)
+			{
+				printf("\r\nSIM���Ѿ�����\r\n");
+				printf("\r\n��ѯ�ź�ǿ��\r\n");
+				waitTimeOutCount = 0;	
+				GSM_GPRS_initStatus = 0x09;
+				break;
+			}
+			
+			if(timer_expired(&queryTime))						//��ʱ��δ���յ�Ӧ��
+			{
+				GSM_GPRS_initStatus = 0x07;	
+				waitTimeOutCount++;										//�ȴ���ʱ����+1
+				break;
+			}
+			break;
+			
+		case 0x09:		//��ѯ�����ź�ǿ��
+			if(waitTimeOutCount > 10)											//��ʱ��δ��ѯ������ע��״̬
+			{
+				waitTimeOutCount = 0;
+				GSM_GPRS_initStatus = 0x00;									//���ص���ʼ״̬
+				printf("\r\n��ѯ���������źţ�����\r\n");
+				break;
+			}
+			GSM_SendAtCmd("AT+CSQ", AT_CMD_CSQ_NO);
+			GSM_GPRS_initStatus = 0x10;
+			timer_restart(&queryTime);							//�ӵ�ǰʱ�����¿�����ʱ��
+			break;
+			
+		case 0x10:		//�ȴ������ź�Ӧ������
+			if(at_cmd_table[AT_CMD_CSQ_NO-1].result == AT_CMD_SUCCESS)
+			{
+				if(signal > 0)
+				{
+					printf("\r\n�ź�ǿ������ = %d\r\n", signal);
+					printf("\r\n��ѯ����ע��״̬\r\n");
+					waitTimeOutCount = 0;											//�ȴ���ʱ��������
+					GSM_GPRS_initStatus = 0x11;
+					break;
+				}
+			}
+			
+			if(timer_expired(&queryTime))						//��ʱ��δ���յ�Ӧ��
+			{
+				GSM_GPRS_initStatus = 0x09;	
+				waitTimeOutCount++;										//�ȴ���ʱ����+1
+				break;
+			}
+			break;
+			
+		case 0x11:			//��ѯ����ע��״̬
+			if(waitTimeOutCount > 10)											//��ʱ��δ��ѯ������ע��״̬
+			{
+				waitTimeOutCount = 0;
+				GSM_GPRS_initStatus = 0x00;									//���ص���ʼ״̬
+				printf("\r\n�ȴ���ʱ����δע�����磡����\r\n");
+				break;
+			}
+			GSM_SendAtCmd("AT+CREG?", AT_CMD_CREG_NO);
+			GSM_GPRS_initStatus = 0x12;
+			timer_restart(&queryTime);							//�ӵ�ǰʱ�����¿�����ʱ��
+			break;
+			
+		case 0x12:			//�ȴ�����ע��ɹ�			
+			if(at_cmd_table[AT_CMD_CREG_NO-1].result == AT_CMD_SUCCESS)
+			{
+				printf("\r\n�Ѿ�ע������\r\n");
+				printf("\r\n��ѯ�Ƿ���GPRSҵ��\r\n");
+				waitTimeOutCount = 0;											//�ȴ���ʱ��������
+				GSM_GPRS_initStatus = 0x13;
+				break;
+			}
+			
+			if(timer_expired(&queryTime))						//��ʱ��δ���յ�Ӧ��
+			{
+				GSM_GPRS_initStatus = 0x11;	
+				waitTimeOutCount++;										//�ȴ���ʱ����+1
+				break;
+			}
+			break;
+			
+		case 0x13:			//���GPRS����״̬
+			if(waitTimeOutCount > 10)											//��ʱ��δ��ѯ��GPRS����״̬
+			{
+				waitTimeOutCount = 0;
+				GSM_GPRS_initStatus = 0x00;									//���ص���ʼ״̬
+				printf("\r\n�ȴ���ʱ����δ����GPRS\r\n");
+				break;
+			}
+			GSM_SendAtCmd("AT+CGATT?", AT_CMD_CGATT_NO);	//���GPRS����״̬						
+			GSM_GPRS_initStatus = 0x14;
+			timer_restart(&queryTime);										//�ӵ�ǰʱ�����¿�����ʱ��
+			break;
+			
+		case 0x14:		//�ȴ�����GPRSҵ��		
+			if(at_cmd_table[AT_CMD_CGATT_NO-1].result == AT_CMD_SUCCESS)
+			{
+				waitTimeOutCount = 0;											//�ȴ���ʱ��������
+				GSM_GPRS_initStatus = 0x00;	
+				printf("\r\n�Ѿ�����GPRSҵ��\r\n");
+				GSM_GPRS_Status = 0x01;	
+				break;
+			}
+			
+			if(timer_expired(&queryTime))									//��ʱ��δ���յ�Ӧ��
+			{
+				GSM_GPRS_initStatus = 0x13;	
+				waitTimeOutCount++;													//�ȴ���ʱ����+1
+				break;
+			}
+			break;
+			
+		default: 
+			GSM_GPRS_initStatus = 0x00;
+			break;
+	}
+}
+
+/*
+***********************************************************************
+*	�� �� ��: TCP_ClientCreate
+*	����˵��: ����TCP�ͻ���
+*	��    �Σ���
+*	�� �� ֵ: ��
+***********************************************************************
+*/
+void TCP_ClientCreate(void)
+{
+// 	static uint8_t createStatus = 0x00;
+	
+	static timer responseTimeout;
+	static timer responseTimeout_3s;
+	static timer registrationTime;
+	static timer connectionWaitTime;
+	static timer waitingTime_2s;
+	static timer reconnectTimeout;
+	static uint8_t timer_ok = 0;
+	
+	if(timer_ok == 0)
+	{
+		timer_ok = 1;
+		timer_set(&responseTimeout, 3);  									//����1����ʱ�������ڷ���AT�����ȴ�Ӧ���ʱ��
+		timer_set(&responseTimeout_3s, CLOCK_SECOND*3);  	//����1����ʱ�������ڷ���AT�����ȴ�Ӧ���ʱ��
+		timer_set(&connectionWaitTime, CLOCK_SECOND*10);  //����1����ʱ�������ڽ������ӵȴ��ĳ�ʱʱ��
+		timer_set(&registrationTime, CLOCK_SECOND*10);  	//����1����ʱ�������ڼ������ע������ĵȴ���ʱʱ��
+		timer_set(&waitingTime_2s, CLOCK_SECOND*2);
+		timer_set(&reconnectTimeout, CLOCK_SECOND*20);
+	}
+	
+	switch(TCP_createStatus)
+	{	
+		case 0x00:			//��ʼ����TCP����
+			printf("\r\n��ʼ��������APN\r\n");
+			GSM_SendAtCmd("AT+CSTT=\"CMNET\"", AT_CMD_CSTT_NO);			//����GPRS�ƶ�̨���ΪB,֧�ְ����������ݽ��� 			
+			TCP_createStatus = 0x01;
+			timer_restart(&responseTimeout);							//�ӵ�ǰʱ�����¿���2�붨ʱ��
+			timer_restart(&reconnectTimeout);							//��ʼ���������ȳ�ʼ����ʱ���������ʱ�ˣ�����Ҫ���¿���
+			break;
+			
+		case 0x01:			//�ȴ�Ӧ��		
+			if(at_cmd_table[AT_CMD_CSTT_NO-1].result == AT_CMD_SUCCESS)
+			{
+				printf("\r\n����APN OK\r\n");
+				TCP_createStatus = 0x02;									//���յ�Ӧ����ת��0x02
+				break;
+			}
+			if(at_cmd_table[AT_CMD_CSTT_NO-1].result == AT_CMD_FAILED)
+			{
+				printf("\r\n����APN ERROR\r\n");
+				TCP_createStatus = 0x20;									//Ӧ�������ת��0x
+				break;
+			}
+			
+			if(timer_expired(&responseTimeout))						//��ʱ��δ���յ�Ӧ��
+			{
+				printf("\r\n�ȴ�Ӧ��ʱ������APN����\r\n");
+				TCP_createStatus = 0x20;	
+				break;
+			}
+			break;
+
+		case 0x02:			//����������·
+			printf("\r\n����������·\r\n");
+			GSM_SendAtCmd("AT+CIICR", AT_CMD_CIICR_NO);		//����PDP������,��������Э��,��������Ϣ
+			TCP_createStatus = 0x03;
+			timer_restart(&responseTimeout_3s);							//�ӵ�ǰʱ�����¿���2�붨ʱ��
+			break;
+			
+		case 0x03:			//�ȴ�Ӧ��				
+			if(at_cmd_table[AT_CMD_CIICR_NO-1].result == AT_CMD_SUCCESS)
+			{
+				printf("\r\n����������·OK\r\n");
+				TCP_createStatus = 0x04;									//���յ�Ӧ����ת��0x
+				break;
+			}
+			if(at_cmd_table[AT_CMD_CIICR_NO-1].result == AT_CMD_FAILED)
+			{
+				printf("\r\n����������· ERROR\r\n");
+				TCP_createStatus = 0x20;									//Ӧ�������ת��0x00
+				break;
+			}
+			
+			if(timer_expired(&responseTimeout_3s))						//��ʱ��δ���յ�Ӧ��
+			{
+				printf("\r\nӦ��OK��ʱ������������·ʧ��\r\n");
+				TCP_createStatus = 0x20;	
+				break;
+			}
+			break;
+		
+		case 0x04:			//���ý���������ʾIPͷ
+			printf("\r\n���ý���������ʾIPͷ\r\n");
+			GSM_SendAtCmd("AT+CIPHEAD=1", AT_CMD_CIPHEAD_NO);	 	//���ý���������ʾIPͷ(�����ж�������Դ)
+			TCP_createStatus = 0x05;
+			timer_restart(&responseTimeout);							//�ӵ�ǰʱ�����¿���2�붨ʱ��
+			break;
+			
+		case 0x05:			
+			if(at_cmd_table[AT_CMD_CIPHEAD_NO-1].result == AT_CMD_SUCCESS)
+			{
+				printf("\r\n���ý���������ʾIPͷOK\r\n");
+				TCP_createStatus = 0x06;									//���յ�Ӧ����ת��0x
+				break;
+			}
+			if(at_cmd_table[AT_CMD_CIPHEAD_NO-1].result == AT_CMD_FAILED)
+			{
+				printf("\r\n���ý���������ʾIPͷʧ��\r\n");
+				TCP_createStatus = 0x20;									//Ӧ�������ת��0x
+				break;
+			}
+			
+			if(timer_expired(&responseTimeout))						//��ʱ��δ���յ�Ӧ��
+			{
+				printf("\r\nӦ��OK��ʱ�����ý���������ʾIPͷʧ��\r\n");
+				TCP_createStatus = 0x20;	
+				break;
+			}
+			break;
+	
+		case 0x06:			//��ñ���IP
+			printf("\r\n��ñ���IP\r\n");
+			GSM_SendAtCmd("AT+CIFSR", AT_CMD_CIFSR_NO);
+			TCP_createStatus = 0x07;
+			timer_restart(&responseTimeout);							//�ӵ�ǰʱ�����¿���n�붨ʱ��
+			break;
+			
+		case 0x07:
+			if(at_cmd_table[AT_CMD_CIFSR_NO-1].result == AT_CMD_SUCCESS)
+			{
+				printf("\r\n�ѻ��IP��ַ\r\n");
+				TCP_createStatus = 0x08;									//���յ�Ӧ����ת��0x
+				break;
+			}
+			if(at_cmd_table[AT_CMD_CIFSR_NO-1].result == AT_CMD_FAILED)
+			{
+				printf("\r\n��ñ���IPʧ�� ERROR\r\n");
+				TCP_createStatus = 0x20;									//Ӧ�������ת��0x00
+				break;
+			}
+			
+			if(timer_expired(&responseTimeout))						//��ʱ��δ���յ�Ӧ��
+			{
+				printf("\r\nӦ��OK��ʱ����ñ���IPʧ��\r\n");
+				TCP_createStatus = 0x20;	
+				break;
+			}
+			break;
+			
+		case 0x08:			//��ʼ����Զ�˷�����
+			printf("\r\n��ʼ����Զ�˷�����\r\n");
+			GSM_SendAtCmd(TCP_IP_COM, AT_CMD_CIPSTART_NO);		//��ʼ����Զ�˷�����
+			TCP_createStatus = 0x09;
+			timer_restart(&connectionWaitTime);						//�ӵ�ǰʱ�����¿�����ʱ��
+			break;	
+			
+		case 0x09:			//�ȴ�Ӧ��CONNECT OK��								
+			if(at_cmd_table[AT_CMD_CIPSTART_NO-1].result == AT_CMD_SUCCESS)
+			{
+				printf("\r\n���ӳɹ�\r\n");
+				
+				//�������ʧ�ܼ����������Ӵ��������Ϊ�˷�ֹ�ڳ������й����г��ִ���������������ģ�鸴λ������
+				sendFailureCount = 0;
+				errorProcessCount = 0;
+				connectionFailureCount = 0;
+				
+				TCP_createStatus = 0x00;											
+				gsm_msg.Running = 1;											//��־ģ���Ѿ�������GPRS
+				
+				//���ӳɹ���������
+				sendMsg.msgType = 1001;														//����
+				MessageSend(MSG_FIFO_PROTOCOL, sendMsg);
+				
+				sendMsg.msgType = 6004;														//�ϴ��豸����״̬��Ϣ���¶ȡ��źš���ࣩ
+				MessageSend(MSG_FIFO_PROTOCOL, sendMsg);
+				
+// 					GSM_SendCmd("AT+CSCLK=2", "OK", 200);			//����ģʽ����
+// 					GSM_SendCmd("AT+CFUN=1", "OK", 200);		
+				
+				GSM_GPRS_Status = 0x02;										//����TCP���ӳɹ���ת�������շ��Ĵ���״̬
+				break;
+			}
+			
+			if(at_cmd_table[AT_CMD_CIPSTART_NO-1].result == AT_CMD_FAILED)
+			{
+				printf("\r\n����ʧ��\r\n");
+				TCP_createStatus = 0x20;
+				break;
+			}
+			
+			if(timer_expired(&connectionWaitTime))				//��ʱ��δ���յ�Ӧ��
+			{
+				printf("\r\n���ӳ�ʱ!!!\r\n");		
+				TCP_createStatus = 0x20;
+				break;
+			}
+			
+			break;
+			
+		case 0x10:		//��ѯGPRS״̬���ʱ��
+			timer_restart(&waitingTime_2s);
+			TCP_createStatus = 0x11;
+			break;
+			
+		case 0x11:		
+			if(timer_expired(&waitingTime_2s))
+			{
+				TCP_createStatus = 0x20;
+			}
+			break;
+			
+		case 0x20:			//��ѯGPRS״̬
+			if(timer_expired(&reconnectTimeout))
+			{
+				printf("\r\n����TCP���ӳ�ʱ������ģ�飡����\r\n");
+				
+				GSM_GPRS_Reset();							//GSMģ�鸴λ������
+				break;
+			}
+			
+			connectionFailureCount++;				//����ʧ�ܼ���
+			printf("\r\n�����쳣���� %d ��\r\n", connectionFailureCount);
+			if(connectionFailureCount >= 10)		//������5�λ����ָ�������������ģ��
+			{
+				//ִ�е���һ����ת��ģ�鸴λ����
+				GSM_GPRS_Reset();							//GSMģ�鸴λ������	
+				printf("\r\n�����쳣�����쳣��������������ģ�飡����\r\n");
+				break;
+			}
+			
+			printf("\r\n��ѯGPRS״̬\r\n");
+			GSM_SendAtCmd("AT+CIPSTATUS", AT_CMD_CIPSTATUS_NO);			//��ѯ����״̬				
+			TCP_createStatus = 0x21;	
+			timer_restart(&responseTimeout_3s);				//�ӵ�ǰʱ�����¿�����ʱ��
+			break;
+			
+		case 0x21:		//����GPRS�ĸ�������״̬
+			switch(at_cmd_table[AT_CMD_CIPSTATUS_NO-1].result)
+			{
+				case GPRS_STATUS_IP_INITIAL:		//GPRS��ʼ��					
+					printf("\r\nGPRS��ʼ��\r\n");
+					TCP_createStatus = 0x00;							
+					break;
+				
+				case GPRS_STATUS_IP_START:		//��ʼTCP/UDP�Ự					
+					printf("\r\n��ʼTCP/UDP�Ự\r\n");
+					TCP_createStatus = 0x02;							
+					break;
+					
+				case GPRS_STATUS_IP_CONFIG:		//����PDP������					
+					printf("\r\n����PDP������\r\n");
+					TCP_createStatus = 0x10;			//������ѯGPRS��״̬						
+					break;
+					
+				case GPRS_STATUS_IP_GPRSACT:	
+					TCP_createStatus = 0x04;							
+					printf("\r\n�������Ѿ�����\r\n");
+					break;
+					
+				case GPRS_STATUS_IP_STATUS:		//�õ�����IP��ַ
+					printf("\r\n�õ�����IP��ַ\r\n");
+					TCP_createStatus = 0x08;							
+					break;
+					
+				case GPRS_STATUS_TCP_CONNECTING:		//��������
+					printf("\r\n�������ӷ�����\r\n");
+					TCP_createStatus = 0x10;							
+					break;
+					
+				case GPRS_STATUS_CONNECT_OK:		//��������
+					printf("\r\n��������\r\n");
+					//�������ʧ�ܼ����������Ӵ��������Ϊ�˷�ֹ�ڳ������й����г��ִ���������������ģ�鸴λ������
+					sendFailureCount = 0;
+					errorProcessCount = 0;
+					
+					TCP_createStatus = 0x00;											
+					gsm_msg.Running = 1;											//��־ģ���Ѿ�������GPRS
+					
+					GSM_GPRS_Status = 0x02;										//����TCP���ӳɹ���ת�������շ��Ĵ���״̬
+					
+					break;
+					
+				case GPRS_STATUS_TCP_CLOSING:
+					printf("\r\n���ڹر�����\r\n");
+					TCP_createStatus = 0x10;				//������ѯGPRS״̬				
+					break;
+					
+				case GPRS_STATUS_TCP_CLOSED:
+					printf("\r\n�����Ѿ��ر���\r\n");
+					TCP_createStatus = 0x30;							
+					break;
+					
+				case GPRS_STATUS_PDP_DEACT:		//�������Ѿ��ر�
+					printf("\r\nPDP������ȥ����\r\n");
+					TCP_createStatus = 0x30;								
+					break;
+						
+				default:
+					break;
+			}
+			
+			if(timer_expired(&responseTimeout_3s))			//��ʱ��δ���յ�Ӧ��
+			{
+				printf("\r\nGPRS״̬��ѯ��ʱû��Ӧ��\r\n");
+				TCP_createStatus = 0x20;
+				break;
+			}
+			
+			break;
+		
+		case 0x30:		//�ر��ƶ�����
+			printf("\r\n�ر��ƶ�����\r\n");
+			GSM_SendAtCmd("AT+CIPSHUT", AT_CMD_CIPSHUT_NO);				//�ر��ƶ�����
+			TCP_createStatus = 0x31;
+			timer_restart(&responseTimeout_3s);						//�ӵ�ǰʱ�����¿�����ʱ��
+			break;
+			
+		case 0x31:		//�ȴ��ر��ƶ�����Ӧ��
+			if(at_cmd_table[AT_CMD_CIPSHUT_NO-1].result == AT_CMD_SUCCESS)
+			{
+				printf("\r\n�ر��ƶ������ɹ�\r\n");
+				TCP_createStatus = 0x00;									//���յ�Ӧ����ת��0x
+				break;
+			}
+			if(at_cmd_table[AT_CMD_CIPSHUT_NO-1].result == AT_CMD_FAILED)
+			{
+				printf("\r\n�ر��ƶ�����ʧ��\r\n");
+				TCP_createStatus = 0x20;
+				break;
+			}
+			
+			if(timer_expired(&responseTimeout_3s))						//��ʱ��δ���յ�Ӧ��
+			{
+				printf("\r\n�ر��ƶ�������ʱδӦ��\r\n");
+				TCP_createStatus = 0x20;	
+				break;
+			}
+			break;
+
+		default: 		//����״̬
+			printf("\r\nδ֪״̬������ģ�飡����\r\n");
+			GSM_GPRS_Reset();							//GSMģ�鸴λ������
+			break;	
+	}
+}
+
+/*
+***********************************************************************
+*	�� �� ��: TCP_ClientHandler
+*	����˵��: TCP�ͻ��˵������շ�����
+*	��    �Σ���
+*	�� �� ֵ: ��
+***********************************************************************
+*/
+void TCP_ClientHandler(void)
+{
+	static Com_ProtocolMessage *pMsg;
+// 	static uint8_t GSM_GPRS_workingState = 0x00;
+	static uint16_t sendDataSize = 0;
+// 	static uint8_t sendFailureCount = 0;								//����ʧ�ܼ���
+	
+	static timer uploadIntervalTime;											//�����ϴ�ʱ�������ƣ�����ͬһʱ�����ظ��ϴ���������
+	static timer responseTimeout;													//Ӧ��ʱʱ����
+	static timer sendTimeout;															//���ͳ�ʱʱ����
+	
+	static uint8_t timer_ok = 0;
+	if(timer_ok == 0)
+	{
+		timer_ok = 1;
+		timer_set(&uploadIntervalTime, CLOCK_SECOND*3);  			
+		timer_set(&responseTimeout, CLOCK_SECOND*3);
+		timer_set(&sendTimeout, CLOCK_SECOND*10);
+	}
+	
+	switch(GSM_GPRS_workingState)
+	{			
+		case 0x00:				//��ǰ������������������Ƿ�������Ҫ���ͣ��оͶ����ݽ��з���
+			pMsg = MessageGet(MSG_FIFO_PROTOCOL);					//��ȡ��Ϣ����
+			if(pMsg){		//�����Ϣ����������Ϣ��������ݷ���
+// 				printf("\r\n������Ҫ���ͣ����ڼ���......\r\n");
+				GSM_GPRS_workingState = 0x01;								//��ת����������
+// 				printf("\r\npThis->msgType = %x\r\n", pThis->msgType);
+// 				printf("\r\npThis->msgData = %x\r\n", pThis->msgData);
+			}else{
+				GSM_GPRS_workingState = 0x00;								
+			}
+			break;
+			
+		case 0x01:				//����AT+CIPSEND����
+			sendOrderCode = pMsg->msgType;										//ȡ�÷��͵�Э����
+			
+			//������ʱ��Ͽ����ӻ�ѹ��δ������������ͬһʱ������ظ�����
+			if(sendOrderCode == 1001)
+			{
+				if(ConnectionStatus == ONLINE)									//��ǰ��������״̬				
+				{
+					if(timer_expired(&uploadIntervalTime))				//����һ�η���������ʱ�䳬���趨ֵ�������������ͣ�
+					{
+						timer_restart(&uploadIntervalTime);					
+					}else{																				//����һ�η���������ʱ����̣����������������ϴ���					
+						GSM_GPRS_workingState = 0x00;		
+						printf("\r\n��������������ȡ������\r\n");
+						timer_restart(&uploadIntervalTime);					//���¿�����ʱ��Ϊһ�´��ж���׼��
+						break;		//����
+					}
+				}else{																					//��ǰ��������״̬���з���ʧ�ܾ�������״̬Ϊ����״̬��
+					timer_restart(&uploadIntervalTime);						//���¿�����ʱ��Ϊһ�´��ж���׼��
+				}
+			}			
+			
+			sendDataSize = ProtocolPackaging(sendOrderCode);	//ͨ����Ϣ�����ͽ�����ӦЭ����
+			getCommand_CIPSEND(sendDataSize);									//ȡ�÷���ָ����������ATָ��
+			
+			//ֹͣ���̨�������ݵ�����
+// 			GSM_GPRS_workingState = 0x00;
+			
+// 			printf("\r\n�������� %s\r\n", command_CIPSEND);
+			GSM_SendAtCmd(command_CIPSEND, AT_CMD_CIPSEND_NO);								//������������"AT+CIPSEND=<len>"
+			GSM_GPRS_workingState = 0x02;
+			timer_restart(&responseTimeout);									//�ӵ�ǰʱ�����¿�����ʱ��
+			break;
+			
+		case 0x02:				//�ȴ�����Ӧ��>��	
+			if(at_cmd_table[AT_CMD_CIPSEND_NO-1].result == AT_CMD_CIPSEND_READY)
+			{
+				printf("\r\nӦ�� > OK\r\n");
+				GSM_GPRS_workingState = 0x03;							//���յ�Ӧ��					
+				break;
+			}
+			
+			if(at_cmd_table[AT_CMD_CIPSEND_NO-1].result == AT_CMD_SEND_FAIL)
+			{
+				printf("\r\nӦ��> ERROR\r\n");
+				sendFailureCount ++;											//����ʧ��+1
+				printf("\r\n����ʧ�ܴ��� = %d\r\n", sendFailureCount);
+				
+				//���յ�ERRORӦ��ʱֱ��ת��������
+				GSM_GPRS_Status = 0x03;										//��ת������������
+				GSM_GPRS_workingState = 0x00;							//�ص���ʼ״̬������������ɺ�ӳ�ʼ����������
+				break;
+			}
+			
+			if(at_cmd_table[AT_CMD_CIPSEND_NO-1].result == TCP_STATUS_CLOSED)
+			{
+				printf("\r\n�����Ѿ��رգ�����ʧ��\r\n");
+				sendFailureCount ++;											//����ʧ��+1
+				printf("\r\n����ʧ�ܴ��� = %d\r\n", sendFailureCount);
+				
+				//���յ�CLOSEDӦ��ʱֱ��ת��������
+				GSM_GPRS_Status = 0x03;										//��ת������������
+				GSM_GPRS_workingState = 0x00;							//�ص���ʼ״̬������������ɺ�ӳ�ʼ����������						
+				break;
+			}
+			
+			if(timer_expired(&responseTimeout))						//��ʱ��δ���յ�Ӧ��
+			{
+				printf("\r\n��ʱδӦ��>ȡ������\r\n");	
+				sendFailureCount ++;												//����ʧ��+1
+				
+				GSM_GPRS_workingState = 0x06;								//���ص����ӳɹ�״̬
+				break;
+			}
+			break;
+			
+		case 0x03:				//ͨ��������ģ�鷢��Ҫ���͵�����
+			memcpy(GPRS_TX_BUF, GPRS_DATA_BUF, sendDataSize);
+			GSM_GPRS_SendOne(sendDataSize);
+			printf("\r\nTCP Sending data......\r\n");
+// 			printf("\r\nStartTime = %d\r\n", time_value);
+			GSM_GPRS_workingState = 0x04;
+			break;
+			
+		case 0x04:				//���ͽ������ݷ�������
+			GSM_GPRS_workingState = 0x05;
+			timer_restart(&sendTimeout);									//�ӵ�ǰʱ�����¿���N�붨ʱ��
+			break;
+			
+		case 0x05:				//�ȴ�����Ӧ��SEND OK��		
+			if(at_cmd_table[AT_CMD_CIPSEND_NO-1].result == AT_CMD_CIPSEND_OK)
+			{
+// 				printf("\r\nEndTime = %d\r\n", time_value);
+				printf("\r\n���ͳɹ�\r\n");
+				
+				ConnectionStatus = ONLINE;								//�����ͳɹ�ʱ��������״̬Ϊ����״̬
+				
+				SetSendProcotolSuccess();									//���ñ��η��͵�Э���ѳɹ�����
+				
+				sendFailureCount = 0;											//�����ͳɹ�������ʧ�ܼ�������
+				errorProcessCount = 0;										//�������ݳɹ���������������
+				
+				if(sendOrderCode == 1001)									//���������ɹ����ѯGSM�ź�ǿ��
+				{
+					GSM_SignalCheck();											//��ѯ�ź�����
+				}
+				GSM_GPRS_workingState = 0x00;							//���յ�Ӧ��
+				break;
+			}
+			
+			if(at_cmd_table[AT_CMD_CIPSEND_NO-1].result == AT_CMD_SEND_FAIL)
+			{
+				printf("\r\nEndTime = %d\r\n", time_value);
+				printf("\r\n����ʧ��\r\n");
+				
+				ConnectionStatus = OFFLINE;								//������ʧ��ʱ��������״̬Ϊ����״̬	
+				sendFailureCount ++;											//����ʧ��+1
+				
+				//������ʧ��ʱ���������������GPRS���̨�����Ƿ�����
+				GPRS_OnlineCheck();
+				
+				GSM_GPRS_workingState = 0x06;							
+				break;
+			}
+			
+			if(timer_expired(&sendTimeout))							//��ʱ��δ���յ�Ӧ��
+			{
+				printf("\r\nEndTime = %d\r\n", time_value);
+				printf("\r\n��ʱ������δ����������ʧ��\r\n");
+				
+				ConnectionStatus = OFFLINE;								//������ʧ��ʱ��������״̬Ϊ����״̬	
+				sendFailureCount ++;											//����ʧ��+1
+				
+				//������ʧ��ʱ���������������GPRS���̨�����Ƿ�����
+				GPRS_OnlineCheck();
+				
+				GSM_GPRS_workingState = 0x06;							//���ص����ӳɹ�״̬
+				break;
+			}
+			break;
+			
+		case 0x06:		//����Ƿ񳬳�����ʧ�ܴ���
+			printf("\r\n��ǰ�ѷ���ʧ�ܴ��� = %d\r\n", sendFailureCount);
+			if(sendFailureCount > 0)		//�������ݷ���ʧ�����ȼ��GSM�ź��Ƿ�����
+			{
+				GSM_SignalCheck();
+			}
+			
+			if(sendFailureCount >= 3)		//��������ʧ�ܴ�������Ҫ���д�����
+			{
+				printf("\r\n��������ʧ�ܴ�����ת��������\r\n");
+				GSM_GPRS_workingState = 0x00;
+				GSM_GPRS_Status = 0x03;											//��ת������������
+				break;
+			}else{
+				GSM_GPRS_workingState = 0x00;
+			}
+			break;
+			
+		default:		//δ֪״̬
+			GSM_GPRS_Reset();							//GSMģ�鸴λ������
+			
+			printf("\r\nException_δ֪״̬������ģ�飡����\r\n");
+			break;		
+	}
+}
+
+/*
+***********************************************************************
+*	�� �� ��: TCP_ErrorHandler
+*	����˵��: TCP���ӹ����еĴ�����
+*	��    �Σ���
+*	�� �� ֵ: ��
+***********************************************************************
+*/
+void TCP_ErrorHandler(void)
+{
+// 	static uint8_t errorStatus = 0x00;	
+	
+	static timer responseTimeout;
+	static timer waitTCPConnectTime;
+	static timer waitingTime2s;					//2S��ʱ
+	
+	static uint8_t timer_ok = 0;
+	if(timer_ok == 0)
+	{
+		timer_ok = 1;
+		timer_set(&responseTimeout, CLOCK_SECOND*3); 
+		timer_set(&waitTCPConnectTime, CLOCK_SECOND*10);
+		timer_set(&waitingTime2s, CLOCK_SECOND*2);
+	}
+	
+	switch(errorStatus)
+	{	
+		case 0x00:				//��ѯGPRS��״̬	
+			ConnectionStatus = OFFLINE;								//������ʧ��ʱ��������״̬Ϊ����״̬
+			
+			//�Ƚ����쳣����������飬������ģ������
+			errorProcessCount++;									//����������+1
+			printf("\r\nException_�쳣���� %d ��\r\n", errorProcessCount);
+			if(errorProcessCount >= 5)		//������5�λ����ָ�������������ģ��
+			{
+				//ִ�е���һ����ת��ģ�鸴λ����
+				GSM_GPRS_Reset();							//GSMģ�鸴λ������	
+				printf("\r\nException_�����쳣��������������ģ�飡����\r\n");
+				break;
+			}
+			
+			printf("\r\nException_��ѯGPRS״̬\r\n");
+			GSM_SendAtCmd("AT+CIPSTATUS", AT_CMD_CIPSTATUS_NO);			//��ѯ����״̬				
+			errorStatus = 0x01;	
+			timer_restart(&responseTimeout);				//�ӵ�ǰʱ�����¿�����ʱ��
+			break;
+			
+		case 0x01:		//���ݵ�ǰGPRS�Ĺ���״̬������Ӧ����
+			switch(at_cmd_table[AT_CMD_CIPSTATUS_NO-1].result)
+			{
+				case GPRS_STATUS_IP_INITIAL:	
+					printf("\r\nException_GPRS��ʼ��\r\n");
+					errorStatus = 0x12;			//ת���ر��ƶ�����				
+					break;
+				
+				case GPRS_STATUS_IP_START:
+					printf("\r\nException_��ʼTCP/UDP�Ự\r\n");
+					errorStatus = 0x10;			//ת���ر��ƶ�����					
+					break;
+					
+				case GPRS_STATUS_IP_CONFIG:
+					printf("\r\nException_����PDP������\r\n");
+					errorStatus = 0x20;			//ת����������жϺ��ٴβ�ѯGPRS״̬				
+					break;
+					
+				case GPRS_STATUS_IP_GPRSACT:
+					printf("\r\nException_�������Ѿ�����\r\n");
+					errorStatus = 0x10;							
+					break;
+					
+				case GPRS_STATUS_IP_STATUS:
+					printf("\r\nException_�õ�����IP��ַ\r\n");
+					errorStatus = 0x12;							
+					break;
+					
+				case GPRS_STATUS_TCP_CONNECTING:		//��������
+					printf("\r\nException_�������ӷ�����\r\n");
+					errorStatus = 0x20;							
+					break;
+					
+				case GPRS_STATUS_CONNECT_OK:		//��������
+					printf("\r\nException_��������\r\n");
+					
+					//����⵽���ӻ������������������ж�GPRS���̨�����Ƿ���������
+					GPRS_OnlineCheck();
+					
+					//����һ����Ȼ��ѯ������״̬Ϊ���ӻ������������п����Ѿ������쳣��
+					//���Դ����������ͷ���ʧ�ܼ����ı������������
+					errorStatus = 0x00;								//���ӳɹ�
+					GSM_GPRS_Status = 0x02;						//ת��TCP�ͻ��������շ���������
+					break;
+					
+				case GPRS_STATUS_TCP_CLOSING:
+					printf("\r\nException_���ڹر�����\r\n");
+					errorStatus = 0x20;							
+					break;
+					
+				case GPRS_STATUS_TCP_CLOSED:
+					printf("\r\nException_�����Ѿ��ر���\r\n");
+					errorStatus = 0x10;							
+					break;
+					
+				case GPRS_STATUS_PDP_DEACT:		//�������Ѿ��ر�
+					printf("\r\nException_PDP������ȥ����\r\n");
+					errorStatus = 0x20;								
+					break;
+						
+				default:
+					break;
+			}
+			
+			if(timer_expired(&responseTimeout))			//��ʱ��δ���յ�Ӧ��
+			{
+				printf("\r\nException_״̬��ѯ��ʱ\r\n");
+				errorStatus = 0x20;
+				break;
+			}
+			break;
+			
+		case 0x10: 				//�ر��ƶ�������AT+CIPSHUT��
+			GSM_SendAtCmd("AT+CIPSHUT", AT_CMD_CIPSHUT_NO);				//�ر��ƶ����� 
+			errorStatus = 0x11;
+			timer_restart(&responseTimeout);					//�ӵ�ǰʱ�����¿�����ʱ��
+			printf("\r\nException_���ڹرճ���\r\n");	
+			break;
+			
+		case 0x11:			
+			if(at_cmd_table[AT_CMD_CIPSHUT_NO-1].result == AT_CMD_SUCCESS)
+			{
+				printf("\r\nException_�����Ѿ��ر�\r\n");
+				errorStatus = 0x12;								
+			}
+			if(at_cmd_table[AT_CMD_CIPSHUT_NO-1].result == AT_CMD_FAILED)
+			{
+				printf("\r\nException_�����رմ���\r\n");
+				errorStatus = 0x20;									
+				break;
+			}
+			
+			if(timer_expired(&responseTimeout))				//��ʱ��δ���յ�Ӧ��
+			{
+				printf("\r\nException_�����رճ�ʱδӦ��\r\n");	
+				errorStatus = 0x20;			
+				break;
+			}
+			break;
+			
+		case 0x12:					//������������TCP���AT+CIPSTART='IP��ַ'��
+			printf("\r\nException_��������\r\n");
+			GSM_SendAtCmd(TCP_IP_COM, AT_CMD_CIPSTART_NO);		//��ʼ����Զ�˷�����
+			errorStatus = 0x13;
+			timer_restart(&waitTCPConnectTime);								//�ӵ�ǰʱ�����¿�����ʱ��
+			printf("\r\nException_�ȴ�Ӧ��CONNECT OK��\r\n");
+			break;	
+			
+		case 0x13:					//�ȴ�Ӧ��CONNECT OK��		
+			if(at_cmd_table[AT_CMD_CIPSTART_NO-1].result == AT_CMD_SUCCESS)
+			{
+				printf("\r\nException_�������ӳɹ�\r\n");
+				
+				GPRS_OnlineCheck();
+				
+				errorProcessCount = 0;
+// 				sendFailureCount = 0;											//�����ͳɹ�������ʧ�ܼ�������
+
+				errorStatus = 0x00;									//���յ�Ӧ����ת��0x10
+				GSM_GPRS_Status = 0x02;							//ת��TCP�ͻ��˴���״̬
+				break;
+			}
+			
+			if(at_cmd_table[AT_CMD_CIPSTART_NO-1].result == AT_CMD_FAILED)
+			{
+				printf("\r\nException_������ʧ��\r\n");
+				errorStatus = 0x20;									
+				break;
+			}
+			
+			if(timer_expired(&waitTCPConnectTime))				//��ʱ��δ���յ�Ӧ��
+			{
+				printf("\r\nException_�ȴ�Ӧ��CONNECT OK����ʱ\r\n");		
+				errorStatus = 0x20;										
+				break;
+			}
+			break;
+			
+		case 0x20:		//����2S��ʱ����2S�������²�ѯGPRS����״̬
+			errorStatus = 0x21;
+			timer_restart(&waitingTime2s);
+			break;
+			
+		case 0x21:		//2S�����²�ѯGPRS����״̬ 
+			if(timer_expired(&waitingTime2s))
+			{
+				errorStatus = 0x00;
+			}
+			break;
+			
+		default:		//δ֪״̬
+			GSM_GPRS_Reset();							//GSMģ�鸴λ������
+			
+			printf("\r\nException_δ֪״̬������ģ�飡����\r\n");
+			break;
+	}
+}
+
+/*
+***********************************************************************
+*	�� �� ��: GSM_GPRS_Task
+*	����˵��: GSM_GPRSͨѶ����
+*	��    �Σ���
+*	�� �� ֵ: ��
+***********************************************************************
+*/
+void GSM_GPRS_Task(void)
+{
+	switch(GSM_GPRS_Status)
+	{
+		case 0x00:		//��ʼ״̬����ģ����п������������״̬�Ĳ�ѯ
+			GSM_GPRS_Loading();
+			break;
+			
+		case 0x01:		//����TCP�ͻ���
+			TCP_ClientCreate();
+			break;
+			
+		case 0x02:		//TCP�ͻ��˴��������ݵ��շ���
+			TCP_ClientHandler();
+			break;
+			
+		case 0x03:		//TCP�����ڼ���ֵĴ�����
+			TCP_ErrorHandler();
+			break;
+			
+		default: 			//δ֪״̬
+			GSM_GPRS_Reset();							//GSMģ�鸴λ������
+			
+			printf("\r\nException_δ֪״̬������ģ�飡����\r\n");
+		break;
+	}
+}
+
+/******************** (C) COPYRIGHT 2017 CXHY *****END OF FILE*******************/
diff --git a/STM32_4路称重_Git提交精简工程/src/HARDWARE/GSM/gsm_gprs.h b/STM32_4路称重_Git提交精简工程/src/HARDWARE/GSM/gsm_gprs.h
new file mode 100755
index 0000000..e88410e
--- /dev/null
+++ b/STM32_4路称重_Git提交精简工程/src/HARDWARE/GSM/gsm_gprs.h
@@ -0,0 +1,33 @@
+/*************************** (C) COPYRIGHT 2017 CXHY ****************************
+ * �ļ���  ��gsm_gprs.h
+ * ��  ��  ��SIM900A����ͷ�ļ�     
+ * ��  ��  ��V1.0
+ * ��  ��  ��XuZhongPing
+ * ��  ��  ��2013/11/21 
+*********************************************************************************/
+#ifndef __GSM_GPRS_H__
+#define __GSM_GPRS_H__	 
+
+// #include "gsm_uart_conf.h"
+// 	
+// #define GSM_PW_KEY PBout(12)
+
+// //�豸����״̬
+// typedef enum
+// {    
+//   OFFLINE = 0, 							//���� 
+// 	ONLINE = 1								//����	
+
+// }_ConnectionStatus;
+
+// extern uint8_t GSM_isPowerON;												//GSMģ���Ƿ��ڿ���
+// extern uint8_t ConnectionStatus;										//����״̬���������ݰ����ͳɹ�����λΪ����״̬��
+
+// void GSM_GPRS_Init(void);
+// uint8_t GSM_PowerON(void);
+// uint8_t GSM_PowerOFF(void);
+
+// void GSM_GPRS_Task(void);
+#endif
+
+/******************** (C) COPYRIGHT 2017 CXHY *****END OF FILE*******************/ 
diff --git a/STM32_4路称重_Git提交精简工程/src/HARDWARE/GSM/gsm_uart.c b/STM32_4路称重_Git提交精简工程/src/HARDWARE/GSM/gsm_uart.c
new file mode 100755
index 0000000..28376d6
--- /dev/null
+++ b/STM32_4路称重_Git提交精简工程/src/HARDWARE/GSM/gsm_uart.c
@@ -0,0 +1,170 @@
+/*************************** (C) COPYRIGHT 2017 CXHY ****************************
+ * �ļ���  ��gsm_uart.c
+ * ��  ��  ��GSM���ƴ��ڣ�����3��
+ * ��  ��  ��V1.0
+ * ��  ��  ��XuZhongPing
+ * ��  ��  ��2017/04/26 
+*********************************************************************************/
+#include "delay.h"
+#include "usart1.h"
+#include "stdarg.h"	 	 
+#include "stdio.h"	
+#include "stdlib.h"  	 
+#include "string.h"		
+#include "gsm_uart.h"
+#include "gsm_uart_conf.h"
+#include "usart3.h"
+#include "at_proc.h"
+#include "tcp_protocol.h"
+
+//���ڷ��ͻ����� 	
+__align(8) uint8_t  GPRS_TX_BUF[GPRS_MAX_SEND_LEN]; 		//���ͻ���,���GPRS_MAX_SEND_LEN�ֽ�
+uint8_t  GPRS_RX_BUF[GPRS_MAX_RECV_LEN]; 								//���ջ���,���GPRS_MAX_RECV_LEN�ֽ�
+
+uint8_t GPRS_DATA_BUF[GPRS_MAX_SEND_LEN];								//GPRS���ݴ�������,���GPRS_MAX_SEND_LEN�ֽ�
+uint8_t GPRS_RECV_DATA_BUF[GPRS_MAX_RECV_LEN];
+
+_gsm_msg gsm_msg;
+uint8_t signal;
+
+uint16_t total_send_length = 0;													//���������ܳ���
+uint16_t ackedBytes = 0;																//�յ������ܳ���
+uint16_t unackedbytes = 0;															//δ�յ������ܳ���
+
+uint8_t receiveDataMark = 0;
+
+uint8_t GSM_ReceiveType = 0;														// GSMģ����յ����������ͣ�0ΪAT����Ӧ��1ΪTCP���ݣ�
+
+uint16_t GPRS_RX_STA;   																//��������״̬
+uint16_t GPRS_RX_Cnt = 0;
+uint16_t recDataLen = 0;
+
+/*
+***********************************************************************
+*	�� �� ��: GSM_Uart_Init
+*	����˵��: GSM���ƴ��ڳ�ʼ��
+*	��    ��: ��
+*	�� �� ֵ: ��
+***********************************************************************
+*/
+void GSM_GPRS_Uart_Init(void)
+{
+	USART3_Init(115200);							//�ⲿ��ʵ��Щ����
+}
+
+/*
+***********************************************************************
+*	�� �� ��: GSM_GPRS_SendOne
+*	����˵��: ��GSM���ڷ���һ������
+*	��    ��: ��
+*	�� �� ֵ: ��
+***********************************************************************
+*/
+void GSM_GPRS_SendOne(uint8_t pDataBuf[], uint16_t len)
+{
+	UART3_Send_One(len);						//�ⲿ��ʵ��Щ����
+}
+
+/*
+***********************************************************************
+*	�� �� ��: GSM_GPRS_SendByteData
+*	����˵��: ��GSM�������һ�ֽ�����
+*	��    ��: ��
+*	�� �� ֵ: ��
+***********************************************************************
+*/
+void GSM_GPRS_SendByteData(uint8_t cmd)
+{
+	while(DMA1_Channel2->CNDTR != 0);			//�ȴ�ͨ��7�������   
+	USART3->DR = (uint32_t)cmd;
+}
+
+/*
+***********************************************************************
+*	�� �� ��: GSM_GPRS_printf
+*	����˵��: GSM�����������
+*	��    ��: ��
+*	�� �� ֵ: ��
+***********************************************************************
+*/
+void GSM_GPRS_printf(char* fmt, ...)  
+{  
+	va_list ap;
+	va_start(ap, fmt);
+	vsprintf((char*)GPRS_TX_BUF, fmt, ap);
+	va_end(ap);
+//	while(DMA1_Channel2->CNDTR!=0);	//�ȴ�ͨ��7�������   
+	GSM_GPRS_SendOne(GPRS_TX_BUF, strlen((const char*)GPRS_TX_BUF)); 	//ͨ��dma���ͳ�ȥ
+}  
+
+
+void show_buf1(uint8_t num[], uint8_t n)
+{
+    uint8_t i;
+		printf("\r\n");
+    for(i=0; i<n; i++)
+		{
+      printf("%x ",num[i]);
+		}
+		printf("\r\n");
+}
+/*
+***********************************************************************
+*	�� �� ��: GSM_GPRS_ReceiveData
+*	����˵��: GSM���ڽ�������
+*	��    ��: ��
+*	�� �� ֵ: ��
+***********************************************************************
+*/
+void GSM_GPRS_ReceiveData(uint8_t rxData)
+{
+	static uint8_t i = 0;
+	static uint8_t len = 0;
+	static uint8_t receiveStatus = 0;
+
+	if(GPRS_RX_Cnt < GPRS_MAX_RECV_LEN)										//�����Խ�������
+	{
+		GPRS_RX_BUF[GPRS_RX_Cnt++] = rxData;								//��¼���յ���ֵ	
+		
+		if(GSM_ReceiveType == 0)		//���յ�GSMģ�������ΪAT����Ӧ������
+		{
+			if(GPRS_RX_BUF[GPRS_RX_Cnt - 1] == '\n')
+			{
+				i++;
+				if(GPRS_RX_Cnt >= 4)
+				{
+					GPRS_RX_BUF[GPRS_RX_Cnt] = 0;					//�ڽ��յ������ݺ��������ַ���������'\0'
+					
+					AT_Protocol(GPRS_RX_BUF, GPRS_RX_Cnt);		//����ATָ��Ӧ�����
+				}
+				GPRS_RX_Cnt = 0;
+			}
+			
+			if((sendAtCmdNo == AT_CMD_QISEND) && (GPRS_RX_BUF[GPRS_RX_Cnt - 1] == '>'))
+			{
+				GPRS_RX_BUF[GPRS_RX_Cnt] = 0;							//�ڽ��յ������ݺ��������ַ���������'\0'	
+				AT_Protocol(GPRS_RX_BUF, GPRS_RX_Cnt);		//����ATָ��Ӧ�����
+				GPRS_RX_Cnt = 0;
+			}
+		}else{											//���յ�ģ���URC�ϱ�����
+			if(GPRS_RX_Cnt >= recDataLen)
+			{
+// 				show_buf1(GPRS_RX_BUF, GPRS_RX_Cnt);
+				GPRS_RX_BUF[GPRS_RX_Cnt] = 0;							//�ڽ��յ������ݺ��������ַ���������'\0'	
+				
+				TCP_Protocol(GPRS_RX_BUF, GPRS_RX_Cnt);
+				GPRS_RX_Cnt = 0;
+				GSM_ReceiveType = 0;
+			}
+		}
+	}else{
+		GPRS_RX_Cnt = 0;
+		GSM_ReceiveType = 0;
+		receiveStatus = 0x00;
+		printf("\r\nData out\r\n");
+	}
+}
+
+
+/******************** (C) COPYRIGHT 2017 CXHY *****END OF FILE*******************/ 
+
diff --git a/STM32_4路称重_Git提交精简工程/src/HARDWARE/GSM/gsm_uart.h b/STM32_4路称重_Git提交精简工程/src/HARDWARE/GSM/gsm_uart.h
new file mode 100755
index 0000000..f5cf86c
--- /dev/null
+++ b/STM32_4路称重_Git提交精简工程/src/HARDWARE/GSM/gsm_uart.h
@@ -0,0 +1,20 @@
+/*************************** (C) COPYRIGHT 2017 CXHY ****************************
+ * �ļ���  ��gsm_uart.h
+ * ��  ��  ��GSM���ƶ˿ڣ�����3��  
+ * ��  ��  ��V1.0
+ * ��  ��  ��XuZhongPing
+ * ��  ��  ��2017/04/26 
+*********************************************************************************/
+#ifndef __GSM_UART_H
+#define __GSM_UART_H	 
+#include "stm32f10x.h"
+
+void GSM_GPRS_Uart_Init(void);											//GSM_GPRS��ʹ�õĴ��ڳ�ʼ��
+void GSM_GPRS_SendOne(uint8_t pDataBuf[], uint16_t len);								//��GSM��ʹ�õĴ��ڷ���һlen���ȵ�����
+void GSM_GPRS_SendByteData(uint8_t cmd);						//��GSM��ʹ�õĴ��ڷ���һ�ֽ�����
+void GSM_GPRS_printf(char* fmt, ...);								//��GSM��ʹ�õĴ��ڷ�������
+void GSM_GPRS_ReceiveData(uint8_t rxData);
+
+#endif
+
+/******************** (C) COPYRIGHT 2014 GLHF *****END OF FILE*******************/
diff --git a/STM32_4路称重_Git提交精简工程/src/HARDWARE/GSM/gsm_uart_conf.c b/STM32_4路称重_Git提交精简工程/src/HARDWARE/GSM/gsm_uart_conf.c
new file mode 100755
index 0000000..2038180
--- /dev/null
+++ b/STM32_4路称重_Git提交精简工程/src/HARDWARE/GSM/gsm_uart_conf.c
@@ -0,0 +1,23 @@
+/*************************** (C) COPYRIGHT 2017 CXHY ****************************
+ * �ļ���  ��gsm_uart.c
+ * ��  ��  ��GSM���ƴ��ڣ�����3��
+ * ��  ��  ��V1.0
+ * ��  ��  ��XuZhongPing
+ * ��  ��  ��2017/04/26 
+*********************************************************************************/
+#include "delay.h"
+#include "sys.h"
+#include "usart.h"
+#include "stdarg.h"	 	 
+#include "stdio.h"	 	 
+#include "string.h"
+#include "gsm_uart_conf.h"
+
+//���ڷ��ͻ����� 	
+// __align(8) uint8_t  GPRS_TX_BUF[GPRS_MAX_SEND_LEN]; 		//���ͻ���,���GPRS_MAX_SEND_LEN�ֽ�
+// uint8_t  GPRS_RX_BUF[GPRS_MAX_RECV_LEN]; 								//���ջ���,���GPRS_MAX_RECV_LEN�ֽ�
+
+// uint16_t GPRS_RX_STA;   																//��������״̬
+
+
+/******************** (C) COPYRIGHT 2017 CXHY *****END OF FILE*******************/ 
diff --git a/STM32_4路称重_Git提交精简工程/src/HARDWARE/GSM/gsm_uart_conf.h b/STM32_4路称重_Git提交精简工程/src/HARDWARE/GSM/gsm_uart_conf.h
new file mode 100755
index 0000000..4597a16
--- /dev/null
+++ b/STM32_4路称重_Git提交精简工程/src/HARDWARE/GSM/gsm_uart_conf.h
@@ -0,0 +1,58 @@
+/*************************** (C) COPYRIGHT 2017 CXHY ****************************
+ * �ļ���  ��gsm_uart.h
+ * ��  ��  ��GSM���ƶ˿�
+ * ��  ��  ��V1.0
+ * ��  ��  ��XuZhongPing
+ * ��  ��  ��2017/04/26 
+*********************************************************************************/
+#ifndef __GSM_UART_CONF_H
+#define __GSM_UART_CONF_H	 
+#include "stdint.h"  
+
+#define TCP_IP_COM "AT+QIOPEN=1,0,\"TCP\",\"112.74.41.228\",9956,0,1"
+// #define TCP_IP_COM "AT+QIOPEN=1,0,\"TCP\",\"xzp71.xicp.net\",41149,0,1"			//������ת������������
+// #define TCP_IP_COM "AT+QIOPEN=1,0,\"TCP\",\"218.59.175.31\",9956,0,1"			//�ൺ������
+
+// #define TCP_IP_COM "AT+CIPSTART=\"TCP\",\"112.74.41.228\",\"9956\""
+// #define TCP_IP_COM "AT+CIPSTART=\"TCP\",\"112.74.41.228\",\"1111\""
+// #define TCP_IP_COM "AT+CIPSTART=\"TCP\",\"115.28.185.180\",\"8956\""
+// #define TCP_IP_COM "AT+CIPSTART=\"TCP\",\"xzp71.xicp.net\",\"50062\""
+
+typedef struct
+{
+	uint8_t Running;								//GSMģ������״̬
+	char IMEI [16];									//�豸��
+	char IMEI_HEX[8];								//IMEI�豸��ʮ�����Ʊ��棬�����ϴ�����̨
+	uint8_t Operator[16];						//ͨ����Ӫ��
+	uint8_t OperatorType;						//0:δ֪��1���й��ƶ���2���й���ͨ
+	char ICCID[24];									//SIM��ICCID��
+	uint8_t simCardStatus;					//sim��״̬��0��δ֪״̬��1��������2���޷�ע�����磬3��û��GPRSҵ��4��û�м�⵽����
+}_gsm_msg;
+
+extern _gsm_msg gsm_msg;
+extern uint8_t signal;  	
+
+extern uint16_t total_send_length;									//���������ܳ���
+extern uint16_t ackedBytes;													//�յ������ܳ���
+extern uint16_t unackedbytes;												//δ�յ������ܳ���
+
+extern uint8_t receiveDataMark;
+
+extern char command_CIPSEND[16];   
+ 
+#define GPRS_MAX_SEND_LEN		1024										//����ͻ����ֽ���
+#define GPRS_MAX_RECV_LEN		1024										//�����ջ����ֽ���
+
+extern uint8_t GPRS_TX_BUF[GPRS_MAX_SEND_LEN]; 			//���ͻ���,���GPRS_MAX_SEND_LEN�ֽ�
+extern uint8_t GPRS_RX_BUF[GPRS_MAX_RECV_LEN]; 			//���ջ���,���GPRS_MAX_RECV_LEN�ֽ�
+
+extern uint8_t GPRS_DATA_BUF[GPRS_MAX_SEND_LEN];		//GPRS���ݴ�������,���GPRS_MAX_SEND_LEN�ֽ�
+extern uint8_t GPRS_RECV_DATA_BUF[GPRS_MAX_RECV_LEN];
+
+extern uint16_t GPRS_RX_STA;   											//��������״̬
+extern uint8_t GSM_ReceiveType;											// GSMģ����յ����������ͣ���AT����Ӧ����TCP���ݣ�
+extern uint16_t recDataLen;
+
+#endif
+
+/******************** (C) COPYRIGHT 2014 GLHF *****END OF FILE*******************/
diff --git a/STM32_4路称重_Git提交精简工程/src/HARDWARE/GSM/netwer_appcall.c b/STM32_4路称重_Git提交精简工程/src/HARDWARE/GSM/netwer_appcall.c
new file mode 100755
index 0000000..f6603ce
--- /dev/null
+++ b/STM32_4路称重_Git提交精简工程/src/HARDWARE/GSM/netwer_appcall.c
@@ -0,0 +1,341 @@
+/*************************** (C) COPYRIGHT 2017 CXHY ****************************
+ * �ļ���  ��gsm_uart.c
+ * ��  ��  ��GSM���ƴ��ڣ�����2��
+ * ��  ��  ��V1.0
+ * ��  ��  ��XuZhongPing
+ * ��  ��  ��2017/04/26 
+*********************************************************************************/
+#include "netwer_appcall.h"
+#include "timer.h"
+#include "data_typedef.h"
+#include "tcp_protocol.h"
+#include "message.h"
+#include "gsm_uart_conf.h"
+#include "ec200x.h"
+#include "at_proc.h"
+
+uint8_t isSendDataMark = 0;								//�Ƿ�������Ҫ���ͱ�־
+uint8_t isReceiveDataMark = 0;						//�Ƿ��н��յ����ݱ�־
+uint8_t dataSendSuccessMark = 0;					//���ݷ��ͳɹ���־
+uint8_t dataSendFailureMark = 0;					//���ݷ���ʧ�ܱ�־
+uint8_t dataSendOkButNoAckMark = 0;				//���ݷ��ͳɹ���û������Ӧ��
+
+uint16_t sendDataLen = 0;									//���͵����ݳ���
+
+
+void show_hex(uint8_t num[], uint8_t n)
+{
+    uint8_t i;
+		printf("\r\n");
+    for(i=0; i<n; i++)
+		{
+      printf("%02X ",num[i]);
+		}
+		printf("\r\n");
+}
+
+/*
+***********************************************************************
+*	�� �� ��: ChackIccidNumber
+*	����˵��: �жϵ�ǰ��ICCID�ź�֮ǰ���Ƿ����
+*	��    �Σ�
+*	�� �� ֵ: ����ȷ���1����ȷ���0
+***********************************************************************
+*/
+uint8_t ChackIccidNumber(char* preId, char* curId)
+{
+	uint8_t i;
+	
+	for(i = 0; i < 20; i++)
+	{
+		if(preId[i] != curId[i]) return 1;
+	}
+	return 0;
+}
+
+
+static uint8_t delaySendMark = 0;								//��ʱ���ͱ�־
+/*
+***********************************************************************
+*	�� �� ��: NetReconnectDelaySendHandler
+*	����˵��: ����������������ʱ���ʹ���
+*	��    �Σ���
+*	�� �� ֵ: ��
+***********************************************************************
+*/
+void NetReconnectDelaySendHandler(void)
+{
+	uint8_t i;
+	static uint8_t currentStatus = 0x00;
+	static uint8_t nextStatus = 0x00;
+	
+	static uint8_t initRandomSendTimerFalg = 0;						//��ʼ������ӳٷ���ʱ���־
+	static uint32_t timeSeed = 0;													//���������ʱʱ�������
+	static char preICCID[24] = {0};												//֮ǰ��ICCID��
+	static uint8_t preNetworkConnectionCount = 0;					//��һ�εĽ����������Ӵ���
+	static uint8_t reuploadICCID = 0;											//�����ϴ�ICCID��
+	uint8_t msgBufSurplus = 0;														//��Ϣ���л�ʣ��ռ�
+	
+	static timer waitingTimer;														//�ȴ�ʱ��
+	static timer delayRandomSendTimer;										//�ӳ��������ʱ��
+	
+	static uint8_t timer_ok = 0;
+	if(timer_ok == 0)
+	{
+		timer_ok = 1;
+		
+		timer_set(&waitingTimer, CLOCK_SECOND*60*2);
+		timer_set(&delayRandomSendTimer, CLOCK_SECOND*1);
+	}
+	
+	if(gsm_msg.Running == 1)										//�����Ѿ�����
+	{
+		if(initRandomSendTimerFalg == 0)					//��ʼ������ӳٷ���ʱ��
+		{
+			initRandomSendTimerFalg = 1;
+			
+			timeSeed = (uint32_t)(gsm_msg.IMEI_HEX[4] << 24) | (gsm_msg.IMEI_HEX[5] << 16) | (gsm_msg.IMEI_HEX[6] << 8) | gsm_msg.IMEI_HEX[7];
+			printf("\r\ntimeSeed = %llu\r\n", (uint64_t)timeSeed);
+			srand(timeSeed);
+			delayRandomTime = rand()%60;																							//�õ�����ӳٷ���ʱ��
+			printf("\r\ndelayRandomTime = %d\r\n", delayRandomTime);
+
+			timer_set(&delayRandomSendTimer, CLOCK_SECOND*delayRandomTime);
+			
+			memset(preICCID, 0, 24);
+			memcpy(preICCID, gsm_msg.ICCID, 20);																			//ȡ����ǰ��ICCID��
+			printf("\r\n��ʱ����ʱ���ʼ���ɹ���\r\n");
+		}
+	}
+	
+	//������������ICCID���з����仯���������ϴ�
+	if(reuploadICCID == 1)					
+	{
+		msgBufSurplus = GetMessageRemainingSpace(MSG_FIFO_PROTOCOL);
+		if(msgBufSurplus >= 5)				//������Ϣ�����пռ�ʱ�ŷ��ͣ���Ȼ�ᷢ�Ͳ��ɹ�
+		{
+			printf("\r\n��ǰ����״̬��%d\r\n", msgBufSurplus);
+			reuploadICCID = 0;
+			
+			sendMsg.msgType = 1003;
+			MessageSend(MSG_FIFO_PROTOCOL, sendMsg);
+		}
+	}
+	
+	currentStatus = nextStatus;
+	switch(currentStatus)
+	{
+		case 0x00:		//��ʼ״̬
+			//�жϵ�ǰ��û�г�����������
+			if(preNetworkConnectionCount != networkConnectionCount)
+			{
+				preNetworkConnectionCount = networkConnectionCount;
+				
+				if(networkConnectionCount != 1)			//�����״ν������磬��־��ǰ����������
+				{
+					printf("\r\n����������������\r\n");
+					delaySendMark = 1;								//��־��ǰ�����������������
+					
+					if(ChackIccidNumber(preICCID, gsm_msg.ICCID))
+					{
+						printf("\r\nICCID�ŷ����ı䣡\r\n");
+						reuploadICCID = 1;
+
+						printf("\r\n��ǰ����״̬��%d\r\n", GetMessageRemainingSpace(MSG_FIFO_PROTOCOL));
+						
+						memcpy(preICCID, gsm_msg.ICCID, 20);
+					}
+					
+					timer_restart(&delayRandomSendTimer);
+					timer_restart(&waitingTimer);
+					nextStatus = 0x01;
+				}
+			}
+			break;
+			
+		case 0x01:		//�ж��������������磬���ӳ��������ʱ���ٷ�������
+			if(timer_expired(&delayRandomSendTimer))
+			{
+				printf("\r\n�ȴ���ʱ����ʱ�䵽��\r\n");
+				delaySendMark = 0;
+				nextStatus = 0x00;
+				break;
+			}
+			
+			if(timer_expired(&waitingTimer))
+			{
+				printf("\r\n��ʱ���͵ȴ���ʱ��\r\n");
+				delaySendMark = 0;
+				nextStatus = 0x00;
+				break;
+			}
+			break;
+			
+		default:
+			break;
+	}
+}
+
+/*
+***********************************************************************
+*	�� �� ��: SendNetworkData
+*	����˵��: ������������
+*	��    �Σ���
+*	�� �� ֵ: ��
+***********************************************************************
+*/
+void SendNetworkData(uint8_t *sendBuf, uint16_t dataLength)
+{
+	sendDataLen = dataLength;
+// 	memcpy(GPRS_TX_BUF, sendBuf, GPRS_sendDataLength);
+	isSendDataMark = 1;
+}
+
+/*
+***********************************************************************
+*	�� �� ��: DataUploadPollingTask
+*	����˵��: �����ϴ���ѯ����
+*	��    �Σ���
+*	�� �� ֵ: ��
+***********************************************************************
+*/
+void DataUploadPollingTask(void)
+{
+	static uint8_t currentStatus = 0x00;
+	static uint8_t nextStatus = 0x00;
+	
+	uint8_t sendFailureFlag = 0;
+	
+	static MESSAGE *pMsg;
+	static uint16_t dataBufLength = 0;
+	
+	static uint32_t nowTime = 0;													//��ǰ����ָ���ʱ��
+	static uint32_t preSendTime_1001 = 0;									//ǰһ�η���ָ���ʱ��
+	static uint32_t preSendTime_6004 = 0;
+	uint16_t repeatCmdIntervalTime = 600;									//�ظ�ָ����ʱ�䣨��λΪ0.1�룩
+	
+	static timer uploadIntervalTime;											//�����ϴ�ʱ�������ƣ�����ͬһʱ�����ظ��ϴ���������
+	static timer responseTimeout;													//Ӧ��ʱʱ����
+	static timer sendTimeout;															//���ͳ�ʱʱ����
+	
+	static uint8_t timer_ok = 0;
+	if(timer_ok == 0)
+	{
+		timer_ok = 1;
+		
+		timer_set(&uploadIntervalTime, CLOCK_SECOND*3);  			
+		timer_set(&responseTimeout, CLOCK_SECOND*3);
+		timer_set(&sendTimeout, CLOCK_SECOND*120);
+	}
+	
+	NetReconnectDelaySendHandler();
+	
+	currentStatus = nextStatus;
+	switch(currentStatus)
+	{
+		case 0x00:
+			if(ConnectionStatus == ONLINE)
+			{
+				if(delaySendMark == 0)		//�Ƿ�Ҫ�ӳٷ���
+				{
+					pMsg = MessageGet(MSG_FIFO_PROTOCOL);					//��ȡ��Ϣ����
+					if(pMsg)		//�����Ϣ����������Ϣ��������ݷ���
+					{
+						sendOrderCode = pMsg->msgType;										//ȡ�÷��͵�Э����
+						
+						nowTime = time_value;															//ȡ����ǰ����ָ���ʱ��
+						if(sendOrderCode == 1001)													//��ǰ���͵���1001ָ��
+						{
+							if((preSendTime_1001 != 0) && ((nowTime - preSendTime_1001) < repeatCmdIntervalTime))
+							{
+								printf("\r\n�ظ�1001ָ��ȡ�����ͣ�\r\n");
+								nextStatus = 0x00;
+								break;
+							}
+							preSendTime_1001 = nowTime;
+						}
+						
+						if(sendOrderCode == 6004)													//��ǰ���͵���6004ָ��
+						{
+							if((preSendTime_6004 != 0) && ((nowTime - preSendTime_6004) < repeatCmdIntervalTime))
+							{
+								printf("\r\n�ظ�6004ָ��ȡ�����ͣ�\r\n");
+								nextStatus = 0x00;
+								break;
+							}
+							preSendTime_6004 = nowTime;
+						}
+						
+						printf("\r\nTCP Sending data......\r\n");
+						nextStatus = 0x01;								//��ת����������
+						break;
+					}
+				}
+			}
+			break;
+			
+		case 0x01:		
+			dataBufLength = SendProtocolPackaging(sendOrderCode);	//ͨ����Ϣ�����ͽ�����ӦЭ����
+			SendNetworkData(GPRS_DATA_BUF, dataBufLength);
+			
+			isReceiveDataMark = 0;
+			dataSendSuccessMark = 0;
+			dataSendFailureMark = 0;
+			timer_restart(&sendTimeout);
+			nextStatus = 0x02;
+			break;
+			
+		case 0x02:		//�ȴ��������
+			if(isReceiveDataMark == 1)
+			{
+				isReceiveDataMark = 0;
+				printf("\r\n���ݷ��ͳɹ���\r\n");
+// 				show_hex(GPRS_RECV_DATA_BUF, receiveDataLen);
+// 				printf("\r\ndata=%s\r\n", GPRS_DATA_BUF);
+// 				TCP_Protocol(GPRS_RECV_DATA_BUF, receiveDataLen);				
+// 				memset(GPRS_RECV_DATA_BUF, 0x00, 1024);
+				nextStatus = 0x00;
+				break;
+			}
+			
+			//�����ѷ��͵�����������û���յ�Ӧ��
+			if(dataSendOkButNoAckMark == 1)
+			{
+				printf("\r\n�����ѷ��ͣ���û��Ӧ��\r\n");
+				dataSendOkButNoAckMark = 0;
+				
+				nextStatus = 0x00;
+				break;
+			}
+			
+			//����ʧ��
+			if(dataSendFailureMark == 1)
+			{
+				dataSendFailureMark = 0;
+				printf("\r\n���ݷ���ʧ�ܣ�\r\n");
+				sendFailureFlag = 1;
+			}
+			
+			//���ͳ�ʱ
+			if(timer_expired(&sendTimeout))						//��ʱ��δ���յ�Ӧ��
+			{
+				printf("\r\n���ͳ�ʱ��\r\n");
+				sendFailureFlag = 1;
+			}
+			
+			if(sendFailureFlag == 1)
+			{
+				printf("\r\nTCP send data failure!\r\n");
+				nextStatus = 0x00;		
+				break;
+			}
+			
+			break;
+			
+		default:
+			break;
+	}
+}
+
+/******************** (C) COPYRIGHT 2017 CXHY *****END OF FILE*******************/ 
+
diff --git a/STM32_4路称重_Git提交精简工程/src/HARDWARE/GSM/netwer_appcall.h b/STM32_4路称重_Git提交精简工程/src/HARDWARE/GSM/netwer_appcall.h
new file mode 100755
index 0000000..fc629bf
--- /dev/null
+++ b/STM32_4路称重_Git提交精简工程/src/HARDWARE/GSM/netwer_appcall.h
@@ -0,0 +1,26 @@
+/*************************** (C) COPYRIGHT 2017 YNHB ****************************
+ * �ļ���  ��netwer_appcall.h
+ * ��  ��  ��GSM���ƶ˿ڣ�����3��  
+ * ��  ��  ��V1.0
+ * ��  ��  ��XuZhongPing
+ * ��  ��  ��2017/04/26 
+*********************************************************************************/
+#ifndef __NETWER_APPCALL_H
+#define __NETWER_APPCALL_H	 
+#include "stdio.h" 
+#include "stdint.h"
+#include "stdlib.h"
+
+extern uint8_t isSendDataMark;									//�Ƿ�������Ҫ���ͱ�־
+extern uint8_t isReceiveDataMark;								//�Ƿ��н��յ����ݱ�־
+extern uint8_t dataSendSuccessMark;							//���ݷ��ͳɹ���־
+extern uint8_t dataSendFailureMark;							//���ݷ���ʧ�ܱ�־
+extern uint8_t dataSendOkButNoAckMark;					//���ݷ��ͳɹ���û������Ӧ��
+
+extern uint16_t sendDataLen;										//���͵����ݳ���
+
+void DataUploadPollingTask(void);
+
+#endif
+
+/******************** (C) COPYRIGHT 2017 YNHB *****END OF FILE*******************/
diff --git a/STM32_4路称重_Git提交精简工程/src/HARDWARE/IR_Distancer/IR_Distancer.c b/STM32_4路称重_Git提交精简工程/src/HARDWARE/IR_Distancer/IR_Distancer.c
new file mode 100755
index 0000000..82b77c7
--- /dev/null
+++ b/STM32_4路称重_Git提交精简工程/src/HARDWARE/IR_Distancer/IR_Distancer.c
@@ -0,0 +1,421 @@
+/*************************** (C) COPYRIGHT 2017 CXHY ****************************
+ * �ļ���  ��UltrasonicWave.c
+ * ��  ��  ��HC-SR04��������������     
+ * ��  ��  ��V1.0
+ * ��  ��  ��XuZhongPing
+ * ��  ��  ��2017/08/04 
+*********************************************************************************/
+#include "IR_Distancer.h"
+#include "timer.h"
+#include "delay.h"
+#include "adc.h"
+#include "my_math.h"
+#include "data_typedef.h"
+
+#define IR_AdcValSize	100
+uint16_t IR_AdcValBuf_1[IR_AdcValSize]; 
+uint16_t IR_AdcVal_1 = 0;
+
+uint16_t IR_AdcValBuf_2[IR_AdcValSize];
+uint16_t IR_AdcVal_2 = 0;
+
+uint8_t IR_GetAdcValMake = 0;
+
+#define IR_GetDataCount		5
+
+uint8_t ir_Distance1 = 0;
+uint8_t ir_dataOutState1 = 0;
+uint8_t ir_Distance2 = 0;
+uint8_t ir_dataOutState2 = 0;
+
+
+
+/*
+***********************************************************************
+*	�� �� ��: show
+*	����˵��: ��ʮ��������ʾ�����������
+*	��    ��:	��
+*	�� �� ֵ: ��
+***********************************************************************
+*/
+void showBuf(uint16_t num[], uint8_t n)
+{
+    uint8_t i;
+		printf("\r\n");
+    for(i=0; i<n; i++)
+		{
+      printf("%04d ",num[i]);
+		}
+		printf("\r\n");
+}
+
+
+
+
+
+/*
+***********************************************************************
+*	�� �� ��: IR_GetAdcVal_1
+*	����˵��: ��ȡ�����ഫ����ADCֵ
+*	��    �Σ���	         
+*	�� �� ֵ: ��
+***********************************************************************
+*/
+void IR_GetAdcVal_1(void)
+{
+	Data_collection(IR_AdcValBuf_1, IR_AdcValSize, ADC_Channel_11);
+	sort_16(IR_AdcValBuf_1, IR_AdcValSize);           											//�Դ��ڻ����еĲɼ����ݽ�������
+	IR_AdcVal_1 = average_16(IR_AdcValBuf_1, IR_AdcValSize, 20);				//ȥ��ͷ��β����ƽ����
+}
+
+/*
+***********************************************************************
+*	�� �� ��: IR_GetAdcVal_2
+*	����˵��: ��ȡ�����ഫ����ADCֵ
+*	��    �Σ���	         
+*	�� �� ֵ: ��
+***********************************************************************
+*/
+void IR_GetAdcVal_2(void)
+{
+	Data_collection(IR_AdcValBuf_2, IR_AdcValSize, ADC_Channel_10);
+	sort_16(IR_AdcValBuf_2, IR_AdcValSize);           									//�Դ��ڻ����еĲɼ����ݽ�������
+	IR_AdcVal_2 = average_16(IR_AdcValBuf_2, IR_AdcValSize, 20);				//ȥ��ͷ��β����ƽ����
+}
+
+uint8_t distanceMap[] = {	 20, 	 30, 	 40, 	 50, 	 60, 	 70, 	 80,   90, 	100,  110,  120,  130,  140,  150};
+float voltageMap[14] = 	{2.49, 1.95, 1.51, 1.21, 1.01, 0.86, 0.76, 0.69, 0.61, 0.53, 0.45, 0.40, 0.34, 0.25};
+// float voltageMap[14] = 	{2.50, 1.95, 1.50, 1.20, 1.00, 0.88, 0.77, 0.69, 0.60, 0.55, 0.49, 0.44, 0.38, 0.30};
+
+// float voltageMap[14] = 	{2.44, 1.94, 1.50, 1.20, 1.00, 0.85, 0.74, 0.67, 0.60, 0.52, 0.48, 0.44, 0.39, 0.33};
+
+/*
+***********************************************************************
+*	�� �� ��: LookupTable
+*	����˵��: ����ó���Ӧ�ľ���ֵ
+*	��    �Σ���	         
+*	�� �� ֵ: ��Ӧ�ľ���
+***********************************************************************
+*/
+float LookupTable(float vIn, float vMap1, float vMap2, uint8_t disMap1, uint8_t disMap2)
+{
+	uint8_t disDifVal;													//����ĵ�ѹ��ֵ
+	float vDifVal;															//����ľ����ֵ
+	float vLtscale;															//��������������
+	float vIntervalVal;													//�����ѹֵ
+	float intervalDistance;											//����ľ���
+	
+	disDifVal = disMap2 - disMap1;
+	vDifVal = vMap1 - vMap2;
+	vLtscale = disDifVal/vDifVal;
+	
+	vIntervalVal = vMap1 - vIn;
+	intervalDistance = vIntervalVal*vLtscale;
+	
+// 	printf("\r\ndisDif = %d\r\n", disDifVal);
+// 	printf("\r\nvDif = %.2f\r\n", vDifVal);
+// 	printf("\r\nvLtscale = %.2f\r\n", vLtscale);
+// 	printf("\r\nvIntervalVal = %.2f\r\n", vIntervalVal);
+// 	printf("\r\nvInvalVal = %.2f\r\n", intervalDistance);
+	
+	return disMap1 + intervalDistance;
+}
+
+/*
+***********************************************************************
+*	�� �� ��: IR_GetDistanceData
+*	����˵��: ȡ��һ�β��ֵ
+*	��    �Σ�num -> ��Ӧ�ĸ�ͨ��
+*	�� �� ֵ: ��ǰͨ���Ĳ��ֵ
+***********************************************************************
+*/
+uint8_t IR_GetDistanceData(uint8_t num)
+{
+	float distanceTemp;
+	float adToVdcVal;
+	int index = 0;
+	
+	switch(num)
+	{
+		case 1:
+			IR_GetAdcVal_1();
+			
+			if(IR_AdcVal_1 < 120)
+			{
+				return 255;
+			}else{
+				adToVdcVal = IR_AdcVal_1/4096.0 * 3.34;
+// 				printf("\r\nV1 = %1.2f, ADC1 = %d  ", adToVdcVal, IR_AdcVal_1);
+			}
+			break;
+			
+		case 2:
+			IR_GetAdcVal_2();
+			
+			if(IR_AdcVal_2 < 120)
+			{
+				return 255;
+			}else{
+				adToVdcVal = IR_AdcVal_2/4096.0 * 3.34;
+// 				printf("\r\nV2 = %1.2f, ADC2 = %d  ", adToVdcVal, IR_AdcVal_2);
+			}
+			break;
+		
+		default:
+			break;
+	}
+	
+// 	printf("ADC = %4d, %4d, V = %1.2f\r\n", IR_AdcVal_1, IR_AdcVal_2, adToVdcVal);
+	
+	for(index = 0; index < 14; index++)
+	{
+		if(adToVdcVal >= voltageMap[index])
+		{
+			break;
+		}
+	}
+		
+// 		printf("\r\nindex = %d\r\n", index);
+	if(index == 0)
+	{
+		distanceTemp = 20;
+	}else if(index == 14){
+		distanceTemp = 150;
+	}else{
+		distanceTemp = LookupTable(adToVdcVal, voltageMap[index-1], voltageMap[index], distanceMap[index-1], distanceMap[index]);
+	}
+	
+// 	printf("D = %d cm\r\n", (uint8_t)distanceTemp);
+	
+	return distanceTemp;
+	
+}
+
+/*
+***********************************************************************
+*	�� �� ��: ULT_DataProcessing
+*	����˵��: �Բɼ�����������ݴ�������������������ƽ������
+*	��    �Σ�
+*       		*p: ��Ҫ����������ָ��
+*						n:  ����ĳ��� 
+*	�� �� ֵ: �������մ�������Ľ��
+***********************************************************************
+*/
+uint8_t IR_DataProcessing(uint8_t *p, uint16_t n, uint8_t discardVal)
+{
+	uint8_t retData = 0;
+	
+	sort_8(p, n);           											//�Դ��ڻ����еĲɼ����ݽ�������
+	retData = average_8(p, n, discardVal);				//ȥ��ͷ��β����ƽ����
+// 	printf("\r\nValue = %d\r\n", retData);
+	return retData;
+}
+
+/*
+***********************************************************************
+*	�� �� ��: IR_GetDistanceTask_01
+*	����˵��: ��ȡ����������
+*	��    �Σ���
+*	�� �� ֵ: ���ݴ���״̬  1���Ѵ�����ɿ��������0����δ�������
+***********************************************************************
+*/
+void IR_GetDistanceTask_01(void)
+{
+	static uint8_t step = 0x00;
+	static uint8_t getDataCnt = 0x00;
+	
+	static uint8_t newValue = 0x00;
+	static uint8_t oleValue = 0x00;
+	static uint8_t IR_DistanceDataBuf[IR_GetDataCount];
+	
+	static timer waitingTimer;
+	static uint8_t timer_ok = 0;
+	
+	if(timer_ok == 0)
+	{
+		timer_ok = 1;
+		timer_set(&waitingTimer, 1);
+	}
+	
+	switch(step)
+	{
+		case 0x00:
+			if(timer_expired(&waitingTimer))
+			{
+				newValue = IR_GetDistanceData(1);
+// 				printf("\r\nValue = %3.1f cm\r\n",(float)newValue);
+				step = 0x01;
+				timer_restart(&waitingTimer);
+			}
+			break;
+		case 0x01:
+			if(DifferenceCompare(newValue, oleValue, 10))		//�Ƚ��¾�ֵ�Ĳ�ֵ������ǰֵ - ֮ǰֵ��> �趨ֵʱ���²ɼ�����
+			{
+				getDataCnt = 0;
+			}
+// 			printf("\r\nCnt1 = %d, newValue = %d, oleValue = %d\r\n", getDataCnt, newValue, oleValue);
+			oleValue = newValue;
+			
+			IR_DistanceDataBuf[getDataCnt] = newValue;
+			getDataCnt++;
+			if(IR_GetDataCount == getDataCnt)							//IR_GetDataCount�����ݶ���������Ϊ�����Ѿ��ȶ��������
+			{
+				getDataCnt = 0;
+				step = 0x02;										//ת�����ݴ������
+			}else{
+				step = 0x00;	
+			}
+			break;
+			
+		case 0x02:
+			ir_Distance1 = IR_DataProcessing(IR_DistanceDataBuf, IR_GetDataCount, 0);	
+// 			printf("\r\nNo1 ---> %3.1f cm\r\n",(float)ir_Distance1);
+			ir_dataOutState1 = 1;
+			step = 0x00;
+			break;
+			
+		default:
+			step = 0x00;
+			break;
+	}
+}
+
+/*
+***********************************************************************
+*	�� �� ��: IR_GetDistanceTask_02
+*	����˵��: ��ȡ����������
+*	��    �Σ���
+*	�� �� ֵ: ���ݴ���״̬  1���Ѵ�����ɿ��������0����δ�������
+***********************************************************************
+*/
+void IR_GetDistanceTask_02(void)
+{
+	static uint8_t step = 0x00;
+	static uint8_t getDataCnt = 0x00;
+	
+	static uint8_t newValue = 0x00;
+	static uint8_t oleValue = 0x00;
+	static uint8_t IR_DistanceDataBuf[IR_GetDataCount];
+	
+	static timer waitingTimer;
+	static uint8_t timer_ok = 0;
+	
+	if(timer_ok == 0)
+	{
+		timer_ok = 1;
+		timer_set(&waitingTimer, 1);
+	}
+	
+	switch(step)
+	{
+		case 0x00:
+			if(timer_expired(&waitingTimer))
+			{
+				newValue = IR_GetDistanceData(2);
+// 				printf("\r\nValue = %3.1f cm\r\n",(float)newValue);
+				step = 0x01;
+				timer_restart(&waitingTimer);
+			}
+			break;
+		case 0x01:
+			if(DifferenceCompare(newValue, oleValue, 10))		//�Ƚ��¾�ֵ�Ĳ�ֵ������ǰֵ - ֮ǰֵ��> �趨ֵʱ���²ɼ�����
+			{
+				getDataCnt = 0;
+			}
+// 			printf("\r\nCnt2 = %d, newValue = %d, oleValue = %d\r\n", getDataCnt, newValue, oleValue);
+			oleValue = newValue;
+			
+			IR_DistanceDataBuf[getDataCnt] = newValue;
+			getDataCnt++;
+			if(IR_GetDataCount == getDataCnt)							//10�����ݶ���������Ϊ�����Ѿ��ȶ��������
+			{
+				getDataCnt = 0;
+				step = 0x02;										//ת�����ݴ������
+			}else{
+				step = 0x00;	
+			}
+			break;
+			
+		case 0x02:
+			ir_Distance2 = IR_DataProcessing(IR_DistanceDataBuf, IR_GetDataCount, 0);	
+// 			printf("\r\nNo2 ---> %3.1f cm\r\n",(float)ir_Distance2);
+			ir_dataOutState2 = 1;
+			step = 0x00;
+			break;
+			
+		default:
+			step = 0x00;
+			break;
+	}
+}
+
+// /*
+// ***********************************************************************
+// *	�� �� ��: IR_GetDistanceTask
+// *	����˵��: ����������
+// *	��    �Σ���
+// *	�� �� ֵ: ��
+// ***********************************************************************
+// */
+// void IR_GetDistanceTask(void)
+// {
+// 	static uint8_t ULT_getDataStatus = 0x00;
+// 	
+// 	static uint8_t distance_1 = 255;
+// 	static uint8_t distance_2 = 255;
+// 	
+// 	static timer waitingTimer;
+// 	static timer responsTimer;
+// 	static uint8_t timer_ok = 0;
+// 	
+// 	if(timer_ok == 0)
+// 	{
+// 		timer_ok = 1;
+// 		timer_set(&waitingTimer, CLOCK_SECOND*2);
+// 		timer_set(&responsTimer, 3);
+// 	}
+// 	
+// 	switch(ULT_getDataStatus)
+// 	{
+// 		case 0x00:
+// 			if(timer_expired(&waitingTimer))
+// 			{
+// 				ULT_getDataStatus = 0x01;
+// 			}
+// 			break;
+// 			
+// 		case 0x01:
+// 			distance_1 = IR_GetDistanceData(1);
+// // 			if(dataOutState1 == 1)			//��һ·������ݲɼ��ɹ�
+// // 			{
+// // 				dataOutState1 = 0;
+// 				ULT_getDataStatus = 0x02;
+// // // 				printf("\r\n��1·�ɼ�OK\r\n");
+// // 			}
+// 			break;
+// 			
+// 		case 0x02:
+// 			distance_2 = IR_GetDistanceData(2);
+// // 			if(dataOutState2 == 1)			//��һ·������ݲɼ��ɹ�
+// // 			{
+// // 				dataOutState2 = 0;
+// 				ULT_getDataStatus = 0x03;
+// // // 				printf("\r\n��2·�ɼ�OK\r\n");
+// // 			}
+// 			break;
+// 			
+// 		case 0x03:
+// 			getDistance1 = distance_1;
+// 			getDistance2 = distance_2;
+// 			
+// // 			printf("\r\n��ࣺNo1 = %3.1f cm, ", (float)distance_1);
+// // 			printf("No2 = %3.1f cm\r\n", (float)distance_2);
+// // 			printf("No3 = %3.1f cm, ", (float)distance3);
+// // 			printf("No4 = %3.1f cm\r\n", (float)distance4);
+// 			ULT_getDataStatus = 0x00;
+// 			timer_restart(&waitingTimer);
+// 			break;
+// 	}
+// }
+
+/******************** (C) COPYRIGHT 2017 CXHY *****END OF FILE*******************/
diff --git a/STM32_4路称重_Git提交精简工程/src/HARDWARE/IR_Distancer/IR_Distancer.h b/STM32_4路称重_Git提交精简工程/src/HARDWARE/IR_Distancer/IR_Distancer.h
new file mode 100755
index 0000000..e632316
--- /dev/null
+++ b/STM32_4路称重_Git提交精简工程/src/HARDWARE/IR_Distancer/IR_Distancer.h
@@ -0,0 +1,25 @@
+/*************************** (C) COPYRIGHT 2017 CXHY ****************************
+ * �ļ���  ��IR_Distancer.h
+ * ��  ��  ����������������     
+ * ��  ��  ��V1.0
+ * ��  ��  ��XuZhongPing
+ * ��  ��  ��2017/08/04 
+*********************************************************************************/
+#ifndef __IR_Distancer_H
+#define	__IR_Distancer_H
+#include "stm32f10x.h"
+
+extern uint8_t ir_Distance1;
+extern uint8_t ir_dataOutState1;
+extern uint8_t ir_Distance2;
+extern uint8_t ir_dataOutState2;
+
+void IR_GetAdc(void);
+
+uint8_t IR_GetDistanceData(uint8_t num);
+void IR_GetDistanceTask_01(void);
+void IR_GetDistanceTask_02(void);
+
+#endif
+
+/******************** (C) COPYRIGHT 2017 CXHY *****END OF FILE*******************/
diff --git a/STM32_4路称重_Git提交精简工程/src/HARDWARE/KEY/key.c b/STM32_4路称重_Git提交精简工程/src/HARDWARE/KEY/key.c
new file mode 100755
index 0000000..242c1d8
--- /dev/null
+++ b/STM32_4路称重_Git提交精简工程/src/HARDWARE/KEY/key.c
@@ -0,0 +1,648 @@
+/*************************** (C) COPYRIGHT 2017 CXHY ****************************
+ * �ļ���  ��key.c
+ * ��  ��  ��������������
+ * ��  ��  ��V1.0
+ * ��  ��  ��XuZhongPing
+ * ��  ��  ��2020/03/30 
+*********************************************************************************/
+#include "key.h"
+#include "timer.h"
+
+//�������ӿ�
+#define KEY1_PORT_PeriphClock 	RCC_APB2Periph_GPIOA
+#define KEY1_PORT								GPIOA
+#define KEY1_PIN								GPIO_Pin_5
+
+#define KEY2_PORT_PeriphClock 	RCC_APB2Periph_GPIOA
+#define KEY2_PORT								GPIOA
+#define KEY2_PIN								GPIO_Pin_7
+
+#define KEY3_PORT_PeriphClock 	RCC_APB2Periph_GPIOC
+#define KEY3_PORT								GPIOC
+#define KEY3_PIN								GPIO_Pin_5
+
+#define KEY4_PORT_PeriphClock 	RCC_APB2Periph_GPIOB
+#define KEY4_PORT								GPIOB
+#define KEY4_PIN								GPIO_Pin_1
+
+//LEDָʾ�ƽӿ�
+#define KEY1_LED_PeriphClock 		RCC_APB2Periph_GPIOA
+#define KEY1_LED_PORT						GPIOA	
+#define KEY1_LED_PIN						GPIO_Pin_4
+
+#define KEY2_LED_PeriphClock 		RCC_APB2Periph_GPIOA
+#define KEY2_LED_PORT						GPIOA	
+#define KEY2_LED_PIN						GPIO_Pin_6
+
+#define KEY3_LED_PeriphClock 		RCC_APB2Periph_GPIOC
+#define KEY3_LED_PORT						GPIOC
+#define KEY3_LED_PIN						GPIO_Pin_4
+
+#define KEY4_LED_PeriphClock 		RCC_APB2Periph_GPIOB
+#define KEY4_LED_PORT						GPIOB
+#define KEY4_LED_PIN						GPIO_Pin_0
+
+//��λ����
+#define LIMI_KEY1_PeriphClock 	RCC_APB2Periph_GPIOB
+#define LIMI_KEY1_PORT					GPIOB
+#define LIMI_KEY1_PIN						GPIO_Pin_8
+
+#define LIMI_KEY2_PeriphClock 	RCC_APB2Periph_GPIOB
+#define LIMI_KEY2_PORT					GPIOB
+#define LIMI_KEY2_PIN						GPIO_Pin_9
+
+#define LIMI_KEY3_PeriphClock 	RCC_APB2Periph_GPIOC
+#define LIMI_KEY3_PORT					GPIOC
+#define LIMI_KEY3_PIN						GPIO_Pin_0
+
+#define LIMI_KEY4_PeriphClock 	RCC_APB2Periph_GPIOC
+#define LIMI_KEY4_PORT					GPIOC
+#define LIMI_KEY4_PIN						GPIO_Pin_1
+
+uint8_t keyBit = 0;											//�����ɼ���λ��Ϻ��ֵ
+uint8_t keyReleaseMark = 0;							//�����ɿ���־
+uint8_t keyValue;												//��ť��ֵ
+
+uint8_t keyNum = 0;											//��������İ������
+uint8_t keyStatus = 0;									//��Ӧ����İ���״̬
+
+uint8_t optoKeyStatus = 0;							//��翪��״̬����MCU2���룩
+
+uint8_t humanSensingKeyStatus = 0;			//�����Ӧ����״̬
+
+uint8_t keyType = 1;										//0:��е������1����������
+	
+/*
+***********************************************************************
+*	�� �� ��: KeyInit
+*	����˵��: ����IO�ڳ�ʼ��
+*	��    �Σ���
+*	�� �� ֵ: ��
+***********************************************************************
+*/
+void KeyInit(void)
+{ 
+ 	GPIO_InitTypeDef GPIO_InitStructure;
+	
+	RCC_APB2PeriphClockCmd(KEY1_PORT_PeriphClock, ENABLE);		//ʹ��IO��ʱ��
+	RCC_APB2PeriphClockCmd(KEY2_PORT_PeriphClock, ENABLE);
+	RCC_APB2PeriphClockCmd(KEY3_PORT_PeriphClock, ENABLE);
+	RCC_APB2PeriphClockCmd(KEY4_PORT_PeriphClock, ENABLE);
+	
+	RCC_APB2PeriphClockCmd(KEY1_LED_PeriphClock, ENABLE);		//ʹ��IO��ʱ��
+	RCC_APB2PeriphClockCmd(KEY2_LED_PeriphClock, ENABLE);
+	RCC_APB2PeriphClockCmd(KEY3_LED_PeriphClock, ENABLE);
+	RCC_APB2PeriphClockCmd(KEY4_LED_PeriphClock, ENABLE);
+	
+	RCC_APB2PeriphClockCmd(LIMI_KEY1_PeriphClock, ENABLE);		//ʹ��IO��ʱ��
+	RCC_APB2PeriphClockCmd(LIMI_KEY2_PeriphClock, ENABLE);
+	RCC_APB2PeriphClockCmd(LIMI_KEY3_PeriphClock, ENABLE);
+	RCC_APB2PeriphClockCmd(LIMI_KEY4_PeriphClock, ENABLE);
+
+// 	GPIO_PinRemapConfig(GPIO_Remap_SWJ_JTAGDisable , ENABLE);		//�ر�JTAG��PB3,PB4���ù���
+
+//�����ӿڳ�ʼ��----------------	
+	//��һ·����IO������
+	GPIO_InitStructure.GPIO_Pin = KEY1_PIN;			 				
+	GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU; 		 		
+	GPIO_Init(KEY1_PORT, &GPIO_InitStructure);	
+	
+	//�ڶ�·����IO������
+	GPIO_InitStructure.GPIO_Pin = KEY2_PIN;			 				
+	GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU; 		 			
+	GPIO_Init(KEY2_PORT, &GPIO_InitStructure);	
+	
+	//����·����IO������
+	GPIO_InitStructure.GPIO_Pin = KEY3_PIN;			 				
+	GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU; 		 		
+	GPIO_Init(KEY3_PORT, &GPIO_InitStructure);	
+	
+	//����·����IO������
+	GPIO_InitStructure.GPIO_Pin = KEY4_PIN;			 				
+	GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU; 			
+	GPIO_Init(KEY4_PORT, &GPIO_InitStructure);
+
+//LED�ƽӿڳ�ʼ��----------------
+	//��һ·������IO������
+	GPIO_InitStructure.GPIO_Pin = KEY1_LED_PIN;													
+ 	GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP; 		 		
+ 	GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;		 							
+ 	GPIO_Init(KEY1_LED_PORT, &GPIO_InitStructure);		
+	GPIO_SetBits(KEY1_LED_PORT, KEY1_LED_PIN);
+
+	//�ڶ�·������IO������
+	GPIO_InitStructure.GPIO_Pin = KEY2_LED_PIN;													
+ 	GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP; 		 	
+ 	GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;		 							
+ 	GPIO_Init(KEY2_LED_PORT, &GPIO_InitStructure);
+	GPIO_SetBits(KEY2_LED_PORT, KEY2_LED_PIN);
+	
+	//����·������IO������
+	GPIO_InitStructure.GPIO_Pin = KEY3_LED_PIN;													
+ 	GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP; 		 	
+ 	GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;		 							
+ 	GPIO_Init(KEY3_LED_PORT, &GPIO_InitStructure);
+	GPIO_SetBits(KEY3_LED_PORT, KEY3_LED_PIN);
+	
+	//����·������IO������
+	GPIO_InitStructure.GPIO_Pin = KEY4_LED_PIN;													
+ 	GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP; 		 	
+ 	GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;		 							
+ 	GPIO_Init(KEY4_LED_PORT, &GPIO_InitStructure);
+	GPIO_SetBits(KEY4_LED_PORT, KEY4_LED_PIN);
+	
+//��λ���ؽӿڳ�ʼ��----------------	
+	//��һ·��λ����IO������
+	GPIO_InitStructure.GPIO_Pin = LIMI_KEY1_PIN;													
+ 	GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU; 		 				 							
+ 	GPIO_Init(LIMI_KEY1_PORT, &GPIO_InitStructure);	
+	
+	//�ڶ�·��λ����IO������
+	GPIO_InitStructure.GPIO_Pin = LIMI_KEY2_PIN;													
+ 	GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU; 		 				 							
+ 	GPIO_Init(LIMI_KEY2_PORT, &GPIO_InitStructure);	
+	
+	//����·��λ����IO������
+	GPIO_InitStructure.GPIO_Pin = LIMI_KEY3_PIN;													
+ 	GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU; 		 				 							
+ 	GPIO_Init(LIMI_KEY3_PORT, &GPIO_InitStructure);
+	
+	//����·��λ����IO������
+	GPIO_InitStructure.GPIO_Pin = LIMI_KEY4_PIN;													
+ 	GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU; 		 				 							
+ 	GPIO_Init(LIMI_KEY4_PORT, &GPIO_InitStructure);
+}
+
+/*
+***********************************************************************
+*	�� �� ��: KeysCanning
+*	����˵��: ����ɨ��
+*	��    �Σ���
+*	�� �� ֵ: ���ض�Ӧ���صļ�ֵ
+***********************************************************************
+*/
+uint8_t KeyScanning(void)
+{
+	static uint8_t key_state = 0, key_value;
+	uint8_t key_press, key_return = 0;
+	
+	static timer keyLongPressTimer;
+	static uint8_t timer_ok = 0;
+	if(timer_ok == 0)
+	{
+		timer_ok = 1;
+		timer_set(&keyLongPressTimer, CLOCK_SECOND*2);		//�趨����ʱ��Ϊ2S
+	}
+
+	switch (key_state)
+	{
+		case 0x00:		// ������ʼ̬
+			if(KEY1 == 0)
+			{	
+				key_value = 1; 
+				key_state = 0x01;					// �������£�״̬ת������ȷ��̬
+			}else if(KEY2 == 0){
+				key_value = 2; 
+				key_state = 0x01;					// �������£�״̬ת������ȷ��̬
+			}
+			else if(KEY3 == 0){
+				key_value = 3; 
+				key_state = 0x01;					// �������£�״̬ת������ȷ��̬
+			}
+			else if(KEY4 == 0){
+				key_value = 4; 
+				key_state = 0x01;					// �������£�״̬ת������ȷ��̬
+			}else{
+				key_value = 0;
+			}
+			break;
+			
+		case 0x01:		// ����ȷ��̬
+			if(KEY1 == 0)
+			{	
+				key_press = 1; 
+			}else if(KEY2 == 0){
+				key_press = 2; 
+			}
+			else if(KEY3 == 0){
+				key_press = 3; 
+			}
+			else if(KEY4 == 0){
+				key_press = 4; 
+			}else{
+				key_press = 0;
+			}
+
+			if(key_value == key_press)
+			{
+			 	key_return = key_value;
+				key_state = 0x02;	 				// �������£�״̬ת������ȷ��̬
+// 				printf("\r\n�̰�KEY = %d\r\n", key_return);
+				timer_restart(&keyLongPressTimer);
+				break;
+			}else{
+				key_state = 0x00;
+			}
+			break;
+			
+		case 0x02:		// �������
+			if(timer_expired(&keyLongPressTimer))
+			{
+				if(key_value == 1)						//����1���������11
+				{
+					key_return = 0x11;
+				}else if(key_value == 2){
+					key_return = 0x22;
+				}else if(key_value == 3){
+					key_return = 0x33;
+				}else if(key_value == 4){
+					key_return = 0x44;
+				}
+				key_state = 0x03;
+				
+// 				printf("\r\n����KEY = %d\r\n", key_return);
+				break;
+			}
+			
+			if((KEY1 == 1) && (KEY2 == 1) && (KEY3 == 1) && (KEY4 == 1))
+			{
+				keyReleaseMark = 1;
+				key_state = 0x00;	// �������ͷţ�ת����������ʼ̬
+// 				printf("\r\n�̰��ɿ�\r\n");
+				break;
+			}
+			break;
+
+		case 0x03:		// �����ͷ�
+			if((KEY1 == 1) && (KEY2 == 1) && (KEY3 == 1) && (KEY4 == 1))
+			{
+				keyReleaseMark = 1;
+				key_state = 0x00;	// �������ͷţ�ת����������ʼ̬
+// 				printf("\r\n�����ɿ�\r\n");
+			}
+			break;
+	}	
+	return key_return;
+}
+
+/*
+***********************************************************************
+*	�� �� ��: TouchKeyScanning
+*	����˵��: ��������ɨ��
+*	��    �Σ���
+*	�� �� ֵ: ���ض�Ӧ���صļ�ֵ
+***********************************************************************
+*/
+uint8_t TouchKeyScanning(void)
+{
+	static uint8_t key_state = 0, key_value;
+	uint8_t key_press = 0, key_return = 0;
+	
+	static timer keyLongPressTimer;
+	static uint8_t timer_ok = 0;
+	if(timer_ok == 0)
+	{
+		timer_ok = 1;
+		timer_set(&keyLongPressTimer, CLOCK_SECOND*2);		//�趨����ʱ��Ϊ2S
+	}
+	
+	keyBit = (KEY3 << 2) | (KEY2 << 1) | KEY1;
+// 	printf("\r\nswkey = %x\r\n", keyBit);
+	switch (key_state)
+	{
+		case 0x00:		// ������ʼ̬
+			if(keyBit > 0)
+			{
+				switch(keyBit)
+				{
+					case 0x01: key_value = 1; break;
+					case 0x02: key_value = 2; break;
+					case 0x03: key_value = 3; break;
+					case 0x04: key_value = 4; break;
+					case 0x05: key_value = 5; break;
+					default:	 key_value = 0; break;
+				}
+				key_state = 0x01;					// �������£�״̬ת������ȷ��̬
+			}else{
+				key_value = 0;
+			}
+			break;
+			
+		case 0x01:		// ����ȷ��̬
+			if(keyBit > 0)
+			{
+				switch(keyBit)
+				{
+					case 0x01: key_press = 1; break;
+					case 0x02: key_press = 2; break;
+					case 0x03: key_press = 3; break;
+					case 0x04: key_press = 4; break;
+					case 0x05: key_press = 5; break;
+					default:	 key_press = 0; break;
+				}
+			}else{
+				key_value = 0;
+			}
+			
+			if(key_value == key_press)
+			{
+			 	key_return = key_value;
+				key_state = 0x02;	 				// �������£�״̬ת������ȷ��̬
+// 				printf("\r\n�̰�KEY = %d\r\n", key_return);
+				timer_restart(&keyLongPressTimer);
+				break;
+			}else{
+				key_state = 0x00;
+			}
+			break;
+			
+		case 0x02:		// �������
+			if(timer_expired(&keyLongPressTimer))
+			{
+				if(key_value == 1)						//����1���������11
+				{
+					key_return = 0x11;
+				}else if(key_value == 2){
+					key_return = 0x22;
+				}else if(key_value == 3){
+					key_return = 0x33;
+				}else if(key_value == 4){
+					key_return = 0x44;
+				}else if(key_value == 5){
+					key_return = 0x55;
+				}
+				key_state = 0x03;
+				
+// 				printf("\r\n����KEY = %d\r\n", key_return);
+				break;
+			}
+			
+			if(keyBit == 0x00)
+			{
+				key_state = 0x00;	// �������ͷţ�ת����������ʼ̬
+				keyReleaseMark = 1;
+// 				printf("\r\n�̰��ɿ�\r\n");
+				break;
+			}
+			break;
+
+		case 0x03:		// �����ͷ�
+			if(keyBit == 0x00)
+			{
+				key_state = 0x00;	// �������ͷţ�ת����������ʼ̬
+				keyReleaseMark = 1;
+// 				printf("\r\n�����ɿ�\r\n");
+			}
+			break;
+	}	
+	return key_return;
+}
+
+/*
+***********************************************************************
+*	�� �� ��: SetKeyLedON
+*	����˵��: ����������Ӧ��LED��
+*	��    ��:	whichOne -> ָ����LED��
+*	�� �� ֵ: ��
+***********************************************************************
+*/
+void SetKeyLedON(uint8_t whichOne)
+{
+	switch(whichOne)
+	{
+		case 1:
+			GPIO_ResetBits(KEY1_LED_PORT, KEY1_LED_PIN);
+			break;
+			
+		case 2:
+			GPIO_ResetBits(KEY2_LED_PORT, KEY2_LED_PIN);
+			break; 
+			
+		case 3:
+			GPIO_ResetBits(KEY3_LED_PORT, KEY3_LED_PIN);
+			break;
+			
+		case 4:
+			GPIO_ResetBits(KEY4_LED_PORT, KEY4_LED_PIN);
+			break;
+			
+// 		case 1:
+// 			GPIO_SetBits(KEY1_LED_PORT, KEY1_LED_PIN);
+// 			break;
+// 			
+// 		case 2:
+// 			GPIO_SetBits(KEY2_LED_PORT, KEY2_LED_PIN);
+// 			break; 
+// 			
+// 		case 3:
+// 			GPIO_SetBits(KEY3_LED_PORT, KEY3_LED_PIN);
+// 			break;
+// 			
+// 		case 4:
+// 			GPIO_SetBits(KEY4_LED_PORT, KEY4_LED_PIN);
+// 			break; 
+			
+		default:
+			break;
+	}
+}
+
+/*
+***********************************************************************
+*	�� �� ��: SetKeyLedAllON
+*	����˵��: ����ȫ��������LED��
+*	��    ��:	��
+*	�� �� ֵ: ��
+***********************************************************************
+*/
+void SetKeyLedAllON(void)
+{
+	GPIO_ResetBits(KEY1_LED_PORT, KEY1_LED_PIN);
+	GPIO_ResetBits(KEY2_LED_PORT, KEY2_LED_PIN);
+	GPIO_ResetBits(KEY3_LED_PORT, KEY3_LED_PIN);
+	GPIO_ResetBits(KEY4_LED_PORT, KEY4_LED_PIN);
+	
+// 	GPIO_SetBits(KEY1_LED_PORT, KEY1_LED_PIN);
+// 	GPIO_SetBits(KEY2_LED_PORT, KEY2_LED_PIN);
+// 	GPIO_SetBits(KEY3_LED_PORT, KEY3_LED_PIN);
+// 	GPIO_SetBits(KEY4_LED_PORT, KEY4_LED_PIN);
+}
+
+/*
+***********************************************************************
+*	�� �� ��: SetKeyLedOFF
+*	����˵��: Ϩ�ư�����Ӧ��LED��
+*	��    ��:	whichOne -> ָ����LED��
+*	�� �� ֵ: ��
+***********************************************************************
+*/
+void SetKeyLedOFF(uint8_t whichOne)
+{
+	switch(whichOne)
+	{
+		case 1:
+			GPIO_SetBits(KEY1_LED_PORT, KEY1_LED_PIN);
+			break;
+			
+		case 2:
+			GPIO_SetBits(KEY2_LED_PORT, KEY2_LED_PIN);
+			break; 
+			
+		case 3:
+			GPIO_SetBits(KEY3_LED_PORT, KEY3_LED_PIN);
+			break;
+			
+		case 4:
+			GPIO_SetBits(KEY4_LED_PORT, KEY4_LED_PIN);
+			break; 
+			
+// 		case 1:
+// 			GPIO_ResetBits(KEY1_LED_PORT, KEY1_LED_PIN);
+// 			break;
+// 			
+// 		case 2:
+// 			GPIO_ResetBits(KEY2_LED_PORT, KEY2_LED_PIN);
+// 			break; 
+// 			
+// 		case 3:
+// 			GPIO_ResetBits(KEY3_LED_PORT, KEY3_LED_PIN);
+// 			break;
+// 			
+// 		case 4:
+// 			GPIO_ResetBits(KEY4_LED_PORT, KEY4_LED_PIN);
+// 			break; 
+			
+		default:
+			break;
+	}
+}
+
+/*
+***********************************************************************
+*	�� �� ��: SetKeyLedAllOFF
+*	����˵��: Ϩ��ȫ��������LED��
+*	��    ��:	��
+*	�� �� ֵ: ��
+***********************************************************************
+*/
+void SetKeyLedAllOFF(void)
+{
+	GPIO_SetBits(KEY1_LED_PORT, KEY1_LED_PIN);
+	GPIO_SetBits(KEY2_LED_PORT, KEY2_LED_PIN);
+	GPIO_SetBits(KEY3_LED_PORT, KEY3_LED_PIN);
+	GPIO_SetBits(KEY4_LED_PORT, KEY4_LED_PIN);
+	
+// 	GPIO_ResetBits(KEY1_LED_PORT, KEY1_LED_PIN);
+// 	GPIO_ResetBits(KEY2_LED_PORT, KEY2_LED_PIN);
+// 	GPIO_ResetBits(KEY3_LED_PORT, KEY3_LED_PIN);
+// 	GPIO_ResetBits(KEY4_LED_PORT, KEY4_LED_PIN);
+}
+
+/*
+***********************************************************************
+*	�� �� ��: KeysTest
+*	����˵��: ��������ָʾ�Ʋ���
+*	��    ��:	��
+*	�� �� ֵ: ��
+***********************************************************************
+*/
+void KeysTest(void)
+{
+	static uint8_t keyStatus1 = 0;
+	
+	if(keyValue > 0)
+	{		
+		SetKeyLedAllOFF();
+		SetKeyLedON(keyValue);
+		
+		keyValue = 0;
+	}
+	
+// 	if((keyStatus1 != keyValue))
+// 	{
+// 		keyStatus1 = keyValue;
+// 		
+// 		SetKeyLedAllOFF();
+// 		SetKeyLedON(keyValue);
+// 	}
+}
+
+/*
+***********************************************************************
+*	�� �� ��: LimitKeysTest
+*	����˵��: ��λ���ز���
+*	��    ��:	��
+*	�� �� ֵ: ��
+***********************************************************************
+*/
+void LimitKeysTest(void)
+{
+	uint8_t limitKeySta1 = 0;
+	uint8_t limitKeySta2 = 0;
+	uint8_t limitKeySta3 = 0;
+	uint8_t limitKeySta4 = 0;
+	
+	static uint8_t limitKeyStaPre1 = 0;
+	static uint8_t limitKeyStaPre2 = 0;
+	static uint8_t limitKeyStaPre3 = 0;
+	static uint8_t limitKeyStaPre4 = 0;
+	
+	if(LIMI_KEY1 == 0)
+	{
+		limitKeySta1 = 1;
+	}else{
+		limitKeySta1 = 0;
+	}
+	
+	if(LIMI_KEY2 == 0)
+	{
+		limitKeySta2 = 1;
+	}else{
+		limitKeySta2 = 0;
+	}
+	
+	if(LIMI_KEY3 == 0)
+	{
+		limitKeySta3 = 1;
+	}else{
+		limitKeySta3 = 0;
+	}
+	
+	if(LIMI_KEY4 == 0)
+	{
+		limitKeySta4 = 1;
+	}else{
+		limitKeySta4 = 0;
+	}
+	
+	
+	if((limitKeySta1 != limitKeyStaPre1) || 
+		 (limitKeySta2 != limitKeyStaPre2) ||
+		 (limitKeySta3 != limitKeyStaPre3) ||
+		 (limitKeySta4 != limitKeyStaPre4))
+	{
+		limitKeyStaPre1 = limitKeySta1;
+		limitKeyStaPre2 = limitKeySta2;
+		limitKeyStaPre3 = limitKeySta3;
+		limitKeyStaPre4 = limitKeySta4;
+		
+		if(limitKeySta1)
+		{
+			printf("\r\n��λ����1��λ\r\n");
+		}
+		if(limitKeySta2)
+		{
+			printf("\r\n��λ����2��λ\r\n");
+		}
+		if(limitKeySta3)
+		{
+			printf("\r\n��λ����3��λ\r\n");
+		}
+		if(limitKeySta4)
+		{
+			printf("\r\n��λ����4��λ\r\n");
+		}
+	}
+}
+
+/******************** (C) COPYRIGHT 2018 Ping *****END OF FILE*******************/
diff --git a/STM32_4路称重_Git提交精简工程/src/HARDWARE/KEY/key.h b/STM32_4路称重_Git提交精简工程/src/HARDWARE/KEY/key.h
new file mode 100755
index 0000000..98bf447
--- /dev/null
+++ b/STM32_4路称重_Git提交精简工程/src/HARDWARE/KEY/key.h
@@ -0,0 +1,62 @@
+/*************************** (C) COPYRIGHT 2018 Ping ****************************
+ * �ļ���  ��key.h
+ * ��  ��  ������������������ͷ�ļ�
+ * ��  ��  ��V1.0
+ * ��  ��  ��XuZhongPing
+ * ��  ��  ��2017/03/06 
+*********************************************************************************/
+#ifndef __KEY_H
+#define __KEY_H	 
+#include "stm32f10x.h"
+#include "stdio.h"
+#include "device.h"
+
+#define KEY1				GPIO_ReadInputDataBit(GPIOA, GPIO_Pin_5)			//����1����
+#define KEY2				GPIO_ReadInputDataBit(GPIOA, GPIO_Pin_7)			//����2����
+#define KEY3				GPIO_ReadInputDataBit(GPIOC, GPIO_Pin_5)			//����3����
+#define KEY4				GPIO_ReadInputDataBit(GPIOB, GPIO_Pin_1)			//����4����
+
+//ע����2��3��4·����λ����Ӳ���ӿڽ���˳��������Ӧ��ת����Ӧ
+//����ԭ����˳��
+#ifdef FOUR_CHANNEL_AND_HARMFUL
+#define LIMI_KEY1		GPIO_ReadInputDataBit(GPIOB, GPIO_Pin_8)			//��λ����1
+#define LIMI_KEY2		GPIO_ReadInputDataBit(GPIOB, GPIO_Pin_9)			//��λ����2
+#define LIMI_KEY3		GPIO_ReadInputDataBit(GPIOC, GPIO_Pin_0)			//��λ����3
+#define LIMI_KEY4		GPIO_ReadInputDataBit(GPIOC, GPIO_Pin_1)			//��λ����4
+
+#else
+#define LIMI_KEY1 	GPIO_ReadInputDataBit(GPIOB, GPIO_Pin_8)			//��λ����1
+#define LIMI_KEY4  	GPIO_ReadInputDataBit(GPIOB, GPIO_Pin_9)			//��λ����4
+#define LIMI_KEY2  	GPIO_ReadInputDataBit(GPIOC, GPIO_Pin_0)			//��λ����2
+#define LIMI_KEY3 	GPIO_ReadInputDataBit(GPIOC, GPIO_Pin_1)			//��λ����3
+#endif
+
+extern uint8_t keyBit;											//�����ɼ���λ��Ϻ��ֵ
+extern uint8_t keyReleaseMark;							//�����ɿ���־
+extern uint8_t keyValue;										//��ť��ֵ
+
+extern uint8_t keyNum;											//��������İ������
+extern uint8_t keyStatus;										//��Ӧ����İ���״̬
+
+extern uint8_t limitKey1Value;							//��λ���ؼ�ֵ
+extern uint8_t limitKey2Value;							//��λ���ؼ�ֵ
+
+extern uint8_t optoKeyStatus;								//��翪��״̬����MCU2���룩
+extern uint8_t humanSensingKeyStatus;				//�����Ӧ����״̬
+
+extern uint8_t keyType;											//0:��е������1����������
+
+void KeyInit(void);													//������ʼ��
+uint8_t KeyScanning(void);									//��е����ɨ����
+uint8_t TouchKeyScanning(void);							//��������ɨ����
+void SetKeyLedON(uint8_t whichOne);					//������Ӧ������ָʾ��
+void SetKeyLedAllON(void);									//����ȫ��������ָʾ��
+void SetKeyLedOFF(uint8_t whichOne);		    //Ϩ���Ӧ������ָʾ��
+void SetKeyLedAllOFF(void);									//Ϩ��ȫ��������ָʾ��
+
+void KeysTest(void);
+void LimitKeysTest(void);
+
+#endif
+
+/******************** (C) COPYRIGHT 2018 Ping *****END OF FILE*******************/
diff --git a/STM32_4路称重_Git提交精简工程/src/HARDWARE/KEY/sw_key.c b/STM32_4路称重_Git提交精简工程/src/HARDWARE/KEY/sw_key.c
new file mode 100755
index 0000000..1e76452
--- /dev/null
+++ b/STM32_4路称重_Git提交精简工程/src/HARDWARE/KEY/sw_key.c
@@ -0,0 +1,117 @@
+/*************************** (C) COPYRIGHT 2017 CXHY ****************************
+ * �ļ���  ��key.c
+ * ��  ��  �����뿪����������
+ * ��  ��  ��V1.0
+ * ��  ��  ��XuZhongPing
+ * ��  ��  ��2017/03/06 
+*********************************************************************************/
+#include "sw_key.h"
+#include "delay.h"
+#include "usart.h"
+
+//���뿪��
+#define SW_KEY1_PORT				GPIOB						
+#define SW_KEY1_PIN					GPIO_Pin_4
+#define SW_KEY2_PORT				GPIOB								
+#define SW_KEY2_PIN					GPIO_Pin_3
+#define SW_KEY3_PORT				GPIOD								
+#define SW_KEY3_PIN					GPIO_Pin_7
+#define SW_KEY4_PORT				GPIOD							
+#define SW_KEY4_PIN					GPIO_Pin_6
+#define SW_KEY5_PORT				GPIOD							
+#define SW_KEY5_PIN					GPIO_Pin_5
+#define SW_KEY6_PORT				GPIOD							
+#define SW_KEY6_PIN					GPIO_Pin_4
+	
+/*
+***********************************************************************
+*	�� �� ��: SwKeyInit
+*	����˵��: ���뿪��IO�ڳ�ʼ��
+*	��    �Σ���
+*	�� �� ֵ: ��
+***********************************************************************
+*/
+void SwKeyInit(void)
+{ 
+ 	GPIO_InitTypeDef GPIO_InitStructure;
+ 	RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOB | RCC_APB2Periph_GPIOD | RCC_APB2Periph_AFIO, ENABLE);
+	
+	GPIO_PinRemapConfig(GPIO_Remap_SWJ_JTAGDisable , ENABLE);
+	
+	GPIO_InitStructure.GPIO_Pin = SW_KEY1_PIN;			 				
+	GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU; 		 		
+	GPIO_Init(SW_KEY1_PORT, &GPIO_InitStructure);	
+	
+	GPIO_InitStructure.GPIO_Pin = SW_KEY2_PIN;			 				
+	GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU; 		 		
+	GPIO_Init(SW_KEY2_PORT, &GPIO_InitStructure);	
+	
+	GPIO_InitStructure.GPIO_Pin = SW_KEY3_PIN;			 				
+	GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU; 		 		
+	GPIO_Init(SW_KEY3_PORT, &GPIO_InitStructure);	
+	
+	GPIO_InitStructure.GPIO_Pin = SW_KEY4_PIN;			 				
+	GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU; 		 		
+	GPIO_Init(SW_KEY4_PORT, &GPIO_InitStructure);	
+	
+	GPIO_InitStructure.GPIO_Pin = SW_KEY5_PIN;			 				
+	GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU; 		 		
+	GPIO_Init(SW_KEY5_PORT, &GPIO_InitStructure);	
+	
+	GPIO_InitStructure.GPIO_Pin = SW_KEY6_PIN;			 				
+	GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU; 		 		
+	GPIO_Init(SW_KEY6_PORT, &GPIO_InitStructure);	
+}
+
+/*
+***********************************************************************
+*	�� �� ��: SwKeysCanning
+*	����˵��: ���뿪��ɨ��
+*	��    �Σ���
+*	�� �� ֵ: ���ض�Ӧ���صļ�ֵ
+***********************************************************************
+*/
+uint8_t SwKeysCanning(void)
+{
+	uint8_t res = 0;
+	
+	uint8_t res1 = 0;
+	uint8_t res2 = 0;
+	uint8_t res3 = 0;
+	uint8_t res4 = 0;
+	uint8_t res5 = 0;
+	uint8_t res6 = 0;
+	
+	delay_ms(10);
+	if(SW_KEY1 == 0)
+	{
+		res1 = 1;
+	}
+	if(SW_KEY2 == 0)
+	{
+		res2 = 1;
+	}
+	if(SW_KEY3 == 0)
+	{
+		res3 = 1;
+	}
+	if(SW_KEY4 == 0)
+	{
+		res4 = 1;
+	}
+	if(SW_KEY5 == 0)
+	{
+		res5 = 1;
+	}
+	if(SW_KEY6 == 0)
+	{
+		res6 = 1;
+	}
+	
+	res = (res6 << 5) | (res5 << 4) | (res4 << 3) | (res3 << 2) | (res2 << 1) | res1;
+	printf("\r\nswkey = %x\r\n", res);
+
+	return res;
+}
+
+/******************** (C) COPYRIGHT 2018 Ping *****END OF FILE*******************/
diff --git a/STM32_4路称重_Git提交精简工程/src/HARDWARE/KEY/sw_key.h b/STM32_4路称重_Git提交精简工程/src/HARDWARE/KEY/sw_key.h
new file mode 100755
index 0000000..11d4b5f
--- /dev/null
+++ b/STM32_4路称重_Git提交精简工程/src/HARDWARE/KEY/sw_key.h
@@ -0,0 +1,26 @@
+/*************************** (C) COPYRIGHT 2018 Ping ****************************
+ * �ļ���  ��key.h
+ * ��  ��  ������������������ͷ�ļ�
+ * ��  ��  ��V1.0
+ * ��  ��  ��XuZhongPing
+ * ��  ��  ��2017/03/06 
+*********************************************************************************/
+#ifndef __SW_KEY_H
+#define __SW_KEY_H	 
+
+#include "stm32f10x.h"
+ 
+#define SW_KEY1		GPIO_ReadInputDataBit(GPIOB, GPIO_Pin_4)
+#define SW_KEY2		GPIO_ReadInputDataBit(GPIOB, GPIO_Pin_3)
+#define SW_KEY3 	GPIO_ReadInputDataBit(GPIOD, GPIO_Pin_7)
+#define SW_KEY4  	GPIO_ReadInputDataBit(GPIOD, GPIO_Pin_6)
+#define SW_KEY5 	GPIO_ReadInputDataBit(GPIOD, GPIO_Pin_5)
+#define SW_KEY6  	GPIO_ReadInputDataBit(GPIOD, GPIO_Pin_4)
+
+
+void SwKeyInit(void);													//������ʼ��
+uint8_t SwKeysCanning(void);
+
+#endif
+
+/******************** (C) COPYRIGHT 2018 Ping *****END OF FILE*******************/
diff --git a/STM32_4路称重_Git提交精简工程/src/HARDWARE/LCD/BMP.h b/STM32_4路称重_Git提交精简工程/src/HARDWARE/LCD/BMP.h
new file mode 100755
index 0000000..8f24f14
--- /dev/null
+++ b/STM32_4路称重_Git提交精简工程/src/HARDWARE/LCD/BMP.h
@@ -0,0 +1,216 @@
+#ifndef  __BMP_H__
+#define  __BMP_H__
+
+
+
+u8 BMP1[]={
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x18,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xE0,0x78,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xF3,0xF8,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x1F,0xC0,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x07,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xFF,0xF8,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xFF,0xF8,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xC0,0x18,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xC0,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xF0,0x78,
+0x00,0x00,0x00,0x0F,0xFF,0xFF,0xFF,0xFF,0x00,0x00,0x00,0x00,0x00,0x00,0xC0,0x18,
+0x00,0x00,0x01,0xFF,0xFF,0xFF,0xFF,0xFF,0xF8,0x00,0x00,0x00,0x00,0x00,0xCF,0x98,
+0x00,0x00,0x1F,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0x00,0x00,0x00,0x00,0x00,0xC6,0x18,
+0x00,0x00,0x7F,0xFF,0xFF,0xFF,0xFF,0x01,0xFF,0xF0,0x00,0x00,0x00,0x00,0xFF,0xF8,
+0x00,0x01,0xFF,0xFF,0xFF,0xFF,0xFE,0x00,0x1F,0xFE,0x00,0x00,0x00,0x00,0xFF,0xF8,
+0x00,0x07,0xFF,0xFF,0xFF,0xFF,0xFE,0x00,0x03,0xFF,0xC0,0x00,0x00,0x00,0x80,0x08,
+0x00,0x1F,0xFF,0xFF,0xFF,0xFF,0xFF,0x00,0x00,0xFF,0xF8,0x00,0x00,0x00,0x78,0x00,
+0x00,0x7F,0xFF,0xFF,0xFF,0xFF,0xFF,0x80,0x00,0x3F,0xFF,0x00,0x00,0x00,0xE0,0x00,
+0x00,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xC0,0x00,0x0F,0xFF,0xC0,0x00,0x00,0xC0,0x18,
+0x03,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xE0,0x00,0x07,0xFF,0xF8,0x00,0x00,0xFF,0xF8,
+0x07,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xF8,0x00,0x01,0xFF,0xFE,0x00,0x00,0xFF,0xF8,
+0x0F,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFE,0x00,0x00,0xFF,0xFF,0x80,0x00,0xC0,0x18,
+0x1F,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xC0,0x00,0x7F,0xFF,0xE0,0x00,0xF8,0x00,
+0x3F,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xF0,0x00,0x3F,0xFF,0xF8,0x00,0x00,0x00,
+0x3F,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0x00,0x1F,0xFF,0xFC,0x00,0xFF,0xF8,
+0x7F,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xF0,0x1F,0xFF,0xFF,0x00,0xFF,0xF8,
+0x7F,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0x80,0x87,0xE0,
+0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xC0,0x7E,0x00,
+0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xE0,0xF8,0x18,
+0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xE0,0xFF,0xF8,
+0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xC0,0x80,0x08,
+0x7F,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0x80,0x10,0xE0,
+0x7F,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xF0,0x1F,0xFF,0xFF,0x00,0xF0,0x38,
+0x3F,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0x00,0x1F,0xFF,0xFE,0x00,0xCF,0x98,
+0x3F,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xF0,0x00,0x3F,0xFF,0xF8,0x00,0xC6,0x18,
+0x1F,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xC0,0x00,0x7F,0xFF,0xE0,0x00,0xC6,0x18,
+0x0F,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFE,0x00,0x00,0x7F,0xFF,0x80,0x00,0xFF,0xF8,
+0x07,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xF8,0x00,0x01,0xFF,0xFE,0x00,0x00,0xC0,0x18,
+0x03,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xE0,0x00,0x03,0xFF,0xF0,0x00,0x00,0x00,0x00,
+0x00,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xC0,0x00,0x0F,0xFF,0xC0,0x00,0x00,0xC0,0x18,
+0x00,0x7F,0xFF,0xFF,0xFF,0xFF,0xFF,0x80,0x00,0x3F,0xFE,0x00,0x00,0x00,0xFF,0xF8,
+0x00,0x1F,0xFF,0xFF,0xFF,0xFF,0xFF,0x00,0x00,0xFF,0xF0,0x00,0x00,0x00,0xFF,0xF8,
+0x00,0x07,0xFF,0xFF,0xFF,0xFF,0xFE,0x00,0x03,0xFF,0xC0,0x00,0x00,0x00,0xC0,0x18,
+0x00,0x03,0xFF,0xFF,0xFF,0xFF,0xFE,0x00,0x3F,0xFC,0x00,0x00,0x00,0x00,0x00,0xF0,
+0x00,0x00,0x7F,0xFF,0xFF,0xFF,0xFF,0x03,0xFF,0xF0,0x00,0x00,0x00,0x00,0x00,0x38,
+0x00,0x00,0x1F,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0x00,0x00,0x00,0x00,0x00,0x00,0x18,
+0x00,0x00,0x01,0xFF,0xFF,0xFF,0xFF,0xFF,0xF0,0x00,0x00,0x00,0x00,0x00,0xC0,0x18,
+0x00,0x00,0x00,0x0F,0xFF,0xFF,0xFF,0xFE,0x00,0x00,0x00,0x00,0x00,0x00,0xFF,0xF8,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xC0,0x18,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x08,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x38,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x07,0xF8,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xFF,0xD8,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xF1,0x80,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x7F,0x88,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x03,0xF8,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x18,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00
+
+};
+
+
+u8 BMP2[]={
+0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xF8,0x03,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xE0,0x00,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xC0,0x00,0x7F,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0x80,0x00,0x7F,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0x80,0x00,0x3F,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0x00,0x00,0x3F,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0x00,0x00,0x3F,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xF8,0x00,0x00,0x1F,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0x80,0x00,0x00,0x1F,0xFF,0xFF,0xFF,0xFF,0xFE,0x07,
+0xFF,0xFF,0xFF,0xFF,0xFF,0xFC,0x00,0x00,0x00,0x1F,0xFF,0xFF,0xFF,0xFF,0xC0,0x01,
+0xFF,0xFF,0xFF,0xFF,0xFF,0xF0,0x00,0x00,0x00,0x1F,0xFF,0xFF,0xFC,0x1C,0x00,0x00,
+0xFF,0xFF,0xFF,0xFF,0xFF,0x00,0x00,0x00,0x00,0x1F,0xFF,0xFF,0xE0,0x00,0x00,0x00,
+0xFF,0xFF,0xFF,0xFF,0x00,0x00,0x00,0x00,0x00,0x1F,0xFF,0xFF,0xE0,0x00,0x00,0x00,
+0xFF,0xFF,0xFF,0xFE,0x00,0x00,0x00,0x00,0x00,0x1F,0xFF,0xFF,0xC0,0x00,0x00,0x00,
+0xFF,0xFF,0xFF,0xE0,0x00,0x00,0x00,0x00,0x00,0x1F,0xFF,0xF8,0x00,0x00,0x00,0x00,
+0xFF,0xFF,0xFF,0xC0,0x00,0x00,0x07,0x00,0x00,0x3F,0xFF,0x00,0x00,0x00,0x3F,0xC3,
+0xFF,0xFF,0xFF,0x00,0x00,0x00,0x1F,0x80,0x00,0x3F,0xF8,0x00,0x00,0x03,0xFF,0xFF,
+0xFF,0xFF,0xFF,0x00,0x00,0x00,0x3F,0x80,0x00,0x7F,0xE0,0x00,0x00,0x0F,0xFF,0xFF,
+0xFF,0xFF,0xFE,0x00,0x00,0x00,0xFF,0xC0,0x00,0x7F,0x80,0x00,0x00,0x1F,0xFF,0xFF,
+0xFF,0xFF,0xFC,0x00,0x00,0x1F,0xFF,0xC0,0x00,0xFE,0x00,0x00,0x03,0xFF,0xFF,0xFF,
+0xF0,0x7F,0xFC,0x00,0x00,0x1F,0xFF,0xE0,0x01,0xFE,0x00,0x00,0x07,0xF8,0x00,0x7F,
+0xC0,0x0F,0xFC,0x00,0x03,0xFF,0xFF,0xF8,0x03,0xF8,0x00,0x00,0x1F,0xE0,0x00,0x7F,
+0x80,0x03,0xF8,0x00,0x0F,0xFF,0xFF,0xFF,0x1E,0x00,0x00,0x00,0x1F,0xC0,0x00,0x7F,
+0x80,0x01,0xF0,0x00,0x0F,0xFF,0xFF,0xFF,0xF0,0x00,0x00,0x00,0x3F,0x80,0x00,0x7F,
+0x00,0x00,0xF0,0x00,0x07,0xFF,0xFF,0xC0,0x00,0x00,0x00,0x00,0x7F,0x80,0x07,0xFF,
+0x00,0x00,0x60,0x00,0x07,0xFF,0xFC,0x00,0x00,0x00,0x00,0x00,0x7F,0x03,0xC7,0xFF,
+0x00,0x00,0x00,0x00,0x01,0xFF,0xE0,0x00,0x00,0x00,0x00,0x00,0xFF,0x80,0x07,0xFF,
+0x00,0x00,0x00,0x00,0x00,0x7F,0x00,0x00,0x00,0x00,0x00,0x01,0xFF,0x80,0x00,0x7F,
+0x00,0x00,0x00,0x00,0x00,0x3F,0x00,0x00,0x00,0x00,0x00,0x01,0xFF,0xC0,0x00,0x7F,
+0x00,0x00,0x00,0x00,0x00,0x1E,0x00,0x00,0x00,0x00,0x00,0x01,0xFF,0xE0,0x00,0x7F,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x03,0xFF,0xF8,0x00,0x7F,
+0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x07,0xFF,0xFF,0xFF,0xFF,
+0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x0F,0xFF,0xFF,0xFF,0xFF,
+0xC0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x1F,0xFF,0x01,0x00,0x7F,
+0xFE,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x3F,0xFF,0x00,0x00,0x7F,
+0xFE,0x3F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x7F,0xFF,0x00,0x00,0x7F,
+0xFF,0xFF,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x7F,0xFF,0x04,0x00,0x7F,
+0xFF,0xFF,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xFF,0xFF,0x0C,0x38,0x7F,
+0xFF,0xFF,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xFF,0xFF,0x0C,0x78,0x7F,
+0xFF,0xFF,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0xFF,0xFF,0x00,0x00,0x7F,
+0xFF,0xFF,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x07,0xFF,0xFF,0x00,0x00,0x7F,
+0xFF,0xFF,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x0F,0xFF,0xFF,0x00,0x00,0x7F,
+0xFF,0xFF,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x1F,0xFF,0xFF,0x00,0x00,0x7F,
+0xFF,0xFF,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x3F,0xFF,0xFF,0x00,0x00,0x7F,
+0xFF,0xFF,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x7F,0xFF,0xFF,0xFF,0xFF,0xFF,
+0xFF,0xFF,0xC0,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+0xFF,0xFF,0xC0,0x00,0x00,0x00,0x00,0x00,0x00,0x03,0xFF,0xFF,0xFF,0x00,0x00,0x7F,
+0xFF,0xFF,0xC0,0x00,0x00,0x00,0x00,0x00,0x00,0x07,0xFF,0xFF,0xFF,0x00,0x00,0x7F,
+0xFF,0xFF,0xC0,0x00,0x00,0x00,0x00,0x00,0x00,0x1F,0xFF,0xFF,0xFF,0x00,0x00,0x7F,
+0xFF,0xFF,0xE0,0x00,0x00,0x00,0x00,0x00,0x00,0x7F,0xFF,0xFF,0xFF,0xFE,0x00,0x7F,
+0xFF,0xFF,0xF0,0x00,0x00,0x00,0x00,0x00,0x00,0x7F,0xFF,0xFF,0xFF,0xF8,0x01,0xFF,
+0xFF,0xFF,0xF8,0x00,0x00,0x00,0x00,0x00,0x00,0x7F,0xFF,0xFF,0xFF,0xC0,0x0F,0xFF,
+0xFF,0xFF,0xF8,0x00,0x00,0x00,0x00,0x00,0x00,0x7F,0xFF,0xFF,0xFF,0x00,0x1F,0xFF,
+0xFF,0xFF,0xFE,0x00,0x00,0x00,0x00,0x00,0x00,0x7F,0xFF,0xFF,0xFF,0x00,0x00,0x7F,
+0xFF,0xFF,0xFF,0x00,0x00,0x00,0x00,0x00,0x03,0xFF,0xFF,0xFF,0xFF,0x00,0x00,0x7F,
+0xFF,0xFF,0xFF,0xC0,0x00,0x00,0x00,0x00,0x0F,0xFF,0xFF,0xFF,0xFF,0x00,0x00,0x7F,
+0xFF,0xFF,0xFF,0xF0,0x00,0x00,0x80,0x00,0x1F,0xFF,0xFF,0xFF,0xFF,0x00,0x00,0x7F,
+0xFF,0xFF,0xFF,0xFF,0x00,0x00,0xC0,0x00,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+0xFF,0xFF,0xFF,0xFF,0x80,0x00,0xE0,0x03,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+0xFF,0xFF,0xFF,0xFF,0xC0,0x00,0xFE,0x0F,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+0xFF,0xFF,0xFF,0xFF,0xE0,0x01,0xFE,0x1F,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+0xFF,0xFF,0xFF,0xFF,0xF8,0x03,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+0xFF,0xFF,0xFF,0xFF,0xFF,0x03,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF
+
+
+};
+
+
+u8 BMP3[]={
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x01,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0x80,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x1F,0xFF,0xFF,0xF0,0x3F,0x00,0x00,0x0F,0xE0,0x00,0x00,0x00,
+0x00,0x00,0x00,0x07,0xFF,0x80,0x00,0x39,0xE1,0xD8,0x00,0x00,0x78,0x00,0x00,0x00,
+0x00,0x00,0x00,0x7F,0x80,0x05,0xF0,0x00,0x00,0x01,0xC0,0x00,0x1E,0x00,0x00,0x00,
+0x00,0x00,0x03,0xF0,0x00,0x00,0x00,0x0B,0xFF,0xA0,0x1C,0x00,0x07,0x80,0x00,0x00,
+0x00,0x00,0x0F,0x86,0x03,0xFF,0xFF,0x80,0x00,0x03,0x81,0x80,0x03,0xC0,0x00,0x00,
+0x00,0x00,0x3C,0x00,0x00,0x00,0x00,0x00,0xA0,0xE0,0x18,0x30,0x00,0xE0,0x00,0x00,
+0x00,0x00,0xF0,0x00,0x1F,0xC0,0x00,0x00,0x40,0x03,0xC3,0x0C,0x00,0x70,0x00,0x00,
+0x00,0x01,0xE0,0x01,0x80,0x01,0x00,0x00,0x80,0x00,0x1C,0x41,0x00,0x38,0x00,0x00,
+0x00,0x01,0xC0,0x06,0x00,0x00,0x00,0x01,0x00,0x00,0x03,0x10,0x40,0x38,0x00,0x00,
+0x00,0x01,0xC0,0x08,0x00,0x02,0x00,0x00,0x00,0x00,0x00,0xC4,0x00,0x1C,0x00,0x00,
+0x00,0x01,0x80,0x00,0x00,0x03,0x00,0x00,0x00,0x7E,0x00,0x20,0x00,0x0E,0x00,0x00,
+0x00,0x03,0x80,0x00,0x00,0x01,0x00,0x00,0x1F,0xFF,0xF8,0x00,0x00,0x07,0x00,0x00,
+0x00,0x07,0x00,0x00,0xFF,0x80,0x00,0x00,0x7C,0x3F,0xFF,0x00,0x00,0x03,0xC0,0x00,
+0x00,0x1E,0x00,0x07,0xFF,0xF8,0x00,0x01,0xE0,0x3F,0xFB,0xC0,0x00,0x01,0xF0,0x00,
+0x00,0x78,0x3F,0xEF,0xFF,0xFE,0x00,0x07,0x81,0xFF,0xFF,0xE3,0x80,0x3F,0xF8,0x00,
+0x00,0xF1,0x00,0x00,0xFF,0xFF,0xF8,0x07,0x1F,0xE0,0x0F,0xC8,0x00,0x00,0x5E,0x00,
+0x01,0xC4,0x00,0x00,0x00,0x1F,0xE0,0x03,0xFC,0x07,0x00,0x00,0x3F,0xF0,0x37,0x00,
+0x01,0x91,0x80,0x00,0x00,0x03,0x80,0x00,0xE0,0x03,0xC0,0x03,0xFF,0xFC,0x0B,0x80,
+0x03,0xA2,0x3F,0xE0,0x00,0x03,0x80,0x00,0x00,0x01,0xF8,0x7F,0xC0,0x0F,0x09,0xC0,
+0x03,0xA2,0xF8,0xF8,0x60,0x03,0x80,0x00,0x00,0x00,0x3F,0xF8,0x06,0x03,0x84,0xE0,
+0x03,0x84,0x00,0x3F,0xE0,0x07,0x00,0x00,0x00,0x00,0x00,0x00,0x1E,0x01,0x84,0x60,
+0x03,0xA4,0x01,0x0F,0x80,0x1E,0x00,0x00,0x00,0x00,0x00,0x00,0x7F,0x01,0xC4,0x60,
+0x03,0xA6,0x03,0x80,0x00,0xF8,0x00,0x03,0xFB,0x00,0x00,0x03,0xF7,0xE1,0xC4,0x60,
+0x01,0xF1,0x03,0x80,0x03,0xF0,0x00,0x00,0x3C,0xFF,0x80,0x3F,0x87,0xF9,0xC4,0x60,
+0x01,0xD8,0x07,0x80,0x0F,0xF0,0x00,0x3E,0x0C,0x00,0x03,0xF8,0x07,0x01,0x88,0xE0,
+0x00,0xE6,0x0F,0xC0,0x61,0x78,0x00,0xFF,0x1C,0x00,0x7F,0xE0,0x0E,0x03,0x88,0xE0,
+0x00,0x70,0xCF,0xF1,0x00,0x1E,0x00,0x00,0x38,0x0F,0xF8,0xC0,0x3E,0x03,0x11,0xC0,
+0x00,0x38,0x0F,0xFC,0x00,0x07,0xF0,0x00,0x03,0xFF,0x00,0xC1,0xFC,0x00,0x63,0x80,
+0x00,0x38,0x1F,0xBF,0x80,0x01,0xE0,0x00,0x7F,0xE0,0x03,0xCF,0xF8,0x03,0x0F,0x00,
+0x00,0x1C,0x1F,0xBB,0xFE,0x00,0x01,0xFF,0xFF,0x80,0x07,0xFE,0x70,0x00,0x7C,0x00,
+0x00,0x0C,0x1F,0x38,0x7F,0xFF,0xFF,0xF8,0x03,0x80,0x7F,0xF0,0xE0,0x00,0x78,0x00,
+0x00,0x0C,0x1F,0x38,0x70,0x1F,0x81,0xC0,0x01,0xC7,0xFF,0xC3,0xC0,0x00,0xE0,0x00,
+0x00,0x0C,0x1F,0xF8,0x60,0x0E,0x01,0xC0,0x01,0xFF,0xF9,0x87,0x80,0x01,0xC0,0x00,
+0x00,0x0C,0x0F,0xFC,0xE0,0x0E,0x01,0xC0,0x1F,0xFF,0x81,0xCE,0x00,0x03,0x80,0x00,
+0x00,0x0C,0x1F,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xF0,0x00,0xFC,0x00,0x07,0x00,0x00,
+0x00,0x0C,0x0F,0xFF,0xFF,0xFF,0xFF,0xFF,0xFE,0xE0,0x00,0xF0,0x00,0x0E,0x00,0x00,
+0x00,0x0C,0x0F,0xFF,0xFF,0xFF,0xFF,0xFF,0xC0,0xE0,0x03,0xE0,0x00,0x1C,0x00,0x00,
+0x00,0x0C,0x0E,0xFF,0xFF,0xFF,0xFF,0xF8,0x00,0x70,0x0F,0x80,0x00,0x38,0x00,0x00,
+0x00,0x0C,0x06,0x67,0xFF,0xFF,0xF8,0x30,0x00,0x70,0x3E,0x00,0x00,0x70,0x00,0x00,
+0x00,0x0C,0x07,0x73,0x8E,0x07,0x00,0x30,0x00,0x39,0xF0,0x00,0x01,0xE0,0x00,0x00,
+0x00,0x0C,0x03,0xE1,0xC7,0x03,0x80,0x30,0x00,0x1F,0xC0,0x00,0x07,0x80,0x00,0x00,
+0x00,0x0C,0x01,0xF1,0xC3,0x83,0x80,0x30,0x01,0xFE,0x01,0x83,0x1F,0x00,0x00,0x00,
+0x00,0x0C,0x00,0x3F,0xF3,0xC3,0x80,0x38,0xFF,0xE0,0x1C,0x18,0x7C,0x00,0x00,0x00,
+0x00,0x0C,0x00,0x03,0xFF,0xFF,0xFF,0xFF,0xF8,0x00,0xE0,0xC1,0xF0,0x00,0x00,0x00,
+0x00,0x1C,0x00,0x00,0x00,0x0F,0xFC,0x00,0x00,0x0E,0x0E,0x0F,0x80,0x00,0x00,0x00,
+0x00,0x1C,0x00,0x40,0x00,0x00,0x00,0x00,0x00,0xE0,0x60,0x7E,0x00,0x00,0x00,0x00,
+0x00,0x1C,0x00,0x30,0x00,0x00,0x00,0x00,0x0E,0x0F,0x03,0xF0,0x00,0x00,0x00,0x00,
+0x00,0x18,0x10,0x06,0x00,0x00,0x00,0x03,0xC0,0xE0,0x3F,0x80,0x00,0x00,0x00,0x00,
+0x00,0x18,0x0C,0x00,0x5F,0xFF,0xDC,0x00,0xB8,0x03,0xF8,0x00,0x00,0x00,0x00,0x00,
+0x00,0x18,0x03,0x80,0x00,0x00,0x00,0x78,0x00,0x1F,0x80,0x00,0x00,0x00,0x00,0x00,
+0x00,0x1C,0x00,0x3F,0xFF,0xFF,0xC0,0x00,0x01,0xFC,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x0E,0x00,0x00,0x00,0x00,0x00,0x00,0x0F,0xC0,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x0F,0x00,0x00,0x00,0x00,0x00,0x00,0xFE,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x03,0x80,0x00,0x00,0x00,0x00,0x7F,0xF0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x01,0xF0,0x00,0x00,0x00,0x1F,0xFE,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x7E,0x00,0x00,0x0F,0xFE,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x0F,0xFF,0xFF,0xFF,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00
+
+
+};
+
+
+#endif
+
diff --git a/STM32_4路称重_Git提交精简工程/src/HARDWARE/LCD/SDWe_LCD.c b/STM32_4路称重_Git提交精简工程/src/HARDWARE/LCD/SDWe_LCD.c
new file mode 100755
index 0000000..32925c1
--- /dev/null
+++ b/STM32_4路称重_Git提交精简工程/src/HARDWARE/LCD/SDWe_LCD.c
@@ -0,0 +1,302 @@
+/*************************** (C) COPYRIGHT 2017 YNHB ****************************
+ * �ļ���  ��LCD_SDWe.c
+ * ��  ��  ��7��LCD������ʾ����������     
+ * ��  ��  ��V1.0
+ * ��  ��  ��XuZhongPing
+ * ��  ��  ��2017/10/23
+*********************************************************************************/
+#include "SDWe_LCD.h"
+#include "usart5.h"
+#include "timer.h"
+#include "string.h"
+#include "stdlib.h" 
+#include "delay.h"
+
+
+/*
+***********************************************************************
+*	�� �� ��: LCD_PackProcotol
+*	����˵��: LCD��ʾ�����ƴ���Э��������
+*	��    �Σ�
+*	�� �� ֵ: ��
+***********************************************************************
+*/
+void SDWe_LCD_PackProcotol(uint8_t* data, uint16_t dataLen)
+{
+	int index = 0;
+	uint8_t buf[128];
+	
+	buf[index++]  = 0xA5;
+	buf[index++]  = 0x5A;
+	buf[index++] = dataLen;
+	if (data != NULL)
+	{
+		memcpy(&buf[index], data, dataLen);
+		index += dataLen;
+	}
+	
+	UART5_Printf((uint8_t*)buf, index);
+}
+
+/*
+***********************************************************************
+*	�� �� ��: LCD_WriteReg
+*	����˵��: дLCD�Ĵ���
+*	��    �Σ�
+*	�� �� ֵ: ��
+***********************************************************************
+*/
+void SDWe_LCD_WriteReg(uint8_t addr, uint8_t *data, uint8_t dataLen)
+{
+	int index = 0;
+	uint8_t buf[128];
+	
+	buf[index++] = 0x80;
+	buf[index++] = addr;
+	if (data != NULL)
+	{
+		memcpy(&buf[index], data, dataLen);
+		index += dataLen;
+	}
+	
+	SDWe_LCD_PackProcotol(buf, index);
+}
+
+/*
+***********************************************************************
+*	�� �� ��: LCD_WriteMem
+*	����˵��: дLCD�洢��
+*	��    �Σ�
+*	�� �� ֵ: ��
+***********************************************************************
+*/
+void SDWe_LCD_WriteMem(uint16_t addr, uint8_t *data, uint8_t dataLen)
+{
+	int index = 0;
+	uint8_t buf[128];
+	
+	buf[index++] = 0x82;
+	buf[index++] = (uint8_t)(addr >> 8);			//���ͱ�����ַ
+	buf[index++] = (uint8_t)addr;
+	if (data != NULL)
+	{
+		memcpy(&buf[index], data, dataLen);
+		index += dataLen;
+	}
+	
+	SDWe_LCD_PackProcotol(buf, index);
+}
+
+/*
+***********************************************************************
+*	�� �� ��: LCD_SetBacklight
+*	����˵��: ����LCD��������
+*	��    �Σ�val -> ����ֵ��0x00-0x40��
+*	�� �� ֵ: ��
+***********************************************************************
+*/
+void SDWe_LCD_SetBacklight(uint8_t val)
+{
+	SDWe_LCD_WriteReg(0x01, &val, 1);		//0x01Ϊ���ñ�������
+}
+
+/*
+***********************************************************************
+*	�� �� ��: LCD_ConfigEN
+*	����˵��: ��������ʹ��
+*	��    �Σ�val -> ����ֵ��0x00-0x40��
+*	�� �� ֵ: ��
+***********************************************************************
+*/
+void SDWe_LCD_ConfigEN(uint8_t cmd)
+{
+	static uint8_t ctrlReg;
+	if(cmd)
+	{
+		ctrlReg = 0x5A;
+	}else{
+		ctrlReg = 0xA5;
+	}
+	SDWe_LCD_WriteReg(0x1D, &ctrlReg, 1);		//0x01Ϊ���ñ�������
+}
+
+/*
+***********************************************************************
+*	�� �� ��: LCD_SetDisplayPage
+*	����˵��: ������ʾҳ��
+*	��    �Σ�page -> �߶�ֵ��0x00-0x40��
+*	�� �� ֵ: ��
+***********************************************************************
+*/
+void SDWe_LCD_SetBound(uint32_t baudrate)
+{
+	uint8_t val;
+	switch(baudrate)
+	{
+		case 1200:
+			val = 0x00;
+			break;
+			
+		case 9600:
+			val = 0x03;
+			break;
+			
+		case 19200:
+			val = 0x04;
+			break;
+		
+		case 38400:
+			val = 0x05;
+			break;
+			
+		default:
+			val = 0x07;
+	}
+	SDWe_LCD_WriteReg(0x11, &val, 1);		//0x03-0x04Ϊ������ʾҳ��
+}
+
+/*
+***********************************************************************
+*	�� �� ��: LCD_SetDisplayPage
+*	����˵��: ������ʾҳ��
+*	��    �Σ�page -> �߶�ֵ��0x00-0x40��
+*	�� �� ֵ: ��
+***********************************************************************
+*/
+void SDWe_LCD_SetDisplayPage(uint16_t page)
+{
+	uint8_t pageBuf[2];
+	
+	pageBuf[0] = (uint8_t)(page >> 8);
+	pageBuf[1] = (uint8_t)page; 
+	SDWe_LCD_WriteReg(0x03, pageBuf, 2);		//0x03-0x04Ϊ������ʾҳ��
+}
+
+/*
+***********************************************************************
+*	�� �� ��: SDWe_LCD_ShowNum
+*	����˵��: ��ʾ���ֱ���
+*	��    �Σ�
+*	�� �� ֵ: ��
+***********************************************************************
+*/
+void SDWe_LCD_ShowNum(uint16_t addr, uint32_t num)
+{
+	uint8_t numBuf[4];
+	
+	numBuf[0] = (uint8_t)(num >> 24);
+	numBuf[1] = (uint8_t)(num >> 16);
+	numBuf[2] = (uint8_t)(num >> 8);
+	numBuf[3] = (uint8_t)num;
+	
+	SDWe_LCD_WriteMem(addr, numBuf, 4);		
+}
+
+/*
+***********************************************************************
+*	�� �� ��: LCD_ShowString
+*	����˵��: ��ʾ�ַ���
+*	��    �Σ�
+*	�� �� ֵ: ��
+***********************************************************************
+*/
+void SDWe_LCD_ShowString(uint16_t addr, char *p)
+{
+	uint8_t len;
+	
+	len = strlen(p);
+	
+	printf("len = %d ", len);
+	
+	SDWe_LCD_WriteMem(addr, (uint8_t *)p, len);		
+}
+
+
+/*
+***********************************************************************
+*	�� �� ��: LCD_GetReturnData
+*	����˵��: ȡ��LCD��ʾ�����ص�����
+*	��    �Σ�
+*	�� �� ֵ: ��
+***********************************************************************
+*/
+void SDWe_LCD_GetReturnData(void)
+{
+	uint8_t i;
+	uint32_t tempData;
+	uint8_t dataLen;										//ָ���
+	uint8_t instructionType;						//ָ���롡
+	uint8_t regAddr;										//�Ĵ�����ַ
+	uint16_t memoryAddr;								//�洢����ַ
+	uint8_t returnDataLen;							//�������ݳ���
+	
+	static uint8_t iValue = 0;
+	
+	if(USART5_RX_STA == 0xfd)									//���յ�һ��������
+	{
+		printf("\r\n�յ�LCD��ʾ�����ص��������ڽ�����\r\n");
+		USART5_RX_STA = 0;		   								//������һ�ν���
+		
+		dataLen = USART5_RX_BUF[0];
+		instructionType = USART5_RX_BUF[1];	//ȡ��ָ����
+		
+		printf("\r\nָ��� = %d \r\n", dataLen);
+		printf("\r\nָ���� = 0x%x \r\n", instructionType);
+		
+		switch(instructionType)
+		{			
+			case 0x81:
+				regAddr = USART5_RX_BUF[2];
+				switch(regAddr)
+				{
+					case 0x00:
+						printf("\r\nVersion = V%x \r\n", USART5_RX_BUF[4]);
+						break;
+						
+					case 0x01:
+						break;
+				}
+				
+				break;
+				
+			case 0x82:
+				break;
+				
+			case 0x83:
+				break;
+		}
+	}
+}
+
+/*
+***********************************************************************
+*	�� �� ��: LCD_DisplayControlTask
+*	����˵��: LCD��ʾ�����Գ���
+*	��    �Σ�
+*	�� �� ֵ: ��
+***********************************************************************
+*/
+void SDWe_LCD_DisplayControlTask(void)
+{
+	static uint32_t page = 0;
+	
+	delay_ms(100);
+	
+// 	LCD_ShowString(0x0021, "show string");
+	
+
+// 	LCD_SetDisplayPage(page);
+// 	delay_ms(100);
+// 	page++;
+// 	if(page > 0xfffffffe)
+// 	{
+// 		page = 0;
+// 	}
+	
+	
+	
+// 	printf("\r\n��LCD��������\r\n");
+}
+
+
+/******************** (C) COPYRIGHT 2017 YNHB *****END OF FILE*******************/
diff --git a/STM32_4路称重_Git提交精简工程/src/HARDWARE/LCD/SDWe_LCD.h b/STM32_4路称重_Git提交精简工程/src/HARDWARE/LCD/SDWe_LCD.h
new file mode 100755
index 0000000..8940817
--- /dev/null
+++ b/STM32_4路称重_Git提交精简工程/src/HARDWARE/LCD/SDWe_LCD.h
@@ -0,0 +1,20 @@
+/*************************** (C) COPYRIGHT 2017 YNHB ****************************
+ * �ļ���  ��LCD_SDWe.h
+ * ��  ��  ��7��LCD������ʾ������ͷ�ļ�
+ * ��  ��  ��V1.0
+ * ��  ��  ��XuZhongPing
+ * ��  ��  ��2017/10/23
+*********************************************************************************/
+#ifndef __LCD_SDWe_H
+#define __LCD_SDWe_H	 
+#include "sys.h"
+
+void SDWe_LCD_SetDisplayPage(uint16_t page);
+void SDWe_LCD_ShowNum(uint16_t addr, uint32_t num);
+void SDWe_LCD_ShowString(uint16_t addr, char *p);
+void SDWe_LCD_GetReturnData(void);
+void SDWe_LCD_DisplayControlTask(void);
+		 				    
+#endif
+
+/******************** (C) COPYRIGHT 2017 YNHB *****END OF FILE*******************/
diff --git a/STM32_4路称重_Git提交精简工程/src/HARDWARE/LCD/display.c b/STM32_4路称重_Git提交精简工程/src/HARDWARE/LCD/display.c
new file mode 100755
index 0000000..27858cb
--- /dev/null
+++ b/STM32_4路称重_Git提交精简工程/src/HARDWARE/LCD/display.c
@@ -0,0 +1,1082 @@
+/*************************** (C) COPYRIGHT 2017 YNHB ****************************
+ * �ļ���  ��display.c
+ * ��  ��  ����ʾӦ�ó���     
+ * ��  ��  ��V1.0
+ * ��  ��  ��XuZhongPing
+ * ��  ��  ��2017/10/16 
+*********************************************************************************/
+#include "timer.h"
+#include "device.h"
+#include "lcd.h"	
+#include "display.h"
+#include "key.h"
+#include "gsm_gprs.h"
+#include "data_typedef.h"	
+
+/*
+***********************************************************************
+*	�� �� ��: Screen_SystemInit
+*	����˵��: ϵͳ��ʼ��
+*	��    �Σ���
+*	�� �� ֵ: ��
+***********************************************************************
+*/
+void Screen_SystemInit(void)
+{
+	LCD_ShowString(1, 0, "                ");
+	LCD_ShowString(2, 0, "                ");
+	LCD_ShowString(3, 0, "                ");
+	
+	LCD_ShowString(0, 0, "    ��ɫ����    ");
+	LCD_ShowString(2, 0, "--ϵͳ��������--");
+}
+
+/*
+***********************************************************************
+*	�� �� ��: GetDeviceTypeSimplifyString
+*	����˵��: ȡ���豸�����ַ������ݣ��򻯣�
+*	��    �Σ�
+*	�� �� ֵ: 
+***********************************************************************
+*/
+void GetDeviceTypeSimplifyString(char *strOut, uint8_t type)
+{
+	switch(type)
+	{
+		case PAPER:
+			sprintf(strOut, "%s", "ֽ");
+			break;
+			
+		case PLASTIC:
+			sprintf(strOut, "%s", "��");
+			break;
+			
+		case GLASS:
+			sprintf(strOut, "%s", "��");
+			break;
+			
+		case METAL:
+			sprintf(strOut, "%s", "��");
+			break;
+			
+		case RECYCLED:
+			sprintf(strOut, "%s", "��");
+			break;
+			
+		case KITCHEN:
+			sprintf(strOut, "%s", "��");
+			break;
+			
+		case SMALL_BOTTLE:
+			sprintf(strOut, "%s", "ƿ");
+			break;
+			
+// 		case BIG_BOTTLE:
+// 			sprintf(strOut, "%s", "ƿ");
+// 			break;
+// 			
+// 		case CANS:
+// 			sprintf(strOut, "%s", "ƿ");
+// 			break;
+			
+		case BATTERY:
+			sprintf(strOut, "%s", "��");
+			break;
+			
+		case FABRIC:
+			sprintf(strOut, "%s", "֯");
+			break;
+			
+		case BOOK:
+			sprintf(strOut, "%s", "��");
+			break;
+			
+		case NEWSPAPER:
+			sprintf(strOut, "%s", "��");
+			break;
+			
+		case PLASTIC_2:
+			sprintf(strOut, "%s", "��");
+			break;
+			
+		case OTHER:
+			sprintf(strOut, "%s", "��");
+			break;
+			
+		case HARMFUL:
+			sprintf(strOut, "%s", "��");
+			break;
+			
+		case DRY_WASTES:
+			sprintf(strOut, "%s", "��");
+			break;
+			
+		case WET_WASTES:
+			sprintf(strOut, "%s", "ʪ");
+			break;
+			
+		default:
+			sprintf(strOut, "%2d", type);
+			break;
+	}
+}
+
+/*
+***********************************************************************
+*	�� �� ��: GetDeviceTypeString
+*	����˵��: ȡ���豸�����ַ�������
+*	��    �Σ�
+*	�� �� ֵ: 
+***********************************************************************
+*/
+void GetDeviceTypeString(char *strOut, uint8_t type)
+{	
+	switch(type)
+	{
+		case PAPER:
+			sprintf(strOut, "%s", "ֽ��");
+			break;
+			
+		case PLASTIC:
+			sprintf(strOut, "%s", "����");
+			break;
+			
+		case GLASS:
+			sprintf(strOut, "%s", "����");
+			break;
+			
+		case METAL:
+			sprintf(strOut, "%s", "����");
+			break;
+			
+		case RECYCLED:
+			sprintf(strOut, "%s", "�ɻ�");
+			break;
+			
+		case KITCHEN:
+			sprintf(strOut, "%s", "����");
+			break;
+			
+		case SMALL_BOTTLE:
+			sprintf(strOut, "%s", "ƿ��");
+			break;
+			
+		case BIG_BOTTLE:
+			sprintf(strOut, "%s", "ƿ��");
+			break;
+			
+		case CANS:
+			sprintf(strOut, "%s", "ƿ��");
+			break;
+			
+		case BATTERY:
+			sprintf(strOut, "%s", "���");
+			break;
+			
+		case FABRIC:
+			sprintf(strOut, "%s", "֯��");
+			break;
+			
+		case BOOK:
+			sprintf(strOut, "%s", "�鱾");
+			break;
+			
+		case NEWSPAPER:
+			sprintf(strOut, "%s", "��ֽ");
+			break;
+			
+		case PLASTIC_2:
+			sprintf(strOut, "%s", "����");
+			break;
+			
+		case OTHER:
+			sprintf(strOut, "%s", "����");
+			break;
+			
+		case HARMFUL:
+			sprintf(strOut, "%s", "�к�");
+			break;
+			
+		case DRY_WASTES:
+			sprintf(strOut, "%s", "��");
+			break;
+			
+		case WET_WASTES:
+			sprintf(strOut, "%s", "ʪ");
+			break;
+			
+		default:
+			sprintf(strOut, "%s", "    ");
+			break;
+	}
+}
+
+/*
+***********************************************************************
+*	�� �� ��: Screen_ShowDeviceInfo
+*	����˵��: ��ʾ�豸��Ϣ
+*	��    �Σ�
+*	�� �� ֵ: ��
+***********************************************************************
+*/
+void Screen_ShowDeviceInfo(char *ver, uint8_t type1, uint8_t type2, uint8_t type3, uint8_t type4)
+{
+	char str[17];
+	char str1[17];
+	char str2[17];
+	char str3[17];
+	char str4[17];
+	
+	LCD_ShowString(1, 0, "                ");
+	LCD_ShowString(2, 0, "                ");
+	LCD_ShowString(3, 0, "                ");
+	
+	//�õ�Ҫ��ʾ��������Ϣ
+	GetDeviceTypeSimplifyString(str1, type1);
+	GetDeviceTypeSimplifyString(str2, type2);
+	GetDeviceTypeSimplifyString(str3, type3);
+	GetDeviceTypeSimplifyString(str4, type4);
+	
+	switch(deviceType)
+	{
+		case THREE_CLASSIFICATION:		//������
+			sprintf(str, "���ͣ�%s%s%s", str1, str2, str3);
+			break;
+			
+		case FOUR_CLASSIFICATION:		//�ķ���
+			sprintf(str, "���ͣ�%s%s%s%s", str1, str2, str3, str4);
+			break;
+	}
+	
+	LCD_ShowString(0, 2, "�豸��Ϣ");
+	LCD_ShowString(2, 0, VersionStr);
+	
+// 	LCD_ShowString(3, 0, str);
+}
+
+/*
+***********************************************************************
+*	�� �� ��: BootScreen
+*	����˵��: ��������
+*	��    �Σ���
+*	�� �� ֵ: ��
+***********************************************************************
+*/
+void BootScreen(void)
+{
+	static uint8_t displayStatus = 0x00;
+	static uint8_t connectingOK = 0;
+
+	static timer switchScreenTimer;
+	static uint8_t timer_ok = 0;
+
+	if(timer_ok == 0)
+	{
+		timer_ok = 1;
+		timer_set(&switchScreenTimer, CLOCK_SECOND*1);
+		
+		LCD_ShowString(1, 0, "                ");
+		LCD_ShowString(2, 0, "                ");
+		LCD_ShowString(3, 0, "                ");
+		
+		LCD_ShowString(0, 2, "��ӭʹ��");
+		LCD_ShowString(2, 0, "    ������      ");
+		
+	}	
+
+	if(connectingOK == 0)					//����Ƿ��Ѿ������Ϻ�̨
+	{
+		if(gsm_msg.Running == 1)		//�Ѿ������Ϻ�̨���˳���������
+		{
+			connectingOK = 1;
+		}
+		
+		if(timer_expired(&switchScreenTimer))
+		{
+			timer_restart(&switchScreenTimer);
+			switch(displayStatus)
+			{
+				case 0x00:
+					LCD_ShowString(2, 0, "                ");
+					LCD_ShowString(2, 0, "    ������.     ");
+					break;
+					
+				case 0x01:
+					LCD_ShowString(2, 0, "    ������..    ");
+					break;
+					
+				case 0x02:
+					LCD_ShowString(2, 0, "    ������...   ");
+					break;
+					
+				case 0x03:
+					LCD_ShowString(2, 0, "                ");
+					LCD_ShowString(2, 0, "    ������      ");
+					break;
+			}
+			
+			displayStatus++;
+			if(displayStatus > 3)
+			{
+				displayStatus = 0;
+			}
+		}
+	}
+}
+
+/*
+***********************************************************************
+*	�� �� ��: Screen_Default
+*	����˵��: Ĭ�Ͻ��棨�����棩
+*	��    �Σ���
+*	�� �� ֵ: ��
+***********************************************************************
+*/
+void Screen_Default(void)
+{
+	LCD_Init();
+	
+	LCD_ShowString(0, 0, "                ");
+	LCD_ShowString(1, 0, "                ");
+	LCD_ShowString(2, 0, "                ");
+	LCD_ShowString(3, 0, "                ");
+	
+// 	LCD_ShowString(0, 2, "�𴴿Ƽ�");
+// 	LCD_ShowString(0, 2, "���ܻ���");
+// 	LCD_ShowString(0, 2, "�������");
+
+
+// 	LCD_ShowString(0, 2, "��ɫ����");
+// 	LCD_ShowString(2, 0, "  ��ɨ���ˢ��  ");
+// 	LCD_ShowString(3, 0, "    ����Ͷ��    ");
+	
+	
+	LCD_ShowString(0, 1, "  ��ɫ����    ");
+	LCD_ShowString(2, 0, "��ӭ��ɨ���ˢ��");
+	LCD_ShowString(3, 0, "    ����Ͷ��    ");
+	
+	
+// 	LCD_ShowString(0, 1, "�ൺε������");
+// 	LCD_ShowString(2, 0, "��ӭ��ɨ���ˢ��");
+// 	LCD_ShowString(3, 0, "    ����Ͷ��    ");
+	
+	if((signal > 0) && (signal <= 32))
+	{
+		LCD_ShowSignal((signal+3)/8);
+	}
+}
+
+/*
+***********************************************************************
+*	�� �� ��: Screen_DeviceDisable
+*	����˵��: �豸���ý���
+*	��    �Σ���
+*	�� �� ֵ: ��
+***********************************************************************
+*/
+void Screen_DeviceDisable(void)
+{
+	LCD_ShowString(1, 0, "                ");
+	LCD_ShowString(2, 0, "                ");
+	LCD_ShowString(3, 0, "                ");
+
+
+	LCD_ShowString(0, 2, "��ɫ����");
+	LCD_ShowString(2, 0, "  �豸����ά��  ");
+	LCD_ShowString(3, 0, "    ��ͣʹ��    ");
+}
+
+/*
+***********************************************************************
+*	�� �� ��: Screen_Landing
+*	����˵��: ���ڵ�½�����û�����
+*	��    �Σ���
+*	�� �� ֵ: ��
+***********************************************************************
+*/
+void Screen_Landing(void)
+{
+	LCD_ShowString(1, 0, "                ");
+	LCD_ShowString(2, 0, "                ");
+	LCD_ShowString(3, 0, "                ");
+	
+	LCD_ShowString(2, 0, "  ���ڼ���...   ");
+}
+
+/*
+***********************************************************************
+*	�� �� ��: Screen_Query
+*	����˵��: �û���Ϣ��ѯ����
+*	��    �Σ�auth -> �Ƿ�ͨ��
+*						mode -> ��ʾ�˺Ż���IC���ţ�0���˺ţ�1��IC���ţ�
+*						inputAccount -> �û��˺�
+*						inputBalance -> �û����
+*	�� �� ֵ: ��
+***********************************************************************
+*/
+void Screen_Query(uint8_t auth, uint8_t mode, uint8_t *icCard, uint32_t inputAccount, uint32_t inputBalance)
+{	
+	uint8_t i;
+	double tempData;			
+	char str1[17];
+	char str2[17];
+	char icCardNumAfter6[7] = {0, 0, 0, 0, 0, 0, '\0'};				//���ź�6λ
+	
+	LCD_ShowString(1, 0, "                ");
+	LCD_ShowString(2, 0, "                ");
+	LCD_ShowString(3, 0, "                ");
+	
+	switch(auth)
+	{
+		case 0x01:
+// 			printf("\r\n��֤ͨ��\r\n");
+	
+			if(mode)
+			{
+				for(i = 0; i < 6; i++)		//ȡ��IC����6λ������ʾ
+				{
+					icCardNumAfter6[i] = icCard[11 + i] + '0';
+				}
+		
+				sprintf(str1, "���ţ�***%s ", icCardNumAfter6);
+				sprintf(str2, "��%.2f", (float)inputBalance/100);
+			}else{
+				sprintf(str1, "�˺ţ�%d", inputAccount);
+				sprintf(str2, "��%.2f", (float)inputBalance/100);
+			}
+			
+			if(synchronousOpenDoorMark == 0)
+			{
+				LCD_ShowString(1, 0, "����ѡͶ�����ͣ�");
+			}
+			LCD_ShowString(2, 0, str1);
+			LCD_ShowString(3, 0, str2);
+			break;
+			
+		case 0x02:
+			printf("\r\n����\r\n");
+			LCD_ShowString(2, 0, "  �����㣩  ");
+			break;
+			
+		case 0x03:
+			printf("\r\n���ű�����\r\n");
+			LCD_ShowString(2, 0, "  ���������ã�  ");
+			break;
+			
+		case 0x04:
+			printf("\r\n��������\r\n");
+			LCD_ShowString(2, 0, "  ��IC����Ч��  ");
+			break;
+			
+		case 0x05:
+			printf("\r\n������Ч\r\n");
+			LCD_ShowString(2, 0, "  ��������Ч��  ");
+			LCD_ShowString(3, 0, "Ͷ���޷���ý���");
+			break;
+			
+		default:
+			break;
+	}
+}
+
+/*
+***********************************************************************
+*	�� �� ��: Screen_Query
+*	����˵��: �û���Ϣ��ѯ����
+*	��    �Σ�auth -> �Ƿ�ͨ��
+*						mode -> ��ʾ�˺Ż���IC���ţ�0���˺ţ�1��IC���ţ�
+*						inputAccount -> �û��˺�
+*						inputBalance -> �û����
+*	�� �� ֵ: ��
+***********************************************************************
+*/
+void Screen_UserInfo(uint8_t auth, uint8_t mode, uint8_t *icCard, uint32_t inputAccount, uint32_t inputBalance)
+{	
+	uint8_t i;
+	double tempData;			
+	char str1[17];
+	char str2[17];
+	char icCardNumAfter6[7] = {0, 0, 0, 0, 0, 0, '\0'};				//���ź�6λ
+	
+	LCD_ShowString(1, 0, "                ");
+	LCD_ShowString(2, 0, "                ");
+	LCD_ShowString(3, 0, "                ");
+	
+	switch(auth)
+	{
+		case 0x01:
+			printf("\r\n��֤ͨ��\r\n");
+	
+			if(mode)
+			{
+				for(i = 0; i < 6; i++)		//ȡ��IC����6λ������ʾ
+				{
+					icCardNumAfter6[i] = icCard[11 + i] + '0';
+				}
+		
+				sprintf(str1, "���ţ�***%s ", icCardNumAfter6);
+				sprintf(str2, "��%.2f", (float)inputBalance/100);
+			}else{
+				sprintf(str1, "�˺ţ�%d", inputAccount);
+				sprintf(str2, "��%.2f", (float)inputBalance/100);
+			}
+			
+			LCD_ShowString(1, 0, str1);
+			LCD_ShowString(2, 0, str2);
+			break;
+			
+		case 0x02:
+// 			printf("\r\n����\r\n");
+			LCD_ShowString(2, 0, "  �����㣩  ");
+			break;
+			
+		case 0x03:
+// 			printf("\r\n���ű�����\r\n");
+			LCD_ShowString(2, 0, "  ���������ã�  ");
+			break;
+			
+		case 0x04:
+// 			printf("\r\n��������\r\n");
+			LCD_ShowString(2, 0, "  ��IC����Ч��  ");
+			break;
+			
+		case 0x05:
+// 			printf("\r\n������Ч\r\n");
+			LCD_ShowString(1, 0, "  ��������Ч��  ");
+			LCD_ShowString(2, 0, "Ͷ���޷���ý���");
+			break;
+			
+		case 0x06:
+// 			printf("\r\n���ڼ���...\r\n");
+			LCD_ShowString(2, 0, "  ���ڼ���...   ");
+			break;
+			
+		default:
+			break;
+	}
+}
+
+/*
+***********************************************************************
+*	�� �� ��: Screen_Query
+*	����˵��: �û���Ϣ��ѯ����
+*	��    �Σ�timerVal -> ʣ�����ʱ��
+*	�� �� ֵ: ��
+***********************************************************************
+*/
+void Screen_Countdown(uint8_t timerVal)
+{	
+	double tempData;			
+	char str1[17];
+	
+	LCD_ShowString(3, 0, "                ");
+	
+	if(timerVal != 0)
+	{
+		sprintf(str1, "     %3d������", timerVal);
+	}else{
+		sprintf(str1, "        ���ڹ���");
+	}
+	
+	LCD_ShowString(3, 0, str1);
+	
+}
+
+/*
+***********************************************************************
+*	�� �� ��: ShowWeightInfo
+*	����˵��: ��ʾ��Ӧ�����Ͷ����Ϣ
+*	��    �Σ�num -> ��һ�����壨0�����䣻1�����䣩
+*						type -> �ɻ����������
+*						inputVal -> ��Ӧ����ֵ
+*	�� �� ֵ: ��
+***********************************************************************
+*/
+static void ShowWeightInfo(uint8_t num, uint8_t type, uint16_t inputVal)
+{
+	char str[17];
+	
+	//�õ�Ҫ��ʾ��������Ϣ
+	switch(type)
+	{
+		case PAPER:
+			sprintf(str, "ֽ�ࣺ%2.2f Kg", (float)inputVal/100);
+			break;
+			
+		case PLASTIC:
+			sprintf(str, "���ϣ�%2.2f Kg", (float)inputVal/100);
+			break;
+			
+		case GLASS:
+			sprintf(str, "������%2.2f Kg", (float)inputVal/100);
+			break;
+			
+		case METAL:
+			sprintf(str, "������%2.2f Kg", (float)inputVal/100);
+			break;
+			
+		case RECYCLED:
+			sprintf(str, "�ɻ��գ�%2.2f Kg", (float)inputVal/100);
+			break;
+			
+		case KITCHEN:
+			if((leftBarrelType == RECYCLED) || (rightBarrelType == RECYCLED))
+			{
+				sprintf(str, "��  �ࣺ%2.2f Kg", (float)inputVal/100);
+			}else{
+				sprintf(str, "���ࣺ%2.2f Kg", (float)inputVal/100);
+			}
+			break;
+			
+		case SMALL_BOTTLE:
+			sprintf(str, "ƿ�ӣ�%3d ��", inputVal);
+			break;
+			
+		case BIG_BOTTLE:
+			sprintf(str, "ƿ�ӣ�%3d ��", inputVal);
+			break;
+			
+		case CANS:
+			sprintf(str, "ƿ�ӣ�%3d ��", inputVal);
+			break;
+			
+		case BATTERY:
+			sprintf(str, "��أ�%2.2f Kg", (float)inputVal/100);
+			break;
+			
+		case FABRIC:
+			sprintf(str, "֯�%2.2f Kg", (float)inputVal/100);
+			break;
+			
+		case BOOK:
+			sprintf(str, "�鱾��%2.2f Kg", (float)inputVal/100);
+			break;
+			
+		case NEWSPAPER:
+			sprintf(str, "��ֽ��%2.2f Kg", (float)inputVal/100);
+			break;
+			
+		case KITCHEN_1:
+			sprintf(str, "������%2.2f Kg", (float)inputVal/100);
+			break;
+			
+		case KITCHEN_2:
+			sprintf(str, "������%2.2f Kg", (float)inputVal/100);
+			break;
+			
+		case PLASTIC_2:
+			sprintf(str, "���ϣ�%2.2f Kg", (float)inputVal/100);
+			break;
+			
+		case OTHER:
+			if((leftBarrelType == RECYCLED) || (rightBarrelType == RECYCLED))
+			{
+				sprintf(str, "��  ����%2.2f Kg", (float)inputVal/100);
+			}else{
+				sprintf(str, "������%2.2f Kg", (float)inputVal/100);
+			}
+			break;
+			
+		case HARMFUL:
+			if((leftBarrelType == RECYCLED) || (rightBarrelType == RECYCLED))
+			{
+				sprintf(str, "��  ����%2.2f Kg", (float)inputVal/100);
+			}else{
+				sprintf(str, "�к���%2.2f Kg", (float)inputVal/100);
+			}
+			break;
+			
+		case DRY_WASTES:
+			sprintf(str, "��������%2.2f Kg", (float)inputVal/100);
+			break;
+			
+		case WET_WASTES:
+			sprintf(str, "ʪ������%2.2f Kg", (float)inputVal/100);
+			break;
+			
+		default:
+			sprintf(str, "������%2.2f Kg", (float)inputVal/100);
+			break;
+	}
+			
+	//��Ӧ��������ʾ�����������ֱ���ʾ�ڲ�ͬ������
+	switch(num)
+	{
+		case 0:		//����
+			LCD_ShowString(2, 0, str);
+			break;
+			
+		case 1:		//����
+			LCD_ShowString(3, 0, str);
+			break;
+			
+		default:
+			break;
+	}
+}
+
+/*
+***********************************************************************
+*	�� �� ��: Screen_ShowPutInInfo
+*	����˵��: ��ʾ����Ͷ�ŵ���Ϣ
+*	��    �Σ�type -> ��������
+*						leftType -> ����ɻ���������
+*						rightType -> ����ɻ���������
+*						leftVal -> ����Ͷ����ֵ
+*						rightVal -> ����Ͷ����ֵ
+*	�� �� ֵ: ��
+***********************************************************************
+*/
+void Screen_ShowPutInInfo(uint8_t type, uint8_t leftType, uint8_t rightType, uint16_t leftVal, uint16_t rightVal)
+{	
+	LCD_ShowString(1, 0, "                ");
+	LCD_ShowString(2, 0, "                ");
+	LCD_ShowString(3, 0, "                ");
+	
+	switch(type)
+	{
+		case DOUBLE_CLASSIFICATION:					//˫Ͱ480L
+			ShowWeightInfo(0, leftType, leftVal);
+			ShowWeightInfo(1, rightType, rightVal);
+			break;
+			
+		case DOUBLE_CLASSIFICATION_BOTTLE:		//˫Ͱ480L��ƿ��
+			ShowWeightInfo(0, leftType, leftVal);
+			ShowWeightInfo(1, rightType, rightVal);
+			break;
+			
+		case SINGLE_CLASSIFICATION:					//��Ͱ660L
+			ShowWeightInfo(0, leftType, leftVal);
+			break;
+			
+		default:
+			break;
+	}
+}
+
+/*
+***********************************************************************
+*	�� �� ��: Screen_ShowPutInInfo
+*	����˵��: ��ʾ����Ͷ�ŵ���Ϣ
+*	��    �Σ�type -> ��������
+*						leftType -> ����ɻ���������
+*						rightType -> ����ɻ���������
+*						leftVal -> ����Ͷ����ֵ
+*						rightVal -> ����Ͷ����ֵ
+*	�� �� ֵ: ��
+***********************************************************************
+*/
+void Screen_ShowPutInInfo2(uint16_t val1, uint16_t val2, uint16_t val3, uint16_t val4)
+{	
+	char str[17];
+	char str1[17];
+	char str2[17];
+	char str3[17];
+	char str4[17];
+	
+	LCD_DrawModeCtrl(0);
+	
+	LCD_ShowString(0, 0, "                ");
+	LCD_ShowString(1, 0, "                ");
+	LCD_ShowString(2, 0, "                ");
+	LCD_ShowString(3, 0, "                ");
+	
+	GetDeviceTypeString(str, devChannel1Type);
+	sprintf(str1, "%s��%2.2f Kg", str, (float)val1/100);
+	GetDeviceTypeString(str, devChannel2Type);
+	sprintf(str2, "%s��%2.2f Kg", str, (float)val2/100);
+	GetDeviceTypeString(str, devChannel3Type);
+	sprintf(str3, "%s��%2.2f Kg", str, (float)val3/100);
+	GetDeviceTypeString(str, devChannel4Type);
+	sprintf(str4, "%s��%2.2f Kg", str, (float)val4/100);
+	
+	switch(deviceType)
+	{
+		case THREE_CLASSIFICATION:		//������
+			LCD_ShowString(1, 0, str1);
+			LCD_ShowString(2, 0, str2);
+			LCD_ShowString(3, 0, str3);
+			break;
+			
+		case FOUR_CLASSIFICATION:		//�ķ���
+			LCD_ShowString(0, 0, str1);
+			LCD_ShowString(1, 0, str2);
+			LCD_ShowString(2, 0, str3);
+			LCD_ShowString(3, 0, str4);
+			break;
+	}
+}
+
+/*
+***********************************************************************
+*	�� �� ��: Screen_ShowPutInReward
+*	����˵��: ��ʾͶ�Ž�����Ϣ
+*	��    �Σ�beforeCapital -> Ͷ��ǰ�Ľ��
+*						afterCapital -> Ͷ�ź�Ľ��
+*	�� �� ֵ: ��
+***********************************************************************
+*/
+void Screen_ShowPutInReward(uint32_t beforeCapital, uint32_t afterCapital)
+{
+	char str1[17];
+	char str2[17];
+	uint32_t temp = 0;
+	
+	if(beforeCapital <= afterCapital)
+	{
+		temp = afterCapital - beforeCapital;
+	}
+	
+	sprintf(str1, "������%.2f", (float)temp/100);
+	sprintf(str2, "��%.2f", (float)afterCapital/100);
+	
+	LCD_ShowString(0, 0, "                ");
+	LCD_ShowString(1, 0, "                ");
+	LCD_ShowString(2, 0, "                ");
+	LCD_ShowString(3, 0, "                ");
+	
+	LCD_ShowString(0, 2, "��ɫ����");
+	LCD_ShowString(2, 0, str1);
+	LCD_ShowString(3, 0, str2);
+	
+	LCD_DrawModeCtrl(1);
+}
+
+/*
+***********************************************************************
+*	�� �� ��: Screen_Exit
+*	����˵��: �˳�ʹ��
+*	��    �Σ���
+*	�� �� ֵ: ��
+***********************************************************************
+*/
+void Screen_Exit(void)
+{
+	LCD_ShowString(0, 0, "                ");
+	LCD_ShowString(1, 0, "                ");
+	LCD_ShowString(2, 0, "                ");
+	LCD_ShowString(3, 0, "                ");
+	
+// 	LCD_ShowString(2, 0, "    ллʹ��    ");
+	
+	LCD_ShowString(0, 2, "��ɫ����");
+	LCD_ShowString(2, 0, "���л��Ϊ�����");
+	LCD_ShowString(3, 0, "  ����һ������  ");
+	
+	LCD_DrawModeCtrl(1);
+}
+
+/*
+***********************************************************************
+*	�� �� ��: Screen_ShowFull
+*	����˵��: ��ʾװ��
+*	��    �Σ���
+*	�� �� ֵ: ��
+***********************************************************************
+*/
+void Screen_ShowFull(void)
+{
+	LCD_ShowString(1, 0, "                ");
+	LCD_ShowString(2, 0, "                ");
+	LCD_ShowString(3, 0, "                ");
+	
+	LCD_ShowString(2, 0, "����װ����ͣʹ��");
+	
+// 	LCD_ShowString(2, 0, "    ����װ��    ");
+// 	LCD_ShowString(3, 0, "    ��ͣʹ��    ");
+}
+
+/*
+***********************************************************************
+*	�� �� ��: Screen_Error
+*	����˵��: ��ʾ�豸��ת����
+*	��    �Σ�type -> �������ͣ�0����Ͱ��1��˫Ͱ��
+*						pre1 -> ������������
+*						pre2 -> �ұ����������
+*	�� �� ֵ: ��
+***********************************************************************
+*/
+void Screen_Error(uint8_t type, uint8_t pre1, uint8_t pre2)
+{
+	char str[17];
+	
+	if(type)		//˫Ͱ
+	{
+		sprintf(str, "�����룺%3d %3d", pre1, pre2);
+	}else{			//��Ͱ
+		sprintf(str, "�����룺%3d", pre1);
+	}
+	
+	LCD_ShowString(1, 0, "                ");
+	LCD_ShowString(2, 0, "                ");
+	LCD_ShowString(3, 0, "                ");
+	
+	LCD_ShowString(2, 0, "�豸������ͣʹ��");
+	LCD_ShowString(3, 0, str);
+}
+
+/*
+***********************************************************************
+*	�� �� ��: Screen_ScaleCalibraEnter
+*	����˵��: ��ʾ�������ڽ���У׼
+*	��    �Σ�num -> ���̱��
+*	�� �� ֵ: ��
+***********************************************************************
+*/
+void Screen_ScaleCalibraEnter(uint8_t num)
+{
+	char str1[17];
+	
+	sprintf(str1, "У׼���̣�%d", num);
+	
+	LCD_ShowString(1, 0, "                ");
+	LCD_ShowString(2, 0, "                ");
+	LCD_ShowString(3, 0, "                ");
+	
+	LCD_ShowString(2, 0, str1);
+	LCD_ShowString(3, 0, "->���ڽ���У׼");
+}
+
+/*
+***********************************************************************
+*	�� �� ��: Screen_ScaleCalibraStart
+*	����˵��: ��ʾ�������ڽ���У׼
+*	��    �Σ�num -> ���̱��
+*	�� �� ֵ: ��
+***********************************************************************
+*/
+void Screen_ScaleCalibraStart(uint8_t num)
+{
+	char str1[17];
+	
+	sprintf(str1, "У׼���̣�%d", num);
+	
+	LCD_ShowString(1, 0, "                ");
+	LCD_ShowString(2, 0, "                ");
+	LCD_ShowString(3, 0, "                ");
+	
+	LCD_ShowString(2, 0, str1);
+	LCD_ShowString(3, 0, "->�����10Kg����");
+}
+
+/*
+***********************************************************************
+*	�� �� ��: Screen_ScaleCalibraFinish
+*	����˵��: ��ʾ�������ڽ���У׼
+*	��    �Σ�num -> ���̱��
+*	�� �� ֵ: ��
+***********************************************************************
+*/
+void Screen_ScaleCalibraFinish(uint8_t num)
+{
+	char str1[17];
+	
+	sprintf(str1, "У׼���̣�%d", num);
+	
+	LCD_ShowString(1, 0, "                ");
+	LCD_ShowString(2, 0, "                ");
+	LCD_ShowString(3, 0, "                ");
+	
+	LCD_ShowString(2, 0, str1);
+	LCD_ShowString(3, 0, "->У׼��ɣ�");
+}
+
+/*
+***********************************************************************
+*	�� �� ��: DispalyTask
+*	����˵��: ��ʾ������Ҫʵʱ���µĽ��棩
+*	��    �Σ���
+*	�� �� ֵ: ��
+***********************************************************************
+*/
+void DispalyTask(void)
+{
+	static uint8_t preSignal = 0;
+	static uint8_t preSimCardStatus = 0;
+	static uint8_t initScreen = 0;
+	static uint8_t showStatus = 0x00;
+	
+	static timer showVersionTimer;
+	static timer waitingTimer_5S;
+	static timer waitingTimer;
+	
+	static uint8_t timer_ok = 0;
+
+	if(timer_ok == 0)
+	{
+		timer_ok = 1;
+		timer_set(&showVersionTimer, CLOCK_SECOND*5);
+		timer_set(&waitingTimer_5S, CLOCK_SECOND*5);
+		timer_set(&waitingTimer, CLOCK_SECOND*60);		
+	}
+	
+	switch(showStatus)
+	{
+		case 0x00:
+			if(timer_expired(&showVersionTimer))
+			{
+				showStatus = 0x02;
+			}
+			break;
+			
+		case 0x01:
+			if(timer_expired(&showVersionTimer))
+			{
+				showStatus = 0x02;
+			}
+			break;
+			
+		case 0x02:
+			if(initScreen == 0)
+			{
+				BootScreen();	
+				
+				if(gsm_msg.Running == 1)		//�Ѿ������Ϻ�̨���˳���������
+				{
+					initScreen = 1;
+					Screen_Default();
+					showStatus = 0x03;
+				}
+				
+				if(timer_expired(&waitingTimer))
+				{
+					initScreen = 1;
+					Screen_Default();
+					showStatus = 0x03;
+				}
+			}
+			break;
+			
+		case 0x03:
+			
+			break;
+	}
+	
+//SIM��״̬��ʾ	
+	if(gsm_msg.simCardStatus != preSimCardStatus)
+	{
+		preSimCardStatus = gsm_msg.simCardStatus;
+		
+		if(gsm_msg.simCardStatus == 2)
+		{
+			LCD_ShowSignal(5);												//��ʾ�޷�ע������
+		}else if(gsm_msg.simCardStatus == 3){
+			LCD_ShowSignal(6);												//û��GPRSҵ��
+		}else if(gsm_msg.simCardStatus == 4){
+			LCD_ShowSignal(7);												//û�м�⵽��
+		}else{
+		}
+	}
+	
+	if(signal != preSignal)
+	{
+// 		printf("\r\n�����ź���ʾ%d\r\n", signal);
+		preSignal = signal;
+		if((signal > 0) && (signal <= 32))
+		{
+			LCD_ShowSignal((signal+3)/8);
+		}
+	}
+}
+
+/******************** (C) COPYRIGHT 2017 YNHB *****END OF FILE*******************/ 
diff --git a/STM32_4路称重_Git提交精简工程/src/HARDWARE/LCD/display.h b/STM32_4路称重_Git提交精简工程/src/HARDWARE/LCD/display.h
new file mode 100755
index 0000000..5678bac
--- /dev/null
+++ b/STM32_4路称重_Git提交精简工程/src/HARDWARE/LCD/display.h
@@ -0,0 +1,33 @@
+/*************************** (C) COPYRIGHT 2017 YNHB ****************************
+ * �ļ���  ��display.h
+ * ��  ��  ����ʾ����     
+ * ��  ��  ��V1.0
+ * ��  ��  ��XuZhongPing
+ * ��  ��  ��2017/10/16 
+*********************************************************************************/
+#ifndef __DISPLAY_H
+#define __DISPLAY_H	 
+#include "stdint.h" 
+
+void Screen_SystemInit(void);
+void Screen_ShowDeviceInfo(char *ver, uint8_t type1, uint8_t type2, uint8_t type3, uint8_t type4);
+void Screen_Default(void);
+void Screen_DeviceDisable(void);
+void Screen_Landing(void);
+void Screen_Query(uint8_t auth, uint8_t mode, uint8_t *icCard, uint32_t inputAccount, uint32_t inputBalance);
+void Screen_UserInfo(uint8_t auth, uint8_t mode, uint8_t *icCard, uint32_t inputAccount, uint32_t inputBalance);
+void Screen_Countdown(uint8_t timerVal);
+void Screen_ShowPutInInfo(uint8_t type, uint8_t leftType, uint8_t rightType, uint16_t leftVal, uint16_t rightVal);
+void Screen_ShowPutInInfo2(uint16_t val1, uint16_t val2, uint16_t val3, uint16_t val4);
+void Screen_ShowPutInReward(uint32_t beforeCapital, uint32_t afterCapital);
+void Screen_Exit(void);
+void Screen_ShowFull(void);
+void Screen_Error(uint8_t type, uint8_t pre1, uint8_t pre2);
+
+void Screen_ScaleCalibraEnter(uint8_t num);
+void Screen_ScaleCalibraStart(uint8_t num);
+void Screen_ScaleCalibraFinish(uint8_t num);
+
+void DispalyTask(void);
+
+#endif
diff --git a/STM32_4路称重_Git提交精简工程/src/HARDWARE/LCD/icon.h b/STM32_4路称重_Git提交精简工程/src/HARDWARE/LCD/icon.h
new file mode 100755
index 0000000..6afd0f3
--- /dev/null
+++ b/STM32_4路称重_Git提交精简工程/src/HARDWARE/LCD/icon.h
@@ -0,0 +1,192 @@
+/*************************** (C) COPYRIGHT 2017 CXHY ****************************
+ * �ļ���  ��icon.h
+ * ��  ��  ��ͼƬ��Ϣͷ�ļ�  
+ * ��  ��  ��V1.0
+ * ��  ��  ��XuZhongPing
+ * ��  ��  ��2017/10/17 
+*********************************************************************************/
+#ifndef __ICON_H__
+#define __ICON_H__	 
+#include "stdint.h"
+
+//����ȡģ
+//�ź�ͼ��
+const unsigned char signalIcon[8][32] = {
+{0x00,0x00,0x7C,0x00,0x38,0x00,0x10,0x00,0x10,0x00,0x10,0x00,0x10,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00},		//���ź�
+ 
+{0x00,0x00,0x7C,0x00,0x38,0x00,0x10,0x00,0x10,0x00,0x12,0x00,0x12,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00},		//1���ź�
+ 
+{0x00,0x00,0x7C,0x00,0x38,0x00,0x10,0x00,0x10,0x80,0x12,0x80,0x12,0x80,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00},		//2���ź�
+ 
+{0x00,0x00,0x7C,0x00,0x38,0x00,0x10,0x20,0x10,0xA0,0x12,0xA0,0x12,0xA0,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00},		//3���ź�
+ 
+{0x00,0x00,0x7C,0x00,0x38,0x08,0x10,0x28,0x10,0xA8,0x12,0xA8,0x12,0xA8,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00},   	//4���ź�
+ 
+{0x00,0x00,0x7C,0x00,0x38,0x11,0x10,0x0A,0x10,0x84,0x12,0x8A,0x12,0x91,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00},		//�޷�ע�����磨��ʶ��������
+ 
+{0x00,0x00,0x7C,0x04,0x38,0x04,0x10,0x04,0x10,0x84,0x12,0x80,0x12,0x84,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00},		//û��GPRSҵ��
+
+{0x00,0x00,0x7C,0x74,0x38,0x94,0x11,0x14,0x11,0x14,0x11,0x10,0x11,0xF4,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00}, 		//û�м�⵽��
+};
+
+//�¶ȷ��š�
+const uint8_t temperatureIcon[32] = {
+0x00,0x00,0x00,0x00,0x00,0x60,0x00,0x6E,0x00,0x1B,0x00,0x31,0x00,0x30,0x00,0x30,
+0x00,0x30,0x00,0x31,0x00,0x1B,0x00,0x0E,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00};
+
+//����Ͱͼ��
+const uint8_t Icon2[11][192] = {
+{	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x30,0x00,0x00,0x00,0x78,0x3F,0xFF,0xFF,0xF8,
+	0x3F,0xFF,0xFF,0xFC,0x08,0x00,0x00,0xD4,0x08,0x00,0x00,0x94,0x08,0x00,0x00,0x94,
+	0x08,0x00,0x00,0x94,0x08,0x00,0x00,0xA4,0x08,0x00,0x00,0xA4,0x08,0x00,0x00,0xA4,
+	0x08,0x00,0x00,0xA4,0x08,0x00,0x00,0xA4,0x08,0x00,0x00,0xA4,0x08,0x00,0x00,0xA4,
+	0x08,0x00,0x00,0x94,0x08,0x00,0x00,0x94,0x08,0x00,0x00,0x94,0x08,0x00,0x00,0x94,
+	0x08,0x00,0x00,0x8C,0x08,0x00,0x00,0x8C,0x04,0x00,0x01,0x0C,0x04,0x00,0x01,0x1C,
+	0x04,0x00,0x01,0x04,0x04,0x00,0x01,0x04,0x04,0x00,0x01,0x00,0x04,0x00,0x01,0x00,
+	0x04,0x00,0x01,0x00,0x04,0x00,0x01,0x00,0x04,0x00,0x01,0x00,0x04,0x00,0x01,0x00,
+	0x04,0x00,0x01,0x00,0x04,0x00,0x03,0x80,0x04,0x00,0x04,0x40,0x04,0x00,0x09,0x20,
+	0x04,0x00,0x0B,0xA0,0x07,0xFF,0xF9,0x20,0x03,0x80,0x04,0x40,0x03,0x80,0x03,0x80,
+	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00},		//0%
+	
+{	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x30,0x00,0x00,0x00,0x78,0x3F,0xFF,0xFF,0xF8,
+	0x3F,0xFF,0xFF,0xFC,0x08,0x00,0x00,0xD4,0x08,0x00,0x00,0x94,0x08,0x00,0x00,0x94,
+	0x08,0x00,0x00,0x94,0x08,0x00,0x00,0xA4,0x08,0x00,0x00,0xA4,0x08,0x00,0x00,0xA4,
+	0x08,0x00,0x00,0xA4,0x08,0x00,0x00,0xA4,0x08,0x00,0x00,0xA4,0x08,0x00,0x00,0xA4,
+	0x08,0x00,0x00,0x94,0x08,0x00,0x00,0x94,0x08,0x00,0x00,0x94,0x08,0x00,0x00,0x94,
+	0x08,0x00,0x00,0x8C,0x08,0x00,0x00,0x8C,0x04,0x00,0x01,0x0C,0x04,0x00,0x01,0x1C,
+	0x04,0x00,0x01,0x04,0x04,0x00,0x01,0x04,0x04,0x00,0x01,0x00,0x04,0x00,0x01,0x00,
+	0x04,0x00,0x01,0x00,0x04,0x00,0x01,0x00,0x04,0x00,0x01,0x00,0x04,0x00,0x01,0x00,
+	0x04,0x00,0x01,0x00,0x05,0xFF,0xFB,0x80,0x05,0xFF,0xF4,0x40,0x05,0xFF,0xE9,0x20,
+	0x04,0x00,0x0B,0xA0,0x07,0xFF,0xF9,0x20,0x03,0x80,0x04,0x40,0x03,0x80,0x03,0x80,
+	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00},		//10%
+	
+{	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x30,0x00,0x00,0x00,0x78,0x3F,0xFF,0xFF,0xF8,
+	0x3F,0xFF,0xFF,0xFC,0x08,0x00,0x00,0xD4,0x08,0x00,0x00,0x94,0x08,0x00,0x00,0x94,
+	0x08,0x00,0x00,0x94,0x08,0x00,0x00,0xA4,0x08,0x00,0x00,0xA4,0x08,0x00,0x00,0xA4,
+	0x08,0x00,0x00,0xA4,0x08,0x00,0x00,0xA4,0x08,0x00,0x00,0xA4,0x08,0x00,0x00,0xA4,
+	0x08,0x00,0x00,0x94,0x08,0x00,0x00,0x94,0x08,0x00,0x00,0x94,0x08,0x00,0x00,0x94,
+	0x08,0x00,0x00,0x8C,0x08,0x00,0x00,0x8C,0x04,0x00,0x01,0x0C,0x04,0x00,0x01,0x1C,
+	0x04,0x00,0x01,0x04,0x04,0x00,0x01,0x04,0x04,0x00,0x01,0x00,0x04,0x00,0x01,0x00,
+	0x04,0x00,0x01,0x00,0x04,0x00,0x01,0x00,0x05,0xFF,0xFD,0x00,0x05,0xFF,0xFD,0x00,
+	0x05,0xFF,0xFD,0x00,0x05,0xFF,0xFB,0x80,0x05,0xFF,0xF4,0x40,0x05,0xFF,0xE9,0x20,
+	0x04,0x00,0x0B,0xA0,0x07,0xFF,0xF9,0x20,0x03,0x80,0x04,0x40,0x03,0x80,0x03,0x80,
+	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00},		//20%
+	
+{	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x30,0x00,0x00,0x00,0x78,0x3F,0xFF,0xFF,0xF8,
+	0x3F,0xFF,0xFF,0xFC,0x08,0x00,0x00,0xD4,0x08,0x00,0x00,0x94,0x08,0x00,0x00,0x94,
+	0x08,0x00,0x00,0x94,0x08,0x00,0x00,0xA4,0x08,0x00,0x00,0xA4,0x08,0x00,0x00,0xA4,
+	0x08,0x00,0x00,0xA4,0x08,0x00,0x00,0xA4,0x08,0x00,0x00,0xA4,0x08,0x00,0x00,0xA4,
+	0x08,0x00,0x00,0x94,0x08,0x00,0x00,0x94,0x08,0x00,0x00,0x94,0x08,0x00,0x00,0x94,
+	0x08,0x00,0x00,0x8C,0x08,0x00,0x00,0x8C,0x04,0x00,0x01,0x0C,0x04,0x00,0x01,0x1C,
+	0x04,0x00,0x01,0x04,0x04,0x00,0x01,0x04,0x04,0x00,0x01,0x00,0x05,0xFF,0xFD,0x00,
+	0x05,0xFF,0xFD,0x00,0x05,0xFF,0xFD,0x00,0x05,0xFF,0xFD,0x00,0x05,0xFF,0xFD,0x00,
+	0x05,0xFF,0xFD,0x00,0x05,0xFF,0xFB,0x80,0x05,0xFF,0xF4,0x40,0x05,0xFF,0xE9,0x20,
+	0x04,0x00,0x0B,0xA0,0x07,0xFF,0xF9,0x20,0x03,0x80,0x04,0x40,0x03,0x80,0x03,0x80,
+	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00},		//30%
+	
+{	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x30,0x00,0x00,0x00,0x78,0x3F,0xFF,0xFF,0xF8,
+	0x3F,0xFF,0xFF,0xFC,0x08,0x00,0x00,0xD4,0x08,0x00,0x00,0x94,0x08,0x00,0x00,0x94,
+	0x08,0x00,0x00,0x94,0x08,0x00,0x00,0xA4,0x08,0x00,0x00,0xA4,0x08,0x00,0x00,0xA4,
+	0x08,0x00,0x00,0xA4,0x08,0x00,0x00,0xA4,0x08,0x00,0x00,0xA4,0x08,0x00,0x00,0xA4,
+	0x08,0x00,0x00,0x94,0x08,0x00,0x00,0x94,0x08,0x00,0x00,0x94,0x08,0x00,0x00,0x94,
+	0x08,0x00,0x00,0x8C,0x08,0x00,0x00,0x8C,0x04,0x00,0x01,0x0C,0x04,0x00,0x01,0x1C,
+	0x05,0xFF,0xFD,0x04,0x05,0xFF,0xFD,0x04,0x05,0xFF,0xFD,0x00,0x05,0xFF,0xFD,0x00,
+	0x05,0xFF,0xFD,0x00,0x05,0xFF,0xFD,0x00,0x05,0xFF,0xFD,0x00,0x05,0xFF,0xFD,0x00,
+	0x05,0xFF,0xFD,0x00,0x05,0xFF,0xFB,0x80,0x05,0xFF,0xF4,0x40,0x05,0xFF,0xE9,0x20,
+	0x04,0x00,0x0B,0xA0,0x07,0xFF,0xF9,0x20,0x03,0x80,0x04,0x40,0x03,0x80,0x03,0x80,
+	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00},		//40%
+	
+{	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x30,0x00,0x00,0x00,0x78,0x3F,0xFF,0xFF,0xF8,
+	0x3F,0xFF,0xFF,0xFC,0x08,0x00,0x00,0xD4,0x08,0x00,0x00,0x94,0x08,0x00,0x00,0x94,
+	0x08,0x00,0x00,0x94,0x08,0x00,0x00,0xA4,0x08,0x00,0x00,0xA4,0x08,0x00,0x00,0xA4,
+	0x08,0x00,0x00,0xA4,0x08,0x00,0x00,0xA4,0x08,0x00,0x00,0xA4,0x08,0x00,0x00,0xA4,
+	0x08,0x00,0x00,0x94,0x08,0x00,0x00,0x94,0x08,0x00,0x00,0x94,0x08,0x00,0x00,0x94,
+	0x08,0x00,0x00,0x8C,0x0B,0xFF,0xFE,0x8C,0x05,0xFF,0xFD,0x0C,0x05,0xFF,0xFD,0x1C,
+	0x05,0xFF,0xFD,0x04,0x05,0xFF,0xFD,0x04,0x05,0xFF,0xFD,0x00,0x05,0xFF,0xFD,0x00,
+	0x05,0xFF,0xFD,0x00,0x05,0xFF,0xFD,0x00,0x05,0xFF,0xFD,0x00,0x05,0xFF,0xFD,0x00,
+	0x05,0xFF,0xFD,0x00,0x05,0xFF,0xFB,0x80,0x05,0xFF,0xF4,0x40,0x05,0xFF,0xE9,0x20,
+	0x04,0x00,0x0B,0xA0,0x07,0xFF,0xF9,0x20,0x03,0x80,0x04,0x40,0x03,0x80,0x03,0x80,
+	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00},		//50%
+	
+{	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x30,0x00,0x00,0x00,0x78,0x3F,0xFF,0xFF,0xF8,
+	0x3F,0xFF,0xFF,0xFC,0x08,0x00,0x00,0xD4,0x08,0x00,0x00,0x94,0x08,0x00,0x00,0x94,
+	0x08,0x00,0x00,0x94,0x08,0x00,0x00,0xA4,0x08,0x00,0x00,0xA4,0x08,0x00,0x00,0xA4,
+	0x08,0x00,0x00,0xA4,0x08,0x00,0x00,0xA4,0x08,0x00,0x00,0xA4,0x08,0x00,0x00,0xA4,
+	0x08,0x00,0x00,0x94,0x08,0x00,0x00,0x94,0x0B,0xFF,0xFE,0x94,0x0B,0xFF,0xFE,0x94,
+	0x0B,0xFF,0xFE,0x8C,0x0B,0xFF,0xFE,0x8C,0x05,0xFF,0xFD,0x0C,0x05,0xFF,0xFD,0x1C,
+	0x05,0xFF,0xFD,0x04,0x05,0xFF,0xFD,0x04,0x05,0xFF,0xFD,0x00,0x05,0xFF,0xFD,0x00,
+	0x05,0xFF,0xFD,0x00,0x05,0xFF,0xFD,0x00,0x05,0xFF,0xFD,0x00,0x05,0xFF,0xFD,0x00,
+	0x05,0xFF,0xFD,0x00,0x05,0xFF,0xFB,0x80,0x05,0xFF,0xF4,0x40,0x05,0xFF,0xE9,0x20,
+	0x04,0x00,0x0B,0xA0,0x07,0xFF,0xF9,0x20,0x03,0x80,0x04,0x40,0x03,0x80,0x03,0x80,
+	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00},		//60%
+	
+{	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x30,0x00,0x00,0x00,0x78,0x3F,0xFF,0xFF,0xF8,
+	0x3F,0xFF,0xFF,0xFC,0x08,0x00,0x00,0xD4,0x08,0x00,0x00,0x94,0x08,0x00,0x00,0x94,
+	0x08,0x00,0x00,0x94,0x08,0x00,0x00,0xA4,0x08,0x00,0x00,0xA4,0x08,0x00,0x00,0xA4,
+	0x08,0x00,0x00,0xA4,0x08,0x00,0x00,0xA4,0x08,0x00,0x00,0xA4,0x0B,0xFF,0xFE,0xA4,
+	0x0B,0xFF,0xFE,0x94,0x0B,0xFF,0xFE,0x94,0x0B,0xFF,0xFE,0x94,0x0B,0xFF,0xFE,0x94,
+	0x0B,0xFF,0xFE,0x8C,0x0B,0xFF,0xFE,0x8C,0x05,0xFF,0xFD,0x0C,0x05,0xFF,0xFD,0x1C,
+	0x05,0xFF,0xFD,0x04,0x05,0xFF,0xFD,0x04,0x05,0xFF,0xFD,0x00,0x05,0xFF,0xFD,0x00,
+	0x05,0xFF,0xFD,0x00,0x05,0xFF,0xFD,0x00,0x05,0xFF,0xFD,0x00,0x05,0xFF,0xFD,0x00,
+	0x05,0xFF,0xFD,0x00,0x05,0xFF,0xFB,0x80,0x05,0xFF,0xF4,0x40,0x05,0xFF,0xE9,0x20,
+	0x04,0x00,0x0B,0xA0,0x07,0xFF,0xF9,0x20,0x03,0x80,0x04,0x40,0x03,0x80,0x03,0x80,
+	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00},		//70%
+	
+{	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x30,0x00,0x00,0x00,0x78,0x3F,0xFF,0xFF,0xF8,
+	0x3F,0xFF,0xFF,0xFC,0x08,0x00,0x00,0xD4,0x08,0x00,0x00,0x94,0x08,0x00,0x00,0x94,
+	0x08,0x00,0x00,0x94,0x08,0x00,0x00,0xA4,0x08,0x00,0x00,0xA4,0x08,0x00,0x00,0xA4,
+	0x0B,0xFF,0xFE,0xA4,0x0B,0xFF,0xFE,0xA4,0x0B,0xFF,0xFE,0xA4,0x0B,0xFF,0xFE,0xA4,
+	0x0B,0xFF,0xFE,0x94,0x0B,0xFF,0xFE,0x94,0x0B,0xFF,0xFE,0x94,0x0B,0xFF,0xFE,0x94,
+	0x0B,0xFF,0xFE,0x8C,0x0B,0xFF,0xFE,0x8C,0x05,0xFF,0xFD,0x0C,0x05,0xFF,0xFD,0x1C,
+	0x05,0xFF,0xFD,0x04,0x05,0xFF,0xFD,0x04,0x05,0xFF,0xFD,0x00,0x05,0xFF,0xFD,0x00,
+	0x05,0xFF,0xFD,0x00,0x05,0xFF,0xFD,0x00,0x05,0xFF,0xFD,0x00,0x05,0xFF,0xFD,0x00,
+	0x05,0xFF,0xFD,0x00,0x05,0xFF,0xFB,0x80,0x05,0xFF,0xF4,0x40,0x05,0xFF,0xE9,0x20,
+	0x04,0x00,0x0B,0xA0,0x07,0xFF,0xF9,0x20,0x03,0x80,0x04,0x40,0x03,0x80,0x03,0x80,
+	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00},		//80%
+	
+{	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x30,0x00,0x00,0x00,0x78,0x3F,0xFF,0xFF,0xF8,
+	0x3F,0xFF,0xFF,0xFC,0x08,0x00,0x00,0xD4,0x08,0x00,0x00,0x94,0x08,0x00,0x00,0x94,
+	0x08,0x00,0x00,0x94,0x0B,0xFF,0xFE,0xA4,0x0B,0xFF,0xFE,0xA4,0x0B,0xFF,0xFE,0xA4,
+	0x0B,0xFF,0xFE,0xA4,0x0B,0xFF,0xFE,0xA4,0x0B,0xFF,0xFE,0xA4,0x0B,0xFF,0xFE,0xA4,
+	0x0B,0xFF,0xFE,0x94,0x0B,0xFF,0xFE,0x94,0x0B,0xFF,0xFE,0x94,0x0B,0xFF,0xFE,0x94,
+	0x0B,0xFF,0xFE,0x8C,0x0B,0xFF,0xFE,0x8C,0x05,0xFF,0xFD,0x0C,0x05,0xFF,0xFD,0x1C,
+	0x05,0xFF,0xFD,0x04,0x05,0xFF,0xFD,0x04,0x05,0xFF,0xFD,0x00,0x05,0xFF,0xFD,0x00,
+	0x05,0xFF,0xFD,0x00,0x05,0xFF,0xFD,0x00,0x05,0xFF,0xFD,0x00,0x05,0xFF,0xFD,0x00,
+	0x05,0xFF,0xFD,0x00,0x05,0xFF,0xFB,0x80,0x05,0xFF,0xF4,0x40,0x05,0xFF,0xE9,0x20,
+	0x04,0x00,0x0B,0xA0,0x07,0xFF,0xF9,0x20,0x03,0x80,0x04,0x40,0x03,0x80,0x03,0x80,
+	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00},		//90%
+	
+{	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x30,0x00,0x00,0x00,0x78,0x3F,0xFF,0xFF,0xF8,
+	0x3F,0xFF,0xFF,0xFC,0x08,0x00,0x00,0xD4,0x0B,0xFF,0xFE,0x94,0x0B,0xFF,0xFE,0x94,
+	0x0B,0xFF,0xFE,0x94,0x0B,0xFF,0xFE,0xA4,0x0B,0xFF,0xFE,0xA4,0x0B,0xFF,0xFE,0xA4,
+	0x0B,0xFF,0xFE,0xA4,0x0B,0xFF,0xFE,0xA4,0x0B,0xFF,0xFE,0xA4,0x0B,0xFF,0xFE,0xA4,
+	0x0B,0xFF,0xFE,0x94,0x0B,0xFF,0xFE,0x94,0x0B,0xFF,0xFE,0x94,0x0B,0xFF,0xFE,0x94,
+	0x0B,0xFF,0xFE,0x8C,0x0B,0xFF,0xFE,0x8C,0x05,0xFF,0xFD,0x0C,0x05,0xFF,0xFD,0x1C,
+	0x05,0xFF,0xFD,0x04,0x05,0xFF,0xFD,0x04,0x05,0xFF,0xFD,0x00,0x05,0xFF,0xFD,0x00,
+	0x05,0xFF,0xFD,0x00,0x05,0xFF,0xFD,0x00,0x05,0xFF,0xFD,0x00,0x05,0xFF,0xFD,0x00,
+	0x05,0xFF,0xFD,0x00,0x05,0xFF,0xFB,0x80,0x05,0xFF,0xF4,0x40,0x05,0xFF,0xE9,0x20,
+	0x04,0x00,0x0B,0xA0,0x07,0xFF,0xF9,0x20,0x03,0x80,0x04,0x40,0x03,0x80,0x03,0x80,
+	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00}		//100%
+};
+
+#endif
+
diff --git a/STM32_4路称重_Git提交精简工程/src/HARDWARE/LCD/lcd.c b/STM32_4路称重_Git提交精简工程/src/HARDWARE/LCD/lcd.c
new file mode 100755
index 0000000..e7ec060
--- /dev/null
+++ b/STM32_4路称重_Git提交精简工程/src/HARDWARE/LCD/lcd.c
@@ -0,0 +1,136 @@
+/*************************** (C) COPYRIGHT 2017 YNHB ****************************
+ * �ļ���  ��lcd.c
+ * ��  ��  ��LCD��ʾ���ӿ�Ӧ�ó���  
+ * ��  ��  ��V1.0
+ * ��  ��  ��XuZhongPing
+ * ��  ��  ��2017/10/23
+*********************************************************************************/
+#include "lcd.h"
+#include "lcd12864.h"
+#include "string.h"
+#include "stdlib.h" 
+#include "delay.h"
+
+/*
+***********************************************************************
+*	�� �� ��: LCD_SetBacklight
+*	����˵��: LCD��ʾ����ʼ��
+*	��    �Σ���
+*	�� �� ֵ: ��
+***********************************************************************
+*/
+void LCD_Init(void)
+{
+	LCD12864_Init();
+}
+
+/*
+***********************************************************************
+*	�� �� ��: LCD_SetBacklight
+*	����˵��: ����LCD��������
+*	��    �Σ�val -> ����ֵ���ٷֱȣ�
+*	�� �� ֵ: ��
+***********************************************************************
+*/
+void LCD_SetBacklight(uint8_t val)
+{
+	
+}
+
+/*
+***********************************************************************
+*	�� �� ��: LCD_Clear
+*	����˵��: ��ʾ����
+*	��    �Σ���
+*	�� �� ֵ: ��
+***********************************************************************
+*/
+void LCD_Clear(void)
+{
+	LCD12864_Clear();
+}
+
+/*
+***********************************************************************
+*	�� �� ��: LCD_DrawModeCtrl
+*	����˵��: ��ͼģʽ����
+*	��    �Σ�param -> 0���رջ�ͼģʽ��1���򿪻�ͼģʽ
+*	�� �� ֵ: ��
+***********************************************************************
+*/
+void LCD_DrawModeCtrl(uint8_t param)
+{
+	LCD12864_DrawModeCtrl(param);
+}
+
+/*
+***********************************************************************
+*	�� �� ��: LCD_ShowChar
+*	����˵��: ��ʾһ���ַ�
+*	��    �Σ�num -> Ҫ��ʾ���ַ�
+*	�� �� ֵ: ��
+***********************************************************************
+*/
+void LCD_ShowChar(uint8_t num)
+{
+	LCD12864_ShowChar(num);
+}
+
+/*
+***********************************************************************
+*	�� �� ��: LCD_ShowString
+*	����˵��: ��ʾ�ַ���
+*	��    �Σ�x -> ������
+*						y -> ������
+*						p -> Ҫ��ʾ������ָ��
+*	�� �� ֵ: ��
+***********************************************************************
+*/
+void LCD_ShowString(uint8_t x, uint8_t y, char *p)
+{
+	LCD12864_ShowString(x, y, p);
+}
+
+/*
+***********************************************************************
+*	�� �� ��: LCD_ShowNum
+*	����˵��: ��ʾ���ֱ���
+*	��    �Σ�
+*	�� �� ֵ: ��
+***********************************************************************
+*/
+void LCD_ShowNum(uint8_t num)
+{
+	LCD12864_ShowNum(num);
+}
+
+/*
+***********************************************************************
+*	�� �� ��: LCD_ShowxNum
+*	����˵��: ��ʾ����
+*	��    �Σ�x,y -> ��ʾ����
+*					  num -> Ҫ��ʾ������
+*           len -> ��ʾ�ĳ��ȣ���λ����
+*	�� �� ֵ: ��
+***********************************************************************
+*/
+void LCD_ShowxNum(uint8_t x, uint8_t y, uint32_t num, uint8_t len)
+{
+	LCD12864_ShowxNum(x, y, num, len);
+}
+
+/*
+***********************************************************************
+*	�� �� ��: LCD_ShowSignal
+*	����˵��: ��ʾGSM�ź�ǿ��
+*	��    �Σ�val -> �źŵ�ǿ�ȣ�0-4����ʾ��
+*	�� �� ֵ: ��
+***********************************************************************
+*/
+void LCD_ShowSignal(uint8_t val)
+{
+	LCD12864_ShowSignal(val);
+}
+
+
+/******************** (C) COPYRIGHT 2017 YNHB *****END OF FILE*******************/
diff --git a/STM32_4路称重_Git提交精简工程/src/HARDWARE/LCD/lcd.h b/STM32_4路称重_Git提交精简工程/src/HARDWARE/LCD/lcd.h
new file mode 100755
index 0000000..3d63c5f
--- /dev/null
+++ b/STM32_4路称重_Git提交精简工程/src/HARDWARE/LCD/lcd.h
@@ -0,0 +1,25 @@
+/*************************** (C) COPYRIGHT 2017 YNHB ****************************
+ * �ļ���  ��lcd.h
+ * ��  ��  ��LCD��ʾ���ӿ�Ӧ�ó���     
+ * ��  ��  ��V1.0
+ * ��  ��  ��XuZhongPing
+ * ��  ��  ��2017/10/23
+*********************************************************************************/
+#ifndef __LCD_H
+#define __LCD_H	 
+#include "stdint.h" 
+#include "string.h" 
+
+void LCD_Init(void);
+void LCD_SetBacklight(uint8_t val);
+void LCD_Clear(void);
+void LCD_DrawModeCtrl(uint8_t param);
+void LCD_ShowChar(uint8_t num);
+void LCD_ShowString(uint8_t x, uint8_t y, char *p);
+void LCD_ShowNum(uint8_t num);
+void LCD_ShowxNum(uint8_t x, uint8_t y, uint32_t num, uint8_t len);
+void LCD_ShowSignal(uint8_t val);
+		 				    
+#endif
+
+/******************** (C) COPYRIGHT 2017 YNHB *****END OF FILE*******************/
diff --git a/STM32_4路称重_Git提交精简工程/src/HARDWARE/LCD/lcd12864.c b/STM32_4路称重_Git提交精简工程/src/HARDWARE/LCD/lcd12864.c
new file mode 100755
index 0000000..5d3175e
--- /dev/null
+++ b/STM32_4路称重_Git提交精简工程/src/HARDWARE/LCD/lcd12864.c
@@ -0,0 +1,523 @@
+/*************************** (C) COPYRIGHT 2017 YNHB ****************************
+ * �ļ���  ��lcd12864.c
+ * ��  ��  ��lcd12864��ʾ��������     
+ * ��  ��  ��V1.0
+ * ��  ��  ��XuZhongPing
+ * ��  ��  ��2017/10/16 
+*********************************************************************************/
+#include "lcd12864.h"	
+#include "delay.h"	
+#include "icon.h" 
+
+#define LCD12864_E_PORT_PeriphClock			RCC_APB2Periph_GPIOB
+#define LCD12864_E_PORT									GPIOB			
+#define LCD12864_E_PORT_PIN							GPIO_Pin_5
+
+#define LCD12864_RW_PORT_PeriphClock		RCC_APB2Periph_GPIOB
+#define LCD12864_RW_PORT								GPIOB			
+#define LCD12864_RW_PORT_PIN						GPIO_Pin_6
+
+#define LCD12864_RS_PORT_PeriphClock		RCC_APB2Periph_GPIOB
+#define LCD12864_RS_PORT								GPIOB			
+#define LCD12864_RS_PORT_PIN						GPIO_Pin_7
+/*
+***********************************************************************
+*	�� �� ��: LCD12864_Init
+*	����˵��: LCD12864�ӳ�ʼ��
+*	��    �Σ���
+*	�� �� ֵ: ��
+***********************************************************************
+*/
+void LCD12864_Init(void)
+{
+ 	GPIO_InitTypeDef  GPIO_InitStructure;
+ 	
+ 	RCC_APB2PeriphClockCmd(LCD12864_E_PORT_PeriphClock, ENABLE);
+	RCC_APB2PeriphClockCmd(LCD12864_RW_PORT_PeriphClock, ENABLE);
+	RCC_APB2PeriphClockCmd(LCD12864_RS_PORT_PeriphClock, ENABLE);
+	
+	//E(CLK),���
+	GPIO_InitStructure.GPIO_Pin = LCD12864_E_PORT_PIN;													
+ 	GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP;
+ 	GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
+ 	GPIO_Init(LCD12864_E_PORT, &GPIO_InitStructure);
+	
+	//R/W(SID),����
+	GPIO_InitStructure.GPIO_Pin = LCD12864_RW_PORT_PIN;													
+ 	GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP;
+ 	GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
+ 	GPIO_Init(LCD12864_RW_PORT, &GPIO_InitStructure);
+	
+	//RS/CS,Ƭѡ	
+	GPIO_InitStructure.GPIO_Pin = LCD12864_RS_PORT_PIN;													
+ 	GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP;
+ 	GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
+ 	GPIO_Init(LCD12864_RS_PORT, &GPIO_InitStructure);
+	
+	
+
+/*--------------------LCD����ָ��-----------------------*/
+	delay_ms(2);
+	LCD12864_WriteCommand(0x30);  								//30--����ָ���
+	delay_ms(5);
+	LCD12864_WriteCommand(0x0c);  								//������ƻ��治��
+	delay_ms(5);
+	LCD12864_WriteCommand(0x01);  								//����
+	delay_ms(5);              										//����ʱ��ϳ�
+	LCD12864_WriteCommand(0x06);  								//��ʾ�򿪣���꿪�����׹�
+	delay_ms(5);
+
+//	LCD12864_WriteCommand(0x34);								// ����ָ��
+//	LCD12864_WriteCommand(0x36);								// �򿪻�ͼָ��
+	LCD12864_Clear();															// ����
+}
+
+/*
+***********************************************************************
+*	�� �� ��: LCD12864_SendByte
+*	����˵��: дһ�ֽ����ݵ�LCD
+*	��    �Σ�zdata -> Ҫд������
+*	�� �� ֵ: ��
+***********************************************************************
+*/
+void LCD12864_SendByte(uint8_t zdata)
+{
+  uint16_t i;
+  for(i=0; i<8; i++)
+	{
+	  if((zdata << i) & 0x80)
+		{
+			SID_H;
+		}else{   
+			SID_L;
+		}
+		
+		SCLK_H;
+		SCLK_L;
+	}
+}
+
+/*
+***********************************************************************
+*	�� �� ��: LCD12864_ReceiveByte
+*	����˵��: ��LCD����
+*	��    �Σ���
+*	�� �� ֵ: ��
+***********************************************************************
+*/
+uint8_t LCD12864_ReceiveByte(void)
+{
+	uint8_t i, temp1, temp2, value;
+// 	temp1 = 0;
+// 	temp2 = 0;
+// 	for(i = 0; i < 8; i++)
+// 	{
+// 		temp1 = temp1<<1;
+// 		SCLK_L;
+// 		SCLK_H;
+// 		SCLK_L;
+// 		if(PAout(7) == 1)
+// 		{
+// 			temp1++;
+// 		}
+// 	}
+// 	for(i = 0; i < 8; i++)
+// 	{
+// 		temp2 = temp2<<1;
+// 		SCLK_L;
+// 		SCLK_H;
+// 		SCLK_L;
+// 		if(PAout(7) == 1)
+// 		{
+// 			temp2++;
+// 		}
+// 	}
+// 	temp1 = 0xf0&temp1;
+// 	temp2 = 0x0f&temp2;
+// 	value = temp1+temp2;
+	return value;
+}
+
+/*
+***********************************************************************
+*	�� �� ��: LCD12864_CheckBusy
+*	����˵��: LCDæ���
+*	��    �Σ���
+*	�� �� ֵ: ��
+***********************************************************************
+*/
+void LCD12864_CheckBusy(void)
+{
+	do{
+		LCD12864_SendByte(0xfc);		  					//11111,RW(1),RS(0),0
+	}while(0x80 & LCD12864_ReceiveByte());
+}
+
+/*
+***********************************************************************
+*	�� �� ��: LCD12864_WriteCommand
+*	����˵��: д���LCD
+*	��    �Σ�cmdcode -> ��д�����������
+*	�� �� ֵ: ��
+***********************************************************************
+*/
+void LCD12864_WriteCommand(uint8_t cmdcode)
+{ 
+	CS_H;
+	LCD12864_CheckBusy();
+	LCD12864_SendByte(0xf8);
+	LCD12864_SendByte(cmdcode & 0xf0);
+	LCD12864_SendByte((cmdcode << 4) & 0xf0);
+	delay_us(100);
+	CS_L;
+}
+
+/*
+***********************************************************************
+*	�� �� ��: LCD12864_WriteData
+*	����˵��: д��ʾ���ݵ�LCD
+*	��    �Σ�dispdata -> ��д�����������
+*	�� �� ֵ: ��
+***********************************************************************
+*/
+void LCD12864_WriteData(uint8_t dispdata)
+{  
+  CS_H;
+  LCD12864_CheckBusy();
+  LCD12864_SendByte(0xfa);	  							//11111,RW(0),RS(1),0
+  LCD12864_SendByte(dispdata & 0xf0);
+  LCD12864_SendByte((dispdata << 4) & 0xf0);
+  delay_us(100);
+  CS_L;
+}
+
+/*
+***********************************************************************
+*	�� �� ��: LCD12864_ReadData
+*	����˵��: ��ȡLCD��ʾ����
+*	��    �Σ���
+*	�� �� ֵ: LCD�յ�������
+***********************************************************************
+*/
+uint8_t LCD12864_ReadData(void)
+{
+	LCD12864_CheckBusy();
+	LCD12864_SendByte(0xfe);    					//11111��RW(1),RS(1),0 LCD->MCU
+	return  LCD12864_ReceiveByte();
+}
+
+/*
+***********************************************************************
+*	�� �� ��: LCD12864_SetPos
+*	����˵��: ������ʾλ��
+*	��    �Σ�x,y��ʾ����
+*	�� �� ֵ: ��
+***********************************************************************
+*/
+void LCD12864_SetPos(uint8_t x, uint8_t y) 
+{
+	uint8_t pos;
+	switch(x)
+	{
+		case 0: x=0x80;break;
+		case 1: x=0x90;break;
+		case 2: x=0x88;break;
+		case 3: x=0x98;break;
+	}
+	pos = x + y;
+	LCD12864_WriteCommand(pos);
+}
+
+/*
+***********************************************************************
+*	�� �� ��: LCD12864_DrawPoint
+*	����˵��: LCD����
+*	��    ��: x,y->����
+*						color -> ��ɫ��0����ʾ��1��ʾ
+*	�� �� ֵ: ��
+***********************************************************************
+*/
+void LCD12864_DrawPoint(uint16_t x, uint16_t y, uint8_t color)
+{
+
+}
+
+/*
+***********************************************************************
+*	�� �� ��: LCD12864_DrawLine
+*	����˵��: ��ֱ��
+*	��    ��: x1,y1->�������
+*			  x2,y2->�յ�����
+*	�� �� ֵ: ��
+***********************************************************************
+*/
+void LCD12864_DrawLine(uint16_t x1, uint16_t y1, uint16_t x2, uint16_t y2)
+{
+	
+}
+
+/*
+***********************************************************************
+*	�� �� ��: LCD12864_DrawRectangle
+*	����˵��: ������
+*	��    ��: x1,y1->���Ͻ�����
+*			  	  x2,y2->���½�����
+*	�� �� ֵ: ��
+***********************************************************************
+*/
+void LCD12864_DrawRectangle(uint16_t x1,uint16_t y1,uint16_t x2,uint16_t y2)
+{
+
+}
+
+/*
+***********************************************************************
+*	�� �� ��: LCD12864_Clear
+*	����˵��: ��ʾ����
+*	��    �Σ���
+*	�� �� ֵ: ��
+***********************************************************************
+*/
+void LCD12864_Clear(void)
+{
+	uint8_t i, j;
+	LCD12864_WriteCommand(0x34);      		//8Bit����ָ�,��ʹ��36HҲҪд����
+	LCD12864_WriteCommand(0x36);      		//��ͼON,����ָ�����36H���ܿ���ͼ
+	for(i = 0; i < 32; i++)            		//12864ʵ��Ϊ256x32
+	{
+		LCD12864_WriteCommand(0x80|i);      //��λ��
+		LCD12864_WriteCommand(0x80);      	//��λ��
+		for(j = 0; j < 32; j++)            	//256/8=32 byte
+		{
+			LCD12864_WriteData(0x00);
+		}
+	}
+	LCD12864_WriteCommand(0x36);
+	LCD12864_WriteCommand(0x30);
+}
+
+/*
+***********************************************************************
+*	�� �� ��: LCD12864_DrawModeCtrl
+*	����˵��: ��ͼģʽ����
+*	��    �Σ�param -> 0���رջ�ͼģʽ��1���򿪻�ͼģʽ
+*	�� �� ֵ: ��
+***********************************************************************
+*/
+void LCD12864_DrawModeCtrl(uint8_t param)
+{
+	if(param == 1)
+	{
+		LCD12864_WriteCommand(0x36);
+		LCD12864_WriteCommand(0x30);
+	}else{
+		LCD12864_WriteCommand(0x34);
+		LCD12864_WriteCommand(0x30);
+	}
+}
+
+/*
+***********************************************************************
+*	�� �� ��: LCD12864_ShowChar
+*	����˵��: ��ʾһ���ַ�
+*	��    �Σ�num -> Ҫ��ʾ���ַ�
+*	�� �� ֵ: ��
+***********************************************************************
+*/
+void LCD12864_ShowChar(uint8_t num)
+{
+	LCD12864_WriteData(num);
+	delay_us(50);
+}
+
+/*
+***********************************************************************
+*	�� �� ��: LCD12864_ShowString
+*	����˵��: ��ʾ�ַ���
+*	��    �Σ�x -> �����꣨0��Ӧ��һ�У�
+*						y -> �����꣨0��Ӧ��ʾ��һ���ֵ�λ�ã��������ʾ8�����֣�
+*						p -> Ҫ��ʾ������ָ��
+*	�� �� ֵ: ��
+***********************************************************************
+*/
+void LCD12864_ShowString(uint8_t x, uint8_t y, char *p)
+{
+	uint8_t addr;
+	switch(x)
+	{
+		case 0: 
+			addr = 0x80;
+			break;
+		case 1: 
+			addr = 0x90;
+			break;
+		case 2: 
+			addr = 0x88;
+			break;
+		case 3: 
+			addr = 0x98;
+			break;
+	}
+	LCD12864_WriteCommand(addr + y);
+	
+	while(*p>0)
+	{  
+		LCD12864_WriteData(*p);
+		p++;
+		delay_us(50);
+	}
+}
+
+
+
+static uint64_t LCD_Pow(uint8_t m, uint8_t n)
+{
+	uint64_t result = 1;	 
+	while(n--)result *= m;    
+	return result;
+}	
+
+const uint8_t numCode[11] = {"0123456789"};
+/*
+***********************************************************************
+*	�� �� ��: LCD12864_ShowNum
+*	����˵��: ��ʾ��������
+*	��    �Σ�num -> Ҫ��ʾ������
+*	�� �� ֵ: ��
+***********************************************************************
+*/
+void LCD12864_ShowNum(uint8_t num)
+{	
+	LCD12864_WriteData(numCode[num]);
+	delay_us(50);
+}
+
+/*
+***********************************************************************
+*	�� �� ��: LCD12864_ShowxNum
+*	����˵��: ��ʾ����
+*	��    �Σ�x,y -> ��ʾ����
+*					  num -> Ҫ��ʾ������
+*           len -> ��ʾ�ĳ��ȣ���λ����
+*	�� �� ֵ: ��
+***********************************************************************
+*/
+void LCD12864_ShowxNum(uint8_t x, uint8_t y, uint32_t num, uint8_t len)
+{
+	uint8_t t, temp;		
+	
+	LCD12864_SetPos(x, y);														//������ʾ����
+	for(t = 0; t < len; t++)
+	{
+		temp = (num/LCD_Pow(10, len-t-1))%10;
+		LCD12864_ShowNum(temp);
+	}
+}
+
+/*
+***********************************************************************
+*	�� �� ��: LCD12864_ShowSignal
+*	����˵��: ��ʾGSM�ź�ǿ��
+*	��    �Σ�val -> �źŵ�ǿ�ȣ�0-4����ʾ��5-6Ϊ�쳣�����ʾ��
+*	�� �� ֵ: ��
+***********************************************************************
+*/
+void LCD12864_ShowSignal(uint8_t val)
+{
+	uint8_t i=0, j=0;
+	LCD12864_WriteCommand(0x34);      //8Bit����ָ�,��ʹ��36HҲҪд����
+	LCD12864_WriteCommand(0x36);      //��ͼON,����ָ�����36H���ܿ���ͼ
+
+	for(i = 0; i < 16; i++)
+	{
+		LCD12864_WriteCommand(0x83 + i);    	//��λ�ã�˵�������Ǵӵ�һ�п�ʼ��ʾ��
+		LCD12864_WriteCommand(0x80);      		//��λ��
+		
+		LCD12864_WriteData((uint8_t)signalIcon[val][j++]);
+		LCD12864_WriteData((uint8_t)signalIcon[val][j++]);			
+	}
+	LCD12864_WriteCommand(0x36);
+	LCD12864_WriteCommand(0x30);
+}
+
+
+void LCD_ShowTrash(uint8_t num, uint8_t val)
+{
+	uint8_t i;
+	uint16_t addr = 0;
+	LCD12864_WriteCommand(0x34);      //8Bit����ָ�,��ʹ��36HҲҪд����
+	LCD12864_WriteCommand(0x36);      //��ͼON,����ָ�����36H���ܿ���ͼ
+
+	for(i = 0; i < 16; i++)
+	{
+		LCD12864_WriteCommand(0x90 | i);    	//��λ��
+		if(num == 1)
+		{
+			LCD12864_WriteCommand(0x92);      		//��λ��
+		}else{
+			LCD12864_WriteCommand(0x96);      		//��λ��
+		}
+		LCD12864_WriteData((uint8_t)Icon2[val][addr++]);
+		LCD12864_WriteData((uint8_t)Icon2[val][addr++]);	
+		LCD12864_WriteData((uint8_t)Icon2[val][addr++]);	
+		LCD12864_WriteData((uint8_t)Icon2[val][addr++]);	
+	}
+	
+	for(i = 0; i < 16; i++)
+	{
+		LCD12864_WriteCommand(0x80 | i);    	//��λ��
+		if(num == 1)
+		{
+			LCD12864_WriteCommand(0x8A);      		//��λ��
+		}else{
+			LCD12864_WriteCommand(0x8E);      		//��λ��
+		}
+		LCD12864_WriteData((uint8_t)Icon2[val][addr++]);
+		LCD12864_WriteData((uint8_t)Icon2[val][addr++]);	
+		LCD12864_WriteData((uint8_t)Icon2[val][addr++]);	
+		LCD12864_WriteData((uint8_t)Icon2[val][addr++]);	
+	}
+	
+	for(i = 0; i < 16; i++)
+	{
+		LCD12864_WriteCommand(0x90 | i);    	//��λ��
+		if(num == 1)
+		{
+			LCD12864_WriteCommand(0x9A);      		//��λ��
+		}else{
+			LCD12864_WriteCommand(0x9E);      		//��λ��
+		}
+		LCD12864_WriteData((uint8_t)Icon2[val][addr++]);
+		LCD12864_WriteData((uint8_t)Icon2[val][addr++]);	
+		LCD12864_WriteData((uint8_t)Icon2[val][addr++]);	
+		LCD12864_WriteData((uint8_t)Icon2[val][addr++]);	
+	}
+	
+	LCD12864_WriteCommand(0x36);
+	LCD12864_WriteCommand(0x30);
+}
+
+void LCD_ShowTemperatureSymbol(uint8_t num)
+{
+	uint8_t i;
+	uint16_t addr = 0;
+	LCD12864_WriteCommand(0x34);      //8Bit����ָ�,��ʹ��36HҲҪд����
+	LCD12864_WriteCommand(0x36);      //��ͼON,����ָ�����36H���ܿ���ͼ
+
+	for(i = 0; i < 16; i++)
+	{
+		LCD12864_WriteCommand(0x90 | i);    	//��λ��
+		if(num == 1)
+		{
+			LCD12864_WriteCommand(0x91);      		//��λ��
+		}else{
+			LCD12864_WriteCommand(0x95);      		//��λ��
+		}
+		LCD12864_WriteData((uint8_t)temperatureIcon[addr++]);
+		LCD12864_WriteData((uint8_t)temperatureIcon[addr++]);	
+	}
+	LCD12864_WriteCommand(0x36);
+	LCD12864_WriteCommand(0x30);
+}
+
+/******************** (C) COPYRIGHT 2017 YNHB *****END OF FILE*******************/ 
diff --git a/STM32_4路称重_Git提交精简工程/src/HARDWARE/LCD/lcd12864.h b/STM32_4路称重_Git提交精简工程/src/HARDWARE/LCD/lcd12864.h
new file mode 100755
index 0000000..a530cb2
--- /dev/null
+++ b/STM32_4路称重_Git提交精简工程/src/HARDWARE/LCD/lcd12864.h
@@ -0,0 +1,43 @@
+/*************************** (C) COPYRIGHT 2017 YNHB ****************************
+ * �ļ���  ��lcd12864.h
+ * ��  ��  ��lcd12864��ʾ��������     
+ * ��  ��  ��V1.0
+ * ��  ��  ��XuZhongPing
+ * ��  ��  ��2017/10/16 
+*********************************************************************************/
+#ifndef __LCD12864_H
+#define __LCD12864_H	
+#include "stm32f10x.h"
+#include "stdio.h"
+
+#define CS_H		GPIO_SetBits(GPIOB, GPIO_Pin_7)				//RS(CS)
+#define CS_L 		GPIO_ResetBits(GPIOB, GPIO_Pin_7)
+#define SID_H 	GPIO_SetBits(GPIOB, GPIO_Pin_6)				//R/W(SID)
+#define SID_L 	GPIO_ResetBits(GPIOB, GPIO_Pin_6)
+#define SCLK_H 	GPIO_SetBits(GPIOB, GPIO_Pin_5)  			//E(SCLK)
+#define SCLK_L 	GPIO_ResetBits(GPIOB, GPIO_Pin_5)
+// #define PSB_L 	GPIO_ResetBits(GPIOD, GPIO_Pin_4)			//PSB
+
+void LCD12864_Init(void);
+void LCD12864_SendByte(uint8_t zdata);
+uint8_t LCD12864_ReceiveByte(void);
+void LCD12864_CheckBusy(void);
+void LCD12864_WriteCommand(uint8_t cmdcode);
+void LCD12864_WriteData(uint8_t dispdata);
+uint8_t LCD12864_ReadData(void);
+void LCD12864_SetPos(uint8_t x, uint8_t y);
+void LCD12864_DrawPoint(uint16_t x, uint16_t y, uint8_t color);
+void LCD12864_DrawLine(uint16_t x1, uint16_t y1, uint16_t x2, uint16_t y2);
+void LCD12864_DrawRectangle(uint16_t x1,uint16_t y1,uint16_t x2,uint16_t y2);
+void LCD12864_Clear(void);
+void LCD12864_DrawModeCtrl(uint8_t param);
+
+void LCD12864_ShowChar(uint8_t num);
+void LCD12864_ShowString(uint8_t x, uint8_t y, char *p);
+void LCD12864_ShowNum(uint8_t num);
+void LCD12864_ShowxNum(uint8_t x, uint8_t y, uint32_t num, uint8_t len);
+void LCD12864_ShowSignal(uint8_t val);
+
+#endif
+
+/******************** (C) COPYRIGHT 2017 YNHB *****END OF FILE*******************/ 
diff --git a/STM32_4路称重_Git提交精简工程/src/HARDWARE/LED/led.c b/STM32_4路称重_Git提交精简工程/src/HARDWARE/LED/led.c
new file mode 100755
index 0000000..417bd17
--- /dev/null
+++ b/STM32_4路称重_Git提交精简工程/src/HARDWARE/LED/led.c
@@ -0,0 +1,137 @@
+/*************************** (C) COPYRIGHT 2017 YNHB ****************************
+ * �ļ���  ��led.c
+ * ��  ��  ��LED��������	     
+ * ��  ��  ��V1.0
+ * ��  ��  ��XuZhongPing
+ * ��  ��  ��2017/09/02
+*********************************************************************************/
+#include "led.h"
+#include "timer.h"
+
+#define SYS_RUNNING_LED_PeriphClock			RCC_APB2Periph_GPIOB | RCC_APB2Periph_AFIO
+#define SYS_RUNNING_LED_PORT						GPIOB			
+#define SYS_RUNNING_LED_PORT_PIN				GPIO_Pin_4
+
+uint8_t ledON_OFF_Status = 0;
+uint8_t fillLightMask = 0;
+
+/*
+***********************************************************************
+*	�� �� ��: LED_Init
+*	����˵��: ��ʼ��LED�ƽӿ�
+*	��    ��:	��
+*	�� �� ֵ: ��
+***********************************************************************
+*/
+void LED_Init(void)
+{
+ 	GPIO_InitTypeDef  GPIO_InitStructure;
+ 	
+ 	RCC_APB2PeriphClockCmd(SYS_RUNNING_LED_PeriphClock, ENABLE);	 						
+	
+	GPIO_PinRemapConfig(GPIO_Remap_SWJ_JTAGDisable , ENABLE);
+	
+	GPIO_InitStructure.GPIO_Pin = SYS_RUNNING_LED_PORT_PIN;													
+ 	GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP; 
+ 	GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
+ 	GPIO_Init(SYS_RUNNING_LED_PORT, &GPIO_InitStructure);
+	
+ 	GPIO_SetBits(SYS_RUNNING_LED_PORT, SYS_RUNNING_LED_PORT_PIN);
+}
+
+/*
+***********************************************************************
+*	�� �� ��: SetLedOn
+*	����˵��: ����LED��
+*	��    ��:	��
+*	�� �� ֵ: ��
+***********************************************************************
+*/
+void SetLedOn(void)
+{
+	GPIO_ResetBits(SYS_RUNNING_LED_PORT, SYS_RUNNING_LED_PORT_PIN);
+	ledON_OFF_Status = 1;
+}
+
+/*
+***********************************************************************
+*	�� �� ��: SetLedOff
+*	����˵��: Ϩ��LED��
+*	��    ��:	��
+*	�� �� ֵ: ��
+***********************************************************************
+*/
+void SetLedOff(void)
+{
+	GPIO_SetBits(SYS_RUNNING_LED_PORT, SYS_RUNNING_LED_PORT_PIN);
+	ledON_OFF_Status = 0;
+}
+
+/*
+***********************************************************************
+*	�� �� ��: SetLedToggle
+*	����˵��: LED�Ʒ�ת
+*	��    ��:	��
+*	�� �� ֵ: ��
+***********************************************************************
+*/
+void SetLedToggle(void)
+{
+	if(ledON_OFF_Status)
+	{
+		SetLedOff();
+	}else{
+		SetLedOn();
+	}
+}
+
+/*
+***********************************************************************
+*	�� �� ��: LED_Task
+*	����˵��: LED������״ָ̬ʾ��
+*	��    ��:	��
+*	�� �� ֵ: ��
+***********************************************************************
+*/
+void LED_Task(void)
+{
+  static uint8_t ledStatus = 0;
+  
+  static timer ledOnTimer;	
+  static timer ledOffTimer;	
+	static uint8_t timer_ok = 0;
+	
+	if(timer_ok == 0)
+	{
+		timer_ok = 1;
+		timer_set(&ledOnTimer, 1);												
+    timer_set(&ledOffTimer, 19);	
+	}
+  
+  switch(ledStatus)
+  {
+    case 0x00:
+      SetLedOff();
+      if(timer_expired(&ledOffTimer))
+      {
+        timer_restart(&ledOnTimer);
+        ledStatus = 0x01;
+      }
+      break;
+      
+    case 0x01:
+      SetLedOn();
+      if(timer_expired(&ledOnTimer))
+      {
+        timer_restart(&ledOffTimer);
+        ledStatus = 0x00;
+      }
+      break;
+      
+    default:
+      ledStatus = 0x00;
+      break;
+  }
+}
+
+/******************** (C) COPYRIGHT 2017 YNHB *****END OF FILE*******************/
diff --git a/STM32_4路称重_Git提交精简工程/src/HARDWARE/LED/led.h b/STM32_4路称重_Git提交精简工程/src/HARDWARE/LED/led.h
new file mode 100755
index 0000000..82456e9
--- /dev/null
+++ b/STM32_4路称重_Git提交精简工程/src/HARDWARE/LED/led.h
@@ -0,0 +1,24 @@
+/*************************** (C) COPYRIGHT 2017 YNHB ****************************
+ * �ļ���  ��led.h
+ * ��  ��  ��LED��������	     
+ * ��  ��  ��V1.0
+ * ��  ��  ��XuZhongPing
+ * ��  ��  ��2017/09/02
+*********************************************************************************/
+#ifndef __LED_H
+#define __LED_H	
+
+#include "stm32f10x.h"
+
+extern uint8_t fillLightMask;
+
+void LED_Init(void);										//��ʼ��
+void SetLedOn(void);
+void SetLedOff(void);
+
+void SetLedToggle(void);
+void LED_Task(void);
+		 				    
+#endif
+
+/******************** (C) COPYRIGHT 2017 YNHB *****END OF FILE*******************/
diff --git a/STM32_4路称重_Git提交精简工程/src/HARDWARE/MOTOR/door_ctrl.c b/STM32_4路称重_Git提交精简工程/src/HARDWARE/MOTOR/door_ctrl.c
new file mode 100755
index 0000000..4ae6b02
--- /dev/null
+++ b/STM32_4路称重_Git提交精简工程/src/HARDWARE/MOTOR/door_ctrl.c
@@ -0,0 +1,1469 @@
+/*************************** (C) COPYRIGHT 2017 CXHY ****************************
+ * �ļ���  ��motor.c
+ * ��  ��  ��������Ƴ���
+ * ��  ��  ��V1.0
+ * ��  ��  ��XuZhongPing
+ * ��  ��  ��2017/03/06 
+*********************************************************************************/
+#include "door_ctrl.h"
+#include "motor.h"
+#include "ElectronicLock.h"
+#include "key.h"
+#include "timer.h"
+#include "data_typedef.h"	
+
+uint8_t doorResetMark = 0;								//�Ÿ�λ״̬
+
+/*
+***********************************************************************
+*	�� �� ��: MotorControlTask_1
+*	����˵��: ���1��������
+*	��    �Σ���
+*	�� �� ֵ: ��
+***********************************************************************
+*/
+void MotorControlTask_1(void)
+{
+	uint8_t tempLimKeyVal = 0;
+	static uint8_t controlSteps = 0;
+	uint8_t motorStopMark = 0;											//���ֹͣ��־
+	uint16_t tempWeight = 0;
+	
+	static uint32_t startTimer = 0;									//�����ſ�ʼʱ��
+	static uint32_t endTimer = 0;										//�����Ž���ʱ��
+	
+	static uint32_t preRemainingTimer = 0;					//��һ�λ�ʣʱ��
+	
+	static timer waitingTimer_100ms;								//�ȴ�100ms��ʱ��
+	static timer waitingTimer_300ms;								//�ȴ�300ms��ʱ��
+	static timer waitingTimer_500ms;								//�ȴ�500ms��ʱ��
+	static timer waitingTimer_1S;										//�ȴ�1S��ʱ��
+	static timer waitingUnlockingTimer;							//���������ʱ��
+	static timer unlockingTimer;										//���������ʱ��
+	static timer openDoorTimer;											//���ڿ���ʱ������
+	static timer closeDoorTimer;										//���ڹ���ʱ������
+	static timer waitingTimer_300S;									//5���Ӻ��Զ�����
+	
+	static uint8_t timer_ok = 0;
+	
+	if(timer_ok == 0)
+	{
+		timer_ok = 1;
+		
+		timer_set(&waitingTimer_100ms, 1);
+		timer_set(&waitingTimer_300ms, 3);
+		timer_set(&waitingTimer_500ms, 5);
+		timer_set(&waitingTimer_1S, CLOCK_SECOND*1);
+		timer_set(&waitingUnlockingTimer, 2);							//����1����ʱ�������ڿ����ȴ򿪵����Ȼ���ٿ���
+		timer_set(&unlockingTimer, 25);											//����1����ʱ�������ڿ��Ƶ������ʱ��
+		timer_set(&openDoorTimer, 16);											//����1����ʱ�������ڿ���ʱ������
+		timer_set(&closeDoorTimer, 20);											//����1����ʱ�������ڹ���ʱ������
+		timer_set(&waitingTimer_300S, CLOCK_SECOND*300);		//����1����ʱ��������5���Ӻ��Զ�����
+	}
+
+	switch(controlSteps)
+	{
+		case 0x00:			//��ʼ״̬
+			if(isOpenDoor_1 == 1)		//���1�����
+			{
+				printf("\r\n--> ���1��!\r\n");	
+				
+				//��ʼʱ������õ��ı���
+				isOpenDoor_1 = 0;				
+				isCloseDoorMark_1 = 0;
+				openDoorCtrlEndMark_1 = 0;
+				
+				faultCode_1 = 0x14;
+				
+				controlSteps = 0x01;											//�п��������������ת������Ͷ�Ų�������
+			}
+			break;
+			
+		case 0x01:		//�򿪵����
+// 			Unlock(1);										//�򿪵����
+			
+			timer_restart(&waitingUnlockingTimer);
+			timer_restart(&unlockingTimer);
+			controlSteps = 0x02;
+			break;
+			
+		case 0x02:		//�ȴ��������
+			if(timer_expired(&waitingUnlockingTimer))
+			{
+				controlSteps = 0x03;
+			}
+			break;
+			
+		case 0x03:		//����
+			printf("\r\n��1��\r\n");
+			DoorOpen(1);
+			
+			controlSteps = 0x04;
+			printf("\r\n������λ���1\r\n");
+			timer_restart(&openDoorTimer);							//�ӵ�ǰʱ�����¿�ʼn�붨ʱ��
+			break;
+			
+		case 0x04:			//������λ���
+			if(timer_expired(&unlockingTimer))					//���������ʱ�䵽������
+			{
+// 				Locked(1);
+			}
+			
+			if(timer_expired(&openDoorTimer))						//�����ʱʱ�䵽�ˣ�����ֹͣ
+			{
+				DoorStop(1);															//��ֹͣ
+// 				Locked(1);
+	
+				printf("\r\n��λ��ʱֹͣ1\r\n");
+				printf("\r\n�ȴ�Ͷ��1\r\n");
+				timer_restart(&waitingTimer_300S);				//�ӵ�ǰʱ�����¿�ʼn�붨ʱ��
+				controlSteps = 0x05;
+				break;
+			}
+			
+			if(motorRunningStatus_1 == 0)								//����Ѿ�ֹͣ��
+			{
+// 				Locked(1);
+				printf("\r\n�ȴ�Ͷ��1\r\n");
+				
+				timer_restart(&waitingTimer_300S);				//�ӵ�ǰʱ�����¿�ʼn�붨ʱ��
+				controlSteps = 0x05;
+				break;
+			}
+			
+			break;
+			
+		case 0x05:		//�ȴ������ź�
+			if(isCloseDoorMark_1 == 1)
+			{
+				isCloseDoorMark_1 = 0;
+				controlSteps = 0x06;										//ת������
+				break;
+			}
+			
+			if(timer_expired(&waitingTimer_300S))			//���5���Ӷ�ʱʱ�䵽�ˣ�����ֹͣ
+			{
+				printf("\r\n5���ӳ�ʱ�Զ�����1\r\n");
+				controlSteps = 0x06;										//ת������
+				break;
+			}
+			break;
+			
+		case 0x06:			//����		
+			printf("\r\n��1�ر���\r\n");
+			DoorClose(1);																//����
+			
+// 			printf("\r\n������λ���1\r\n");
+			timer_restart(&closeDoorTimer);							//�ӵ�ǰʱ�����¿�ʼn�붨ʱ��
+			controlSteps = 0x07;
+			break;
+			
+		case 0x07:			//����
+			if(timer_expired(&closeDoorTimer))					//�����ʱʱ�䵽�ˣ������ֹͣ
+			{
+				DoorStop(1);															//��ֹͣ
+
+// 				printf("\r\n����ʱ�䵽ֹͣ1\r\n");				
+				controlSteps = 0x08;
+				break;
+			}
+			
+			//��λ���ؼ��
+			if(LIMI_KEY1 == 0)
+			{				
+				DoorStop(1);																//��ֹͣ	
+			}
+			
+			if(motorRunningStatus_1 == 0)											//����Ѿ�ֹͣ��
+			{
+				DoorStop(1);
+// 				printf("\r\nM1->Stop\r\n");
+				controlSteps = 0x08;											//ת���ȴ���������
+				break;
+			}
+			break;
+			
+		case 0x08:		//������λ���ع��ϼ��
+			if(LIMI_KEY1 != 0)					//��λ���ؼ��
+			{
+				faultCode_1 = 0x32;
+				limitKeyExceptionMark = 0x20;
+				devChannel1FaultMark = 1;
+				printf("\r\nͶ��1��λ�������쳣��\r\n");
+			}else{
+				faultCode_1 = 0x14;
+			}
+			
+			controlSteps = 0x09;
+			
+//			if(LIMI_KEY1 != 0)					//��λ���ؼ��
+//			{
+//				controlSteps = 0x30;
+//			}else{
+//				controlSteps = 0x09;
+//			}
+			break;
+			
+		case 0x09:		//�����ſ��ƽ���
+			isOpenDoor_1 = 0;
+			isCloseDoorMark_1 = 0;
+			
+			openDoorCtrlEndMark_1 = 1;					//��־�����ſ��ƽ���
+			printf("\r\nNo.1 OK��\r\n");
+			controlSteps = 0x00;
+			break;
+	
+//-------------------------------------------------------------------------------------
+//�����쳣����		
+		case 0x30:
+			printf("\r\nE->����1\r\n");
+// 			Unlock(1);															//�򿪵����
+			timer_restart(&waitingUnlockingTimer);
+			controlSteps = 0x31;
+			break;
+			
+		case 0x31:
+			if(timer_expired(&waitingUnlockingTimer))
+			{
+				printf("\r\nE->����1\r\n");
+				DoorOpen(1);
+				
+				controlSteps = 0x32;
+				timer_restart(&waitingTimer_100ms);
+			}
+			break;
+			
+		case 0x32:
+			if(timer_expired(&waitingTimer_100ms))
+			{
+				printf("\r\nE->��������1ֹͣ\r\n");
+// 				Locked(1);
+				DoorStop(1);															//��ֹͣ
+				controlSteps = 0x33;
+				printf("\r\nE->��1��λ\r\n");
+			}
+			break;
+			
+		case 0x33:
+			if(DoorReset_1() == 1)
+			{
+				controlSteps = 0x34;
+			}
+			break;
+			
+		case 0x34:
+			if(LIMI_KEY1 != 0)
+			{
+				faultCode_1 = 0x32;
+				limitKeyExceptionMark = 0x20;
+				devChannel1FaultMark = 1;
+				controlSteps = 0x09;
+				break;
+			}else{																				//�Ѿ��ָ���ص������Ĵ�������
+				faultCode_1 = 0x14;
+				timer_restart(&waitingTimer_100ms);
+				controlSteps = 0x09;
+			}
+			break;
+			
+		default:
+			controlSteps = 0x00;
+			break;
+	}
+}
+
+/*
+***********************************************************************
+*	�� �� ��: MotorControlTask_1
+*	����˵��: ���1��������
+*	��    �Σ���
+*	�� �� ֵ: ��
+***********************************************************************
+*/
+void MotorControlTask_2(void)
+{
+	uint8_t tempLimKeyVal = 0;
+	static uint8_t controlSteps = 0;
+	uint8_t motorStopMark = 0;											//���ֹͣ��־
+	uint16_t tempWeight = 0;
+	
+	static uint32_t startTimer = 0;									//�����ſ�ʼʱ��
+	static uint32_t endTimer = 0;										//�����Ž���ʱ��
+	
+	static uint32_t preRemainingTimer = 0;					//��һ�λ�ʣʱ��
+	
+	static timer waitingTimer_100ms;								//�ȴ�100ms��ʱ��
+	static timer waitingTimer_300ms;								//�ȴ�300ms��ʱ��
+	static timer waitingTimer_500ms;								//�ȴ�500ms��ʱ��
+	static timer waitingTimer_1S;										//�ȴ�1S��ʱ��
+	static timer waitingUnlockingTimer;							//���������ʱ��
+	static timer unlockingTimer;										//���������ʱ��
+	static timer openDoorTimer;											//���ڿ���ʱ������
+	static timer closeDoorTimer;										//���ڹ���ʱ������
+	static timer waitingTimer_300S;									//5���Ӻ��Զ�����
+	
+	static uint8_t timer_ok = 0;
+	
+	if(timer_ok == 0)
+	{
+		timer_ok = 1;
+		
+		timer_set(&waitingTimer_100ms, 1);
+		timer_set(&waitingTimer_300ms, 3);
+		timer_set(&waitingTimer_500ms, 5);
+		timer_set(&waitingTimer_1S, CLOCK_SECOND*1);
+		timer_set(&waitingUnlockingTimer, 2);								//����1����ʱ�������ڿ����ȴ򿪵����Ȼ���ٿ���
+		timer_set(&unlockingTimer, 25);											//����1����ʱ�������ڿ��Ƶ������ʱ��
+		timer_set(&openDoorTimer, 16);											//����1����ʱ�������ڿ���ʱ������
+		timer_set(&closeDoorTimer, 20);											//����1����ʱ�������ڹ���ʱ������
+		timer_set(&waitingTimer_300S, CLOCK_SECOND*300);		//����1����ʱ��������5���Ӻ��Զ�����
+	}
+
+	switch(controlSteps)
+	{
+		case 0x00:			//��ʼ״̬
+			if(isOpenDoor_2 == 1)		//���1�����
+			{
+				printf("\r\n--> ���2��!\r\n");	
+				
+				//��ʼʱ������õ��ı���
+				isOpenDoor_2 = 0;				
+				isCloseDoorMark_2 = 0;
+				openDoorCtrlEndMark_2 = 0;
+				
+				faultCode_2 = 0x14;
+				
+				controlSteps = 0x01;											//�п��������������ת������Ͷ�Ų�������
+			}
+			break;
+			
+		case 0x01:		//�򿪵����
+// 			Unlock(2);										//�򿪵����
+			
+			timer_restart(&waitingUnlockingTimer);
+			timer_restart(&unlockingTimer);
+			controlSteps = 0x02;
+			break;
+			
+		case 0x02:		//�ȴ��������
+			if(timer_expired(&waitingUnlockingTimer))
+			{
+				controlSteps = 0x03;
+			}
+			break;
+			
+		case 0x03:		//����
+			printf("\r\n��2��\r\n");
+			DoorOpen(2);
+			
+			controlSteps = 0x04;
+			printf("\r\n������λ���2\r\n");
+			timer_restart(&openDoorTimer);							//�ӵ�ǰʱ�����¿�ʼn�붨ʱ��
+			break;
+			
+		case 0x04:			//������λ���
+			if(timer_expired(&unlockingTimer))					//���������ʱ�䵽������
+			{
+// 				Locked(2);
+			}
+			
+			if(timer_expired(&openDoorTimer))						//�����ʱʱ�䵽�ˣ�����ֹͣ
+			{
+				DoorStop(2);															//��ֹͣ
+// 				Locked(2);
+	
+				printf("\r\n��λ��ʱֹͣ2\r\n");
+				printf("\r\n�ȴ�Ͷ��2\r\n");
+				timer_restart(&waitingTimer_300S);				//�ӵ�ǰʱ�����¿�ʼn�붨ʱ��
+				controlSteps = 0x05;
+				break;
+			}
+			
+			if(motorRunningStatus_2 == 0)								//����Ѿ�ֹͣ��
+			{
+// 				Locked(2);
+				printf("\r\n�ȴ�Ͷ��2\r\n");
+				
+				timer_restart(&waitingTimer_300S);				//�ӵ�ǰʱ�����¿�ʼn�붨ʱ��
+				controlSteps = 0x05;
+				break;
+			}
+			
+			break;
+			
+		case 0x05:		//�ȴ������ź�
+			if(isCloseDoorMark_2 == 1)
+			{
+				isCloseDoorMark_2 = 0;
+				controlSteps = 0x06;										//ת������
+				break;
+			}
+			
+			if(timer_expired(&waitingTimer_300S))			//���5���Ӷ�ʱʱ�䵽�ˣ�����ֹͣ
+			{
+				printf("\r\n5���ӳ�ʱ�Զ�����2\r\n");
+				controlSteps = 0x06;										//ת������
+				break;
+			}
+			break;
+			
+		case 0x06:			//����		
+			printf("\r\n��2�ر���\r\n");
+			DoorClose(2);																//����
+			
+// 			printf("\r\n������λ���2\r\n");
+			timer_restart(&closeDoorTimer);							//�ӵ�ǰʱ�����¿�ʼn�붨ʱ��
+			controlSteps = 0x07;
+			break;
+			
+		case 0x07:			//����
+			if(timer_expired(&closeDoorTimer))					//�����ʱʱ�䵽�ˣ������ֹͣ
+			{
+				DoorStop(2);															//��ֹͣ
+
+// 				printf("\r\n����ʱ�䵽ֹͣ2\r\n");				
+				controlSteps = 0x08;
+				break;
+			}
+			
+			//��λ���ؼ��
+			if(LIMI_KEY2 == 0)
+			{				
+				DoorStop(2);																//��ֹͣ	
+			}
+			
+			if(motorRunningStatus_2 == 0)											//����Ѿ�ֹͣ��
+			{
+				DoorStop(2);
+// 				printf("\r\nM2->Stop\r\n");
+				controlSteps = 0x08;											//ת���ȴ���������
+				break;
+			}
+			break;
+			
+		case 0x08:		//������λ���ع��ϼ��
+			if(LIMI_KEY2 != 0)					//��λ���ؼ��
+			{
+				faultCode_2 = 0x32;
+				limitKeyExceptionMark = 0x20;
+				devChannel2FaultMark = 1;
+				printf("\r\nͶ��2��λ�������쳣��\r\n");
+			}else{
+				faultCode_2 = 0x14;
+			}
+			
+			controlSteps = 0x09;
+			
+//			if(LIMI_KEY2 != 0)					//��λ���ؼ��
+//			{
+//				controlSteps = 0x30;
+//			}else{
+//				controlSteps = 0x09;
+//			}
+			break;
+			
+		case 0x09:		//�����ſ��ƽ���
+			isOpenDoor_2 = 0;
+			isCloseDoorMark_2 = 0;
+			
+			openDoorCtrlEndMark_2 = 1;					//��־�����ſ��ƽ���
+			printf("\r\nNo.2 OK��\r\n");
+			controlSteps = 0x00;
+			break;
+	
+//-------------------------------------------------------------------------------------
+//�����쳣����		
+		case 0x30:
+			printf("\r\nE->����2\r\n");
+// 			Unlock(2);															//�򿪵����
+			timer_restart(&waitingUnlockingTimer);
+			controlSteps = 0x31;
+			break;
+			
+		case 0x31:
+			if(timer_expired(&waitingUnlockingTimer))
+			{
+				printf("\r\nE->����2\r\n");
+				DoorOpen(2);
+				
+				controlSteps = 0x32;
+				timer_restart(&waitingTimer_100ms);
+			}
+			break;
+			
+		case 0x32:
+			if(timer_expired(&waitingTimer_100ms))
+			{
+				printf("\r\nE->��������2ֹͣ\r\n");
+// 				Locked(2);
+				DoorStop(2);															//��ֹͣ
+				controlSteps = 0x33;
+				printf("\r\nE->��2��λ\r\n");
+			}
+			break;
+			
+		case 0x33:
+			if(DoorReset_2() == 1)
+			{
+				controlSteps = 0x34;
+			}
+			break;
+			
+		case 0x34:
+			if(LIMI_KEY2 != 0)
+			{
+				faultCode_2 = 0x32;
+				limitKeyExceptionMark = 0x20;
+				devChannel2FaultMark = 1;
+				controlSteps = 0x09;
+				break;
+			}else{																				//�Ѿ��ָ���ص������Ĵ�������
+				faultCode_2 = 0x14;
+				timer_restart(&waitingTimer_100ms);
+				controlSteps = 0x09;
+			}
+			break;
+			
+		default:
+			controlSteps = 0x00;
+			break;
+	}
+}
+
+/*
+***********************************************************************
+*	�� �� ��: MotorControlTask_3
+*	����˵��: ���1��������
+*	��    �Σ���
+*	�� �� ֵ: ��
+***********************************************************************
+*/
+void MotorControlTask_3(void)
+{
+	uint8_t tempLimKeyVal = 0;
+	static uint8_t controlSteps = 0;
+	uint8_t motorStopMark = 0;											//���ֹͣ��־
+	uint16_t tempWeight = 0;
+	
+	static uint32_t startTimer = 0;									//�����ſ�ʼʱ��
+	static uint32_t endTimer = 0;										//�����Ž���ʱ��
+	
+	static uint32_t preRemainingTimer = 0;					//��һ�λ�ʣʱ��
+	
+	static timer waitingTimer_100ms;								//�ȴ�100ms��ʱ��
+	static timer waitingTimer_300ms;								//�ȴ�300ms��ʱ��
+	static timer waitingTimer_500ms;								//�ȴ�500ms��ʱ��
+	static timer waitingTimer_1S;										//�ȴ�1S��ʱ��
+	static timer waitingUnlockingTimer;							//���������ʱ��
+	static timer unlockingTimer;										//���������ʱ��
+	static timer openDoorTimer;											//���ڿ���ʱ������
+	static timer closeDoorTimer;										//���ڹ���ʱ������
+	static timer waitingTimer_300S;									//5���Ӻ��Զ�����
+	
+	static uint8_t timer_ok = 0;
+	
+	if(timer_ok == 0)
+	{
+		timer_ok = 1;
+		
+		timer_set(&waitingTimer_100ms, 1);
+		timer_set(&waitingTimer_300ms, 3);
+		timer_set(&waitingTimer_500ms, 5);
+		timer_set(&waitingTimer_1S, CLOCK_SECOND*1);
+		timer_set(&waitingUnlockingTimer, 15);							//����1����ʱ�������ڿ����ȴ򿪵����Ȼ���ٿ���
+		timer_set(&unlockingTimer, 25);											//����1����ʱ�������ڿ��Ƶ������ʱ��
+		timer_set(&openDoorTimer, 15);											//����1����ʱ�������ڿ���ʱ������
+		timer_set(&closeDoorTimer, 20);											//����1����ʱ�������ڹ���ʱ������
+		timer_set(&waitingTimer_300S, CLOCK_SECOND*300);		//����1����ʱ��������5���Ӻ��Զ�����
+	}
+
+	switch(controlSteps)
+	{
+		case 0x00:			//��ʼ״̬
+			if(isOpenDoor_3 == 1)		//���1�����
+			{
+				printf("\r\n--> ���3��!\r\n");	
+				
+				//��ʼʱ������õ��ı���
+				isOpenDoor_3 = 0;				
+				isCloseDoorMark_3 = 0;
+				openDoorCtrlEndMark_3 = 0;
+				
+				faultCode_3 = 0x14;
+				
+				controlSteps = 0x01;											//�п��������������ת������Ͷ�Ų�������
+			}
+			break;
+			
+		case 0x01:		//�򿪵����
+			Unlock(3);										//�򿪵����
+			
+			timer_restart(&waitingUnlockingTimer);
+			timer_restart(&unlockingTimer);
+			controlSteps = 0x02;
+			break;
+			
+		case 0x02:		//�ȴ��������
+			if(timer_expired(&waitingUnlockingTimer))
+			{
+				controlSteps = 0x03;
+			}
+			break;
+			
+		case 0x03:		//����
+			printf("\r\n��3��\r\n");
+			DoorOpen(3);
+			
+			controlSteps = 0x04;
+			printf("\r\n������λ���3\r\n");
+			timer_restart(&openDoorTimer);							//�ӵ�ǰʱ�����¿�ʼn�붨ʱ��
+			break;
+			
+		case 0x04:			//������λ���
+			if(timer_expired(&unlockingTimer))					//���������ʱ�䵽������
+			{
+				Locked(3);
+			}
+			
+			if(timer_expired(&openDoorTimer))						//�����ʱʱ�䵽�ˣ�����ֹͣ
+			{
+				DoorStop(3);															//��ֹͣ
+				Locked(3);
+	
+				printf("\r\n��λ��ʱֹͣ3\r\n");
+				printf("\r\n�ȴ�Ͷ��3\r\n");
+				timer_restart(&waitingTimer_300S);				//�ӵ�ǰʱ�����¿�ʼn�붨ʱ��
+				controlSteps = 0x05;
+				break;
+			}
+			
+			if(motorRunningStatus_3 == 0)								//����Ѿ�ֹͣ��
+			{
+				Locked(3);
+				printf("\r\n�ȴ�Ͷ��3\r\n");
+				
+				timer_restart(&waitingTimer_300S);				//�ӵ�ǰʱ�����¿�ʼn�붨ʱ��
+				controlSteps = 0x05;
+				break;
+			}
+			
+			break;
+			
+		case 0x05:		//�ȴ������ź�
+			if(isCloseDoorMark_3 == 1)
+			{
+				isCloseDoorMark_3 = 0;
+				controlSteps = 0x06;										//ת������
+				break;
+			}
+			
+			if(timer_expired(&waitingTimer_300S))			//���5���Ӷ�ʱʱ�䵽�ˣ�����ֹͣ
+			{
+				printf("\r\n5���ӳ�ʱ�Զ�����3\r\n");
+				controlSteps = 0x06;										//ת������
+				break;
+			}
+			break;
+			
+		case 0x06:			//����		
+			printf("\r\n��3�ر���\r\n");
+			DoorClose(3);																//����
+			
+// 			printf("\r\n������λ���3\r\n");
+			timer_restart(&closeDoorTimer);							//�ӵ�ǰʱ�����¿�ʼn�붨ʱ��
+			controlSteps = 0x07;
+			break;
+			
+		case 0x07:			//����
+			if(timer_expired(&closeDoorTimer))					//�����ʱʱ�䵽�ˣ������ֹͣ
+			{
+				DoorStop(3);															//��ֹͣ
+
+// 				printf("\r\n����ʱ�䵽ֹͣ3\r\n");				
+				controlSteps = 0x08;
+				break;
+			}
+			
+			//��λ���ؼ��
+			if(LIMI_KEY3 == 0)
+			{				
+				DoorStop(3);																//��ֹͣ	
+			}
+			
+			if(motorRunningStatus_3 == 0)											//����Ѿ�ֹͣ��
+			{
+				DoorStop(3);
+// 				printf("\r\nM3->Stop\r\n");
+				controlSteps = 0x08;											//ת���ȴ���������
+				break;
+			}
+			break;
+			
+		case 0x08:		//������λ���ع��ϼ��
+			if(LIMI_KEY3 != 0)					//��λ���ؼ��
+			{
+				controlSteps = 0x30;
+			}else{
+				controlSteps = 0x09;
+			}
+			break;
+			
+		case 0x09:		//�����ſ��ƽ���
+			isOpenDoor_3 = 0;
+			isCloseDoorMark_3 = 0;
+			
+			openDoorCtrlEndMark_3 = 1;					//��־�����ſ��ƽ���
+			printf("\r\nNo.3 OK��\r\n");
+			controlSteps = 0x00;
+			break;
+	
+//-------------------------------------------------------------------------------------
+//�����쳣����		
+		case 0x30:
+			printf("\r\nE->����3\r\n");
+			Unlock(3);															//�򿪵����
+			timer_restart(&waitingUnlockingTimer);
+			controlSteps = 0x31;
+			break;
+			
+		case 0x31:
+			if(timer_expired(&waitingUnlockingTimer))
+			{
+				printf("\r\nE->����3\r\n");
+				DoorOpen(3);
+				
+				controlSteps = 0x32;
+				timer_restart(&waitingTimer_100ms);
+			}
+			break;
+			
+		case 0x32:
+			if(timer_expired(&waitingTimer_100ms))
+			{
+				printf("\r\nE->��������3ֹͣ\r\n");
+				Locked(3);
+				DoorStop(3);															//��ֹͣ
+				controlSteps = 0x33;
+				printf("\r\nE->��3��λ\r\n");
+			}
+			break;
+			
+		case 0x33:
+			if(DoorReset_3() == 1)
+			{
+				controlSteps = 0x34;
+			}
+			break;
+			
+		case 0x34:
+			if(LIMI_KEY3 != 0)
+			{
+				faultCode_3 = 0x32;
+				limitKeyExceptionMark = 0x20;
+				devChannel3FaultMark = 1;
+				controlSteps = 0x09;
+				break;
+			}else{																				//�Ѿ��ָ���ص������Ĵ�������
+				faultCode_3 = 0x14;
+				timer_restart(&waitingTimer_100ms);
+				controlSteps = 0x09;
+			}
+			break;
+			
+		default:
+			controlSteps = 0x00;
+			break;
+	}
+}
+
+/*
+***********************************************************************
+*	�� �� ��: MotorControlTask_4
+*	����˵��: ���1��������
+*	��    �Σ���
+*	�� �� ֵ: ��
+***********************************************************************
+*/
+void MotorControlTask_4(void)
+{
+	uint8_t tempLimKeyVal = 0;
+	static uint8_t controlSteps = 0;
+	uint8_t motorStopMark = 0;											//���ֹͣ��־
+	uint16_t tempWeight = 0;
+	
+	static uint32_t startTimer = 0;									//�����ſ�ʼʱ��
+	static uint32_t endTimer = 0;										//�����Ž���ʱ��
+	
+	static uint32_t preRemainingTimer = 0;					//��һ�λ�ʣʱ��
+	
+	static timer waitingTimer_100ms;								//�ȴ�100ms��ʱ��
+	static timer waitingTimer_300ms;								//�ȴ�300ms��ʱ��
+	static timer waitingTimer_500ms;								//�ȴ�500ms��ʱ��
+	static timer waitingTimer_1S;										//�ȴ�1S��ʱ��
+	static timer waitingUnlockingTimer;							//���������ʱ��
+	static timer unlockingTimer;										//���������ʱ��
+	static timer openDoorTimer;											//���ڿ���ʱ������
+	static timer closeDoorTimer;										//���ڹ���ʱ������
+	static timer waitingTimer_300S;									//5���Ӻ��Զ�����
+	
+	static uint8_t timer_ok = 0;
+	
+	if(timer_ok == 0)
+	{
+		timer_ok = 1;
+		
+		timer_set(&waitingTimer_100ms, 1);
+		timer_set(&waitingTimer_300ms, 3);
+		timer_set(&waitingTimer_500ms, 5);
+		timer_set(&waitingTimer_1S, CLOCK_SECOND*1);
+		timer_set(&waitingUnlockingTimer, 15);							//����1����ʱ�������ڿ����ȴ򿪵����Ȼ���ٿ���
+		timer_set(&unlockingTimer, 25);											//����1����ʱ�������ڿ��Ƶ������ʱ��
+		timer_set(&openDoorTimer, 15);											//����1����ʱ�������ڿ���ʱ������
+		timer_set(&closeDoorTimer, 20);											//����1����ʱ�������ڹ���ʱ������
+		timer_set(&waitingTimer_300S, CLOCK_SECOND*300);		//����1����ʱ��������5���Ӻ��Զ�����
+	}
+
+	switch(controlSteps)
+	{
+		case 0x00:			//��ʼ״̬
+			if(isOpenDoor_4 == 1)		//���1�����
+			{
+				printf("\r\n--> ���4��!\r\n");	
+				
+				//��ʼʱ������õ��ı���
+				isOpenDoor_4 = 0;				
+				isCloseDoorMark_4 = 0;
+				openDoorCtrlEndMark_4 = 0;
+				
+				faultCode_4 = 0x14;
+				
+				controlSteps = 0x01;											//�п��������������ת������Ͷ�Ų�������
+			}
+			break;
+			
+		case 0x01:		//�򿪵����
+			Unlock(4);										//�򿪵����
+			
+			timer_restart(&waitingUnlockingTimer);
+			timer_restart(&unlockingTimer);
+			controlSteps = 0x02;
+			break;
+			
+		case 0x02:		//�ȴ��������
+			if(timer_expired(&waitingUnlockingTimer))
+			{
+				controlSteps = 0x03;
+			}
+			break;
+			
+		case 0x03:		//����
+			printf("\r\n��4��\r\n");
+			DoorOpen(4);
+			
+			controlSteps = 0x04;
+			printf("\r\n������λ���4\r\n");
+			timer_restart(&openDoorTimer);							//�ӵ�ǰʱ�����¿�ʼn�붨ʱ��
+			break;
+			
+		case 0x04:			//������λ���
+			if(timer_expired(&unlockingTimer))					//���������ʱ�䵽������
+			{
+				Locked(4);
+			}
+			
+			if(timer_expired(&openDoorTimer))						//�����ʱʱ�䵽�ˣ�����ֹͣ
+			{
+				DoorStop(4);															//��ֹͣ
+				Locked(4);
+	
+				printf("\r\n��λ��ʱֹͣ4\r\n");
+				printf("\r\n�ȴ�Ͷ��4\r\n");
+				timer_restart(&waitingTimer_300S);				//�ӵ�ǰʱ�����¿�ʼn�붨ʱ��
+				controlSteps = 0x05;
+				break;
+			}
+			
+			if(motorRunningStatus_4 == 0)								//����Ѿ�ֹͣ��
+			{
+				Locked(4);
+				printf("\r\n�ȴ�Ͷ��4\r\n");
+				
+				timer_restart(&waitingTimer_300S);				//�ӵ�ǰʱ�����¿�ʼn�붨ʱ��
+				controlSteps = 0x05;
+				break;
+			}
+			
+			break;
+			
+		case 0x05:		//�ȴ������ź�
+			if(isCloseDoorMark_4 == 1)
+			{
+				isCloseDoorMark_4 = 0;
+				controlSteps = 0x06;										//ת������
+				break;
+			}
+			
+			if(timer_expired(&waitingTimer_300S))			//���5���Ӷ�ʱʱ�䵽�ˣ�����ֹͣ
+			{
+				printf("\r\n5���ӳ�ʱ�Զ�����4\r\n");
+				controlSteps = 0x06;										//ת������
+				break;
+			}
+			break;
+			
+		case 0x06:			//����		
+			printf("\r\n��4�ر���\r\n");
+			DoorClose(4);																//����
+			
+// 			printf("\r\n������λ���4\r\n");
+			timer_restart(&closeDoorTimer);							//�ӵ�ǰʱ�����¿�ʼn�붨ʱ��
+			controlSteps = 0x07;
+			break;
+			
+		case 0x07:			//����
+			if(timer_expired(&closeDoorTimer))					//�����ʱʱ�䵽�ˣ������ֹͣ
+			{
+				DoorStop(4);															//��ֹͣ
+
+// 				printf("\r\n����ʱ�䵽ֹͣ4\r\n");				
+				controlSteps = 0x08;
+				break;
+			}
+			
+			//��λ���ؼ��
+			if(LIMI_KEY4 == 0)
+			{				
+				DoorStop(4);																//��ֹͣ	
+			}
+			
+			if(motorRunningStatus_4 == 0)									//����Ѿ�ֹͣ��
+			{
+				DoorStop(4);
+// 				printf("\r\nM4->Stop\r\n");
+				controlSteps = 0x08;											//ת���ȴ���������
+				break;
+			}
+			break;
+			
+		case 0x08:		//������λ���ع��ϼ��
+			if(LIMI_KEY4 != 0)					//��λ���ؼ��
+			{
+				controlSteps = 0x30;
+			}else{
+				controlSteps = 0x09;
+			}
+			break;
+			
+		case 0x09:		//�����ſ��ƽ���
+			isOpenDoor_4 = 0;
+			isCloseDoorMark_4 = 0;
+			
+			openDoorCtrlEndMark_4 = 1;					//��־�����ſ��ƽ���
+			printf("\r\nNo.4 OK��\r\n");
+			controlSteps = 0x00;
+			break;
+	
+//-------------------------------------------------------------------------------------
+//�����쳣����		
+		case 0x30:
+			printf("\r\nE->����4\r\n");
+			Unlock(4);															//�򿪵����
+			timer_restart(&waitingUnlockingTimer);
+			controlSteps = 0x31;
+			break;
+			
+		case 0x31:
+			if(timer_expired(&waitingUnlockingTimer))
+			{
+				printf("\r\nE->����4\r\n");
+				DoorOpen(4);
+				
+				controlSteps = 0x32;
+				timer_restart(&waitingTimer_100ms);
+			}
+			break;
+			
+		case 0x32:
+			if(timer_expired(&waitingTimer_100ms))
+			{
+				printf("\r\nE->��������4ֹͣ\r\n");
+				Locked(4);
+				DoorStop(4);															//��ֹͣ
+				controlSteps = 0x33;
+				printf("\r\nE->��4��λ\r\n");
+			}
+			break;
+			
+		case 0x33:
+			if(DoorReset_4() == 1)
+			{
+				controlSteps = 0x34;
+			}
+			break;
+			
+		case 0x34:
+			if(LIMI_KEY4 != 0)
+			{
+				faultCode_4 = 0x32;
+				limitKeyExceptionMark = 0x20;
+				devChannel4FaultMark = 1;
+				controlSteps = 0x09;
+				break;
+			}else{																				//�Ѿ��ָ���ص������Ĵ�������
+				faultCode_4 = 0x14;
+				timer_restart(&waitingTimer_100ms);
+				controlSteps = 0x09;
+			}
+			break;
+			
+		default:
+			controlSteps = 0x00;
+			break;
+	}
+}
+
+/*
+***********************************************************************
+*	�� �� ��: OpenDoorControlTask
+*	����˵��: �����ſ�������
+*	��    �Σ���
+*	�� �� ֵ: ��
+***********************************************************************
+*/
+void OpenDoorControlTask(void)
+{
+	MotorControlTask_1();
+	MotorControlTask_2();
+	MotorControlTask_3();
+	MotorControlTask_4();
+}
+
+/*
+***********************************************************************
+*	�� �� ��: DoorReset_1
+*	����˵��: ��1��λ�ص����
+*	��    �Σ���
+*	�� �� ֵ: ��λ��ɺ󷵻�1
+***********************************************************************
+*/
+uint8_t DoorReset_1(void)
+{
+	static uint8_t resetStatus = 0x00;			//�Ÿ�λ״̬
+	uint8_t returnVal = 0;
+	
+	static timer resetMotorTimer;
+	static uint8_t timer_ok = 0;
+	
+	if(timer_ok == 0)
+	{
+		timer_ok = 1;
+		timer_set(&resetMotorTimer, 20);	
+	}
+	
+	//�����λ���̿���
+	switch(resetStatus)
+	{
+		case 0x00:		//��ʼ״̬
+// 			printf("\r\n��1��λ����\r\n");
+			if(LIMI_KEY1 == 0)			//��λ�����Ѿ�������λ
+			{
+				resetStatus = 0x03;
+			}else{
+				resetStatus = 0x01;
+			}
+			break;
+			
+		case 0x01:		//�Ÿ�λ����
+			DoorClose(1);																//����
+			resetStatus = 0x02;
+// 			printf("\r\n��1��λ��λ���\r\n");
+			timer_restart(&resetMotorTimer);							//�ӵ�ǰʱ�����¿�ʼn�붨ʱ��
+			break;
+			
+		case 0x02:		//���Ѹ�λ�ɹ��ж�
+			if(timer_expired(&resetMotorTimer))					//�����ʱʱ�䵽�ˣ������ֹͣ
+			{
+				DoorStop(1);															//��ֹͣ
+		
+				resetStatus = 0x03;
+// 				printf("\r\n��1��λʱ�䵽ֹͣ\r\n");
+				break;
+			}
+			
+			//��λ���ؼ��
+			if(LIMI_KEY1 == 0)												//��λ���ؼ��
+			{				
+				DoorStop(1);																//��ֹͣ	
+// 				printf("\r\nR->���1�ѿ�����λֹͣ\r\n");
+			}
+
+// 			//����������
+// 			if(motorCurrentVal_1 > M1_CLOSE_MAX_CurrentVal)			//������λ��⣬ͨ������������ж���λ
+// 			{
+// 				DoorStop(1);																//��ֹͣ		
+// // 				printf("\r\n���1����λֹͣ��������ֵ = %d\r\n", motorCurrentVal_1);
+// 			}
+			
+			if(motorRunningStatus_1 == 0)								//����Ѿ�ֹͣ��
+			{
+// 				printf("\r\n���1�Ѿ�ֹͣ\r\n");
+				resetStatus = 0x03;										
+				break;
+			}
+			break;
+			
+		case 0x03:		//������ɸ�λ
+			printf("\r\n��1����ɸ�λ������\r\n");
+			
+			//����һ���������������ֹͣ
+			DoorStop(1);															//��ֹͣ
+			returnVal = 1;
+			resetStatus = 0x00;
+			break;
+			
+		default:
+			printf("\r\n ���1��λδ֪״̬������\r\n");
+			
+			//����һ���費�����������ֹͣ
+			DoorStop(1);															//��ֹͣ
+			returnVal = 1;
+			resetStatus = 0x00;
+			break;
+	}
+	
+	return returnVal;
+}
+
+/*
+***********************************************************************
+*	�� �� ��: DoorReset_2
+*	����˵��: ��2��λ�ص����
+*	��    �Σ���
+*	�� �� ֵ: ��λ��ɺ󷵻�1
+***********************************************************************
+*/
+uint8_t DoorReset_2(void)
+{
+	static uint8_t resetStatus = 0x00;			//�Ÿ�λ״̬
+	uint8_t returnVal = 0;
+	
+	static timer resetMotorTimer;
+	static uint8_t timer_ok = 0;
+	
+	if(timer_ok == 0)
+	{
+		timer_ok = 1;
+		timer_set(&resetMotorTimer, 20);	
+	}
+	
+	//�����λ���̿���
+	switch(resetStatus)
+	{
+		case 0x00:		//��ʼ״̬
+// 			printf("\r\n��2��λ����\r\n");
+			
+			if(LIMI_KEY2 == 0)			//��λ�����Ѿ�������λ
+			{
+				resetStatus = 0x03;
+			}else{
+				resetStatus = 0x01;
+			}
+			break;
+			
+		case 0x01:		//�Ÿ�λ����
+			DoorClose(2);																//����
+			resetStatus = 0x02;
+// 			printf("\r\n��2��λ��λ���\r\n");
+			timer_restart(&resetMotorTimer);							//�ӵ�ǰʱ�����¿�ʼn�붨ʱ��
+			break;
+			
+		case 0x02:		//���Ѹ�λ�ɹ��ж�
+			if(timer_expired(&resetMotorTimer))					//�����ʱʱ�䵽�ˣ������ֹͣ
+			{
+				DoorStop(2);															//��ֹͣ
+		
+				resetStatus = 0x03;
+// 				printf("\r\n��2��λʱ�䵽ֹͣ\r\n");
+				break;
+			}
+			
+			//��λ���ؼ��
+			if(LIMI_KEY2 == 0)												//��λ���ؼ��
+			{				
+				DoorStop(2);																//��ֹͣ	
+// 				printf("\r\nR->���2�ѿ�����λֹͣ\r\n");
+			}
+
+// 			//����������
+// 			if(motorCurrentVal_2 > M2_CLOSE_MAX_CurrentVal)			//������λ��⣬ͨ������������ж���λ
+// 			{
+// 				DoorStop(2);																//��ֹͣ		
+// // 				printf("\r\n���2����λֹͣ��������ֵ = %d\r\n", motorCurrentVal_2);
+// 			}
+			
+			if(motorRunningStatus_2 == 0)								//����Ѿ�ֹͣ��
+			{
+// 				printf("\r\n���2�Ѿ�ֹͣ\r\n");
+				resetStatus = 0x03;										
+				break;
+			}
+			break;
+			
+		case 0x03:		//������ɸ�λ
+			printf("\r\n��2����ɸ�λ������\r\n");
+			
+			//����һ���������������ֹͣ
+			DoorStop(2);															//��ֹͣ
+			returnVal = 1;
+			resetStatus = 0x00;
+			break;
+			
+		default:
+			printf("\r\n ���2��λδ֪״̬������\r\n");
+			
+			//����һ���費�����������ֹͣ
+			DoorStop(2);															//��ֹͣ
+			returnVal = 1;
+			resetStatus = 0x00;
+			break;
+	}
+	
+	return returnVal;
+}
+
+/*
+***********************************************************************
+*	�� �� ��: DoorReset_3
+*	����˵��: ��3��λ�ص����
+*	��    �Σ���
+*	�� �� ֵ: ��λ��ɺ󷵻�1
+***********************************************************************
+*/
+uint8_t DoorReset_3(void)
+{
+	static uint8_t resetStatus = 0x00;			//�Ÿ�λ״̬
+	uint8_t returnVal = 0;
+	
+	static timer resetMotorTimer;
+	static uint8_t timer_ok = 0;
+	
+	if(timer_ok == 0)
+	{
+		timer_ok = 1;
+		timer_set(&resetMotorTimer, 20);	
+	}
+	
+	//�����λ���̿���
+	switch(resetStatus)
+	{
+		case 0x00:		//��ʼ״̬
+// 			printf("\r\n��3��λ����\r\n");
+			if(LIMI_KEY3 == 0)			//��λ�����Ѿ�������λ
+			{
+				resetStatus = 0x03;
+			}else{
+				resetStatus = 0x01;
+			}
+			break;
+			
+		case 0x01:		//�Ÿ�λ����
+			DoorClose(3);																//����
+			resetStatus = 0x02;
+// 			printf("\r\n��3��λ��λ���\r\n");
+			timer_restart(&resetMotorTimer);							//�ӵ�ǰʱ�����¿�ʼn�붨ʱ��
+			break;
+			
+		case 0x02:		//���Ѹ�λ�ɹ��ж�
+			if(timer_expired(&resetMotorTimer))					//�����ʱʱ�䵽�ˣ������ֹͣ
+			{
+				DoorStop(3);															//��ֹͣ
+		
+				resetStatus = 0x03;
+// 				printf("\r\n��3��λʱ�䵽ֹͣ\r\n");
+				break;
+			}
+			
+			//��λ���ؼ��
+			if(LIMI_KEY3 == 0)												//��λ���ؼ��
+			{				
+				DoorStop(3);																//��ֹͣ	
+// 				printf("\r\nR->���3�ѿ�����λֹͣ\r\n");
+			}
+
+// 			//����������
+// 			if(motorCurrentVal_2 > M2_CLOSE_MAX_CurrentVal)			//������λ��⣬ͨ������������ж���λ
+// 			{
+// 				DoorStop(2);																//��ֹͣ		
+// // 				printf("\r\n���2����λֹͣ��������ֵ = %d\r\n", motorCurrentVal_2);
+// 			}
+			
+			if(motorRunningStatus_3 == 0)								//����Ѿ�ֹͣ��
+			{
+// 				printf("\r\n���3�Ѿ�ֹͣ\r\n");
+				resetStatus = 0x03;										
+				break;
+			}
+			break;
+			
+		case 0x03:		//������ɸ�λ
+			printf("\r\n��3����ɸ�λ������\r\n");
+			
+			//����һ���������������ֹͣ
+			DoorStop(3);															//��ֹͣ
+			returnVal = 1;
+			resetStatus = 0x00;
+			break;
+			
+		default:
+			printf("\r\n ���3��λδ֪״̬������\r\n");
+			
+			//����һ���費�����������ֹͣ
+			DoorStop(3);															//��ֹͣ
+			returnVal = 1;
+			resetStatus = 0x00;
+			break;
+	}
+	
+	return returnVal;
+}
+
+/*
+***********************************************************************
+*	�� �� ��: DoorReset_4
+*	����˵��: ��4��λ�ص����
+*	��    �Σ���
+*	�� �� ֵ: ��λ��ɺ󷵻�1
+***********************************************************************
+*/
+uint8_t DoorReset_4(void)
+{
+	static uint8_t resetStatus = 0x00;			//�Ÿ�λ״̬
+	uint8_t returnVal = 0;
+	
+	static timer resetMotorTimer;
+	static uint8_t timer_ok = 0;
+	
+	if(timer_ok == 0)
+	{
+		timer_ok = 1;
+		timer_set(&resetMotorTimer, 20);	
+	}
+	
+	//�����λ���̿���
+	switch(resetStatus)
+	{
+		case 0x00:		//��ʼ״̬
+// 			printf("\r\n��4��λ����\r\n");
+			
+			if(LIMI_KEY4 == 0)			//��λ�����Ѿ�������λ
+			{
+				resetStatus = 0x03;
+			}else{
+				resetStatus = 0x01;
+			}
+			break;
+			
+		case 0x01:		//�Ÿ�λ����
+			DoorClose(4);																//����
+			resetStatus = 0x02;
+// 			printf("\r\n��4��λ��λ���\r\n");
+			timer_restart(&resetMotorTimer);							//�ӵ�ǰʱ�����¿�ʼn�붨ʱ��
+			break;
+			
+		case 0x02:		//���Ѹ�λ�ɹ��ж�
+			if(timer_expired(&resetMotorTimer))					//�����ʱʱ�䵽�ˣ������ֹͣ
+			{
+				DoorStop(4);															//��ֹͣ
+		
+				resetStatus = 0x03;
+// 				printf("\r\n��4��λʱ�䵽ֹͣ\r\n");
+				break;
+			}
+			
+			//��λ���ؼ��
+			if(LIMI_KEY4 == 0)												//��λ���ؼ��
+			{				
+				DoorStop(4);																//��ֹͣ	
+// 				printf("\r\nR->���2�ѿ�����λֹͣ\r\n");
+			}
+
+// 			//����������
+// 			if(motorCurrentVal_2 > M2_CLOSE_MAX_CurrentVal)			//������λ��⣬ͨ������������ж���λ
+// 			{
+// 				DoorStop(2);																//��ֹͣ		
+// // 				printf("\r\n���2����λֹͣ��������ֵ = %d\r\n", motorCurrentVal_2);
+// 			}
+			
+			if(motorRunningStatus_4 == 0)								//����Ѿ�ֹͣ��
+			{
+// 				printf("\r\n���4�Ѿ�ֹͣ\r\n");
+				resetStatus = 0x03;										
+				break;
+			}
+			break;
+			
+		case 0x03:		//������ɸ�λ
+			printf("\r\n��4����ɸ�λ������\r\n");
+			
+			//����һ���������������ֹͣ
+			DoorStop(4);															//��ֹͣ
+			returnVal = 1;
+			resetStatus = 0x00;
+			break;
+			
+		default:
+			printf("\r\n ���4��λδ֪״̬������\r\n");
+			
+			//����һ���費�����������ֹͣ
+			DoorStop(4);															//��ֹͣ
+			returnVal = 1;
+			resetStatus = 0x00;
+			break;
+	}
+	
+	return returnVal;
+}
+
+/*
+***********************************************************************
+*	�� �� ��: DoorResetTask
+*	����˵��: ��ʼ�ϵ��Ÿ�λ�ص����
+*	��    �Σ���
+*	�� �� ֵ: �ޣ��ı�doorResetMark״̬��
+***********************************************************************
+*/
+void DoorResetTask(void)
+{
+	static uint8_t doorResetStatus_1 = 0;
+	static uint8_t doorResetStatus_2 = 0;
+	static uint8_t doorResetStatus_3 = 0;
+	static uint8_t doorResetStatus_4 = 0;
+	
+	if(doorResetStatus_1 == 0)
+	{
+		doorResetStatus_1 = DoorReset_1();
+	}
+	
+	if(doorResetStatus_2 == 0)
+	{
+		doorResetStatus_2 = DoorReset_2();
+	}
+	
+	if(doorResetStatus_3 == 0)
+	{
+		doorResetStatus_3 = DoorReset_3();
+	}
+	
+	if(doorResetStatus_4 == 0)
+	{
+		doorResetStatus_4 = DoorReset_4();
+	}
+	
+	if((doorResetStatus_1 == 1) && (doorResetStatus_2 == 1) &&
+		 (doorResetStatus_3 == 1) && (doorResetStatus_4 == 1))
+	{
+		doorResetMark = 1;
+	}
+}
+
+/******************** (C) COPYRIGHT 2017 ping *****END OF FILE*******************/
diff --git a/STM32_4路称重_Git提交精简工程/src/HARDWARE/MOTOR/door_ctrl.h b/STM32_4路称重_Git提交精简工程/src/HARDWARE/MOTOR/door_ctrl.h
new file mode 100755
index 0000000..037d791
--- /dev/null
+++ b/STM32_4路称重_Git提交精简工程/src/HARDWARE/MOTOR/door_ctrl.h
@@ -0,0 +1,26 @@
+/*************************** (C) COPYRIGHT 2017 CXHY ****************************
+ * �ļ���  ��door_ctrl.h
+ * ��  ��  ��Ͷ�ſڿ��Ƴ���
+ * ��  ��  ��V1.0
+ * ��  ��  ��XuZhongPing
+ * ��  ��  ��2017/03/06 
+*********************************************************************************/
+#ifndef __DOOR_CTRL_H
+#define __DOOR_CTRL_H	 
+
+#include "stm32f10x.h"
+#include "stdio.h"
+
+extern uint8_t doorResetMark;							//�Ÿ�λ״̬
+
+void OpenDoorControlTask(void);
+
+uint8_t DoorReset_1(void);
+uint8_t DoorReset_2(void);
+uint8_t DoorReset_3(void);
+uint8_t DoorReset_4(void);
+void DoorResetTask(void);
+
+#endif
+
+/******************** (C) COPYRIGHT 2017 YNHB *****END OF FILE*******************/
diff --git a/STM32_4路称重_Git提交精简工程/src/HARDWARE/MOTOR/motor.c b/STM32_4路称重_Git提交精简工程/src/HARDWARE/MOTOR/motor.c
new file mode 100755
index 0000000..c19d681
--- /dev/null
+++ b/STM32_4路称重_Git提交精简工程/src/HARDWARE/MOTOR/motor.c
@@ -0,0 +1,474 @@
+/*************************** (C) COPYRIGHT 2017 CXHY ****************************
+ * �ļ���  ��motor.c
+ * ��  ��  ��������Ƴ���
+ * ��  ��  ��V1.0
+ * ��  ��  ��XuZhongPing
+ * ��  ��  ��2017/03/06 
+*********************************************************************************/
+#include "motor.h"
+#include "delay.h"
+#include "timer.h"
+#include "adc.h"
+#include "my_math.h"
+#include "device.h"
+
+//���ʹ�õ�IO�ڶ���
+#define MOTOR1_PORT_PeriphClock_A 	RCC_APB2Periph_GPIOB	
+#define MOTOR1_PORT_A								GPIOB
+#define MOTOR1_CTRL_PIN_A						GPIO_Pin_15
+#define MOTOR1_PORT_PeriphClock_B 	RCC_APB2Periph_GPIOC	
+#define MOTOR1_PORT_B								GPIOC
+#define MOTOR1_CTRL_PIN_B						GPIO_Pin_6
+
+#define MOTOR2_PORT_PeriphClock_A 	RCC_APB2Periph_GPIOC	
+#define MOTOR2_PORT_A								GPIOC
+#define MOTOR2_CTRL_PIN_A						GPIO_Pin_7
+#define MOTOR2_PORT_PeriphClock_B 	RCC_APB2Periph_GPIOC	
+#define MOTOR2_PORT_B								GPIOC
+#define MOTOR2_CTRL_PIN_B						GPIO_Pin_8
+
+#define MOTOR3_PORT_PeriphClock_A 	RCC_APB2Periph_GPIOC	
+#define MOTOR3_PORT_A								GPIOC
+#define MOTOR3_CTRL_PIN_A						GPIO_Pin_9
+#define MOTOR3_PORT_PeriphClock_B 	RCC_APB2Periph_GPIOA	
+#define MOTOR3_PORT_B								GPIOA
+#define MOTOR3_CTRL_PIN_B						GPIO_Pin_8	
+
+#define MOTOR4_PORT_PeriphClock_A 	RCC_APB2Periph_GPIOA	
+#define MOTOR4_PORT_A								GPIOA
+#define MOTOR4_CTRL_PIN_A						GPIO_Pin_11
+#define MOTOR4_PORT_PeriphClock_B 	RCC_APB2Periph_GPIOA	
+#define MOTOR4_PORT_B								GPIOA
+#define MOTOR4_CTRL_PIN_B						GPIO_Pin_12
+
+
+#define CurrentValSize	50
+uint16_t motorCurrentValBuf_1[CurrentValSize];
+uint16_t motorCurrentVal_1 = 0;
+uint8_t motorRunningStatus_1 = 0;
+uint8_t motorPreStatus_1 = 0;	
+
+uint16_t motorCurrentValBuf_2[CurrentValSize];
+uint16_t motorCurrentVal_2 = 0;
+uint8_t motorRunningStatus_2 = 0;
+uint8_t motorPreStatus_2 = 0;	
+
+uint8_t motorRunningStatus_3 = 0;
+uint8_t motorRunningStatus_4 = 0;
+	
+/*
+***********************************************************************
+*	�� �� ��: MotorInit
+*	����˵��: �������IO�ڳ�ʼ��
+*	��    �Σ���
+*	�� �� ֵ: ��
+***********************************************************************
+*/
+void MotorInit(void)
+{ 
+ 	GPIO_InitTypeDef GPIO_InitStructure;
+	
+ 	RCC_APB2PeriphClockCmd(MOTOR1_PORT_PeriphClock_A, ENABLE);
+	RCC_APB2PeriphClockCmd(MOTOR1_PORT_PeriphClock_B, ENABLE);
+	RCC_APB2PeriphClockCmd(MOTOR2_PORT_PeriphClock_A, ENABLE);
+	RCC_APB2PeriphClockCmd(MOTOR2_PORT_PeriphClock_B, ENABLE);
+	RCC_APB2PeriphClockCmd(MOTOR3_PORT_PeriphClock_A, ENABLE);
+	RCC_APB2PeriphClockCmd(MOTOR3_PORT_PeriphClock_B, ENABLE);
+	RCC_APB2PeriphClockCmd(MOTOR4_PORT_PeriphClock_A, ENABLE);
+	RCC_APB2PeriphClockCmd(MOTOR4_PORT_PeriphClock_B, ENABLE);
+
+	//���1��������IO�ڳ�ʼ��
+	GPIO_InitStructure.GPIO_Pin  = MOTOR1_CTRL_PIN_A;
+	GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP;
+	GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
+	GPIO_Init(MOTOR1_PORT_A, &GPIO_InitStructure);
+	GPIO_ResetBits(MOTOR1_PORT_A, MOTOR1_CTRL_PIN_A);
+	
+	GPIO_InitStructure.GPIO_Pin  = MOTOR1_CTRL_PIN_B;
+	GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP;
+	GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
+	GPIO_Init(MOTOR1_PORT_B, &GPIO_InitStructure);
+	GPIO_ResetBits(MOTOR1_PORT_B, MOTOR1_CTRL_PIN_B);
+	
+	//���2��������IO�ڳ�ʼ��
+	GPIO_InitStructure.GPIO_Pin  = MOTOR2_CTRL_PIN_A;
+	GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP;
+	GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
+	GPIO_Init(MOTOR2_PORT_A, &GPIO_InitStructure);
+	GPIO_ResetBits(MOTOR2_PORT_A, MOTOR2_CTRL_PIN_A);
+	
+	GPIO_InitStructure.GPIO_Pin  = MOTOR2_CTRL_PIN_B;
+	GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP;
+	GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
+	GPIO_Init(MOTOR2_PORT_B, &GPIO_InitStructure);
+	GPIO_ResetBits(MOTOR2_PORT_B, MOTOR2_CTRL_PIN_B);
+	
+	//���3��������IO�ڳ�ʼ��
+	GPIO_InitStructure.GPIO_Pin  = MOTOR3_CTRL_PIN_A;
+	GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP;
+	GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
+	GPIO_Init(MOTOR3_PORT_A, &GPIO_InitStructure);
+	GPIO_ResetBits(MOTOR3_PORT_A, MOTOR3_CTRL_PIN_A);
+	
+	GPIO_InitStructure.GPIO_Pin  = MOTOR3_CTRL_PIN_B;
+	GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP;
+	GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
+	GPIO_Init(MOTOR3_PORT_B, &GPIO_InitStructure);
+	GPIO_ResetBits(MOTOR3_PORT_B, MOTOR3_CTRL_PIN_B);
+	
+	//���4��������IO�ڳ�ʼ��
+	GPIO_InitStructure.GPIO_Pin  = MOTOR4_CTRL_PIN_A;
+	GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP;
+	GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
+	GPIO_Init(MOTOR4_PORT_A, &GPIO_InitStructure);
+	GPIO_ResetBits(MOTOR4_PORT_A, MOTOR4_CTRL_PIN_A);
+	
+	GPIO_InitStructure.GPIO_Pin  = MOTOR4_CTRL_PIN_B;
+	GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP;
+	GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
+	GPIO_Init(MOTOR4_PORT_B, &GPIO_InitStructure);
+	GPIO_ResetBits(MOTOR4_PORT_B, MOTOR4_CTRL_PIN_B);
+}
+
+/*
+***********************************************************************
+*	�� �� ��: DoorOpen
+*	����˵��: ����
+*	��    �Σ�num -> ��һ����
+*	�� �� ֵ: ��
+***********************************************************************
+*/
+void DoorOpen(uint8_t num)
+{
+	printf("\r\n�����%d����ת��\r\n", num);
+	switch(num)
+	{
+		case 0x01:
+			GPIO_ResetBits(MOTOR1_PORT_A, MOTOR1_CTRL_PIN_A);
+			GPIO_SetBits(MOTOR1_PORT_B, MOTOR1_CTRL_PIN_B);
+			motorRunningStatus_1 = 1;
+			break;
+		
+		case 0x02:
+			GPIO_ResetBits(MOTOR2_PORT_A, MOTOR2_CTRL_PIN_A);
+			GPIO_SetBits(MOTOR2_PORT_B, MOTOR2_CTRL_PIN_B);
+			motorRunningStatus_2 = 1;
+			break;
+			
+		case 0x03:
+			GPIO_ResetBits(MOTOR3_PORT_A, MOTOR3_CTRL_PIN_A);
+			GPIO_SetBits(MOTOR3_PORT_B, MOTOR3_CTRL_PIN_B);
+			motorRunningStatus_3 = 1;
+			break;
+			
+		case 0x04:
+			GPIO_ResetBits(MOTOR4_PORT_A, MOTOR4_CTRL_PIN_A);
+			GPIO_SetBits(MOTOR4_PORT_B, MOTOR4_CTRL_PIN_B);
+			motorRunningStatus_4 = 1;
+			break;
+
+		default:
+			break;
+	}
+}
+
+/*
+***********************************************************************
+*	�� �� ��: DoorClose
+*	����˵��: ����
+*	��    �Σ���
+*	�� �� ֵ: ��
+***********************************************************************
+*/
+void DoorClose(uint8_t num)
+{
+	printf("\r\n�����%d����ת��\r\n", num);
+	switch(num)
+	{
+		case 0x01:
+			GPIO_SetBits(MOTOR1_PORT_A, MOTOR1_CTRL_PIN_A);
+			GPIO_ResetBits(MOTOR1_PORT_B, MOTOR1_CTRL_PIN_B);
+			motorRunningStatus_1 = 2;
+			break;
+		
+		case 0x02:
+			GPIO_SetBits(MOTOR2_PORT_A, MOTOR2_CTRL_PIN_A);
+			GPIO_ResetBits(MOTOR2_PORT_B, MOTOR2_CTRL_PIN_B);
+			motorRunningStatus_2 = 2;
+			break;
+			
+		case 0x03:
+			GPIO_SetBits(MOTOR3_PORT_A, MOTOR3_CTRL_PIN_A);
+			GPIO_ResetBits(MOTOR3_PORT_B, MOTOR3_CTRL_PIN_B);
+			motorRunningStatus_3 = 2;
+			break;
+			
+		case 0x04:
+			GPIO_SetBits(MOTOR4_PORT_A, MOTOR4_CTRL_PIN_A);
+			GPIO_ResetBits(MOTOR4_PORT_B, MOTOR4_CTRL_PIN_B);
+			motorRunningStatus_4 = 2;
+			break;
+
+		default:
+			break;
+	}
+}
+
+/*
+***********************************************************************
+*	�� �� ��: DoorStop
+*	����˵��: ֹͣ
+*	��    �Σ���
+*	�� �� ֵ: ��
+***********************************************************************
+*/
+void DoorStop(uint8_t num)
+{
+	switch(num)
+	{
+		case 0x01:
+			GPIO_ResetBits(MOTOR1_PORT_A, MOTOR1_CTRL_PIN_A);
+			GPIO_ResetBits(MOTOR1_PORT_B, MOTOR1_CTRL_PIN_B);
+			
+			if(motorRunningStatus_1 > 0)			//ԭ��״̬��ת�����ֹͣ�Ŵ�ӡ��ʾ
+			{
+				printf("\r\n�����%d��ֹͣ��\r\n", num);
+			}
+			motorRunningStatus_1 = 0;
+			break;
+		
+		case 0x02:
+			GPIO_ResetBits(MOTOR2_PORT_A, MOTOR2_CTRL_PIN_A);
+			GPIO_ResetBits(MOTOR2_PORT_B, MOTOR2_CTRL_PIN_B);
+			
+			if(motorRunningStatus_2 > 0)			//ԭ��״̬��ת�����ֹͣ�Ŵ�ӡ��ʾ
+			{
+				printf("\r\n�����%d��ֹͣ��\r\n", num);
+			}
+			motorRunningStatus_2 = 0;
+			break;
+			
+		case 0x03:
+			GPIO_ResetBits(MOTOR3_PORT_A, MOTOR3_CTRL_PIN_A);
+			GPIO_ResetBits(MOTOR3_PORT_B, MOTOR3_CTRL_PIN_B);
+			
+			if(motorRunningStatus_3 > 0)			//ԭ��״̬��ת�����ֹͣ�Ŵ�ӡ��ʾ
+			{
+				printf("\r\n�����%d��ֹͣ��\r\n", num);
+			}
+			motorRunningStatus_3 = 0;
+			break;
+			
+		case 0x04:
+			GPIO_ResetBits(MOTOR4_PORT_A, MOTOR4_CTRL_PIN_A);
+			GPIO_ResetBits(MOTOR4_PORT_B, MOTOR4_CTRL_PIN_B);
+			
+			if(motorRunningStatus_4 > 0)			//ԭ��״̬��ת�����ֹͣ�Ŵ�ӡ��ʾ
+			{
+				printf("\r\n�����%d��ֹͣ��\r\n", num);
+			}
+			motorRunningStatus_4 = 0;
+			break;
+
+		default:
+			break;
+	}
+}
+
+/*
+***********************************************************************
+*	�� �� ��: Get_MotorCurrentVal
+*	����˵��: ��ȡ���1������������
+*	��    �Σ���	         
+*	�� �� ֵ: ��
+***********************************************************************
+*/
+void Get_MotorCurrentVal_1(void)
+{
+	Data_collection(motorCurrentValBuf_1, CurrentValSize, ADC_Channel_8);
+	sort_16(motorCurrentValBuf_1, CurrentValSize);           							//�Դ��ڻ����еĲɼ����ݽ�������
+	motorCurrentVal_1 = average_16(motorCurrentValBuf_1, CurrentValSize, 20);				//ȥ��ͷ��β����ƽ����
+}
+
+/*
+***********************************************************************
+*	�� �� ��: Get_MotorCurrentVal
+*	����˵��: ��ȡ���2������������
+*	��    �Σ���	         
+*	�� �� ֵ: ��
+***********************************************************************
+*/
+void Get_MotorCurrentVal_2(void)
+{
+	Data_collection(motorCurrentValBuf_2, CurrentValSize, ADC_Channel_9);
+	sort_16(motorCurrentValBuf_2, CurrentValSize);           							//�Դ��ڻ����еĲɼ����ݽ�������
+	motorCurrentVal_2 = average_16(motorCurrentValBuf_2, CurrentValSize, 20);				//ȥ��ͷ��β����ƽ����
+}
+
+
+/*
+***********************************************************************
+*	�� �� ��: Get_MotorCurrentVal
+*	����˵��: ��ȡ���������������
+*	��    �Σ���	         
+*	�� �� ֵ: ��
+***********************************************************************
+*/
+void Get_MotorCurrentVal(void)
+{
+	Get_MotorCurrentVal_1();
+	Get_MotorCurrentVal_2();
+// 	printf("%4d, %4d\r\n", motorCurrentVal_1, motorCurrentVal_2);
+}
+
+/*
+***********************************************************************
+*	�� �� ��: MotorTest
+*	����˵��: ������Ʋ��Գ���
+*	��    �Σ���	         
+*	�� �� ֵ: ��
+***********************************************************************
+*/
+void MotorTest(void)
+{
+	static uint8_t motorNum = 1;
+	static uint8_t motorStatus = 0;
+	
+	static timer timer_01, timer_02;
+	static uint8_t timer_ok = 0;
+	
+	if(timer_ok == 0)
+	{
+		timer_ok = 1;
+		timer_set(&timer_01, 20);
+		timer_set(&timer_02, CLOCK_SECOND*2);
+	}
+	switch(motorStatus)
+	{
+		case 0x00:
+			if(timer_expired(&timer_01))
+			{
+				DoorOpen(motorNum);
+				timer_restart(&timer_01);
+				motorStatus = 0x01;
+				break;
+			}
+			break;
+			
+		case 0x01:
+			if(timer_expired(&timer_01))
+			{
+				DoorStop(motorNum);
+				timer_restart(&timer_02);
+				motorStatus = 0x02;
+				break;
+			}
+			break;
+			
+		case 0x02:
+			if(timer_expired(&timer_02))
+			{
+				DoorClose(motorNum);
+				timer_restart(&timer_01);
+				motorStatus = 0x03;
+				break;
+			}
+			break;
+			
+		case 0x03:
+			if(timer_expired(&timer_01))
+			{
+				DoorStop(motorNum);
+				timer_restart(&timer_02);
+				motorStatus = 0x04;
+				break;
+			}
+			break;
+			
+		case 0x04:
+			if(timer_expired(&timer_02))
+			{
+				motorNum++;
+				if(motorNum >= 5)
+				{
+					motorNum = 1;
+				}
+				motorStatus = 0x00;
+				break;
+			}
+			break;
+	}
+}
+
+/*
+***********************************************************************
+*	�� �� ��: Get_MotorCurrentVal
+*	����˵��: ��ȡ���������������
+*	��    �Σ���	         
+*	�� �� ֵ: ��
+***********************************************************************
+*/
+void MotorCtrlTask2(void)
+{
+	static timer timer_01, timer_02;
+	static uint8_t timer_ok = 0;
+	static uint8_t motorStatus = 0;
+	
+	if(timer_ok == 0)
+	{
+		timer_ok = 1;
+		timer_set(&timer_01, 1);
+		timer_set(&timer_02, CLOCK_SECOND*2);
+	}
+	switch(motorStatus)
+	{
+		case 0x00:
+			if(motorRunningStatus_2)
+			{
+				motorStatus = 0x01;
+				timer_restart(&timer_01);
+			}
+			break;
+			
+		case 0x01:
+			if(timer_expired(&timer_01))
+			{
+				motorStatus = 0x02;
+			}
+			break;
+			
+		case 0x02:
+			if(motorCurrentVal_2 > 600)
+			{
+				motorPreStatus_2 = motorRunningStatus_2;
+				motorRunningStatus_2 = 0;
+				motorStatus = 0x03;
+				timer_restart(&timer_02);
+			}
+			break;
+			
+		case 0x03:
+			if(timer_expired(&timer_02))
+			{
+				if(motorPreStatus_2 == 1)
+				{
+					motorRunningStatus_2 = 2;
+				}else{
+					motorRunningStatus_2 = 1;
+				}
+				motorStatus = 0x00;
+			}	
+			break;
+	}
+	
+	if(motorRunningStatus_2 == 0)
+	{
+		DoorStop(2);
+	}else if(motorRunningStatus_2 == 1){
+		DoorClose(2);
+	}else{
+		DoorOpen(2);
+	}
+}
+
+/******************** (C) COPYRIGHT 2017 ping *****END OF FILE*******************/
diff --git a/STM32_4路称重_Git提交精简工程/src/HARDWARE/MOTOR/motor.h b/STM32_4路称重_Git提交精简工程/src/HARDWARE/MOTOR/motor.h
new file mode 100755
index 0000000..0b08326
--- /dev/null
+++ b/STM32_4路称重_Git提交精简工程/src/HARDWARE/MOTOR/motor.h
@@ -0,0 +1,39 @@
+/*************************** (C) COPYRIGHT 2017 CXHY ****************************
+ * �ļ���  ��motor.h
+ * ��  ��  ��������Ƴ���
+ * ��  ��  ��V1.0
+ * ��  ��  ��XuZhongPing
+ * ��  ��  ��2017/03/06 
+*********************************************************************************/
+#ifndef __MOTOR_H
+#define __MOTOR_H	 
+
+#include "stm32f10x.h"
+
+#define M1_OPEN_MAX_CurrentVal		3000
+#define M1_CLOSE_MAX_CurrentVal		3000
+
+#define M2_OPEN_MAX_CurrentVal		3000
+#define M2_CLOSE_MAX_CurrentVal		3000
+
+extern uint16_t motorCurrentVal_1;
+extern uint8_t motorRunningStatus_1; 
+
+extern uint16_t motorCurrentVal_2;
+extern uint8_t motorRunningStatus_2; 
+
+extern uint8_t motorRunningStatus_3;
+extern uint8_t motorRunningStatus_4;
+
+void MotorInit(void);
+void DoorOpen(uint8_t num);
+void DoorClose(uint8_t num);
+void DoorStop(uint8_t num);
+
+void Get_MotorCurrentVal(void);
+
+void MotorTest(void);
+
+#endif
+
+/******************** (C) COPYRIGHT 2017 YNHB *****END OF FILE*******************/
diff --git a/STM32_4路称重_Git提交精简工程/src/HARDWARE/NTC_ADC/adc.c b/STM32_4路称重_Git提交精简工程/src/HARDWARE/NTC_ADC/adc.c
new file mode 100755
index 0000000..cdbe05b
--- /dev/null
+++ b/STM32_4路称重_Git提交精简工程/src/HARDWARE/NTC_ADC/adc.c
@@ -0,0 +1,113 @@
+/*************************** (C) COPYRIGHT 2017 CXHY ****************************
+ * �ļ���  ��adc.c
+ * ��  ��  ��ADC��������
+ * ��  ��  ��V1.0
+ * ��  ��  ��XuZhongPing
+ * ��  ��  ��2017/04/30
+*********************************************************************************/
+#include "adc.h" 
+
+/*
+***********************************************************************
+*	�� �� ��: Adc_Init
+*	����˵��: ��ʼ��ADC		
+*	��    �Σ���
+*	�� �� ֵ: ��
+***********************************************************************
+*/															   
+void Adc_Init(void)
+{ 	
+	ADC_InitTypeDef ADC_InitStructure; 
+	GPIO_InitTypeDef GPIO_InitStructure;
+	RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOA | RCC_APB2Periph_GPIOC | RCC_APB2Periph_GPIOC | RCC_APB2Periph_ADC1, ENABLE);	  							//ʹ��ADC1ͨ��ʱ��
+ 
+	RCC_ADCCLKConfig(RCC_PCLK2_Div6);   																	//72M/6=12,ADC���ʱ�䲻�ܳ���14M
+	
+	//�ⲿ�¶ȼ��	
+	GPIO_InitStructure.GPIO_Pin = GPIO_Pin_4 | GPIO_Pin_5;
+	GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AIN;													//ģ����������
+	GPIO_Init(GPIOC, &GPIO_InitStructure);	
+	
+	//�����¶ȼ��
+	GPIO_InitStructure.GPIO_Pin = GPIO_Pin_4;
+	GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AIN;													//ģ����������
+	GPIO_Init(GPIOA, &GPIO_InitStructure);	
+	
+	//����������
+	GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_1;
+	GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AIN;													//ģ����������
+	GPIO_Init(GPIOB, &GPIO_InitStructure);	
+	
+	//������ADC����
+	GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_1;
+	GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AIN;													//ģ����������
+	GPIO_Init(GPIOC, &GPIO_InitStructure);	
+
+	ADC_DeInit(ADC1);  																										//������ ADC1 ��ȫ���Ĵ�������Ϊȱʡֵ
+
+	ADC_InitStructure.ADC_Mode = ADC_Mode_Independent;										//ADC����ģʽ:ADC1��ADC2�����ڶ���ģʽ
+	ADC_InitStructure.ADC_ScanConvMode = DISABLE;													//ģ��ת�������ڵ�ͨ��ģʽ
+	ADC_InitStructure.ADC_ContinuousConvMode = DISABLE;										//ģ��ת�������ڵ���ת��ģʽ
+	ADC_InitStructure.ADC_ExternalTrigConv = ADC_ExternalTrigConv_None;		//ת���������������ⲿ��������
+	ADC_InitStructure.ADC_DataAlign = ADC_DataAlign_Right;								//ADC�����Ҷ���
+	ADC_InitStructure.ADC_NbrOfChannel = 1;																//˳����й���ת����ADCͨ������Ŀ
+	ADC_Init(ADC1, &ADC_InitStructure);																		//����ADC_InitStruct��ָ���Ĳ�����ʼ������ADCx�ļĴ���   
+ 
+
+	ADC_Cmd(ADC1, ENABLE);														//ʹ��ָ����ADC1
+	
+	ADC_ResetCalibration(ADC1);												//����ָ����ADC1��У׼�Ĵ���
+	 
+	while(ADC_GetResetCalibrationStatus(ADC1));				//��ȡADC1����У׼�Ĵ�����״̬,����״̬��ȴ�
+	
+	ADC_StartCalibration(ADC1);												//��ʼָ��ADC1��У׼״̬
+ 
+	while(ADC_GetCalibrationStatus(ADC1));						//��ȡָ��ADC1��У׼����,����״̬��ȴ�
+ 
+	ADC_SoftwareStartConvCmd(ADC1, ENABLE);						//ʹ��ָ����ADC1������ת����������
+
+}				  
+
+/*
+***********************************************************************
+*	�� �� ��: Get_Adc
+*	����˵��: ���ADCֵ
+*	��    �Σ�ch:ͨ��ֵ 0~3
+*	�� �� ֵ: ��
+***********************************************************************
+*/
+uint16_t GetADC(uint8_t ch)   
+{
+  //����ָ��ADC�Ĺ�����ͨ�����������ǵ�ת��˳��Ͳ���ʱ��
+	ADC_RegularChannelConfig(ADC1, ch, 1, ADC_SampleTime_28Cycles5);
+//	ADC_RegularChannelConfig(ADC1, ch, 1, ADC_SampleTime_239Cycles5 );	//ADC1,ADCͨ��3,�������˳��ֵΪ1,����ʱ��Ϊ239.5����	  			    
+  
+	ADC_SoftwareStartConvCmd(ADC1, ENABLE);																//ʹ��ָ����ADC1������ת����������	
+	 
+	while(!ADC_GetFlagStatus(ADC1, ADC_FLAG_EOC));												//�ȴ�ת������
+
+	return ADC_GetConversionValue(ADC1);																	//�������һ��ADC1�������ת�����
+}
+
+/*
+***********************************************************************
+*	�� �� ��: Data_collection
+*	����˵��: ���ݲɼ�			
+*	��    �Σ�
+*       		x[]:��Ҫ����������
+*						n:�ɼ��Ĵ���
+*						ch:��ɼ���ͨ��
+*	�� �� ֵ: ��
+***********************************************************************
+*/
+void Data_collection(uint16_t x[], uint16_t n, uint8_t ch)
+{
+	uint8_t i;
+	
+	for(i=0; i<n; i++)
+	{
+		x[i] = GetADC(ch);     //���������ͻ���
+	}
+}
+
+/******************** (C) COPYRIGHT 2017 CXHY *****END OF FILE*******************/
diff --git a/STM32_4路称重_Git提交精简工程/src/HARDWARE/NTC_ADC/adc.h b/STM32_4路称重_Git提交精简工程/src/HARDWARE/NTC_ADC/adc.h
new file mode 100755
index 0000000..ee798a4
--- /dev/null
+++ b/STM32_4路称重_Git提交精简工程/src/HARDWARE/NTC_ADC/adc.h
@@ -0,0 +1,17 @@
+/*************************** (C) COPYRIGHT 2017 CXHY ****************************
+ * �ļ���  ��adc.j
+ * ��  ��  ��ADC��������
+ * ��  ��  ��V1.0
+ * ��  ��  ��XuZhongPing
+ * ��  ��  ��2017/04/30
+*********************************************************************************/
+#ifndef __ADC_H
+#define __ADC_H	
+#include "stm32f10x.h"
+ 
+void Adc_Init(void);
+uint16_t GetADC(uint8_t ch);  
+void Data_collection(uint16_t x[], uint16_t n, uint8_t ch);
+ 
+#endif 
+/******************** (C) COPYRIGHT 2017 CXHY *****END OF FILE*******************/
diff --git a/STM32_4路称重_Git提交精简工程/src/HARDWARE/NTC_ADC/ntc.c b/STM32_4路称重_Git提交精简工程/src/HARDWARE/NTC_ADC/ntc.c
new file mode 100755
index 0000000..a9117d1
--- /dev/null
+++ b/STM32_4路称重_Git提交精简工程/src/HARDWARE/NTC_ADC/ntc.c
@@ -0,0 +1,149 @@
+/*************************** (C) COPYRIGHT 2017 CXHY ****************************
+ * �ļ���  ��ntc.c
+ * ��  ��  ��NTC���������¶ȴ������������� 
+ * ��  ��  ��V1.0
+ * ��  ��  ��XuZhongPing
+ * ��  ��  ��2017/04/30
+*********************************************************************************/
+#include "ntc.h"
+#include "my_math.h"
+#include "timer.h"
+#include "delay.h"
+#include "ntc_10K_tab.h"
+#include "usart2.h"
+
+#define ADC_SIZE 20					      						//һ�βɼ�����ADֵ
+#define FILTER_SIZE 10					  						//�˲����
+
+uint16_t adc_buf[ADC_SIZE]; 		              //����ADC�ɼ���������
+		
+
+uint16_t NTC1_value = 0;											
+uint16_t NTC2_value = 0; 
+uint16_t NTC3_value = 0;	  									//��ͨ���ɼ����������ֵ
+					
+uint8_t temperature = 0;											//�¶�
+uint8_t temperature_A = 0;										//A·�¶�
+uint8_t temperature_B = 0;										//B·�¶�
+uint8_t temperature_C = 0;										//C·�¶�
+
+uint8_t fanRunningStatus = 0;									//������ת״̬
+
+
+/*
+***********************************************************************
+*	�� �� ��: data_input
+*	����˵��: �ɼ�n�����ݲ���������������ƽ��������	
+*	��    �Σ�
+*       		x[]:��Ҫ����������
+*						n:  �ɼ��Ĵ���
+*						ch: ��ɼ���ͨ��
+*	�� �� ֵ: ��
+***********************************************************************
+*/
+uint16_t data_input(uint16_t *p, uint16_t n, uint8_t ch)
+{
+	uint16_t x;
+	Data_collection(p, n, ch);			//�����ɼ�n������,�ݴ浽Pָ���ĵط�
+	sort_16(p, n);           				//�Դ��ڻ����еĲɼ����ݽ�������
+	x = average_16(p, n, 2);						//ȥ��ͷ��β����ƽ����
+	return x;
+}
+
+/*
+***********************************************************************
+*	�� �� ��: filter
+*	����˵��: �����˲�����			
+*	��    �Σ�
+*       		value -> ��Ҫ�˲���ֵ
+*						ch -> ��ɼ���ͨ��
+*	�� �� ֵ: �˲���Ľ��
+***********************************************************************
+*/
+uint16_t filter(uint16_t value, uint8_t ch) 
+{ 
+	uint8_t count=0; 
+	uint16_t new_value; 
+	new_value = data_input(adc_buf, ADC_SIZE, ch);   
+	while (value != new_value)
+	{ 
+		count++; 
+		if (count >= FILTER_SIZE) return new_value; 
+		new_value = data_input(adc_buf, ADC_SIZE, ch);
+	} 
+	return value; 
+}
+
+/*
+***********************************************************************
+*	�� �� ��: Get_NTC_values
+*	����˵��: ��ȡAD8,AD9�ɼ������������
+*	��    �Σ�	          
+*	�� �� ֵ: 
+***********************************************************************
+*/
+void Get_NTC_values(void)
+{
+	NTC1_value = filter(NTC1_value, ADC_Channel_14);
+	NTC2_value = filter(NTC2_value, ADC_Channel_15);
+	NTC3_value = filter(NTC3_value, ADC_Channel_4);
+// 	printf("\r\nNTC1_value = %d  NTC2_value = %d\r\n", NTC1_value, NTC2_value);
+}
+
+/*
+***********************************************************************
+*	�� �� ��: GetTemperatureTask
+*	����˵��: �¶Ȳɼ�����
+*	��    �Σ���	          
+*	�� �� ֵ: ��
+***********************************************************************
+*/
+void GetTemperatureTask(void)
+{
+	uint8_t i;
+	
+	static timer getTemperatureTimer;					//����ɼ�ʱ����
+	static timer waitingTimer;
+	
+	static uint8_t timer_ok = 0;
+	if(timer_ok == 0)
+	{
+		timer_ok = 1;
+		timer_set(&getTemperatureTimer, CLOCK_SECOND*10);
+		timer_set(&waitingTimer, CLOCK_SECOND*30);
+	}
+	
+	if(timer_expired(&getTemperatureTimer))		//ÿ10S�ɼ�һ���¶�
+	{
+		timer_restart(&getTemperatureTimer);
+		
+		
+// 		if((temperature_A > 0) || (temperature_B > 0) || (temperature_C > 0))
+// 		{
+// 			printf("\r\n�¶ȣ�No1 = %2.1f ��, No2 = %2.1f ��, No3 = %2.1f ��, Out = %2.1f ��\r\n", (float)temperature_A, (float)temperature_B, (float)temperature_C, (float)temperature);
+// 		}
+		
+// 		printf("\r\n�����¶ȣ�%2.1f ��\r\n", (float)temperature_C);
+		
+	}
+	
+	if(temperature_A > temperature_B){
+			temperature = temperature_A;
+	}else{
+		temperature = temperature_B;
+	}
+	
+	if(temperature < temperature_C)
+	{
+		temperature = temperature_C;
+	}
+	
+	if(timer_expired(&waitingTimer))
+	{
+		timer_restart(&waitingTimer);
+		
+		printf("\r\n�����¶ȣ�%2.1f ��\r\n", (float)temperature);
+	}
+}
+
+/******************** (C) COPYRIGHT 2017 CXHY *****END OF FILE*******************/
diff --git a/STM32_4路称重_Git提交精简工程/src/HARDWARE/NTC_ADC/ntc.h b/STM32_4路称重_Git提交精简工程/src/HARDWARE/NTC_ADC/ntc.h
new file mode 100755
index 0000000..8ed4538
--- /dev/null
+++ b/STM32_4路称重_Git提交精简工程/src/HARDWARE/NTC_ADC/ntc.h
@@ -0,0 +1,26 @@
+/*************************** (C) COPYRIGHT 2017 CXHY ****************************
+ * �ļ���  ��ntc.h
+ * ��  ��  ��NTC���������¶ȴ�������������ͷ�ļ�  
+ * ��  ��  ��V1.0
+ * ��  ��  ��XuZhongPing
+ * ��  ��  ��2017/04/30
+*********************************************************************************/
+#ifndef __ADC_INPUT_h
+#define __ADC_INPUT_h
+
+#include "adc.h"
+
+extern uint16_t NTC1_value, NTC2_value;	  					//��ͨ���ɼ����������ֵ
+
+extern uint8_t temperature;													//�¶�
+extern uint8_t temperature_A;												//A·�¶�
+extern uint8_t temperature_B;												//B·�¶�
+extern uint8_t temperature_C;												//B·�¶�
+
+
+void Get_NTC_values(void);			 										//��ȡ�������ɼ���������
+void GetTemperatureTask(void);											//�¶Ȳɼ�����
+
+#endif
+
+/******************** (C) COPYRIGHT 2017 CXHY *****END OF FILE*******************/
diff --git a/STM32_4路称重_Git提交精简工程/src/HARDWARE/NTC_ADC/ntc_10K_tab.h b/STM32_4路称重_Git提交精简工程/src/HARDWARE/NTC_ADC/ntc_10K_tab.h
new file mode 100755
index 0000000..61d6b7d
--- /dev/null
+++ b/STM32_4路称重_Git提交精简工程/src/HARDWARE/NTC_ADC/ntc_10K_tab.h
@@ -0,0 +1,31 @@
+/*************************** (C) COPYRIGHT 2017 CXHY ****************************
+ * �ļ���  ��ntc_10K_tab.h
+ * ��  ��  ��NTC���������ӦADCֵ��  
+ * ��  ��  ��V1.0
+ * ��  ��  ��XuZhongPing
+ * ��  ��  ��2017/04/30
+*********************************************************************************/
+#ifndef __NTC_10K_TAB_h
+#define __NTC_10K_TAB_h
+
+#include "stdint.h"
+
+#define TempSize  100 //���������
+
+const uint16_t TabNTC_10K[TempSize] = 
+{
+	2548,2498,2448,2398,2348,2297,2247,2197,2147,2097, 
+	2047,1998,1949,1900,1852,1805,1758,1711,1666,1620,
+	1576,1532,1489,1447,1406,1365,1326,1287,1249,1212,
+	1175,1140,1105,1072,1039,1007, 976, 945, 916, 887,
+	 859, 833, 806, 781, 756, 732, 709, 686, 665, 644,
+	 623, 603, 584, 565, 547, 530, 513, 497, 481, 466,
+	 451, 437, 423, 410, 397, 385, 372, 361, 350, 339,
+	 328, 318, 308, 299, 289, 281, 272, 264, 256, 248,
+	 241, 233, 226, 220, 213, 207, 201, 195, 189, 183,
+	 178, 173, 168, 163, 158, 154, 150, 145, 141, 137
+};
+
+#endif
+
+/******************** (C) COPYRIGHT 2017 CXHY *****END OF FILE*******************/
diff --git a/STM32_4路称重_Git提交精简工程/src/HARDWARE/OPTO_SWITCH/opto_sw_key.c b/STM32_4路称重_Git提交精简工程/src/HARDWARE/OPTO_SWITCH/opto_sw_key.c
new file mode 100755
index 0000000..8304874
--- /dev/null
+++ b/STM32_4路称重_Git提交精简工程/src/HARDWARE/OPTO_SWITCH/opto_sw_key.c
@@ -0,0 +1,367 @@
+/*************************** (C) COPYRIGHT 2017 CXHY ****************************
+ * �ļ���  ��opto_sw_key.c
+ * ��  ��  ����翪����������
+ * ��  ��  ��V1.0
+ * ��  ��  ��XuZhongPing
+ * ��  ��  ��2017/03/06 
+*********************************************************************************/
+#include "opto_sw_key.h"
+#include "delay.h"
+#include "timer.h"
+#include "device.h"
+#include "data_typedef.h"
+
+//�����翪��
+#define OPTO_KEY1_PORT				GPIOA						
+#define OPTO_KEY1_PIN					GPIO_Pin_8
+
+#define OPTO_KEY2_PORT				GPIOB					
+#define OPTO_KEY2_PIN					GPIO_Pin_7
+
+#define OPTO_KEY3_PORT				GPIOD					
+#define OPTO_KEY3_PIN					GPIO_Pin_0
+
+#define OPTO_KEY4_PORT				GPIOD				
+#define OPTO_KEY4_PIN					GPIO_Pin_3
+
+
+uint8_t optoKeyValue1 = 0;								//�����翪�ؼ�ֵ
+uint8_t optoKeyValue2 = 0;								//�����翪�ؼ�ֵ
+uint8_t optoKeyValue3 = 0;								//�����翪�ؼ�ֵ
+uint8_t optoKeyValue4 = 0;								//�����翪�ؼ�ֵ
+	
+/*
+***********************************************************************
+*	�� �� ��: OptoKeyInit
+*	����˵��: �����翪��IO�ڳ�ʼ��
+*	��    �Σ���
+*	�� �� ֵ: ��
+***********************************************************************
+*/
+void OptoKeyInit(void)
+{ 
+ 	GPIO_InitTypeDef GPIO_InitStructure;
+ 	RCC_APB2PeriphClockCmd(	RCC_APB2Periph_GPIOA | 
+													RCC_APB2Periph_GPIOB | 
+													RCC_APB2Periph_GPIOD, ENABLE);		//ʹ��PORTAʱ��
+	
+	//��һ·�����翪��IO������
+	GPIO_InitStructure.GPIO_Pin = OPTO_KEY1_PIN;			 				
+	GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU; 		 		
+	GPIO_Init(OPTO_KEY1_PORT, &GPIO_InitStructure);	
+	
+	//�ڶ�·�����翪��IO������
+	GPIO_InitStructure.GPIO_Pin = OPTO_KEY2_PIN;			 				
+	GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU; 		 			
+	GPIO_Init(OPTO_KEY2_PORT, &GPIO_InitStructure);	
+	
+	//����·�����翪��IO������
+	GPIO_InitStructure.GPIO_Pin = OPTO_KEY3_PIN;			 				
+	GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU; 		 		
+	GPIO_Init(OPTO_KEY3_PORT, &GPIO_InitStructure);	
+	
+	//����·�����翪��IO������
+	GPIO_InitStructure.GPIO_Pin = OPTO_KEY4_PIN;			 				
+	GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU; 		 		
+	GPIO_Init(OPTO_KEY4_PORT, &GPIO_InitStructure);	
+}
+
+/*
+***********************************************************************
+*	�� �� ��: OptoKeysCanning
+*	����˵��: �����翪�ؼ��
+*	��    �Σ���
+*	�� �� ֵ: ��
+***********************************************************************
+*/
+void OptoKeysCanning(void)
+{
+	static uint8_t key1_state = 0;
+	static uint8_t key2_state = 0;
+	
+	//��1·�����翪�ؼ��
+	switch (key1_state)
+	{
+		case 0x00:
+			if(OPTO_KEY1 == 0)
+			{
+				key1_state = 0x01;
+			}
+			break;
+			
+		case 0x01:
+			if(OPTO_KEY1 == 0)
+			{
+				optoKeyValue1 = 1;
+			}else{
+				optoKeyValue1 = 0;
+				key1_state = 0x00;
+			}
+			break;
+			
+		default:
+			key1_state = 0x00;
+			break;
+	}
+	
+	//��2·�����翪�ؼ��
+	switch (key2_state)
+	{
+		case 0x00:
+			if(OPTO_KEY2 == 0)
+			{
+				key2_state = 0x01;
+			}
+			break;
+			
+		case 0x01:
+			if(OPTO_KEY2 == 0)
+			{
+				optoKeyValue2 = 1;
+			}else{
+				optoKeyValue2 = 0;
+				key2_state = 0x00;
+			}
+			break;
+			
+		default:
+			key2_state = 0x00;
+			break;
+	}
+}
+
+/*
+***********************************************************************
+*	�� �� ��: BottleScanning
+*	����˵��: ƿ��Ͷ��ɨ����
+*	��    �Σ���
+*	�� �� ֵ: ���ض�Ӧ���صļ�ֵ
+***********************************************************************
+*/
+void BottleScanning(void)
+{
+	static uint8_t bottleType = 0;
+	static uint16_t count;
+	static uint8_t testStatus = 0x00;
+	
+	static timer timerOut;
+	static timer waitingTimer;
+	static timer wrongOperationTimer;
+	
+	static uint8_t timer_ok = 0;
+	
+	if(timer_ok == 0)
+	{
+		timer_ok = 1;
+		timer_set(&timerOut, 4);
+		timer_set(&waitingTimer, CLOCK_SECOND*5);
+		timer_set(&wrongOperationTimer, CLOCK_SECOND*3);
+	}
+	
+	switch(testStatus)
+	{
+		case 0x00:
+			if((OPTO_KEY3 == 1) && (OPTO_KEY4 == 0))
+			{
+// 				printf("\r\n�������\r\n");
+// 				printf("%d %d\r\n", OPTO_KEY3, OPTO_KEY4);
+				timer_restart(&wrongOperationTimer);
+				testStatus = 0x10;
+				break;
+			}
+			if((OPTO_KEY3 == 0) && (OPTO_KEY4 == 1))				//��⵽��ʼͶƿ
+			{
+// 				printf("\r\n��ʼͶƿ\r\n");
+// 				printf("%d %d\r\n", OPTO_KEY3, OPTO_KEY4);
+				timer_restart(&waitingTimer);
+				testStatus = 0x01;
+			}
+			break;
+			
+		case 0x01:		//�ȴ�ƿ�Ӿ�����һ�����̽ͷ
+			if(timer_expired(&waitingTimer))
+			{
+				printf("\r\n0x01Ͷ�ų�ʱ����\r\n");
+				testStatus = 0x00;
+				break;
+			}
+// 			if((OPTO_KEY3 == 0) || (OPTO_KEY4 == 0))
+// 			{
+// 				printf("%d %d\r\n", OPTO_KEY3, OPTO_KEY4);
+// 			}
+			if((OPTO_KEY3 == 0) && (OPTO_KEY4 == 0))				//����̽ͷͬʱ��⵽ƿ��˵��Ϊ��ƿ��
+			{
+				bottleType = 1;																									//��־Ϊ��ƿ��
+			}
+			if((OPTO_KEY3 == 1) && (OPTO_KEY4 == 0))				//�ȴ�ƿ����ȫͨ����һ��̽ͷ
+			{
+				timer_restart(&waitingTimer);
+				testStatus = 0x02;
+				break;
+			}
+			break;
+			
+		case 0x02:		//���ƿ����ȫͨ������̽ͷ��˵���Ѿ�����ͨ����ͨ����
+			if(timer_expired(&waitingTimer))
+			{
+				printf("\r\n0x02Ͷ�ų�ʱ����\r\n");
+				testStatus = 0x00;
+				break;
+			}
+			
+// 			if((OPTO_KEY3 == 0) || (OPTO_KEY4 == 0))
+// 			{
+// 				printf("%d %d\r\n", OPTO_KEY3, OPTO_KEY4);
+// 			}
+			if((OPTO_KEY3 == 0) && (OPTO_KEY4 == 0))				//����̽ͷͬʱ��⵽ƿ��˵��Ϊ��ƿ��
+			{
+				bottleType = 1;																									//��־Ϊ��ƿ��
+			}
+			if((OPTO_KEY3 == 1) && (OPTO_KEY4 == 1))
+			{
+				timer_restart(&timerOut);
+				timer_restart(&waitingTimer);
+				testStatus = 0x03;
+				break;
+			}
+			break;
+			
+		case 0x03:		//�ж��Ѿ���ȫͨ�����ͨ�������һС��ʱ���û�м�⵽ƿ��˵���Ѿ�Ͷ�ųɹ���
+			if(timer_expired(&timerOut))
+			{
+				if(timer_expired(&waitingTimer))
+				{
+					printf("\r\n0x03Ͷ�ų�ʱ����\r\n");
+					testStatus = 0x00;
+					break;
+				}
+			
+				if((OPTO_KEY3 == 1) || (OPTO_KEY4 == 1))			//ƿ���Ѿ���ȫ�뿪ͨ��
+				{
+					printf("\r\nͶ�ųɹ�������\r\n");
+					beep_shortBeepMark = 1;
+					
+					//Ŀǰֻ��Сƿ��������
+// 					if(bottleType)
+// 					{
+// 						bigBottleCount++;	
+// 					}else{
+// 						smallBottleCount++;
+// 					}
+					
+					smallBottleCount++;
+
+// 					printf("\r\n��ƿ�ӣ�������%d����Сƿ�ӣ�������%d��\r\n", bigBottleCount, smallBottleCount);
+					bottleType = 0;
+					testStatus = 0x00;
+					break;
+				}
+			}
+			break;
+			
+		case 0x10:		//�������
+			if(timer_expired(&wrongOperationTimer))
+			{
+				testStatus = 0x00;
+				printf("\r\nerror return!\r\n");
+				break;
+			}
+// 			if((OPTO_KEY3 == 0) || (OPTO_KEY4 == 0))
+// 			{
+// 				printf("%d %d\r\n", OPTO_KEY3, OPTO_KEY4);
+// 			}
+			if((OPTO_KEY3 == 0) && (OPTO_KEY4 == 1))
+			{
+				testStatus = 0x11;
+				timer_restart(&waitingTimer);
+				break;
+			}
+			break;
+			
+		case 0x11:	
+			if(timer_expired(&waitingTimer))
+				{
+					printf("\r\n0x11time out return!\r\n");
+					testStatus = 0x00;
+					break;
+				}
+// 			if((OPTO_KEY3 == 0) || (OPTO_KEY4 == 0))
+// 			{
+// 				printf("%d %d\r\n", OPTO_KEY3, OPTO_KEY4);
+// 			}
+			if((OPTO_KEY3 == 1) && (OPTO_KEY4 == 1))
+			{
+				timer_restart(&timerOut);
+				timer_restart(&waitingTimer);
+				testStatus = 0x12;
+				break;
+			}
+			break;
+		
+		case 0x12:
+			if(timer_expired(&timerOut))
+			{
+				if(timer_expired(&waitingTimer))
+				{
+					printf("\r\n0x12time out return!\r\n");
+					testStatus = 0x00;
+					break;
+				}
+				
+				if((OPTO_KEY3 == 1) || (OPTO_KEY4 == 1))
+				{
+					printf("\r\nwarning!\r\n");
+					beep_warningBeepMark = 1;							//��־������
+					
+					if(smallBottleCount > 0)
+					{
+						smallBottleCount--;
+					}
+					testStatus = 0x00;
+					break;
+				}
+			}
+			break;
+		default: break;
+	}
+}
+
+/*
+***********************************************************************
+*	�� �� ��: OptoKeysTest
+*	����˵��: �����翪�ز���
+*	��    ��:	��
+*	�� �� ֵ: ��
+***********************************************************************
+*/
+void OptoKeysTest(void)
+{
+	static uint8_t optoKeyStatus1 = 0;
+	static uint8_t optoKeyStatus2 = 0;
+	
+	if(optoKeyStatus1 != optoKeyValue1)
+	{
+		optoKeyStatus1 = optoKeyValue1;
+		
+		if(optoKeyValue1)
+		{
+			printf("\r\n�����翪��1����\r\n");
+		}else{
+			printf("\r\n�����翪��1�ָ�����\r\n");
+		}
+	}
+	
+	if(optoKeyStatus2 != optoKeyValue2)
+	{
+		optoKeyStatus2 = optoKeyValue2;
+		
+		if(optoKeyValue2)
+		{
+			printf("\r\n�����翪��2����\r\n");
+		}else{
+			printf("\r\n�����翪��2�ָ�����\r\n");
+		}
+	}
+}
+
+/******************** (C) COPYRIGHT 2018 Ping *****END OF FILE*******************/
diff --git a/STM32_4路称重_Git提交精简工程/src/HARDWARE/OPTO_SWITCH/opto_sw_key.h b/STM32_4路称重_Git提交精简工程/src/HARDWARE/OPTO_SWITCH/opto_sw_key.h
new file mode 100755
index 0000000..e3cdd16
--- /dev/null
+++ b/STM32_4路称重_Git提交精简工程/src/HARDWARE/OPTO_SWITCH/opto_sw_key.h
@@ -0,0 +1,30 @@
+/*************************** (C) COPYRIGHT 2018 Ping ****************************
+ * �ļ���  ��opto_sw_key.h
+ * ��  ��  ����翪�ؿ�����������ͷ�ļ�
+ * ��  ��  ��V1.0
+ * ��  ��  ��XuZhongPing
+ * ��  ��  ��2017/03/06 
+*********************************************************************************/
+#ifndef __OPTO_SW_KEY_H
+#define __OPTO_SW_KEY_H	 
+
+#include "stm32f10x.h"
+
+#define OPTO_KEY1				GPIO_ReadInputDataBit(GPIOA, GPIO_Pin_8)			//�����翪��1����
+#define OPTO_KEY2				GPIO_ReadInputDataBit(GPIOB, GPIO_Pin_7)			//�����翪��2����
+#define OPTO_KEY3				GPIO_ReadInputDataBit(GPIOD, GPIO_Pin_0)			//�����翪��3����
+#define OPTO_KEY4				GPIO_ReadInputDataBit(GPIOD, GPIO_Pin_3)			//�����翪��4����
+
+extern uint8_t optoKeyValue1;								//�����翪�ؼ�ֵ
+extern uint8_t optoKeyValue2;								//�����翪�ؼ�ֵ
+extern uint8_t optoKeyValue3;								//�����翪�ؼ�ֵ
+extern uint8_t optoKeyValue4;								//�����翪�ؼ�ֵ
+
+void OptoKeyInit(void);
+void OptoKeysCanning(void);
+void BottleScanning(void);
+void OptoKeysTest(void);
+
+#endif
+
+/******************** (C) COPYRIGHT 2018 Ping *****END OF FILE*******************/
diff --git a/STM32_4路称重_Git提交精简工程/src/HARDWARE/QR_Code/qr_code.c b/STM32_4路称重_Git提交精简工程/src/HARDWARE/QR_Code/qr_code.c
new file mode 100755
index 0000000..3785136
--- /dev/null
+++ b/STM32_4路称重_Git提交精简工程/src/HARDWARE/QR_Code/qr_code.c
@@ -0,0 +1,202 @@
+/*************************** (C) COPYRIGHT 2017 CXHY ****************************
+ * �ļ���  ��2code.c
+ * ��  ��  ����ά�봦������    
+ * ��  ��  ��V1.0
+ * ��  ��  ��XuZhongPing
+ * ��  ��  ��2017/03/06 
+*********************************************************************************/
+#include "qr_code.h"
+#include "usart1.h"
+#include "timer.h"
+#include "string.h"	 
+#include "RFID_IC.h"
+#include "my_math.h"
+
+//������Ч��ά��ʶ��ɹ���־״̬
+uint8_t sweep2CodeState = 0;			//ɨ���ά��״̬���ɹ���Ϊ1�����ⲿ�����ȡ�����		
+uint8_t scanBarCodeState = 0;			//ɨ����������������ά��״̬���ɹ���Ϊ1�����ⲿ�����ȡ�����		
+uint8_t scanLabelCodeState = 0;		//ɨ���ǩ��ά��״̬���ɹ���Ϊ1�����ⲿ�����ȡ�����		
+uint8_t scanIC_2CodeState = 0;		//ɨ��IC����ά�뿪��״̬���ɹ���Ϊ1�����ⲿ�����ȡ�����
+uint8_t devSetQrCodeState = 0;		//�������ö�ά��
+
+uint8_t codeBuf[128];							//�����ȡ������Ч��ά������
+uint8_t codeDataLength = 0;				//�����ȡ������Ч��ά�����ݳ���
+
+uint8_t IC_Code[17];							//IC����ά��
+uint8_t IC_HEX_Code[17];					//IC����ά��ʮ����������
+uint8_t IC_HEX_ID[9];
+
+uint8_t setParamCmd;							//���ò���ָ��
+uint8_t setParamCount;						//�����ĸ���
+char setParamList[16][16];				//���������б�
+
+/*
+***********************************************************************
+*	�� �� ��: DeleteStrEndingCode
+*	����˵��: ɾ���ַ�����β�Ļس�������
+*	��    �Σ����������ַ����׵�ַ
+*	�� �� ֵ: ��
+***********************************************************************
+*/
+static void DeleteStrEndingCode(char *pStr)
+{
+	uint16_t i = 0;
+	uint16_t len1 = 0, len2;
+	
+	len1 = strlen(pStr);
+	
+	for(i = 0; i < len1; i++)
+	{
+		if((*(pStr + i) == 0x0D) || ((*(pStr + i) == 0x0A)))
+		{
+			*(pStr + i) = '\0';
+		}
+	}
+	
+	len2 = strlen(pStr);
+	printf("\r\nqrLen %d, %d\r\n", len1, len2);
+}
+
+/*
+***********************************************************************
+*	�� �� ��: QR_CodeDecode_StandardFormat
+*	����˵��: ��׼��ʽ��ά�����ݽ���
+*	��    �Σ�pStr -> �������Ķ�ά��
+*						pCheckStr -> ������ʽ
+*	�� �� ֵ: ����ɹ�����1,ʧ�ܷ���0
+***********************************************************************
+*/
+uint8_t QR_CodeDecode_StandardFormat(char *pStr, char *pCheckStr)
+{
+	uint8_t returnMark = 0;
+	uint8_t i = 0;
+	uint8_t len = 0;
+	char *p;
+	char *pQRcode;							//���ϸ�ʽ�Ķ�ά��
+	
+	pQRcode = (char*)strstr((const char*)pStr, pCheckStr);
+	
+	if(pQRcode != NULL)
+	{
+		p = (char*)strstr((const char*)pQRcode, "=");								//ȡ���û���Ϣ
+		
+		if(p != NULL)
+		{
+			len = strlen(p + 1);																			//�����û���Ϣ����
+			if((len > 0) && (len <= 128))															//��Ϊ�û�APP��ά����ܴ���
+			{
+				codeDataLength = len;																		//�����û���Ϣ����
+				memset(codeBuf, 0x00, 128);
+				memcpy(codeBuf, p+1, codeDataLength);
+				
+				printf("\r\nLen:%d, data:%s\r\n", codeDataLength, codeBuf);
+				
+				returnMark = 1;																					//��־����ɹ�
+			}
+		}
+	}
+		
+	return returnMark;
+}
+
+/*
+***********************************************************************
+*	�� �� ��: QR_CodeDecode
+*	����˵��: ��ά�����ݽ���
+*	��    �Σ��������Ķ�ά��
+*	�� �� ֵ: �ޣ�Ӱ����Ӧ����Ч��ά���־λ��
+***********************************************************************
+*/
+void QR_CodeDecode(char *pStr)
+{
+	uint8_t i;
+	char *p;
+	
+	char *pAppQRcode;							//APP��ά��
+	char *pAppQRcode2;						//����APP��ά��
+	char *pBagQRcode;							//��������ά��
+	char *pBagQRcodeAtCD;					//�ɶ���������ά��
+	char *pIcCardQRcode;					//�ɶ�IC����ά��
+	char *pDevSetQRcode;					//�������ö�ά��
+	
+	uint8_t len = 0;
+	
+	uint32_t IC_HEX01, IC_HEX02;
+	uint8_t IC_HEX03, IC_HEX04;
+	
+	uint8_t successMark = 0;												//ɨ����Ч��־
+	
+// 	printf("\r\n2code = %s\r\n", (const char*)pStr);
+	
+	DeleteStrEndingCode(pStr);		//ȥ����ά�������ַ�����β�Ļس�������
+	
+// 	pAppQRcode = (char*)strstr((const char*)pStr, "www.kinglive.com.cn");
+// 	pAppQRcode2 = (char*)strstr((const char*)pStr, "zoomlion");
+// 	pBagQRcode = (char*)strstr((const char*)pStr, "YN");
+// 	pBagQRcodeAtCD = (char*)strstr((const char*)pStr, "yueng");
+// 	pIcCardQRcode = (char*)strstr((const char*)pStr, "510104");
+// 	
+	pDevSetQRcode = (char*)strstr((const char*)pStr, "devSet:");
+
+//---------------------------------------------------------------------------------------	
+	if(strlen(pStr) >= 128)
+	{
+		printf("\r\n�������ȣ�\r\n");
+	}else{
+		if(pDevSetQRcode != NULL)		//�������ö�ά��
+		{
+			len = strlen(pDevSetQRcode);																	//���㳤��
+
+			devSetQrCodeState = 1;																				//��־ɨ��������ά��ɹ�
+			successMark = 1;
+			
+			codeDataLength = len;																					//�����û���Ϣ����
+			memcpy(codeBuf, pDevSetQRcode, codeDataLength);
+			*(codeBuf+len) = '\0';
+			
+			printf("\r\n���ö�ά�룡\r\n");
+			printf("\r\ndata = %s\r\n", codeBuf);
+			printf("\r\ndataLen = %d\r\n", codeDataLength);
+		}if(QR_CodeDecode_StandardFormat(pStr, "https://www.wastereduction.gov.hk")){
+			printf("\r\n��ۿͻ���ά�룡\r\n");
+			
+			sweep2CodeState = 1;																	
+			successMark = 1;
+		}else{
+			len = strlen(pStr);
+			codeDataLength = len;
+			memset(codeBuf, 0x00, 128);
+			memcpy(codeBuf, pStr, codeDataLength);
+		
+			sweep2CodeState = 1;																		//��־Ϊ�û�APP��ά�뿪��
+			successMark = 1;
+		}
+	}
+//---------------------------------------------------------------------------------------
+	
+	if(successMark == 0)
+	{
+		printf("\r\n��Ч��ά�룡����\r\n");
+	}
+}
+
+// /*
+// ***********************************************************************
+// *	�� �� ��: Get2Code
+// *	����˵��: ȡ�����ݶ�ά������
+// *	��    �Σ���
+// *	�� �� ֵ: ��
+// ***********************************************************************
+// */
+// void Get2Code(void)
+// {
+// 	if(USART1_RX_STA & 0X8000)		//���յ�һ��������
+// 	{
+// 		QR_CodeDecode((char*)USART_RX_BUF);
+// 		
+// 		memset(USART_RX_BUF, 0x00, 128);														//�����������
+// 		USART1_RX_STA = 0;		   																			//������һ�ν���
+// 	}
+// }
+
+/******************** (C) COPYRIGHT 2017 CXHY *****END OF FILE*******************/
diff --git a/STM32_4路称重_Git提交精简工程/src/HARDWARE/QR_Code/qr_code.h b/STM32_4路称重_Git提交精简工程/src/HARDWARE/QR_Code/qr_code.h
new file mode 100755
index 0000000..789beb4
--- /dev/null
+++ b/STM32_4路称重_Git提交精简工程/src/HARDWARE/QR_Code/qr_code.h
@@ -0,0 +1,29 @@
+/*************************** (C) COPYRIGHT 2017 CXHY ****************************
+ * �ļ���  ��2code.h
+ * ��  ��  ������������    
+ * ��  ��  ��V1.0
+ * ��  ��  ��XuZhongPing
+ * ��  ��  ��2017/03/06 
+*********************************************************************************/
+#ifndef __2CODE_H
+#define __2CODE_H	 
+#include "stdint.h" 
+#include "string.h" 
+
+//������Ч��ά��ʶ��ɹ���־״̬
+extern uint8_t sweep2CodeState;						//ɨ���ά��״̬���ɹ���Ϊ1�����ⲿ�����ȡ�����
+extern uint8_t scanBarCodeState;					//ɨ����������������ά��״̬���ɹ���Ϊ1�����ⲿ�����ȡ�����		
+extern uint8_t scanLabelCodeState;				//ɨ���ǩ��ά��״̬���ɹ���Ϊ1�����ⲿ�����ȡ�����		
+extern uint8_t scanIC_2CodeState;					//ɨ��IC����ά�뿪��״̬���ɹ���Ϊ1�����ⲿ�����ȡ�����
+extern uint8_t devSetQrCodeState;					//�������ö�ά��
+
+extern uint8_t codeBuf[128];							//�����ȡ������Ч��ά������
+extern uint8_t codeDataLength;						//�����ȡ������Ч��ά�����ݳ���	
+
+extern uint8_t setParamCmd;								//���ò���ָ��
+extern uint8_t setParamCount;							//�����ĸ���
+extern char setParamList[16][16];					//���������б�
+
+void QR_CodeDecode(char *pStr);
+void Get2Code(void);
+#endif
diff --git a/STM32_4路称重_Git提交精简工程/src/HARDWARE/RFID/RFID_IC.c b/STM32_4路称重_Git提交精简工程/src/HARDWARE/RFID/RFID_IC.c
new file mode 100755
index 0000000..02f98c9
--- /dev/null
+++ b/STM32_4路称重_Git提交精简工程/src/HARDWARE/RFID/RFID_IC.c
@@ -0,0 +1,331 @@
+/*************************** (C) COPYRIGHT 2017 CXHY ****************************
+ * �ļ���  ��RFID_IC.c
+ * ��  ��  ��RFID_IC����������    
+ * ��  ��  ��V1.0
+ * ��  ��  ��XuZhongPing
+ * ��  ��  ��2017/03/06 
+*********************************************************************************/
+#include "RFID_IC.h"
+#include "rfid_decode_yn.h"
+#include "rfid_decode_yhk.h"
+#include "rfid_decode_zl.h"
+#include "delay.h"
+#include "usart1.h"
+#include "stdio.h"
+#include "string.h" 
+#include "stdlib.h" 
+#include "my_math.h"
+
+#define RFID_PW_CTRL_PORT_PeriphClock			RCC_APB2Periph_GPIOA | RCC_APB2Periph_AFIO
+#define RFID_PW_CTRL_PORT									GPIOA
+#define RFID_PW_CTRL_PIN									GPIO_Pin_15
+
+
+uint8_t RFID_ID[16] = {0};							//���RFID���ţ��մ�IC�����������������ݣ�ʮ�����Ʊ��棩
+uint8_t cardNumberBit[32] = {0};				//������������Ŀ��ţ�ʮ���Ʊ�ʾ��
+uint8_t cardNumberStr[33] = {0};				//������������Ŀ��ţ��ַ�����ʾ��
+uint8_t createCardNum[16] = {0};				//���ɵ�IC���ű�������
+uint8_t cardNumberLen = 0;							//IC�������ݳ���
+uint8_t RFID_state = 0;									//RFID_ICˢ��״̬������ˢ��1����ˢ����0����ˢ����2�����˿���
+
+uint8_t cardSetWorkMode = 0;						//IC��ģ�鹤��ģʽ
+uint8_t cardSetReadBlock = 0;						//IC��ģ���ȡ�Ŀ��
+uint8_t cardSetUploadMode = 0;					//IC�������ϴ�ģʽ
+
+uint8_t cardSetKeyA[6] = {0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF};				//IC����дKeyA
+uint8_t cardSetKeyCtrlBit[4] = {0xFF, 0x07, 0x80, 0x69};							//IC����д����λ
+uint8_t cardSetKeyB[6] = {0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF};				//IC����дKeyB
+
+uint8_t originalPassword[6] = {0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF};		//IC��ԭʼ����
+
+uint32_t cardNumberAreaCode = 0;				//IC�������ţ�ǰ6λ��
+uint32_t cardNumberSerialNum = 0;				//IC������ˮ�ţ���7-14λ��
+
+//IC��ģ��������
+uint8_t Cmd_WorkMode[8] = {0x03, 0x08, 0xC1, 0x20, 0x00, 0x00, 0x00, 0x00};
+uint8_t Cmd_SECRET_KEY[21] = {0x03, 0x15, 0xC3, 0x20, 0xFF, 0xFF, 0xFF, 0xFF, 	//����IC������ģ����Կ
+															0xFF, 0xFF, 0xFF, 0x07, 0x80, 0x69, 0xFF, 0xFF, 
+															0xFF, 0xFF, 0xFF, 0xFF, 0x1B};
+															
+uint8_t Cmd_Write_Block[23] = {0x01,0x17,0xA4,0x20,0x00,0x01,0x00,0x00,
+															0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+															0x00,0x00,0x00,0x00,0x00,0x00,0x00};							//д������
+															
+uint8_t Cmd_SectorEncryption[8] = {0x01, 0x08, 0xA5, 0x20, 0x00, 0x01, 0x00, 0x00};		//��������
+
+//����IC��ģ���������Ĭ�ϲ�����
+uint8_t YN_IC_MODE[8] = {0x03, 0x08, 0xC1, 0x20, 0x03, 0x09, 0x00, 0x1F};				//����IC������ģ�鹤��ģʽ
+uint8_t YN_SECRET_KEY[21] = {0x03, 0x15, 0xC3, 0x20, 0x7F, 0xFF, 0xFF, 0xFF, 		//����IC������ģ����Կ
+															0xFF, 0xFF, 0xFF, 0x07, 0x80, 0x69, 0x6F, 0xFF, 
+															0xFF, 0xFF, 0xFF, 0xFF, 0x0B};
+
+//����IC��ģ���������Ĭ�ϲ�����													
+uint8_t SET_IC_MODE[8] = {0x03, 0x08, 0xC1, 0x20, 0x03, 0x09, 0x00, 0x1F};				//����IC������ģ�鹤��ģʽ
+uint8_t SET_SECRET_KEY[21] = {0x03, 0x15, 0xC3, 0x20, 0x7F, 0xFF, 0xFF, 0xFF, 		//����IC������ģ����Կ
+															0xFF, 0xFF, 0xFF, 0x07, 0x80, 0x69, 0x6F, 0xFF, 
+															0xFF, 0xFF, 0xFF, 0xFF, 0x0B};
+
+//����IC��ģ�����
+// uint8_t SET_IC_MODE[8] = {0x03, 0x08, 0xC1, 0x20, 0x03, 0x02, 0x00, 0x14};			//����IC������ģ�鹤��ģʽ
+// uint8_t SET_SECRET_KEY[21] = {0x03, 0x15, 0xC3, 0x20, 0xFF, 0xFF, 0xFF, 0xFF, 	//����IC������ģ����Կ
+// 															0xFF, 0xFF, 0xFF, 0x07, 0x80, 0x69, 0xFF, 0xFF, 
+// 															0xFF, 0xFF, 0xFF, 0xFF, 0x1B};
+
+// //�ɶ�										
+// uint8_t SET_IC_MODE[8] = {0x03, 0x08, 0xC1, 0x20, 0x03, 0x16, 0x00, 0x00};			//����IC������ģ�鹤��ģʽ
+// uint8_t SET_SECRET_KEY[21] = {0x03, 0x15, 0xC3, 0x20, 0x8F, 0x7F, 0x6F, 0x5F, 	//����IC������ģ����Կ
+// 															0x4F, 0x3F, 0xFF, 0x07, 0x80, 0x69, 0x1F, 0x2F, 
+// 															0x3F, 0x4F, 0x5F, 0x6F, 0xDB};
+
+void showCardHex(uint8_t *buf, uint8_t len)
+{
+	uint8_t i;
+	
+	printf("\r\n");
+	for(i=0; i<len; i++)
+	{
+		printf("%02X ",buf[i]);
+	}
+	printf("\r\n");
+}
+
+/*
+***********************************************************************
+*	�� �� ��: RFID_Init
+*	����˵��: RFID�豸��ʼ��
+*	��    �Σ���
+*	�� �� ֵ: ��
+***********************************************************************
+*/
+void RFID_Init(void)
+{ 
+ 	GPIO_InitTypeDef GPIO_InitStructure;
+ 	RCC_APB2PeriphClockCmd(RFID_PW_CTRL_PORT_PeriphClock, ENABLE);
+
+	GPIO_InitStructure.GPIO_Pin = RFID_PW_CTRL_PIN;				 				
+	GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP;
+	GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
+	GPIO_Init(RFID_PW_CTRL_PORT, &GPIO_InitStructure);
+	
+	GPIO_SetBits(RFID_PW_CTRL_PORT, RFID_PW_CTRL_PIN);
+}
+
+/*
+***********************************************************************
+*	�� �� ��: RFID_PowerON
+*	����˵��: ��RFID�豸��Դ
+*	��    �Σ���
+*	�� �� ֵ: ��
+***********************************************************************
+*/
+void RFID_PowerON(void)
+{
+	GPIO_SetBits(RFID_PW_CTRL_PORT, RFID_PW_CTRL_PIN);
+}
+
+/*
+***********************************************************************
+*	�� �� ��: RFID_PowerOFF
+*	����˵��: �ر�RFID�豸��Դ
+*	��    �Σ���
+*	�� �� ֵ: ��
+***********************************************************************
+*/
+void RFID_PowerOFF(void)
+{
+	GPIO_ResetBits(RFID_PW_CTRL_PORT, RFID_PW_CTRL_PIN);
+}
+
+/*
+***********************************************************************
+*	�� �� ��: IC_CardDecode
+*	����˵��: IC������
+*	��    �Σ���
+*	�� �� ֵ: ��
+***********************************************************************
+*/
+void IC_CardDecode(void)
+{
+	if(IC_CardDecode_YN())
+	{
+		printf("\r\n����IC����\r\n");
+	}else if(IC_CardDecode_YHK()){
+		printf("\r\n���п���\r\n");
+	}else if(IC_CardDecode_ZL()){
+		printf("\r\n����IC����\r\n");
+	}else{
+		printf("\r\n��Ч����\r\n");
+	}
+}
+
+
+//-------------------------------------------------------------------------------------
+//IC��ģ����ز���
+
+void TxCheckSum(uint8_t *ptr, uint8_t len)
+{
+	uint8_t i = 0;
+	uint8_t checksum = 0;
+
+	checksum = 0;
+	for(i=0; i<(len-1); i++)
+	{
+		checksum ^= ptr[i];
+	}
+	checksum = ~checksum;
+	ptr[len-1] = checksum;
+}
+
+/*
+***********************************************************************
+*	�� �� ��: IC_CardReset
+*	����˵��: ICģ������ָ�����Ĭ��ֵ
+*	��    �Σ���
+*	�� �� ֵ: ��
+***********************************************************************
+*/
+void IC_CarderReset(void)
+{
+	delay_ms(300);
+	USART1_SendFrameData(YN_IC_MODE, 8);
+	delay_ms(300);
+	USART1_SendFrameData(YN_SECRET_KEY, 21);
+	delay_ms(300);
+}
+
+/*
+***********************************************************************
+*	�� �� ��: IC_CardWorkModeSet
+*	����˵��: ICģ�鹤��ģʽ����
+*	��    �Σ�mode -> ����ģʽ
+*						block -> ��ȡ�Ŀ��
+*						outputMode -> ���ģʽ
+*	�� �� ֵ: ��
+***********************************************************************
+*/
+void IC_CarderWorkModeSet(uint8_t mode, uint8_t block, uint8_t outputMode)
+{	
+	Cmd_WorkMode[4] = mode;
+	Cmd_WorkMode[5] = block;
+	Cmd_WorkMode[6] = outputMode;
+	TxCheckSum(Cmd_WorkMode, 8);
+	
+	delay_ms(300);
+	USART1_SendFrameData(Cmd_WorkMode, 8);
+	delay_ms(300);
+}
+
+/*
+***********************************************************************
+*	�� �� ��: IC_CarderWorkModeSet
+*	����˵��: ICģ���д��������
+*	��    �Σ�keyA -> keyA����
+*						keyCtrlBit -> �������λ
+*						keyB -> keyB����
+*	�� �� ֵ: ��
+***********************************************************************
+*/
+void IC_CarderKeySet(uint8_t *keyA, uint8_t *keyCtrlBit, uint8_t *keyB)
+{	
+	memcpy(&Cmd_SECRET_KEY[4], keyA, 6);
+	memcpy(&Cmd_SECRET_KEY[10], keyCtrlBit, 4);
+	memcpy(&Cmd_SECRET_KEY[14], keyA, 6);
+	TxCheckSum(Cmd_SECRET_KEY, 21);
+	
+	delay_ms(300);
+	USART1_SendFrameData(Cmd_SECRET_KEY, 21);
+	delay_ms(300);
+}
+
+/*
+***********************************************************************
+*	�� �� ��: RFID_SectorEncrypt
+*	����˵��: ��������
+*	��    �Σ�blockNumber -> �������
+*	�� �� ֵ: ��
+***********************************************************************
+*/
+void RFID_SectorEncrypt(uint8_t blockNumber)
+{
+	Cmd_SectorEncryption[4] = blockNumber;
+	TxCheckSum(Cmd_SectorEncryption, Cmd_SectorEncryption[1]);	//��������У��λ
+	
+	delay_ms(500);
+	USART1_SendFrameData(Cmd_SectorEncryption, Cmd_SectorEncryption[1]);
+	delay_ms(500);
+}
+
+/*
+***********************************************************************
+*	�� �� ��: RFID_WriteDataToBlock
+*	����˵��: д������
+*	��    �Σ���
+*	�� �� ֵ: ��
+***********************************************************************
+*/
+void RFID_WriteDataToBlock(uint8_t *datain, uint8_t block)
+{
+	uint8_t i;
+	
+	Cmd_Write_Block[4] = block;
+	
+	for(i=0; i<16; i++)
+	{
+		Cmd_Write_Block[6+i] = datain[i];
+	}
+	TxCheckSum(Cmd_Write_Block, Cmd_Write_Block[1]);	//��������У��λ
+	
+	delay_ms(500);
+	USART1_SendFrameData(Cmd_Write_Block, Cmd_Write_Block[1]);
+	delay_ms(500);
+}
+
+/*
+***********************************************************************
+*	�� �� ��: SetRFID_Param
+*	����˵��: ����IC��ģ�����
+*	��    �Σ���
+*	�� �� ֵ: ��
+***********************************************************************
+*/
+void SetRFID_Param(void)
+{
+	delay_ms(200);
+	USART1_SendFrameData(SET_IC_MODE, 8);
+	delay_ms(200);
+	USART1_SendFrameData(SET_SECRET_KEY, 21);
+	delay_ms(200);
+}
+
+/*
+***********************************************************************
+*	�� �� ��: ConfigureDoorKey
+*	����˵��: ��������IC��Կ��
+*	��    �Σ���
+*	�� �� ֵ: ��
+***********************************************************************
+*/
+void ConfigureDoorKey(uint32_t id)
+{
+	IC_CardEncode_YN(id, 1, 55);
+	RFID_WriteDataToBlock(createCardNum, 9);
+	printf("\r\n��������IC��Կ�ף�\r\n");
+}
+
+/*
+***********************************************************************
+*	�� �� ��: WriteIC_CardNumber
+*	����˵��: дIC����
+*	��    �Σ�areaCode -> IC�����ţ�ǰ6λ��
+*						serialNum -> IC����ˮ�ţ���7-14λ��
+*	�� �� ֵ: ��
+***********************************************************************
+*/
+void WriteIC_CardNumber(uint32_t areaCode, uint32_t serialNum)
+{
+	IC_CardEncode_YN(areaCode, serialNum, 1);
+	RFID_WriteDataToBlock(createCardNum, 9);
+	printf("\r\nдIC����\r\n");
+}
+
+/******************** (C) COPYRIGHT 2017 ping *****END OF FILE*******************/
diff --git a/STM32_4路称重_Git提交精简工程/src/HARDWARE/RFID/RFID_IC.h b/STM32_4路称重_Git提交精简工程/src/HARDWARE/RFID/RFID_IC.h
new file mode 100755
index 0000000..da76162
--- /dev/null
+++ b/STM32_4路称重_Git提交精简工程/src/HARDWARE/RFID/RFID_IC.h
@@ -0,0 +1,47 @@
+/*************************** (C) COPYRIGHT 2017 CXHY ****************************
+ * �ļ���  ��RFID_IC.h
+ * ��  ��  ��RFID_IC����������    
+ * ��  ��  ��V1.0
+ * ��  ��  ��XuZhongPing
+ * ��  ��  ��2017/03/06 
+*********************************************************************************/
+#ifndef __RFID_IC_H
+#define __RFID_IC_H	
+#include "stm32f10x.h"
+
+extern uint8_t RFID_ID[16];						//���RFID���ţ��մ�IC�����������������ݣ�ʮ�����Ʊ��棩
+extern uint8_t cardNumberBit[32];			//������������Ŀ��ţ�ʮ���Ʊ�ʾ��
+extern uint8_t cardNumberStr[33];			//������������Ŀ��ţ��ַ�����ʾ��
+extern uint8_t createCardNum[16];			//���ɵ�IC���ű�������
+extern uint8_t cardNumberLen;					//IC�������ݳ���
+extern uint8_t RFID_state;						//RFID_ICˢ��״̬������ˢ��1����ˢ����0����ˢ����
+
+extern uint8_t cardSetWorkMode;				//IC��ģ�鹤��ģʽ
+extern uint8_t cardSetReadBlock;			//IC��ģ���ȡ�Ŀ��
+extern uint8_t cardSetUploadMode;			//IC�������ϴ�ģʽ
+
+extern uint8_t cardSetKeyA[6];				//IC����дKeyA
+extern uint8_t cardSetKeyCtrlBit[4];	//IC����д����λ
+extern uint8_t cardSetKeyB[6];				//IC����дKeyB
+
+extern uint8_t originalPassword[6];		//IC��ԭʼ����
+
+extern uint32_t cardNumberAreaCode;		//IC�������ţ�ǰ6λ��
+extern uint32_t cardNumberSerialNum;	//IC������ˮ�ţ���7-14λ��
+
+void RFID_Init(void);
+void RFID_PowerON(void);
+void RFID_PowerOFF(void);
+void IC_CardDecode(void);
+
+void IC_CarderReset(void);
+void IC_CarderWorkModeSet(uint8_t mode, uint8_t block, uint8_t outputMode);
+void IC_CarderKeySet(uint8_t *keyA, uint8_t *keyCtrlBit, uint8_t *keyB);
+void RFID_SectorEncrypt(uint8_t blockNumber);
+void RFID_WriteDataToBlock(uint8_t *datain, uint8_t block);
+void SetRFID_Param(void);
+void ConfigureDoorKey(uint32_t id);
+void WriteIC_CardNumber(uint32_t areaCode, uint32_t serialNum);
+#endif
+
+/******************** (C) COPYRIGHT 2017 CXHY *****END OF FILE*******************/
diff --git a/STM32_4路称重_Git提交精简工程/src/HARDWARE/RFID/rfid_decode_yhk.c b/STM32_4路称重_Git提交精简工程/src/HARDWARE/RFID/rfid_decode_yhk.c
new file mode 100755
index 0000000..003f997
--- /dev/null
+++ b/STM32_4路称重_Git提交精简工程/src/HARDWARE/RFID/rfid_decode_yhk.c
@@ -0,0 +1,127 @@
+/*************************** (C) COPYRIGHT 2017 CXHY ****************************
+ * �ļ���  ��rfid_decode_yhk.c
+ * ��  ��  �����п��������
+ * ��  ��  ��V1.0
+ * ��  ��  ��XuZhongPing
+ * ��  ��  ��2017/03/06 
+*********************************************************************************/
+#include "rfid_decode_yhk.h"
+#include "RFID_IC.h"
+#include "string.h" 
+#include "stdlib.h" 
+#include "stdbool.h"
+#include "my_math.h"
+#include "data_typedef.h"
+
+
+void showBufHex1(uint8_t *buf, uint8_t len)
+{
+	uint8_t i;
+	
+	printf("\r\n");
+	for(i=0; i<len; i++)
+	{
+		printf("%02X ",buf[i]);
+	}
+	printf("\r\n");
+}
+
+/*
+***********************************************************************
+*	�� �� ��: CheckLuhn
+*	����˵��: ��⿨��У��λ
+*	��    �Σ���
+*	�� �� ֵ: ��
+***********************************************************************
+*/
+static bool CheckLuhn(const char *pPurported)
+{
+	uint8_t i = 0;
+	int nSum = 0;
+	int nDigit = 0;
+	int nDigits = 0;
+	int nParity = 0;
+	char cDigit[2] = {0};
+	
+	nDigits = strlen(pPurported);
+	nParity = (nDigits-1) % 2;
+	
+	for (i = nDigits; i > 0 ; i--)
+	{
+		cDigit[0]  = pPurported[i-1];
+		nDigit = atoi(cDigit);
+
+		if (nParity == i % 2)
+		{
+			nDigit = nDigit * 2;
+		}
+
+		nSum += nDigit/10;
+		nSum += nDigit%10;
+	}
+	return 0 == nSum % 10;
+}
+	
+/*
+***********************************************************************
+*	�� �� ��: IC_CardDecode_YHK
+*	����˵��: ����IC������
+*	��    �Σ���
+*	�� �� ֵ: ����ɹ�����1�����ɹ�����0
+***********************************************************************
+*/
+uint8_t IC_CardDecode_YHK(void)
+{
+	uint8_t res = 0;
+	uint8_t i, j;
+	uint32_t dataTemp;
+	uint8_t icCardBitBuf[32] = {0};
+	uint8_t icCardLen = 0;				//�������ݳ���
+	uint32_t supplierID = 0;			//��Ӧ�̴���
+	
+	//���ŷ���
+	//���ŷ���
+	j = 0;
+	memset(cardNumberStr, 0x00, 33);
+	memset(cardNumberBit, 0x00, 32);
+	for(i = 0; i < 16; i++)
+	{
+		sprintf((char*)&cardNumberStr[j], "%01X", RFID_ID[i] >> 4);
+		cardNumberBit[j++] = RFID_ID[i] >> 4;
+		
+		sprintf((char*)&cardNumberStr[j], "%01X", RFID_ID[i] & 0x0F);
+		cardNumberBit[j++] = RFID_ID[i] & 0x0F;
+	}
+	
+	//���㿨�ų���
+	for(i = 0; i < 32; i++)
+	{
+		if(cardNumberStr[i] == 'F')
+		{
+			cardNumberLen = i;
+			break;
+		}
+	}
+	
+	printf("\r\nlen = %d\r\n", cardNumberLen);
+	showBufHex1(cardNumberBit, cardNumberLen);
+	printf("\r\nIC = %s\r\n", cardNumberStr);
+	
+	if((cardNumberLen >= 10) && (cardNumberLen <= 20))		//IC��ͷ����ϢУ��
+	{
+		memcpy(icCardBitBuf, cardNumberStr, cardNumberLen);
+		if(CheckLuhn((const char*)icCardBitBuf))
+		{
+			RFID_state = 3;						//RFID_ICˢ��״̬
+			printf("\r\n���п��û���\r\n");
+			res = 1;
+		}else{
+			printf("\r\nУ�����\r\n");
+		}
+	}else{
+// 		printf("\r\n������������Ч������\r\n");
+	}
+	
+	return res;
+}
+/******************** (C) COPYRIGHT 2017 ping *****END OF FILE*******************/
diff --git a/STM32_4路称重_Git提交精简工程/src/HARDWARE/RFID/rfid_decode_yhk.h b/STM32_4路称重_Git提交精简工程/src/HARDWARE/RFID/rfid_decode_yhk.h
new file mode 100755
index 0000000..8110ed6
--- /dev/null
+++ b/STM32_4路称重_Git提交精简工程/src/HARDWARE/RFID/rfid_decode_yhk.h
@@ -0,0 +1,16 @@
+/*************************** (C) COPYRIGHT 2017 CXHY ****************************
+ * �ļ���  ��rfid_decode_yhk.h
+ * ��  ��  �����п�����ͷ�ļ�
+ * ��  ��  ��V1.0
+ * ��  ��  ��XuZhongPing
+ * ��  ��  ��2017/03/06 
+*********************************************************************************/
+#ifndef __RFID_DECODE_YHK_H
+#define __RFID_DECODE_YHK_H	
+
+#include "stm32f10x.h"
+
+uint8_t IC_CardDecode_YHK(void);
+#endif
+
+/******************** (C) COPYRIGHT 2017 CXHY *****END OF FILE*******************/
diff --git a/STM32_4路称重_Git提交精简工程/src/HARDWARE/RFID/rfid_decode_yn.c b/STM32_4路称重_Git提交精简工程/src/HARDWARE/RFID/rfid_decode_yn.c
new file mode 100755
index 0000000..8cc7e8f
--- /dev/null
+++ b/STM32_4路称重_Git提交精简工程/src/HARDWARE/RFID/rfid_decode_yn.c
@@ -0,0 +1,259 @@
+/*************************** (C) COPYRIGHT 2017 CXHY ****************************
+ * �ļ���  ��RFID_IC.c
+ * ��  ��  ��RFID_IC����������    
+ * ��  ��  ��V1.0
+ * ��  ��  ��XuZhongPing
+ * ��  ��  ��2017/03/06 
+*********************************************************************************/
+#include "rfid_decode_yn.h"
+#include "RFID_IC.h"
+#include "string.h" 
+#include "stdlib.h" 
+#include "my_math.h"
+#include "data_typedef.h"
+
+#define secretKey "1357975312468642"				//IC������Կ1357975312468642
+// #define secretKey "2468642135797531"				//IC������Կ2468642135797531
+
+uint8_t secretKeyBit[16];					//���������16λʮ������Կ
+uint8_t checkBit;									//����У��λ
+
+
+static void SecretCardNumHEX2Bit(uint8_t outputBuf[], uint8_t inputBuf[]);
+
+
+void showCardHex1(uint8_t *buf, uint8_t len)
+{
+	uint8_t i;
+	
+	printf("\r\n");
+	for(i=0; i<len; i++)
+	{
+		printf("%02X ",buf[i]);
+	}
+	printf("\r\n");
+}
+
+/*
+***********************************************************************
+*	�� �� ��: SecretCardNumHEX2Bit
+*	����˵��: 16���ƿ��ŷ����17λ10������
+*	��    �Σ���
+*	�� �� ֵ: ��
+***********************************************************************
+*/
+static void SecretCardNumHEX2Bit(uint8_t outputBuf[], uint8_t inputBuf[])
+{
+	uint8_t i;
+	uint32_t dataTemp;
+	
+	//����
+	dataTemp = inputBuf[0] << 16;
+	dataTemp |= inputBuf[1] << 8;
+	dataTemp |= inputBuf[2];	
+	
+	//��������
+	outputBuf[0] = dataTemp/Pow(10, 5);
+	outputBuf[1] = (dataTemp/Pow(10, 4))%10;
+	outputBuf[2] = (dataTemp/Pow(10, 3))%10;
+	outputBuf[3] = (dataTemp/Pow(10, 2))%10;
+	outputBuf[4] = (dataTemp/Pow(10, 1))%10;
+	outputBuf[5] = (dataTemp%10);
+	
+// 		printf("\r\n%6d", dataTemp);
+	
+	//��ˮ��
+	dataTemp = inputBuf[3] << 24;
+	dataTemp |= inputBuf[4] << 16;
+	dataTemp |= inputBuf[5] << 8;
+	dataTemp |= inputBuf[6];		
+	
+// 		printf("%8d", dataTemp);
+	
+	//�������ˮ��
+	outputBuf[6] = dataTemp/Pow(10, 7);
+	outputBuf[7] = (dataTemp/Pow(10, 6))%10;
+	outputBuf[8] = (dataTemp/Pow(10, 5))%10;
+	outputBuf[9] = (dataTemp/Pow(10, 4))%10;
+	outputBuf[10] = (dataTemp/Pow(10, 3))%10;
+	outputBuf[11] = (dataTemp/Pow(10, 2))%10;
+	outputBuf[12] = (dataTemp/Pow(10, 1))%10;
+	outputBuf[13] = (dataTemp%10);
+	
+	//�����Ԥ����
+	outputBuf[14] = inputBuf[7]/10;
+	outputBuf[15] = inputBuf[7]%10;
+	
+// 		printf("%2d", inputBuf[7]);
+	
+	//�����У��λ
+	outputBuf[16] = (inputBuf[8]%10);
+
+// 		printf("%1d", inputBuf[8]);	
+	
+// 	printf("\r\n����Ϊ��");
+// 	for(i = 0; i < 17; i++)
+// 	{
+// 		printf("%d ", outputBuf[i]);
+// 	}
+// 	printf("\r\n");
+}
+
+/*
+***********************************************************************
+*	�� �� ��: SecretKeyHEX2Bit
+*	����˵��: 16������Կ�����16λ10������
+*	��    �Σ���
+*	�� �� ֵ: ��
+***********************************************************************
+*/
+void SecretKeyHEX2Bit(uint8_t outputBuf[], char *inputStr)
+{
+	uint16_t i;
+	char keyStr[17];
+	
+	sprintf(keyStr, "%s", inputStr);
+	
+// 	printf("\r\n��ԿΪ��");
+	for(i = 0; i < 16; i++)
+	{
+		outputBuf[i] = keyStr[i] - '0';
+// 		printf("%d ", outputBuf[i]);
+	}
+// 	printf("\r\n");
+}
+
+/*
+***********************************************************************
+*	�� �� ��: CalculateCheckDigit
+*	����˵��: ���㿨��У��λ
+*	��    �Σ���
+*	�� �� ֵ: ��
+***********************************************************************
+*/
+uint8_t CalculateCheckDigit(uint8_t cardNumBit[], uint8_t keyBit[])
+{
+	uint8_t crc = 0;
+	uint16_t i;
+	uint16_t encryptionSum = 0;
+	uint16_t sum = 0;
+	uint8_t remainder = 0;
+	
+	//����У��λ
+	for(i = 0; i < 16; i++)
+	{
+		sum = cardNumBit[i] * keyBit[i];
+		encryptionSum += sum;
+	}
+// 		printf("\r\n%d \r\n", encryptionSum);
+	remainder = encryptionSum % 11;
+// 		printf("\r\n%d \r\n", remainder);
+	
+	if(remainder == 10)
+	{
+		crc = 0;
+	}else if(remainder == 0){
+		crc = 5;
+	}else{
+		crc = remainder;
+	}
+	
+// 	printf("\r\nIC��У����Ϣ��У��� = %d, ���� = %d, У��λ = %d\r\n", encryptionSum, remainder, crc);
+		
+	return crc;
+}
+
+/*
+***********************************************************************
+*	�� �� ��: IC_CardEncode
+*	����˵��: IC������
+*	��    �Σ���
+*	�� �� ֵ: ��
+***********************************************************************
+*/
+void IC_CardEncode_YN(uint32_t areaCode, uint32_t serialNum, uint8_t cardType)
+{
+	uint8_t i;
+	uint8_t cardNumBitBuf[17];				//���ŷ��������17λʮ�������ݣ����ڼ���У��λ
+	uint8_t checkBit = 0;
+
+	memset(createCardNum, 0, 16);
+	
+	//���������
+	createCardNum[0] = (uint8_t)(areaCode >> 16);
+	createCardNum[1] = (uint8_t)(areaCode >> 8);
+	createCardNum[2] = (uint8_t)areaCode;
+	
+	//������ˮ��
+	createCardNum[3] = (uint8_t)(serialNum >> 24);
+	createCardNum[4] = (uint8_t)(serialNum >> 16);
+	createCardNum[5] = (uint8_t)(serialNum >> 8);
+	createCardNum[6] = (uint8_t)serialNum;
+	
+	//���ɿ�����
+	createCardNum[7] = cardType;
+	
+	//����У��λ
+	SecretCardNumHEX2Bit(cardNumBitBuf, createCardNum);
+	SecretKeyHEX2Bit(secretKeyBit, secretKey);
+	checkBit = CalculateCheckDigit(cardNumBitBuf, secretKeyBit);
+	createCardNum[8] = checkBit;
+	cardNumBitBuf[16] = checkBit;
+	
+	printf("\r\n���ɿ���Ϊ��");
+	for(i = 0; i < 17; i++)
+	{
+		printf("%d", cardNumBitBuf[i]);
+	}
+	printf("\r\n");
+}
+
+/*
+***********************************************************************
+*	�� �� ��: IC_CardDecode_YN
+*	����˵��: ����IC������
+*	��    �Σ���
+*	�� �� ֵ: ����ɹ�����1�����ɹ�����0
+***********************************************************************
+*/
+uint8_t IC_CardDecode_YN(void)
+{
+	uint8_t res = 0;
+	uint8_t i;
+	uint8_t checkBit;
+	
+	SecretCardNumHEX2Bit(cardNumberBit, RFID_ID);
+	SecretKeyHEX2Bit(secretKeyBit, secretKey);
+	checkBit = CalculateCheckDigit(cardNumberBit, secretKeyBit);
+	
+	if(checkBit == cardNumberBit[16])		//IC����У����ȷ�����־ˢ����Ч
+	{
+		printf("\r\nIC���ţ�");
+		for(i = 0; i < 17; i++)
+		{
+			cardNumberStr[i] = cardNumberBit[i] + '0';
+			printf("%d", cardNumberBit[i]);
+		}
+		printf("\r\n");
+	
+		if((cardNumberBit[14] == 0) && (cardNumberBit[15] == 1))
+		{
+			RFID_state = 1;						//RFID_ICˢ��״̬������ˢ����1->��ˢ����0->��ˢ����2->���ſ����ⲿ�����ȡ�����
+			printf("\r\nIC����Ч���û���������\r\n");
+			res = 1;
+		}else if((cardNumberBit[14] == 5) && (cardNumberBit[15] == 5)){
+			RFID_state = 2;						//RFID_ICˢ��״̬������ˢ����1->��ˢ����0->��ˢ����2->���ſ����ⲿ�����ȡ�����
+			printf("\r\nIC����Ч�����˿�������\r\n");
+			res = 1;
+		}else{
+			RFID_state = 0;
+		}
+		
+	}else{
+// 		printf("\r\nIC����Ч������\r\n");
+	}
+	
+	return res;
+}
+
+/******************** (C) COPYRIGHT 2017 ping *****END OF FILE*******************/
diff --git a/STM32_4路称重_Git提交精简工程/src/HARDWARE/RFID/rfid_decode_yn.h b/STM32_4路称重_Git提交精简工程/src/HARDWARE/RFID/rfid_decode_yn.h
new file mode 100755
index 0000000..f904cd7
--- /dev/null
+++ b/STM32_4路称重_Git提交精简工程/src/HARDWARE/RFID/rfid_decode_yn.h
@@ -0,0 +1,19 @@
+/*************************** (C) COPYRIGHT 2017 CXHY ****************************
+ * �ļ���  ��rfid_decode_yn.h
+ * ��  ��  ������IC������ͷ�ļ�
+ * ��  ��  ��V1.0
+ * ��  ��  ��XuZhongPing
+ * ��  ��  ��2017/03/06 
+*********************************************************************************/
+#ifndef __RFID_DECODE_YN_H
+#define __RFID_DECODE_YN_H	
+
+#include "stm32f10x.h"
+
+void SecretKeyHEX2Bit(uint8_t outputBuf[], char *inputStr);
+uint8_t CalculateCheckDigit(uint8_t cardNumBit[], uint8_t keyBit[]);
+void IC_CardEncode_YN(uint32_t areaCode, uint32_t serialNum, uint8_t cardType);
+uint8_t IC_CardDecode_YN(void);
+#endif
+
+/******************** (C) COPYRIGHT 2017 CXHY *****END OF FILE*******************/
diff --git a/STM32_4路称重_Git提交精简工程/src/HARDWARE/RFID/rfid_decode_zl.c b/STM32_4路称重_Git提交精简工程/src/HARDWARE/RFID/rfid_decode_zl.c
new file mode 100755
index 0000000..b17c5f3
--- /dev/null
+++ b/STM32_4路称重_Git提交精简工程/src/HARDWARE/RFID/rfid_decode_zl.c
@@ -0,0 +1,72 @@
+/*************************** (C) COPYRIGHT 2017 CXHY ****************************
+ * �ļ���  ��rfid_decode_zl.c
+ * ��  ��  ������IC������    
+ * ��  ��  ��V1.0
+ * ��  ��  ��XuZhongPing
+ * ��  ��  ��2017/03/06 
+*********************************************************************************/
+#include "rfid_decode_zl.h"
+#include "RFID_IC.h"
+#include "string.h" 
+#include "stdio.h"
+#include "data_typedef.h"
+
+
+void showCardHex2(uint8_t *buf, uint8_t len)
+{
+	uint8_t i;
+	
+	printf("\r\n");
+	for(i=0; i<len; i++)
+	{
+		printf("%02X ",buf[i]);
+	}
+	printf("\r\n");
+}
+
+/*
+***********************************************************************
+*	�� �� ��: IC_CardDecode_ZL
+*	����˵��: ����IC������
+*	��    �Σ���
+*	�� �� ֵ: ����ɹ�����1�����ɹ�����0
+***********************************************************************
+*/
+uint8_t IC_CardDecode_ZL(void)
+{
+	uint8_t res = 0;
+	uint8_t i, j;
+	
+	
+	if((RFID_ID[0] == 0x7A) && (RFID_ID[1] == 0x6C))		//IC��ͷ����ϢУ��
+	{
+		//���ŷ���
+		j = 0;
+		memset(cardNumberStr, 0x00, 33);
+		memset(cardNumberBit, 0x00, 32);
+		for(i = 0; i < 16; i++)
+		{
+			sprintf((char*)&cardNumberStr[j], "%01X", RFID_ID[i] >> 4);
+			cardNumberBit[j++] = RFID_ID[i] >> 4;
+			
+			sprintf((char*)&cardNumberStr[j], "%01X", RFID_ID[i] & 0x0F);
+			cardNumberBit[j++] = RFID_ID[i] & 0x0F;
+		}
+		
+		//���㿨�ų���
+		cardNumberLen = ((cardNumberBit[4]*10) + cardNumberBit[5])*2 + 6;
+		
+// 		showCardHex2(cardNumberBit, 32);
+		printf("\r\nIC = %s  len = %d\r\n", cardNumberStr, cardNumberLen);
+	
+		RFID_state = 3;						//RFID_ICˢ��״̬
+		printf("\r\n����IC�����û�����\r\n");
+		res = 1;
+	}else{
+// 		printf("\r\n������������Ч������\r\n");
+	}
+	
+	return res;
+}
+
+/******************** (C) COPYRIGHT 2017 YNHB *****END OF FILE*******************/
diff --git a/STM32_4路称重_Git提交精简工程/src/HARDWARE/RFID/rfid_decode_zl.h b/STM32_4路称重_Git提交精简工程/src/HARDWARE/RFID/rfid_decode_zl.h
new file mode 100755
index 0000000..ab3782f
--- /dev/null
+++ b/STM32_4路称重_Git提交精简工程/src/HARDWARE/RFID/rfid_decode_zl.h
@@ -0,0 +1,18 @@
+/*************************** (C) COPYRIGHT 2017 CXHY ****************************
+ * �ļ���  ��rfid_decode_zl.h
+ * ��  ��  ������IC������ͷ�ļ�
+ * ��  ��  ��V1.0
+ * ��  ��  ��XuZhongPing
+ * ��  ��  ��2017/03/06 
+*********************************************************************************/
+
+
+#ifndef __RFID_DECODE_ZL_H
+#define __RFID_DECODE_ZL_H	
+
+#include "stm32f10x.h"
+
+uint8_t IC_CardDecode_ZL(void);
+#endif
+
+/******************** (C) COPYRIGHT 2017 CXHY *****END OF FILE*******************/
diff --git a/STM32_4路称重_Git提交精简工程/src/HARDWARE/RS485/RS485.c b/STM32_4路称重_Git提交精简工程/src/HARDWARE/RS485/RS485.c
new file mode 100755
index 0000000..90f5e10
--- /dev/null
+++ b/STM32_4路称重_Git提交精简工程/src/HARDWARE/RS485/RS485.c
@@ -0,0 +1,672 @@
+/*************************** (C) COPYRIGHT 2017 CXHY ****************************
+ * �ļ���  ��RS485.c
+ * ��  ��  ��RS485ͨ�Ŵ�������������3���֣�����֡���򡢷���֡����ִ���������     
+ * ��  ��  ��V1.0
+ * ��  ��  ��XuZhongPing
+ * ��  ��  ��2017/02/10
+*********************************************************************************/
+#include "delay.h"
+#include "sys.h"
+#include "RS485.h"
+// #include "usart5.h"
+#include "usart.h"
+#include "timer.h"
+#include "message.h"
+#include "device.h"
+#include "data_typedef.h"
+
+/*ͨѶ��������*/
+#define BaudRate 9600 							//������
+#define DATA_SIZE 32 								//ͨѶ����������
+
+uint8_t Address = 0x00;							//�豸��ַ
+uint8_t Serial_buf[DATA_SIZE]; 			//����ͨѶ������
+uint8_t RS485_RX_BUF[64];  					//���ջ���,���64���ֽ�
+uint8_t RS485_TX_BUF[64]; 					//���ͻ���,���64���ֽ�
+
+//�������������
+uint8_t RS485_RX_STA = 0x00; 				//RS485����״̬���
+uint8_t RS485_CommunicationState;		//RS485ͨѶ�ɹ�����־
+uint8_t radioCom = 0;								//�㲥�����־
+uint8_t responseMark = 0;						//����Ӧ���־
+uint16_t RS485_serialNumber;				//RS485ͨ����ˮ��
+uint8_t rxCmd;											//�ӻ����ص�ָ����
+
+uint8_t slaveAddress = 0;						//�ӻ����صĵ�ַ
+
+uint8_t getMCU2DataStatus;					//ȡ��MCU2������״̬
+uint8_t getMCU2DistanceStatus;			//ȡ��MCU2�Ĳ������״̬
+
+/*
+***********************************************************************
+*	�� �� ��: RS485_Init
+*	����˵��: ��ʼ��RS485�ӿ�
+*	��    ��:	��
+*	�� �� ֵ: ��
+***********************************************************************
+*/
+void RS485_Init(void)
+{
+	//GPIO�˿�����
+	GPIO_InitTypeDef GPIO_InitStructure;
+	 
+	RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOC, ENABLE);		//ʹ��GPIOAʱ��
+
+	
+	//RS485_TX_EN  RS485���ͽ��տ��ƽ�
+	GPIO_InitStructure.GPIO_Pin = GPIO_Pin_2;	
+ 	GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP; 
+ 	GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
+ 	GPIO_Init(GPIOC, &GPIO_InitStructure);
+	
+	GPIO_ResetBits(GPIOC, GPIO_Pin_2);    									//���0��Ĭ�Ͻ���״̬
+	
+	USART5_Init(BaudRate);																	//RS485��Ӧ�Ĵ��ڳ�ʼ��
+}
+
+/*
+***********************************************************************
+*	�� �� ��: RS485_ReceiveData
+*	����˵��: RS485��������
+*	��    ��:	rxData -> ���յ�������
+*	�� �� ֵ: ��
+***********************************************************************
+*/
+void RS485_ReceiveData(uint8_t rxData)
+{
+	static uint8_t RX_State = 0;						//����״̬
+	static uint8_t CS = 0;		  						//���պ����
+	static uint8_t RX_Size = 0;							//����ͨѶ���ݳ���
+	static uint8_t Byte_Count = 0;	  			//���������ֽڼ���
+
+// 	printf("R = %x\r\n", rxData);
+	switch(RX_State)
+	{
+		case 0:	  //��һǰ���ֽ�
+			if(rxData == 0xfe){
+				RX_State = 1;
+			}else{
+				RX_State = 0;
+			}
+			break;
+		case 1:	  //�ڶ�ǰ���ֽ�
+			if(rxData == 0xfe){
+				RX_State = 1;						//ת������֡ͷ
+			}else{
+				if(rxData == 0x68)
+				{
+					RX_State = 3;						//ת�������豸ͨѶ��ַ
+					CS = 0x68;
+				}else{
+					RX_State = 0;
+				}
+			}
+			break;
+		case 2:	  //����֡ͷ
+			if(rxData == 0x68){
+				RX_State = 3;						//ת�������豸ͨѶ��ַ
+				CS = 0x68;
+			}else{
+				RX_State = 0;
+			}
+			break;
+		case 3:		//�����豸ͨѶ��ַ
+			RS485_RX_BUF[0] = rxData;
+			CS += rxData;
+			RX_State = 4;
+			break;
+		case 4:	  //����֡ͷ
+			if(rxData == 0x68){
+				RX_State = 5;						//ת������ͨѶ����
+				CS += 0x68;
+			}else{
+				RX_State = 0;
+			}
+			break;
+		case 5:		//����ͨѶ����
+			RS485_RX_BUF[1] = rxData;
+			CS += rxData;
+			RX_State = 6;							//ת���������ݳ���
+			break;
+		case 6:		//����ͨѶ���ݳ���
+			RS485_RX_BUF[2] = rxData;
+			CS += rxData;
+			RX_Size = rxData;						//���յ����ݳ���
+			if(RX_Size == 0x00){			//������ݳ���Ϊ0����ֱ��ת������У����
+				RX_State = 8;
+			}else{
+				RX_State = 7;						//ת����������
+			}
+			break;				
+		case 7:	  //����N���ֽ�����
+			if(Byte_Count < RX_Size-1){
+				RS485_RX_BUF[Byte_Count + 3] = rxData;
+				CS += rxData;
+				Byte_Count++;
+			}else{
+				RS485_RX_BUF[Byte_Count + 3] = rxData;
+				CS += rxData;
+				Byte_Count = 0;					//�����N���ֽڵ����ݽ��ռ�����0
+				RX_State = 8;						//ת�����պ�����
+			}
+			break;
+		case 8:	  //����У��
+			if(CS != rxData){
+				RX_State = 0;
+			}else{
+				RX_State = 9;						//ת������֡β��0x16
+			}
+			break;
+		case 9:	  //����֡β
+			if(rxData == 0x16){ 					//��֡β��
+				RS485_RX_STA = 0xfd; 		//һ֡���ճɹ������USART_RX_STA=0xfd֪ͨ���������ͨѶ����
+			}
+			RX_State = 0;
+			break;
+		default:  //����
+			break;
+	}
+}
+
+
+/*
+***********************************************************************
+*	�� �� ��: Receive_One
+*	����˵��: ����һ֡ͨѶ����
+*	��    ��:	���մ�ȡ��ַָ��
+*	�� �� ֵ: ������ȷ��־��1 Ϊ���յ�һ֡���ݣ�0 δ���յ�����
+***********************************************************************
+*/
+// uint8_t Receive_One(uint8_t *s)
+// {
+// 	if(RS485_RX_STA == 0xfd)
+// 	{
+// 		return 1; 		//һ֡���ճɹ����رս���ͨѶ������һ֡����ٴ�
+// 	}else{
+// 		return 0;
+// 	}
+// }
+
+
+/*
+***********************************************************************
+*	�� �� ��: RS485_SendData
+*	����˵��: ����һ���ֽ�����
+*	��    ��:	��������
+*	�� �� ֵ: ��
+***********************************************************************
+*/
+void RS485_SendData(uint8_t Serial_data)
+{
+// 	CTRL485 = 1;													//����Ϊ����ģʽ
+	UART5_Send_Data(Serial_data);
+// 	CTRL485 = 0;													//�ָ�Ϊ����ģʽ	
+}
+
+/*
+***********************************************************************
+*	�� �� ��: RS485_SendOne
+*	����˵��: ͨ��RS485����һ֡����
+*	��    ��:	��������֡��ַָ��
+*	�� �� ֵ: ��
+***********************************************************************
+*/
+void RS485_SendOne(uint8_t *s)
+{
+	uint8_t i;
+	uint8_t CS = 0x68;								//���պ����
+	uint8_t TX_Size = 0;							//����ͨѶ���ݳ���
+	
+	printf("\r\nRS485 --> %x\r\n", *(s+1));
+	
+	CTRL485 = 1;		 									//RS-485 ͨѶ���л�Ϊ����״̬
+	
+	delay_ms(1);
+	RS485_SendData(0xfe); 						//����ǰ���ֽ�
+	RS485_SendData(0xfe);
+	RS485_SendData(0xfe);
+	RS485_SendData(0xfe);
+	RS485_SendData(0x68); 						//����֡ͷ
+	RS485_SendData(*s); 							//���͵�ַ
+	CS += *s;
+	RS485_SendData(0x68); 						//����֡ͷ
+	CS += 0x68;
+	RS485_SendData(*(s+1)); 					//����֡����
+	CS += *(s+1);
+	TX_Size = *(s+2);									//ȡ��ͨѶ���ݳ���
+	RS485_SendData(TX_Size); 					//�������ݳ���
+	CS += *(s+2);
+	for(i=0; i<TX_Size; i++) 					//��������
+	{
+		RS485_SendData(*(s+i+3));
+		CS += (*(s+i+3));
+	}
+	RS485_SendData(CS); 							//����У���ֽ�
+	RS485_SendData(0x16); 						//����֡β
+
+	delay_ms(1);
+	
+	CTRL485 = 0; 											//һ֡������ϣ��ָ��ŵ��л�����
+}
+
+/*
+***********************************************************************
+*	�� �� ��: Serial_AddrxDatas
+*	����˵��: ͨѶ��ַ�ж�
+*	��    ��:	s ָ���ͨѶ��ַ
+*	�� �� ֵ: 0x00 ����0x01 ��ȷ��0x02 �㲥��ַ
+***********************************************************************
+*/
+static uint8_t Serial_Address(uint8_t *s)
+{
+// 	printf("\r\n��ַ��%x\r\n", *s);
+	if(*s == 0x99)
+	{
+// 		printf("\r\n�յ��㲥ָ��\r\n");
+		return(0x02); 				//�ǹ㲥��ַ
+	}
+	if(*s == Address)
+	{
+// 		printf("\r\n��ַƥ����ȷ\r\n");
+		return(0x01); 				//��ַƥ����ȷ
+	}
+// 	printf("\r\n��ַƥ�䲻��ȷ\r\n");
+	return(0x00); 					//��ַƥ�䲻��ȷ
+}
+
+/*
+***********************************************************************
+*	�� �� ��: RS485_CommandDecoding
+*	����˵��: ִ��ͨѶ����
+*	��    ��:	s ��������֡��ַָ��
+*	�� �� ֵ: 0 ����1 ��ȷ
+***********************************************************************
+*/
+uint8_t RS485_CommandDecoding(uint8_t *pRxBuf, uint8_t *pTxBuf)
+{	
+	printf("\r\nRS485_%x <-- %x\r\n", *(pRxBuf+3), *(pRxBuf+1));
+	rxCmd = *(pRxBuf+1);
+	
+	switch(Serial_Address(pRxBuf)) 		//�жϵ�ַ�Ƿ���ȷ
+	{
+		case 0x02: 		//�㲥��ַ0x99
+			switch(*(pRxBuf+1))														//ͨѶ��������
+			{
+				case 0x20:			//�����㲥��������
+					printf("\r\n�յ��㲥����ָ��\r\n");
+					radioCom = 1;
+					isOpenDoor = 1;
+					break;
+					
+				default:
+					break;
+			}
+	 		break;
+			
+		case 0x01: 		//������ַ
+			slaveAddress = *(pRxBuf+3);										//ȡ��Ӧ��ӻ��ĵ�ַ
+
+			switch(*(pRxBuf+1))														//ͨѶ��������
+			{
+				case 0x00: 			//Ӧ������
+
+					break;
+					
+				case 0x01: 			//��ȡ����������ֵ
+
+					break;
+					
+				case 0x10:			//����ָ��
+// 					switch(slaveAddress)
+// 					{
+// 						case 0x11:		//�ӻ�1�ķֻ�1��������
+// 							devRunningStatusNO_1 = 1;
+// 							break;
+// 							
+// 						case 0x12:		//�ӻ�1�ķֻ�2��������
+// 							devRunningStatusNO_2 = 1;
+// 							break;
+// 							
+// 						case 0x21:		//�ӻ�2�ķֻ�1��������
+// 							devRunningStatusNO_3 = 1;
+// 							break;
+// 							
+// 						case 0x22:		//�ӻ�2�ķֻ�2��������
+// 							devRunningStatusNO_4 = 1;
+// 							break;
+// 							
+// 						default:
+// 							printf("\r\nError_0x10ָ�����\r\n");
+// 							break;
+// 					}
+					
+					break;
+				
+				case 0x11:			//��ȡ���ſ�������״ָ̬��
+// 					switch(slaveAddress)
+// 					{
+// 						case 0x11:		//�ӻ�1�ķֻ�1��������
+// 							devRunningStatusNO_1 = *(pRxBuf+4);
+// 							printf("\r\nRX_Data = 0x%02X\r\n", *(pRxBuf+4));
+// 							break;
+// 							
+// 						case 0x12:		//�ӻ�1�ķֻ�2��������
+// 							devRunningStatusNO_2 = *(pRxBuf+4);
+// 							printf("\r\nRX_Data = 0x%02X\r\n", *(pRxBuf+4));
+// 							break;
+// 							
+// 						case 0x21:		//�ӻ�2�ķֻ�1��������
+// 							devRunningStatusNO_3 = *(pRxBuf+4);
+// 							printf("\r\nRX_Data = 0x%02X\r\n", *(pRxBuf+4));
+// 							break;
+// 						
+// 						case 0x22:		//�ӻ�2�ķֻ�2��������
+// 							devRunningStatusNO_4 = *(pRxBuf+4);
+// 							printf("\r\nRX_Data = 0x%02X\r\n", *(pRxBuf+4));
+// 							break;
+// 							
+// 						default:
+// 							printf("\r\nError_0x10ָ�����\r\n");
+// 							break;
+// 					}
+					break;
+					
+				case 0x12:			//��ȡ�ӻ��������ָ��
+// 					switch(slaveAddress)
+// 					{
+// 						case 0x10:
+// 						case 0x11:
+// 						case 0x12:
+// 							getDistance1 = *(pRxBuf+4);				//����
+// 							getDistance2 = *(pRxBuf+5);				//����
+// 							break;
+// 							
+// 						case 0x20:
+// 						case 0x21:
+// 						case 0x22:
+// 							getDistance3 = *(pRxBuf+4);				//ƿ��
+// 							getDistance4 = *(pRxBuf+5);				//����
+// 							break;
+// 							
+// 					}
+// 					printf("\r\nRX_Data = %d, %d\r\n", *(pRxBuf+4), *(pRxBuf+5));
+					break;
+					
+				case 0x13:			//��ȡ�ӻ�Ͷ������ָ��
+// 					switch(slaveAddress)
+// 					{
+// 						case 0x11:		//�ӻ�1�ķֻ�1�������ݣ�ע�⣺�˳����ɵ�2·�ӷ��أ�
+// 							getWeight4 = (uint16_t)(*(pRxBuf+4)) << 8;							//ȡ��������8λ����
+// 							getWeight4 |= *(pRxBuf+5);															//ȡ��������8λ����
+// 							
+// 							getWeightBefore4 = (uint16_t)(*(pRxBuf+6)) << 8;				//ȡ��������8λ����
+// 							getWeightBefore4 |= *(pRxBuf+7);												//ȡ��������8λ����
+// 							
+// 							getWeightAfter4 = (uint16_t)(*(pRxBuf+8)) << 8;					//ȡ��������8λ����
+// 							getWeightAfter4 |= *(pRxBuf+9);													//ȡ��������8λ����
+// 							
+// 							getDistance1 = *(pRxBuf+10);														//ȡ���������
+// 							
+// 							faultCodeNO_1 = *(pRxBuf+11);														//ȡ���豸������
+// 							
+// 							devRunningStatusNO_1 = 3;
+// 							printf("\r\nRX_Data1 = %d, %d, %d, %d, %d\r\n", getWeight4, getWeightBefore4, getWeightAfter4, getDistance1, faultCodeNO_1);
+// 							break;
+// 							
+// 						case 0x12:		//�ӻ�1�ķֻ�2�������ݣ�ע�⣺�˳����ɵ�3·�ӷ��أ�
+// 							getWeight3 = (uint16_t)(*(pRxBuf+4)) << 8;							//ȡ��������8λ����
+// 							getWeight3 |= *(pRxBuf+5);															//ȡ��������8λ����
+// 							
+// 							getWeightBefore3 = (uint16_t)(*(pRxBuf+6)) << 8;				//ȡ��������8λ����
+// 							getWeightBefore3 |= *(pRxBuf+7);												//ȡ��������8λ����
+// 							
+// 							getWeightAfter3 = (uint16_t)(*(pRxBuf+8)) << 8;					//ȡ��������8λ����
+// 							getWeightAfter3 |= *(pRxBuf+9);													//ȡ��������8λ����
+// 							
+// 							getDistance2 = *(pRxBuf+10);														//ȡ���������
+// 							
+// 							faultCodeNO_2 = *(pRxBuf+11);														//ȡ���豸������
+// 							
+// 							devRunningStatusNO_2 = 3;
+// 							printf("\r\nRX_Data2 = %d, %d, %d, %d, %d\r\n", getWeight3, getWeightBefore3, getWeightAfter3, getDistance2, faultCodeNO_2);
+// 							break;
+// 							
+// 						case 0x21:		//�ӻ�2�ķֻ�1�������ݣ�ע�⣺�˳����ɵ�3·�ӷ��أ�
+// 							getWeight2 = (uint16_t)(*(pRxBuf+4)) << 8;							//ȡ��������8λ����
+// 							getWeight2 |= *(pRxBuf+5);															//ȡ��������8λ����
+// 							
+// 							getWeightBefore2 = (uint16_t)(*(pRxBuf+6)) << 8;				//ȡ��������8λ����
+// 							getWeightBefore2 |= *(pRxBuf+7);												//ȡ��������8λ����
+// 							
+// 							getWeightAfter2 = (uint16_t)(*(pRxBuf+8)) << 8;					//ȡ��������8λ����
+// 							getWeightAfter2 |= *(pRxBuf+9);													//ȡ��������8λ����
+// 							
+// 							getDistance3 = *(pRxBuf+10);														//ȡ���������
+// 							
+// 							faultCodeNO_3 = *(pRxBuf+11);														//ȡ���豸������
+// 							
+// 							devRunningStatusNO_3 = 3;
+// 							printf("\r\nRX_Data3 = %d, %d, %d, %d, %d\r\n", getWeight2, getWeightBefore2, getWeightAfter2, getDistance3, faultCodeNO_3);
+// 							break;
+// 						
+// 						case 0x22:		//�ӻ�2�ķֻ�2��������
+// 							getWeight1 = (uint16_t)(*(pRxBuf+4)) << 8;							//ȡ��������8λ����
+// 							getWeight1 |= *(pRxBuf+5);															//ȡ��������8λ����
+// 							
+// 							getWeightBefore1 = (uint16_t)(*(pRxBuf+6)) << 8;				//ȡ��������8λ����
+// 							getWeightBefore1 |= *(pRxBuf+7);												//ȡ��������8λ����
+// 							
+// 							getWeightAfter1 = (uint16_t)(*(pRxBuf+8)) << 8;					//ȡ��������8λ����
+// 							getWeightAfter1 |= *(pRxBuf+9);													//ȡ��������8λ����
+// 							
+// 							getDistance4 = *(pRxBuf+10);														//ȡ���������
+// 							
+// 							faultCodeNO_4 = *(pRxBuf+11);														//ȡ���豸������
+// 							
+// 							devRunningStatusNO_4 = 3;
+// 							printf("\r\nRX_Data4 = %d, %d, %d, %d, %d\r\n", getWeight1, getWeightBefore1, getWeightAfter1, getDistance4, faultCodeNO_4);
+// 							break;
+// 							
+// 						default:
+// 							printf("\r\nError_0x10ָ�����\r\n");
+// 							break;
+// 					}
+					
+					break;
+					
+				case 0x14:			//��ȡ�ӻ�Ͷ����������ָ�����ֻ��ȡƿ��+����������ݣ�
+							
+// 					getWeight2 = (uint16_t)(*(pRxBuf+4)) << 8;							//ȡ��������8λ����
+// 					getWeight2 |= *(pRxBuf+5);															//ȡ��������8λ����
+// 					
+// 					getWeightBefore2 = (uint16_t)(*(pRxBuf+6)) << 8;				//ȡ��������8λ����
+// 					getWeightBefore2 |= *(pRxBuf+7);												//ȡ��������8λ����
+// 					
+// 					getWeightAfter2 = (uint16_t)(*(pRxBuf+8)) << 8;					//ȡ��������8λ����
+// 					getWeightAfter2 |= *(pRxBuf+9);													//ȡ��������8λ����
+// 					
+// 					getDistance3 = *(pRxBuf+10);														//ȡ���������
+// 					faultCodeNO_3 = *(pRxBuf+11);														//ȡ���豸������
+// 					
+// 					devRunningStatusNO_3 = 3;
+// 					
+// 					getSmallBottleCount = (uint16_t)(*(pRxBuf+12)) << 8;		//ȡ��ƿ�Ӹ�8λ����
+// 					getSmallBottleCount |= *(pRxBuf+13);										//ȡ��ƿ�ӵ�8λ����
+// 					getDistance5 = *(pRxBuf+14);														//ȡ���������
+
+// 					printf("\r\nRX_Data3 = %d, %d, %d, %d, %d\r\n", getWeight2, getWeightBefore2, getWeightAfter2, getDistance3, faultCodeNO_3);
+// 					
+					break;
+					
+				case 0x20:			//��ȡ�ӻ��豸�ĵ�ǰ״ָ̬��
+// 					switch(slaveAddress)
+// 					{
+// 						case 0x11:		//�ӻ�1�ķֻ�1��������
+// 							deviceStatusNO_1 = *(pRxBuf+4);
+// 							break;
+// 							
+// 						case 0x12:		//�ӻ�1�ķֻ�2��������
+// 							deviceStatusNO_2 = *(pRxBuf+4);
+// 							break;
+// 							
+// 						case 0x21:		//�ӻ�2�ķֻ�1��������			
+// 							deviceStatusNO_3 = *(pRxBuf+4);
+// 							break;
+// 							
+// 						case 0x22:		//�ӻ�2�ķֻ�2��������
+// 							deviceStatusNO_4 = *(pRxBuf+4);
+// 							break;
+// 							
+// 						default:
+// 							printf("\r\nError_0x20ָ�����\r\n");
+// 							break;
+// 					}
+					break;
+					
+				case 0x30:			//���������û���ϢӦ��
+					break;
+					
+				case 0x31:			//���������û�Ͷ�Ž�����ϢӦ��
+					break;
+					
+				case 0x32:			//���������˳���ʾ����Ӧ��
+					break;
+					
+				case 0x39:			//���������˳�����Ӧ��
+					break;		
+					
+				default: 				//��������
+					break;
+			}
+			break;
+
+		case 0x00: 	//��ַ����
+			return 0;
+	}
+	return 1; 		//ִ֡����ȷ������
+}
+
+/*
+***********************************************************************
+*	�� �� ��: RS485_PackSendProtocol
+*	����˵��: ����RS485��Ϣ�����������֡
+*	��    ��:	msg -> RS485������Ϣ
+*						������msg->msgTypeΪָ�msg->msgDataΪҪ���͵Ĵӻ���ַ��
+*						0x01->��ȡ����������ֵ��
+*						0x02->��ȡ����ֵ
+*						0x03->��ȡ�¶�ֵ
+*						0x10->��ȡ�¶ȡ���ࡢˮλ��������������Ϣ�����
+*						0x20->�����㲥����ָ��
+*	�� �� ֵ: ��
+***********************************************************************
+*/
+void RS485_PackSendProtocol(Com_ProtocolMessage *msg)
+{
+	RS485_TX_BUF[0] = msg->msgData; 										//���ôӻ�ͨѶ��ַ
+	RS485_TX_BUF[1] = msg->msgType;											//����ָ����
+	RS485_TX_BUF[2] = 0;																//�������ݳ���
+	
+// 	switch(msg->msgType)
+// 	{
+// 		case 0x30:
+// 			RS485_TX_BUF[2] = 27;														//�������ݳ���
+// 			
+// 			RS485_TX_BUF[3] = isAuth;												//��������
+// 			RS485_TX_BUF[4] = putInType;
+// 			memcpy(&RS485_TX_BUF[5], icCardNumberBit, 17);
+// 			RS485_TX_BUF[5+17] = (uint8_t)(accountNum >> 24);
+// 			RS485_TX_BUF[6+17] = (uint8_t)(accountNum >> 16);
+// 			RS485_TX_BUF[7+17] = (uint8_t)(accountNum >> 8);
+// 			RS485_TX_BUF[8+17] = (uint8_t)accountNum;
+// 			
+// 			RS485_TX_BUF[9+17] = (uint8_t)(capital >> 24);
+// 			RS485_TX_BUF[10+17] = (uint8_t)(capital >> 16);
+// 			RS485_TX_BUF[11+17] = (uint8_t)(capital >> 8);
+// 			RS485_TX_BUF[12+17] = (uint8_t)capital;
+// 			break;
+// 			
+// 		case 0x31:
+// 			RS485_TX_BUF[2] = 8;														//�������ݳ���
+// 			
+// 			RS485_TX_BUF[3] = (uint8_t)(capital >> 24);
+// 			RS485_TX_BUF[4] = (uint8_t)(capital >> 16);
+// 			RS485_TX_BUF[5] = (uint8_t)(capital >> 8);
+// 			RS485_TX_BUF[6] = (uint8_t)capital;
+// 			
+// 			RS485_TX_BUF[7] = (uint8_t)(capitalAfter >> 24);
+// 			RS485_TX_BUF[8] = (uint8_t)(capitalAfter >> 16);
+// 			RS485_TX_BUF[9] = (uint8_t)(capitalAfter >> 8);
+// 			RS485_TX_BUF[10] = (uint8_t)capitalAfter;
+// 			break;
+// 			
+// 		default:
+// 			break;
+// 	}
+}
+
+/*
+***********************************************************************
+*	�� �� ��: RS485_Task
+*	����˵��: RS485ͨѶ����
+*	��    ��:	��
+*	�� �� ֵ: ��
+***********************************************************************
+*/
+void RS485_Task(void)
+{
+	uint8_t rs485succeedFlag = 0;
+	uint8_t timerOut = 0;
+	static Com_ProtocolMessage *pMsg;
+	static timer timer_01;
+	static uint8_t timer_ok = 0;
+	
+	if(timer_ok == 0)
+	{
+		timer_ok = 1;
+		timer_set(&timer_01, 4);  															//����1����ʱ�� 
+	}
+	
+	pMsg = MessageGet(MSG_FIFO_RS485_PROTOCOL);								//����Ϣ������ȡ��RS485ͨѶЭ����Ϣ
+	if(pMsg)
+	{
+// 		printf("\r\n----->RS485������Ҫ�������ڼ�������......\r\n");
+// 		printf("\r\n----->RS485msgType = %x\r\n", pMsg->msgType);
+// 		printf("\r\n----->RS485msgData = %x\r\n", pMsg->msgData);
+		
+		RS485_PackSendProtocol(pMsg);
+		RS485_SendOne(RS485_TX_BUF); 														//���ӻ�����һ֡����
+		
+		if(pMsg->msgData == 0x99)		//�㲥��ַ����ȴ�Ӧ��
+		{
+			RS485_RX_STA = 0;	
+		}else{
+			timer_restart(&timer_01);
+			while(!timerOut && !rs485succeedFlag)
+			{
+				if(timer_expired(&timer_01))												//��ʱδ���յ�����
+				{
+					timerOut = 1;																			//��ʱ���س�ʼ״̬		
+					printf("\r\n----->RS485TimerOut\r\n");
+					RS485_RX_STA = 0;	
+				}
+				if(RS485_RX_STA == 0xfd)														//�н��յ��ӻ����ص����ݣ����е�ַ��������֤
+				{
+					RS485_RX_STA = 0;	
+					if(RS485_CommandDecoding(RS485_RX_BUF, RS485_TX_BUF)) 		//���ͷ��ص�����
+					{
+// 						printf("\r\nmsgType = %x, rxCmd = %x\r\n", pMsg->msgType, rxCmd);
+						if(pMsg->msgType == rxCmd)
+						{
+							rs485succeedFlag = 1;							
+							RS485_CommunicationState = 1;									//���ñ��η��͵�����֡�ɹ�
+							
+							printf("\r\n----->RS485<--OK\r\n");
+						}
+					}
+				}
+			}
+		}
+	}
+}
+
+/******************** (C) COPYRIGHT 2017 YNHB *****END OF FILE*******************/
diff --git a/STM32_4路称重_Git提交精简工程/src/HARDWARE/RS485/RS485.h b/STM32_4路称重_Git提交精简工程/src/HARDWARE/RS485/RS485.h
new file mode 100755
index 0000000..6f383f7
--- /dev/null
+++ b/STM32_4路称重_Git提交精简工程/src/HARDWARE/RS485/RS485.h
@@ -0,0 +1,44 @@
+/*************************** (C) COPYRIGHT 2017 CXHY ****************************
+ * �ļ���  ��RS485.h
+ * ��  ��  ��RS485ͨ�Ŵ���ͷ�ļ�  
+ * ��  ��  ��V1.0
+ * ��  ��  ��XuZhongPing
+ * ��  ��  ��2017/02/10
+*********************************************************************************/
+#ifndef __RS485_H
+#define __RS485_H
+
+#include "stdio.h"
+#include "sys.h"
+
+#define CTRL485	PCout(2)											//485ģʽ��������
+
+extern uint8_t Address;
+	  	
+extern uint8_t RS485_RX_BUF[64];     					//���ջ���,���63���ֽ�.ĩ�ֽ�Ϊ���з� 
+extern uint8_t RS485_TX_BUF[64];     					//���ͻ���,���64���ֽ�.
+
+extern uint8_t RS485_RX_STA; 									//RS485����״̬���
+extern uint8_t RS485_CommunicationState;			//RS485ͨѶ�ɹ�����־
+extern uint8_t radioCom;											//�㲥����
+extern uint8_t responseMark;									//����Ӧ���־
+extern uint16_t RS485_serialNumber;						//RS485ͨ����ˮ��
+
+extern uint8_t getMCU2DataStatus;							//ȡ��MCU2������״̬
+extern uint8_t getMCU2DistanceStatus;					//ȡ��MCU2�Ĳ������״̬
+
+void RS485_Init(void);
+void  RS485_1(void);
+void RS485_ReceiveData(uint8_t rxData);
+
+void SendDoorCtrlCMD(void);										//��ӻ����Ϳ��ſ���ָ��
+void SendGetPutInMsgCMD(void);								//��ӻ����������û�Ͷ������
+void SendReadyPutInCMD(void);			
+void SendEndPutInCMD(void);				
+
+void RS485_Task(void);
+
+
+#endif
+
+/******************** (C) COPYRIGHT 2017 CXHY *****END OF FILE*******************/
diff --git a/STM32_4路称重_Git提交精简工程/src/HARDWARE/SCALE/scale.c b/STM32_4路称重_Git提交精简工程/src/HARDWARE/SCALE/scale.c
new file mode 100755
index 0000000..1ce3b00
--- /dev/null
+++ b/STM32_4路称重_Git提交精简工程/src/HARDWARE/SCALE/scale.c
@@ -0,0 +1,177 @@
+/*************************** (C) COPYRIGHT 2017 Ping ****************************
+ * �ļ���  ��scale.c
+ * ��  ��  ������������    
+ * ��  ��  ��V1.0
+ * ��  ��  ��XuZhongPing
+ * ��  ��  ��2017/03/06 
+*********************************************************************************/
+#include "stdio.h"
+#include "scale.h"
+#include "timer.h"
+
+uint16_t weight1 = 0;							//��ǰ��������������Ŵ�100������λkg
+uint16_t weight2 = 0;
+uint16_t weight3 = 0;
+uint16_t weight4 = 0;
+
+uint8_t scaleNum = 0;							//���̱��
+uint8_t receiveScaleNum = 0;					//ȡ�õĳ��̱��
+
+uint8_t calibrationParam1[16];		//У׼ʱ���յ�������
+uint8_t calibrationParam2[16];		
+
+uint8_t getCalibraDataMark1 = 0;			//ȡ��У׼ָ������
+uint8_t getCalibraZeroMark1 = 0;			//ȡ��У׼���
+uint8_t getCalibraParamOkMark1 = 0;		//ȡ��У׼���
+
+uint8_t getCalibraDataMark2 = 0;
+uint8_t getCalibraZeroMark2 = 0;
+uint8_t getCalibraParamOkMark2 = 0;
+
+void ScaleCmdRun1(uint8_t* pRxBuf);
+void ScaleCmdRun2(uint8_t* pRxBuf);
+void ScaleCmdDecodeTask(void);
+
+/*
+***********************************************************************
+*	�� �� ��: Scale_Init
+*	����˵��: �� ��Դ����IO�ڳ�ʼ��
+*	��    �Σ���
+*	�� �� ֵ: ��
+***********************************************************************
+*/
+void ScaleInit(void)
+{ 
+	
+}
+
+/*
+***********************************************************************
+*	�� �� ��: ScalePowerON
+*	����˵��: �򿪳Ƶ�Դ
+*	��    �Σ�ѡ����һ·�ӳƵ�Դ��
+*	�� �� ֵ: ��
+***********************************************************************
+*/
+void ScalePowerON(uint8_t whichOne)
+{
+	
+}
+
+/*
+***********************************************************************
+*	�� �� ��: ScalePowerOFF
+*	����˵��: �رճƵ�Դ
+*	��    �Σ�whichOne -> ѡ����һ·�ӳƵ�Դ��
+*	�� �� ֵ: ��
+***********************************************************************
+*/
+void ScalePowerOFF(uint8_t whichOne)
+{
+	
+}
+
+/*
+***********************************************************************
+*	�� �� ��: GetWeight
+*	����˵��: ȡ�ó����������
+*	��    �Σ���
+*	�� �� ֵ: �ޣ����ô˺������ı�ȫ�ֱ���currentWeight��currentWeight2��
+***********************************************************************
+*/
+void SendCalibraCmd(uint8_t num)
+{
+	uint8_t cmd[10] = {0xfe, 0xfe, 0xfe, 0x68, 0x00, 0x68, 0xa1, 0x00, 0x71, 0x16};
+	
+	if(num ==1)
+	{
+		USART4_SendFrameData(cmd, 10);
+	}else if(num == 2){
+		USART5_SendFrameData(cmd, 10);
+	}
+}
+
+/*
+***********************************************************************
+*	�� �� ��: ScaleCmdRun1
+*	����˵��: ����У׼ָ��ִ��
+*	��    �Σ���
+*	�� �� ֵ: ��
+***********************************************************************
+*/
+void ScaleCmdRun1(uint8_t* pRxBuf)
+{
+	uint8_t proNum;
+	
+	proNum = *(pRxBuf+1);
+	
+	printf("\r\nS1 <-- 0x%02X\r\n", proNum);
+	switch(proNum)														//ͨѶ��������
+	{			
+		case 0xA2:		//�յ�У׼���
+			getCalibraZeroMark1 = 1;
+			break;
+			
+		case 0xA3:
+			getCalibraParamOkMark1 = 1;
+			break;
+			
+		default:
+			break;
+	}
+}
+
+/*
+***********************************************************************
+*	�� �� ��: ScaleCmdRun2
+*	����˵��: ����У׼ָ��ִ��
+*	��    �Σ���
+*	�� �� ֵ: ��
+***********************************************************************
+*/
+void ScaleCmdRun2(uint8_t* pRxBuf)
+{
+	uint8_t proNum;
+	
+	proNum = *(pRxBuf+1);
+	
+	printf("\r\nS2 <-- 0x%02X\r\n", proNum);
+	switch(proNum)														//ͨѶ��������
+	{			
+		case 0xA2:		//�յ�У׼���
+			getCalibraZeroMark2 = 1;
+			break;
+			
+		case 0xA3:
+			getCalibraParamOkMark2 = 1;
+			break;
+			
+		default:
+			break;
+	}
+}
+
+/*
+***********************************************************************
+*	�� �� ��: ScaleCmdDecodeTask
+*	����˵��: ����ģ�����ָ���������
+*	��    ��:	��
+*	�� �� ֵ: ��
+***********************************************************************
+*/
+void ScaleCmdDecodeTask(void)
+{
+	if(getCalibraDataMark1 == 1)										//�н��յ�����
+	{
+		ScaleCmdRun1(calibrationParam1); 							//���ͷ��ص�����
+		getCalibraDataMark1 = 0;
+	}
+	
+	if(getCalibraDataMark2 == 1)										//�н��յ�����
+	{
+		ScaleCmdRun2(calibrationParam2); 							//���ͷ��ص�����
+		getCalibraDataMark2 = 0;
+	}
+}
+
+/******************** (C) COPYRIGHT 2017 Ping *****END OF FILE*******************/
diff --git a/STM32_4路称重_Git提交精简工程/src/HARDWARE/SCALE/scale.h b/STM32_4路称重_Git提交精简工程/src/HARDWARE/SCALE/scale.h
new file mode 100755
index 0000000..56cd65f
--- /dev/null
+++ b/STM32_4路称重_Git提交精简工程/src/HARDWARE/SCALE/scale.h
@@ -0,0 +1,53 @@
+/*************************** (C) COPYRIGHT 2017 CXHY ****************************
+ * �ļ���  ��scale.h
+ * ��  ��  ������������    
+ * ��  ��  ��V1.0
+ * ��  ��  ��XuZhongPing
+ * ��  ��  ��2017/03/06 
+*********************************************************************************/
+#ifndef __SCALE_H
+#define __SCALE_H	 
+
+#include "stm32f10x.h"
+#include "usart1.h"
+#include "usart3.h"
+#include "usart4.h"
+#include "usart5.h"
+
+extern uint16_t weight1;							//��ǰ��������������Ŵ�100������λkg
+extern uint16_t weight2;
+extern uint16_t weight3;
+extern uint16_t weight4;
+
+extern uint8_t scaleNum;
+extern uint8_t receiveScaleNum;					//ȡ�õĳ��̱��
+
+extern uint8_t calibrationParam1[16];
+extern uint8_t calibrationParam2[16];
+
+extern uint8_t getCalibraDataMark1;			//ȡ��У׼ָ������
+extern uint8_t getCalibraZeroMark1;			//ȡ��У׼���
+extern uint8_t getCalibraParamOkMark1;		//ȡ��У׼���
+
+extern uint8_t getCalibraDataMark2;
+extern uint8_t getCalibraZeroMark2;
+extern uint8_t getCalibraParamOkMark2;
+
+
+
+void ScaleInit(void);									//��ؽӿڳ�ʼ��
+void ScalePowerON(uint8_t whichOne);	//�ӵ�Դ��
+void ScalePowerOFF(uint8_t whichOne);	//�ӵ�Դ�ر�
+void Clear_01(void);									//��һ·������
+void Clear_02(void);									//�ڶ�·������	
+void ClearWeight(void);								//�����������
+  
+void WeightDetection(void);						//���ؼ��  
+void UpdateWeight(void);							//���µ�ǰ�������������û��Ͷ�Ų���ʱ�ĳ��ر仯��
+void GetWeight(void);									//ȡ�õ�ǰ�������������Ͷ�Ź����еĳ��ر仯��
+
+void SendCalibraCmd(uint8_t num);
+
+#endif
+
+/******************** (C) COPYRIGHT 2017 CXHY *****END OF FILE*******************/
diff --git a/STM32_4路称重_Git提交精简工程/src/HARDWARE/SPI/spi.c b/STM32_4路称重_Git提交精简工程/src/HARDWARE/SPI/spi.c
new file mode 100755
index 0000000..96c325b
--- /dev/null
+++ b/STM32_4路称重_Git提交精简工程/src/HARDWARE/SPI/spi.c
@@ -0,0 +1,87 @@
+/*************************** (C) COPYRIGHT 2014 GLHF ****************************
+ *  �ļ���  ��spi.h
+ *  ��  ��  ��SPI�ӿ���������
+ *  ��  ��  ��V1.0
+ *  ��  ��  ��2018-11-24
+ *  ��  ��  ��XuZhongPing 
+ * ���¼�¼ ��
+*********************************************************************************/
+#include "spi.h"
+
+/*
+ * ��������SPI1_Init
+ * ����  ��ENC28J60 SPI �ӿڳ�ʼ��
+ * ����  ���� 
+ * ���  ����
+ * ����  ����
+ */																						  
+void SPI1_Init(void)
+{
+	GPIO_InitTypeDef GPIO_InitStructure;
+	SPI_InitTypeDef  SPI_InitStructure;	
+	
+	RCC_APB2PeriphClockCmd(	RCC_APB2Periph_GPIOA | RCC_APB2Periph_GPIOE, ENABLE ); 
+	RCC_APB2PeriphClockCmd(	RCC_APB2Periph_SPI1,  ENABLE );//SPI1ʱ��ʹ�� 	
+
+	//PA5 -> SCK  PA6 -> MISO	 PA7 -> MOSI
+	GPIO_InitStructure.GPIO_Pin = GPIO_Pin_5 | GPIO_Pin_6 | GPIO_Pin_7;
+	GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;  										//PA5/6/7����������� 
+	GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
+	GPIO_Init(GPIOA, &GPIO_InitStructure);
+
+	/* PC4-SPI1-NSS:SD-CS */ 											 // Ƭѡ
+  GPIO_InitStructure.GPIO_Pin = GPIO_Pin_8;
+  GPIO_InitStructure.GPIO_Speed = GPIO_Speed_10MHz;
+  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP;	   // �������
+  GPIO_Init(GPIOE, &GPIO_InitStructure);						  
+	GPIO_SetBits(GPIOE, GPIO_Pin_8);										 // �Ȱ�Ƭѡ���ߣ������õ�ʱ��������
+	
+	/* PA4-SPI1-NSS:FLASH-CS */ 											 // Ƭѡ
+  GPIO_InitStructure.GPIO_Pin = GPIO_Pin_7;
+  GPIO_InitStructure.GPIO_Speed = GPIO_Speed_10MHz;
+  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP;	   // �������
+  GPIO_Init(GPIOE, &GPIO_InitStructure);						  
+	GPIO_SetBits(GPIOE, GPIO_Pin_7);										 // �Ȱ�Ƭѡ���ߣ������õ�ʱ��������
+ 
+
+	/* SPI1 ���� */ 
+	SPI_InitStructure.SPI_Direction = SPI_Direction_2Lines_FullDuplex;
+	SPI_InitStructure.SPI_Mode = SPI_Mode_Master;
+	SPI_InitStructure.SPI_DataSize = SPI_DataSize_8b;
+	SPI_InitStructure.SPI_CPOL = SPI_CPOL_Low;
+	SPI_InitStructure.SPI_CPHA = SPI_CPHA_1Edge;
+	SPI_InitStructure.SPI_NSS = SPI_NSS_Soft;
+	SPI_InitStructure.SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_64;
+	SPI_InitStructure.SPI_FirstBit = SPI_FirstBit_MSB;
+	SPI_InitStructure.SPI_CRCPolynomial = 7;
+	SPI_Init(SPI1, &SPI_InitStructure);
+	
+	/* ʹ�� SPI1  */
+	SPI_Cmd(SPI1, ENABLE); 
+}
+
+/*
+ * ��������SPI1_ReadWrite
+ * ����  ��SPI1��дһ�ֽ�����
+ * ����  �� 
+ * ���  ��
+ * ����  ��SPI1_ReadWriteByte
+ */
+uint8_t	SPI1_ReadWriteByte(uint8_t writedat)
+{
+	uint8_t retry=0;				 	
+	while (SPI_I2S_GetFlagStatus(SPI1, SPI_I2S_FLAG_TXE) == RESET) //���ָ����SPI��־λ�������:���ͻ���ձ�־λ
+	{
+		retry++;
+		if(retry>200)return 0;
+	}			  
+	SPI_I2S_SendData(SPI1, writedat); //ͨ������SPIx����һ������
+	retry=0;
+
+	while (SPI_I2S_GetFlagStatus(SPI1, SPI_I2S_FLAG_RXNE) == RESET) //���ָ����SPI��־λ�������:���ܻ���ǿձ�־λ
+	{
+		retry++;
+		if(retry>200)return 0;
+	}	  						    
+	return SPI_I2S_ReceiveData(SPI1); //����ͨ��SPIx������յ�����	
+}
diff --git a/STM32_4路称重_Git提交精简工程/src/HARDWARE/SPI/spi.h b/STM32_4路称重_Git提交精简工程/src/HARDWARE/SPI/spi.h
new file mode 100755
index 0000000..3673ec2
--- /dev/null
+++ b/STM32_4路称重_Git提交精简工程/src/HARDWARE/SPI/spi.h
@@ -0,0 +1,10 @@
+#ifndef __SPI1_H
+#define __SPI1_H
+
+#include "stm32f10x.h"
+
+void SPI1_Init(void);
+uint8_t SPI1_ReadWriteByte(uint8_t writedat);
+   
+
+#endif
diff --git a/STM32_4路称重_Git提交精简工程/src/HARDWARE/STMFLASH/stmflash.c b/STM32_4路称重_Git提交精简工程/src/HARDWARE/STMFLASH/stmflash.c
new file mode 100755
index 0000000..b9dfd5e
--- /dev/null
+++ b/STM32_4路称重_Git提交精简工程/src/HARDWARE/STMFLASH/stmflash.c
@@ -0,0 +1,459 @@
+/*************************** (C) COPYRIGHT 2017 CXHY ****************************
+ * �ļ���  ��stmflash.c
+ * ��  ��  ��STM32-FLASH��������
+ * ��  ��  ��V1.0
+ * ��  ��  ��XuZhongPing
+ * ��  ��  ��2017/07/23 
+*********************************************************************************/
+#include "stmflash.h"
+#include "stdio.h"
+#include "delay.h"
+#include "timer.h"
+#include "gsm_gprs.h"
+#include "data_typedef.h"
+ 
+#if STM32_FLASH_SIZE < 256									//��������С������MCUһҳ�Ĵ�С��Ϊ1K�ֽ�
+#define STM_SECTOR_SIZE 1024 								//һҳ�ֽ���
+#else 
+#define STM_SECTOR_SIZE	2048
+#endif	
+	 
+uint16_t STMFLASH_BUF[STM_SECTOR_SIZE/2];		//���ڱ���һ�����������ݻ��棬��������ʱ���ȶ�ȡԭ����������ݣ�Ȼ��������д��
+
+/*
+***********************************************************************
+*	�� �� ��: STMFLASH_ReadHalfWord
+*	����˵��: ��ȡָ����ַ�İ���(16λ����)
+*	��    �Σ�faddr:����ַ(�˵�ַ����Ϊ2�ı���!!)
+*	�� �� ֵ: ��Ӧ��ַ���������
+***********************************************************************
+*/
+uint16_t STMFLASH_ReadHalfWord(uint32_t faddr)
+{
+	return *(vu16*)faddr; 
+}
+
+/*
+***********************************************************************
+*	�� �� ��: STMFLASH_Write_NoCheck
+*	����˵��: ��������ָ����ַд������
+*	��    �Σ�WriteAddr:��ʼ��ַ
+*						pBuffer:����ָ��
+*						NumToWrite:����(16λ)��
+*	�� �� ֵ: �� 
+***********************************************************************
+*/
+void STMFLASH_Write_NoCheck(uint32_t WriteAddr, uint16_t *pBuffer, uint16_t NumToWrite)   
+{ 			 		 
+	uint16_t i;
+	
+	for(i = 0; i < NumToWrite; i++)
+	{
+		FLASH_ProgramHalfWord(WriteAddr, pBuffer[i]);
+		WriteAddr += 2;																		//��ַ����2.
+	}  
+} 
+
+/*
+***********************************************************************
+*	�� �� ��: STMFLASH_Write
+*	����˵��: ��ָ����ַ��ʼд��ָ�����ȵ�����
+*	��    �Σ�WriteAddr:��ʼ��ַ(�˵�ַ����Ϊ2�ı���!!)
+*						pBuffer:����ָ��
+*						NumToWrite:����(16λ)��(����Ҫд���16λ���ݵĸ���.)
+*	�� �� ֵ: �� 
+***********************************************************************
+*/
+void STMFLASH_Write(uint32_t WriteAddr, uint16_t *pBuffer, uint16_t NumToWrite)	
+{
+	uint32_t secpos;	   								//������ַ
+	uint16_t secoff;	   								//������ƫ�Ƶ�ַ(16λ�ּ���)
+	uint16_t secremain; 								//������ʣ���ַ(16λ�ּ���)	    
+	uint32_t offaddr;   								//ȥ��0X08000000��ĵ�ַ
+	uint16_t i;   
+	
+	if((WriteAddr < STM32_FLASH_BASE) || (WriteAddr >= (STM32_FLASH_BASE + 1024*STM32_FLASH_SIZE)))return;	//�Ƿ���ַ
+	FLASH_Unlock();																		//����
+	offaddr = WriteAddr-STM32_FLASH_BASE;							//ʵ��ƫ�Ƶ�ַ.
+	secpos = offaddr/STM_SECTOR_SIZE;									//������ַ  0~127 for STM32F103RBT6
+	secoff = (offaddr%STM_SECTOR_SIZE)/2;							//�������ڵ�ƫ��(2���ֽ�Ϊ������λ.)
+	secremain = STM_SECTOR_SIZE/2 - secoff;						//����ʣ��ռ��С   
+	if(NumToWrite <= secremain)												//�����ڸ�������Χ
+	{
+		secremain = NumToWrite;
+	}
+	while(1) 
+	{	
+		STMFLASH_Read(secpos * STM_SECTOR_SIZE + STM32_FLASH_BASE, STMFLASH_BUF, STM_SECTOR_SIZE/2);		//������������������
+		for(i = 0; i < secremain; i++)									//У������
+		{
+			if(STMFLASH_BUF[secoff + i] != 0XFFFF)break;	//��Ҫ����  	  
+		}
+		if(i<secremain)			//��Ҫ����
+		{
+			FLASH_ErasePage(secpos * STM_SECTOR_SIZE + STM32_FLASH_BASE);	//�����������
+			for(i = 0; i < secremain; i++)								//����Ҫд�������
+			{
+				STMFLASH_BUF[i + secoff] = pBuffer[i];	  
+			}
+			STMFLASH_Write_NoCheck(secpos * STM_SECTOR_SIZE + STM32_FLASH_BASE, STMFLASH_BUF, STM_SECTOR_SIZE/2);		//д����������  
+		}else{			//д�Ѿ������˵�,ֱ��д������ʣ������.
+			STMFLASH_Write_NoCheck(WriteAddr,pBuffer,secremain);
+		}
+			 				   
+		if(NumToWrite == secremain)		//д�������
+		{
+			break;								
+		}else{		//д��δ����
+			secpos++;																			//������ַ��1
+			secoff = 0;																		//ƫ��λ��Ϊ0 	 
+			pBuffer += secremain;  												//ָ��ƫ��
+			WriteAddr += secremain;												//д��ַƫ��	   
+			NumToWrite -= secremain;											//�ֽ�(16λ)���ݼ�
+			if(NumToWrite > (STM_SECTOR_SIZE/2))					//��һ����������д����
+			{
+				secremain = STM_SECTOR_SIZE/2;
+			}else{		//��һ����������д����
+				secremain = NumToWrite;
+			}
+		}	 
+	}
+	FLASH_Lock();																			//����
+}
+
+/*
+***********************************************************************
+*	�� �� ��: STMFLASH_Read
+*	����˵��: ��ָ����ַ��ʼ����ָ�����ȵ�����
+*	��    �Σ�ReadAddr:��ʼ��ַ
+*						pBuffer:����ָ��
+*						NumToRead:����(16λ)��
+*	�� �� ֵ: �� 
+***********************************************************************
+*/
+void STMFLASH_Read(uint32_t ReadAddr, uint16_t *pBuffer, uint16_t NumToRead)   	
+{
+	uint16_t i;
+	
+	for(i = 0; i < NumToRead; i++)
+	{
+		pBuffer[i] = STMFLASH_ReadHalfWord(ReadAddr);				//��ȡ2���ֽ�.
+		ReadAddr += 2;																			//ƫ��2���ֽ�.	
+	}
+}
+
+
+/*
+***********************************************************************
+*	�� �� ��: STMFLASH_WriteHalfWord
+*	����˵��: ��ָ��FLASH��ַд��һ��16λ����
+*	��    �Σ�WriteAddr:��ʼ��ַ
+*						WriteData:Ҫд�������
+*	�� �� ֵ: �� 
+***********************************************************************
+*/
+void STMFLASH_WriteHalfWord(uint32_t WriteAddr, uint16_t WriteData)   	
+{
+// 	STMFLASH_Write(WriteAddr, &WriteData, 1);			//д��һ���֣�16λ�� 
+	FLASH_ProgramHalfWord(WriteAddr, WriteData);
+}
+
+/*
+***********************************************************************
+*	�� �� ��: DeviceConfigErase
+*	����˵��: ����������������flash
+*	��    �Σ���
+*	�� �� ֵ: �� 
+***********************************************************************
+*/
+void DeviceConfigErase(uint32_t WriteAddr)
+{
+	uint32_t secpos;	   								//������ַ
+	uint16_t secoff;	   								//������ƫ�Ƶ�ַ(16λ�ּ���)  
+	uint32_t offaddr;   								//ȥ��0X08000000��ĵ�ַ
+	
+	if((WriteAddr < STM32_FLASH_BASE) || (WriteAddr >= (STM32_FLASH_BASE + 1024*STM32_FLASH_SIZE)))return;	//�Ƿ���ַ
+	
+	offaddr = WriteAddr-STM32_FLASH_BASE;							//ʵ��ƫ�Ƶ�ַ.
+	secpos = offaddr/STM_SECTOR_SIZE;									//������ַ  0~127 for STM32F103RBT6
+
+	FLASH_ErasePage(secpos * STM_SECTOR_SIZE + STM32_FLASH_BASE);	//�����������
+}
+
+/*
+***********************************************************************
+*	�� �� ��: SaveDeviceConfig
+*	����˵��: �����豸���õĲ���
+*	��    �Σ���
+*	�� �� ֵ: �� 
+***********************************************************************
+*/
+void SaveDeviceConfig(void)
+{
+	uint8_t i = 0;
+	uint16_t uTempData = 0;
+	uint32_t flashSaveAddr = 0;
+	
+	flashSaveAddr = FLASH_SAVE_ADDR;
+	printf("\r\nTime1 = %d\r\n", time_value);
+	
+	FLASH_Unlock();																		//����
+	DeviceConfigErase(FLASH_SAVE_ADDR);
+	
+	//���ݱ���ɹ���־λ
+	uTempData = 0xFFFF;
+	STMFLASH_WriteHalfWord(flashSaveAddr, uTempData);
+	flashSaveAddr += 2;
+	
+	//�豸��������
+	uTempData = (uint16_t)(setPassword >> 16);
+	STMFLASH_WriteHalfWord(flashSaveAddr, uTempData);	
+	flashSaveAddr += 2;
+	uTempData = (uint16_t)setPassword;
+	STMFLASH_WriteHalfWord(flashSaveAddr, uTempData);
+	flashSaveAddr += 2;
+	
+	//�豸�ͻ���
+	uTempData = (uint16_t)(setCustomerID >> 16);
+	STMFLASH_WriteHalfWord(flashSaveAddr, uTempData);	
+	flashSaveAddr += 2;
+	uTempData = (uint16_t)setCustomerID;
+	STMFLASH_WriteHalfWord(flashSaveAddr, uTempData);
+	flashSaveAddr += 2;
+	
+	//�豸���ͼ�ͨ������
+	uTempData = (uint16_t)(setDeviceType << 8) | setDevChannelNumbers;
+	STMFLASH_WriteHalfWord(flashSaveAddr, uTempData);
+	flashSaveAddr += 2;
+	
+	//��1·Ͷ����ز���
+	uTempData = (uint16_t)(setDevChannel1Type << 8) | setDevChannel1DisDepthVal;
+	STMFLASH_WriteHalfWord(flashSaveAddr, uTempData);
+	flashSaveAddr += 2;
+	uTempData = (uint16_t)(setDevChannel1DisMaxVal << 8) | setDevChannel1DisAlarmPercent;
+	STMFLASH_WriteHalfWord(flashSaveAddr, uTempData);
+	flashSaveAddr += 2;
+	
+	//��2·Ͷ����ز���
+	uTempData = (uint16_t)(setDevChannel2Type << 8) | setDevChannel2DisDepthVal;
+	STMFLASH_WriteHalfWord(flashSaveAddr, uTempData);
+	flashSaveAddr += 2;
+	uTempData = (uint16_t)(setDevChannel2DisMaxVal << 8) | setDevChannel2DisAlarmPercent;
+	STMFLASH_WriteHalfWord(flashSaveAddr, uTempData);
+	flashSaveAddr += 2;
+	
+	//��3·Ͷ����ز���
+	uTempData = (uint16_t)(setDevChannel3Type << 8) | setDevChannel3DisDepthVal;
+	STMFLASH_WriteHalfWord(flashSaveAddr, uTempData);
+	flashSaveAddr += 2;
+	uTempData = (uint16_t)(setDevChannel3DisMaxVal << 8) | setDevChannel3DisAlarmPercent;
+	STMFLASH_WriteHalfWord(flashSaveAddr, uTempData);
+	flashSaveAddr += 2;
+	
+	//��4·Ͷ����ز���
+	uTempData = (uint16_t)(setDevChannel4Type << 8) | setDevChannel4DisDepthVal;
+	STMFLASH_WriteHalfWord(flashSaveAddr, uTempData);
+	flashSaveAddr += 2;
+	uTempData = (uint16_t)(setDevChannel4DisMaxVal << 8) | setDevChannel4DisAlarmPercent;
+	STMFLASH_WriteHalfWord(flashSaveAddr, uTempData);
+	flashSaveAddr += 2;
+	
+	flashSaveAddr += 24;			//Ԥ��32���ֽ����ڱ���Ͷ��ͨ������
+	
+	//����IC���û����ܺ���������IC����ά�빦�ܱ�־λ
+	uTempData = (uint16_t)(setDisableICCardFunStatus << 8) | setEnableCleanQRCodeStatus;
+	STMFLASH_WriteHalfWord(flashSaveAddr, uTempData);
+	flashSaveAddr += 2;
+	
+	//�豸��ų���
+	STMFLASH_WriteHalfWord(flashSaveAddr, setDeviceIdLength);
+	flashSaveAddr += 2;
+	
+	printf("\r\nTime2 = %d\r\n", time_value);
+	//�豸���
+	for(i = 0; i < 32; i+=2)
+	{
+		uTempData = (uint16_t)(setDeviceIdBuf[i] << 8) | setDeviceIdBuf[i+1];
+		STMFLASH_WriteHalfWord(flashSaveAddr, uTempData);
+		flashSaveAddr += 2;
+	}
+	printf("\r\nTime3 = %d\r\n", time_value);
+	
+	//������IP��ַ���˿ں�
+	uTempData = (uint16_t)(setIpAddr0 << 8) | setIpAddr1;
+	STMFLASH_WriteHalfWord(flashSaveAddr, uTempData);
+	flashSaveAddr += 2;
+	uTempData = (uint16_t)(setIpAddr2 << 8) | setIpAddr3;
+	STMFLASH_WriteHalfWord(flashSaveAddr, uTempData);
+	flashSaveAddr += 2;
+	STMFLASH_WriteHalfWord(flashSaveAddr, setIpPort);
+	flashSaveAddr += 2;
+	
+	//��־�����������
+	uTempData = 0x0A0B;
+	STMFLASH_WriteHalfWord(FLASH_SAVE_ADDR, uTempData);
+	FLASH_Lock();																			//����
+	
+	printf("\r\nTime4 = %d\r\n", time_value);
+	printf("\r\n��������ɹ���\r\n");
+}
+
+/*
+***********************************************************************
+*	�� �� ��: GetDeviceConfig
+*	����˵��: ȡ���豸���ò���
+*	��    �Σ���
+*	�� �� ֵ: �� 
+***********************************************************************
+*/
+uint8_t GetDeviceConfig(void)
+{
+	uint8_t i = 0;
+	uint16_t uTempData = 0;
+	uint32_t flashSaveAddr = 0;
+	
+	flashSaveAddr = FLASH_SAVE_ADDR;
+	
+	uTempData = STMFLASH_ReadHalfWord(flashSaveAddr);
+	flashSaveAddr += 2;
+
+	if(uTempData == 0x0A0B)
+	{
+		//�豸��������
+		uTempData = STMFLASH_ReadHalfWord(flashSaveAddr);
+		flashSaveAddr += 2;
+		setPassword = uTempData;
+		uTempData = STMFLASH_ReadHalfWord(flashSaveAddr);
+		flashSaveAddr += 2;
+		setPassword = (setPassword << 16) | uTempData;
+		
+		//�豸�ͻ���
+		uTempData = STMFLASH_ReadHalfWord(flashSaveAddr);
+		flashSaveAddr += 2;
+		setCustomerID = uTempData;
+		uTempData = STMFLASH_ReadHalfWord(flashSaveAddr);
+		flashSaveAddr += 2;
+		setCustomerID = (setCustomerID << 16) | uTempData;
+		
+		//�豸����
+		uTempData = STMFLASH_ReadHalfWord(flashSaveAddr);
+		flashSaveAddr += 2;
+		setDeviceType = uTempData >> 8;
+		setDevChannelNumbers = (uint8_t)uTempData;
+		
+		//��1·Ͷ����ز���
+		uTempData = STMFLASH_ReadHalfWord(flashSaveAddr);
+		flashSaveAddr += 2;
+		setDevChannel1Type = uTempData >> 8;
+		setDevChannel1DisDepthVal = (uint8_t)uTempData;
+		uTempData = STMFLASH_ReadHalfWord(flashSaveAddr);
+		flashSaveAddr += 2;
+		setDevChannel1DisMaxVal = uTempData >> 8;
+		setDevChannel1DisAlarmPercent = (uint8_t)uTempData;
+		
+		//��2·Ͷ����ز���
+		uTempData = STMFLASH_ReadHalfWord(flashSaveAddr);
+		flashSaveAddr += 2;
+		setDevChannel2Type = uTempData >> 8;
+		setDevChannel2DisDepthVal = (uint8_t)uTempData;
+		uTempData = STMFLASH_ReadHalfWord(flashSaveAddr);
+		flashSaveAddr += 2;
+		setDevChannel2DisMaxVal = uTempData >> 8;
+		setDevChannel2DisAlarmPercent = (uint8_t)uTempData;
+		
+		//��3·Ͷ����ز���
+		uTempData = STMFLASH_ReadHalfWord(flashSaveAddr);
+		flashSaveAddr += 2;
+		setDevChannel3Type = uTempData >> 8;
+		setDevChannel3DisDepthVal = (uint8_t)uTempData;
+		uTempData = STMFLASH_ReadHalfWord(flashSaveAddr);
+		flashSaveAddr += 2;
+		setDevChannel3DisMaxVal = uTempData >> 8;
+		setDevChannel3DisAlarmPercent = (uint8_t)uTempData;
+		
+		//��4·Ͷ����ز���
+		uTempData = STMFLASH_ReadHalfWord(flashSaveAddr);
+		flashSaveAddr += 2;
+		setDevChannel4Type = uTempData >> 8;
+		setDevChannel4DisDepthVal = (uint8_t)uTempData;
+		uTempData = STMFLASH_ReadHalfWord(flashSaveAddr);
+		flashSaveAddr += 2;
+		setDevChannel4DisMaxVal = uTempData >> 8;
+		setDevChannel4DisAlarmPercent = (uint8_t)uTempData;
+		
+		flashSaveAddr += 24;
+		
+		//����IC���û����ܺ���������IC����ά�빦�ܱ�־λ
+		uTempData = STMFLASH_ReadHalfWord(flashSaveAddr);
+		flashSaveAddr += 2;
+		setDisableICCardFunStatus = uTempData >> 8;
+		setEnableCleanQRCodeStatus = (uint8_t)uTempData;	
+		
+		//�豸��ų���
+		uTempData = STMFLASH_ReadHalfWord(flashSaveAddr);
+		flashSaveAddr += 2;
+		setDeviceIdLength = uTempData;
+		
+		//�豸���
+		for(i = 0; i < 32; i+=2)
+		{
+			uTempData = STMFLASH_ReadHalfWord(flashSaveAddr);
+			flashSaveAddr += 2;
+			setDeviceIdBuf[i] = uTempData >> 8;
+			setDeviceIdBuf[i+1] = (uint8_t)uTempData;				
+		}
+		
+		//������IP��ַ���˿ں�
+		uTempData = STMFLASH_ReadHalfWord(flashSaveAddr);
+		flashSaveAddr += 2;
+		setIpAddr0 = uTempData >> 8;
+		setIpAddr1 = (uint8_t)uTempData;
+		uTempData = STMFLASH_ReadHalfWord(flashSaveAddr);
+		flashSaveAddr += 2;
+		setIpAddr2 = uTempData >> 8;
+		setIpAddr3 = (uint8_t)uTempData;
+		uTempData = STMFLASH_ReadHalfWord(flashSaveAddr);
+		flashSaveAddr += 2;
+		setIpPort = uTempData;
+		
+		printf("\r\n������ȡ�ɹ���\r\n");
+		
+		printf("\r\nSet P=%d; ID=%d; Type=%d; Cnt=%d; T1=%d, h1=%d, H1=%d, A1=%d; T2=%d, h2=%d, H2=%d, A2=%d, ICE=%d; ICQR=%d; "\
+						"devLen=%d; devID=%s; IP=%d.%d.%d.%d:%d\r\n",
+						setPassword,
+						setCustomerID,
+						setDeviceType,
+						setDevChannelNumbers,
+						setDevChannel1Type, setDevChannel1DisDepthVal, setDevChannel1DisMaxVal, setDevChannel1DisAlarmPercent,
+						setDevChannel2Type, setDevChannel2DisDepthVal, setDevChannel2DisMaxVal, setDevChannel2DisAlarmPercent,
+						setDisableICCardFunStatus,
+						setEnableCleanQRCodeStatus,
+						setDeviceIdLength,
+						setDeviceIdBuf,
+						setIpAddr0,setIpAddr1,setIpAddr2,setIpAddr3,setIpPort
+					);
+						
+		return 0;
+	}else{
+		printf("\r\n��û�б�����豸������\r\n");
+		return 1;
+	}
+}
+
+/*
+***********************************************************************
+*	�� �� ��: ResetDeviceConfig
+*	����˵��: �ָ��豸���ò�������������
+*	��    �Σ���
+*	�� �� ֵ: �� 
+***********************************************************************
+*/
+void ResetDeviceConfig(void)
+{
+	FLASH_Unlock();																		//����
+	DeviceConfigErase(FLASH_SAVE_ADDR);
+	FLASH_Lock();																			//����
+	printf("\r\n�豸���ò����ѻָ��ɳ������ã�\r\n");
+}
+
+/******************** (C) COPYRIGHT 2017 CXHY *****END OF FILE*******************/
diff --git a/STM32_4路称重_Git提交精简工程/src/HARDWARE/STMFLASH/stmflash.h b/STM32_4路称重_Git提交精简工程/src/HARDWARE/STMFLASH/stmflash.h
new file mode 100755
index 0000000..e8bf6fe
--- /dev/null
+++ b/STM32_4路称重_Git提交精简工程/src/HARDWARE/STMFLASH/stmflash.h
@@ -0,0 +1,32 @@
+/*************************** (C) COPYRIGHT 2017 CXHY ****************************
+ * �ļ���  ��stmflash.c
+ * ��  ��  ��STM32-FLASH��������
+ * ��  ��  ��V1.0
+ * ��  ��  ��XuZhongPing
+ * ��  ��  ��2017/07/23 
+*********************************************************************************/
+#ifndef __STMFLASH_H__
+#define __STMFLASH_H__
+#include "stm32f10x.h"
+
+#define STM32_FLASH_SIZE 512 	 					//��ѡSTM32��FLASH������С(��λΪK)
+#define STM32_FLASH_WREN 1              //ʹ��FLASHд��(0��������;1��ʹ��)
+
+//FLASH��ַ
+#define STM32_FLASH_BASE 0x08000000 		//STM32 FLASH����ʼ��ַ
+#define FLASH_SAVE_ADDR  0X0807F800 		//����FLASH �����ַ(����Ϊż��) 
+ 
+
+uint16_t STMFLASH_ReadHalfWord(uint32_t faddr);		  																//��������  
+uint32_t STMFLASH_ReadLenByte(uint32_t ReadAddr, uint16_t Len);											//ָ����ַ��ʼ��ȡָ����������
+void STMFLASH_Write(uint32_t WriteAddr, uint16_t *pBuffer, uint16_t NumToWrite);		//��ָ����ַ��ʼд��ָ�����ȵ�����
+void STMFLASH_Read(uint32_t ReadAddr, uint16_t *pBuffer, uint16_t NumToRead);   		//��ָ����ַ��ʼ����ָ�����ȵ�����
+void STMFLASH_WriteHalfWord(uint32_t WriteAddr, uint16_t WriteData);								//��ָ����ַ��д��һ�����֣�16λ��					   
+
+void SaveDeviceConfig(void);
+uint8_t GetDeviceConfig(void);
+void ResetDeviceConfig(void);
+
+#endif
+
+/******************** (C) COPYRIGHT 2017 CXHY *****END OF FILE*******************/
diff --git a/STM32_4路称重_Git提交精简工程/src/HARDWARE/TIMER/timer.c b/STM32_4路称重_Git提交精简工程/src/HARDWARE/TIMER/timer.c
new file mode 100755
index 0000000..0b96b26
--- /dev/null
+++ b/STM32_4路称重_Git提交精简工程/src/HARDWARE/TIMER/timer.c
@@ -0,0 +1,353 @@
+/*************************** (C) COPYRIGHT 2018 Ping ****************************
+ * �ļ���  ��timer.c
+ * ��  ��  ����ʱ����������     
+ * ��  ��  ��V1.0
+ * ��  ��  ��XuZhongPing
+ * ��  ��  ��2017/02/07 
+*********************************************************************************/
+#include "timer.h"
+#include "usart1.h"
+#include "device.h"
+#include "data_typedef.h"
+
+uint32_t time_value = 0;//uip ��ʱ����ÿ10ms����1.
+
+/*
+***********************************************************************
+*	�� �� ��: clock_time
+*	����˵��: ȡ�õ�ǰ��ʱֵ
+*	��    ��: ��
+*	�� �� ֵ: ��ǰ��ʱֵ
+***********************************************************************
+*/
+clock_time_t clock_time(void)
+{
+	return time_value; /* 10ms ��λ */	 
+}
+
+/*
+***********************************************************************
+*	�� �� ��: timer_set
+*	����˵��: ����һ����ʱ���
+*	��    ��:	
+*						t:��ʱ����
+*						interval����ʱ���ֵ
+*	�� �� ֵ: ��
+***********************************************************************
+*/
+void timer_set(timer *t, clock_time_t interval)
+{
+  t->interval = interval;
+  t->start = clock_time();
+}
+
+/*
+***********************************************************************
+*	�� �� ��: timer_reset
+*	����˵��: �Զ�ʱ�������и�λ
+*	��    ��:	
+*						t:��ʱ����
+*	�� �� ֵ: ��
+***********************************************************************
+*/
+void timer_reset(timer *t)
+{
+  t->start += t->interval;
+}
+
+/*
+***********************************************************************
+*	�� �� ��: timer_reset_interval
+*	����˵��: �������ö�ʱʱ��
+*	��    ��:	
+*						t:��ʱ����
+*	�� �� ֵ: ��
+***********************************************************************
+*/
+void timer_reset_interval(timer *t, clock_time_t interval)
+{
+  t->interval = interval;
+}
+
+/*
+***********************************************************************
+*	�� �� ��: timer_restart
+*	����˵��: �ӵ�ǰʱ�������������ʱ��
+*	��    ��:	
+*						t:��ʱ����
+*	�� �� ֵ: ��
+***********************************************************************
+*/
+void timer_restart(timer *t)
+{
+  t->start = clock_time();
+}
+
+/*
+***********************************************************************
+*	�� �� ��: timer_expired
+*	����˵��: �ж�һ����ʱ���Ƿ�ﵽ��ʱʱ��
+*	��    ��:	
+*						t:��ʱ����
+*	�� �� ֵ: �������Ѿ����˶�ʱʱ�䣬����ʱ��δ��
+***********************************************************************
+*/
+int timer_expired(timer *t)
+{
+  return (clock_time_t)(clock_time() - t->start) >= (clock_time_t)t->interval;
+}
+
+/*
+***********************************************************************
+*	�� �� ��: timer_remaining
+*	����˵��: �ж�һ����ʱ����ʣ�¶���ʱ��ﵽ��ʱʱ��
+*	��    ��:	
+*						t:��ʱ����
+*	�� �� ֵ: ���ض�ʱ��ʣ��ʱ��
+***********************************************************************
+*/
+uint32_t timer_remaining(timer *t)
+{
+	uint32_t res = 0;
+	
+	if(clock_time() < (t->start + (clock_time_t)t->interval))
+	{
+		res = (t->start + (clock_time_t)t->interval) - clock_time();
+		return res;
+	}else{
+		return 0;
+	}
+}
+
+//��ʱ����ʱ��2���ڿ�ʼһ��������ʱ���ⲿ����ʹ��
+//��λΪ100ms(0.1S)
+/*
+***********************************************************************
+*	�� �� ��: TIM2_Int_Init
+*	����˵��: ��ʱ��2��ʼ������
+*	��    �Σ�arr���Զ���װֵ
+*						psc��ʱ��Ԥ��Ƶ��
+*	�� �� ֵ: ��
+***********************************************************************
+*/
+void TIM2_Int_Init(uint16_t arr,uint16_t psc)
+{
+  TIM_TimeBaseInitTypeDef  TIM_TimeBaseStructure;
+	NVIC_InitTypeDef NVIC_InitStructure;
+
+	RCC_APB1PeriphClockCmd(RCC_APB1Periph_TIM2, ENABLE); 					//ʱ��ʹ��
+
+	TIM_TimeBaseStructure.TIM_Period = arr; 											//��������һ�������¼�װ�����Զ���װ�ؼĴ������ڵ�ֵ	 ������5000Ϊ500ms
+	TIM_TimeBaseStructure.TIM_Prescaler = psc; 										//����������ΪTIMxʱ��Ƶ�ʳ�����Ԥ��Ƶֵ  10Khz�ļ���Ƶ�ʣ���0.1ms���ڣ�  
+	TIM_TimeBaseStructure.TIM_ClockDivision = 0; 									//����ʱ�ӷָ�:TDTS = Tck_tim
+	TIM_TimeBaseStructure.TIM_CounterMode = TIM_CounterMode_Up;  	//TIM���ϼ���ģʽ
+	TIM_TimeBaseInit(TIM2, &TIM_TimeBaseStructure); 							//����TIM_TimeBaseInitStruct��ָ���Ĳ�����ʼ��TIMx��ʱ�������λ
+ 
+	TIM_ITConfig( TIM2, TIM_IT_Update|TIM_IT_Trigger, ENABLE);		//ʹ�ܶ�ʱ��2���´����ж�
+	TIM_Cmd(TIM2, ENABLE);  																			//ʹ��TIMx����
+	
+	NVIC_InitStructure.NVIC_IRQChannel = TIM2_IRQn;  							//TIM3�ж�
+	NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0;  		//��ռ���ȼ�0��
+	NVIC_InitStructure.NVIC_IRQChannelSubPriority = 3;  					//�����ȼ�3��
+	NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE; 							//IRQͨ����ʹ��
+	NVIC_Init(&NVIC_InitStructure);  															//����NVIC_InitStruct��ָ���Ĳ�����ʼ������NVIC�Ĵ���				 
+}
+
+/*
+***********************************************************************
+*	�� �� ��: TIM2_IRQHandler
+*	����˵��: ��ʱ��2�жϷ����ӳ���
+*	��    �Σ���
+*	�� �� ֵ: ��
+***********************************************************************
+*/
+void TIM2_IRQHandler(void)   //TIM2�ж�
+{
+	if (TIM_GetITStatus(TIM2, TIM_IT_Update) != RESET) //���ָ����TIM�жϷ������:TIM �ж�Դ 
+	{
+		time_value++;						//��ʱ������1	
+	}
+	TIM_ClearITPendingBit(TIM2, TIM_IT_Update);  //���TIMx���жϴ�����λ:TIM �ж�Դ 
+}
+
+/////////////////////////////////////////////////////////////////////////////////////////////////
+//��ʱ��3���֣����ڰ���ɨ�裩ÿ10ms�ж�һ��
+/*
+***********************************************************************
+*	�� �� ��: TIM3_Int_Init
+*	����˵��: ��ʱ��3��ʼ������
+*	��    �Σ�arr���Զ���װֵ
+*						psc��ʱ��Ԥ��Ƶ��
+*	�� �� ֵ: ��
+***********************************************************************
+*/
+void TIM3_Int_Init(uint16_t arr,uint16_t psc)
+{
+  TIM_TimeBaseInitTypeDef  TIM_TimeBaseStructure;
+	NVIC_InitTypeDef NVIC_InitStructure;
+
+	RCC_APB1PeriphClockCmd(RCC_APB1Periph_TIM3, ENABLE); 					//ʱ��ʹ��
+
+	TIM_TimeBaseStructure.TIM_Period = arr; 											//��������һ�������¼�װ�����Զ���װ�ؼĴ������ڵ�ֵ
+	TIM_TimeBaseStructure.TIM_Prescaler = psc; 										//����������ΪTIMxʱ��Ƶ�ʳ�����Ԥ��Ƶֵ  10Khz�ļ���Ƶ�ʣ���0.1ms���ڣ�  
+	TIM_TimeBaseStructure.TIM_ClockDivision = 0; 									//����ʱ�ӷָ�:TDTS = Tck_tim
+	TIM_TimeBaseStructure.TIM_CounterMode = TIM_CounterMode_Up;  	//TIM���ϼ���ģʽ
+	TIM_TimeBaseInit(TIM3, &TIM_TimeBaseStructure); 							//����TIM_TimeBaseInitStruct��ָ���Ĳ�����ʼ��TIMx��ʱ�������λ
+ 
+	TIM_ITConfig( TIM3, TIM_IT_Update|TIM_IT_Trigger, ENABLE);		//ʹ�ܶ�ʱ��2���´����ж�
+	TIM_Cmd(TIM3, ENABLE);  																			//ʹ��TIMx����
+	
+	NVIC_InitStructure.NVIC_IRQChannel = TIM3_IRQn;  							//TIM3�ж�
+	NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 2;  		//��ռ���ȼ�0��
+	NVIC_InitStructure.NVIC_IRQChannelSubPriority = 2;  					//�����ȼ�3��
+	NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE; 							//IRQͨ����ʹ��
+	NVIC_Init(&NVIC_InitStructure);  															//����NVIC_InitStruct��ָ���Ĳ�����ʼ������NVIC�Ĵ���			 
+}
+
+/*
+***********************************************************************
+*	�� �� ��: TIM3_IRQHandler
+*	����˵��: ��ʱ��2�жϷ����ӳ���
+*	��    �Σ���
+*	�� �� ֵ: ��
+***********************************************************************
+*/
+void TIM3_IRQHandler(void)   //TIM3�ж�
+{
+	uint8_t keyTemp = 0;
+	static uint8_t timerCut = 0;
+	
+	if (TIM_GetITStatus(TIM3, TIM_IT_Update) != RESET) 	//���ָ����TIM�жϷ������:TIM �ж�Դ 
+	{
+		if(deviceInitFlag == 1)
+		{
+// 			OptoKeyScanning();
+// 			BottleScanning();																	//����ƿ��ɨ���⺯��
+			
+			if(keyType == 0)
+			{
+				keyTemp = KeyScanning();				
+			}else if(keyType == 1){
+				keyTemp = TouchKeyScanning();
+			}
+
+			if(keyTemp != 0)
+			{		
+				keyValue = keyTemp;															//�����ֵ���ⲿ��ȡ�����
+			}
+		}
+	}
+	TIM_ClearITPendingBit(TIM3, TIM_IT_Update);  				//���TIMx���жϴ�����λ:TIM �ж�Դ 
+}
+
+/////////////////////////////////////////////////////////////////////////////////////////////////
+//��ʱ��4���֣����ڳ�������ࣩ
+/*
+***********************************************************************
+*	�� �� ��: TIM4_Int_Init
+*	����˵��: ��ʱ��4��ʼ������
+*	��    �Σ�arr���Զ���װֵ
+*						psc��ʱ��Ԥ��Ƶ��
+*	�� �� ֵ: ��
+***********************************************************************
+*/
+void TIM4_Int_Init(u16 arr,u16 psc)
+{
+	TIM_TimeBaseInitTypeDef  TIM_TimeBaseStructure;
+	NVIC_InitTypeDef NVIC_InitStructure;
+
+	RCC_APB1PeriphClockCmd(RCC_APB1Periph_TIM4, ENABLE); 					//ʱ��ʹ��
+	
+	//��ʱ��TIM4��ʼ��
+	TIM_TimeBaseStructure.TIM_Period = arr; 											//��������һ�������¼�װ�����Զ���װ�ؼĴ������ڵ�ֵ	
+	TIM_TimeBaseStructure.TIM_Prescaler =psc; 										//����������ΪTIMxʱ��Ƶ�ʳ�����Ԥ��Ƶֵ
+	TIM_TimeBaseStructure.TIM_ClockDivision = TIM_CKD_DIV1; 			//����ʱ�ӷָ�:TDTS = Tck_tim
+	TIM_TimeBaseStructure.TIM_CounterMode = TIM_CounterMode_Up;  	//TIM���ϼ���ģʽ
+	TIM_TimeBaseInit(TIM4, &TIM_TimeBaseStructure); 							//����ָ���Ĳ�����ʼ��TIMx��ʱ�������λ
+ 
+	TIM_ITConfig(TIM4, TIM_IT_Update | TIM_IT_Trigger, ENABLE); 	//ʹ��ָ����TIM4�ж�,���������ж�
+
+	//�ж����ȼ�NVIC����
+	NVIC_InitStructure.NVIC_IRQChannel = TIM4_IRQn;  						
+	NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 2; 
+	NVIC_InitStructure.NVIC_IRQChannelSubPriority = 2; 
+	NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE; 
+	NVIC_Init(&NVIC_InitStructure);
+
+	TIM_Cmd(TIM4, DISABLE);
+// 	TIM_Cmd(TIM4, ENABLE);			 
+}
+
+/*
+***********************************************************************
+*	�� �� ��: TIM4_IRQHandler
+*	����˵��: ��ʱ��4�жϷ����ӳ���
+*	��    �Σ���
+*	�� �� ֵ: ��
+***********************************************************************
+*/
+void TIM4_IRQHandler(void)   //TIM4�ж�
+{
+	if (TIM_GetITStatus(TIM4, TIM_IT_Update) != RESET)  //���TIM4�����жϷ������
+	{
+		TIM_ClearITPendingBit(TIM4, TIM_IT_Update);  //���TIMx�����жϱ�־ 
+	}
+}
+
+/////////////////////////////////////////////////////////////////////////////////////////////////
+//��ʱ��4���֣����ڶ�ά���ͷ���ݽ�����ɱ���ã�
+/*
+***********************************************************************
+*	�� �� ��: TIM5_Int_Init
+*	����˵��: ��ʱ��5��ʼ������
+*	��    �Σ�arr���Զ���װֵ
+*						psc��ʱ��Ԥ��Ƶ��
+*	�� �� ֵ: ��
+***********************************************************************
+*/
+void TIM5_Int_Init(uint16_t arr, uint16_t psc)
+{
+	TIM_TimeBaseInitTypeDef  TIM_TimeBaseStructure;
+	NVIC_InitTypeDef NVIC_InitStructure;
+
+	RCC_APB1PeriphClockCmd(RCC_APB1Periph_TIM5, ENABLE);
+	
+	//��ʱ��TIM5��ʼ��
+	TIM_TimeBaseStructure.TIM_Period = arr; 											//��������һ�������¼�װ�����Զ���װ�ؼĴ������ڵ�ֵ	
+	TIM_TimeBaseStructure.TIM_Prescaler =psc; 										//����������ΪTIMxʱ��Ƶ�ʳ�����Ԥ��Ƶֵ
+	TIM_TimeBaseStructure.TIM_ClockDivision = TIM_CKD_DIV1; 			//����ʱ�ӷָ�:TDTS = Tck_tim
+	TIM_TimeBaseStructure.TIM_CounterMode = TIM_CounterMode_Up;  	//TIM���ϼ���ģʽ
+	TIM_TimeBaseInit(TIM5, &TIM_TimeBaseStructure); 							//����ָ���Ĳ�����ʼ��TIMx��ʱ�������λ
+ 
+	TIM_ITConfig(TIM5,TIM_IT_Update,ENABLE ); 										//ʹ��ָ����TIM4�ж�,���������ж�
+
+	//�ж����ȼ�NVIC����
+	NVIC_InitStructure.NVIC_IRQChannel = TIM5_IRQn;  							//TIM5�ж�
+	NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 3;  		//��ռ���ȼ�3��
+	NVIC_InitStructure.NVIC_IRQChannelSubPriority = 2;  					//�����ȼ�2��
+	NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE; 							//IRQͨ����ʹ��
+	NVIC_Init(&NVIC_InitStructure);  															//��ʼ��NVIC�Ĵ���
+
+	TIM_Cmd(TIM5, DISABLE);  																			//ʧ��TIMx����			 
+}
+
+/*
+***********************************************************************
+*	�� �� ��: TIM5_IRQHandler
+*	����˵��: ��ʱ��4�жϷ����ӳ���
+*	��    �Σ���
+*	�� �� ֵ: ��
+***********************************************************************
+*/
+void TIM5_IRQHandler(void)
+{
+	if(TIM_GetITStatus(TIM5, TIM_IT_Update) != RESET)  	//���TIM5�����жϷ������
+	{
+		USART1_RX_STA |= 1<<15;														//��ǽ������
+		TIM_ClearITPendingBit(TIM5, TIM_IT_Update);  			//���TIMx�����жϱ�־ 
+		TIM_Cmd(TIM5, DISABLE);  	 												//�ر�TIMx
+	}
+}
+
+/******************** (C) COPYRIGHT 2018 Ping *****END OF FILE*******************/
+
diff --git a/STM32_4路称重_Git提交精简工程/src/HARDWARE/TIMER/timer.h b/STM32_4路称重_Git提交精简工程/src/HARDWARE/TIMER/timer.h
new file mode 100755
index 0000000..02ac6cf
--- /dev/null
+++ b/STM32_4路称重_Git提交精简工程/src/HARDWARE/TIMER/timer.h
@@ -0,0 +1,35 @@
+#ifndef __TIMER_H
+#define __TIMER_H
+
+#include "stm32f10x.h"
+
+typedef uint32_t clock_time_t;
+#define CLOCK_CONF_SECOND 10
+#define CLOCK_SECOND CLOCK_CONF_SECOND
+extern uint32_t time_value;					//��ʱ��ֵ
+
+
+typedef struct _timer {
+  clock_time_t start;
+  clock_time_t interval;
+}timer;
+
+void timer_set(timer *t, clock_time_t interval);
+void timer_reset(timer *t);
+void timer_reset_interval(timer *t, clock_time_t interval);
+void timer_restart(timer *t);
+int timer_expired(timer *t);
+uint32_t timer_remaining(timer *t);
+
+void TIM2_Int_Init(u16 arr,u16 psc); 
+
+// void TIM2_Int_Init(u16 arr,u16 psc);
+void TIM3_Int_Init(u16 arr,u16 psc);
+void TIM3_Period_Reset(u16 arr);
+
+void TIM4_Int_Init(u16 arr,u16 psc);
+void TIM5_Int_Init(u16 arr,u16 psc);
+
+void TIM6_Int_Init(u16 arr,u16 psc);
+ 
+#endif
diff --git a/STM32_4路称重_Git提交精简工程/src/HARDWARE/USART/RS485.c b/STM32_4路称重_Git提交精简工程/src/HARDWARE/USART/RS485.c
new file mode 100755
index 0000000..dc3f642
--- /dev/null
+++ b/STM32_4路称重_Git提交精简工程/src/HARDWARE/USART/RS485.c
@@ -0,0 +1,453 @@
+/*************************** (C) COPYRIGHT 2017 CXHY ****************************
+ * �ļ���  ��RS485.c
+ * ��  ��  ��RS485ͨ�Ŵ�������������3���֣�����֡���򡢷���֡����ִ���������     
+ * ��  ��  ��V1.0
+ * ��  ��  ��XuZhongPing
+ * ��  ��  ��2017/02/10
+*********************************************************************************/
+#include "delay.h"
+#include "sys.h"
+#include "RS485.h"
+#include "usart.h"
+#include "timer.h"
+#include "DataProcessing.h"	 
+#include "message.h"
+
+/*ͨѶ��������*/
+#define BaudRate 19200 								//������1200bps
+
+uint8_t Address = 0x00;								//�豸��ַ
+uint8_t RS485_RX_BUF[128];  					//���ջ���,���64���ֽ�
+uint8_t RS485_TX_BUF[64]; 						//���ͻ���,���64���ֽ�
+
+//�������������
+uint8_t RS485_RX_STA = 0x00; 					//RS485����״̬���
+uint8_t RS485_communicationStatus;		//RS485ͨѶ�ɹ�����־
+uint16_t RS485_serialNumber;					//RS485ͨ����ˮ��
+uint16_t RS485_RX_serialNumber;				//RS485ͨ����ˮ��
+uint8_t rxCmd;												//�ӻ����ص�ָ����
+
+/*
+***********************************************************************
+*	�� �� ��: RS485_Init
+*	����˵��: ��ʼ��RS485�ӿ�
+*	��    ��:	��
+*	�� �� ֵ: ��
+***********************************************************************
+*/
+void RS485_Init(void)
+{
+	//GPIO�˿�����
+	GPIO_InitTypeDef GPIO_InitStructure;
+	USART_InitTypeDef USART_InitStructure;
+	NVIC_InitTypeDef NVIC_InitStructure;
+	 
+	RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOA, ENABLE);		//ʹ��GPIOAʱ��
+	RCC_APB1PeriphClockCmd(RCC_APB1Periph_USART2, ENABLE);	//ʹ��USART2ʱ��
+	
+	//RS485_TX_EN  PA.0  RS485���ͽ��տ��ƽ�
+	GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0;				 				//PA0�˿�����
+ 	GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP; 		 		//�������
+ 	GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
+ 	GPIO_Init(GPIOA, &GPIO_InitStructure);
+	GPIO_ResetBits(GPIOA, GPIO_Pin_0);    									//���0��Ĭ�Ͻ���״̬
+	
+	//USART2_TX   PA.2
+	GPIO_InitStructure.GPIO_Pin = GPIO_Pin_2; 							//PA.2
+	GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
+	GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;					//�����������
+	GPIO_Init(GPIOA, &GPIO_InitStructure); 									//��ʼ��PA2
+ 
+	//USART2_RX	  PA.3
+	GPIO_InitStructure.GPIO_Pin = GPIO_Pin_3;
+	GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;		//��������
+	GPIO_Init(GPIOA, &GPIO_InitStructure);  								//��ʼ��PA3
+
+	//USART ��ʼ������
+
+	USART_InitStructure.USART_BaudRate = BaudRate;										//һ������Ϊ9600;
+	USART_InitStructure.USART_WordLength = USART_WordLength_8b;				//�ֳ�Ϊ8λ���ݸ�ʽ
+	USART_InitStructure.USART_StopBits = USART_StopBits_1;						//һ��ֹͣλ
+	USART_InitStructure.USART_Parity = USART_Parity_No;								//����żУ��λ
+	USART_InitStructure.USART_HardwareFlowControl = USART_HardwareFlowControl_None;	//��Ӳ������������
+	USART_InitStructure.USART_Mode = USART_Mode_Rx | USART_Mode_Tx;		//�շ�ģʽ
+	USART_Init(USART2, &USART_InitStructure); //��ʼ������
+	
+	//Usart2 NVIC ����
+	NVIC_InitStructure.NVIC_IRQChannel = USART2_IRQn;
+	NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0 ;				//��ռ���ȼ�0
+	NVIC_InitStructure.NVIC_IRQChannelSubPriority = 1;								//�����ȼ�0
+	NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;										//IRQͨ��ʹ��
+	NVIC_Init(&NVIC_InitStructure);																		//����ָ���Ĳ�����ʼ��VIC�Ĵ���
+   
+	USART_ITConfig(USART2, USART_IT_RXNE, ENABLE);										//�����ж�
+	USART_Cmd(USART2, ENABLE);                    										//ʹ�ܴ��� 
+}
+
+/*
+***********************************************************************
+*	�� �� ��: USART2_IRQHandler
+*	����˵��: ����2�жϷ����Ӻ���������RS485����
+*	��    ��:	��
+*	�� �� ֵ: ��
+***********************************************************************
+*/
+void USART2_IRQHandler(void)
+{
+	uint8_t res;
+	static uint8_t RX_State = 0;						//����״̬
+	static uint8_t CS = 0;		  						//���պ����
+	static uint8_t RX_Size = 0;							//����ͨѶ���ݳ���
+	static uint8_t Byte_Count = 0;	  			//���������ֽڼ���
+
+	if(USART_GetITStatus(USART2, USART_IT_RXNE) != RESET)
+	{
+		res = USART_ReceiveData(USART2);	//��ȡ���յ�������
+// 		printf("RX_DATA = %x\r\n", res);
+		switch(RX_State)
+		{
+			case 0:	  //��һǰ���ֽ�
+				if(res == 0xfe){
+					RX_State = 1;
+				}else{
+					RX_State = 0;
+				}
+				break;
+			case 1:	  //�ڶ�ǰ���ֽ�
+				if(res == 0xfe){
+					RX_State = 1;						//ת������֡ͷ
+				}else{
+					if(res == 0x68)
+					{
+						RX_State = 3;						//ת�������豸ͨѶ��ַ
+						CS = 0x68;
+					}else{
+						RX_State = 0;
+					}
+				}
+				break;
+// 			case 2:	  //����֡ͷ
+// 				if(res == 0x68){
+// 					RX_State = 3;						//ת�������豸ͨѶ��ַ
+// 					CS = 0x68;
+// 				}else{
+// 					RX_State = 0;
+// 				}
+// 				break;
+			case 3:		//�����豸ͨѶ��ַ
+				RS485_RX_BUF[0] = res;
+				CS += res;
+				RX_State = 4;
+				break;
+			case 4:	  //����֡ͷ
+				if(res == 0x68){
+					RX_State = 5;						//ת������ͨѶ����
+					CS += 0x68;
+				}else{
+					RX_State = 0;
+				}
+				break;
+			case 5:		//����ͨѶ����
+				RS485_RX_BUF[1] = res;
+				CS += res;
+				RX_State = 6;							//ת���������ݳ���
+				break;
+			case 6:		//����ͨѶ���ݳ���
+				RS485_RX_BUF[2] = res;
+				CS += res;
+				RX_Size = res;						//���յ����ݳ���
+				if(RX_Size == 0x00){			//������ݳ���Ϊ0����ֱ��ת������У����
+					RX_State = 8;
+				}else{
+					RX_State = 7;						//ת����������
+				}
+				break;				
+			case 7:	  //����N���ֽ�����
+				if(Byte_Count < RX_Size-1){
+					RS485_RX_BUF[Byte_Count + 3] = res;
+					CS += res;
+					Byte_Count++;
+				}else{
+					RS485_RX_BUF[Byte_Count + 3] = res;
+					CS += res;
+					Byte_Count = 0;					//�����N���ֽڵ����ݽ��ռ�����0
+					RX_State = 8;						//ת�����պ�����
+				}
+				break;
+			case 8:	  //����У��
+				if(CS != res){
+					RX_State = 0;
+				}else{
+					RX_State = 9;						//ת������֡β��0x16
+				}
+				break;
+			case 9:	  //����֡β
+				if(res == 0x16){ 					//��֡β��
+					RS485_RX_STA = 0xfd; 		//һ֡���ճɹ������USART_RX_STA=0xfd֪ͨ���������ͨѶ����
+// 					printf("\r\n<--\r\n");
+				}
+				RX_State = 0;
+				break;
+			default:  //����
+				break;
+		}
+	}
+}
+
+/*
+***********************************************************************
+*	�� �� ��: Send_Data
+*	����˵��: ����һ���ֽ�����
+*	��    ��:	��������
+*	�� �� ֵ: ��
+***********************************************************************
+*/
+void Send_Data(uint8_t Serial_data)
+{
+// 	CTRL485 = 1;													//����Ϊ����ģʽ
+	USART_SendData(USART2, Serial_data);	//�򴮿ڷ�������
+	while(USART_GetFlagStatus(USART2, USART_FLAG_TC) != SET);//�ȴ����ͽ���
+// 	CTRL485 = 0;													//�ָ�Ϊ����ģʽ	
+}
+
+/*
+***********************************************************************
+*	�� �� ��: Send_One
+*	����˵��: ����һ֡����
+*	��    ��:	��������֡��ַָ��
+*	�� �� ֵ: ��
+***********************************************************************
+*/
+void Send_One(uint8_t *s)
+{
+	uint8_t i;
+	uint8_t CS = 0x68;					//���պ����
+	uint8_t TX_Size = 0;				//����ͨѶ���ݳ���
+	printf("\r\n----->RS485--> %x\r\n", *(s+1));
+	CTRL485 = 1;		 						//RS-485 ͨѶ���л�Ϊ����״̬
+	
+	delay_ms(1);
+	Send_Data(0xfe); 						//����2��ǰ���ֽ�
+	Send_Data(0xfe);
+	Send_Data(0xfe);
+	Send_Data(0x68); 						//����֡ͷ
+	Send_Data(*s); 							//���͵�ַ
+	CS += *s;
+	Send_Data(0x68); 						//����֡ͷ
+	CS += 0x68;
+	Send_Data(*(s+1)); 					//����֡����
+	CS += *(s+1);
+	TX_Size = *(s+2);						//ȡ��ͨѶ���ݳ���
+	Send_Data(TX_Size); 				//�������ݳ���
+	CS += *(s+2);
+	for(i=0; i<TX_Size; i++) 		//��������
+	{
+		Send_Data(*(s+i+3));
+		CS += (*(s+i+3));
+	}
+	Send_Data(CS); 							//����У���ֽ�
+	Send_Data(0x16); 						//����֡β
+
+	delay_ms(1);
+	CTRL485 = 0; 								//һ֡������ϣ��ָ��ŵ��л�����
+}
+
+/*
+***********************************************************************
+*	�� �� ��: Serial_Address
+*	����˵��: ͨѶ��ַ�ж�
+*	��    ��:	s ָ���ͨѶ��ַ
+*	�� �� ֵ: 0x00 ����0x01 ��ȷ��0x02 �㲥��ַ
+***********************************************************************
+*/
+static uint8_t Serial_Address(uint8_t *s)
+{
+	if(*s == 0x99)
+	{
+		return(0x02); 				//�ǹ㲥��ַ
+	}
+	if(*s == Address)
+	{
+		return(0x01); 				//��ַƥ����ȷ
+	}
+	return(0x00); 					//��ַƥ�䲻��ȷ
+}
+
+/*
+***********************************************************************
+*	�� �� ��: Serial_Command_Run
+*	����˵��: ִ��ͨѶ����
+*	��    ��:	s ��������֡��ַָ��
+*	�� �� ֵ: 0 ����1 ��ȷ
+***********************************************************************
+*/
+uint8_t Serial_Command_Run(uint8_t *s)
+{
+	uint8_t i;
+
+// 	printf("\r\n<-- %x\r\n", *(s+1));
+	rxCmd = *(s+1);
+	switch(Serial_Address(s)) 		//�жϵ�ַ�Ƿ���ȷ
+	{
+		case 0x02: 	//�㲥��ַ0x99
+	 		break;
+			
+		case 0x01: 	//������ַ
+			printf("\r\n<-- %x\r\n", *(s+1));
+			
+			switch(*(s+1))		//ͨѶ��������
+			{
+				case 0x00: 			//Ӧ������
+					break;
+					
+				case 0x01: 			//��ȡ����������ֵ
+					distance = *(s+3);
+					break;
+					
+				case 0x02: 			//��ȡ����ֵ
+
+					break;
+					
+				case 0x03: 			//��ȡ�¶�ֵ
+					temperature = *(s+3);		//ȡ���������
+					break;
+					
+				case 0x10:			//��ȡ�¶ȡ���ࡢˮλ��������������Ϣ�����		
+// 					temperature = *(s+3);									//ȡ���¶�����
+// 					distance = *(s+4);										//ȡ���������
+// 					water = *(s+5);												//ȡ��ˮλ����
+// 					weight = (uint16_t)(*(s+6)) << 8;			//ȡ��������8λ����
+// 					weight |= *(s+7);											//ȡ��������8λ����
+// 					
+// 					receivePutInType = *(s+8);						//ȡ��������������
+// 					receiveDataLength = *(s+9);						//ȡ������������Ϣ�����ݳ���
+// 					
+// 					memcpy(receiveDataBuf, (s+10), 33);		//ȡ������������Ϣ����
+					break;
+					
+				case 0x21:			//���������ȡ�û�����
+// 					temperature = *(s+3);									//ȡ���¶�����
+// 					getUserInfoMark = *(s+4);							//��ȡ�ӻ����̴�����״̬���жϴӻ��Ƿ��Ѿ���ȡ���û�Ͷ��������Ϣ��
+// 					if(getUserInfoMark)										//ȡ���û������Ϣ
+// 					{
+// 						receivePutInType = *(s+5);					//ȡ�������������ͣ�0x00->�ޣ�0x01->IC����0x02->��ά�룩
+// 						receiveDataLength = *(s+6);					//ȡ������������Ϣ�����ݳ���
+// 						memcpy(receiveDataBuf, (s+7), 33);	//ȡ������������Ϣ����
+// 					}
+					break;
+					
+				case 0x22:			//����Ҫ��ӻ�����ϴε��û�����״̬��Ϣ
+// 					if(*(s+3))
+// 					{
+// 						clearPutInInfoMark = 1;
+// 					}
+					break;
+					
+				case 0x23:			//��ȡ��ࡢ���������
+// 					getPutInInfoMark = *(s+3);											//��ȡ�ӻ����̴�����״̬
+// 					if(getPutInInfoMark)														//�ӻ��Ѿ���ɹ��̴���
+// 					{
+// 						receiveDistance_a = *(s+4);										//ȡ���������
+// 						receiveDistance_b = *(s+5);										//ȡ���������
+
+// 						receiveWeight_a = (uint16_t)(*(s+6)) << 8;		//ȡ��������8λ����
+// 						receiveWeight_a |= *(s+7);										//ȡ��������8λ����
+// 						
+// 						receiveWeight_b = (uint16_t)(*(s+8)) << 8;		//ȡ��������8λ����
+// 						receiveWeight_b |= *(s+9);										//ȡ��������8λ����
+// 						
+// 						printf("\r\n<- ���� = %2.2f Kg; %2.2f Kg\r\n", (float)receiveWeight_a/100, (float)receiveWeight_b/100);
+// 						printf("\r\n<- ���1 = %3.1f cm\r\n", (float)receiveDistance_a);
+// 						printf("\r\n<- ���2 = %3.1f cm\r\n", (float)receiveDistance_b);
+// 						
+// 					}
+					break;
+					
+				case 0x24:			//�յ�MCU2�����������ϴ�����̨�����ݣ��û�Ͷ����Ϣ��
+					memset(receiveDataBuf, 0x00, 33);							//��������ǰ�Ȱ�֮ǰ�Ļ����������
+					
+					//ȡ���û�������Ϣ
+					receivePutInType = *(s+3);										//ȡ�������������ͣ�0x00->�ޣ�0x01->IC����0x02->��ά�룩
+					receiveDataLength = *(s+4);										//ȡ������������Ϣ�����ݳ���
+					memcpy(receiveDataBuf, (s+5), 33);						//ȡ������������Ϣ����
+					
+					//ȡ����һ����غͲ������
+					weight_paper = (uint16_t)(*(s+38)) << 8;			//ȡ��������8λ����
+					weight_paper |= *(s+39);											//ȡ��������8λ����
+					distance_paper = *(s+40);											//ȡ���������
+					
+					//ȡ���ڶ�����غͲ������
+					weight_plastic = (uint16_t)(*(s+41)) << 8;		//ȡ��������8λ����
+					weight_plastic |= *(s+42);										//ȡ��������8λ����
+					distance_plastic = *(s+43);										//ȡ���������
+					
+					//ȡ����������غͲ������
+					weight_metal = (uint16_t)(*(s+44)) << 8;			//ȡ��������8λ����
+					weight_metal |= *(s+45);											//ȡ��������8λ����
+					distance_metal = *(s+46);											//ȡ���������
+					
+					//ȡ����������غͲ������
+					weight_glass = (uint16_t)(*(s+47)) << 8;			//ȡ��������8λ����
+					weight_glass |= *(s+48);											//ȡ��������8λ����
+					distance_glass = *(s+49);											//ȡ���������
+					
+					receiveDataStatus = 1;													//�յ�MCU2���͵�Ͷ����Ϣ�����ñ�־λ��1�����ⲿ��ȡ�����
+
+					break;
+					
+				case 0x25:			//���յ�MCU2���͹������豸������Ϣ��������ࡢ�¶ȣ�
+					temperature = *(s+3);													//ȡ���¶�����
+							
+					distance_paper = *(s+4);											//ȡ��ֽ��Ͱ�������
+					distance_plastic = *(s+5);										//ȡ������Ͱ�������
+					distance_metal = *(s+6);											//ȡ������Ͱ�������
+					distance_glass = *(s+7);											//ȡ������Ͱ�������
+					
+					recDeviceStatus = 1;													//�յ�MCU2���͵��豸������Ϣ�����ñ�־λ��1�����ⲿ��ȡ�����
+
+					break;
+					
+				default: 				//��������
+					break;
+			}
+			
+			break;
+
+		case 0x00: //��ַ����
+			return 0;
+			break;	
+	}
+	return 1; //ִ֡����ȷ������
+}
+
+
+/*
+***********************************************************************
+*	�� �� ��: RS485_Task
+*	����˵��: RS485ͨѶ����
+*	��    ��:	��
+*	�� �� ֵ: ��
+***********************************************************************
+*/
+void RS485_Task(void)
+{
+}
+
+/*
+***********************************************************************
+*	�� �� ��: Receive_One
+*	����˵��: RS485����һ��ͨѶ����
+*	��    ��:	��
+*	�� �� ֵ: ��
+***********************************************************************
+*/
+void RS485_ReceiveTask(void)
+{
+	if(RS485_RX_STA == 0xfd)											//�н��յ��ӻ����ص����ݣ���Ҫ����������֤			
+	{
+		Serial_Command_Run(RS485_RX_BUF); 					//���ͷ��ص�����
+		RS485_RX_STA = 0;
+	}
+}
+
+/******************** (C) COPYRIGHT 2017 CXHY *****END OF FILE*******************/
diff --git a/STM32_4路称重_Git提交精简工程/src/HARDWARE/USART/UsarInterface.c b/STM32_4路称重_Git提交精简工程/src/HARDWARE/USART/UsarInterface.c
new file mode 100755
index 0000000..49bf36a
--- /dev/null
+++ b/STM32_4路称重_Git提交精简工程/src/HARDWARE/USART/UsarInterface.c
@@ -0,0 +1,17 @@
+/*************************** (C) COPYRIGHT 2014 GLHF ****************************
+ * �ļ���  ��USART5.c
+ * ��  ��  ������5��������(���ش�����2����)      
+ * ��  ��  ��V1.0
+ * ��  ��  ��XuZhongPing
+ * ��  ��  ��2017/03/15 
+*********************************************************************************/
+#include "usart.h"
+#include "UsarInterface.h"
+#include "rs485.h"
+
+
+void USART5_ReceiveDataHandler(uint8_t res)
+{
+}
+ 
+/******************** (C) COPYRIGHT 2017 CXHY *****END OF FILE*******************/
diff --git a/STM32_4路称重_Git提交精简工程/src/HARDWARE/USART/UsarInterface.h b/STM32_4路称重_Git提交精简工程/src/HARDWARE/USART/UsarInterface.h
new file mode 100755
index 0000000..739a6e2
--- /dev/null
+++ b/STM32_4路称重_Git提交精简工程/src/HARDWARE/USART/UsarInterface.h
@@ -0,0 +1,19 @@
+/*************************** (C) COPYRIGHT 2017 CXHY ****************************
+ * �ļ���  ��usart5.h
+ * ��  ��  ������5����ͷ�ļ�����     
+ * ��  ��  ��V1.0
+ * ��  ��  ��XuZhongPing
+ * ��  ��  ��2017/03/15 
+*********************************************************************************/
+#ifndef __USART_InterFace_H
+#define __USART_InterFace_H	
+
+#include "stm32f10x.h"
+#include "stdio.h" 
+
+void USART5_ReceiveDataHandler(uint8_t res);
+
+#endif
+
+
+/******************** (C) COPYRIGHT 2017 CXHY *****END OF FILE*******************/ 
diff --git a/STM32_4路称重_Git提交精简工程/src/HARDWARE/USART/crc16.c b/STM32_4路称重_Git提交精简工程/src/HARDWARE/USART/crc16.c
new file mode 100755
index 0000000..4f1952c
--- /dev/null
+++ b/STM32_4路称重_Git提交精简工程/src/HARDWARE/USART/crc16.c
@@ -0,0 +1,77 @@
+#include <string.h>
+#include <stdlib.h>
+#include "stdio.h"
+#include "crc16.h"
+
+const unsigned char auchCRCLo[]={ 
+0x00, 0xC0, 0xC1, 0x01, 0xC3, 0x03, 0x02, 0xC2, 0xC6, 0x06, 0x07, 0xC7, 0x05, 0xC5, 0xC4, 
+0x04, 0xCC, 0x0C, 0x0D, 0xCD, 0x0F, 0xCF, 0xCE, 0x0E, 0x0A, 0xCA, 0xCB, 0x0B, 0xC9, 0x09, 
+0x08, 0xC8, 0xD8, 0x18, 0x19, 0xD9, 0x1B, 0xDB, 0xDA, 0x1A, 0x1E, 0xDE, 0xDF, 0x1F, 0xDD, 
+0x1D, 0x1C, 0xDC, 0x14, 0xD4, 0xD5, 0x15, 0xD7, 0x17, 0x16, 0xD6, 0xD2, 0x12, 0x13, 0xD3, 
+0x11, 0xD1, 0xD0, 0x10, 0xF0, 0x30, 0x31, 0xF1, 0x33, 0xF3, 0xF2, 0x32, 0x36, 0xF6, 0xF7, 
+0x37, 0xF5, 0x35, 0x34, 0xF4, 0x3C, 0xFC, 0xFD, 0x3D, 0xFF, 0x3F, 0x3E, 0xFE, 0xFA, 0x3A, 
+0x3B, 0xFB, 0x39, 0xF9, 0xF8, 0x38, 0x28, 0xE8, 0xE9, 0x29, 0xEB, 0x2B, 0x2A, 0xEA, 0xEE, 
+0x2E, 0x2F, 0xEF, 0x2D, 0xED, 0xEC, 0x2C, 0xE4, 0x24, 0x25, 0xE5, 0x27, 0xE7, 0xE6, 0x26, 
+0x22, 0xE2, 0xE3, 0x23, 0xE1, 0x21, 0x20, 0xE0, 0xA0, 0x60, 0x61, 0xA1, 0x63, 0xA3, 0xA2, 
+0x62, 0x66, 0xA6, 0xA7, 0x67, 0xA5, 0x65, 0x64, 0xA4, 0x6C, 0xAC, 0xAD, 0x6D, 0xAF, 0x6F, 
+0x6E, 0xAE, 0xAA, 0x6A, 0x6B, 0xAB, 0x69, 0xA9, 0xA8, 0x68, 0x78, 0xB8, 0xB9, 0x79, 0xBB, 
+0x7B, 0x7A, 0xBA, 0xBE, 0x7E, 0x7F, 0xBF, 0x7D, 0xBD, 0xBC, 0x7C, 0xB4, 0x74, 0x75, 0xB5, 
+0x77, 0xB7, 0xB6, 0x76, 0x72, 0xB2, 0xB3, 0x73, 0xB1, 0x71, 0x70, 0xB0, 0x50, 0x90, 0x91, 
+0x51, 0x93, 0x53, 0x52, 0x92, 0x96, 0x56, 0x57, 0x97, 0x55, 0x95, 0x94, 0x54, 0x9C, 0x5C, 
+0x5D, 0x9D, 0x5F, 0x9F, 0x9E, 0x5E, 0x5A, 0x9A, 0x9B, 0x5B, 0x99, 0x59, 0x58, 0x98, 0x88, 
+0x48, 0x49, 0x89, 0x4B, 0x8B, 0x8A, 0x4A, 0x4E, 0x8E, 0x8F, 0x4F, 0x8D, 0x4D, 0x4C, 0x8C, 
+0x44, 0x84, 0x85, 0x45, 0x87, 0x47, 0x46, 0x86, 0x82, 0x42, 0x43, 0x83, 0x41, 0x81, 0x80, 
+0x40 
+};
+
+/* Table of CRC values for high�Corder byte */  
+const unsigned char auchCRCHi[]={
+0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, 0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 
+0x40, 0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40, 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 
+0x80, 0x41, 0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40, 0x00, 0xC1, 0x81, 0x40, 0x01, 
+0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, 0x01, 0xC0, 0x80, 0x41, 
+0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40, 0x00, 0xC1, 0x81, 
+0x40, 0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, 0x01, 0xC0, 
+0x80, 0x41, 0x00, 0xC1, 0x81, 0x40, 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, 0x01, 
+0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40, 
+0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, 0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 
+0x40, 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 
+0x80, 0x41, 0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40, 0x00, 0xC1, 0x81, 0x40, 0x01, 
+0xC0, 0x80, 0x41, 0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, 
+0x00, 0xC1, 0x81, 0x40, 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 
+0x40, 0x01, 0xC0, 0x80, 0x41, 0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 
+0x80, 0x41, 0x00, 0xC1, 0x81, 0x40, 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, 0x01, 
+0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40, 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, 
+0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, 0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 
+0x40 
+};
+
+/*---------------------------------------------------------
+ *�������ƣ�unsigned int getCRC16(unsigned char array[],unsigned int length)
+ *�������ܣ�CRC16У��
+ *���������У������ݡ�У�鳤��
+ *�����������
+ *���ز���������У��ֵ
+ *-------------------------------------------------------*/
+unsigned int GetCRC16(unsigned char *array,unsigned int length)
+{
+    unsigned char uchCRCHi = 0xFF ; /* ��ʼ�����ֽ�*/ 
+    unsigned char uchCRCLo = 0xFF ; /* ��ʼ�����ֽ�*/ 
+    unsigned char uIndex ; /*CRC������*/
+	unsigned char *p = array;
+    while(length--)
+    {
+        uIndex = uchCRCHi^*(p++);
+        uchCRCHi = uchCRCLo^auchCRCHi[uIndex];
+        uchCRCLo = auchCRCLo[uIndex];
+    }
+	return ((uchCRCHi<<8)|uchCRCLo); 
+	
+	//ĳЩ�����У��ֵ����ָ�8λ���8λΪ0x00�������
+	//�Ӷ����³���û����������ʱ����������������0x00�滻������һ����0x00��ֵ
+    //return ((((uchCRCHi<<8) == 0)?(0xAA<<8):(uchCRCHi<<8)) | ((uchCRCLo == 0)?0xAA:uchCRCLo));   
+}
+
+
+
+
diff --git a/STM32_4路称重_Git提交精简工程/src/HARDWARE/USART/crc16.h b/STM32_4路称重_Git提交精简工程/src/HARDWARE/USART/crc16.h
new file mode 100755
index 0000000..b24e28f
--- /dev/null
+++ b/STM32_4路称重_Git提交精简工程/src/HARDWARE/USART/crc16.h
@@ -0,0 +1,9 @@
+#ifndef __CRC16_H
+#define __CRC16_H
+
+unsigned int GetCRC16(unsigned char *array,unsigned int length);
+	
+#endif
+
+
+
diff --git a/STM32_4路称重_Git提交精简工程/src/HARDWARE/USART/printf.c b/STM32_4路称重_Git提交精简工程/src/HARDWARE/USART/printf.c
new file mode 100755
index 0000000..20cac30
--- /dev/null
+++ b/STM32_4路称重_Git提交精简工程/src/HARDWARE/USART/printf.c
@@ -0,0 +1,65 @@
+/*
+*******************************************************************************
+*	                                  
+*	ģ������ : printfģ��    
+*	�ļ����� : printf.c
+*	˵    �� : ʵ��printf��scanf�����ض��򵽴���1����֧��printf��Ϣ��USART1
+*				ʵ���ض���ֻ��Ҫ����2������:
+*				int fputc(int ch, FILE *f);
+*				int fgetc(FILE *f);
+*				����KEIL MDK������������ѡ������Ҫ��MicorLibǰ��򹳣����򲻻������ݴ�ӡ��USART1��
+*				
+*				���cģ���޶�Ӧ��h�ļ���
+*
+*******************************************************************************
+*/
+
+/* Includes ------------------------------------------------------------------*/
+#include <stdio.h>			
+#include "sys.h"
+
+#if 1
+
+struct __FILE 
+{ 
+	int handle; 
+}; 
+
+FILE __stdout;       
+//����_sys_exit()�Ա���ʹ�ð�����ģʽ    
+_sys_exit(int x) 
+{ 
+	x = x; 
+} 
+
+/*********************************************************
+  * @function  fputc
+  * @role      �ض���putc��������������ʹ��printf�����Ӵ���1��ӡ���
+  * @input     None
+  * @output    None
+  * @return    None
+  ********************************************************/
+int fputc(int ch, FILE *f)
+{
+	while((USART1->SR&0X40)==0);//ѭ������,ֱ���������   
+	USART1->DR = (u8) ch;      
+	return ch;
+}
+
+///*********************************************************
+//  * @function  fgetc
+//  * @role      �ض���getc��������������ʹ��scanff�����Ӵ���1��������
+//  * @input     None
+//  * @output    None
+//  * @return    None
+//  ********************************************************/
+//int fgetc(FILE *f)
+//{
+//	/* �ȴ�����1�������� */
+//	while (USART_GetFlagStatus(USART1, USART_FLAG_RXNE) == RESET);
+//	return (int)USART_ReceiveData(USART1);
+//}
+
+
+#endif
+
diff --git a/STM32_4路称重_Git提交精简工程/src/HARDWARE/USART/rs485.h b/STM32_4路称重_Git提交精简工程/src/HARDWARE/USART/rs485.h
new file mode 100755
index 0000000..81a340b
--- /dev/null
+++ b/STM32_4路称重_Git提交精简工程/src/HARDWARE/USART/rs485.h
@@ -0,0 +1,37 @@
+/*************************** (C) COPYRIGHT 2017 CXHY ****************************
+ * �ļ���  ��RS485.h
+ * ��  ��  ��RS485ͨ�Ŵ���ͷ�ļ�  
+ * ��  ��  ��V1.0
+ * ��  ��  ��XuZhongPing
+ * ��  ��  ��2017/02/10
+*********************************************************************************/
+#ifndef __RS485_H
+#define __RS485_H
+#include "stdio.h"
+#include "stdint.h"
+
+#define CTRL485	PAout(0)											//485ģʽ��������
+extern uint8_t Address;
+	  	
+extern uint8_t RS485_RX_BUF[128];     				//���ջ���
+extern uint8_t RS485_TX_BUF[64];     					//���ͻ���
+
+extern uint8_t RS485_RX_STA; 									//RS485����״̬���
+extern uint8_t RS485_communicationStatus;			//RS485ͨѶ�ɹ�����־
+extern uint16_t RS485_serialNumber;						//RS485ͨ����ˮ��
+extern uint16_t RS485_RX_serialNumber;				//RS485ͨ����ˮ��
+extern uint8_t rxCmd;													//�ӻ����ص�ָ����
+
+void RS485_Init(void);
+uint8_t Receive_One(uint8_t *s);
+void Send_Data(uint8_t Serial_data);
+void Send_One(uint8_t *s);
+uint8_t Serial_Command_Run(uint8_t *s);
+void Serial_Command(void);
+void RS485_Task(void);
+void RS485_ReceiveTask(void);
+
+#endif
+
+
+/******************** (C) COPYRIGHT 2017 CXHY *****END OF FILE*******************/
diff --git a/STM32_4路称重_Git提交精简工程/src/HARDWARE/USART/usart1.c b/STM32_4路称重_Git提交精简工程/src/HARDWARE/USART/usart1.c
new file mode 100755
index 0000000..0fe6b13
--- /dev/null
+++ b/STM32_4路称重_Git提交精简工程/src/HARDWARE/USART/usart1.c
@@ -0,0 +1,125 @@
+/*************************** (C) COPYRIGHT 2017 CXHY ****************************
+ * �ļ���  ��usart.c
+ * ��  ��  ������1��������    
+ * ��  ��  ��V1.0
+ * ��  ��  ��XuZhongPing
+ * ��  ��  ��2017/03/06 
+*********************************************************************************/
+#include "usart1.h"	  
+
+uint8_t USART1_RX_BUF[USART1_RECV_LEN];     	//���ջ���,���USART_REC_LEN���ֽ�.
+uint16_t USART1_RX_STA = 0;       					//����״̬���	
+
+/*
+***********************************************************************
+*	�� �� ��: USART1_Init
+*	����˵��: ����1��ʼ��
+*	��    �Σ���
+*	�� �� ֵ: ��
+***********************************************************************
+*/
+void USART1_Init(uint32_t bound)
+{
+	//GPIO�˿�����
+	GPIO_InitTypeDef GPIO_InitStructure;
+	USART_InitTypeDef USART_InitStructure;
+	NVIC_InitTypeDef NVIC_InitStructure;
+	 
+	RCC_APB2PeriphClockCmd(RCC_APB2Periph_USART1 | RCC_APB2Periph_GPIOA, ENABLE);	//ʹ��USART1��GPIOAʱ��
+ 	USART_DeInit(USART1);  //��λ����1
+	
+	//USART1_TX   PA.9
+	GPIO_InitStructure.GPIO_Pin = GPIO_Pin_9; 				
+	GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
+	GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;			//�����������
+	GPIO_Init(GPIOA, &GPIO_InitStructure); 							
+   
+	//USART1_RX	  PA.10
+	GPIO_InitStructure.GPIO_Pin = GPIO_Pin_10;
+	GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;		//��������
+	GPIO_Init(GPIOA, &GPIO_InitStructure); 
+
+  //USART ��ʼ������
+	USART_InitStructure.USART_BaudRate = bound;												//���ò�����
+	USART_InitStructure.USART_WordLength = USART_WordLength_8b;				//�ֳ�Ϊ8λ���ݸ�ʽ
+	USART_InitStructure.USART_StopBits = USART_StopBits_1;						//һ��ֹͣλ
+	USART_InitStructure.USART_Parity = USART_Parity_No;								//����żУ��λ
+	USART_InitStructure.USART_HardwareFlowControl = USART_HardwareFlowControl_None;//��Ӳ������������
+	USART_InitStructure.USART_Mode = USART_Mode_Rx | USART_Mode_Tx;		//�շ�ģʽ
+	USART_Init(USART1, &USART_InitStructure); 												//��ʼ������
+
+	//Usart1 NVIC ����
+	NVIC_InitStructure.NVIC_IRQChannel = USART1_IRQn;
+	NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 1 ;		//��ռ���ȼ�
+	NVIC_InitStructure.NVIC_IRQChannelSubPriority = 2;						//�����ȼ�
+	NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;								//IRQͨ��ʹ��
+	NVIC_Init(&NVIC_InitStructure);		
+  
+	USART_ITConfig(USART1, USART_IT_RXNE, ENABLE);								//�����ж�
+	USART_Cmd(USART1, ENABLE);     
+	USART1_RX_STA = 0;	
+}
+
+/*
+***********************************************************************
+*	�� �� ��: USART1_IRQHandler
+*	����˵��: �����жϷ������
+*	��    �Σ���
+*	�� �� ֵ: ��
+***********************************************************************
+*/
+void USART1_IRQHandler(void)
+{
+	uint8_t res = 0;
+	
+	if(USART_GetITStatus(USART1, USART_IT_RXNE) != RESET)  	//�����ж�(���յ������ݱ�����0x0d 0x0a��β)
+	{
+		res = USART_ReceiveData(USART1);											//��ȡ���յ�������
+		if(USART1_RX_STA < USART1_RECV_LEN)										//�����Խ�������
+		{
+			TIM_SetCounter(TIM5, 0);         										//���������
+			if(USART1_RX_STA == 0)
+			{
+				TIM_Cmd(TIM5, ENABLE);   													//ʹ�ܶ�ʱ��5���ж�
+			}							
+			USART1_RX_BUF[USART1_RX_STA++] = res;									//��¼���յ���ֵ	 			
+		}else{
+			USART1_RX_STA |= 1<<15;															//ǿ�Ʊ�ǽ������
+		}
+	}	
+} 
+
+/*
+***********************************************************************
+*	�� �� ��: USART1_SendByteData
+*	����˵��: ����һ�ֽ�����
+*	��    ��: ��
+*	�� �� ֵ: ��
+***********************************************************************
+*/
+void USART1_SendByteData(uint8_t bData)
+{ 
+	USART_SendData(USART1, bData);
+	while(USART_GetFlagStatus(USART1, USART_FLAG_TC) != SET);		//�ȴ����ͽ���
+}	
+
+/*
+***********************************************************************
+*	�� �� ��: USART1_SendFrameData
+*	����˵��: ����һ֡����
+*	��    ��: pData -> ���ݵ��׵�ַ��len -> ���ݵĳ���
+*	�� �� ֵ: ��
+***********************************************************************
+*/
+void USART1_SendFrameData(uint8_t pDataBuf[], uint16_t len)
+{
+	uint16_t i = 0;
+	
+	USART_ClearFlag(USART1, USART_FLAG_TC);
+	for(i = 0; i < len; i++)
+	{
+		USART1_SendByteData(pDataBuf[i]);
+	}
+}
+
+/******************** (C) COPYRIGHT 2017 ping *****END OF FILE*******************/
diff --git a/STM32_4路称重_Git提交精简工程/src/HARDWARE/USART/usart1.h b/STM32_4路称重_Git提交精简工程/src/HARDWARE/USART/usart1.h
new file mode 100755
index 0000000..a37b15a
--- /dev/null
+++ b/STM32_4路称重_Git提交精简工程/src/HARDWARE/USART/usart1.h
@@ -0,0 +1,25 @@
+/*************************** (C) COPYRIGHT 2017 CXHY ****************************
+ * �ļ���  ��usart.h
+ * ��  ��  ������1��������    
+ * ��  ��  ��V1.0
+ * ��  ��  ��XuZhongPing
+ * ��  ��  ��2017/03/06 
+*********************************************************************************/
+#ifndef __USART_H
+#define __USART_H
+#include "stm32f10x.h"
+
+#define USART1_RECV_LEN		128										//�����ջ����ֽ���
+#define USART1_SEND_LEN		128										//����ͻ����ֽ���
+	  	
+extern uint8_t USART1_RX_BUF[USART1_RECV_LEN]; 	//���ջ���,���USART_REC_LEN���ֽ�
+extern uint16_t USART1_RX_STA;         					//����״̬���	
+
+void USART1_Init(uint32_t bound);
+void USART1_SendByteData(uint8_t bData);
+void USART1_SendFrameData(uint8_t pDataBuf[], uint16_t len);
+
+#endif
+
+/******************** (C) COPYRIGHT 2017 YNHB *****END OF FILE*******************/
+
diff --git a/STM32_4路称重_Git提交精简工程/src/HARDWARE/USART/usart2.c b/STM32_4路称重_Git提交精简工程/src/HARDWARE/USART/usart2.c
new file mode 100755
index 0000000..a96ba42
--- /dev/null
+++ b/STM32_4路称重_Git提交精简工程/src/HARDWARE/USART/usart2.c
@@ -0,0 +1,220 @@
+/*************************** (C) COPYRIGHT 2017 Ping ****************************
+ * �ļ���  ��usart2.c
+ * ��  ��  ������2��������
+ * ��  ��  ��V1.0
+ * ��  ��  ��XuZhongPing
+ * ��  ��  ��2017/09/04
+*********************************************************************************/
+#include "usart2.h"
+
+uint8_t USART2_RX_BUF[USART2_RECV_LEN];			//�����ջ���
+uint8_t USART2_TX_BUF[USART2_SEND_LEN];			//����ջ���
+uint8_t USART2_RX_STA = 0;       						//����״̬���
+
+void USART2_ReceiveHandler(uint8_t res);
+
+/*
+***********************************************************************
+*	�� �� ��: USART2_Init
+*	����˵��: ����2��ʼ��
+*	��    �Σ���
+*	�� �� ֵ: ��
+***********************************************************************
+*/
+void USART2_Init(uint32_t bound)
+{
+	//GPIO�˿�����
+	GPIO_InitTypeDef GPIO_InitStructure;
+	USART_InitTypeDef USART_InitStructure;
+	NVIC_InitTypeDef NVIC_InitStructure;
+	 
+	RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOA, ENABLE);		//ʹ��GPIOAʱ��
+	RCC_APB1PeriphClockCmd(RCC_APB1Periph_USART2, ENABLE);	//ʹ��USART2ʱ��
+	
+	//USART2_TX   PA.2
+	GPIO_InitStructure.GPIO_Pin = GPIO_Pin_2; 							//PA.2
+	GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
+	GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;					//�����������
+	GPIO_Init(GPIOA, &GPIO_InitStructure); 									//��ʼ��PA2
+ 
+	//USART2_RX	  PA.3
+	GPIO_InitStructure.GPIO_Pin = GPIO_Pin_3;
+	GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;		//��������
+	GPIO_Init(GPIOA, &GPIO_InitStructure);  								//��ʼ��PA3
+
+	//USART ��ʼ������
+	USART_InitStructure.USART_BaudRate = bound;												//һ������Ϊ9600;
+	USART_InitStructure.USART_WordLength = USART_WordLength_8b;				//�ֳ�Ϊ8λ���ݸ�ʽ
+	USART_InitStructure.USART_StopBits = USART_StopBits_1;						//һ��ֹͣλ
+	USART_InitStructure.USART_Parity = USART_Parity_No;								//����żУ��λ
+	USART_InitStructure.USART_HardwareFlowControl = USART_HardwareFlowControl_None;	//��Ӳ������������
+	USART_InitStructure.USART_Mode = USART_Mode_Rx | USART_Mode_Tx;		//�շ�ģʽ
+	USART_Init(USART2, &USART_InitStructure); 												//��ʼ������
+	
+	//Usart1 NVIC ����
+	NVIC_InitStructure.NVIC_IRQChannel = USART2_IRQn;
+	NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0 ;				//��ռ���ȼ�0
+	NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0;								//�����ȼ�0
+	NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;										//IRQͨ��ʹ��
+	NVIC_Init(&NVIC_InitStructure);																		//����ָ���Ĳ�����ʼ��VIC�Ĵ���
+   
+	USART_ITConfig(USART2, USART_IT_RXNE, ENABLE);										//�����ж�
+	USART_Cmd(USART2, ENABLE);                    										//ʹ�ܴ��� 
+}
+
+/*
+***********************************************************************
+*	�� �� ��: USART2_IRQHandler
+*	����˵��: ����2�жϷ������
+*	��    �Σ���
+*	�� �� ֵ: ��
+***********************************************************************
+*/
+void USART2_IRQHandler(void)
+{
+	uint8_t res = 0;	
+	
+	if(USART_GetITStatus(USART2, USART_IT_RXNE) != RESET)		//���յ�����
+	{	 
+		res = USART_ReceiveData(USART2);											//��ȡ���յ�������
+		USART2_ReceiveHandler(res);
+	}
+}
+
+/*
+***********************************************************************
+*	�� �� ��: USART2_SendByteData
+*	����˵��: ����һ�ֽ�����
+*	��    ��: ��
+*	�� �� ֵ: ��
+***********************************************************************
+*/
+void USART2_SendByteData(uint8_t bData)
+{ 
+	USART_SendData(USART2, bData);
+	while(USART_GetFlagStatus(USART2, USART_FLAG_TC) != SET);		//�ȴ����ͽ���
+}
+
+/*
+***********************************************************************
+*	�� �� ��: USART2_SendFrameData
+*	����˵��: ����һ֡����
+*	��    ��: pData -> ���ݵ��׵�ַ��len -> ���ݵĳ���
+*	�� �� ֵ: ��
+***********************************************************************
+*/
+void USART2_SendFrameData(uint8_t pDataBuf[], uint16_t len)
+{
+	uint16_t i = 0;
+	
+	USART_ClearFlag(USART2, USART_FLAG_TC);
+	for(i = 0; i < len; i++)
+	{
+		USART2_SendByteData(pDataBuf[i]);
+	}
+}
+
+/*
+***********************************************************************
+*	�� �� ��: USART2_ReceiveHandler
+*	����˵��: �������ݽ��մ�������
+*	��    ��: ���봮�ڽ��յ�������
+*	�� �� ֵ: �ޣ�Ӱ�촮�ڽ���״̬USART2_RX_STA��
+***********************************************************************
+*/
+void USART2_ReceiveHandler(uint8_t res)
+{
+	static uint8_t RX_Status = 0;						//����״̬
+	static uint8_t CS = 0;		  						//���պ����
+	static uint8_t RX_Size = 0;							//����ͨѶ���ݳ���
+	static uint8_t RX_ByteCount = 0;	  		//���������ֽڼ���
+	
+// 	printf("U2 = %02X\r\n", res);
+	
+	switch(RX_Status)
+	{
+		case 0:	  //��һǰ���ֽ�
+			if(res == 0xfe){
+				RX_Status = 1;
+			}else{
+				RX_Status = 0;
+			}
+			break;
+			
+		case 1:	  //�ڶ�ǰ���ֽ�
+			if(res == 0xfe){
+				RX_Status = 1;						//����ǰ���ֽ�
+			}else if(res == 0x68){
+				RX_Status = 3;						//ת�������豸ͨѶ��ַ
+				CS = 0x68;
+			}else{
+				RX_Status = 0;
+			}
+			break;
+
+		case 3:		//�����豸ͨѶ��ַ
+			USART2_RX_BUF[0] = res;
+			CS += res;
+			RX_Status = 4;
+			break;
+			
+		case 4:	  //����֡ͷ
+			if(res == 0x68){
+				RX_Status = 5;						//ת������ͨѶ����
+				CS += 0x68;
+			}else{
+				RX_Status = 0;
+			}
+			break;
+		case 5:		//����ͨѶ����
+			USART2_RX_BUF[1] = res;
+			CS += res;
+			RX_Status = 6;							//ת���������ݳ���
+			break;
+			
+		case 6:		//����ͨѶ���ݳ���
+			USART2_RX_BUF[2] = res;
+			CS += res;
+			RX_Size = res;						//���յ����ݳ���
+			if(RX_Size == 0x00){			//������ݳ���Ϊ0����ֱ��ת������У����
+				RX_Status = 8;
+			}else{
+				RX_Status = 7;						//ת����������
+			}
+			break;	
+			
+		case 7:	  //����N���ֽ�����
+			if(RX_ByteCount < RX_Size-1){
+				USART2_RX_BUF[RX_ByteCount + 3] = res;
+				CS += res;
+				RX_ByteCount++;
+			}else{
+				USART2_RX_BUF[RX_ByteCount + 3] = res;
+				CS += res;
+				RX_ByteCount = 0;					//�����N���ֽڵ����ݽ��ռ�����0
+				RX_Status = 8;						//ת�����պ�����
+			}
+			break;
+			
+		case 8:	  //����У��
+			if(CS != res){
+				RX_Status = 0;
+			}else{
+				RX_Status = 9;						//ת������֡β��0x16
+			}
+			break;
+			
+		case 9:	  //����֡β
+			if(res == 0x16){ 						//��֡β��
+				USART2_RX_STA = 0xfd; 		//һ֡���ճɹ�����ǽ��յ�һ֡����֪ͨ���������ͨѶ����
+			}
+			RX_Status = 0;
+			break;
+			
+		default:  //����
+			RX_Status = 0;
+			break;
+	}
+}
+
+/******************** (C) COPYRIGHT 2017 Ping *****END OF FILE*******************/ 
diff --git a/STM32_4路称重_Git提交精简工程/src/HARDWARE/USART/usart2.h b/STM32_4路称重_Git提交精简工程/src/HARDWARE/USART/usart2.h
new file mode 100755
index 0000000..8123468
--- /dev/null
+++ b/STM32_4路称重_Git提交精简工程/src/HARDWARE/USART/usart2.h
@@ -0,0 +1,26 @@
+/*************************** (C) COPYRIGHT 2017 Ping ****************************
+ * �ļ���  ��usart2.h
+ * ��  ��  ������2����ͷ�ļ�     
+ * ��  ��  ��V1.0
+ * ��  ��  ��XuZhongPing
+ * ��  ��  ��2017/09/04 
+*********************************************************************************/
+#ifndef __USART2_H
+#define __USART2_H
+#include "stm32f10x.h"
+#include "stdio.h"
+
+#define USART2_RECV_LEN		128										//�����ջ����ֽ���
+#define USART2_SEND_LEN		128										//����ͻ����ֽ���
+	  	
+extern uint8_t USART2_RX_BUF[USART2_RECV_LEN];
+extern uint8_t USART2_TX_BUF[USART2_SEND_LEN]; 
+extern uint8_t USART2_RX_STA;
+
+void USART2_Init(uint32_t bound);
+void USART2_SendByteData(uint8_t bData);
+void USART2_SendFrameData(uint8_t pDataBuf[], uint16_t len);
+
+#endif
+
+/******************** (C) COPYRIGHT 2017 Ping *****END OF FILE*******************/
diff --git a/STM32_4路称重_Git提交精简工程/src/HARDWARE/USART/usart3.c b/STM32_4路称重_Git提交精简工程/src/HARDWARE/USART/usart3.c
new file mode 100755
index 0000000..1aac56d
--- /dev/null
+++ b/STM32_4路称重_Git提交精简工程/src/HARDWARE/USART/usart3.c
@@ -0,0 +1,156 @@
+/*************************** (C) COPYRIGHT 2014 GLHF ****************************
+ * �ļ���  ��usart3.c
+ * ��  ��  ������3��������(GPRS����)    
+ * ��  ��  ��V1.0
+ * ��  ��  ��XuZhongPing
+ * ��  ��  ��2013/11/21 
+*********************************************************************************/
+#include "stm32f10x.h"
+#include "delay.h"
+#include "usart3.h"
+#include "stdarg.h"	 	 
+#include "stdio.h"	 	 
+#include "string.h"		   
+#include "gsm_uart.h"
+#include "gsm_uart_conf.h"   
+
+static void UART3_DMA_Config(void);
+
+/*
+***********************************************************************
+*	�� �� ��: USART3_Init
+*	����˵��: ����3��ʼ��
+*	��    ��: ��
+*	�� �� ֵ: ��
+***********************************************************************
+*/
+void USART3_Init(u32 bound)
+{
+	//GPIO�˿�����
+	GPIO_InitTypeDef GPIO_InitStructure;
+	USART_InitTypeDef USART_InitStructure;
+	NVIC_InitTypeDef NVIC_InitStructure;
+
+	//������ʹ�õ�ʱ��
+	RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOB, ENABLE);		//ʹ��GPIOBʱ��
+ 	RCC_APB1PeriphClockCmd(RCC_APB1Periph_USART3, ENABLE);		//ʹ��USART3ʱ��
+	
+	USART_DeInit(USART3);  																	//��λ����3
+	
+	//USART3_TX   PB.10
+	GPIO_InitStructure.GPIO_Pin = GPIO_Pin_10; 							
+	GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
+	GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;					//�����������
+	GPIO_Init(GPIOB, &GPIO_InitStructure); 									//��ʼ��PB10
+   
+	//USART3_RX	  PB.11
+	GPIO_InitStructure.GPIO_Pin = GPIO_Pin_11;
+	GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;		//��������
+	GPIO_Init(GPIOB, &GPIO_InitStructure);  								//��ʼ��PB11
+
+
+	//USART ��ʼ������
+	USART_InitStructure.USART_BaudRate = bound;												//���ò�����;
+	USART_InitStructure.USART_WordLength = USART_WordLength_8b;				//�ֳ�Ϊ8λ���ݸ�ʽ
+	USART_InitStructure.USART_StopBits = USART_StopBits_1;						//һ��ֹͣλ
+	USART_InitStructure.USART_Parity = USART_Parity_No;								//����żУ��λ
+	USART_InitStructure.USART_HardwareFlowControl = USART_HardwareFlowControl_None;	//��Ӳ������������
+	USART_InitStructure.USART_Mode = USART_Mode_Rx | USART_Mode_Tx;		//�շ�ģʽ
+
+	USART_Init(USART3, &USART_InitStructure); 								//��ʼ������
+	
+	UART3_DMA_Config();																				//DMA1ͨ��2,����Ϊ����3,�洢��ΪUSART3_TX_BUF 
+
+	//Usart3 NVIC ����
+	NVIC_InitStructure.NVIC_IRQChannel = USART3_IRQn;
+	NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority=0 ;	//��ռ���ȼ�0
+	NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0;				//�����ȼ�1
+	NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;						//IRQͨ��ʹ��
+	NVIC_Init(&NVIC_InitStructure);														//����ָ���Ĳ�����ʼ��VIC�Ĵ���
+   
+	USART_ITConfig(USART3, USART_IT_RXNE, ENABLE);						//�����ж�
+
+	USART_Cmd(USART3, ENABLE);                    						//ʹ�ܴ��� 
+	GPRS_RX_STA = 0;																					//����״̬����
+	TIM_Cmd(TIM4, DISABLE);  	 																//�ر�TIMx
+}
+
+/*
+***********************************************************************
+*	�� �� ��: USART3_IRQHandler
+*	����˵��: ����3�жϣ����ڽ���GSM_GPRS���ݣ�
+*						ͨ���жϽ�������2���ַ�֮���ʱ������10ms�������ǲ���һ������������.
+*						���2���ַ����ռ������10ms,����Ϊ����1����������.Ҳ���ǳ���10msû�н��յ�
+*						�κ�����,���ʾ�˴ν������.
+*	��    ��: ��
+*	�� �� ֵ: Ӱ��ȫ�ֱ���GPRS_RX_STA���������:
+*						[15]:0,û�н��յ�����;1,���յ���һ������.
+*						[14:0]:���յ������ݳ���
+***********************************************************************
+*/
+void USART3_IRQHandler(void)
+{
+	uint8_t res;	    
+	if(USART_GetITStatus(USART3, USART_IT_RXNE) != RESET)		//���յ�����
+	{	 
+		res = USART_ReceiveData(USART3);											//��ȡ���յ�������
+		GSM_GPRS_ReceiveData(res);
+	}  											 
+} 
+		 
+///////////////////////////////////////USART3 DMA�������ò���//////////////////////////////////	   		    
+//DMA1�ĸ�ͨ������
+//����Ĵ�����ʽ�ǹ̶���,���Ҫ���ݲ�ͬ��������޸�
+//�Ӵ洢��->����ģʽ/8λ���ݿ���/�洢������ģʽ
+//DMA_CHx:DMAͨ��CHx
+//cpar:�����ַ
+//cmar:�洢����ַ   
+
+/*
+***********************************************************************
+*	�� �� ��: UART3_DMA_Config
+*	����˵��: GSM�����������
+*	��    ��: ��
+*	�� �� ֵ: ��
+***********************************************************************
+*/
+static void UART3_DMA_Config(void)
+{
+ 	DMA_InitTypeDef DMA_InitStructure;
+	RCC_AHBPeriphClockCmd(RCC_AHBPeriph_DMA1, ENABLE);	//ʹ��DMA����
+	
+	delay_us(5);
+	DMA_DeInit(DMA1_Channel2);   //��DMA��ͨ��2�Ĵ�������Ϊȱʡֵ
+//	DMA1_MEM_LEN=cndtr;
+	DMA_InitStructure.DMA_PeripheralBaseAddr = (uint32_t)&USART3->DR;  				//DMA����ADC����ַ
+	DMA_InitStructure.DMA_MemoryBaseAddr = (uint32_t)GPRS_TX_BUF;  						//DMA�ڴ����ַ
+	DMA_InitStructure.DMA_DIR = DMA_DIR_PeripheralDST;  											//���ݴ��䷽�򣬴��ڴ��ȡ���͵�����
+//	DMA_InitStructure.DMA_BufferSize = cndtr;  															//DMAͨ����DMA����Ĵ�С
+	DMA_InitStructure.DMA_PeripheralInc = DMA_PeripheralInc_Disable;  				//�����ַ�Ĵ�������
+	DMA_InitStructure.DMA_MemoryInc = DMA_MemoryInc_Enable;  									//�ڴ��ַ�Ĵ�������
+	DMA_InitStructure.DMA_PeripheralDataSize = DMA_PeripheralDataSize_Byte;		//���ݿ���Ϊ8λ
+	DMA_InitStructure.DMA_MemoryDataSize = DMA_MemoryDataSize_Byte; 					//���ݿ���Ϊ8λ
+	DMA_InitStructure.DMA_Mode = DMA_Mode_Normal;  														//��������������ģʽ
+	DMA_InitStructure.DMA_Priority = DMA_Priority_Medium; 										//DMAͨ�� xӵ�������ȼ� 
+	DMA_InitStructure.DMA_M2M = DMA_M2M_Disable;  														//DMAͨ��xû������Ϊ�ڴ浽�ڴ洫��
+	DMA_Init(DMA1_Channel2, &DMA_InitStructure);  														//����DMA_InitStruct��ָ���Ĳ�����ʼ��DMA��ͨ��USART1_Tx_DMA_Channel����ʶ�ļĴ���		  	
+
+	USART_DMACmd(USART3, USART_DMAReq_Tx, ENABLE); 														//ʹ�ܴ���3��DMA����
+}    
+
+/*
+***********************************************************************
+*	�� �� ��: UART3_Send_One
+*	����˵��: ͨ��DMA�򴮿�3����һ������
+*	��    ��: ��
+*	�� �� ֵ: ��
+***********************************************************************
+*/
+void UART3_Send_One(uint16_t len)
+{ 
+	DMA_Cmd(DMA1_Channel2, DISABLE);  						//�ر�USART3 TX DMA1 ��ָʾ��ͨ��      
+ 	DMA_SetCurrDataCounter(DMA1_Channel2, len);		//DMAͨ����DMA����Ĵ�С
+ 	DMA_Cmd(DMA1_Channel2, ENABLE);  							//ʹ��USART3 TX DMA1 ��ָʾ��ͨ�� 
+}	
+
+/******************** (C) COPYRIGHT 2017 CXHY *****END OF FILE*******************/
diff --git a/STM32_4路称重_Git提交精简工程/src/HARDWARE/USART/usart3.h b/STM32_4路称重_Git提交精简工程/src/HARDWARE/USART/usart3.h
new file mode 100755
index 0000000..94e84f4
--- /dev/null
+++ b/STM32_4路称重_Git提交精简工程/src/HARDWARE/USART/usart3.h
@@ -0,0 +1,19 @@
+/*************************** (C) COPYRIGHT 2014 GLHF ****************************
+ * �ļ���  ��usart3.h
+ * ��  ��  ������3����ͷ�ļ�     
+ * ��  ��  ��V1.0
+ * ��  ��  ��XuZhongPing
+ * ��  ��  ��2013/11/21 
+*********************************************************************************/
+#ifndef __USART3_H
+#define __USART3_H	 
+
+#include "stm32f10x.h"
+
+void USART3_Init(u32 bound);							//����3��ʼ�� 
+void UART3_Send_One(u16 len);
+#endif
+
+/******************** (C) COPYRIGHT 2014 GLHF *****END OF FILE*******************/
+
+
diff --git a/STM32_4路称重_Git提交精简工程/src/HARDWARE/USART/usart4.c b/STM32_4路称重_Git提交精简工程/src/HARDWARE/USART/usart4.c
new file mode 100755
index 0000000..6c760fe
--- /dev/null
+++ b/STM32_4路称重_Git提交精简工程/src/HARDWARE/USART/usart4.c
@@ -0,0 +1,227 @@
+/*************************** (C) COPYRIGHT 2014 GLHF ****************************
+ * �ļ���  ��USART4.c
+ * ��  ��  ������4��������   
+ * ��  ��  ��V1.0
+ * ��  ��  ��XuZhongPing
+ * ��  ��  ��2017/09/03 
+*********************************************************************************/
+#include "usart4.h"
+
+uint8_t USART4_RX_BUF[USART4_RECV_LEN];			//�����ջ���
+uint8_t USART4_TX_BUF[USART4_SEND_LEN];			//����ջ���
+uint8_t USART4_RX_STA = 0;       						//����״̬���
+
+void USART4_ReceiveHandler(uint8_t rxBuf[], uint8_t bData);
+/*
+***********************************************************************
+*	�� �� ��: USART4_Init
+*	����˵��: ��ʼ��IO ����4
+*	��    �Σ�bound:������	 
+*	�� �� ֵ: ��
+***********************************************************************
+*/
+void USART4_Init(u32 bound)
+{  	
+	//GPIO�˿�����
+	GPIO_InitTypeDef GPIO_InitStructure;
+	USART_InitTypeDef USART_InitStructure;
+	NVIC_InitTypeDef NVIC_InitStructure;
+	 
+	RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOC, ENABLE);		//ʹ��GPIOAʱ��
+ 	RCC_APB1PeriphClockCmd(RCC_APB1Periph_UART4, ENABLE);		//ʹ��USART4ʱ��
+
+	//USART4_TX   PC.10
+	GPIO_InitStructure.GPIO_Pin = GPIO_Pin_10; 							//PC.10
+	GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
+	GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;					//�����������
+	GPIO_Init(GPIOC, &GPIO_InitStructure); 									//��ʼ��PC.10
+   
+	//USART4_RX	  PC.11
+	GPIO_InitStructure.GPIO_Pin = GPIO_Pin_11;
+	GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;		//��������
+	GPIO_Init(GPIOC, &GPIO_InitStructure);  								//��ʼ��PC.11
+
+	//USART ��ʼ������
+	USART_InitStructure.USART_BaudRate = bound;																			//���ò�����;
+	USART_InitStructure.USART_WordLength = USART_WordLength_8b;											//�ֳ�Ϊ8λ���ݸ�ʽ
+	USART_InitStructure.USART_StopBits = USART_StopBits_1;													//һ��ֹͣλ
+	USART_InitStructure.USART_Parity = USART_Parity_No;															//����żУ��λ
+	USART_InitStructure.USART_HardwareFlowControl = USART_HardwareFlowControl_None;	//��Ӳ������������
+	USART_InitStructure.USART_Mode = USART_Mode_Rx | USART_Mode_Tx;									//�շ�ģʽ
+	USART_Init(UART4, &USART_InitStructure); 																				//��ʼ������
+	
+	//Usart4 NVIC ����
+	NVIC_InitStructure.NVIC_IRQChannel = UART4_IRQn;
+	NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 1 ;		//��ռ���ȼ�0
+	NVIC_InitStructure.NVIC_IRQChannelSubPriority = 1;					//�����ȼ�1
+	NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;							//IRQͨ��ʹ��
+	NVIC_Init(&NVIC_InitStructure);															//����ָ���Ĳ�����ʼ��VIC�Ĵ���
+  
+	USART_ITConfig(UART4, USART_IT_RXNE, ENABLE);			//�����ж�
+	USART_Cmd(UART4, ENABLE);													//ʹ�ܴ��� 									  	
+}
+
+/*
+***********************************************************************
+*	�� �� ��: USART4_IRQHandler
+*	����˵��: ����4�жϷ������
+*	��    �Σ���
+*	�� �� ֵ: ��
+***********************************************************************
+*/
+void UART4_IRQHandler(void)
+{
+	uint8_t res = 0;
+	
+	if(USART_GetITStatus(UART4, USART_IT_RXNE) != RESET)
+	{
+		res = USART_ReceiveData(UART4);			//��ȡ���յ�������
+		USART4_ReceiveHandler(USART4_RX_BUF, res);
+	}	
+}
+
+/*
+***********************************************************************
+*	�� �� ��: USART4_SendByteData
+*	����˵��: ����һ�ֽ�����
+*	��    ��: ��
+*	�� �� ֵ: ��
+***********************************************************************
+*/
+void USART4_SendByteData(uint8_t bData)
+{ 
+	USART_SendData(UART4, bData);
+	while(USART_GetFlagStatus(UART4, USART_FLAG_TC) != SET);		//�ȴ����ͽ���
+}	
+
+/*
+***********************************************************************
+*	�� �� ��: USART4_SendFrameData
+*	����˵��: ����һ֡����
+*	��    ��: pData -> ���ݵ��׵�ַ��len -> ���ݵĳ���
+*	�� �� ֵ: ��
+***********************************************************************
+*/
+void USART4_SendFrameData(uint8_t pDataBuf[], uint16_t len)
+{
+	uint16_t i = 0;
+	
+	USART_ClearFlag(UART4, USART_FLAG_TC);
+	for(i = 0; i < len; i++)
+	{
+		USART4_SendByteData(pDataBuf[i]);
+	}
+}	
+
+/*
+***********************************************************************
+*	�� �� ��: USART4_ReceiveHandler
+*	����˵��: �������ݽ��մ�������
+*	��    ��: ���봮�ڽ��յ�������
+*	�� �� ֵ: �ޣ�Ӱ�촮�ڽ���״̬USART4_RX_STA��
+***********************************************************************
+*/
+void USART4_ReceiveHandler(uint8_t rxBuf[], uint8_t bData)
+{
+	static uint8_t RX_Status = 0;						//����״̬
+	static uint8_t CS = 0;		  						//���պ����
+	static uint16_t RX_Size = 0;						//����ͨѶ���ݳ���
+	static uint16_t RX_ByteCount = 0;	  		//���������ֽڼ���
+	
+// 	printf("U3 = %02X\r\n", bData);
+	
+	switch(RX_Status)
+	{
+		case 0:	  //��һǰ���ֽ�
+			if(bData == 0xfe){
+				RX_Status = 1;
+			}else{
+				RX_Status = 0;
+			}
+			break;
+			
+		case 1:	  //�ڶ�ǰ���ֽ�
+			if(bData == 0xfe){
+				RX_Status = 1;						//����ǰ���ֽ�
+			}else if(bData == 0x68){
+				RX_Status = 3;						//ת�������豸ͨѶ��ַ
+				CS = 0x68;
+			}else{
+				RX_Status = 0;
+			}
+			break;
+
+		case 3:		//�����豸ͨѶ��ַ
+			rxBuf[0] = bData;
+			CS += bData;
+			RX_Status = 4;
+			break;
+			
+		case 4:	  //����֡ͷ
+			if(bData == 0x68){
+				RX_Status = 5;						//ת������ͨѶ����
+				CS += 0x68;
+			}else{
+				RX_Status = 0;
+			}
+			break;
+		case 5:		//����ͨѶ����
+			rxBuf[1] = bData;
+			CS += bData;
+			RX_Status = 6;							//ת���������ݳ���
+			break;
+			
+		case 6:		//����ͨѶ���ݳ��ȣ���8λ��
+			rxBuf[2] = bData;
+			CS += bData;
+			RX_Status = 62;							//ת����������
+			break;
+			
+		case 62:		//����ͨѶ���ݳ��ȣ���8λ��
+			rxBuf[3] = bData;
+			CS += bData;
+			RX_Size = (rxBuf[2] << 8) | rxBuf[3];				//���յ����ݳ���
+			if(RX_Size == 0x00){			//������ݳ���Ϊ0����ֱ��ת������У����
+				RX_Status = 8;
+			}else{
+				RX_ByteCount = 0;
+				RX_Status = 7;						//ת����������
+			}
+			break;	
+			
+		case 7:	  //����N���ֽ�����
+			if(RX_ByteCount < RX_Size-1){
+				rxBuf[RX_ByteCount + 4] = bData;
+				CS += bData;
+				RX_ByteCount++;
+			}else{
+				rxBuf[RX_ByteCount + 4] = bData;
+				CS += bData;
+				RX_ByteCount = 0;					//�����N���ֽڵ����ݽ��ռ�����0
+				RX_Status = 8;						//ת�����պ�����
+			}
+			break;
+			
+		case 8:	  //����У��
+			if(CS != bData){
+				RX_Status = 0;
+			}else{
+				RX_Status = 9;						//ת������֡β��0x16
+			}
+			break;
+			
+		case 9:	  //����֡β
+			if(bData == 0x16) 					//��֡β��
+			{
+				USART4_RX_STA = 0xfd; 	//һ֡���ճɹ�����ǽ��յ�һ֡����֪ͨ���������ͨѶ����
+			}
+			RX_Status = 0;
+			break;
+			
+		default:  //����
+			RX_Status = 0;
+			break;
+	}
+}
+
+/******************** (C) COPYRIGHT 2017 YNHB *****END OF FILE*******************/
diff --git a/STM32_4路称重_Git提交精简工程/src/HARDWARE/USART/usart4.h b/STM32_4路称重_Git提交精简工程/src/HARDWARE/USART/usart4.h
new file mode 100755
index 0000000..f59a46f
--- /dev/null
+++ b/STM32_4路称重_Git提交精简工程/src/HARDWARE/USART/usart4.h
@@ -0,0 +1,26 @@
+/*************************** (C) COPYRIGHT 2017 YNHB ****************************
+ * �ļ���  ��usart4.h
+ * ��  ��  ������4����ͷ�ļ�����     
+ * ��  ��  ��V1.0
+ * ��  ��  ��XuZhongPing
+ * ��  ��  ��2017/02/05 
+*********************************************************************************/
+#ifndef __USART4_H
+#define __USART4_H	
+#include "stm32f10x.h"
+#include "stdio.h" 
+     
+#define USART4_RECV_LEN		256										//�����ջ����ֽ���
+#define USART4_SEND_LEN		256										//����ͻ����ֽ���
+	  	
+extern uint8_t USART4_RX_BUF[USART4_RECV_LEN]; 
+extern uint8_t USART4_TX_BUF[USART4_SEND_LEN]; 
+extern uint8_t USART4_RX_STA; 
+
+void USART4_Init(uint32_t bound);	
+void USART4_SendByteData(uint8_t bData);
+void USART4_SendFrameData(uint8_t pDataBuf[], uint16_t len);
+
+#endif
+
+/******************** (C) COPYRIGHT 2017 YNHB *****END OF FILE*******************/ 
diff --git a/STM32_4路称重_Git提交精简工程/src/HARDWARE/USART/usart5.c b/STM32_4路称重_Git提交精简工程/src/HARDWARE/USART/usart5.c
new file mode 100755
index 0000000..a8daf62
--- /dev/null
+++ b/STM32_4路称重_Git提交精简工程/src/HARDWARE/USART/usart5.c
@@ -0,0 +1,141 @@
+/*************************** (C) COPYRIGHT 2014 GLHF ****************************
+ * �ļ���  ��USART5.c
+ * ��  ��  ������5��������   
+ * ��  ��  ��V1.0
+ * ��  ��  ��XuZhongPing
+ * ��  ��  ��2017/09/03 
+*********************************************************************************/
+#include "usart5.h"
+
+uint8_t USART5_RX_BUF[USART5_RECV_LEN];			//�����ջ���
+uint8_t USART5_TX_BUF[USART5_SEND_LEN];			//����ջ���
+uint8_t USART5_RX_STA = 0;       						//����״̬���
+
+void USART5_ReceiveHandler(uint8_t res);
+
+/*
+***********************************************************************
+*	�� �� ��: USART5_Init
+*	����˵��: ��ʼ��IO ����5
+*	��    �Σ�bound:������	 
+*	�� �� ֵ: ��
+***********************************************************************
+*/
+void USART5_Init(uint32_t bound)
+{  	
+	//GPIO�˿�����
+	GPIO_InitTypeDef GPIO_InitStructure;
+	USART_InitTypeDef USART_InitStructure;
+	NVIC_InitTypeDef NVIC_InitStructure;
+	 
+	RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOC | RCC_APB2Periph_GPIOD, ENABLE);
+ 	RCC_APB1PeriphClockCmd(RCC_APB1Periph_UART5, ENABLE);
+
+	//USART5_TX   PC.12
+	GPIO_InitStructure.GPIO_Pin = GPIO_Pin_12;
+	GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
+	GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
+	GPIO_Init(GPIOC, &GPIO_InitStructure);
+   
+	//USART5_RX	  PD.2
+	GPIO_InitStructure.GPIO_Pin = GPIO_Pin_2;
+	GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;		//��������
+	GPIO_Init(GPIOD, &GPIO_InitStructure);  								//��ʼ��PD.2
+
+	//USART ��ʼ������
+	USART_InitStructure.USART_BaudRate = bound;																			//���ò�����;
+	USART_InitStructure.USART_WordLength = USART_WordLength_8b;											//�ֳ�Ϊ8λ���ݸ�ʽ
+	USART_InitStructure.USART_StopBits = USART_StopBits_1;													//һ��ֹͣλ
+	USART_InitStructure.USART_Parity = USART_Parity_No;															//����żУ��λ
+	USART_InitStructure.USART_HardwareFlowControl = USART_HardwareFlowControl_None;	//��Ӳ������������
+	USART_InitStructure.USART_Mode = USART_Mode_Rx | USART_Mode_Tx;									//�շ�ģʽ
+	USART_Init(UART5, &USART_InitStructure); 																				//��ʼ������
+	
+	//Usart5 NVIC ����
+	NVIC_InitStructure.NVIC_IRQChannel = UART5_IRQn;
+	NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority=2 ;		//��ռ���ȼ�0
+	NVIC_InitStructure.NVIC_IRQChannelSubPriority = 1;					//�����ȼ�1
+	NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;							//IRQͨ��ʹ��
+	NVIC_Init(&NVIC_InitStructure);															//����ָ���Ĳ�����ʼ��VIC�Ĵ���
+  
+	USART_ITConfig(UART5, USART_IT_RXNE, ENABLE);			//�����ж�
+	USART_Cmd(UART5, ENABLE);													//ʹ�ܴ���
+}
+
+/*
+***********************************************************************
+*	�� �� ��: UART5_IRQHandler
+*	����˵��: ����5�жϷ������ӳ���
+*	��    �Σ���
+*	�� �� ֵ: ��
+***********************************************************************
+*/ 	 
+void UART5_IRQHandler(void)
+{
+	uint8_t res = 0;
+	
+	if(USART_GetITStatus(UART5, USART_IT_RXNE) != RESET)  //�����ж�(���յ������ݱ�����0x0d 0x0a��β)
+	{
+		res = USART_ReceiveData(UART5);
+		USART5_ReceiveHandler(res);
+	}									 
+}   
+
+/*
+***********************************************************************
+*	�� �� ��: UART5_Send_Data
+*	����˵��: ����һ���ֽ�����
+*	��    ��:	��������
+*	�� �� ֵ: ��
+***********************************************************************
+*/
+void USART5_SendByteData(uint8_t Serial_data)
+{
+	USART_SendData(UART5, Serial_data);												//�򴮿ڷ�������
+	while(USART_GetFlagStatus(UART5, USART_FLAG_TC) != SET);	//�ȴ����ͽ���
+}
+
+/*
+***********************************************************************
+*	�� �� ��: USART5_SendFrameData
+*	����˵��: ����һ֡����
+*	��    ��: pData -> ���ݵ��׵�ַ��len -> ���ݵĳ���
+*	�� �� ֵ: ��
+***********************************************************************
+*/
+void USART5_SendFrameData(uint8_t pDataBuf[], uint16_t len)
+{
+	uint16_t i = 0;
+	
+	USART_ClearFlag(UART5, USART_FLAG_TC);
+	for(i = 0; i < len; i++)
+	{
+		USART5_SendByteData(pDataBuf[i]);
+	}
+}
+
+/*
+***********************************************************************
+*	�� �� ��: USART5_ReceiveHandler
+*	����˵��: �������ݽ��մ�������
+*	��    ��: ���봮�ڽ��յ�������
+*	�� �� ֵ: �ޣ�Ӱ�촮�ڽ���״̬USART5_RX_STA��
+***********************************************************************
+*/
+void USART5_ReceiveHandler(uint8_t res)
+{	
+	static uint8_t Byte_count = 0;	  			//���������ֽڼ���
+	static uint8_t receiveState = 0;				//����״̬
+		
+	switch(receiveState)
+	{
+		case 0:	  //��һ��ʼ��
+			
+			break;
+
+		default:  //����
+			break;
+	}							 
+}
+ 
+/******************** (C) COPYRIGHT 2017 CXHY *****END OF FILE*******************/
diff --git a/STM32_4路称重_Git提交精简工程/src/HARDWARE/USART/usart5.h b/STM32_4路称重_Git提交精简工程/src/HARDWARE/USART/usart5.h
new file mode 100755
index 0000000..b261659
--- /dev/null
+++ b/STM32_4路称重_Git提交精简工程/src/HARDWARE/USART/usart5.h
@@ -0,0 +1,27 @@
+/*************************** (C) COPYRIGHT 2017 CXHY ****************************
+ * �ļ���  ��usart5.h
+ * ��  ��  ������5����ͷ�ļ�����     
+ * ��  ��  ��V1.0
+ * ��  ��  ��XuZhongPing
+ * ��  ��  ��2017/03/15 
+*********************************************************************************/
+#ifndef __USART5_H
+#define __USART5_H	
+#include "stm32f10x.h"
+#include "stdio.h" 
+
+#define USART5_RECV_LEN		128										//�����ջ����ֽ���
+#define USART5_SEND_LEN		128										//����ͻ����ֽ���
+	  	
+extern uint8_t USART5_RX_BUF[USART5_RECV_LEN]; 
+extern uint8_t USART5_TX_BUF[USART5_SEND_LEN]; 
+extern uint8_t USART5_RX_STA; 
+
+void USART5_Init(uint32_t bound);	
+void USART5_SendByteData(uint8_t bData);
+void USART5_SendFrameData(uint8_t pDataBuf[], uint16_t len);
+
+#endif
+
+
+/******************** (C) COPYRIGHT 2017 CXHY *****END OF FILE*******************/ 
diff --git a/STM32_4路称重_Git提交精简工程/src/HARDWARE/UltrasonicWave/UltrasonicWave.c b/STM32_4路称重_Git提交精简工程/src/HARDWARE/UltrasonicWave/UltrasonicWave.c
new file mode 100755
index 0000000..fcfa744
--- /dev/null
+++ b/STM32_4路称重_Git提交精简工程/src/HARDWARE/UltrasonicWave/UltrasonicWave.c
@@ -0,0 +1,518 @@
+/*************************** (C) COPYRIGHT 2017 CXHY ****************************
+ * �ļ���  ��UltrasonicWave.c
+ * ��  ��  ��HC-SR04��������������     
+ * ��  ��  ��V1.0
+ * ��  ��  ��XuZhongPing
+ * ��  ��  ��2017/08/04 
+*********************************************************************************/
+#include "UltrasonicWave.h"
+#include "timer.h"
+#include "delay.h"
+#include "my_math.h"
+#include "data_typedef.h"
+
+
+#define	TRIG1_PORT      GPIOA										//TRIG���ڵ�IO��       
+#define	ECHO1_PORT      GPIOC										//ECHO���ڵ�IO��
+#define	TRIG1_PIN      	GPIO_Pin_11   					//TRIG����      
+#define	ECHO1_PIN       GPIO_Pin_1							//ECHO���� 
+#define ECHO1_PortSource	GPIO_PortSourceGPIOC	//�ж�Դ����IO��
+#define ECHO1_PinSource		GPIO_PinSource1				//�ж�����
+#define ECHO1_EXTI_Line		EXTI_Line1						//�ж���
+
+#define	TRIG2_PORT    	GPIOA										//TRIG���ڵ�IO��      
+#define	ECHO2_PORT    	GPIOC										//ECHO���ڵ�IO��
+#define	TRIG2_PIN     	GPIO_Pin_12   					//TRIG����       
+#define	ECHO2_PIN     	GPIO_Pin_0							//ECHO���� 
+#define ECHO2_PortSource	GPIO_PortSourceGPIOC	//�ж�Դ����IO��
+#define ECHO2_PinSource		GPIO_PinSource0				//�ж�����
+#define ECHO2_EXTI_Line		EXTI_Line0						//�ж���
+
+#define	TRIG3_PORT    	GPIOA										//TRIG���ڵ�IO��         
+#define	ECHO3_PORT    	GPIOD										//ECHO���ڵ�IO��   
+#define	TRIG3_PIN     	GPIO_Pin_15   						//TRIG����        
+#define	ECHO3_PIN     	GPIO_Pin_0							//ECHO���� 
+#define ECHO3_PortSource	GPIO_PortSourceGPIOD	//�ж�Դ����IO��
+#define ECHO3_PinSource		GPIO_PinSource0				//�ж�����
+#define ECHO3_EXTI_Line		EXTI_Line0						//�ж���
+
+#define	TRIG4_PORT    	GPIOD										//TRIG���ڵ�IO��       
+#define	ECHO4_PORT    	GPIOD										//ECHO���ڵ�IO�� 
+#define	TRIG4_PIN     	GPIO_Pin_1   						//TRIG����        
+#define	ECHO4_PIN     	GPIO_Pin_3							//ECHO���� 
+#define ECHO4_PortSource	GPIO_PortSourceGPIOD	//�ж�Դ����IO��
+#define ECHO4_PinSource		GPIO_PinSource3				//�ж�����
+#define ECHO4_EXTI_Line		EXTI_Line3						//�ж���   
+
+#define ULT_Data_Size		5
+
+uint8_t distance1 = 255;      								//���ó���������õľ��� 
+uint8_t distance2 = 255;      								//���ó���������õľ��� 
+uint8_t distance3 = 255;      								//���ó���������õľ��� 
+uint8_t distance4 = 255;      								//���ó���������õľ��� 
+
+uint8_t dataOutState = 0;											//�����Ƿ��Ѿ��������״̬��1���Ѵ�����ɿ������״̬��0����δ�������
+uint8_t dataOutState1 = 0;										
+uint8_t dataOutState2 = 0;
+
+uint8_t succeedFlag;											//���ճɹ���־
+uint16_t counterValue;										//�������ز�ʱ��
+// uint8_t ULT_Data[ULT_Data_Size];
+
+static void EXTI_Cmd(uint16_t EXTI_Line, uint8_t NewState);
+
+/*
+***********************************************************************
+*	�� �� ��: UltrasonicWave_Configuration
+*	����˵��: ������ģ��ĳ�ʼ��
+*	��    �Σ���
+*	�� �� ֵ: ��
+***********************************************************************
+*/
+void UltrasonicWaveInit(void)
+{
+  GPIO_InitTypeDef GPIO_InitStructure;	
+	EXTI_InitTypeDef EXTI_InitStructure;
+ 	NVIC_InitTypeDef NVIC_InitStructure;
+	
+  RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOA | RCC_APB2Periph_GPIOC | RCC_APB2Periph_GPIOD | RCC_APB2Periph_AFIO, ENABLE);
+	
+	GPIO_PinRemapConfig(GPIO_Remap_SWJ_JTAGDisable , ENABLE);	
+  
+	//NO.1������
+  GPIO_InitStructure.GPIO_Pin = TRIG1_PIN;					 					//TRIG����
+  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP;		     		//��Ϊ�������ģʽ
+  GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;	         
+  GPIO_Init(TRIG1_PORT, &GPIO_InitStructure);	              
+
+  GPIO_InitStructure.GPIO_Pin = ECHO1_PIN;				     				//ECHO����
+  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU;		 						//��Ϊ��������
+  GPIO_Init(ECHO1_PORT, &GPIO_InitStructure);						 			
+	
+	//NO.2������
+  GPIO_InitStructure.GPIO_Pin = TRIG2_PIN;					 					//TRIG����
+  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP;		     		//��Ϊ�������ģʽ
+  GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;	         
+  GPIO_Init(TRIG2_PORT, &GPIO_InitStructure);	              
+
+  GPIO_InitStructure.GPIO_Pin = ECHO2_PIN;				     				//ECHO����
+  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU;		 						//��Ϊ��������
+  GPIO_Init(ECHO2_PORT, &GPIO_InitStructure);							
+	
+	//NO.1�������ж��߳�ʼ������
+ 	GPIO_EXTILineConfig(ECHO1_PortSource, ECHO1_PinSource);
+	EXTI_InitStructure.EXTI_Line = ECHO1_EXTI_Line;
+	EXTI_InitStructure.EXTI_Mode = EXTI_Mode_Interrupt;	
+	EXTI_InitStructure.EXTI_Trigger = EXTI_Trigger_Falling;			//�½��ش���
+	EXTI_InitStructure.EXTI_LineCmd = ENABLE;
+	EXTI_Init(&EXTI_InitStructure);	
+	EXTI_Cmd(ECHO1_EXTI_Line, DISABLE);
+	
+	//NO.2�������ж��߳�ʼ������
+ 	GPIO_EXTILineConfig(ECHO2_PortSource, ECHO2_PinSource);
+	EXTI_InitStructure.EXTI_Line = ECHO2_EXTI_Line;
+	EXTI_InitStructure.EXTI_Mode = EXTI_Mode_Interrupt;	
+	EXTI_InitStructure.EXTI_Trigger = EXTI_Trigger_Falling;			//�½��ش���
+	EXTI_InitStructure.EXTI_LineCmd = ENABLE;
+	EXTI_Init(&EXTI_InitStructure);	
+	EXTI_Cmd(ECHO2_EXTI_Line, DISABLE);
+	
+	//�ж�����
+	NVIC_InitStructure.NVIC_IRQChannel = EXTI0_IRQn;						//ʹ�ܼ������ڵ��ⲿ�ж�ͨ��
+	NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 2;		//��ռ���ȼ�2 
+	NVIC_InitStructure.NVIC_IRQChannelSubPriority = 2;					//�����ȼ�2 
+	NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;							//ʹ���ⲿ�ж�ͨ��
+	NVIC_Init(&NVIC_InitStructure); 
+	
+	NVIC_InitStructure.NVIC_IRQChannel = EXTI1_IRQn;					//ʹ�ܼ������ڵ��ⲿ�ж�ͨ��
+	NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 2;		//��ռ���ȼ�2 
+	NVIC_InitStructure.NVIC_IRQChannelSubPriority = 2;					//�����ȼ�2 
+	NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;							//ʹ���ⲿ�ж�ͨ��
+	NVIC_Init(&NVIC_InitStructure); 
+}
+
+/*
+***********************************************************************
+*	�� �� ��: EXTI15_10_IRQHandler
+*	����˵��: �ⲿ�жϷ����ӳ���
+*	��    �Σ���
+*	�� �� ֵ: ��
+***********************************************************************
+*/
+void EXTI0_IRQHandler(void)
+{          
+	counterValue = TIM_GetCounter(TIM4);					//ȡ���ز��Ķ�ʱʱ��
+// 	printf("��ʱΪ:%d\r\n", counterValue);
+	succeedFlag = 1;															//�ý��ճɹ���־
+	EXTI_ClearITPendingBit(ECHO2_EXTI_Line);  		//���NO.1������EXTI��·����λ
+}
+
+/*
+***********************************************************************
+*	�� �� ��: EXTI9_5_IRQHandler
+*	����˵��: �ⲿ�жϷ����ӳ���
+*	��    �Σ���
+*	�� �� ֵ: ��
+***********************************************************************
+*/
+void EXTI1_IRQHandler(void)
+{          
+	counterValue = TIM_GetCounter(TIM4);					//ȡ���ز��Ķ�ʱʱ��
+// 	printf("��ʱΪ:%d\r\n", counterValue);
+	succeedFlag = 1;															//�ý��ճɹ���־
+	EXTI_ClearITPendingBit(ECHO1_EXTI_Line);  		//���NO.3������EXTI��·����λ
+}
+
+/*
+***********************************************************************
+*	�� �� ��: EXTI_Cmd
+*	����˵��: �ⲿ�ж�ʹ��/���ܲ���
+*	��    �Σ�
+*           EXTI_Line:�ⲿ�ж����ź�
+*	          NewState :ʹ��ENABLE������DISABLE
+*	�� �� ֵ: ��
+***********************************************************************
+*/
+static void EXTI_Cmd(uint16_t EXTI_Line, uint8_t NewState)
+{
+    EXTI->PR = EXTI_Line;  									//���EXTI_Line�ϵ��жϱ�־λ
+    if(NewState){
+			EXTI->IMR |= EXTI_Line;								//������EXTI_Line�ϵ��ж�
+		}else{
+			EXTI->IMR &= ~EXTI_Line;							//����EXTI_Line�ϵ��ж�
+		}
+}
+
+/*
+***********************************************************************
+*	�� �� ��: GetDistance
+*	����˵��: ��ȡһ�γ������������
+*	��    �Σ���
+*	�� �� ֵ: ����õ�����
+***********************************************************************
+*/
+uint8_t GetDistance(uint8_t whichOne)
+{
+	uint8_t value = 255;
+	uint16_t TIM_Count = 0;
+	
+	GPIO_TypeDef *TRIG_PORTx;
+	GPIO_TypeDef *ECHO_PORTx;	
+	uint16_t TRIG_PINx;
+	uint16_t ECHO_PINx;
+	uint16_t ECHO_EXTI_LineX;
+	
+	switch(whichOne)
+	{
+		case 1:
+			TRIG_PORTx = TRIG1_PORT;
+			ECHO_PORTx = ECHO1_PORT;
+			TRIG_PINx = TRIG1_PIN;
+			ECHO_PINx = ECHO1_PIN;
+			ECHO_EXTI_LineX = ECHO1_EXTI_Line;
+			break;
+			
+		case 2:
+			TRIG_PORTx = TRIG2_PORT;
+			ECHO_PORTx = ECHO2_PORT;
+			TRIG_PINx = TRIG2_PIN;
+			ECHO_PINx = ECHO2_PIN;
+			ECHO_EXTI_LineX = ECHO2_EXTI_Line;
+			break;
+			
+		case 3:
+			TRIG_PORTx = TRIG3_PORT;
+			ECHO_PORTx = ECHO3_PORT;
+			TRIG_PINx = TRIG3_PIN;
+			ECHO_PINx = ECHO3_PIN;
+			ECHO_EXTI_LineX = ECHO3_EXTI_Line;
+			break;
+			
+		case 4:
+			TRIG_PORTx = TRIG4_PORT;
+			ECHO_PORTx = ECHO4_PORT;
+			TRIG_PINx = TRIG4_PIN;
+			ECHO_PINx = ECHO4_PIN;
+			ECHO_EXTI_LineX = ECHO4_EXTI_Line;
+			break;
+		
+		default:
+			break;
+	}
+
+	//��TRIG���Ų���һ��10us���ϵĸߵ�ƽ���崥���ź�����������
+	GPIO_SetBits(TRIG_PORTx, TRIG_PINx); 		  	
+  delay_us(20);		                      			
+  GPIO_ResetBits(TRIG_PORTx, TRIG_PINx);
+	while((GPIO_ReadInputDataBit(ECHO_PORTx, ECHO_PINx) == 0) && (TIM_Count<4000))	//�ȴ�Echo�ز����ű�ɸߵ�ƽ
+	{
+		TIM_Count++;
+	}
+	if(TIM_Count >= 4000)
+	{
+		return 255;
+	}
+	TIM_Count = 0;
+	succeedFlag = 0;
+	EXTI_Cmd(ECHO_EXTI_LineX, ENABLE);				//��ECHO_EXTI_Line�����ⲿ�жϣ�������صĵ���
+	
+	TIM_SetCounter(TIM4, 0);									//��ʱ������ֵ��0
+	TIM_Cmd(TIM4, ENABLE);  									//�򿪶�ʱ����ʼ��ʱ
+	
+	while(TIM_Count < 120 && succeedFlag == 0)										//�޶��ȴ�ʱ�䣨��12ms���Ϊ2�׾��룩��������ʱ�仹û�д����ⲿ�ж���˵����Ч
+	{
+		TIM_Count = TIM_GetCounter(TIM4);
+	}
+	
+	TIM_Cmd(TIM4, DISABLE);										//�رն�ʱ
+	EXTI_Cmd(ECHO_EXTI_LineX, DISABLE);				//�ر�ECHO_EXTI_Line�����ⲿ�ж�
+
+// 	printf("TIM_count:%d\r\n", TIM_Count);
+	if(succeedFlag == 1)											//�жϲ���Ƿ�ɹ�
+	{
+// 		printf("\r\nsucceedFlag\r\n");
+		value = (float)(counterValue*100)/58;
+	}
+	counterValue = 0;
+	return value;
+}
+
+/*
+***********************************************************************
+*	�� �� ��: ULT_DataProcessing
+*	����˵��: �Բɼ�����������ݴ�������������������ƽ������
+*	��    �Σ�
+*       		*p: ��Ҫ����������ָ��
+*						n:  ����ĳ��� 
+*	�� �� ֵ: �������մ�������Ľ��
+***********************************************************************
+*/
+uint8_t ULT_DataProcessing(uint8_t *p, uint16_t n, uint8_t discardVal)
+{
+	uint8_t retData;
+	sort_8(p, n);           											//�Դ��ڻ����еĲɼ����ݽ�������
+	retData = average_8(p, n, discardVal);				//ȥ��ͷ��β����ƽ����
+// 	printf("\r\nValue = %d\r\n", retData);
+	return retData;
+}
+
+/*
+***********************************************************************
+*	�� �� ��: GetDistanceData
+*	����˵��: ��ȡ���������
+*	��    �Σ���
+*	�� �� ֵ: ���ز������
+***********************************************************************
+*/
+uint8_t GetDistanceData(uint8_t num)
+{
+	uint8_t retData = 0;
+	retData = GetDistance(num);
+	return retData;
+}
+
+/*
+***********************************************************************
+*	�� �� ��: GetDistanceTask
+*	����˵��: ��ȡ�������������
+*	��    �Σ���
+*	�� �� ֵ: ���ݴ���״̬  1���Ѵ�����ɿ��������0����δ�������
+***********************************************************************
+*/
+void GetDistanceTask_01(void)
+{
+	static uint8_t ULT_status = 0x00;
+	static uint8_t getDataCnt = 0x00;
+	
+	static uint8_t newValue = 0x00;
+	static uint8_t oleValue = 0x00;
+	static uint8_t ULT_Data[ULT_Data_Size];
+	
+	static timer waitingTimer;
+	static uint8_t timer_ok = 0;
+	
+	if(timer_ok == 0)
+	{
+		timer_ok = 1;
+		timer_set(&waitingTimer, 3);
+	}
+	
+	switch(ULT_status)
+	{
+		case 0x00:
+			if(timer_expired(&waitingTimer))
+			{
+				newValue = GetDistanceData(1);
+// 				printf("\r\nValue = %3.1f cm\r\n",(float)newValue);
+				ULT_status = 0x01;
+				timer_restart(&waitingTimer);
+			}
+			break;
+		case 0x01:
+			if(DifferenceCompare(newValue, oleValue, 5))		//�Ƚ��¾�ֵ�Ĳ�ֵ������ǰֵ - ֮ǰֵ��> �趨ֵʱ���²ɼ�����
+			{
+				getDataCnt = 0;
+			}
+// 			printf("\r\nCnt = %d, newValue = %d, oleValue = %d\r\n", getDataCnt, newValue, oleValue);
+			oleValue = newValue;
+			
+			ULT_Data[getDataCnt] = newValue;
+			getDataCnt++;
+			if(ULT_Data_Size == getDataCnt)							//10�����ݶ���������Ϊ�����Ѿ��ȶ��������
+			{
+				getDataCnt = 0;
+				ULT_status = 0x02;										//ת�����ݴ������
+			}else{
+				ULT_status = 0x00;	
+			}
+			break;
+			
+		case 0x02:
+			distance1 = ULT_DataProcessing(ULT_Data, ULT_Data_Size, 0);	
+// 			printf("\r\nNo1 ---> %3.1f cm\r\n",(float)distance_01);
+			dataOutState1 = 1;
+			ULT_status = 0x00;
+			break;
+			
+		default:
+			ULT_status = 0x00;
+			break;
+	}
+}
+
+/*
+***********************************************************************
+*	�� �� ��: GetDistanceTask_02
+*	����˵��: ��ȡ�������������
+*	��    �Σ���
+*	�� �� ֵ: ���ݴ���״̬  1���Ѵ�����ɿ��������0����δ�������
+***********************************************************************
+*/
+void GetDistanceTask_02(void)
+{
+	static uint8_t ULT_status = 0x00;
+	static uint8_t getDataCnt = 0x00;
+	
+	static uint8_t newValue = 0x00;
+	static uint8_t oleValue = 0x00;
+	static uint8_t ULT_Data[ULT_Data_Size];
+	
+	static timer waitingTimer;
+	static uint8_t timer_ok = 0;
+	
+	if(timer_ok == 0)
+	{
+		timer_ok = 1;
+		timer_set(&waitingTimer, 3);
+	}
+	
+	switch(ULT_status)
+	{
+		case 0x00:
+			if(timer_expired(&waitingTimer))
+			{
+				newValue = GetDistanceData(2);
+// 				printf("\r\nValue = %3.1f cm\r\n",(float)newValue);
+				ULT_status = 0x01;
+				timer_restart(&waitingTimer);
+			}
+			break;
+		case 0x01:
+			if(DifferenceCompare(newValue, oleValue, 5))		//�Ƚ��¾�ֵ�Ĳ�ֵ������ǰֵ - ֮ǰֵ��> �趨ֵʱ���²ɼ�����
+			{
+				getDataCnt = 0;
+			}
+// 			printf("\r\nCnt = %d, newValue = %d, oleValue = %d\r\n", getDataCnt, newValue, oleValue);
+			oleValue = newValue;
+			
+			ULT_Data[getDataCnt] = newValue;
+			getDataCnt++;
+			if(ULT_Data_Size == getDataCnt)							//10�����ݶ���������Ϊ�����Ѿ��ȶ��������
+			{
+				getDataCnt = 0;
+				ULT_status = 0x02;										//ת�����ݴ������
+			}else{
+				ULT_status = 0x00;	
+			}
+			break;
+			
+		case 0x02:
+			distance2 = ULT_DataProcessing(ULT_Data, ULT_Data_Size, 0);	
+// 			printf("\r\nNo2 ---> %3.1f cm\r\n",(float)distance_02);
+			dataOutState2 = 1;												//�Ѿ�׼�������ݣ���������ˣ��˱�־���ⲿ���
+			ULT_status = 0x00;
+			break;
+			
+		default:
+			ULT_status = 0x00;
+			break;
+	}
+}
+
+// /*
+// ***********************************************************************
+// *	�� �� ��: GetDistanceTask
+// *	����˵��: ��ȡ�������������
+// *	��    �Σ���
+// *	�� �� ֵ: ��
+// ***********************************************************************
+// */
+// void GetDistanceTask(void)
+// {
+// 	static uint8_t ULT_getDataStatus = 0x00;
+// 	
+// 	static timer waitingTimer;
+// 	static timer responsTimer;
+// 	static uint8_t timer_ok = 0;
+// 	
+// 	if(timer_ok == 0)
+// 	{
+// 		timer_ok = 1;
+// 		timer_set(&waitingTimer, CLOCK_SECOND*2);
+// 		timer_set(&responsTimer, 3);
+// 	}
+// 	
+// 	switch(ULT_getDataStatus)
+// 	{
+// 		case 0x00:
+// 			if(timer_expired(&waitingTimer))
+// 			{
+// 				ULT_getDataStatus = 0x01;
+// 			}
+// 			break;
+// 			
+// 		case 0x01:
+// 			GetDistanceTask_01();
+// 			if(dataOutState1 == 1)			//��һ·������ݲɼ��ɹ�
+// 			{
+// 				dataOutState1 = 0;
+// 				ULT_getDataStatus = 0x02;
+// // 				printf("\r\n��1·�ɼ�OK\r\n");
+// 			}
+// 			break;
+// 			
+// 		case 0x02:
+// 			GetDistanceTask_02();
+// 			if(dataOutState2 == 1)			//��һ·������ݲɼ��ɹ�
+// 			{
+// 				dataOutState2 = 0;
+// 				ULT_getDataStatus = 0x03;
+// // 				printf("\r\n��2·�ɼ�OK\r\n");
+// 			}
+// 			break;
+// 			
+// 		case 0x03:
+// 			getDistance1 = distance1;
+// 			getDistance2 = distance2;
+// 			printf("\r\n��ࣺNo1 = %3.1f cm, ", (float)distance1);
+// 			printf("No2 = %3.1f cm\r\n", (float)distance2);
+// // 			printf("No3 = %3.1f cm, ", (float)distance3);
+// // 			printf("No4 = %3.1f cm\r\n", (float)distance4);
+// 			ULT_getDataStatus = 0x00;
+// 			timer_restart(&waitingTimer);
+// 			break;
+// 	}
+// }
+
+
+/******************** (C) COPYRIGHT 2017 CXHY *****END OF FILE*******************/
diff --git a/STM32_4路称重_Git提交精简工程/src/HARDWARE/UltrasonicWave/UltrasonicWave.h b/STM32_4路称重_Git提交精简工程/src/HARDWARE/UltrasonicWave/UltrasonicWave.h
new file mode 100755
index 0000000..a9d083c
--- /dev/null
+++ b/STM32_4路称重_Git提交精简工程/src/HARDWARE/UltrasonicWave/UltrasonicWave.h
@@ -0,0 +1,28 @@
+/*************************** (C) COPYRIGHT 2017 CXHY ****************************
+ * �ļ���  ��UltrasonicWave.h
+ * ��  ��  ��HC-SR04��������������     
+ * ��  ��  ��V1.0
+ * ��  ��  ��XuZhongPing
+ * ��  ��  ��2017/08/04 
+*********************************************************************************/
+#ifndef __UltrasonicWave_H
+#define	__UltrasonicWave_H
+#include "stm32f10x.h"
+
+extern uint8_t distance1;      								//���ó���������õľ��� 
+extern uint8_t distance2;      								//���ó���������õľ��� 
+extern uint8_t distance3;      								//���ó���������õľ��� 
+extern uint8_t distance4;      								//���ó���������õľ��� 
+
+extern uint8_t dataOutState;										//�����������������״̬��־��Ϊ1�����������
+extern uint8_t dataOutState1;
+extern uint8_t dataOutState2;
+
+void UltrasonicWaveInit(void);            			//�Գ�����ģ���ʼ��
+void GetDistanceTask_01(void);
+void GetDistanceTask_02(void);
+// void GetDistanceTask(void);
+
+#endif
+
+/******************** (C) COPYRIGHT 2017 CXHY *****END OF FILE*******************/
diff --git a/STM32_4路称重_Git提交精简工程/src/HARDWARE/WDG/wdg.c b/STM32_4路称重_Git提交精简工程/src/HARDWARE/WDG/wdg.c
new file mode 100755
index 0000000..f4cf6d8
--- /dev/null
+++ b/STM32_4路称重_Git提交精简工程/src/HARDWARE/WDG/wdg.c
@@ -0,0 +1,75 @@
+/*************************** (C) COPYRIGHT 2017 CXHY ****************************
+ * �ļ���  ��2code.c
+ * ��  ��  ����ά�봦������    
+ * ��  ��  ��V1.0
+ * ��  ��  ��XuZhongPing
+ * ��  ��  ��2017/03/06 
+*********************************************************************************/
+#include "wdg.h"
+#include "timer.h"
+
+/*
+***********************************************************************
+*	�� �� ��: IWDG_Init
+*	����˵��: ��ʼ���������Ź�
+*	��    ��: prer -> ��Ƶ��:0~7(ֻ�е�3λ��Ч!)
+*										��Ƶ����=4*2^prer.�����ֵֻ����256!
+*						rlr -> ��װ�ؼĴ���ֵ:��11λ��Ч.
+*						ʱ�����(���):Tout=((4*2^prer)*rlr)/40 (ms).
+*	�� �� ֵ: ��
+***********************************************************************
+*/
+void IWDG_Init(uint8_t prer, uint16_t rlr) 
+{	
+ 	IWDG_WriteAccessCmd(IWDG_WriteAccess_Enable);  	//ʹ�ܶԼĴ���IWDG_PR��IWDG_RLR��д����
+	
+	IWDG_SetPrescaler(prer);  											//����IWDGԤ��Ƶֵ:����IWDGԤ��ƵֵΪ64
+	
+	IWDG_SetReload(rlr);  													//����IWDG��װ��ֵ
+	
+	IWDG_ReloadCounter();  													//����IWDG��װ�ؼĴ�����ֵ��װ��IWDG������
+	
+	IWDG_Enable();  																//ʹ��IWDG
+}
+
+/*
+***********************************************************************
+*	�� �� ��: IWDG_Feed
+*	����˵��: ι�������Ź�
+*	��    ��: ��
+*	�� �� ֵ: ��
+***********************************************************************
+*/
+void IWDG_Feed(void)
+{   
+ 	IWDG_ReloadCounter();					//reload										   
+}
+
+/*
+***********************************************************************
+*	�� �� ��: IWDG_FeedTask
+*	����˵��: ���Ź�ι������
+*	��    �Σ���        
+*	�� �� ֵ: ��
+***********************************************************************
+*/
+void IWDG_FeedTask(void)
+{
+	static timer WDG_feedTimer;							//���Ź�ι��ʱ��
+	
+	static uint8_t timer_ok = 0;
+	if(timer_ok == 0)
+	{
+		timer_ok = 1;
+		timer_set(&WDG_feedTimer, 5);		
+	}
+	
+	if(timer_expired(&WDG_feedTimer))
+	{
+		timer_restart(&WDG_feedTimer);
+		IWDG_Feed();													//ι��
+// 		printf("\r\nι��\r\n");
+	}
+}
+
+/******************** (C) COPYRIGHT 2017 CXHY *****END OF FILE*******************/ 
diff --git a/STM32_4路称重_Git提交精简工程/src/HARDWARE/WDG/wdg.h b/STM32_4路称重_Git提交精简工程/src/HARDWARE/WDG/wdg.h
new file mode 100755
index 0000000..93e59be
--- /dev/null
+++ b/STM32_4路称重_Git提交精简工程/src/HARDWARE/WDG/wdg.h
@@ -0,0 +1,18 @@
+/*************************** (C) COPYRIGHT 2017 ping ****************************
+ * �ļ���  ��wdg.h
+ * ��  ��  �����Ź�ͷ�ļ�
+ * ��  ��  ��V1.0
+ * ��  ��  ��XuZhongPing
+ * ��  ��  ��2017/02/05 
+*********************************************************************************/
+#ifndef __WDG_H
+#define __WDG_H
+#include "stm32f10x.h"
+
+void IWDG_Init(uint8_t prer, uint16_t rlr);
+void IWDG_Feed(void);
+void IWDG_FeedTask(void);
+
+#endif
+
+/******************** (C) COPYRIGHT 2017 ping *****END OF FILE*******************/ 
diff --git a/STM32_4路称重_Git提交精简工程/src/Project/Project.uvprojx b/STM32_4路称重_Git提交精简工程/src/Project/Project.uvprojx
new file mode 100755
index 0000000..b941a5a
--- /dev/null
+++ b/STM32_4路称重_Git提交精简工程/src/Project/Project.uvprojx
@@ -0,0 +1,751 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<Project xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_projx.xsd">
+
+  <SchemaVersion>2.1</SchemaVersion>
+
+  <Header>### uVision Project, (C) Keil Software</Header>
+
+  <Targets>
+    <Target>
+      <TargetName>Target 1</TargetName>
+      <ToolsetNumber>0x4</ToolsetNumber>
+      <ToolsetName>ARM-ADS</ToolsetName>
+      <pCCUsed>5060750::V5.06 update 6 (build 750)::ARMCC</pCCUsed>
+      <uAC6>0</uAC6>
+      <TargetOption>
+        <TargetCommonOption>
+          <Device>STM32F103RC</Device>
+          <Vendor>STMicroelectronics</Vendor>
+          <PackID>Keil.STM32F1xx_DFP.2.3.0</PackID>
+          <PackURL>http://www.keil.com/pack/</PackURL>
+          <Cpu>IRAM(0x20000000,0x0000C000) IROM(0x08000000,0x00040000) CPUTYPE("Cortex-M3") CLOCK(12000000) ELITTLE</Cpu>
+          <FlashUtilSpec></FlashUtilSpec>
+          <StartupFile></StartupFile>
+          <FlashDriverDll>UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0STM32F10x_512 -FS08000000 -FL080000 -FP0($$Device:STM32F103RC$Flash\STM32F10x_512.FLM))</FlashDriverDll>
+          <DeviceId>0</DeviceId>
+          <RegisterFile>$$Device:STM32F103RC$Device\Include\stm32f10x.h</RegisterFile>
+          <MemoryEnv></MemoryEnv>
+          <Cmp></Cmp>
+          <Asm></Asm>
+          <Linker></Linker>
+          <OHString></OHString>
+          <InfinionOptionDll></InfinionOptionDll>
+          <SLE66CMisc></SLE66CMisc>
+          <SLE66AMisc></SLE66AMisc>
+          <SLE66LinkerMisc></SLE66LinkerMisc>
+          <SFDFile>$$Device:STM32F103RC$SVD\STM32F103xx.svd</SFDFile>
+          <bCustSvd>0</bCustSvd>
+          <UseEnv>0</UseEnv>
+          <BinPath></BinPath>
+          <IncludePath></IncludePath>
+          <LibPath></LibPath>
+          <RegisterFilePath></RegisterFilePath>
+          <DBRegisterFilePath></DBRegisterFilePath>
+          <TargetStatus>
+            <Error>0</Error>
+            <ExitCodeStop>0</ExitCodeStop>
+            <ButtonStop>0</ButtonStop>
+            <NotGenerated>0</NotGenerated>
+            <InvalidFlash>1</InvalidFlash>
+          </TargetStatus>
+          <OutputDirectory>..\Output\</OutputDirectory>
+          <OutputName>HEX_Output</OutputName>
+          <CreateExecutable>1</CreateExecutable>
+          <CreateLib>0</CreateLib>
+          <CreateHexFile>1</CreateHexFile>
+          <DebugInformation>1</DebugInformation>
+          <BrowseInformation>1</BrowseInformation>
+          <ListingPath>..\Listing\</ListingPath>
+          <HexFormatSelection>1</HexFormatSelection>
+          <Merge32K>0</Merge32K>
+          <CreateBatchFile>0</CreateBatchFile>
+          <BeforeCompile>
+            <RunUserProg1>0</RunUserProg1>
+            <RunUserProg2>0</RunUserProg2>
+            <UserProg1Name></UserProg1Name>
+            <UserProg2Name></UserProg2Name>
+            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+            <nStopU1X>0</nStopU1X>
+            <nStopU2X>0</nStopU2X>
+          </BeforeCompile>
+          <BeforeMake>
+            <RunUserProg1>0</RunUserProg1>
+            <RunUserProg2>0</RunUserProg2>
+            <UserProg1Name></UserProg1Name>
+            <UserProg2Name></UserProg2Name>
+            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+            <nStopB1X>0</nStopB1X>
+            <nStopB2X>0</nStopB2X>
+          </BeforeMake>
+          <AfterMake>
+            <RunUserProg1>0</RunUserProg1>
+            <RunUserProg2>0</RunUserProg2>
+            <UserProg1Name></UserProg1Name>
+            <UserProg2Name></UserProg2Name>
+            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+            <nStopA1X>0</nStopA1X>
+            <nStopA2X>0</nStopA2X>
+          </AfterMake>
+          <SelectedForBatchBuild>0</SelectedForBatchBuild>
+          <SVCSIdString></SVCSIdString>
+        </TargetCommonOption>
+        <CommonProperty>
+          <UseCPPCompiler>0</UseCPPCompiler>
+          <RVCTCodeConst>0</RVCTCodeConst>
+          <RVCTZI>0</RVCTZI>
+          <RVCTOtherData>0</RVCTOtherData>
+          <ModuleSelection>0</ModuleSelection>
+          <IncludeInBuild>1</IncludeInBuild>
+          <AlwaysBuild>0</AlwaysBuild>
+          <GenerateAssemblyFile>0</GenerateAssemblyFile>
+          <AssembleAssemblyFile>0</AssembleAssemblyFile>
+          <PublicsOnly>0</PublicsOnly>
+          <StopOnExitCode>3</StopOnExitCode>
+          <CustomArgument></CustomArgument>
+          <IncludeLibraryModules></IncludeLibraryModules>
+          <ComprImg>1</ComprImg>
+        </CommonProperty>
+        <DllOption>
+          <SimDllName>SARMCM3.DLL</SimDllName>
+          <SimDllArguments> -REMAP</SimDllArguments>
+          <SimDlgDll>DCM.DLL</SimDlgDll>
+          <SimDlgDllArguments>-pCM3</SimDlgDllArguments>
+          <TargetDllName>SARMCM3.DLL</TargetDllName>
+          <TargetDllArguments></TargetDllArguments>
+          <TargetDlgDll>TCM.DLL</TargetDlgDll>
+          <TargetDlgDllArguments>-pCM3</TargetDlgDllArguments>
+        </DllOption>
+        <DebugOption>
+          <OPTHX>
+            <HexSelection>1</HexSelection>
+            <HexRangeLowAddress>0</HexRangeLowAddress>
+            <HexRangeHighAddress>0</HexRangeHighAddress>
+            <HexOffset>0</HexOffset>
+            <Oh166RecLen>16</Oh166RecLen>
+          </OPTHX>
+        </DebugOption>
+        <Utilities>
+          <Flash1>
+            <UseTargetDll>1</UseTargetDll>
+            <UseExternalTool>0</UseExternalTool>
+            <RunIndependent>0</RunIndependent>
+            <UpdateFlashBeforeDebugging>1</UpdateFlashBeforeDebugging>
+            <Capability>1</Capability>
+            <DriverSelection>4096</DriverSelection>
+          </Flash1>
+          <bUseTDR>1</bUseTDR>
+          <Flash2>BIN\UL2CM3.DLL</Flash2>
+          <Flash3>"" ()</Flash3>
+          <Flash4></Flash4>
+          <pFcarmOut></pFcarmOut>
+          <pFcarmGrp></pFcarmGrp>
+          <pFcArmRoot></pFcArmRoot>
+          <FcArmLst>0</FcArmLst>
+        </Utilities>
+        <TargetArmAds>
+          <ArmAdsMisc>
+            <GenerateListings>0</GenerateListings>
+            <asHll>1</asHll>
+            <asAsm>1</asAsm>
+            <asMacX>1</asMacX>
+            <asSyms>1</asSyms>
+            <asFals>1</asFals>
+            <asDbgD>1</asDbgD>
+            <asForm>1</asForm>
+            <ldLst>0</ldLst>
+            <ldmm>1</ldmm>
+            <ldXref>1</ldXref>
+            <BigEnd>0</BigEnd>
+            <AdsALst>1</AdsALst>
+            <AdsACrf>1</AdsACrf>
+            <AdsANop>0</AdsANop>
+            <AdsANot>0</AdsANot>
+            <AdsLLst>1</AdsLLst>
+            <AdsLmap>1</AdsLmap>
+            <AdsLcgr>1</AdsLcgr>
+            <AdsLsym>1</AdsLsym>
+            <AdsLszi>1</AdsLszi>
+            <AdsLtoi>1</AdsLtoi>
+            <AdsLsun>1</AdsLsun>
+            <AdsLven>1</AdsLven>
+            <AdsLsxf>1</AdsLsxf>
+            <RvctClst>0</RvctClst>
+            <GenPPlst>0</GenPPlst>
+            <AdsCpuType>"Cortex-M3"</AdsCpuType>
+            <RvctDeviceName></RvctDeviceName>
+            <mOS>0</mOS>
+            <uocRom>0</uocRom>
+            <uocRam>0</uocRam>
+            <hadIROM>1</hadIROM>
+            <hadIRAM>1</hadIRAM>
+            <hadXRAM>0</hadXRAM>
+            <uocXRam>0</uocXRam>
+            <RvdsVP>0</RvdsVP>
+            <hadIRAM2>0</hadIRAM2>
+            <hadIROM2>0</hadIROM2>
+            <StupSel>8</StupSel>
+            <useUlib>0</useUlib>
+            <EndSel>0</EndSel>
+            <uLtcg>0</uLtcg>
+            <nSecure>0</nSecure>
+            <RoSelD>3</RoSelD>
+            <RwSelD>3</RwSelD>
+            <CodeSel>0</CodeSel>
+            <OptFeed>0</OptFeed>
+            <NoZi1>0</NoZi1>
+            <NoZi2>0</NoZi2>
+            <NoZi3>0</NoZi3>
+            <NoZi4>0</NoZi4>
+            <NoZi5>0</NoZi5>
+            <Ro1Chk>0</Ro1Chk>
+            <Ro2Chk>0</Ro2Chk>
+            <Ro3Chk>0</Ro3Chk>
+            <Ir1Chk>1</Ir1Chk>
+            <Ir2Chk>0</Ir2Chk>
+            <Ra1Chk>0</Ra1Chk>
+            <Ra2Chk>0</Ra2Chk>
+            <Ra3Chk>0</Ra3Chk>
+            <Im1Chk>1</Im1Chk>
+            <Im2Chk>0</Im2Chk>
+            <OnChipMemories>
+              <Ocm1>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm1>
+              <Ocm2>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm2>
+              <Ocm3>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm3>
+              <Ocm4>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm4>
+              <Ocm5>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm5>
+              <Ocm6>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm6>
+              <IRAM>
+                <Type>0</Type>
+                <StartAddress>0x20000000</StartAddress>
+                <Size>0xc000</Size>
+              </IRAM>
+              <IROM>
+                <Type>1</Type>
+                <StartAddress>0x8000000</StartAddress>
+                <Size>0x40000</Size>
+              </IROM>
+              <XRAM>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </XRAM>
+              <OCR_RVCT1>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT1>
+              <OCR_RVCT2>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT2>
+              <OCR_RVCT3>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT3>
+              <OCR_RVCT4>
+                <Type>1</Type>
+                <StartAddress>0x8000000</StartAddress>
+                <Size>0x40000</Size>
+              </OCR_RVCT4>
+              <OCR_RVCT5>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT5>
+              <OCR_RVCT6>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT6>
+              <OCR_RVCT7>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT7>
+              <OCR_RVCT8>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT8>
+              <OCR_RVCT9>
+                <Type>0</Type>
+                <StartAddress>0x20000000</StartAddress>
+                <Size>0xc000</Size>
+              </OCR_RVCT9>
+              <OCR_RVCT10>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT10>
+            </OnChipMemories>
+            <RvctStartVector></RvctStartVector>
+          </ArmAdsMisc>
+          <Cads>
+            <interw>1</interw>
+            <Optim>4</Optim>
+            <oTime>0</oTime>
+            <SplitLS>0</SplitLS>
+            <OneElfS>1</OneElfS>
+            <Strict>0</Strict>
+            <EnumInt>0</EnumInt>
+            <PlainCh>0</PlainCh>
+            <Ropi>0</Ropi>
+            <Rwpi>0</Rwpi>
+            <wLevel>0</wLevel>
+            <uThumb>0</uThumb>
+            <uSurpInc>0</uSurpInc>
+            <uC99>0</uC99>
+            <uGnu>0</uGnu>
+            <useXO>0</useXO>
+            <v6Lang>1</v6Lang>
+            <v6LangP>1</v6LangP>
+            <vShortEn>1</vShortEn>
+            <vShortWch>1</vShortWch>
+            <v6Lto>0</v6Lto>
+            <v6WtE>0</v6WtE>
+            <v6Rtti>0</v6Rtti>
+            <VariousControls>
+              <MiscControls></MiscControls>
+              <Define>STM32F10X_HD,USE_STDPERIPH_DRIVER</Define>
+              <Undefine></Undefine>
+              <IncludePath>..\USER;..\CORE;..\SYSTEM\delay;..\SYSTEM\debug;..\SYSTEM\usart;..\STM32F10x_FWLib\inc;..\HARDWARE\LED;..\HARDWARE\KEY;..\HARDWARE\LCD;..\HARDWARE\24CXX;..\HARDWARE\FLASH;..\HARDWARE\IIC;..\HARDWARE\SPI;..\HARDWARE\BUZZER;..\HARDWARE\RFID;..\HARDWARE\EXTI;..\HARDWARE\TIMER;..\HARDWARE\UltrasonicWave;..\HARDWARE\USART;..\HARDWARE\GPS;..\HARDWARE\GSM;..\HARDWARE\QR_Code;..\HARDWARE\DEVICE;..\HARDWARE\LCD;..\HARDWARE\NTC_ADC;..\HARDWARE\WDG;..\HARDWARE\SCALE;..\HARDWARE\ElectronicLock;..\HARDWARE\MOTOR;..\HARDWARE\AUDIO;..\HARDWARE\FLASH;..\HARDWARE\OPTO_SWITCH;..\HARDWARE\IR_Distancer;..\HARDWARE\RS485;..\HARDWARE\STMFLASH;..\HARDWARE\Disinfection</IncludePath>
+            </VariousControls>
+          </Cads>
+          <Aads>
+            <interw>1</interw>
+            <Ropi>0</Ropi>
+            <Rwpi>0</Rwpi>
+            <thumb>0</thumb>
+            <SplitLS>0</SplitLS>
+            <SwStkChk>0</SwStkChk>
+            <NoWarn>0</NoWarn>
+            <uSurpInc>0</uSurpInc>
+            <useXO>0</useXO>
+            <uClangAs>0</uClangAs>
+            <VariousControls>
+              <MiscControls></MiscControls>
+              <Define></Define>
+              <Undefine></Undefine>
+              <IncludePath></IncludePath>
+            </VariousControls>
+          </Aads>
+          <LDads>
+            <umfTarg>1</umfTarg>
+            <Ropi>0</Ropi>
+            <Rwpi>0</Rwpi>
+            <noStLib>0</noStLib>
+            <RepFail>1</RepFail>
+            <useFile>0</useFile>
+            <TextAddressRange>0x08000000</TextAddressRange>
+            <DataAddressRange>0x20000000</DataAddressRange>
+            <pXoBase></pXoBase>
+            <ScatterFile></ScatterFile>
+            <IncludeLibs></IncludeLibs>
+            <IncludeLibsPath></IncludeLibsPath>
+            <Misc></Misc>
+            <LinkerInputFile></LinkerInputFile>
+            <DisabledWarnings></DisabledWarnings>
+          </LDads>
+        </TargetArmAds>
+      </TargetOption>
+      <Groups>
+        <Group>
+          <GroupName>USER</GroupName>
+          <Files>
+            <File>
+              <FileName>main.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\USER\main.c</FilePath>
+            </File>
+            <File>
+              <FileName>stm32f10x_it.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\USER\stm32f10x_it.c</FilePath>
+            </File>
+            <File>
+              <FileName>system_stm32f10x.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\CMSIS\system_stm32f10x.c</FilePath>
+            </File>
+            <File>
+              <FileName>data_typedef.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\USER\data_typedef.c</FilePath>
+            </File>
+            <File>
+              <FileName>message.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\USER\message.c</FilePath>
+            </File>
+            <File>
+              <FileName>my_math.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\USER\my_math.c</FilePath>
+            </File>
+            <File>
+              <FileName>date_time.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\USER\date_time.c</FilePath>
+            </File>
+            <File>
+              <FileName>tcp_protocol.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\USER\tcp_protocol.c</FilePath>
+            </File>
+            <File>
+              <FileName>pc_protocol.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\USER\pc_protocol.c</FilePath>
+            </File>
+            <File>
+              <FileName>user_app.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\USER\user_app.c</FilePath>
+            </File>
+            <File>
+              <FileName>user_manag.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\USER\user_manag.c</FilePath>
+            </File>
+          </Files>
+        </Group>
+        <Group>
+          <GroupName>HARDWARE</GroupName>
+          <Files>
+            <File>
+              <FileName>wdg.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\HARDWARE\WDG\wdg.c</FilePath>
+            </File>
+            <File>
+              <FileName>timer.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\HARDWARE\TIMER\timer.c</FilePath>
+            </File>
+            <File>
+              <FileName>usart1.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\HARDWARE\USART\usart1.c</FilePath>
+            </File>
+            <File>
+              <FileName>usart2.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\HARDWARE\USART\usart2.c</FilePath>
+            </File>
+            <File>
+              <FileName>usart3.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\HARDWARE\USART\usart3.c</FilePath>
+            </File>
+            <File>
+              <FileName>usart4.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\HARDWARE\USART\usart4.c</FilePath>
+            </File>
+            <File>
+              <FileName>usart5.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\HARDWARE\USART\usart5.c</FilePath>
+            </File>
+            <File>
+              <FileName>led.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\HARDWARE\LED\led.c</FilePath>
+            </File>
+            <File>
+              <FileName>key.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\HARDWARE\KEY\key.c</FilePath>
+            </File>
+            <File>
+              <FileName>buzzer.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\HARDWARE\BUZZER\buzzer.c</FilePath>
+            </File>
+            <File>
+              <FileName>scale.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\HARDWARE\SCALE\scale.c</FilePath>
+            </File>
+            <File>
+              <FileName>gps.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\HARDWARE\GPS\gps.c</FilePath>
+            </File>
+            <File>
+              <FileName>gsm_uart.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\HARDWARE\GSM\gsm_uart.c</FilePath>
+            </File>
+            <File>
+              <FileName>ec200x.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\HARDWARE\GSM\ec200x.c</FilePath>
+            </File>
+            <File>
+              <FileName>at_proc.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\HARDWARE\GSM\at_proc.c</FilePath>
+            </File>
+            <File>
+              <FileName>netwer_appcall.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\HARDWARE\GSM\netwer_appcall.c</FilePath>
+            </File>
+            <File>
+              <FileName>rfid_decode_yn.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\HARDWARE\RFID\rfid_decode_yn.c</FilePath>
+            </File>
+            <File>
+              <FileName>rfid_decode_yhk.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\HARDWARE\RFID\rfid_decode_yhk.c</FilePath>
+            </File>
+            <File>
+              <FileName>rfid_decode_zl.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\HARDWARE\RFID\rfid_decode_zl.c</FilePath>
+            </File>
+            <File>
+              <FileName>RFID_IC.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\HARDWARE\RFID\RFID_IC.c</FilePath>
+            </File>
+            <File>
+              <FileName>qr_code.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\HARDWARE\QR_Code\qr_code.c</FilePath>
+            </File>
+            <File>
+              <FileName>adc.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\HARDWARE\NTC_ADC\adc.c</FilePath>
+            </File>
+            <File>
+              <FileName>ntc.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\HARDWARE\NTC_ADC\ntc.c</FilePath>
+            </File>
+            <File>
+              <FileName>display.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\HARDWARE\LCD\display.c</FilePath>
+            </File>
+            <File>
+              <FileName>lcd.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\HARDWARE\LCD\lcd.c</FilePath>
+            </File>
+            <File>
+              <FileName>lcd12864.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\HARDWARE\LCD\lcd12864.c</FilePath>
+            </File>
+            <File>
+              <FileName>ElectronicLock.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\HARDWARE\ElectronicLock\ElectronicLock.c</FilePath>
+            </File>
+            <File>
+              <FileName>motor.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\HARDWARE\MOTOR\motor.c</FilePath>
+            </File>
+            <File>
+              <FileName>door_ctrl.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\HARDWARE\MOTOR\door_ctrl.c</FilePath>
+            </File>
+            <File>
+              <FileName>device.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\HARDWARE\DEVICE\device.c</FilePath>
+            </File>
+            <File>
+              <FileName>deviceSet.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\HARDWARE\DEVICE\deviceSet.c</FilePath>
+            </File>
+            <File>
+              <FileName>IR_Distancer.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\HARDWARE\IR_Distancer\IR_Distancer.c</FilePath>
+            </File>
+            <File>
+              <FileName>distancer.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\HARDWARE\DEVICE\distancer.c</FilePath>
+            </File>
+            <File>
+              <FileName>sound.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\HARDWARE\AUDIO\sound.c</FilePath>
+            </File>
+            <File>
+              <FileName>spi.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\HARDWARE\SPI\spi.c</FilePath>
+            </File>
+            <File>
+              <FileName>stmflash.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\HARDWARE\STMFLASH\stmflash.c</FilePath>
+            </File>
+            <File>
+              <FileName>m_s_comm.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\HARDWARE\DEVICE\m_s_comm.c</FilePath>
+            </File>
+            <File>
+              <FileName>disinfection.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\HARDWARE\Disinfection\disinfection.c</FilePath>
+            </File>
+          </Files>
+        </Group>
+        <Group>
+          <GroupName>SYSTEM</GroupName>
+          <Files>
+            <File>
+              <FileName>delay.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\SYSTEM\delay\delay.c</FilePath>
+            </File>
+            <File>
+              <FileName>debug_conf.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\SYSTEM\debug\debug_conf.c</FilePath>
+            </File>
+          </Files>
+        </Group>
+        <Group>
+          <GroupName>CORE</GroupName>
+          <Files>
+            <File>
+              <FileName>core_cm3.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\CMSIS\core_cm3.c</FilePath>
+            </File>
+            <File>
+              <FileName>startup_stm32f10x_hd.s</FileName>
+              <FileType>2</FileType>
+              <FilePath>..\CMSIS\Startup\startup_stm32f10x_hd.s</FilePath>
+            </File>
+          </Files>
+        </Group>
+        <Group>
+          <GroupName>FWLib</GroupName>
+          <Files>
+            <File>
+              <FileName>misc.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\STM32F10x_FWLib\src\misc.c</FilePath>
+            </File>
+            <File>
+              <FileName>stm32f10x_fsmc.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\STM32F10x_FWLib\src\stm32f10x_fsmc.c</FilePath>
+            </File>
+            <File>
+              <FileName>stm32f10x_gpio.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\STM32F10x_FWLib\src\stm32f10x_gpio.c</FilePath>
+            </File>
+            <File>
+              <FileName>stm32f10x_rcc.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\STM32F10x_FWLib\src\stm32f10x_rcc.c</FilePath>
+            </File>
+            <File>
+              <FileName>stm32f10x_usart.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\STM32F10x_FWLib\src\stm32f10x_usart.c</FilePath>
+            </File>
+            <File>
+              <FileName>stm32f10x_spi.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\STM32F10x_FWLib\src\stm32f10x_spi.c</FilePath>
+            </File>
+            <File>
+              <FileName>stm32f10x_exti.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\STM32F10x_FWLib\src\stm32f10x_exti.c</FilePath>
+            </File>
+            <File>
+              <FileName>stm32f10x_tim.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\STM32F10x_FWLib\src\stm32f10x_tim.c</FilePath>
+            </File>
+            <File>
+              <FileName>stm32f10x_dma.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\STM32F10x_FWLib\src\stm32f10x_dma.c</FilePath>
+            </File>
+            <File>
+              <FileName>stm32f10x_adc.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\STM32F10x_FWLib\src\stm32f10x_adc.c</FilePath>
+            </File>
+            <File>
+              <FileName>stm32f10x_iwdg.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\STM32F10x_FWLib\src\stm32f10x_iwdg.c</FilePath>
+            </File>
+            <File>
+              <FileName>stm32f10x_flash.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\STM32F10x_FWLib\src\stm32f10x_flash.c</FilePath>
+            </File>
+          </Files>
+        </Group>
+        <Group>
+          <GroupName>::CMSIS</GroupName>
+        </Group>
+      </Groups>
+    </Target>
+  </Targets>
+
+  <RTE>
+    <apis/>
+    <components>
+      <component Cclass="CMSIS" Cgroup="CORE" Cvendor="ARM" Cversion="5.1.1" condition="ARMv6_7_8-M Device">
+        <package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.3.0"/>
+        <targetInfos>
+          <targetInfo name="Target 1"/>
+        </targetInfos>
+      </component>
+    </components>
+    <files/>
+  </RTE>
+
+</Project>
diff --git a/STM32_4路称重_Git提交精简工程/src/Project/stm32f10x_conf.h b/STM32_4路称重_Git提交精简工程/src/Project/stm32f10x_conf.h
new file mode 100755
index 0000000..fd1c485
--- /dev/null
+++ b/STM32_4路称重_Git提交精简工程/src/Project/stm32f10x_conf.h
@@ -0,0 +1,77 @@
+/**
+  ******************************************************************************
+  * @file    GPIO/IOToggle/stm32f10x_conf.h 
+  * @author  MCD Application Team
+  * @version V3.5.0
+  * @date    08-April-2011
+  * @brief   Library configuration file.
+  ******************************************************************************
+  * @attention
+  *
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+  *
+  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F10x_CONF_H
+#define __STM32F10x_CONF_H
+
+/* Includes ------------------------------------------------------------------*/
+/* Uncomment/Comment the line below to enable/disable peripheral header file inclusion */
+//#include "stm32f10x_adc.h"
+//#include "stm32f10x_bkp.h"
+//#include "stm32f10x_can.h"
+//#include "stm32f10x_cec.h"
+//#include "stm32f10x_crc.h"
+//#include "stm32f10x_dac.h"
+#include "stm32f10x_dbgmcu.h"
+#include "stm32f10x_dma.h"
+#include "stm32f10x_exti.h"
+#include "stm32f10x_flash.h"
+#include "stm32f10x_fsmc.h"
+#include "stm32f10x_gpio.h"
+//#include "stm32f10x_i2c.h"
+//#include "stm32f10x_iwdg.h"
+//#include "stm32f10x_pwr.h"
+#include "stm32f10x_rcc.h"
+#include "stm32f10x_rtc.h"
+//#include "stm32f10x_sdio.h"
+#include "stm32f10x_spi.h"
+#include "stm32f10x_tim.h"
+#include "stm32f10x_usart.h"
+//#include "stm32f10x_wwdg.h"
+#include "misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/* Uncomment the line below to expanse the "assert_param" macro in the 
+   Standard Peripheral Library drivers code */
+/* #define USE_FULL_ASSERT    1 */
+
+/* Exported macro ------------------------------------------------------------*/
+#ifdef  USE_FULL_ASSERT
+
+/**
+  * @brief  The assert_param macro is used for function's parameters check.
+  * @param  expr: If expr is false, it calls assert_failed function which reports 
+  *         the name of the source file and the source line number of the call 
+  *         that failed. If expr is true, it returns no value.
+  * @retval None
+  */
+  #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
+/* Exported functions ------------------------------------------------------- */
+  void assert_failed(uint8_t* file, uint32_t line);
+#else
+  #define assert_param(expr) ((void)0)
+#endif /* USE_FULL_ASSERT */
+
+#endif /* __STM32F10x_CONF_H */
+
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/STM32_4路称重_Git提交精简工程/src/STM32F10x_FWLib/inc/misc.h b/STM32_4路称重_Git提交精简工程/src/STM32F10x_FWLib/inc/misc.h
new file mode 100755
index 0000000..7d401ca
--- /dev/null
+++ b/STM32_4路称重_Git提交精简工程/src/STM32F10x_FWLib/inc/misc.h
@@ -0,0 +1,220 @@
+/**
+  ******************************************************************************
+  * @file    misc.h
+  * @author  MCD Application Team
+  * @version V3.5.0
+  * @date    11-March-2011
+  * @brief   This file contains all the functions prototypes for the miscellaneous
+  *          firmware library functions (add-on to CMSIS functions).
+  ******************************************************************************
+  * @attention
+  *
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+  *
+  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __MISC_H
+#define __MISC_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x.h"
+
+/** @addtogroup STM32F10x_StdPeriph_Driver
+  * @{
+  */
+
+/** @addtogroup MISC
+  * @{
+  */
+
+/** @defgroup MISC_Exported_Types
+  * @{
+  */
+
+/** 
+  * @brief  NVIC Init Structure definition  
+  */
+
+typedef struct
+{
+  uint8_t NVIC_IRQChannel;                    /*!< Specifies the IRQ channel to be enabled or disabled.
+                                                   This parameter can be a value of @ref IRQn_Type 
+                                                   (For the complete STM32 Devices IRQ Channels list, please
+                                                    refer to stm32f10x.h file) */
+
+  uint8_t NVIC_IRQChannelPreemptionPriority;  /*!< Specifies the pre-emption priority for the IRQ channel
+                                                   specified in NVIC_IRQChannel. This parameter can be a value
+                                                   between 0 and 15 as described in the table @ref NVIC_Priority_Table */
+
+  uint8_t NVIC_IRQChannelSubPriority;         /*!< Specifies the subpriority level for the IRQ channel specified
+                                                   in NVIC_IRQChannel. This parameter can be a value
+                                                   between 0 and 15 as described in the table @ref NVIC_Priority_Table */
+
+  FunctionalState NVIC_IRQChannelCmd;         /*!< Specifies whether the IRQ channel defined in NVIC_IRQChannel
+                                                   will be enabled or disabled. 
+                                                   This parameter can be set either to ENABLE or DISABLE */   
+} NVIC_InitTypeDef;
+ 
+/**
+  * @}
+  */
+
+/** @defgroup NVIC_Priority_Table 
+  * @{
+  */
+
+/**
+@code  
+ The table below gives the allowed values of the pre-emption priority and subpriority according
+ to the Priority Grouping configuration performed by NVIC_PriorityGroupConfig function
+  ============================================================================================================================
+    NVIC_PriorityGroup   | NVIC_IRQChannelPreemptionPriority | NVIC_IRQChannelSubPriority  | Description
+  ============================================================================================================================
+   NVIC_PriorityGroup_0  |                0                  |            0-15             |   0 bits for pre-emption priority
+                         |                                   |                             |   4 bits for subpriority
+  ----------------------------------------------------------------------------------------------------------------------------
+   NVIC_PriorityGroup_1  |                0-1                |            0-7              |   1 bits for pre-emption priority
+                         |                                   |                             |   3 bits for subpriority
+  ----------------------------------------------------------------------------------------------------------------------------    
+   NVIC_PriorityGroup_2  |                0-3                |            0-3              |   2 bits for pre-emption priority
+                         |                                   |                             |   2 bits for subpriority
+  ----------------------------------------------------------------------------------------------------------------------------    
+   NVIC_PriorityGroup_3  |                0-7                |            0-1              |   3 bits for pre-emption priority
+                         |                                   |                             |   1 bits for subpriority
+  ----------------------------------------------------------------------------------------------------------------------------    
+   NVIC_PriorityGroup_4  |                0-15               |            0                |   4 bits for pre-emption priority
+                         |                                   |                             |   0 bits for subpriority                       
+  ============================================================================================================================
+@endcode
+*/
+
+/**
+  * @}
+  */
+
+/** @defgroup MISC_Exported_Constants
+  * @{
+  */
+
+/** @defgroup Vector_Table_Base 
+  * @{
+  */
+
+#define NVIC_VectTab_RAM             ((uint32_t)0x20000000)
+#define NVIC_VectTab_FLASH           ((uint32_t)0x08000000)
+#define IS_NVIC_VECTTAB(VECTTAB) (((VECTTAB) == NVIC_VectTab_RAM) || \
+                                  ((VECTTAB) == NVIC_VectTab_FLASH))
+/**
+  * @}
+  */
+
+/** @defgroup System_Low_Power 
+  * @{
+  */
+
+#define NVIC_LP_SEVONPEND            ((uint8_t)0x10)
+#define NVIC_LP_SLEEPDEEP            ((uint8_t)0x04)
+#define NVIC_LP_SLEEPONEXIT          ((uint8_t)0x02)
+#define IS_NVIC_LP(LP) (((LP) == NVIC_LP_SEVONPEND) || \
+                        ((LP) == NVIC_LP_SLEEPDEEP) || \
+                        ((LP) == NVIC_LP_SLEEPONEXIT))
+/**
+  * @}
+  */
+
+/** @defgroup Preemption_Priority_Group 
+  * @{
+  */
+
+#define NVIC_PriorityGroup_0         ((uint32_t)0x700) /*!< 0 bits for pre-emption priority
+                                                            4 bits for subpriority */
+#define NVIC_PriorityGroup_1         ((uint32_t)0x600) /*!< 1 bits for pre-emption priority
+                                                            3 bits for subpriority */
+#define NVIC_PriorityGroup_2         ((uint32_t)0x500) /*!< 2 bits for pre-emption priority
+                                                            2 bits for subpriority */
+#define NVIC_PriorityGroup_3         ((uint32_t)0x400) /*!< 3 bits for pre-emption priority
+                                                            1 bits for subpriority */
+#define NVIC_PriorityGroup_4         ((uint32_t)0x300) /*!< 4 bits for pre-emption priority
+                                                            0 bits for subpriority */
+
+#define IS_NVIC_PRIORITY_GROUP(GROUP) (((GROUP) == NVIC_PriorityGroup_0) || \
+                                       ((GROUP) == NVIC_PriorityGroup_1) || \
+                                       ((GROUP) == NVIC_PriorityGroup_2) || \
+                                       ((GROUP) == NVIC_PriorityGroup_3) || \
+                                       ((GROUP) == NVIC_PriorityGroup_4))
+
+#define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY)  ((PRIORITY) < 0x10)
+
+#define IS_NVIC_SUB_PRIORITY(PRIORITY)  ((PRIORITY) < 0x10)
+
+#define IS_NVIC_OFFSET(OFFSET)  ((OFFSET) < 0x000FFFFF)
+
+/**
+  * @}
+  */
+
+/** @defgroup SysTick_clock_source 
+  * @{
+  */
+
+#define SysTick_CLKSource_HCLK_Div8    ((uint32_t)0xFFFFFFFB)
+#define SysTick_CLKSource_HCLK         ((uint32_t)0x00000004)
+#define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SysTick_CLKSource_HCLK) || \
+                                       ((SOURCE) == SysTick_CLKSource_HCLK_Div8))
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup MISC_Exported_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup MISC_Exported_Functions
+  * @{
+  */
+
+void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup);
+void NVIC_Init(NVIC_InitTypeDef* NVIC_InitStruct);
+void NVIC_SetVectorTable(uint32_t NVIC_VectTab, uint32_t Offset);
+void NVIC_SystemLPConfig(uint8_t LowPowerMode, FunctionalState NewState);
+void SysTick_CLKSourceConfig(uint32_t SysTick_CLKSource);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __MISC_H */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/STM32_4路称重_Git提交精简工程/src/STM32F10x_FWLib/inc/stm32f10x_adc.h b/STM32_4路称重_Git提交精简工程/src/STM32F10x_FWLib/inc/stm32f10x_adc.h
new file mode 100755
index 0000000..d1b2653
--- /dev/null
+++ b/STM32_4路称重_Git提交精简工程/src/STM32F10x_FWLib/inc/stm32f10x_adc.h
@@ -0,0 +1,483 @@
+/**
+  ******************************************************************************
+  * @file    stm32f10x_adc.h
+  * @author  MCD Application Team
+  * @version V3.5.0
+  * @date    11-March-2011
+  * @brief   This file contains all the functions prototypes for the ADC firmware 
+  *          library.
+  ******************************************************************************
+  * @attention
+  *
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+  *
+  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F10x_ADC_H
+#define __STM32F10x_ADC_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x.h"
+
+/** @addtogroup STM32F10x_StdPeriph_Driver
+  * @{
+  */
+
+/** @addtogroup ADC
+  * @{
+  */
+
+/** @defgroup ADC_Exported_Types
+  * @{
+  */
+
+/** 
+  * @brief  ADC Init structure definition  
+  */
+
+typedef struct
+{
+  uint32_t ADC_Mode;                      /*!< Configures the ADC to operate in independent or
+                                               dual mode. 
+                                               This parameter can be a value of @ref ADC_mode */
+
+  FunctionalState ADC_ScanConvMode;       /*!< Specifies whether the conversion is performed in
+                                               Scan (multichannels) or Single (one channel) mode.
+                                               This parameter can be set to ENABLE or DISABLE */
+
+  FunctionalState ADC_ContinuousConvMode; /*!< Specifies whether the conversion is performed in
+                                               Continuous or Single mode.
+                                               This parameter can be set to ENABLE or DISABLE. */
+
+  uint32_t ADC_ExternalTrigConv;          /*!< Defines the external trigger used to start the analog
+                                               to digital conversion of regular channels. This parameter
+                                               can be a value of @ref ADC_external_trigger_sources_for_regular_channels_conversion */
+
+  uint32_t ADC_DataAlign;                 /*!< Specifies whether the ADC data alignment is left or right.
+                                               This parameter can be a value of @ref ADC_data_align */
+
+  uint8_t ADC_NbrOfChannel;               /*!< Specifies the number of ADC channels that will be converted
+                                               using the sequencer for regular channel group.
+                                               This parameter must range from 1 to 16. */
+}ADC_InitTypeDef;
+/**
+  * @}
+  */
+
+/** @defgroup ADC_Exported_Constants
+  * @{
+  */
+
+#define IS_ADC_ALL_PERIPH(PERIPH) (((PERIPH) == ADC1) || \
+                                   ((PERIPH) == ADC2) || \
+                                   ((PERIPH) == ADC3))
+
+#define IS_ADC_DMA_PERIPH(PERIPH) (((PERIPH) == ADC1) || \
+                                   ((PERIPH) == ADC3))
+
+/** @defgroup ADC_mode 
+  * @{
+  */
+
+#define ADC_Mode_Independent                       ((uint32_t)0x00000000)
+#define ADC_Mode_RegInjecSimult                    ((uint32_t)0x00010000)
+#define ADC_Mode_RegSimult_AlterTrig               ((uint32_t)0x00020000)
+#define ADC_Mode_InjecSimult_FastInterl            ((uint32_t)0x00030000)
+#define ADC_Mode_InjecSimult_SlowInterl            ((uint32_t)0x00040000)
+#define ADC_Mode_InjecSimult                       ((uint32_t)0x00050000)
+#define ADC_Mode_RegSimult                         ((uint32_t)0x00060000)
+#define ADC_Mode_FastInterl                        ((uint32_t)0x00070000)
+#define ADC_Mode_SlowInterl                        ((uint32_t)0x00080000)
+#define ADC_Mode_AlterTrig                         ((uint32_t)0x00090000)
+
+#define IS_ADC_MODE(MODE) (((MODE) == ADC_Mode_Independent) || \
+                           ((MODE) == ADC_Mode_RegInjecSimult) || \
+                           ((MODE) == ADC_Mode_RegSimult_AlterTrig) || \
+                           ((MODE) == ADC_Mode_InjecSimult_FastInterl) || \
+                           ((MODE) == ADC_Mode_InjecSimult_SlowInterl) || \
+                           ((MODE) == ADC_Mode_InjecSimult) || \
+                           ((MODE) == ADC_Mode_RegSimult) || \
+                           ((MODE) == ADC_Mode_FastInterl) || \
+                           ((MODE) == ADC_Mode_SlowInterl) || \
+                           ((MODE) == ADC_Mode_AlterTrig))
+/**
+  * @}
+  */
+
+/** @defgroup ADC_external_trigger_sources_for_regular_channels_conversion 
+  * @{
+  */
+
+#define ADC_ExternalTrigConv_T1_CC1                ((uint32_t)0x00000000) /*!< For ADC1 and ADC2 */
+#define ADC_ExternalTrigConv_T1_CC2                ((uint32_t)0x00020000) /*!< For ADC1 and ADC2 */
+#define ADC_ExternalTrigConv_T2_CC2                ((uint32_t)0x00060000) /*!< For ADC1 and ADC2 */
+#define ADC_ExternalTrigConv_T3_TRGO               ((uint32_t)0x00080000) /*!< For ADC1 and ADC2 */
+#define ADC_ExternalTrigConv_T4_CC4                ((uint32_t)0x000A0000) /*!< For ADC1 and ADC2 */
+#define ADC_ExternalTrigConv_Ext_IT11_TIM8_TRGO    ((uint32_t)0x000C0000) /*!< For ADC1 and ADC2 */
+
+#define ADC_ExternalTrigConv_T1_CC3                ((uint32_t)0x00040000) /*!< For ADC1, ADC2 and ADC3 */
+#define ADC_ExternalTrigConv_None                  ((uint32_t)0x000E0000) /*!< For ADC1, ADC2 and ADC3 */
+
+#define ADC_ExternalTrigConv_T3_CC1                ((uint32_t)0x00000000) /*!< For ADC3 only */
+#define ADC_ExternalTrigConv_T2_CC3                ((uint32_t)0x00020000) /*!< For ADC3 only */
+#define ADC_ExternalTrigConv_T8_CC1                ((uint32_t)0x00060000) /*!< For ADC3 only */
+#define ADC_ExternalTrigConv_T8_TRGO               ((uint32_t)0x00080000) /*!< For ADC3 only */
+#define ADC_ExternalTrigConv_T5_CC1                ((uint32_t)0x000A0000) /*!< For ADC3 only */
+#define ADC_ExternalTrigConv_T5_CC3                ((uint32_t)0x000C0000) /*!< For ADC3 only */
+
+#define IS_ADC_EXT_TRIG(REGTRIG) (((REGTRIG) == ADC_ExternalTrigConv_T1_CC1) || \
+                                  ((REGTRIG) == ADC_ExternalTrigConv_T1_CC2) || \
+                                  ((REGTRIG) == ADC_ExternalTrigConv_T1_CC3) || \
+                                  ((REGTRIG) == ADC_ExternalTrigConv_T2_CC2) || \
+                                  ((REGTRIG) == ADC_ExternalTrigConv_T3_TRGO) || \
+                                  ((REGTRIG) == ADC_ExternalTrigConv_T4_CC4) || \
+                                  ((REGTRIG) == ADC_ExternalTrigConv_Ext_IT11_TIM8_TRGO) || \
+                                  ((REGTRIG) == ADC_ExternalTrigConv_None) || \
+                                  ((REGTRIG) == ADC_ExternalTrigConv_T3_CC1) || \
+                                  ((REGTRIG) == ADC_ExternalTrigConv_T2_CC3) || \
+                                  ((REGTRIG) == ADC_ExternalTrigConv_T8_CC1) || \
+                                  ((REGTRIG) == ADC_ExternalTrigConv_T8_TRGO) || \
+                                  ((REGTRIG) == ADC_ExternalTrigConv_T5_CC1) || \
+                                  ((REGTRIG) == ADC_ExternalTrigConv_T5_CC3))
+/**
+  * @}
+  */
+
+/** @defgroup ADC_data_align 
+  * @{
+  */
+
+#define ADC_DataAlign_Right                        ((uint32_t)0x00000000)
+#define ADC_DataAlign_Left                         ((uint32_t)0x00000800)
+#define IS_ADC_DATA_ALIGN(ALIGN) (((ALIGN) == ADC_DataAlign_Right) || \
+                                  ((ALIGN) == ADC_DataAlign_Left))
+/**
+  * @}
+  */
+
+/** @defgroup ADC_channels 
+  * @{
+  */
+
+#define ADC_Channel_0                               ((uint8_t)0x00)
+#define ADC_Channel_1                               ((uint8_t)0x01)
+#define ADC_Channel_2                               ((uint8_t)0x02)
+#define ADC_Channel_3                               ((uint8_t)0x03)
+#define ADC_Channel_4                               ((uint8_t)0x04)
+#define ADC_Channel_5                               ((uint8_t)0x05)
+#define ADC_Channel_6                               ((uint8_t)0x06)
+#define ADC_Channel_7                               ((uint8_t)0x07)
+#define ADC_Channel_8                               ((uint8_t)0x08)
+#define ADC_Channel_9                               ((uint8_t)0x09)
+#define ADC_Channel_10                              ((uint8_t)0x0A)
+#define ADC_Channel_11                              ((uint8_t)0x0B)
+#define ADC_Channel_12                              ((uint8_t)0x0C)
+#define ADC_Channel_13                              ((uint8_t)0x0D)
+#define ADC_Channel_14                              ((uint8_t)0x0E)
+#define ADC_Channel_15                              ((uint8_t)0x0F)
+#define ADC_Channel_16                              ((uint8_t)0x10)
+#define ADC_Channel_17                              ((uint8_t)0x11)
+
+#define ADC_Channel_TempSensor                      ((uint8_t)ADC_Channel_16)
+#define ADC_Channel_Vrefint                         ((uint8_t)ADC_Channel_17)
+
+#define IS_ADC_CHANNEL(CHANNEL) (((CHANNEL) == ADC_Channel_0) || ((CHANNEL) == ADC_Channel_1) || \
+                                 ((CHANNEL) == ADC_Channel_2) || ((CHANNEL) == ADC_Channel_3) || \
+                                 ((CHANNEL) == ADC_Channel_4) || ((CHANNEL) == ADC_Channel_5) || \
+                                 ((CHANNEL) == ADC_Channel_6) || ((CHANNEL) == ADC_Channel_7) || \
+                                 ((CHANNEL) == ADC_Channel_8) || ((CHANNEL) == ADC_Channel_9) || \
+                                 ((CHANNEL) == ADC_Channel_10) || ((CHANNEL) == ADC_Channel_11) || \
+                                 ((CHANNEL) == ADC_Channel_12) || ((CHANNEL) == ADC_Channel_13) || \
+                                 ((CHANNEL) == ADC_Channel_14) || ((CHANNEL) == ADC_Channel_15) || \
+                                 ((CHANNEL) == ADC_Channel_16) || ((CHANNEL) == ADC_Channel_17))
+/**
+  * @}
+  */
+
+/** @defgroup ADC_sampling_time 
+  * @{
+  */
+
+#define ADC_SampleTime_1Cycles5                    ((uint8_t)0x00)
+#define ADC_SampleTime_7Cycles5                    ((uint8_t)0x01)
+#define ADC_SampleTime_13Cycles5                   ((uint8_t)0x02)
+#define ADC_SampleTime_28Cycles5                   ((uint8_t)0x03)
+#define ADC_SampleTime_41Cycles5                   ((uint8_t)0x04)
+#define ADC_SampleTime_55Cycles5                   ((uint8_t)0x05)
+#define ADC_SampleTime_71Cycles5                   ((uint8_t)0x06)
+#define ADC_SampleTime_239Cycles5                  ((uint8_t)0x07)
+#define IS_ADC_SAMPLE_TIME(TIME) (((TIME) == ADC_SampleTime_1Cycles5) || \
+                                  ((TIME) == ADC_SampleTime_7Cycles5) || \
+                                  ((TIME) == ADC_SampleTime_13Cycles5) || \
+                                  ((TIME) == ADC_SampleTime_28Cycles5) || \
+                                  ((TIME) == ADC_SampleTime_41Cycles5) || \
+                                  ((TIME) == ADC_SampleTime_55Cycles5) || \
+                                  ((TIME) == ADC_SampleTime_71Cycles5) || \
+                                  ((TIME) == ADC_SampleTime_239Cycles5))
+/**
+  * @}
+  */
+
+/** @defgroup ADC_external_trigger_sources_for_injected_channels_conversion 
+  * @{
+  */
+
+#define ADC_ExternalTrigInjecConv_T2_TRGO           ((uint32_t)0x00002000) /*!< For ADC1 and ADC2 */
+#define ADC_ExternalTrigInjecConv_T2_CC1            ((uint32_t)0x00003000) /*!< For ADC1 and ADC2 */
+#define ADC_ExternalTrigInjecConv_T3_CC4            ((uint32_t)0x00004000) /*!< For ADC1 and ADC2 */
+#define ADC_ExternalTrigInjecConv_T4_TRGO           ((uint32_t)0x00005000) /*!< For ADC1 and ADC2 */
+#define ADC_ExternalTrigInjecConv_Ext_IT15_TIM8_CC4 ((uint32_t)0x00006000) /*!< For ADC1 and ADC2 */
+
+#define ADC_ExternalTrigInjecConv_T1_TRGO           ((uint32_t)0x00000000) /*!< For ADC1, ADC2 and ADC3 */
+#define ADC_ExternalTrigInjecConv_T1_CC4            ((uint32_t)0x00001000) /*!< For ADC1, ADC2 and ADC3 */
+#define ADC_ExternalTrigInjecConv_None              ((uint32_t)0x00007000) /*!< For ADC1, ADC2 and ADC3 */
+
+#define ADC_ExternalTrigInjecConv_T4_CC3            ((uint32_t)0x00002000) /*!< For ADC3 only */
+#define ADC_ExternalTrigInjecConv_T8_CC2            ((uint32_t)0x00003000) /*!< For ADC3 only */
+#define ADC_ExternalTrigInjecConv_T8_CC4            ((uint32_t)0x00004000) /*!< For ADC3 only */
+#define ADC_ExternalTrigInjecConv_T5_TRGO           ((uint32_t)0x00005000) /*!< For ADC3 only */
+#define ADC_ExternalTrigInjecConv_T5_CC4            ((uint32_t)0x00006000) /*!< For ADC3 only */
+
+#define IS_ADC_EXT_INJEC_TRIG(INJTRIG) (((INJTRIG) == ADC_ExternalTrigInjecConv_T1_TRGO) || \
+                                        ((INJTRIG) == ADC_ExternalTrigInjecConv_T1_CC4) || \
+                                        ((INJTRIG) == ADC_ExternalTrigInjecConv_T2_TRGO) || \
+                                        ((INJTRIG) == ADC_ExternalTrigInjecConv_T2_CC1) || \
+                                        ((INJTRIG) == ADC_ExternalTrigInjecConv_T3_CC4) || \
+                                        ((INJTRIG) == ADC_ExternalTrigInjecConv_T4_TRGO) || \
+                                        ((INJTRIG) == ADC_ExternalTrigInjecConv_Ext_IT15_TIM8_CC4) || \
+                                        ((INJTRIG) == ADC_ExternalTrigInjecConv_None) || \
+                                        ((INJTRIG) == ADC_ExternalTrigInjecConv_T4_CC3) || \
+                                        ((INJTRIG) == ADC_ExternalTrigInjecConv_T8_CC2) || \
+                                        ((INJTRIG) == ADC_ExternalTrigInjecConv_T8_CC4) || \
+                                        ((INJTRIG) == ADC_ExternalTrigInjecConv_T5_TRGO) || \
+                                        ((INJTRIG) == ADC_ExternalTrigInjecConv_T5_CC4))
+/**
+  * @}
+  */
+
+/** @defgroup ADC_injected_channel_selection 
+  * @{
+  */
+
+#define ADC_InjectedChannel_1                       ((uint8_t)0x14)
+#define ADC_InjectedChannel_2                       ((uint8_t)0x18)
+#define ADC_InjectedChannel_3                       ((uint8_t)0x1C)
+#define ADC_InjectedChannel_4                       ((uint8_t)0x20)
+#define IS_ADC_INJECTED_CHANNEL(CHANNEL) (((CHANNEL) == ADC_InjectedChannel_1) || \
+                                          ((CHANNEL) == ADC_InjectedChannel_2) || \
+                                          ((CHANNEL) == ADC_InjectedChannel_3) || \
+                                          ((CHANNEL) == ADC_InjectedChannel_4))
+/**
+  * @}
+  */
+
+/** @defgroup ADC_analog_watchdog_selection 
+  * @{
+  */
+
+#define ADC_AnalogWatchdog_SingleRegEnable         ((uint32_t)0x00800200)
+#define ADC_AnalogWatchdog_SingleInjecEnable       ((uint32_t)0x00400200)
+#define ADC_AnalogWatchdog_SingleRegOrInjecEnable  ((uint32_t)0x00C00200)
+#define ADC_AnalogWatchdog_AllRegEnable            ((uint32_t)0x00800000)
+#define ADC_AnalogWatchdog_AllInjecEnable          ((uint32_t)0x00400000)
+#define ADC_AnalogWatchdog_AllRegAllInjecEnable    ((uint32_t)0x00C00000)
+#define ADC_AnalogWatchdog_None                    ((uint32_t)0x00000000)
+
+#define IS_ADC_ANALOG_WATCHDOG(WATCHDOG) (((WATCHDOG) == ADC_AnalogWatchdog_SingleRegEnable) || \
+                                          ((WATCHDOG) == ADC_AnalogWatchdog_SingleInjecEnable) || \
+                                          ((WATCHDOG) == ADC_AnalogWatchdog_SingleRegOrInjecEnable) || \
+                                          ((WATCHDOG) == ADC_AnalogWatchdog_AllRegEnable) || \
+                                          ((WATCHDOG) == ADC_AnalogWatchdog_AllInjecEnable) || \
+                                          ((WATCHDOG) == ADC_AnalogWatchdog_AllRegAllInjecEnable) || \
+                                          ((WATCHDOG) == ADC_AnalogWatchdog_None))
+/**
+  * @}
+  */
+
+/** @defgroup ADC_interrupts_definition 
+  * @{
+  */
+
+#define ADC_IT_EOC                                 ((uint16_t)0x0220)
+#define ADC_IT_AWD                                 ((uint16_t)0x0140)
+#define ADC_IT_JEOC                                ((uint16_t)0x0480)
+
+#define IS_ADC_IT(IT) ((((IT) & (uint16_t)0xF81F) == 0x00) && ((IT) != 0x00))
+
+#define IS_ADC_GET_IT(IT) (((IT) == ADC_IT_EOC) || ((IT) == ADC_IT_AWD) || \
+                           ((IT) == ADC_IT_JEOC))
+/**
+  * @}
+  */
+
+/** @defgroup ADC_flags_definition 
+  * @{
+  */
+
+#define ADC_FLAG_AWD                               ((uint8_t)0x01)
+#define ADC_FLAG_EOC                               ((uint8_t)0x02)
+#define ADC_FLAG_JEOC                              ((uint8_t)0x04)
+#define ADC_FLAG_JSTRT                             ((uint8_t)0x08)
+#define ADC_FLAG_STRT                              ((uint8_t)0x10)
+#define IS_ADC_CLEAR_FLAG(FLAG) ((((FLAG) & (uint8_t)0xE0) == 0x00) && ((FLAG) != 0x00))
+#define IS_ADC_GET_FLAG(FLAG) (((FLAG) == ADC_FLAG_AWD) || ((FLAG) == ADC_FLAG_EOC) || \
+                               ((FLAG) == ADC_FLAG_JEOC) || ((FLAG)== ADC_FLAG_JSTRT) || \
+                               ((FLAG) == ADC_FLAG_STRT))
+/**
+  * @}
+  */
+
+/** @defgroup ADC_thresholds 
+  * @{
+  */
+
+#define IS_ADC_THRESHOLD(THRESHOLD) ((THRESHOLD) <= 0xFFF)
+
+/**
+  * @}
+  */
+
+/** @defgroup ADC_injected_offset 
+  * @{
+  */
+
+#define IS_ADC_OFFSET(OFFSET) ((OFFSET) <= 0xFFF)
+
+/**
+  * @}
+  */
+
+/** @defgroup ADC_injected_length 
+  * @{
+  */
+
+#define IS_ADC_INJECTED_LENGTH(LENGTH) (((LENGTH) >= 0x1) && ((LENGTH) <= 0x4))
+
+/**
+  * @}
+  */
+
+/** @defgroup ADC_injected_rank 
+  * @{
+  */
+
+#define IS_ADC_INJECTED_RANK(RANK) (((RANK) >= 0x1) && ((RANK) <= 0x4))
+
+/**
+  * @}
+  */ 
+
+
+/** @defgroup ADC_regular_length 
+  * @{
+  */
+
+#define IS_ADC_REGULAR_LENGTH(LENGTH) (((LENGTH) >= 0x1) && ((LENGTH) <= 0x10))
+/**
+  * @}
+  */
+
+/** @defgroup ADC_regular_rank 
+  * @{
+  */
+
+#define IS_ADC_REGULAR_RANK(RANK) (((RANK) >= 0x1) && ((RANK) <= 0x10))
+
+/**
+  * @}
+  */
+
+/** @defgroup ADC_regular_discontinuous_mode_number 
+  * @{
+  */
+
+#define IS_ADC_REGULAR_DISC_NUMBER(NUMBER) (((NUMBER) >= 0x1) && ((NUMBER) <= 0x8))
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup ADC_Exported_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup ADC_Exported_Functions
+  * @{
+  */
+
+void ADC_DeInit(ADC_TypeDef* ADCx);
+void ADC_Init(ADC_TypeDef* ADCx, ADC_InitTypeDef* ADC_InitStruct);
+void ADC_StructInit(ADC_InitTypeDef* ADC_InitStruct);
+void ADC_Cmd(ADC_TypeDef* ADCx, FunctionalState NewState);
+void ADC_DMACmd(ADC_TypeDef* ADCx, FunctionalState NewState);
+void ADC_ITConfig(ADC_TypeDef* ADCx, uint16_t ADC_IT, FunctionalState NewState);
+void ADC_ResetCalibration(ADC_TypeDef* ADCx);
+FlagStatus ADC_GetResetCalibrationStatus(ADC_TypeDef* ADCx);
+void ADC_StartCalibration(ADC_TypeDef* ADCx);
+FlagStatus ADC_GetCalibrationStatus(ADC_TypeDef* ADCx);
+void ADC_SoftwareStartConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
+FlagStatus ADC_GetSoftwareStartConvStatus(ADC_TypeDef* ADCx);
+void ADC_DiscModeChannelCountConfig(ADC_TypeDef* ADCx, uint8_t Number);
+void ADC_DiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
+void ADC_RegularChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime);
+void ADC_ExternalTrigConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
+uint16_t ADC_GetConversionValue(ADC_TypeDef* ADCx);
+uint32_t ADC_GetDualModeConversionValue(void);
+void ADC_AutoInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
+void ADC_InjectedDiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
+void ADC_ExternalTrigInjectedConvConfig(ADC_TypeDef* ADCx, uint32_t ADC_ExternalTrigInjecConv);
+void ADC_ExternalTrigInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
+void ADC_SoftwareStartInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
+FlagStatus ADC_GetSoftwareStartInjectedConvCmdStatus(ADC_TypeDef* ADCx);
+void ADC_InjectedChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime);
+void ADC_InjectedSequencerLengthConfig(ADC_TypeDef* ADCx, uint8_t Length);
+void ADC_SetInjectedOffset(ADC_TypeDef* ADCx, uint8_t ADC_InjectedChannel, uint16_t Offset);
+uint16_t ADC_GetInjectedConversionValue(ADC_TypeDef* ADCx, uint8_t ADC_InjectedChannel);
+void ADC_AnalogWatchdogCmd(ADC_TypeDef* ADCx, uint32_t ADC_AnalogWatchdog);
+void ADC_AnalogWatchdogThresholdsConfig(ADC_TypeDef* ADCx, uint16_t HighThreshold, uint16_t LowThreshold);
+void ADC_AnalogWatchdogSingleChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel);
+void ADC_TempSensorVrefintCmd(FunctionalState NewState);
+FlagStatus ADC_GetFlagStatus(ADC_TypeDef* ADCx, uint8_t ADC_FLAG);
+void ADC_ClearFlag(ADC_TypeDef* ADCx, uint8_t ADC_FLAG);
+ITStatus ADC_GetITStatus(ADC_TypeDef* ADCx, uint16_t ADC_IT);
+void ADC_ClearITPendingBit(ADC_TypeDef* ADCx, uint16_t ADC_IT);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__STM32F10x_ADC_H */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/STM32_4路称重_Git提交精简工程/src/STM32F10x_FWLib/inc/stm32f10x_bkp.h b/STM32_4路称重_Git提交精简工程/src/STM32F10x_FWLib/inc/stm32f10x_bkp.h
new file mode 100755
index 0000000..b620753
--- /dev/null
+++ b/STM32_4路称重_Git提交精简工程/src/STM32F10x_FWLib/inc/stm32f10x_bkp.h
@@ -0,0 +1,195 @@
+/**
+  ******************************************************************************
+  * @file    stm32f10x_bkp.h
+  * @author  MCD Application Team
+  * @version V3.5.0
+  * @date    11-March-2011
+  * @brief   This file contains all the functions prototypes for the BKP firmware 
+  *          library.
+  ******************************************************************************
+  * @attention
+  *
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+  *
+  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F10x_BKP_H
+#define __STM32F10x_BKP_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x.h"
+
+/** @addtogroup STM32F10x_StdPeriph_Driver
+  * @{
+  */
+
+/** @addtogroup BKP
+  * @{
+  */
+
+/** @defgroup BKP_Exported_Types
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup BKP_Exported_Constants
+  * @{
+  */
+
+/** @defgroup Tamper_Pin_active_level 
+  * @{
+  */
+
+#define BKP_TamperPinLevel_High           ((uint16_t)0x0000)
+#define BKP_TamperPinLevel_Low            ((uint16_t)0x0001)
+#define IS_BKP_TAMPER_PIN_LEVEL(LEVEL) (((LEVEL) == BKP_TamperPinLevel_High) || \
+                                        ((LEVEL) == BKP_TamperPinLevel_Low))
+/**
+  * @}
+  */
+
+/** @defgroup RTC_output_source_to_output_on_the_Tamper_pin 
+  * @{
+  */
+
+#define BKP_RTCOutputSource_None          ((uint16_t)0x0000)
+#define BKP_RTCOutputSource_CalibClock    ((uint16_t)0x0080)
+#define BKP_RTCOutputSource_Alarm         ((uint16_t)0x0100)
+#define BKP_RTCOutputSource_Second        ((uint16_t)0x0300)
+#define IS_BKP_RTC_OUTPUT_SOURCE(SOURCE) (((SOURCE) == BKP_RTCOutputSource_None) || \
+                                          ((SOURCE) == BKP_RTCOutputSource_CalibClock) || \
+                                          ((SOURCE) == BKP_RTCOutputSource_Alarm) || \
+                                          ((SOURCE) == BKP_RTCOutputSource_Second))
+/**
+  * @}
+  */
+
+/** @defgroup Data_Backup_Register 
+  * @{
+  */
+
+#define BKP_DR1                           ((uint16_t)0x0004)
+#define BKP_DR2                           ((uint16_t)0x0008)
+#define BKP_DR3                           ((uint16_t)0x000C)
+#define BKP_DR4                           ((uint16_t)0x0010)
+#define BKP_DR5                           ((uint16_t)0x0014)
+#define BKP_DR6                           ((uint16_t)0x0018)
+#define BKP_DR7                           ((uint16_t)0x001C)
+#define BKP_DR8                           ((uint16_t)0x0020)
+#define BKP_DR9                           ((uint16_t)0x0024)
+#define BKP_DR10                          ((uint16_t)0x0028)
+#define BKP_DR11                          ((uint16_t)0x0040)
+#define BKP_DR12                          ((uint16_t)0x0044)
+#define BKP_DR13                          ((uint16_t)0x0048)
+#define BKP_DR14                          ((uint16_t)0x004C)
+#define BKP_DR15                          ((uint16_t)0x0050)
+#define BKP_DR16                          ((uint16_t)0x0054)
+#define BKP_DR17                          ((uint16_t)0x0058)
+#define BKP_DR18                          ((uint16_t)0x005C)
+#define BKP_DR19                          ((uint16_t)0x0060)
+#define BKP_DR20                          ((uint16_t)0x0064)
+#define BKP_DR21                          ((uint16_t)0x0068)
+#define BKP_DR22                          ((uint16_t)0x006C)
+#define BKP_DR23                          ((uint16_t)0x0070)
+#define BKP_DR24                          ((uint16_t)0x0074)
+#define BKP_DR25                          ((uint16_t)0x0078)
+#define BKP_DR26                          ((uint16_t)0x007C)
+#define BKP_DR27                          ((uint16_t)0x0080)
+#define BKP_DR28                          ((uint16_t)0x0084)
+#define BKP_DR29                          ((uint16_t)0x0088)
+#define BKP_DR30                          ((uint16_t)0x008C)
+#define BKP_DR31                          ((uint16_t)0x0090)
+#define BKP_DR32                          ((uint16_t)0x0094)
+#define BKP_DR33                          ((uint16_t)0x0098)
+#define BKP_DR34                          ((uint16_t)0x009C)
+#define BKP_DR35                          ((uint16_t)0x00A0)
+#define BKP_DR36                          ((uint16_t)0x00A4)
+#define BKP_DR37                          ((uint16_t)0x00A8)
+#define BKP_DR38                          ((uint16_t)0x00AC)
+#define BKP_DR39                          ((uint16_t)0x00B0)
+#define BKP_DR40                          ((uint16_t)0x00B4)
+#define BKP_DR41                          ((uint16_t)0x00B8)
+#define BKP_DR42                          ((uint16_t)0x00BC)
+
+#define IS_BKP_DR(DR) (((DR) == BKP_DR1)  || ((DR) == BKP_DR2)  || ((DR) == BKP_DR3)  || \
+                       ((DR) == BKP_DR4)  || ((DR) == BKP_DR5)  || ((DR) == BKP_DR6)  || \
+                       ((DR) == BKP_DR7)  || ((DR) == BKP_DR8)  || ((DR) == BKP_DR9)  || \
+                       ((DR) == BKP_DR10) || ((DR) == BKP_DR11) || ((DR) == BKP_DR12) || \
+                       ((DR) == BKP_DR13) || ((DR) == BKP_DR14) || ((DR) == BKP_DR15) || \
+                       ((DR) == BKP_DR16) || ((DR) == BKP_DR17) || ((DR) == BKP_DR18) || \
+                       ((DR) == BKP_DR19) || ((DR) == BKP_DR20) || ((DR) == BKP_DR21) || \
+                       ((DR) == BKP_DR22) || ((DR) == BKP_DR23) || ((DR) == BKP_DR24) || \
+                       ((DR) == BKP_DR25) || ((DR) == BKP_DR26) || ((DR) == BKP_DR27) || \
+                       ((DR) == BKP_DR28) || ((DR) == BKP_DR29) || ((DR) == BKP_DR30) || \
+                       ((DR) == BKP_DR31) || ((DR) == BKP_DR32) || ((DR) == BKP_DR33) || \
+                       ((DR) == BKP_DR34) || ((DR) == BKP_DR35) || ((DR) == BKP_DR36) || \
+                       ((DR) == BKP_DR37) || ((DR) == BKP_DR38) || ((DR) == BKP_DR39) || \
+                       ((DR) == BKP_DR40) || ((DR) == BKP_DR41) || ((DR) == BKP_DR42))
+
+#define IS_BKP_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x7F)
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup BKP_Exported_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup BKP_Exported_Functions
+  * @{
+  */
+
+void BKP_DeInit(void);
+void BKP_TamperPinLevelConfig(uint16_t BKP_TamperPinLevel);
+void BKP_TamperPinCmd(FunctionalState NewState);
+void BKP_ITConfig(FunctionalState NewState);
+void BKP_RTCOutputConfig(uint16_t BKP_RTCOutputSource);
+void BKP_SetRTCCalibrationValue(uint8_t CalibrationValue);
+void BKP_WriteBackupRegister(uint16_t BKP_DR, uint16_t Data);
+uint16_t BKP_ReadBackupRegister(uint16_t BKP_DR);
+FlagStatus BKP_GetFlagStatus(void);
+void BKP_ClearFlag(void);
+ITStatus BKP_GetITStatus(void);
+void BKP_ClearITPendingBit(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F10x_BKP_H */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/STM32_4路称重_Git提交精简工程/src/STM32F10x_FWLib/inc/stm32f10x_can.h b/STM32_4路称重_Git提交精简工程/src/STM32F10x_FWLib/inc/stm32f10x_can.h
new file mode 100755
index 0000000..648f747
--- /dev/null
+++ b/STM32_4路称重_Git提交精简工程/src/STM32F10x_FWLib/inc/stm32f10x_can.h
@@ -0,0 +1,697 @@
+/**
+  ******************************************************************************
+  * @file    stm32f10x_can.h
+  * @author  MCD Application Team
+  * @version V3.5.0
+  * @date    11-March-2011
+  * @brief   This file contains all the functions prototypes for the CAN firmware 
+  *          library.
+  ******************************************************************************
+  * @attention
+  *
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+  *
+  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F10x_CAN_H
+#define __STM32F10x_CAN_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x.h"
+
+/** @addtogroup STM32F10x_StdPeriph_Driver
+  * @{
+  */
+
+/** @addtogroup CAN
+  * @{
+  */
+
+/** @defgroup CAN_Exported_Types
+  * @{
+  */
+
+#define IS_CAN_ALL_PERIPH(PERIPH) (((PERIPH) == CAN1) || \
+                                   ((PERIPH) == CAN2))
+
+/** 
+  * @brief  CAN init structure definition
+  */
+
+typedef struct
+{
+  uint16_t CAN_Prescaler;   /*!< Specifies the length of a time quantum. 
+                                 It ranges from 1 to 1024. */
+  
+  uint8_t CAN_Mode;         /*!< Specifies the CAN operating mode.
+                                 This parameter can be a value of 
+                                @ref CAN_operating_mode */
+
+  uint8_t CAN_SJW;          /*!< Specifies the maximum number of time quanta 
+                                 the CAN hardware is allowed to lengthen or 
+                                 shorten a bit to perform resynchronization.
+                                 This parameter can be a value of 
+                                 @ref CAN_synchronisation_jump_width */
+
+  uint8_t CAN_BS1;          /*!< Specifies the number of time quanta in Bit 
+                                 Segment 1. This parameter can be a value of 
+                                 @ref CAN_time_quantum_in_bit_segment_1 */
+
+  uint8_t CAN_BS2;          /*!< Specifies the number of time quanta in Bit 
+                                 Segment 2.
+                                 This parameter can be a value of 
+                                 @ref CAN_time_quantum_in_bit_segment_2 */
+  
+  FunctionalState CAN_TTCM; /*!< Enable or disable the time triggered 
+                                 communication mode. This parameter can be set 
+                                 either to ENABLE or DISABLE. */
+  
+  FunctionalState CAN_ABOM;  /*!< Enable or disable the automatic bus-off 
+                                  management. This parameter can be set either 
+                                  to ENABLE or DISABLE. */
+
+  FunctionalState CAN_AWUM;  /*!< Enable or disable the automatic wake-up mode. 
+                                  This parameter can be set either to ENABLE or 
+                                  DISABLE. */
+
+  FunctionalState CAN_NART;  /*!< Enable or disable the no-automatic 
+                                  retransmission mode. This parameter can be 
+                                  set either to ENABLE or DISABLE. */
+
+  FunctionalState CAN_RFLM;  /*!< Enable or disable the Receive FIFO Locked mode.
+                                  This parameter can be set either to ENABLE 
+                                  or DISABLE. */
+
+  FunctionalState CAN_TXFP;  /*!< Enable or disable the transmit FIFO priority.
+                                  This parameter can be set either to ENABLE 
+                                  or DISABLE. */
+} CAN_InitTypeDef;
+
+/** 
+  * @brief  CAN filter init structure definition
+  */
+
+typedef struct
+{
+  uint16_t CAN_FilterIdHigh;         /*!< Specifies the filter identification number (MSBs for a 32-bit
+                                              configuration, first one for a 16-bit configuration).
+                                              This parameter can be a value between 0x0000 and 0xFFFF */
+
+  uint16_t CAN_FilterIdLow;          /*!< Specifies the filter identification number (LSBs for a 32-bit
+                                              configuration, second one for a 16-bit configuration).
+                                              This parameter can be a value between 0x0000 and 0xFFFF */
+
+  uint16_t CAN_FilterMaskIdHigh;     /*!< Specifies the filter mask number or identification number,
+                                              according to the mode (MSBs for a 32-bit configuration,
+                                              first one for a 16-bit configuration).
+                                              This parameter can be a value between 0x0000 and 0xFFFF */
+
+  uint16_t CAN_FilterMaskIdLow;      /*!< Specifies the filter mask number or identification number,
+                                              according to the mode (LSBs for a 32-bit configuration,
+                                              second one for a 16-bit configuration).
+                                              This parameter can be a value between 0x0000 and 0xFFFF */
+
+  uint16_t CAN_FilterFIFOAssignment; /*!< Specifies the FIFO (0 or 1) which will be assigned to the filter.
+                                              This parameter can be a value of @ref CAN_filter_FIFO */
+  
+  uint8_t CAN_FilterNumber;          /*!< Specifies the filter which will be initialized. It ranges from 0 to 13. */
+
+  uint8_t CAN_FilterMode;            /*!< Specifies the filter mode to be initialized.
+                                              This parameter can be a value of @ref CAN_filter_mode */
+
+  uint8_t CAN_FilterScale;           /*!< Specifies the filter scale.
+                                              This parameter can be a value of @ref CAN_filter_scale */
+
+  FunctionalState CAN_FilterActivation; /*!< Enable or disable the filter.
+                                              This parameter can be set either to ENABLE or DISABLE. */
+} CAN_FilterInitTypeDef;
+
+/** 
+  * @brief  CAN Tx message structure definition  
+  */
+
+typedef struct
+{
+  uint32_t StdId;  /*!< Specifies the standard identifier.
+                        This parameter can be a value between 0 to 0x7FF. */
+
+  uint32_t ExtId;  /*!< Specifies the extended identifier.
+                        This parameter can be a value between 0 to 0x1FFFFFFF. */
+
+  uint8_t IDE;     /*!< Specifies the type of identifier for the message that 
+                        will be transmitted. This parameter can be a value 
+                        of @ref CAN_identifier_type */
+
+  uint8_t RTR;     /*!< Specifies the type of frame for the message that will 
+                        be transmitted. This parameter can be a value of 
+                        @ref CAN_remote_transmission_request */
+
+  uint8_t DLC;     /*!< Specifies the length of the frame that will be 
+                        transmitted. This parameter can be a value between 
+                        0 to 8 */
+
+  uint8_t Data[8]; /*!< Contains the data to be transmitted. It ranges from 0 
+                        to 0xFF. */
+} CanTxMsg;
+
+/** 
+  * @brief  CAN Rx message structure definition  
+  */
+
+typedef struct
+{
+  uint32_t StdId;  /*!< Specifies the standard identifier.
+                        This parameter can be a value between 0 to 0x7FF. */
+
+  uint32_t ExtId;  /*!< Specifies the extended identifier.
+                        This parameter can be a value between 0 to 0x1FFFFFFF. */
+
+  uint8_t IDE;     /*!< Specifies the type of identifier for the message that 
+                        will be received. This parameter can be a value of 
+                        @ref CAN_identifier_type */
+
+  uint8_t RTR;     /*!< Specifies the type of frame for the received message.
+                        This parameter can be a value of 
+                        @ref CAN_remote_transmission_request */
+
+  uint8_t DLC;     /*!< Specifies the length of the frame that will be received.
+                        This parameter can be a value between 0 to 8 */
+
+  uint8_t Data[8]; /*!< Contains the data to be received. It ranges from 0 to 
+                        0xFF. */
+
+  uint8_t FMI;     /*!< Specifies the index of the filter the message stored in 
+                        the mailbox passes through. This parameter can be a 
+                        value between 0 to 0xFF */
+} CanRxMsg;
+
+/**
+  * @}
+  */
+
+/** @defgroup CAN_Exported_Constants
+  * @{
+  */
+
+/** @defgroup CAN_sleep_constants 
+  * @{
+  */
+
+#define CAN_InitStatus_Failed              ((uint8_t)0x00) /*!< CAN initialization failed */
+#define CAN_InitStatus_Success             ((uint8_t)0x01) /*!< CAN initialization OK */
+
+/**
+  * @}
+  */
+
+/** @defgroup CAN_Mode 
+  * @{
+  */
+
+#define CAN_Mode_Normal             ((uint8_t)0x00)  /*!< normal mode */
+#define CAN_Mode_LoopBack           ((uint8_t)0x01)  /*!< loopback mode */
+#define CAN_Mode_Silent             ((uint8_t)0x02)  /*!< silent mode */
+#define CAN_Mode_Silent_LoopBack    ((uint8_t)0x03)  /*!< loopback combined with silent mode */
+
+#define IS_CAN_MODE(MODE) (((MODE) == CAN_Mode_Normal) || \
+                           ((MODE) == CAN_Mode_LoopBack)|| \
+                           ((MODE) == CAN_Mode_Silent) || \
+                           ((MODE) == CAN_Mode_Silent_LoopBack))
+/**
+  * @}
+  */
+
+
+/**
+  * @defgroup CAN_Operating_Mode 
+  * @{
+  */  
+#define CAN_OperatingMode_Initialization  ((uint8_t)0x00) /*!< Initialization mode */
+#define CAN_OperatingMode_Normal          ((uint8_t)0x01) /*!< Normal mode */
+#define CAN_OperatingMode_Sleep           ((uint8_t)0x02) /*!< sleep mode */
+
+
+#define IS_CAN_OPERATING_MODE(MODE) (((MODE) == CAN_OperatingMode_Initialization) ||\
+                                    ((MODE) == CAN_OperatingMode_Normal)|| \
+																		((MODE) == CAN_OperatingMode_Sleep))
+/**
+  * @}
+  */
+  
+/**
+  * @defgroup CAN_Mode_Status
+  * @{
+  */  
+
+#define CAN_ModeStatus_Failed    ((uint8_t)0x00)                /*!< CAN entering the specific mode failed */
+#define CAN_ModeStatus_Success   ((uint8_t)!CAN_ModeStatus_Failed)   /*!< CAN entering the specific mode Succeed */
+
+
+/**
+  * @}
+  */
+
+/** @defgroup CAN_synchronisation_jump_width 
+  * @{
+  */
+
+#define CAN_SJW_1tq                 ((uint8_t)0x00)  /*!< 1 time quantum */
+#define CAN_SJW_2tq                 ((uint8_t)0x01)  /*!< 2 time quantum */
+#define CAN_SJW_3tq                 ((uint8_t)0x02)  /*!< 3 time quantum */
+#define CAN_SJW_4tq                 ((uint8_t)0x03)  /*!< 4 time quantum */
+
+#define IS_CAN_SJW(SJW) (((SJW) == CAN_SJW_1tq) || ((SJW) == CAN_SJW_2tq)|| \
+                         ((SJW) == CAN_SJW_3tq) || ((SJW) == CAN_SJW_4tq))
+/**
+  * @}
+  */
+
+/** @defgroup CAN_time_quantum_in_bit_segment_1 
+  * @{
+  */
+
+#define CAN_BS1_1tq                 ((uint8_t)0x00)  /*!< 1 time quantum */
+#define CAN_BS1_2tq                 ((uint8_t)0x01)  /*!< 2 time quantum */
+#define CAN_BS1_3tq                 ((uint8_t)0x02)  /*!< 3 time quantum */
+#define CAN_BS1_4tq                 ((uint8_t)0x03)  /*!< 4 time quantum */
+#define CAN_BS1_5tq                 ((uint8_t)0x04)  /*!< 5 time quantum */
+#define CAN_BS1_6tq                 ((uint8_t)0x05)  /*!< 6 time quantum */
+#define CAN_BS1_7tq                 ((uint8_t)0x06)  /*!< 7 time quantum */
+#define CAN_BS1_8tq                 ((uint8_t)0x07)  /*!< 8 time quantum */
+#define CAN_BS1_9tq                 ((uint8_t)0x08)  /*!< 9 time quantum */
+#define CAN_BS1_10tq                ((uint8_t)0x09)  /*!< 10 time quantum */
+#define CAN_BS1_11tq                ((uint8_t)0x0A)  /*!< 11 time quantum */
+#define CAN_BS1_12tq                ((uint8_t)0x0B)  /*!< 12 time quantum */
+#define CAN_BS1_13tq                ((uint8_t)0x0C)  /*!< 13 time quantum */
+#define CAN_BS1_14tq                ((uint8_t)0x0D)  /*!< 14 time quantum */
+#define CAN_BS1_15tq                ((uint8_t)0x0E)  /*!< 15 time quantum */
+#define CAN_BS1_16tq                ((uint8_t)0x0F)  /*!< 16 time quantum */
+
+#define IS_CAN_BS1(BS1) ((BS1) <= CAN_BS1_16tq)
+/**
+  * @}
+  */
+
+/** @defgroup CAN_time_quantum_in_bit_segment_2 
+  * @{
+  */
+
+#define CAN_BS2_1tq                 ((uint8_t)0x00)  /*!< 1 time quantum */
+#define CAN_BS2_2tq                 ((uint8_t)0x01)  /*!< 2 time quantum */
+#define CAN_BS2_3tq                 ((uint8_t)0x02)  /*!< 3 time quantum */
+#define CAN_BS2_4tq                 ((uint8_t)0x03)  /*!< 4 time quantum */
+#define CAN_BS2_5tq                 ((uint8_t)0x04)  /*!< 5 time quantum */
+#define CAN_BS2_6tq                 ((uint8_t)0x05)  /*!< 6 time quantum */
+#define CAN_BS2_7tq                 ((uint8_t)0x06)  /*!< 7 time quantum */
+#define CAN_BS2_8tq                 ((uint8_t)0x07)  /*!< 8 time quantum */
+
+#define IS_CAN_BS2(BS2) ((BS2) <= CAN_BS2_8tq)
+
+/**
+  * @}
+  */
+
+/** @defgroup CAN_clock_prescaler 
+  * @{
+  */
+
+#define IS_CAN_PRESCALER(PRESCALER) (((PRESCALER) >= 1) && ((PRESCALER) <= 1024))
+
+/**
+  * @}
+  */
+
+/** @defgroup CAN_filter_number 
+  * @{
+  */
+#ifndef STM32F10X_CL
+  #define IS_CAN_FILTER_NUMBER(NUMBER) ((NUMBER) <= 13)
+#else
+  #define IS_CAN_FILTER_NUMBER(NUMBER) ((NUMBER) <= 27)
+#endif /* STM32F10X_CL */ 
+/**
+  * @}
+  */
+
+/** @defgroup CAN_filter_mode 
+  * @{
+  */
+
+#define CAN_FilterMode_IdMask       ((uint8_t)0x00)  /*!< identifier/mask mode */
+#define CAN_FilterMode_IdList       ((uint8_t)0x01)  /*!< identifier list mode */
+
+#define IS_CAN_FILTER_MODE(MODE) (((MODE) == CAN_FilterMode_IdMask) || \
+                                  ((MODE) == CAN_FilterMode_IdList))
+/**
+  * @}
+  */
+
+/** @defgroup CAN_filter_scale 
+  * @{
+  */
+
+#define CAN_FilterScale_16bit       ((uint8_t)0x00) /*!< Two 16-bit filters */
+#define CAN_FilterScale_32bit       ((uint8_t)0x01) /*!< One 32-bit filter */
+
+#define IS_CAN_FILTER_SCALE(SCALE) (((SCALE) == CAN_FilterScale_16bit) || \
+                                    ((SCALE) == CAN_FilterScale_32bit))
+
+/**
+  * @}
+  */
+
+/** @defgroup CAN_filter_FIFO
+  * @{
+  */
+
+#define CAN_Filter_FIFO0             ((uint8_t)0x00)  /*!< Filter FIFO 0 assignment for filter x */
+#define CAN_Filter_FIFO1             ((uint8_t)0x01)  /*!< Filter FIFO 1 assignment for filter x */
+#define IS_CAN_FILTER_FIFO(FIFO) (((FIFO) == CAN_FilterFIFO0) || \
+                                  ((FIFO) == CAN_FilterFIFO1))
+/**
+  * @}
+  */
+
+/** @defgroup Start_bank_filter_for_slave_CAN 
+  * @{
+  */
+#define IS_CAN_BANKNUMBER(BANKNUMBER) (((BANKNUMBER) >= 1) && ((BANKNUMBER) <= 27))
+/**
+  * @}
+  */
+
+/** @defgroup CAN_Tx 
+  * @{
+  */
+
+#define IS_CAN_TRANSMITMAILBOX(TRANSMITMAILBOX) ((TRANSMITMAILBOX) <= ((uint8_t)0x02))
+#define IS_CAN_STDID(STDID)   ((STDID) <= ((uint32_t)0x7FF))
+#define IS_CAN_EXTID(EXTID)   ((EXTID) <= ((uint32_t)0x1FFFFFFF))
+#define IS_CAN_DLC(DLC)       ((DLC) <= ((uint8_t)0x08))
+
+/**
+  * @}
+  */
+
+/** @defgroup CAN_identifier_type 
+  * @{
+  */
+
+#define CAN_Id_Standard             ((uint32_t)0x00000000)  /*!< Standard Id */
+#define CAN_Id_Extended             ((uint32_t)0x00000004)  /*!< Extended Id */
+#define IS_CAN_IDTYPE(IDTYPE) (((IDTYPE) == CAN_Id_Standard) || \
+                               ((IDTYPE) == CAN_Id_Extended))
+/**
+  * @}
+  */
+
+/** @defgroup CAN_remote_transmission_request 
+  * @{
+  */
+
+#define CAN_RTR_Data                ((uint32_t)0x00000000)  /*!< Data frame */
+#define CAN_RTR_Remote              ((uint32_t)0x00000002)  /*!< Remote frame */
+#define IS_CAN_RTR(RTR) (((RTR) == CAN_RTR_Data) || ((RTR) == CAN_RTR_Remote))
+
+/**
+  * @}
+  */
+
+/** @defgroup CAN_transmit_constants 
+  * @{
+  */
+
+#define CAN_TxStatus_Failed         ((uint8_t)0x00)/*!< CAN transmission failed */
+#define CAN_TxStatus_Ok             ((uint8_t)0x01) /*!< CAN transmission succeeded */
+#define CAN_TxStatus_Pending        ((uint8_t)0x02) /*!< CAN transmission pending */
+#define CAN_TxStatus_NoMailBox      ((uint8_t)0x04) /*!< CAN cell did not provide an empty mailbox */
+
+/**
+  * @}
+  */
+
+/** @defgroup CAN_receive_FIFO_number_constants 
+  * @{
+  */
+
+#define CAN_FIFO0                 ((uint8_t)0x00) /*!< CAN FIFO 0 used to receive */
+#define CAN_FIFO1                 ((uint8_t)0x01) /*!< CAN FIFO 1 used to receive */
+
+#define IS_CAN_FIFO(FIFO) (((FIFO) == CAN_FIFO0) || ((FIFO) == CAN_FIFO1))
+
+/**
+  * @}
+  */
+
+/** @defgroup CAN_sleep_constants 
+  * @{
+  */
+
+#define CAN_Sleep_Failed     ((uint8_t)0x00) /*!< CAN did not enter the sleep mode */
+#define CAN_Sleep_Ok         ((uint8_t)0x01) /*!< CAN entered the sleep mode */
+
+/**
+  * @}
+  */
+
+/** @defgroup CAN_wake_up_constants 
+  * @{
+  */
+
+#define CAN_WakeUp_Failed        ((uint8_t)0x00) /*!< CAN did not leave the sleep mode */
+#define CAN_WakeUp_Ok            ((uint8_t)0x01) /*!< CAN leaved the sleep mode */
+
+/**
+  * @}
+  */
+
+/**
+  * @defgroup   CAN_Error_Code_constants
+  * @{
+  */  
+                                                                
+#define CAN_ErrorCode_NoErr           ((uint8_t)0x00) /*!< No Error */ 
+#define	CAN_ErrorCode_StuffErr        ((uint8_t)0x10) /*!< Stuff Error */ 
+#define	CAN_ErrorCode_FormErr         ((uint8_t)0x20) /*!< Form Error */ 
+#define	CAN_ErrorCode_ACKErr          ((uint8_t)0x30) /*!< Acknowledgment Error */ 
+#define	CAN_ErrorCode_BitRecessiveErr ((uint8_t)0x40) /*!< Bit Recessive Error */ 
+#define	CAN_ErrorCode_BitDominantErr  ((uint8_t)0x50) /*!< Bit Dominant Error */ 
+#define	CAN_ErrorCode_CRCErr          ((uint8_t)0x60) /*!< CRC Error  */ 
+#define	CAN_ErrorCode_SoftwareSetErr  ((uint8_t)0x70) /*!< Software Set Error */ 
+
+
+/**
+  * @}
+  */
+
+/** @defgroup CAN_flags 
+  * @{
+  */
+/* If the flag is 0x3XXXXXXX, it means that it can be used with CAN_GetFlagStatus()
+   and CAN_ClearFlag() functions. */
+/* If the flag is 0x1XXXXXXX, it means that it can only be used with CAN_GetFlagStatus() function.  */
+
+/* Transmit Flags */
+#define CAN_FLAG_RQCP0             ((uint32_t)0x38000001) /*!< Request MailBox0 Flag */
+#define CAN_FLAG_RQCP1             ((uint32_t)0x38000100) /*!< Request MailBox1 Flag */
+#define CAN_FLAG_RQCP2             ((uint32_t)0x38010000) /*!< Request MailBox2 Flag */
+
+/* Receive Flags */
+#define CAN_FLAG_FMP0              ((uint32_t)0x12000003) /*!< FIFO 0 Message Pending Flag */
+#define CAN_FLAG_FF0               ((uint32_t)0x32000008) /*!< FIFO 0 Full Flag            */
+#define CAN_FLAG_FOV0              ((uint32_t)0x32000010) /*!< FIFO 0 Overrun Flag         */
+#define CAN_FLAG_FMP1              ((uint32_t)0x14000003) /*!< FIFO 1 Message Pending Flag */
+#define CAN_FLAG_FF1               ((uint32_t)0x34000008) /*!< FIFO 1 Full Flag            */
+#define CAN_FLAG_FOV1              ((uint32_t)0x34000010) /*!< FIFO 1 Overrun Flag         */
+
+/* Operating Mode Flags */
+#define CAN_FLAG_WKU               ((uint32_t)0x31000008) /*!< Wake up Flag */
+#define CAN_FLAG_SLAK              ((uint32_t)0x31000012) /*!< Sleep acknowledge Flag */
+/* Note: When SLAK intterupt is disabled (SLKIE=0), no polling on SLAKI is possible. 
+         In this case the SLAK bit can be polled.*/
+
+/* Error Flags */
+#define CAN_FLAG_EWG               ((uint32_t)0x10F00001) /*!< Error Warning Flag   */
+#define CAN_FLAG_EPV               ((uint32_t)0x10F00002) /*!< Error Passive Flag   */
+#define CAN_FLAG_BOF               ((uint32_t)0x10F00004) /*!< Bus-Off Flag         */
+#define CAN_FLAG_LEC               ((uint32_t)0x30F00070) /*!< Last error code Flag */
+
+#define IS_CAN_GET_FLAG(FLAG) (((FLAG) == CAN_FLAG_LEC)  || ((FLAG) == CAN_FLAG_BOF)   || \
+                               ((FLAG) == CAN_FLAG_EPV)  || ((FLAG) == CAN_FLAG_EWG)   || \
+                               ((FLAG) == CAN_FLAG_WKU)  || ((FLAG) == CAN_FLAG_FOV0)  || \
+                               ((FLAG) == CAN_FLAG_FF0)  || ((FLAG) == CAN_FLAG_FMP0)  || \
+                               ((FLAG) == CAN_FLAG_FOV1) || ((FLAG) == CAN_FLAG_FF1)   || \
+                               ((FLAG) == CAN_FLAG_FMP1) || ((FLAG) == CAN_FLAG_RQCP2) || \
+                               ((FLAG) == CAN_FLAG_RQCP1)|| ((FLAG) == CAN_FLAG_RQCP0) || \
+                               ((FLAG) == CAN_FLAG_SLAK ))
+
+#define IS_CAN_CLEAR_FLAG(FLAG)(((FLAG) == CAN_FLAG_LEC) || ((FLAG) == CAN_FLAG_RQCP2) || \
+                                ((FLAG) == CAN_FLAG_RQCP1)  || ((FLAG) == CAN_FLAG_RQCP0) || \
+                                ((FLAG) == CAN_FLAG_FF0)  || ((FLAG) == CAN_FLAG_FOV0) ||\
+                                ((FLAG) == CAN_FLAG_FF1) || ((FLAG) == CAN_FLAG_FOV1) || \
+                                ((FLAG) == CAN_FLAG_WKU) || ((FLAG) == CAN_FLAG_SLAK))
+/**
+  * @}
+  */
+
+  
+/** @defgroup CAN_interrupts 
+  * @{
+  */
+
+
+  
+#define CAN_IT_TME                  ((uint32_t)0x00000001) /*!< Transmit mailbox empty Interrupt*/
+
+/* Receive Interrupts */
+#define CAN_IT_FMP0                 ((uint32_t)0x00000002) /*!< FIFO 0 message pending Interrupt*/
+#define CAN_IT_FF0                  ((uint32_t)0x00000004) /*!< FIFO 0 full Interrupt*/
+#define CAN_IT_FOV0                 ((uint32_t)0x00000008) /*!< FIFO 0 overrun Interrupt*/
+#define CAN_IT_FMP1                 ((uint32_t)0x00000010) /*!< FIFO 1 message pending Interrupt*/
+#define CAN_IT_FF1                  ((uint32_t)0x00000020) /*!< FIFO 1 full Interrupt*/
+#define CAN_IT_FOV1                 ((uint32_t)0x00000040) /*!< FIFO 1 overrun Interrupt*/
+
+/* Operating Mode Interrupts */
+#define CAN_IT_WKU                  ((uint32_t)0x00010000) /*!< Wake-up Interrupt*/
+#define CAN_IT_SLK                  ((uint32_t)0x00020000) /*!< Sleep acknowledge Interrupt*/
+
+/* Error Interrupts */
+#define CAN_IT_EWG                  ((uint32_t)0x00000100) /*!< Error warning Interrupt*/
+#define CAN_IT_EPV                  ((uint32_t)0x00000200) /*!< Error passive Interrupt*/
+#define CAN_IT_BOF                  ((uint32_t)0x00000400) /*!< Bus-off Interrupt*/
+#define CAN_IT_LEC                  ((uint32_t)0x00000800) /*!< Last error code Interrupt*/
+#define CAN_IT_ERR                  ((uint32_t)0x00008000) /*!< Error Interrupt*/
+
+/* Flags named as Interrupts : kept only for FW compatibility */
+#define CAN_IT_RQCP0   CAN_IT_TME
+#define CAN_IT_RQCP1   CAN_IT_TME
+#define CAN_IT_RQCP2   CAN_IT_TME
+
+
+#define IS_CAN_IT(IT)        (((IT) == CAN_IT_TME) || ((IT) == CAN_IT_FMP0)  ||\
+                             ((IT) == CAN_IT_FF0)  || ((IT) == CAN_IT_FOV0)  ||\
+                             ((IT) == CAN_IT_FMP1) || ((IT) == CAN_IT_FF1)   ||\
+                             ((IT) == CAN_IT_FOV1) || ((IT) == CAN_IT_EWG)   ||\
+                             ((IT) == CAN_IT_EPV)  || ((IT) == CAN_IT_BOF)   ||\
+                             ((IT) == CAN_IT_LEC)  || ((IT) == CAN_IT_ERR)   ||\
+                             ((IT) == CAN_IT_WKU)  || ((IT) == CAN_IT_SLK))
+
+#define IS_CAN_CLEAR_IT(IT) (((IT) == CAN_IT_TME) || ((IT) == CAN_IT_FF0)    ||\
+                             ((IT) == CAN_IT_FOV0)|| ((IT) == CAN_IT_FF1)    ||\
+                             ((IT) == CAN_IT_FOV1)|| ((IT) == CAN_IT_EWG)    ||\
+                             ((IT) == CAN_IT_EPV) || ((IT) == CAN_IT_BOF)    ||\
+                             ((IT) == CAN_IT_LEC) || ((IT) == CAN_IT_ERR)    ||\
+                             ((IT) == CAN_IT_WKU) || ((IT) == CAN_IT_SLK))
+
+/**
+  * @}
+  */
+
+/** @defgroup CAN_Legacy 
+  * @{
+  */
+#define CANINITFAILED               CAN_InitStatus_Failed
+#define CANINITOK                   CAN_InitStatus_Success
+#define CAN_FilterFIFO0             CAN_Filter_FIFO0
+#define CAN_FilterFIFO1             CAN_Filter_FIFO1
+#define CAN_ID_STD                  CAN_Id_Standard           
+#define CAN_ID_EXT                  CAN_Id_Extended
+#define CAN_RTR_DATA                CAN_RTR_Data         
+#define CAN_RTR_REMOTE              CAN_RTR_Remote
+#define CANTXFAILE                  CAN_TxStatus_Failed
+#define CANTXOK                     CAN_TxStatus_Ok
+#define CANTXPENDING                CAN_TxStatus_Pending
+#define CAN_NO_MB                   CAN_TxStatus_NoMailBox
+#define CANSLEEPFAILED              CAN_Sleep_Failed
+#define CANSLEEPOK                  CAN_Sleep_Ok
+#define CANWAKEUPFAILED             CAN_WakeUp_Failed        
+#define CANWAKEUPOK                 CAN_WakeUp_Ok        
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup CAN_Exported_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup CAN_Exported_Functions
+  * @{
+  */
+/*  Function used to set the CAN configuration to the default reset state *****/ 
+void CAN_DeInit(CAN_TypeDef* CANx);
+
+/* Initialization and Configuration functions *********************************/ 
+uint8_t CAN_Init(CAN_TypeDef* CANx, CAN_InitTypeDef* CAN_InitStruct);
+void CAN_FilterInit(CAN_FilterInitTypeDef* CAN_FilterInitStruct);
+void CAN_StructInit(CAN_InitTypeDef* CAN_InitStruct);
+void CAN_SlaveStartBank(uint8_t CAN_BankNumber); 
+void CAN_DBGFreeze(CAN_TypeDef* CANx, FunctionalState NewState);
+void CAN_TTComModeCmd(CAN_TypeDef* CANx, FunctionalState NewState);
+
+/* Transmit functions *********************************************************/
+uint8_t CAN_Transmit(CAN_TypeDef* CANx, CanTxMsg* TxMessage);
+uint8_t CAN_TransmitStatus(CAN_TypeDef* CANx, uint8_t TransmitMailbox);
+void CAN_CancelTransmit(CAN_TypeDef* CANx, uint8_t Mailbox);
+
+/* Receive functions **********************************************************/
+void CAN_Receive(CAN_TypeDef* CANx, uint8_t FIFONumber, CanRxMsg* RxMessage);
+void CAN_FIFORelease(CAN_TypeDef* CANx, uint8_t FIFONumber);
+uint8_t CAN_MessagePending(CAN_TypeDef* CANx, uint8_t FIFONumber);
+
+
+/* Operation modes functions **************************************************/
+uint8_t CAN_OperatingModeRequest(CAN_TypeDef* CANx, uint8_t CAN_OperatingMode);
+uint8_t CAN_Sleep(CAN_TypeDef* CANx);
+uint8_t CAN_WakeUp(CAN_TypeDef* CANx);
+
+/* Error management functions *************************************************/
+uint8_t CAN_GetLastErrorCode(CAN_TypeDef* CANx);
+uint8_t CAN_GetReceiveErrorCounter(CAN_TypeDef* CANx);
+uint8_t CAN_GetLSBTransmitErrorCounter(CAN_TypeDef* CANx);
+
+/* Interrupts and flags management functions **********************************/
+void CAN_ITConfig(CAN_TypeDef* CANx, uint32_t CAN_IT, FunctionalState NewState);
+FlagStatus CAN_GetFlagStatus(CAN_TypeDef* CANx, uint32_t CAN_FLAG);
+void CAN_ClearFlag(CAN_TypeDef* CANx, uint32_t CAN_FLAG);
+ITStatus CAN_GetITStatus(CAN_TypeDef* CANx, uint32_t CAN_IT);
+void CAN_ClearITPendingBit(CAN_TypeDef* CANx, uint32_t CAN_IT);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F10x_CAN_H */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/STM32_4路称重_Git提交精简工程/src/STM32F10x_FWLib/inc/stm32f10x_cec.h b/STM32_4路称重_Git提交精简工程/src/STM32F10x_FWLib/inc/stm32f10x_cec.h
new file mode 100755
index 0000000..a3f8fc7
--- /dev/null
+++ b/STM32_4路称重_Git提交精简工程/src/STM32F10x_FWLib/inc/stm32f10x_cec.h
@@ -0,0 +1,210 @@
+/**
+  ******************************************************************************
+  * @file    stm32f10x_cec.h
+  * @author  MCD Application Team
+  * @version V3.5.0
+  * @date    11-March-2011
+  * @brief   This file contains all the functions prototypes for the CEC firmware 
+  *          library.
+  ******************************************************************************
+  * @attention
+  *
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+  *
+  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F10x_CEC_H
+#define __STM32F10x_CEC_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x.h"
+
+/** @addtogroup STM32F10x_StdPeriph_Driver
+  * @{
+  */
+
+/** @addtogroup CEC
+  * @{
+  */
+  
+
+/** @defgroup CEC_Exported_Types
+  * @{
+  */
+   
+/** 
+  * @brief  CEC Init structure definition  
+  */ 
+typedef struct
+{
+  uint16_t CEC_BitTimingMode; /*!< Configures the CEC Bit Timing Error Mode. 
+                               This parameter can be a value of @ref CEC_BitTiming_Mode */
+  uint16_t CEC_BitPeriodMode; /*!< Configures the CEC Bit Period Error Mode. 
+                               This parameter can be a value of @ref CEC_BitPeriod_Mode */
+}CEC_InitTypeDef;
+
+/**
+  * @}
+  */
+
+/** @defgroup CEC_Exported_Constants
+  * @{
+  */ 
+  
+/** @defgroup CEC_BitTiming_Mode 
+  * @{
+  */ 
+#define CEC_BitTimingStdMode                    ((uint16_t)0x00) /*!< Bit timing error Standard Mode */
+#define CEC_BitTimingErrFreeMode                CEC_CFGR_BTEM   /*!< Bit timing error Free Mode */
+
+#define IS_CEC_BIT_TIMING_ERROR_MODE(MODE) (((MODE) == CEC_BitTimingStdMode) || \
+                                            ((MODE) == CEC_BitTimingErrFreeMode))
+/**
+  * @}
+  */
+
+/** @defgroup CEC_BitPeriod_Mode 
+  * @{
+  */ 
+#define CEC_BitPeriodStdMode                    ((uint16_t)0x00) /*!< Bit period error Standard Mode */
+#define CEC_BitPeriodFlexibleMode                CEC_CFGR_BPEM   /*!< Bit period error Flexible Mode */
+
+#define IS_CEC_BIT_PERIOD_ERROR_MODE(MODE) (((MODE) == CEC_BitPeriodStdMode) || \
+                                            ((MODE) == CEC_BitPeriodFlexibleMode))
+/**
+  * @}
+  */ 
+
+
+/** @defgroup CEC_interrupts_definition 
+  * @{
+  */ 
+#define CEC_IT_TERR                              CEC_CSR_TERR
+#define CEC_IT_TBTRF                             CEC_CSR_TBTRF
+#define CEC_IT_RERR                              CEC_CSR_RERR
+#define CEC_IT_RBTF                              CEC_CSR_RBTF
+#define IS_CEC_GET_IT(IT) (((IT) == CEC_IT_TERR) || ((IT) == CEC_IT_TBTRF) || \
+                           ((IT) == CEC_IT_RERR) || ((IT) == CEC_IT_RBTF))
+/**
+  * @}
+  */ 
+
+
+/** @defgroup CEC_Own_Address 
+  * @{
+  */ 
+#define IS_CEC_ADDRESS(ADDRESS) ((ADDRESS) < 0x10)
+/**
+  * @}
+  */ 
+
+/** @defgroup CEC_Prescaler 
+  * @{
+  */ 
+#define IS_CEC_PRESCALER(PRESCALER) ((PRESCALER) <= 0x3FFF)
+
+/**
+  * @}
+  */
+
+/** @defgroup CEC_flags_definition 
+  * @{
+  */
+   
+/** 
+  * @brief  ESR register flags  
+  */ 
+#define CEC_FLAG_BTE                            ((uint32_t)0x10010000)
+#define CEC_FLAG_BPE                            ((uint32_t)0x10020000)
+#define CEC_FLAG_RBTFE                          ((uint32_t)0x10040000)
+#define CEC_FLAG_SBE                            ((uint32_t)0x10080000)
+#define CEC_FLAG_ACKE                           ((uint32_t)0x10100000)
+#define CEC_FLAG_LINE                           ((uint32_t)0x10200000)
+#define CEC_FLAG_TBTFE                          ((uint32_t)0x10400000)
+
+/** 
+  * @brief  CSR register flags  
+  */ 
+#define CEC_FLAG_TEOM                           ((uint32_t)0x00000002)  
+#define CEC_FLAG_TERR                           ((uint32_t)0x00000004)
+#define CEC_FLAG_TBTRF                          ((uint32_t)0x00000008)
+#define CEC_FLAG_RSOM                           ((uint32_t)0x00000010)
+#define CEC_FLAG_REOM                           ((uint32_t)0x00000020)
+#define CEC_FLAG_RERR                           ((uint32_t)0x00000040)
+#define CEC_FLAG_RBTF                           ((uint32_t)0x00000080)
+
+#define IS_CEC_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFFFF03) == 0x00) && ((FLAG) != 0x00))
+                               
+#define IS_CEC_GET_FLAG(FLAG) (((FLAG) == CEC_FLAG_BTE) || ((FLAG) == CEC_FLAG_BPE) || \
+                               ((FLAG) == CEC_FLAG_RBTFE) || ((FLAG)== CEC_FLAG_SBE) || \
+                               ((FLAG) == CEC_FLAG_ACKE) || ((FLAG) == CEC_FLAG_LINE) || \
+                               ((FLAG) == CEC_FLAG_TBTFE) || ((FLAG) == CEC_FLAG_TEOM) || \
+                               ((FLAG) == CEC_FLAG_TERR) || ((FLAG) == CEC_FLAG_TBTRF) || \
+                               ((FLAG) == CEC_FLAG_RSOM) || ((FLAG) == CEC_FLAG_REOM) || \
+                               ((FLAG) == CEC_FLAG_RERR) || ((FLAG) == CEC_FLAG_RBTF))
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+
+/** @defgroup CEC_Exported_Macros
+  * @{
+  */
+ 
+/**
+  * @}
+  */
+
+/** @defgroup CEC_Exported_Functions
+  * @{
+  */ 
+void CEC_DeInit(void);
+void CEC_Init(CEC_InitTypeDef* CEC_InitStruct);
+void CEC_Cmd(FunctionalState NewState);
+void CEC_ITConfig(FunctionalState NewState);
+void CEC_OwnAddressConfig(uint8_t CEC_OwnAddress);
+void CEC_SetPrescaler(uint16_t CEC_Prescaler);
+void CEC_SendDataByte(uint8_t Data);
+uint8_t CEC_ReceiveDataByte(void);
+void CEC_StartOfMessage(void);
+void CEC_EndOfMessageCmd(FunctionalState NewState);
+FlagStatus CEC_GetFlagStatus(uint32_t CEC_FLAG);
+void CEC_ClearFlag(uint32_t CEC_FLAG);
+ITStatus CEC_GetITStatus(uint8_t CEC_IT);
+void CEC_ClearITPendingBit(uint16_t CEC_IT);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F10x_CEC_H */
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/STM32_4路称重_Git提交精简工程/src/STM32F10x_FWLib/inc/stm32f10x_crc.h b/STM32_4路称重_Git提交精简工程/src/STM32F10x_FWLib/inc/stm32f10x_crc.h
new file mode 100755
index 0000000..658a51c
--- /dev/null
+++ b/STM32_4路称重_Git提交精简工程/src/STM32F10x_FWLib/inc/stm32f10x_crc.h
@@ -0,0 +1,94 @@
+/**
+  ******************************************************************************
+  * @file    stm32f10x_crc.h
+  * @author  MCD Application Team
+  * @version V3.5.0
+  * @date    11-March-2011
+  * @brief   This file contains all the functions prototypes for the CRC firmware 
+  *          library.
+  ******************************************************************************
+  * @attention
+  *
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+  *
+  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F10x_CRC_H
+#define __STM32F10x_CRC_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x.h"
+
+/** @addtogroup STM32F10x_StdPeriph_Driver
+  * @{
+  */
+
+/** @addtogroup CRC
+  * @{
+  */
+
+/** @defgroup CRC_Exported_Types
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup CRC_Exported_Constants
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup CRC_Exported_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup CRC_Exported_Functions
+  * @{
+  */
+
+void CRC_ResetDR(void);
+uint32_t CRC_CalcCRC(uint32_t Data);
+uint32_t CRC_CalcBlockCRC(uint32_t pBuffer[], uint32_t BufferLength);
+uint32_t CRC_GetCRC(void);
+void CRC_SetIDRegister(uint8_t IDValue);
+uint8_t CRC_GetIDRegister(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F10x_CRC_H */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/STM32_4路称重_Git提交精简工程/src/STM32F10x_FWLib/inc/stm32f10x_dac.h b/STM32_4路称重_Git提交精简工程/src/STM32F10x_FWLib/inc/stm32f10x_dac.h
new file mode 100755
index 0000000..7106164
--- /dev/null
+++ b/STM32_4路称重_Git提交精简工程/src/STM32F10x_FWLib/inc/stm32f10x_dac.h
@@ -0,0 +1,317 @@
+/**
+  ******************************************************************************
+  * @file    stm32f10x_dac.h
+  * @author  MCD Application Team
+  * @version V3.5.0
+  * @date    11-March-2011
+  * @brief   This file contains all the functions prototypes for the DAC firmware 
+  *          library.
+  ******************************************************************************
+  * @attention
+  *
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+  *
+  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F10x_DAC_H
+#define __STM32F10x_DAC_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x.h"
+
+/** @addtogroup STM32F10x_StdPeriph_Driver
+  * @{
+  */
+
+/** @addtogroup DAC
+  * @{
+  */
+
+/** @defgroup DAC_Exported_Types
+  * @{
+  */
+
+/** 
+  * @brief  DAC Init structure definition
+  */
+
+typedef struct
+{
+  uint32_t DAC_Trigger;                      /*!< Specifies the external trigger for the selected DAC channel.
+                                                  This parameter can be a value of @ref DAC_trigger_selection */
+
+  uint32_t DAC_WaveGeneration;               /*!< Specifies whether DAC channel noise waves or triangle waves
+                                                  are generated, or whether no wave is generated.
+                                                  This parameter can be a value of @ref DAC_wave_generation */
+
+  uint32_t DAC_LFSRUnmask_TriangleAmplitude; /*!< Specifies the LFSR mask for noise wave generation or
+                                                  the maximum amplitude triangle generation for the DAC channel. 
+                                                  This parameter can be a value of @ref DAC_lfsrunmask_triangleamplitude */
+
+  uint32_t DAC_OutputBuffer;                 /*!< Specifies whether the DAC channel output buffer is enabled or disabled.
+                                                  This parameter can be a value of @ref DAC_output_buffer */
+}DAC_InitTypeDef;
+
+/**
+  * @}
+  */
+
+/** @defgroup DAC_Exported_Constants
+  * @{
+  */
+
+/** @defgroup DAC_trigger_selection 
+  * @{
+  */
+
+#define DAC_Trigger_None                   ((uint32_t)0x00000000) /*!< Conversion is automatic once the DAC1_DHRxxxx register 
+                                                                       has been loaded, and not by external trigger */
+#define DAC_Trigger_T6_TRGO                ((uint32_t)0x00000004) /*!< TIM6 TRGO selected as external conversion trigger for DAC channel */
+#define DAC_Trigger_T8_TRGO                ((uint32_t)0x0000000C) /*!< TIM8 TRGO selected as external conversion trigger for DAC channel
+                                                                       only in High-density devices*/
+#define DAC_Trigger_T3_TRGO                ((uint32_t)0x0000000C) /*!< TIM8 TRGO selected as external conversion trigger for DAC channel
+                                                                       only in Connectivity line, Medium-density and Low-density Value Line devices */
+#define DAC_Trigger_T7_TRGO                ((uint32_t)0x00000014) /*!< TIM7 TRGO selected as external conversion trigger for DAC channel */
+#define DAC_Trigger_T5_TRGO                ((uint32_t)0x0000001C) /*!< TIM5 TRGO selected as external conversion trigger for DAC channel */
+#define DAC_Trigger_T15_TRGO               ((uint32_t)0x0000001C) /*!< TIM15 TRGO selected as external conversion trigger for DAC channel 
+                                                                       only in Medium-density and Low-density Value Line devices*/
+#define DAC_Trigger_T2_TRGO                ((uint32_t)0x00000024) /*!< TIM2 TRGO selected as external conversion trigger for DAC channel */
+#define DAC_Trigger_T4_TRGO                ((uint32_t)0x0000002C) /*!< TIM4 TRGO selected as external conversion trigger for DAC channel */
+#define DAC_Trigger_Ext_IT9                ((uint32_t)0x00000034) /*!< EXTI Line9 event selected as external conversion trigger for DAC channel */
+#define DAC_Trigger_Software               ((uint32_t)0x0000003C) /*!< Conversion started by software trigger for DAC channel */
+
+#define IS_DAC_TRIGGER(TRIGGER) (((TRIGGER) == DAC_Trigger_None) || \
+                                 ((TRIGGER) == DAC_Trigger_T6_TRGO) || \
+                                 ((TRIGGER) == DAC_Trigger_T8_TRGO) || \
+                                 ((TRIGGER) == DAC_Trigger_T7_TRGO) || \
+                                 ((TRIGGER) == DAC_Trigger_T5_TRGO) || \
+                                 ((TRIGGER) == DAC_Trigger_T2_TRGO) || \
+                                 ((TRIGGER) == DAC_Trigger_T4_TRGO) || \
+                                 ((TRIGGER) == DAC_Trigger_Ext_IT9) || \
+                                 ((TRIGGER) == DAC_Trigger_Software))
+
+/**
+  * @}
+  */
+
+/** @defgroup DAC_wave_generation 
+  * @{
+  */
+
+#define DAC_WaveGeneration_None            ((uint32_t)0x00000000)
+#define DAC_WaveGeneration_Noise           ((uint32_t)0x00000040)
+#define DAC_WaveGeneration_Triangle        ((uint32_t)0x00000080)
+#define IS_DAC_GENERATE_WAVE(WAVE) (((WAVE) == DAC_WaveGeneration_None) || \
+                                    ((WAVE) == DAC_WaveGeneration_Noise) || \
+                                    ((WAVE) == DAC_WaveGeneration_Triangle))
+/**
+  * @}
+  */
+
+/** @defgroup DAC_lfsrunmask_triangleamplitude
+  * @{
+  */
+
+#define DAC_LFSRUnmask_Bit0                ((uint32_t)0x00000000) /*!< Unmask DAC channel LFSR bit0 for noise wave generation */
+#define DAC_LFSRUnmask_Bits1_0             ((uint32_t)0x00000100) /*!< Unmask DAC channel LFSR bit[1:0] for noise wave generation */
+#define DAC_LFSRUnmask_Bits2_0             ((uint32_t)0x00000200) /*!< Unmask DAC channel LFSR bit[2:0] for noise wave generation */
+#define DAC_LFSRUnmask_Bits3_0             ((uint32_t)0x00000300) /*!< Unmask DAC channel LFSR bit[3:0] for noise wave generation */
+#define DAC_LFSRUnmask_Bits4_0             ((uint32_t)0x00000400) /*!< Unmask DAC channel LFSR bit[4:0] for noise wave generation */
+#define DAC_LFSRUnmask_Bits5_0             ((uint32_t)0x00000500) /*!< Unmask DAC channel LFSR bit[5:0] for noise wave generation */
+#define DAC_LFSRUnmask_Bits6_0             ((uint32_t)0x00000600) /*!< Unmask DAC channel LFSR bit[6:0] for noise wave generation */
+#define DAC_LFSRUnmask_Bits7_0             ((uint32_t)0x00000700) /*!< Unmask DAC channel LFSR bit[7:0] for noise wave generation */
+#define DAC_LFSRUnmask_Bits8_0             ((uint32_t)0x00000800) /*!< Unmask DAC channel LFSR bit[8:0] for noise wave generation */
+#define DAC_LFSRUnmask_Bits9_0             ((uint32_t)0x00000900) /*!< Unmask DAC channel LFSR bit[9:0] for noise wave generation */
+#define DAC_LFSRUnmask_Bits10_0            ((uint32_t)0x00000A00) /*!< Unmask DAC channel LFSR bit[10:0] for noise wave generation */
+#define DAC_LFSRUnmask_Bits11_0            ((uint32_t)0x00000B00) /*!< Unmask DAC channel LFSR bit[11:0] for noise wave generation */
+#define DAC_TriangleAmplitude_1            ((uint32_t)0x00000000) /*!< Select max triangle amplitude of 1 */
+#define DAC_TriangleAmplitude_3            ((uint32_t)0x00000100) /*!< Select max triangle amplitude of 3 */
+#define DAC_TriangleAmplitude_7            ((uint32_t)0x00000200) /*!< Select max triangle amplitude of 7 */
+#define DAC_TriangleAmplitude_15           ((uint32_t)0x00000300) /*!< Select max triangle amplitude of 15 */
+#define DAC_TriangleAmplitude_31           ((uint32_t)0x00000400) /*!< Select max triangle amplitude of 31 */
+#define DAC_TriangleAmplitude_63           ((uint32_t)0x00000500) /*!< Select max triangle amplitude of 63 */
+#define DAC_TriangleAmplitude_127          ((uint32_t)0x00000600) /*!< Select max triangle amplitude of 127 */
+#define DAC_TriangleAmplitude_255          ((uint32_t)0x00000700) /*!< Select max triangle amplitude of 255 */
+#define DAC_TriangleAmplitude_511          ((uint32_t)0x00000800) /*!< Select max triangle amplitude of 511 */
+#define DAC_TriangleAmplitude_1023         ((uint32_t)0x00000900) /*!< Select max triangle amplitude of 1023 */
+#define DAC_TriangleAmplitude_2047         ((uint32_t)0x00000A00) /*!< Select max triangle amplitude of 2047 */
+#define DAC_TriangleAmplitude_4095         ((uint32_t)0x00000B00) /*!< Select max triangle amplitude of 4095 */
+
+#define IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(VALUE) (((VALUE) == DAC_LFSRUnmask_Bit0) || \
+                                                      ((VALUE) == DAC_LFSRUnmask_Bits1_0) || \
+                                                      ((VALUE) == DAC_LFSRUnmask_Bits2_0) || \
+                                                      ((VALUE) == DAC_LFSRUnmask_Bits3_0) || \
+                                                      ((VALUE) == DAC_LFSRUnmask_Bits4_0) || \
+                                                      ((VALUE) == DAC_LFSRUnmask_Bits5_0) || \
+                                                      ((VALUE) == DAC_LFSRUnmask_Bits6_0) || \
+                                                      ((VALUE) == DAC_LFSRUnmask_Bits7_0) || \
+                                                      ((VALUE) == DAC_LFSRUnmask_Bits8_0) || \
+                                                      ((VALUE) == DAC_LFSRUnmask_Bits9_0) || \
+                                                      ((VALUE) == DAC_LFSRUnmask_Bits10_0) || \
+                                                      ((VALUE) == DAC_LFSRUnmask_Bits11_0) || \
+                                                      ((VALUE) == DAC_TriangleAmplitude_1) || \
+                                                      ((VALUE) == DAC_TriangleAmplitude_3) || \
+                                                      ((VALUE) == DAC_TriangleAmplitude_7) || \
+                                                      ((VALUE) == DAC_TriangleAmplitude_15) || \
+                                                      ((VALUE) == DAC_TriangleAmplitude_31) || \
+                                                      ((VALUE) == DAC_TriangleAmplitude_63) || \
+                                                      ((VALUE) == DAC_TriangleAmplitude_127) || \
+                                                      ((VALUE) == DAC_TriangleAmplitude_255) || \
+                                                      ((VALUE) == DAC_TriangleAmplitude_511) || \
+                                                      ((VALUE) == DAC_TriangleAmplitude_1023) || \
+                                                      ((VALUE) == DAC_TriangleAmplitude_2047) || \
+                                                      ((VALUE) == DAC_TriangleAmplitude_4095))
+/**
+  * @}
+  */
+
+/** @defgroup DAC_output_buffer 
+  * @{
+  */
+
+#define DAC_OutputBuffer_Enable            ((uint32_t)0x00000000)
+#define DAC_OutputBuffer_Disable           ((uint32_t)0x00000002)
+#define IS_DAC_OUTPUT_BUFFER_STATE(STATE) (((STATE) == DAC_OutputBuffer_Enable) || \
+                                           ((STATE) == DAC_OutputBuffer_Disable))
+/**
+  * @}
+  */
+
+/** @defgroup DAC_Channel_selection 
+  * @{
+  */
+
+#define DAC_Channel_1                      ((uint32_t)0x00000000)
+#define DAC_Channel_2                      ((uint32_t)0x00000010)
+#define IS_DAC_CHANNEL(CHANNEL) (((CHANNEL) == DAC_Channel_1) || \
+                                 ((CHANNEL) == DAC_Channel_2))
+/**
+  * @}
+  */
+
+/** @defgroup DAC_data_alignment 
+  * @{
+  */
+
+#define DAC_Align_12b_R                    ((uint32_t)0x00000000)
+#define DAC_Align_12b_L                    ((uint32_t)0x00000004)
+#define DAC_Align_8b_R                     ((uint32_t)0x00000008)
+#define IS_DAC_ALIGN(ALIGN) (((ALIGN) == DAC_Align_12b_R) || \
+                             ((ALIGN) == DAC_Align_12b_L) || \
+                             ((ALIGN) == DAC_Align_8b_R))
+/**
+  * @}
+  */
+
+/** @defgroup DAC_wave_generation 
+  * @{
+  */
+
+#define DAC_Wave_Noise                     ((uint32_t)0x00000040)
+#define DAC_Wave_Triangle                  ((uint32_t)0x00000080)
+#define IS_DAC_WAVE(WAVE) (((WAVE) == DAC_Wave_Noise) || \
+                           ((WAVE) == DAC_Wave_Triangle))
+/**
+  * @}
+  */
+
+/** @defgroup DAC_data 
+  * @{
+  */
+
+#define IS_DAC_DATA(DATA) ((DATA) <= 0xFFF0) 
+/**
+  * @}
+  */
+#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL)  || defined (STM32F10X_HD_VL)
+/** @defgroup DAC_interrupts_definition 
+  * @{
+  */ 
+  
+#define DAC_IT_DMAUDR                      ((uint32_t)0x00002000)  
+#define IS_DAC_IT(IT) (((IT) == DAC_IT_DMAUDR)) 
+
+/**
+  * @}
+  */ 
+
+/** @defgroup DAC_flags_definition 
+  * @{
+  */ 
+  
+#define DAC_FLAG_DMAUDR                    ((uint32_t)0x00002000)  
+#define IS_DAC_FLAG(FLAG) (((FLAG) == DAC_FLAG_DMAUDR))  
+
+/**
+  * @}
+  */
+#endif
+
+/**
+  * @}
+  */
+
+/** @defgroup DAC_Exported_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup DAC_Exported_Functions
+  * @{
+  */
+
+void DAC_DeInit(void);
+void DAC_Init(uint32_t DAC_Channel, DAC_InitTypeDef* DAC_InitStruct);
+void DAC_StructInit(DAC_InitTypeDef* DAC_InitStruct);
+void DAC_Cmd(uint32_t DAC_Channel, FunctionalState NewState);
+#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
+void DAC_ITConfig(uint32_t DAC_Channel, uint32_t DAC_IT, FunctionalState NewState);
+#endif
+void DAC_DMACmd(uint32_t DAC_Channel, FunctionalState NewState);
+void DAC_SoftwareTriggerCmd(uint32_t DAC_Channel, FunctionalState NewState);
+void DAC_DualSoftwareTriggerCmd(FunctionalState NewState);
+void DAC_WaveGenerationCmd(uint32_t DAC_Channel, uint32_t DAC_Wave, FunctionalState NewState);
+void DAC_SetChannel1Data(uint32_t DAC_Align, uint16_t Data);
+void DAC_SetChannel2Data(uint32_t DAC_Align, uint16_t Data);
+void DAC_SetDualChannelData(uint32_t DAC_Align, uint16_t Data2, uint16_t Data1);
+uint16_t DAC_GetDataOutputValue(uint32_t DAC_Channel);
+#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) 
+FlagStatus DAC_GetFlagStatus(uint32_t DAC_Channel, uint32_t DAC_FLAG);
+void DAC_ClearFlag(uint32_t DAC_Channel, uint32_t DAC_FLAG);
+ITStatus DAC_GetITStatus(uint32_t DAC_Channel, uint32_t DAC_IT);
+void DAC_ClearITPendingBit(uint32_t DAC_Channel, uint32_t DAC_IT);
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__STM32F10x_DAC_H */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/STM32_4路称重_Git提交精简工程/src/STM32F10x_FWLib/inc/stm32f10x_dbgmcu.h b/STM32_4路称重_Git提交精简工程/src/STM32F10x_FWLib/inc/stm32f10x_dbgmcu.h
new file mode 100755
index 0000000..1e6a68a
--- /dev/null
+++ b/STM32_4路称重_Git提交精简工程/src/STM32F10x_FWLib/inc/stm32f10x_dbgmcu.h
@@ -0,0 +1,119 @@
+/**
+  ******************************************************************************
+  * @file    stm32f10x_dbgmcu.h
+  * @author  MCD Application Team
+  * @version V3.5.0
+  * @date    11-March-2011
+  * @brief   This file contains all the functions prototypes for the DBGMCU 
+  *          firmware library.
+  ******************************************************************************
+  * @attention
+  *
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+  *
+  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F10x_DBGMCU_H
+#define __STM32F10x_DBGMCU_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x.h"
+
+/** @addtogroup STM32F10x_StdPeriph_Driver
+  * @{
+  */
+
+/** @addtogroup DBGMCU
+  * @{
+  */
+
+/** @defgroup DBGMCU_Exported_Types
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup DBGMCU_Exported_Constants
+  * @{
+  */
+
+#define DBGMCU_SLEEP                 ((uint32_t)0x00000001)
+#define DBGMCU_STOP                  ((uint32_t)0x00000002)
+#define DBGMCU_STANDBY               ((uint32_t)0x00000004)
+#define DBGMCU_IWDG_STOP             ((uint32_t)0x00000100)
+#define DBGMCU_WWDG_STOP             ((uint32_t)0x00000200)
+#define DBGMCU_TIM1_STOP             ((uint32_t)0x00000400)
+#define DBGMCU_TIM2_STOP             ((uint32_t)0x00000800)
+#define DBGMCU_TIM3_STOP             ((uint32_t)0x00001000)
+#define DBGMCU_TIM4_STOP             ((uint32_t)0x00002000)
+#define DBGMCU_CAN1_STOP             ((uint32_t)0x00004000)
+#define DBGMCU_I2C1_SMBUS_TIMEOUT    ((uint32_t)0x00008000)
+#define DBGMCU_I2C2_SMBUS_TIMEOUT    ((uint32_t)0x00010000)
+#define DBGMCU_TIM8_STOP             ((uint32_t)0x00020000)
+#define DBGMCU_TIM5_STOP             ((uint32_t)0x00040000)
+#define DBGMCU_TIM6_STOP             ((uint32_t)0x00080000)
+#define DBGMCU_TIM7_STOP             ((uint32_t)0x00100000)
+#define DBGMCU_CAN2_STOP             ((uint32_t)0x00200000)
+#define DBGMCU_TIM15_STOP            ((uint32_t)0x00400000)
+#define DBGMCU_TIM16_STOP            ((uint32_t)0x00800000)
+#define DBGMCU_TIM17_STOP            ((uint32_t)0x01000000)
+#define DBGMCU_TIM12_STOP            ((uint32_t)0x02000000)
+#define DBGMCU_TIM13_STOP            ((uint32_t)0x04000000)
+#define DBGMCU_TIM14_STOP            ((uint32_t)0x08000000)
+#define DBGMCU_TIM9_STOP             ((uint32_t)0x10000000)
+#define DBGMCU_TIM10_STOP            ((uint32_t)0x20000000)
+#define DBGMCU_TIM11_STOP            ((uint32_t)0x40000000)
+                                              
+#define IS_DBGMCU_PERIPH(PERIPH) ((((PERIPH) & 0x800000F8) == 0x00) && ((PERIPH) != 0x00))
+/**
+  * @}
+  */ 
+
+/** @defgroup DBGMCU_Exported_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup DBGMCU_Exported_Functions
+  * @{
+  */
+
+uint32_t DBGMCU_GetREVID(void);
+uint32_t DBGMCU_GetDEVID(void);
+void DBGMCU_Config(uint32_t DBGMCU_Periph, FunctionalState NewState);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F10x_DBGMCU_H */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/STM32_4路称重_Git提交精简工程/src/STM32F10x_FWLib/inc/stm32f10x_dma.h b/STM32_4路称重_Git提交精简工程/src/STM32F10x_FWLib/inc/stm32f10x_dma.h
new file mode 100755
index 0000000..b5dc6a8
--- /dev/null
+++ b/STM32_4路称重_Git提交精简工程/src/STM32F10x_FWLib/inc/stm32f10x_dma.h
@@ -0,0 +1,439 @@
+/**
+  ******************************************************************************
+  * @file    stm32f10x_dma.h
+  * @author  MCD Application Team
+  * @version V3.5.0
+  * @date    11-March-2011
+  * @brief   This file contains all the functions prototypes for the DMA firmware 
+  *          library.
+  ******************************************************************************
+  * @attention
+  *
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+  *
+  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F10x_DMA_H
+#define __STM32F10x_DMA_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x.h"
+
+/** @addtogroup STM32F10x_StdPeriph_Driver
+  * @{
+  */
+
+/** @addtogroup DMA
+  * @{
+  */
+
+/** @defgroup DMA_Exported_Types
+  * @{
+  */
+
+/** 
+  * @brief  DMA Init structure definition
+  */
+
+typedef struct
+{
+  uint32_t DMA_PeripheralBaseAddr; /*!< Specifies the peripheral base address for DMAy Channelx. */
+
+  uint32_t DMA_MemoryBaseAddr;     /*!< Specifies the memory base address for DMAy Channelx. */
+
+  uint32_t DMA_DIR;                /*!< Specifies if the peripheral is the source or destination.
+                                        This parameter can be a value of @ref DMA_data_transfer_direction */
+
+  uint32_t DMA_BufferSize;         /*!< Specifies the buffer size, in data unit, of the specified Channel. 
+                                        The data unit is equal to the configuration set in DMA_PeripheralDataSize
+                                        or DMA_MemoryDataSize members depending in the transfer direction. */
+
+  uint32_t DMA_PeripheralInc;      /*!< Specifies whether the Peripheral address register is incremented or not.
+                                        This parameter can be a value of @ref DMA_peripheral_incremented_mode */
+
+  uint32_t DMA_MemoryInc;          /*!< Specifies whether the memory address register is incremented or not.
+                                        This parameter can be a value of @ref DMA_memory_incremented_mode */
+
+  uint32_t DMA_PeripheralDataSize; /*!< Specifies the Peripheral data width.
+                                        This parameter can be a value of @ref DMA_peripheral_data_size */
+
+  uint32_t DMA_MemoryDataSize;     /*!< Specifies the Memory data width.
+                                        This parameter can be a value of @ref DMA_memory_data_size */
+
+  uint32_t DMA_Mode;               /*!< Specifies the operation mode of the DMAy Channelx.
+                                        This parameter can be a value of @ref DMA_circular_normal_mode.
+                                        @note: The circular buffer mode cannot be used if the memory-to-memory
+                                              data transfer is configured on the selected Channel */
+
+  uint32_t DMA_Priority;           /*!< Specifies the software priority for the DMAy Channelx.
+                                        This parameter can be a value of @ref DMA_priority_level */
+
+  uint32_t DMA_M2M;                /*!< Specifies if the DMAy Channelx will be used in memory-to-memory transfer.
+                                        This parameter can be a value of @ref DMA_memory_to_memory */
+}DMA_InitTypeDef;
+
+/**
+  * @}
+  */
+
+/** @defgroup DMA_Exported_Constants
+  * @{
+  */
+
+#define IS_DMA_ALL_PERIPH(PERIPH) (((PERIPH) == DMA1_Channel1) || \
+                                   ((PERIPH) == DMA1_Channel2) || \
+                                   ((PERIPH) == DMA1_Channel3) || \
+                                   ((PERIPH) == DMA1_Channel4) || \
+                                   ((PERIPH) == DMA1_Channel5) || \
+                                   ((PERIPH) == DMA1_Channel6) || \
+                                   ((PERIPH) == DMA1_Channel7) || \
+                                   ((PERIPH) == DMA2_Channel1) || \
+                                   ((PERIPH) == DMA2_Channel2) || \
+                                   ((PERIPH) == DMA2_Channel3) || \
+                                   ((PERIPH) == DMA2_Channel4) || \
+                                   ((PERIPH) == DMA2_Channel5))
+
+/** @defgroup DMA_data_transfer_direction 
+  * @{
+  */
+
+#define DMA_DIR_PeripheralDST              ((uint32_t)0x00000010)
+#define DMA_DIR_PeripheralSRC              ((uint32_t)0x00000000)
+#define IS_DMA_DIR(DIR) (((DIR) == DMA_DIR_PeripheralDST) || \
+                         ((DIR) == DMA_DIR_PeripheralSRC))
+/**
+  * @}
+  */
+
+/** @defgroup DMA_peripheral_incremented_mode 
+  * @{
+  */
+
+#define DMA_PeripheralInc_Enable           ((uint32_t)0x00000040)
+#define DMA_PeripheralInc_Disable          ((uint32_t)0x00000000)
+#define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PeripheralInc_Enable) || \
+                                            ((STATE) == DMA_PeripheralInc_Disable))
+/**
+  * @}
+  */
+
+/** @defgroup DMA_memory_incremented_mode 
+  * @{
+  */
+
+#define DMA_MemoryInc_Enable               ((uint32_t)0x00000080)
+#define DMA_MemoryInc_Disable              ((uint32_t)0x00000000)
+#define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MemoryInc_Enable) || \
+                                        ((STATE) == DMA_MemoryInc_Disable))
+/**
+  * @}
+  */
+
+/** @defgroup DMA_peripheral_data_size 
+  * @{
+  */
+
+#define DMA_PeripheralDataSize_Byte        ((uint32_t)0x00000000)
+#define DMA_PeripheralDataSize_HalfWord    ((uint32_t)0x00000100)
+#define DMA_PeripheralDataSize_Word        ((uint32_t)0x00000200)
+#define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PeripheralDataSize_Byte) || \
+                                           ((SIZE) == DMA_PeripheralDataSize_HalfWord) || \
+                                           ((SIZE) == DMA_PeripheralDataSize_Word))
+/**
+  * @}
+  */
+
+/** @defgroup DMA_memory_data_size 
+  * @{
+  */
+
+#define DMA_MemoryDataSize_Byte            ((uint32_t)0x00000000)
+#define DMA_MemoryDataSize_HalfWord        ((uint32_t)0x00000400)
+#define DMA_MemoryDataSize_Word            ((uint32_t)0x00000800)
+#define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MemoryDataSize_Byte) || \
+                                       ((SIZE) == DMA_MemoryDataSize_HalfWord) || \
+                                       ((SIZE) == DMA_MemoryDataSize_Word))
+/**
+  * @}
+  */
+
+/** @defgroup DMA_circular_normal_mode 
+  * @{
+  */
+
+#define DMA_Mode_Circular                  ((uint32_t)0x00000020)
+#define DMA_Mode_Normal                    ((uint32_t)0x00000000)
+#define IS_DMA_MODE(MODE) (((MODE) == DMA_Mode_Circular) || ((MODE) == DMA_Mode_Normal))
+/**
+  * @}
+  */
+
+/** @defgroup DMA_priority_level 
+  * @{
+  */
+
+#define DMA_Priority_VeryHigh              ((uint32_t)0x00003000)
+#define DMA_Priority_High                  ((uint32_t)0x00002000)
+#define DMA_Priority_Medium                ((uint32_t)0x00001000)
+#define DMA_Priority_Low                   ((uint32_t)0x00000000)
+#define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_Priority_VeryHigh) || \
+                                   ((PRIORITY) == DMA_Priority_High) || \
+                                   ((PRIORITY) == DMA_Priority_Medium) || \
+                                   ((PRIORITY) == DMA_Priority_Low))
+/**
+  * @}
+  */
+
+/** @defgroup DMA_memory_to_memory 
+  * @{
+  */
+
+#define DMA_M2M_Enable                     ((uint32_t)0x00004000)
+#define DMA_M2M_Disable                    ((uint32_t)0x00000000)
+#define IS_DMA_M2M_STATE(STATE) (((STATE) == DMA_M2M_Enable) || ((STATE) == DMA_M2M_Disable))
+
+/**
+  * @}
+  */
+
+/** @defgroup DMA_interrupts_definition 
+  * @{
+  */
+
+#define DMA_IT_TC                          ((uint32_t)0x00000002)
+#define DMA_IT_HT                          ((uint32_t)0x00000004)
+#define DMA_IT_TE                          ((uint32_t)0x00000008)
+#define IS_DMA_CONFIG_IT(IT) ((((IT) & 0xFFFFFFF1) == 0x00) && ((IT) != 0x00))
+
+#define DMA1_IT_GL1                        ((uint32_t)0x00000001)
+#define DMA1_IT_TC1                        ((uint32_t)0x00000002)
+#define DMA1_IT_HT1                        ((uint32_t)0x00000004)
+#define DMA1_IT_TE1                        ((uint32_t)0x00000008)
+#define DMA1_IT_GL2                        ((uint32_t)0x00000010)
+#define DMA1_IT_TC2                        ((uint32_t)0x00000020)
+#define DMA1_IT_HT2                        ((uint32_t)0x00000040)
+#define DMA1_IT_TE2                        ((uint32_t)0x00000080)
+#define DMA1_IT_GL3                        ((uint32_t)0x00000100)
+#define DMA1_IT_TC3                        ((uint32_t)0x00000200)
+#define DMA1_IT_HT3                        ((uint32_t)0x00000400)
+#define DMA1_IT_TE3                        ((uint32_t)0x00000800)
+#define DMA1_IT_GL4                        ((uint32_t)0x00001000)
+#define DMA1_IT_TC4                        ((uint32_t)0x00002000)
+#define DMA1_IT_HT4                        ((uint32_t)0x00004000)
+#define DMA1_IT_TE4                        ((uint32_t)0x00008000)
+#define DMA1_IT_GL5                        ((uint32_t)0x00010000)
+#define DMA1_IT_TC5                        ((uint32_t)0x00020000)
+#define DMA1_IT_HT5                        ((uint32_t)0x00040000)
+#define DMA1_IT_TE5                        ((uint32_t)0x00080000)
+#define DMA1_IT_GL6                        ((uint32_t)0x00100000)
+#define DMA1_IT_TC6                        ((uint32_t)0x00200000)
+#define DMA1_IT_HT6                        ((uint32_t)0x00400000)
+#define DMA1_IT_TE6                        ((uint32_t)0x00800000)
+#define DMA1_IT_GL7                        ((uint32_t)0x01000000)
+#define DMA1_IT_TC7                        ((uint32_t)0x02000000)
+#define DMA1_IT_HT7                        ((uint32_t)0x04000000)
+#define DMA1_IT_TE7                        ((uint32_t)0x08000000)
+
+#define DMA2_IT_GL1                        ((uint32_t)0x10000001)
+#define DMA2_IT_TC1                        ((uint32_t)0x10000002)
+#define DMA2_IT_HT1                        ((uint32_t)0x10000004)
+#define DMA2_IT_TE1                        ((uint32_t)0x10000008)
+#define DMA2_IT_GL2                        ((uint32_t)0x10000010)
+#define DMA2_IT_TC2                        ((uint32_t)0x10000020)
+#define DMA2_IT_HT2                        ((uint32_t)0x10000040)
+#define DMA2_IT_TE2                        ((uint32_t)0x10000080)
+#define DMA2_IT_GL3                        ((uint32_t)0x10000100)
+#define DMA2_IT_TC3                        ((uint32_t)0x10000200)
+#define DMA2_IT_HT3                        ((uint32_t)0x10000400)
+#define DMA2_IT_TE3                        ((uint32_t)0x10000800)
+#define DMA2_IT_GL4                        ((uint32_t)0x10001000)
+#define DMA2_IT_TC4                        ((uint32_t)0x10002000)
+#define DMA2_IT_HT4                        ((uint32_t)0x10004000)
+#define DMA2_IT_TE4                        ((uint32_t)0x10008000)
+#define DMA2_IT_GL5                        ((uint32_t)0x10010000)
+#define DMA2_IT_TC5                        ((uint32_t)0x10020000)
+#define DMA2_IT_HT5                        ((uint32_t)0x10040000)
+#define DMA2_IT_TE5                        ((uint32_t)0x10080000)
+
+#define IS_DMA_CLEAR_IT(IT) (((((IT) & 0xF0000000) == 0x00) || (((IT) & 0xEFF00000) == 0x00)) && ((IT) != 0x00))
+
+#define IS_DMA_GET_IT(IT) (((IT) == DMA1_IT_GL1) || ((IT) == DMA1_IT_TC1) || \
+                           ((IT) == DMA1_IT_HT1) || ((IT) == DMA1_IT_TE1) || \
+                           ((IT) == DMA1_IT_GL2) || ((IT) == DMA1_IT_TC2) || \
+                           ((IT) == DMA1_IT_HT2) || ((IT) == DMA1_IT_TE2) || \
+                           ((IT) == DMA1_IT_GL3) || ((IT) == DMA1_IT_TC3) || \
+                           ((IT) == DMA1_IT_HT3) || ((IT) == DMA1_IT_TE3) || \
+                           ((IT) == DMA1_IT_GL4) || ((IT) == DMA1_IT_TC4) || \
+                           ((IT) == DMA1_IT_HT4) || ((IT) == DMA1_IT_TE4) || \
+                           ((IT) == DMA1_IT_GL5) || ((IT) == DMA1_IT_TC5) || \
+                           ((IT) == DMA1_IT_HT5) || ((IT) == DMA1_IT_TE5) || \
+                           ((IT) == DMA1_IT_GL6) || ((IT) == DMA1_IT_TC6) || \
+                           ((IT) == DMA1_IT_HT6) || ((IT) == DMA1_IT_TE6) || \
+                           ((IT) == DMA1_IT_GL7) || ((IT) == DMA1_IT_TC7) || \
+                           ((IT) == DMA1_IT_HT7) || ((IT) == DMA1_IT_TE7) || \
+                           ((IT) == DMA2_IT_GL1) || ((IT) == DMA2_IT_TC1) || \
+                           ((IT) == DMA2_IT_HT1) || ((IT) == DMA2_IT_TE1) || \
+                           ((IT) == DMA2_IT_GL2) || ((IT) == DMA2_IT_TC2) || \
+                           ((IT) == DMA2_IT_HT2) || ((IT) == DMA2_IT_TE2) || \
+                           ((IT) == DMA2_IT_GL3) || ((IT) == DMA2_IT_TC3) || \
+                           ((IT) == DMA2_IT_HT3) || ((IT) == DMA2_IT_TE3) || \
+                           ((IT) == DMA2_IT_GL4) || ((IT) == DMA2_IT_TC4) || \
+                           ((IT) == DMA2_IT_HT4) || ((IT) == DMA2_IT_TE4) || \
+                           ((IT) == DMA2_IT_GL5) || ((IT) == DMA2_IT_TC5) || \
+                           ((IT) == DMA2_IT_HT5) || ((IT) == DMA2_IT_TE5))
+
+/**
+  * @}
+  */
+
+/** @defgroup DMA_flags_definition 
+  * @{
+  */
+#define DMA1_FLAG_GL1                      ((uint32_t)0x00000001)
+#define DMA1_FLAG_TC1                      ((uint32_t)0x00000002)
+#define DMA1_FLAG_HT1                      ((uint32_t)0x00000004)
+#define DMA1_FLAG_TE1                      ((uint32_t)0x00000008)
+#define DMA1_FLAG_GL2                      ((uint32_t)0x00000010)
+#define DMA1_FLAG_TC2                      ((uint32_t)0x00000020)
+#define DMA1_FLAG_HT2                      ((uint32_t)0x00000040)
+#define DMA1_FLAG_TE2                      ((uint32_t)0x00000080)
+#define DMA1_FLAG_GL3                      ((uint32_t)0x00000100)
+#define DMA1_FLAG_TC3                      ((uint32_t)0x00000200)
+#define DMA1_FLAG_HT3                      ((uint32_t)0x00000400)
+#define DMA1_FLAG_TE3                      ((uint32_t)0x00000800)
+#define DMA1_FLAG_GL4                      ((uint32_t)0x00001000)
+#define DMA1_FLAG_TC4                      ((uint32_t)0x00002000)
+#define DMA1_FLAG_HT4                      ((uint32_t)0x00004000)
+#define DMA1_FLAG_TE4                      ((uint32_t)0x00008000)
+#define DMA1_FLAG_GL5                      ((uint32_t)0x00010000)
+#define DMA1_FLAG_TC5                      ((uint32_t)0x00020000)
+#define DMA1_FLAG_HT5                      ((uint32_t)0x00040000)
+#define DMA1_FLAG_TE5                      ((uint32_t)0x00080000)
+#define DMA1_FLAG_GL6                      ((uint32_t)0x00100000)
+#define DMA1_FLAG_TC6                      ((uint32_t)0x00200000)
+#define DMA1_FLAG_HT6                      ((uint32_t)0x00400000)
+#define DMA1_FLAG_TE6                      ((uint32_t)0x00800000)
+#define DMA1_FLAG_GL7                      ((uint32_t)0x01000000)
+#define DMA1_FLAG_TC7                      ((uint32_t)0x02000000)
+#define DMA1_FLAG_HT7                      ((uint32_t)0x04000000)
+#define DMA1_FLAG_TE7                      ((uint32_t)0x08000000)
+
+#define DMA2_FLAG_GL1                      ((uint32_t)0x10000001)
+#define DMA2_FLAG_TC1                      ((uint32_t)0x10000002)
+#define DMA2_FLAG_HT1                      ((uint32_t)0x10000004)
+#define DMA2_FLAG_TE1                      ((uint32_t)0x10000008)
+#define DMA2_FLAG_GL2                      ((uint32_t)0x10000010)
+#define DMA2_FLAG_TC2                      ((uint32_t)0x10000020)
+#define DMA2_FLAG_HT2                      ((uint32_t)0x10000040)
+#define DMA2_FLAG_TE2                      ((uint32_t)0x10000080)
+#define DMA2_FLAG_GL3                      ((uint32_t)0x10000100)
+#define DMA2_FLAG_TC3                      ((uint32_t)0x10000200)
+#define DMA2_FLAG_HT3                      ((uint32_t)0x10000400)
+#define DMA2_FLAG_TE3                      ((uint32_t)0x10000800)
+#define DMA2_FLAG_GL4                      ((uint32_t)0x10001000)
+#define DMA2_FLAG_TC4                      ((uint32_t)0x10002000)
+#define DMA2_FLAG_HT4                      ((uint32_t)0x10004000)
+#define DMA2_FLAG_TE4                      ((uint32_t)0x10008000)
+#define DMA2_FLAG_GL5                      ((uint32_t)0x10010000)
+#define DMA2_FLAG_TC5                      ((uint32_t)0x10020000)
+#define DMA2_FLAG_HT5                      ((uint32_t)0x10040000)
+#define DMA2_FLAG_TE5                      ((uint32_t)0x10080000)
+
+#define IS_DMA_CLEAR_FLAG(FLAG) (((((FLAG) & 0xF0000000) == 0x00) || (((FLAG) & 0xEFF00000) == 0x00)) && ((FLAG) != 0x00))
+
+#define IS_DMA_GET_FLAG(FLAG) (((FLAG) == DMA1_FLAG_GL1) || ((FLAG) == DMA1_FLAG_TC1) || \
+                               ((FLAG) == DMA1_FLAG_HT1) || ((FLAG) == DMA1_FLAG_TE1) || \
+                               ((FLAG) == DMA1_FLAG_GL2) || ((FLAG) == DMA1_FLAG_TC2) || \
+                               ((FLAG) == DMA1_FLAG_HT2) || ((FLAG) == DMA1_FLAG_TE2) || \
+                               ((FLAG) == DMA1_FLAG_GL3) || ((FLAG) == DMA1_FLAG_TC3) || \
+                               ((FLAG) == DMA1_FLAG_HT3) || ((FLAG) == DMA1_FLAG_TE3) || \
+                               ((FLAG) == DMA1_FLAG_GL4) || ((FLAG) == DMA1_FLAG_TC4) || \
+                               ((FLAG) == DMA1_FLAG_HT4) || ((FLAG) == DMA1_FLAG_TE4) || \
+                               ((FLAG) == DMA1_FLAG_GL5) || ((FLAG) == DMA1_FLAG_TC5) || \
+                               ((FLAG) == DMA1_FLAG_HT5) || ((FLAG) == DMA1_FLAG_TE5) || \
+                               ((FLAG) == DMA1_FLAG_GL6) || ((FLAG) == DMA1_FLAG_TC6) || \
+                               ((FLAG) == DMA1_FLAG_HT6) || ((FLAG) == DMA1_FLAG_TE6) || \
+                               ((FLAG) == DMA1_FLAG_GL7) || ((FLAG) == DMA1_FLAG_TC7) || \
+                               ((FLAG) == DMA1_FLAG_HT7) || ((FLAG) == DMA1_FLAG_TE7) || \
+                               ((FLAG) == DMA2_FLAG_GL1) || ((FLAG) == DMA2_FLAG_TC1) || \
+                               ((FLAG) == DMA2_FLAG_HT1) || ((FLAG) == DMA2_FLAG_TE1) || \
+                               ((FLAG) == DMA2_FLAG_GL2) || ((FLAG) == DMA2_FLAG_TC2) || \
+                               ((FLAG) == DMA2_FLAG_HT2) || ((FLAG) == DMA2_FLAG_TE2) || \
+                               ((FLAG) == DMA2_FLAG_GL3) || ((FLAG) == DMA2_FLAG_TC3) || \
+                               ((FLAG) == DMA2_FLAG_HT3) || ((FLAG) == DMA2_FLAG_TE3) || \
+                               ((FLAG) == DMA2_FLAG_GL4) || ((FLAG) == DMA2_FLAG_TC4) || \
+                               ((FLAG) == DMA2_FLAG_HT4) || ((FLAG) == DMA2_FLAG_TE4) || \
+                               ((FLAG) == DMA2_FLAG_GL5) || ((FLAG) == DMA2_FLAG_TC5) || \
+                               ((FLAG) == DMA2_FLAG_HT5) || ((FLAG) == DMA2_FLAG_TE5))
+/**
+  * @}
+  */
+
+/** @defgroup DMA_Buffer_Size 
+  * @{
+  */
+
+#define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1) && ((SIZE) < 0x10000))
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup DMA_Exported_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup DMA_Exported_Functions
+  * @{
+  */
+
+void DMA_DeInit(DMA_Channel_TypeDef* DMAy_Channelx);
+void DMA_Init(DMA_Channel_TypeDef* DMAy_Channelx, DMA_InitTypeDef* DMA_InitStruct);
+void DMA_StructInit(DMA_InitTypeDef* DMA_InitStruct);
+void DMA_Cmd(DMA_Channel_TypeDef* DMAy_Channelx, FunctionalState NewState);
+void DMA_ITConfig(DMA_Channel_TypeDef* DMAy_Channelx, uint32_t DMA_IT, FunctionalState NewState);
+void DMA_SetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx, uint16_t DataNumber); 
+uint16_t DMA_GetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx);
+FlagStatus DMA_GetFlagStatus(uint32_t DMAy_FLAG);
+void DMA_ClearFlag(uint32_t DMAy_FLAG);
+ITStatus DMA_GetITStatus(uint32_t DMAy_IT);
+void DMA_ClearITPendingBit(uint32_t DMAy_IT);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__STM32F10x_DMA_H */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/STM32_4路称重_Git提交精简工程/src/STM32F10x_FWLib/inc/stm32f10x_exti.h b/STM32_4路称重_Git提交精简工程/src/STM32F10x_FWLib/inc/stm32f10x_exti.h
new file mode 100755
index 0000000..a1ab7d0
--- /dev/null
+++ b/STM32_4路称重_Git提交精简工程/src/STM32F10x_FWLib/inc/stm32f10x_exti.h
@@ -0,0 +1,184 @@
+/**
+  ******************************************************************************
+  * @file    stm32f10x_exti.h
+  * @author  MCD Application Team
+  * @version V3.5.0
+  * @date    11-March-2011
+  * @brief   This file contains all the functions prototypes for the EXTI firmware
+  *          library.
+  ******************************************************************************
+  * @attention
+  *
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+  *
+  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F10x_EXTI_H
+#define __STM32F10x_EXTI_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x.h"
+
+/** @addtogroup STM32F10x_StdPeriph_Driver
+  * @{
+  */
+
+/** @addtogroup EXTI
+  * @{
+  */
+
+/** @defgroup EXTI_Exported_Types
+  * @{
+  */
+
+/** 
+  * @brief  EXTI mode enumeration  
+  */
+
+typedef enum
+{
+  EXTI_Mode_Interrupt = 0x00,
+  EXTI_Mode_Event = 0x04
+}EXTIMode_TypeDef;
+
+#define IS_EXTI_MODE(MODE) (((MODE) == EXTI_Mode_Interrupt) || ((MODE) == EXTI_Mode_Event))
+
+/** 
+  * @brief  EXTI Trigger enumeration  
+  */
+
+typedef enum
+{
+  EXTI_Trigger_Rising = 0x08,
+  EXTI_Trigger_Falling = 0x0C,  
+  EXTI_Trigger_Rising_Falling = 0x10
+}EXTITrigger_TypeDef;
+
+#define IS_EXTI_TRIGGER(TRIGGER) (((TRIGGER) == EXTI_Trigger_Rising) || \
+                                  ((TRIGGER) == EXTI_Trigger_Falling) || \
+                                  ((TRIGGER) == EXTI_Trigger_Rising_Falling))
+/** 
+  * @brief  EXTI Init Structure definition  
+  */
+
+typedef struct
+{
+  uint32_t EXTI_Line;               /*!< Specifies the EXTI lines to be enabled or disabled.
+                                         This parameter can be any combination of @ref EXTI_Lines */
+   
+  EXTIMode_TypeDef EXTI_Mode;       /*!< Specifies the mode for the EXTI lines.
+                                         This parameter can be a value of @ref EXTIMode_TypeDef */
+
+  EXTITrigger_TypeDef EXTI_Trigger; /*!< Specifies the trigger signal active edge for the EXTI lines.
+                                         This parameter can be a value of @ref EXTIMode_TypeDef */
+
+  FunctionalState EXTI_LineCmd;     /*!< Specifies the new state of the selected EXTI lines.
+                                         This parameter can be set either to ENABLE or DISABLE */ 
+}EXTI_InitTypeDef;
+
+/**
+  * @}
+  */
+
+/** @defgroup EXTI_Exported_Constants
+  * @{
+  */
+
+/** @defgroup EXTI_Lines 
+  * @{
+  */
+
+#define EXTI_Line0       ((uint32_t)0x00001)  /*!< External interrupt line 0 */
+#define EXTI_Line1       ((uint32_t)0x00002)  /*!< External interrupt line 1 */
+#define EXTI_Line2       ((uint32_t)0x00004)  /*!< External interrupt line 2 */
+#define EXTI_Line3       ((uint32_t)0x00008)  /*!< External interrupt line 3 */
+#define EXTI_Line4       ((uint32_t)0x00010)  /*!< External interrupt line 4 */
+#define EXTI_Line5       ((uint32_t)0x00020)  /*!< External interrupt line 5 */
+#define EXTI_Line6       ((uint32_t)0x00040)  /*!< External interrupt line 6 */
+#define EXTI_Line7       ((uint32_t)0x00080)  /*!< External interrupt line 7 */
+#define EXTI_Line8       ((uint32_t)0x00100)  /*!< External interrupt line 8 */
+#define EXTI_Line9       ((uint32_t)0x00200)  /*!< External interrupt line 9 */
+#define EXTI_Line10      ((uint32_t)0x00400)  /*!< External interrupt line 10 */
+#define EXTI_Line11      ((uint32_t)0x00800)  /*!< External interrupt line 11 */
+#define EXTI_Line12      ((uint32_t)0x01000)  /*!< External interrupt line 12 */
+#define EXTI_Line13      ((uint32_t)0x02000)  /*!< External interrupt line 13 */
+#define EXTI_Line14      ((uint32_t)0x04000)  /*!< External interrupt line 14 */
+#define EXTI_Line15      ((uint32_t)0x08000)  /*!< External interrupt line 15 */
+#define EXTI_Line16      ((uint32_t)0x10000)  /*!< External interrupt line 16 Connected to the PVD Output */
+#define EXTI_Line17      ((uint32_t)0x20000)  /*!< External interrupt line 17 Connected to the RTC Alarm event */
+#define EXTI_Line18      ((uint32_t)0x40000)  /*!< External interrupt line 18 Connected to the USB Device/USB OTG FS
+                                                   Wakeup from suspend event */                                    
+#define EXTI_Line19      ((uint32_t)0x80000)  /*!< External interrupt line 19 Connected to the Ethernet Wakeup event */
+                                          
+#define IS_EXTI_LINE(LINE) ((((LINE) & (uint32_t)0xFFF00000) == 0x00) && ((LINE) != (uint16_t)0x00))
+#define IS_GET_EXTI_LINE(LINE) (((LINE) == EXTI_Line0) || ((LINE) == EXTI_Line1) || \
+                            ((LINE) == EXTI_Line2) || ((LINE) == EXTI_Line3) || \
+                            ((LINE) == EXTI_Line4) || ((LINE) == EXTI_Line5) || \
+                            ((LINE) == EXTI_Line6) || ((LINE) == EXTI_Line7) || \
+                            ((LINE) == EXTI_Line8) || ((LINE) == EXTI_Line9) || \
+                            ((LINE) == EXTI_Line10) || ((LINE) == EXTI_Line11) || \
+                            ((LINE) == EXTI_Line12) || ((LINE) == EXTI_Line13) || \
+                            ((LINE) == EXTI_Line14) || ((LINE) == EXTI_Line15) || \
+                            ((LINE) == EXTI_Line16) || ((LINE) == EXTI_Line17) || \
+                            ((LINE) == EXTI_Line18) || ((LINE) == EXTI_Line19))
+
+                    
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup EXTI_Exported_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup EXTI_Exported_Functions
+  * @{
+  */
+
+void EXTI_DeInit(void);
+void EXTI_Init(EXTI_InitTypeDef* EXTI_InitStruct);
+void EXTI_StructInit(EXTI_InitTypeDef* EXTI_InitStruct);
+void EXTI_GenerateSWInterrupt(uint32_t EXTI_Line);
+FlagStatus EXTI_GetFlagStatus(uint32_t EXTI_Line);
+void EXTI_ClearFlag(uint32_t EXTI_Line);
+ITStatus EXTI_GetITStatus(uint32_t EXTI_Line);
+void EXTI_ClearITPendingBit(uint32_t EXTI_Line);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F10x_EXTI_H */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/STM32_4路称重_Git提交精简工程/src/STM32F10x_FWLib/inc/stm32f10x_flash.h b/STM32_4路称重_Git提交精简工程/src/STM32F10x_FWLib/inc/stm32f10x_flash.h
new file mode 100755
index 0000000..f46d4e8
--- /dev/null
+++ b/STM32_4路称重_Git提交精简工程/src/STM32F10x_FWLib/inc/stm32f10x_flash.h
@@ -0,0 +1,426 @@
+/**
+  ******************************************************************************
+  * @file    stm32f10x_flash.h
+  * @author  MCD Application Team
+  * @version V3.5.0
+  * @date    11-March-2011
+  * @brief   This file contains all the functions prototypes for the FLASH 
+  *          firmware library.
+  ******************************************************************************
+  * @attention
+  *
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+  *
+  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F10x_FLASH_H
+#define __STM32F10x_FLASH_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x.h"
+
+/** @addtogroup STM32F10x_StdPeriph_Driver
+  * @{
+  */
+
+/** @addtogroup FLASH
+  * @{
+  */
+
+/** @defgroup FLASH_Exported_Types
+  * @{
+  */
+
+/** 
+  * @brief  FLASH Status  
+  */
+
+typedef enum
+{ 
+  FLASH_BUSY = 1,
+  FLASH_ERROR_PG,
+  FLASH_ERROR_WRP,
+  FLASH_COMPLETE,
+  FLASH_TIMEOUT
+}FLASH_Status;
+
+/**
+  * @}
+  */
+
+/** @defgroup FLASH_Exported_Constants
+  * @{
+  */
+
+/** @defgroup Flash_Latency 
+  * @{
+  */
+
+#define FLASH_Latency_0                ((uint32_t)0x00000000)  /*!< FLASH Zero Latency cycle */
+#define FLASH_Latency_1                ((uint32_t)0x00000001)  /*!< FLASH One Latency cycle */
+#define FLASH_Latency_2                ((uint32_t)0x00000002)  /*!< FLASH Two Latency cycles */
+#define IS_FLASH_LATENCY(LATENCY) (((LATENCY) == FLASH_Latency_0) || \
+                                   ((LATENCY) == FLASH_Latency_1) || \
+                                   ((LATENCY) == FLASH_Latency_2))
+/**
+  * @}
+  */
+
+/** @defgroup Half_Cycle_Enable_Disable 
+  * @{
+  */
+
+#define FLASH_HalfCycleAccess_Enable   ((uint32_t)0x00000008)  /*!< FLASH Half Cycle Enable */
+#define FLASH_HalfCycleAccess_Disable  ((uint32_t)0x00000000)  /*!< FLASH Half Cycle Disable */
+#define IS_FLASH_HALFCYCLEACCESS_STATE(STATE) (((STATE) == FLASH_HalfCycleAccess_Enable) || \
+                                               ((STATE) == FLASH_HalfCycleAccess_Disable)) 
+/**
+  * @}
+  */
+
+/** @defgroup Prefetch_Buffer_Enable_Disable 
+  * @{
+  */
+
+#define FLASH_PrefetchBuffer_Enable    ((uint32_t)0x00000010)  /*!< FLASH Prefetch Buffer Enable */
+#define FLASH_PrefetchBuffer_Disable   ((uint32_t)0x00000000)  /*!< FLASH Prefetch Buffer Disable */
+#define IS_FLASH_PREFETCHBUFFER_STATE(STATE) (((STATE) == FLASH_PrefetchBuffer_Enable) || \
+                                              ((STATE) == FLASH_PrefetchBuffer_Disable)) 
+/**
+  * @}
+  */
+
+/** @defgroup Option_Bytes_Write_Protection 
+  * @{
+  */
+
+/* Values to be used with STM32 Low and Medium density devices */
+#define FLASH_WRProt_Pages0to3         ((uint32_t)0x00000001) /*!< STM32 Low and Medium density devices: Write protection of page 0 to 3 */
+#define FLASH_WRProt_Pages4to7         ((uint32_t)0x00000002) /*!< STM32 Low and Medium density devices: Write protection of page 4 to 7 */
+#define FLASH_WRProt_Pages8to11        ((uint32_t)0x00000004) /*!< STM32 Low and Medium density devices: Write protection of page 8 to 11 */
+#define FLASH_WRProt_Pages12to15       ((uint32_t)0x00000008) /*!< STM32 Low and Medium density devices: Write protection of page 12 to 15 */
+#define FLASH_WRProt_Pages16to19       ((uint32_t)0x00000010) /*!< STM32 Low and Medium density devices: Write protection of page 16 to 19 */
+#define FLASH_WRProt_Pages20to23       ((uint32_t)0x00000020) /*!< STM32 Low and Medium density devices: Write protection of page 20 to 23 */
+#define FLASH_WRProt_Pages24to27       ((uint32_t)0x00000040) /*!< STM32 Low and Medium density devices: Write protection of page 24 to 27 */
+#define FLASH_WRProt_Pages28to31       ((uint32_t)0x00000080) /*!< STM32 Low and Medium density devices: Write protection of page 28 to 31 */
+
+/* Values to be used with STM32 Medium-density devices */
+#define FLASH_WRProt_Pages32to35       ((uint32_t)0x00000100) /*!< STM32 Medium-density devices: Write protection of page 32 to 35 */
+#define FLASH_WRProt_Pages36to39       ((uint32_t)0x00000200) /*!< STM32 Medium-density devices: Write protection of page 36 to 39 */
+#define FLASH_WRProt_Pages40to43       ((uint32_t)0x00000400) /*!< STM32 Medium-density devices: Write protection of page 40 to 43 */
+#define FLASH_WRProt_Pages44to47       ((uint32_t)0x00000800) /*!< STM32 Medium-density devices: Write protection of page 44 to 47 */
+#define FLASH_WRProt_Pages48to51       ((uint32_t)0x00001000) /*!< STM32 Medium-density devices: Write protection of page 48 to 51 */
+#define FLASH_WRProt_Pages52to55       ((uint32_t)0x00002000) /*!< STM32 Medium-density devices: Write protection of page 52 to 55 */
+#define FLASH_WRProt_Pages56to59       ((uint32_t)0x00004000) /*!< STM32 Medium-density devices: Write protection of page 56 to 59 */
+#define FLASH_WRProt_Pages60to63       ((uint32_t)0x00008000) /*!< STM32 Medium-density devices: Write protection of page 60 to 63 */
+#define FLASH_WRProt_Pages64to67       ((uint32_t)0x00010000) /*!< STM32 Medium-density devices: Write protection of page 64 to 67 */
+#define FLASH_WRProt_Pages68to71       ((uint32_t)0x00020000) /*!< STM32 Medium-density devices: Write protection of page 68 to 71 */
+#define FLASH_WRProt_Pages72to75       ((uint32_t)0x00040000) /*!< STM32 Medium-density devices: Write protection of page 72 to 75 */
+#define FLASH_WRProt_Pages76to79       ((uint32_t)0x00080000) /*!< STM32 Medium-density devices: Write protection of page 76 to 79 */
+#define FLASH_WRProt_Pages80to83       ((uint32_t)0x00100000) /*!< STM32 Medium-density devices: Write protection of page 80 to 83 */
+#define FLASH_WRProt_Pages84to87       ((uint32_t)0x00200000) /*!< STM32 Medium-density devices: Write protection of page 84 to 87 */
+#define FLASH_WRProt_Pages88to91       ((uint32_t)0x00400000) /*!< STM32 Medium-density devices: Write protection of page 88 to 91 */
+#define FLASH_WRProt_Pages92to95       ((uint32_t)0x00800000) /*!< STM32 Medium-density devices: Write protection of page 92 to 95 */
+#define FLASH_WRProt_Pages96to99       ((uint32_t)0x01000000) /*!< STM32 Medium-density devices: Write protection of page 96 to 99 */
+#define FLASH_WRProt_Pages100to103     ((uint32_t)0x02000000) /*!< STM32 Medium-density devices: Write protection of page 100 to 103 */
+#define FLASH_WRProt_Pages104to107     ((uint32_t)0x04000000) /*!< STM32 Medium-density devices: Write protection of page 104 to 107 */
+#define FLASH_WRProt_Pages108to111     ((uint32_t)0x08000000) /*!< STM32 Medium-density devices: Write protection of page 108 to 111 */
+#define FLASH_WRProt_Pages112to115     ((uint32_t)0x10000000) /*!< STM32 Medium-density devices: Write protection of page 112 to 115 */
+#define FLASH_WRProt_Pages116to119     ((uint32_t)0x20000000) /*!< STM32 Medium-density devices: Write protection of page 115 to 119 */
+#define FLASH_WRProt_Pages120to123     ((uint32_t)0x40000000) /*!< STM32 Medium-density devices: Write protection of page 120 to 123 */
+#define FLASH_WRProt_Pages124to127     ((uint32_t)0x80000000) /*!< STM32 Medium-density devices: Write protection of page 124 to 127 */
+
+/* Values to be used with STM32 High-density and STM32F10X Connectivity line devices */
+#define FLASH_WRProt_Pages0to1         ((uint32_t)0x00000001) /*!< STM32 High-density, XL-density and Connectivity line devices:
+                                                                   Write protection of page 0 to 1 */
+#define FLASH_WRProt_Pages2to3         ((uint32_t)0x00000002) /*!< STM32 High-density, XL-density and Connectivity line devices:
+                                                                   Write protection of page 2 to 3 */
+#define FLASH_WRProt_Pages4to5         ((uint32_t)0x00000004) /*!< STM32 High-density, XL-density and Connectivity line devices:
+                                                                   Write protection of page 4 to 5 */
+#define FLASH_WRProt_Pages6to7         ((uint32_t)0x00000008) /*!< STM32 High-density, XL-density and Connectivity line devices:
+                                                                   Write protection of page 6 to 7 */
+#define FLASH_WRProt_Pages8to9         ((uint32_t)0x00000010) /*!< STM32 High-density, XL-density and Connectivity line devices:
+                                                                   Write protection of page 8 to 9 */
+#define FLASH_WRProt_Pages10to11       ((uint32_t)0x00000020) /*!< STM32 High-density, XL-density and Connectivity line devices:
+                                                                   Write protection of page 10 to 11 */
+#define FLASH_WRProt_Pages12to13       ((uint32_t)0x00000040) /*!< STM32 High-density, XL-density and Connectivity line devices:
+                                                                   Write protection of page 12 to 13 */
+#define FLASH_WRProt_Pages14to15       ((uint32_t)0x00000080) /*!< STM32 High-density, XL-density and Connectivity line devices:
+                                                                   Write protection of page 14 to 15 */
+#define FLASH_WRProt_Pages16to17       ((uint32_t)0x00000100) /*!< STM32 High-density, XL-density and Connectivity line devices:
+                                                                   Write protection of page 16 to 17 */
+#define FLASH_WRProt_Pages18to19       ((uint32_t)0x00000200) /*!< STM32 High-density, XL-density and Connectivity line devices:
+                                                                   Write protection of page 18 to 19 */
+#define FLASH_WRProt_Pages20to21       ((uint32_t)0x00000400) /*!< STM32 High-density, XL-density and Connectivity line devices:
+                                                                   Write protection of page 20 to 21 */
+#define FLASH_WRProt_Pages22to23       ((uint32_t)0x00000800) /*!< STM32 High-density, XL-density and Connectivity line devices:
+                                                                   Write protection of page 22 to 23 */
+#define FLASH_WRProt_Pages24to25       ((uint32_t)0x00001000) /*!< STM32 High-density, XL-density and Connectivity line devices:
+                                                                   Write protection of page 24 to 25 */
+#define FLASH_WRProt_Pages26to27       ((uint32_t)0x00002000) /*!< STM32 High-density, XL-density and Connectivity line devices:
+                                                                   Write protection of page 26 to 27 */
+#define FLASH_WRProt_Pages28to29       ((uint32_t)0x00004000) /*!< STM32 High-density, XL-density and Connectivity line devices:
+                                                                   Write protection of page 28 to 29 */
+#define FLASH_WRProt_Pages30to31       ((uint32_t)0x00008000) /*!< STM32 High-density, XL-density and Connectivity line devices:
+                                                                   Write protection of page 30 to 31 */
+#define FLASH_WRProt_Pages32to33       ((uint32_t)0x00010000) /*!< STM32 High-density, XL-density and Connectivity line devices:
+                                                                   Write protection of page 32 to 33 */
+#define FLASH_WRProt_Pages34to35       ((uint32_t)0x00020000) /*!< STM32 High-density, XL-density and Connectivity line devices:
+                                                                   Write protection of page 34 to 35 */
+#define FLASH_WRProt_Pages36to37       ((uint32_t)0x00040000) /*!< STM32 High-density, XL-density and Connectivity line devices:
+                                                                   Write protection of page 36 to 37 */
+#define FLASH_WRProt_Pages38to39       ((uint32_t)0x00080000) /*!< STM32 High-density, XL-density and Connectivity line devices:
+                                                                   Write protection of page 38 to 39 */
+#define FLASH_WRProt_Pages40to41       ((uint32_t)0x00100000) /*!< STM32 High-density, XL-density and Connectivity line devices:
+                                                                   Write protection of page 40 to 41 */
+#define FLASH_WRProt_Pages42to43       ((uint32_t)0x00200000) /*!< STM32 High-density, XL-density and Connectivity line devices:
+                                                                   Write protection of page 42 to 43 */
+#define FLASH_WRProt_Pages44to45       ((uint32_t)0x00400000) /*!< STM32 High-density, XL-density and Connectivity line devices:
+                                                                   Write protection of page 44 to 45 */
+#define FLASH_WRProt_Pages46to47       ((uint32_t)0x00800000) /*!< STM32 High-density, XL-density and Connectivity line devices:
+                                                                   Write protection of page 46 to 47 */
+#define FLASH_WRProt_Pages48to49       ((uint32_t)0x01000000) /*!< STM32 High-density, XL-density and Connectivity line devices:
+                                                                   Write protection of page 48 to 49 */
+#define FLASH_WRProt_Pages50to51       ((uint32_t)0x02000000) /*!< STM32 High-density, XL-density and Connectivity line devices:
+                                                                   Write protection of page 50 to 51 */
+#define FLASH_WRProt_Pages52to53       ((uint32_t)0x04000000) /*!< STM32 High-density, XL-density and Connectivity line devices:
+                                                                   Write protection of page 52 to 53 */
+#define FLASH_WRProt_Pages54to55       ((uint32_t)0x08000000) /*!< STM32 High-density, XL-density and Connectivity line devices:
+                                                                   Write protection of page 54 to 55 */
+#define FLASH_WRProt_Pages56to57       ((uint32_t)0x10000000) /*!< STM32 High-density, XL-density and Connectivity line devices:
+                                                                   Write protection of page 56 to 57 */
+#define FLASH_WRProt_Pages58to59       ((uint32_t)0x20000000) /*!< STM32 High-density, XL-density and Connectivity line devices:
+                                                                   Write protection of page 58 to 59 */
+#define FLASH_WRProt_Pages60to61       ((uint32_t)0x40000000) /*!< STM32 High-density, XL-density and Connectivity line devices:
+                                                                   Write protection of page 60 to 61 */
+#define FLASH_WRProt_Pages62to127      ((uint32_t)0x80000000) /*!< STM32 Connectivity line devices: Write protection of page 62 to 127 */
+#define FLASH_WRProt_Pages62to255      ((uint32_t)0x80000000) /*!< STM32 Medium-density devices: Write protection of page 62 to 255 */
+#define FLASH_WRProt_Pages62to511      ((uint32_t)0x80000000) /*!< STM32 XL-density devices: Write protection of page 62 to 511 */
+
+#define FLASH_WRProt_AllPages          ((uint32_t)0xFFFFFFFF) /*!< Write protection of all Pages */
+
+#define IS_FLASH_WRPROT_PAGE(PAGE) (((PAGE) != 0x00000000))
+
+#define IS_FLASH_ADDRESS(ADDRESS) (((ADDRESS) >= 0x08000000) && ((ADDRESS) < 0x080FFFFF))
+
+#define IS_OB_DATA_ADDRESS(ADDRESS) (((ADDRESS) == 0x1FFFF804) || ((ADDRESS) == 0x1FFFF806))
+
+/**
+  * @}
+  */
+
+/** @defgroup Option_Bytes_IWatchdog 
+  * @{
+  */
+
+#define OB_IWDG_SW                     ((uint16_t)0x0001)  /*!< Software IWDG selected */
+#define OB_IWDG_HW                     ((uint16_t)0x0000)  /*!< Hardware IWDG selected */
+#define IS_OB_IWDG_SOURCE(SOURCE) (((SOURCE) == OB_IWDG_SW) || ((SOURCE) == OB_IWDG_HW))
+
+/**
+  * @}
+  */
+
+/** @defgroup Option_Bytes_nRST_STOP 
+  * @{
+  */
+
+#define OB_STOP_NoRST                  ((uint16_t)0x0002) /*!< No reset generated when entering in STOP */
+#define OB_STOP_RST                    ((uint16_t)0x0000) /*!< Reset generated when entering in STOP */
+#define IS_OB_STOP_SOURCE(SOURCE) (((SOURCE) == OB_STOP_NoRST) || ((SOURCE) == OB_STOP_RST))
+
+/**
+  * @}
+  */
+
+/** @defgroup Option_Bytes_nRST_STDBY 
+  * @{
+  */
+
+#define OB_STDBY_NoRST                 ((uint16_t)0x0004) /*!< No reset generated when entering in STANDBY */
+#define OB_STDBY_RST                   ((uint16_t)0x0000) /*!< Reset generated when entering in STANDBY */
+#define IS_OB_STDBY_SOURCE(SOURCE) (((SOURCE) == OB_STDBY_NoRST) || ((SOURCE) == OB_STDBY_RST))
+
+#ifdef STM32F10X_XL
+/**
+  * @}
+  */
+/** @defgroup FLASH_Boot
+  * @{
+  */
+#define FLASH_BOOT_Bank1  ((uint16_t)0x0000) /*!< At startup, if boot pins are set in boot from user Flash position
+                                                  and this parameter is selected the device will boot from Bank1(Default) */
+#define FLASH_BOOT_Bank2  ((uint16_t)0x0001) /*!< At startup, if boot pins are set in boot from user Flash position
+                                                  and this parameter is selected the device will boot from Bank 2 or Bank 1,
+                                                  depending on the activation of the bank */
+#define IS_FLASH_BOOT(BOOT) (((BOOT) == FLASH_BOOT_Bank1) || ((BOOT) == FLASH_BOOT_Bank2))
+#endif
+/**
+  * @}
+  */
+/** @defgroup FLASH_Interrupts 
+  * @{
+  */
+#ifdef STM32F10X_XL
+#define FLASH_IT_BANK2_ERROR                 ((uint32_t)0x80000400)  /*!< FPEC BANK2 error interrupt source */
+#define FLASH_IT_BANK2_EOP                   ((uint32_t)0x80001000)  /*!< End of FLASH BANK2 Operation Interrupt source */
+
+#define FLASH_IT_BANK1_ERROR                 FLASH_IT_ERROR          /*!< FPEC BANK1 error interrupt source */
+#define FLASH_IT_BANK1_EOP                   FLASH_IT_EOP            /*!< End of FLASH BANK1 Operation Interrupt source */
+
+#define FLASH_IT_ERROR                 ((uint32_t)0x00000400)  /*!< FPEC BANK1 error interrupt source */
+#define FLASH_IT_EOP                   ((uint32_t)0x00001000)  /*!< End of FLASH BANK1 Operation Interrupt source */
+#define IS_FLASH_IT(IT) ((((IT) & (uint32_t)0x7FFFEBFF) == 0x00000000) && (((IT) != 0x00000000)))
+#else
+#define FLASH_IT_ERROR                 ((uint32_t)0x00000400)  /*!< FPEC error interrupt source */
+#define FLASH_IT_EOP                   ((uint32_t)0x00001000)  /*!< End of FLASH Operation Interrupt source */
+#define FLASH_IT_BANK1_ERROR           FLASH_IT_ERROR          /*!< FPEC BANK1 error interrupt source */
+#define FLASH_IT_BANK1_EOP             FLASH_IT_EOP            /*!< End of FLASH BANK1 Operation Interrupt source */
+
+#define IS_FLASH_IT(IT) ((((IT) & (uint32_t)0xFFFFEBFF) == 0x00000000) && (((IT) != 0x00000000)))
+#endif
+
+/**
+  * @}
+  */
+
+/** @defgroup FLASH_Flags 
+  * @{
+  */
+#ifdef STM32F10X_XL
+#define FLASH_FLAG_BANK2_BSY                 ((uint32_t)0x80000001)  /*!< FLASH BANK2 Busy flag */
+#define FLASH_FLAG_BANK2_EOP                 ((uint32_t)0x80000020)  /*!< FLASH BANK2 End of Operation flag */
+#define FLASH_FLAG_BANK2_PGERR               ((uint32_t)0x80000004)  /*!< FLASH BANK2 Program error flag */
+#define FLASH_FLAG_BANK2_WRPRTERR            ((uint32_t)0x80000010)  /*!< FLASH BANK2 Write protected error flag */
+
+#define FLASH_FLAG_BANK1_BSY                 FLASH_FLAG_BSY       /*!< FLASH BANK1 Busy flag*/
+#define FLASH_FLAG_BANK1_EOP                 FLASH_FLAG_EOP       /*!< FLASH BANK1 End of Operation flag */
+#define FLASH_FLAG_BANK1_PGERR               FLASH_FLAG_PGERR     /*!< FLASH BANK1 Program error flag */
+#define FLASH_FLAG_BANK1_WRPRTERR            FLASH_FLAG_WRPRTERR  /*!< FLASH BANK1 Write protected error flag */
+
+#define FLASH_FLAG_BSY                 ((uint32_t)0x00000001)  /*!< FLASH Busy flag */
+#define FLASH_FLAG_EOP                 ((uint32_t)0x00000020)  /*!< FLASH End of Operation flag */
+#define FLASH_FLAG_PGERR               ((uint32_t)0x00000004)  /*!< FLASH Program error flag */
+#define FLASH_FLAG_WRPRTERR            ((uint32_t)0x00000010)  /*!< FLASH Write protected error flag */
+#define FLASH_FLAG_OPTERR              ((uint32_t)0x00000001)  /*!< FLASH Option Byte error flag */
+ 
+#define IS_FLASH_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0x7FFFFFCA) == 0x00000000) && ((FLAG) != 0x00000000))
+#define IS_FLASH_GET_FLAG(FLAG)  (((FLAG) == FLASH_FLAG_BSY) || ((FLAG) == FLASH_FLAG_EOP) || \
+                                  ((FLAG) == FLASH_FLAG_PGERR) || ((FLAG) == FLASH_FLAG_WRPRTERR) || \
+                                  ((FLAG) == FLASH_FLAG_OPTERR)|| \
+                                  ((FLAG) == FLASH_FLAG_BANK1_BSY) || ((FLAG) == FLASH_FLAG_BANK1_EOP) || \
+                                  ((FLAG) == FLASH_FLAG_BANK1_PGERR) || ((FLAG) == FLASH_FLAG_BANK1_WRPRTERR) || \
+                                  ((FLAG) == FLASH_FLAG_BANK2_BSY) || ((FLAG) == FLASH_FLAG_BANK2_EOP) || \
+                                  ((FLAG) == FLASH_FLAG_BANK2_PGERR) || ((FLAG) == FLASH_FLAG_BANK2_WRPRTERR))
+#else
+#define FLASH_FLAG_BSY                 ((uint32_t)0x00000001)  /*!< FLASH Busy flag */
+#define FLASH_FLAG_EOP                 ((uint32_t)0x00000020)  /*!< FLASH End of Operation flag */
+#define FLASH_FLAG_PGERR               ((uint32_t)0x00000004)  /*!< FLASH Program error flag */
+#define FLASH_FLAG_WRPRTERR            ((uint32_t)0x00000010)  /*!< FLASH Write protected error flag */
+#define FLASH_FLAG_OPTERR              ((uint32_t)0x00000001)  /*!< FLASH Option Byte error flag */
+
+#define FLASH_FLAG_BANK1_BSY                 FLASH_FLAG_BSY       /*!< FLASH BANK1 Busy flag*/
+#define FLASH_FLAG_BANK1_EOP                 FLASH_FLAG_EOP       /*!< FLASH BANK1 End of Operation flag */
+#define FLASH_FLAG_BANK1_PGERR               FLASH_FLAG_PGERR     /*!< FLASH BANK1 Program error flag */
+#define FLASH_FLAG_BANK1_WRPRTERR            FLASH_FLAG_WRPRTERR  /*!< FLASH BANK1 Write protected error flag */
+ 
+#define IS_FLASH_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFFFFCA) == 0x00000000) && ((FLAG) != 0x00000000))
+#define IS_FLASH_GET_FLAG(FLAG)  (((FLAG) == FLASH_FLAG_BSY) || ((FLAG) == FLASH_FLAG_EOP) || \
+                                  ((FLAG) == FLASH_FLAG_PGERR) || ((FLAG) == FLASH_FLAG_WRPRTERR) || \
+								  ((FLAG) == FLASH_FLAG_BANK1_BSY) || ((FLAG) == FLASH_FLAG_BANK1_EOP) || \
+                                  ((FLAG) == FLASH_FLAG_BANK1_PGERR) || ((FLAG) == FLASH_FLAG_BANK1_WRPRTERR) || \
+                                  ((FLAG) == FLASH_FLAG_OPTERR))
+#endif
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup FLASH_Exported_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup FLASH_Exported_Functions
+  * @{
+  */
+
+/*------------ Functions used for all STM32F10x devices -----*/
+void FLASH_SetLatency(uint32_t FLASH_Latency);
+void FLASH_HalfCycleAccessCmd(uint32_t FLASH_HalfCycleAccess);
+void FLASH_PrefetchBufferCmd(uint32_t FLASH_PrefetchBuffer);
+void FLASH_Unlock(void);
+void FLASH_Lock(void);
+FLASH_Status FLASH_ErasePage(uint32_t Page_Address);
+FLASH_Status FLASH_EraseAllPages(void);
+FLASH_Status FLASH_EraseOptionBytes(void);
+FLASH_Status FLASH_ProgramWord(uint32_t Address, uint32_t Data);
+FLASH_Status FLASH_ProgramHalfWord(uint32_t Address, uint16_t Data);
+FLASH_Status FLASH_ProgramOptionByteData(uint32_t Address, uint8_t Data);
+FLASH_Status FLASH_EnableWriteProtection(uint32_t FLASH_Pages);
+FLASH_Status FLASH_ReadOutProtection(FunctionalState NewState);
+FLASH_Status FLASH_UserOptionByteConfig(uint16_t OB_IWDG, uint16_t OB_STOP, uint16_t OB_STDBY);
+uint32_t FLASH_GetUserOptionByte(void);
+uint32_t FLASH_GetWriteProtectionOptionByte(void);
+FlagStatus FLASH_GetReadOutProtectionStatus(void);
+FlagStatus FLASH_GetPrefetchBufferStatus(void);
+void FLASH_ITConfig(uint32_t FLASH_IT, FunctionalState NewState);
+FlagStatus FLASH_GetFlagStatus(uint32_t FLASH_FLAG);
+void FLASH_ClearFlag(uint32_t FLASH_FLAG);
+FLASH_Status FLASH_GetStatus(void);
+FLASH_Status FLASH_WaitForLastOperation(uint32_t Timeout);
+
+/*------------ New function used for all STM32F10x devices -----*/
+void FLASH_UnlockBank1(void);
+void FLASH_LockBank1(void);
+FLASH_Status FLASH_EraseAllBank1Pages(void);
+FLASH_Status FLASH_GetBank1Status(void);
+FLASH_Status FLASH_WaitForLastBank1Operation(uint32_t Timeout);
+
+#ifdef STM32F10X_XL
+/*---- New Functions used only with STM32F10x_XL density devices -----*/
+void FLASH_UnlockBank2(void);
+void FLASH_LockBank2(void);
+FLASH_Status FLASH_EraseAllBank2Pages(void);
+FLASH_Status FLASH_GetBank2Status(void);
+FLASH_Status FLASH_WaitForLastBank2Operation(uint32_t Timeout);
+FLASH_Status FLASH_BootConfig(uint16_t FLASH_BOOT);
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F10x_FLASH_H */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/STM32_4路称重_Git提交精简工程/src/STM32F10x_FWLib/inc/stm32f10x_fsmc.h b/STM32_4路称重_Git提交精简工程/src/STM32F10x_FWLib/inc/stm32f10x_fsmc.h
new file mode 100755
index 0000000..ee707e7
--- /dev/null
+++ b/STM32_4路称重_Git提交精简工程/src/STM32F10x_FWLib/inc/stm32f10x_fsmc.h
@@ -0,0 +1,733 @@
+/**
+  ******************************************************************************
+  * @file    stm32f10x_fsmc.h
+  * @author  MCD Application Team
+  * @version V3.5.0
+  * @date    11-March-2011
+  * @brief   This file contains all the functions prototypes for the FSMC firmware 
+  *          library.
+  ******************************************************************************
+  * @attention
+  *
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+  *
+  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F10x_FSMC_H
+#define __STM32F10x_FSMC_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x.h"
+
+/** @addtogroup STM32F10x_StdPeriph_Driver
+  * @{
+  */
+
+/** @addtogroup FSMC
+  * @{
+  */
+
+/** @defgroup FSMC_Exported_Types
+  * @{
+  */
+
+/** 
+  * @brief  Timing parameters For NOR/SRAM Banks  
+  */
+
+typedef struct
+{
+  uint32_t FSMC_AddressSetupTime;       /*!< Defines the number of HCLK cycles to configure
+                                             the duration of the address setup time. 
+                                             This parameter can be a value between 0 and 0xF.
+                                             @note: It is not used with synchronous NOR Flash memories. */
+
+  uint32_t FSMC_AddressHoldTime;        /*!< Defines the number of HCLK cycles to configure
+                                             the duration of the address hold time.
+                                             This parameter can be a value between 0 and 0xF. 
+                                             @note: It is not used with synchronous NOR Flash memories.*/
+
+  uint32_t FSMC_DataSetupTime;          /*!< Defines the number of HCLK cycles to configure
+                                             the duration of the data setup time.
+                                             This parameter can be a value between 0 and 0xFF.
+                                             @note: It is used for SRAMs, ROMs and asynchronous multiplexed NOR Flash memories. */
+
+  uint32_t FSMC_BusTurnAroundDuration;  /*!< Defines the number of HCLK cycles to configure
+                                             the duration of the bus turnaround.
+                                             This parameter can be a value between 0 and 0xF.
+                                             @note: It is only used for multiplexed NOR Flash memories. */
+
+  uint32_t FSMC_CLKDivision;            /*!< Defines the period of CLK clock output signal, expressed in number of HCLK cycles.
+                                             This parameter can be a value between 1 and 0xF.
+                                             @note: This parameter is not used for asynchronous NOR Flash, SRAM or ROM accesses. */
+
+  uint32_t FSMC_DataLatency;            /*!< Defines the number of memory clock cycles to issue
+                                             to the memory before getting the first data.
+                                             The value of this parameter depends on the memory type as shown below:
+                                              - It must be set to 0 in case of a CRAM
+                                              - It is don't care in asynchronous NOR, SRAM or ROM accesses
+                                              - It may assume a value between 0 and 0xF in NOR Flash memories
+                                                with synchronous burst mode enable */
+
+  uint32_t FSMC_AccessMode;             /*!< Specifies the asynchronous access mode. 
+                                             This parameter can be a value of @ref FSMC_Access_Mode */
+}FSMC_NORSRAMTimingInitTypeDef;
+
+/** 
+  * @brief  FSMC NOR/SRAM Init structure definition
+  */
+
+typedef struct
+{
+  uint32_t FSMC_Bank;                /*!< Specifies the NOR/SRAM memory bank that will be used.
+                                          This parameter can be a value of @ref FSMC_NORSRAM_Bank */
+
+  uint32_t FSMC_DataAddressMux;      /*!< Specifies whether the address and data values are
+                                          multiplexed on the databus or not. 
+                                          This parameter can be a value of @ref FSMC_Data_Address_Bus_Multiplexing */
+
+  uint32_t FSMC_MemoryType;          /*!< Specifies the type of external memory attached to
+                                          the corresponding memory bank.
+                                          This parameter can be a value of @ref FSMC_Memory_Type */
+
+  uint32_t FSMC_MemoryDataWidth;     /*!< Specifies the external memory device width.
+                                          This parameter can be a value of @ref FSMC_Data_Width */
+
+  uint32_t FSMC_BurstAccessMode;     /*!< Enables or disables the burst access mode for Flash memory,
+                                          valid only with synchronous burst Flash memories.
+                                          This parameter can be a value of @ref FSMC_Burst_Access_Mode */
+                                       
+  uint32_t FSMC_AsynchronousWait;     /*!< Enables or disables wait signal during asynchronous transfers,
+                                          valid only with asynchronous Flash memories.
+                                          This parameter can be a value of @ref FSMC_AsynchronousWait */
+
+  uint32_t FSMC_WaitSignalPolarity;  /*!< Specifies the wait signal polarity, valid only when accessing
+                                          the Flash memory in burst mode.
+                                          This parameter can be a value of @ref FSMC_Wait_Signal_Polarity */
+
+  uint32_t FSMC_WrapMode;            /*!< Enables or disables the Wrapped burst access mode for Flash
+                                          memory, valid only when accessing Flash memories in burst mode.
+                                          This parameter can be a value of @ref FSMC_Wrap_Mode */
+
+  uint32_t FSMC_WaitSignalActive;    /*!< Specifies if the wait signal is asserted by the memory one
+                                          clock cycle before the wait state or during the wait state,
+                                          valid only when accessing memories in burst mode. 
+                                          This parameter can be a value of @ref FSMC_Wait_Timing */
+
+  uint32_t FSMC_WriteOperation;      /*!< Enables or disables the write operation in the selected bank by the FSMC. 
+                                          This parameter can be a value of @ref FSMC_Write_Operation */
+
+  uint32_t FSMC_WaitSignal;          /*!< Enables or disables the wait-state insertion via wait
+                                          signal, valid for Flash memory access in burst mode. 
+                                          This parameter can be a value of @ref FSMC_Wait_Signal */
+
+  uint32_t FSMC_ExtendedMode;        /*!< Enables or disables the extended mode.
+                                          This parameter can be a value of @ref FSMC_Extended_Mode */
+
+  uint32_t FSMC_WriteBurst;          /*!< Enables or disables the write burst operation.
+                                          This parameter can be a value of @ref FSMC_Write_Burst */ 
+
+  FSMC_NORSRAMTimingInitTypeDef* FSMC_ReadWriteTimingStruct; /*!< Timing Parameters for write and read access if the  ExtendedMode is not used*/  
+
+  FSMC_NORSRAMTimingInitTypeDef* FSMC_WriteTimingStruct;     /*!< Timing Parameters for write access if the  ExtendedMode is used*/      
+}FSMC_NORSRAMInitTypeDef;
+
+/** 
+  * @brief  Timing parameters For FSMC NAND and PCCARD Banks
+  */
+
+typedef struct
+{
+  uint32_t FSMC_SetupTime;      /*!< Defines the number of HCLK cycles to setup address before
+                                     the command assertion for NAND-Flash read or write access
+                                     to common/Attribute or I/O memory space (depending on
+                                     the memory space timing to be configured).
+                                     This parameter can be a value between 0 and 0xFF.*/
+
+  uint32_t FSMC_WaitSetupTime;  /*!< Defines the minimum number of HCLK cycles to assert the
+                                     command for NAND-Flash read or write access to
+                                     common/Attribute or I/O memory space (depending on the
+                                     memory space timing to be configured). 
+                                     This parameter can be a number between 0x00 and 0xFF */
+
+  uint32_t FSMC_HoldSetupTime;  /*!< Defines the number of HCLK clock cycles to hold address
+                                     (and data for write access) after the command deassertion
+                                     for NAND-Flash read or write access to common/Attribute
+                                     or I/O memory space (depending on the memory space timing
+                                     to be configured).
+                                     This parameter can be a number between 0x00 and 0xFF */
+
+  uint32_t FSMC_HiZSetupTime;   /*!< Defines the number of HCLK clock cycles during which the
+                                     databus is kept in HiZ after the start of a NAND-Flash
+                                     write access to common/Attribute or I/O memory space (depending
+                                     on the memory space timing to be configured).
+                                     This parameter can be a number between 0x00 and 0xFF */
+}FSMC_NAND_PCCARDTimingInitTypeDef;
+
+/** 
+  * @brief  FSMC NAND Init structure definition
+  */
+
+typedef struct
+{
+  uint32_t FSMC_Bank;              /*!< Specifies the NAND memory bank that will be used.
+                                      This parameter can be a value of @ref FSMC_NAND_Bank */
+
+  uint32_t FSMC_Waitfeature;      /*!< Enables or disables the Wait feature for the NAND Memory Bank.
+                                       This parameter can be any value of @ref FSMC_Wait_feature */
+
+  uint32_t FSMC_MemoryDataWidth;  /*!< Specifies the external memory device width.
+                                       This parameter can be any value of @ref FSMC_Data_Width */
+
+  uint32_t FSMC_ECC;              /*!< Enables or disables the ECC computation.
+                                       This parameter can be any value of @ref FSMC_ECC */
+
+  uint32_t FSMC_ECCPageSize;      /*!< Defines the page size for the extended ECC.
+                                       This parameter can be any value of @ref FSMC_ECC_Page_Size */
+
+  uint32_t FSMC_TCLRSetupTime;    /*!< Defines the number of HCLK cycles to configure the
+                                       delay between CLE low and RE low.
+                                       This parameter can be a value between 0 and 0xFF. */
+
+  uint32_t FSMC_TARSetupTime;     /*!< Defines the number of HCLK cycles to configure the
+                                       delay between ALE low and RE low.
+                                       This parameter can be a number between 0x0 and 0xFF */ 
+
+  FSMC_NAND_PCCARDTimingInitTypeDef*  FSMC_CommonSpaceTimingStruct;   /*!< FSMC Common Space Timing */ 
+
+  FSMC_NAND_PCCARDTimingInitTypeDef*  FSMC_AttributeSpaceTimingStruct; /*!< FSMC Attribute Space Timing */
+}FSMC_NANDInitTypeDef;
+
+/** 
+  * @brief  FSMC PCCARD Init structure definition
+  */
+
+typedef struct
+{
+  uint32_t FSMC_Waitfeature;    /*!< Enables or disables the Wait feature for the Memory Bank.
+                                    This parameter can be any value of @ref FSMC_Wait_feature */
+
+  uint32_t FSMC_TCLRSetupTime;  /*!< Defines the number of HCLK cycles to configure the
+                                     delay between CLE low and RE low.
+                                     This parameter can be a value between 0 and 0xFF. */
+
+  uint32_t FSMC_TARSetupTime;   /*!< Defines the number of HCLK cycles to configure the
+                                     delay between ALE low and RE low.
+                                     This parameter can be a number between 0x0 and 0xFF */ 
+
+  
+  FSMC_NAND_PCCARDTimingInitTypeDef*  FSMC_CommonSpaceTimingStruct; /*!< FSMC Common Space Timing */
+
+  FSMC_NAND_PCCARDTimingInitTypeDef*  FSMC_AttributeSpaceTimingStruct;  /*!< FSMC Attribute Space Timing */ 
+  
+  FSMC_NAND_PCCARDTimingInitTypeDef*  FSMC_IOSpaceTimingStruct; /*!< FSMC IO Space Timing */  
+}FSMC_PCCARDInitTypeDef;
+
+/**
+  * @}
+  */
+
+/** @defgroup FSMC_Exported_Constants
+  * @{
+  */
+
+/** @defgroup FSMC_NORSRAM_Bank 
+  * @{
+  */
+#define FSMC_Bank1_NORSRAM1                             ((uint32_t)0x00000000)
+#define FSMC_Bank1_NORSRAM2                             ((uint32_t)0x00000002)
+#define FSMC_Bank1_NORSRAM3                             ((uint32_t)0x00000004)
+#define FSMC_Bank1_NORSRAM4                             ((uint32_t)0x00000006)
+/**
+  * @}
+  */
+
+/** @defgroup FSMC_NAND_Bank 
+  * @{
+  */  
+#define FSMC_Bank2_NAND                                 ((uint32_t)0x00000010)
+#define FSMC_Bank3_NAND                                 ((uint32_t)0x00000100)
+/**
+  * @}
+  */
+
+/** @defgroup FSMC_PCCARD_Bank 
+  * @{
+  */    
+#define FSMC_Bank4_PCCARD                               ((uint32_t)0x00001000)
+/**
+  * @}
+  */
+
+#define IS_FSMC_NORSRAM_BANK(BANK) (((BANK) == FSMC_Bank1_NORSRAM1) || \
+                                    ((BANK) == FSMC_Bank1_NORSRAM2) || \
+                                    ((BANK) == FSMC_Bank1_NORSRAM3) || \
+                                    ((BANK) == FSMC_Bank1_NORSRAM4))
+
+#define IS_FSMC_NAND_BANK(BANK) (((BANK) == FSMC_Bank2_NAND) || \
+                                 ((BANK) == FSMC_Bank3_NAND))
+
+#define IS_FSMC_GETFLAG_BANK(BANK) (((BANK) == FSMC_Bank2_NAND) || \
+                                    ((BANK) == FSMC_Bank3_NAND) || \
+                                    ((BANK) == FSMC_Bank4_PCCARD))
+
+#define IS_FSMC_IT_BANK(BANK) (((BANK) == FSMC_Bank2_NAND) || \
+                               ((BANK) == FSMC_Bank3_NAND) || \
+                               ((BANK) == FSMC_Bank4_PCCARD))
+
+/** @defgroup NOR_SRAM_Controller 
+  * @{
+  */
+
+/** @defgroup FSMC_Data_Address_Bus_Multiplexing 
+  * @{
+  */
+
+#define FSMC_DataAddressMux_Disable                       ((uint32_t)0x00000000)
+#define FSMC_DataAddressMux_Enable                        ((uint32_t)0x00000002)
+#define IS_FSMC_MUX(MUX) (((MUX) == FSMC_DataAddressMux_Disable) || \
+                          ((MUX) == FSMC_DataAddressMux_Enable))
+
+/**
+  * @}
+  */
+
+/** @defgroup FSMC_Memory_Type 
+  * @{
+  */
+
+#define FSMC_MemoryType_SRAM                            ((uint32_t)0x00000000)
+#define FSMC_MemoryType_PSRAM                           ((uint32_t)0x00000004)
+#define FSMC_MemoryType_NOR                             ((uint32_t)0x00000008)
+#define IS_FSMC_MEMORY(MEMORY) (((MEMORY) == FSMC_MemoryType_SRAM) || \
+                                ((MEMORY) == FSMC_MemoryType_PSRAM)|| \
+                                ((MEMORY) == FSMC_MemoryType_NOR))
+
+/**
+  * @}
+  */
+
+/** @defgroup FSMC_Data_Width 
+  * @{
+  */
+
+#define FSMC_MemoryDataWidth_8b                         ((uint32_t)0x00000000)
+#define FSMC_MemoryDataWidth_16b                        ((uint32_t)0x00000010)
+#define IS_FSMC_MEMORY_WIDTH(WIDTH) (((WIDTH) == FSMC_MemoryDataWidth_8b) || \
+                                     ((WIDTH) == FSMC_MemoryDataWidth_16b))
+
+/**
+  * @}
+  */
+
+/** @defgroup FSMC_Burst_Access_Mode 
+  * @{
+  */
+
+#define FSMC_BurstAccessMode_Disable                    ((uint32_t)0x00000000) 
+#define FSMC_BurstAccessMode_Enable                     ((uint32_t)0x00000100)
+#define IS_FSMC_BURSTMODE(STATE) (((STATE) == FSMC_BurstAccessMode_Disable) || \
+                                  ((STATE) == FSMC_BurstAccessMode_Enable))
+/**
+  * @}
+  */
+  
+/** @defgroup FSMC_AsynchronousWait 
+  * @{
+  */
+#define FSMC_AsynchronousWait_Disable                   ((uint32_t)0x00000000)
+#define FSMC_AsynchronousWait_Enable                    ((uint32_t)0x00008000)
+#define IS_FSMC_ASYNWAIT(STATE) (((STATE) == FSMC_AsynchronousWait_Disable) || \
+                                 ((STATE) == FSMC_AsynchronousWait_Enable))
+
+/**
+  * @}
+  */
+  
+/** @defgroup FSMC_Wait_Signal_Polarity 
+  * @{
+  */
+
+#define FSMC_WaitSignalPolarity_Low                     ((uint32_t)0x00000000)
+#define FSMC_WaitSignalPolarity_High                    ((uint32_t)0x00000200)
+#define IS_FSMC_WAIT_POLARITY(POLARITY) (((POLARITY) == FSMC_WaitSignalPolarity_Low) || \
+                                         ((POLARITY) == FSMC_WaitSignalPolarity_High)) 
+
+/**
+  * @}
+  */
+
+/** @defgroup FSMC_Wrap_Mode 
+  * @{
+  */
+
+#define FSMC_WrapMode_Disable                           ((uint32_t)0x00000000)
+#define FSMC_WrapMode_Enable                            ((uint32_t)0x00000400) 
+#define IS_FSMC_WRAP_MODE(MODE) (((MODE) == FSMC_WrapMode_Disable) || \
+                                 ((MODE) == FSMC_WrapMode_Enable))
+
+/**
+  * @}
+  */
+
+/** @defgroup FSMC_Wait_Timing 
+  * @{
+  */
+
+#define FSMC_WaitSignalActive_BeforeWaitState           ((uint32_t)0x00000000)
+#define FSMC_WaitSignalActive_DuringWaitState           ((uint32_t)0x00000800) 
+#define IS_FSMC_WAIT_SIGNAL_ACTIVE(ACTIVE) (((ACTIVE) == FSMC_WaitSignalActive_BeforeWaitState) || \
+                                            ((ACTIVE) == FSMC_WaitSignalActive_DuringWaitState))
+
+/**
+  * @}
+  */
+
+/** @defgroup FSMC_Write_Operation 
+  * @{
+  */
+
+#define FSMC_WriteOperation_Disable                     ((uint32_t)0x00000000)
+#define FSMC_WriteOperation_Enable                      ((uint32_t)0x00001000)
+#define IS_FSMC_WRITE_OPERATION(OPERATION) (((OPERATION) == FSMC_WriteOperation_Disable) || \
+                                            ((OPERATION) == FSMC_WriteOperation_Enable))
+                              
+/**
+  * @}
+  */
+
+/** @defgroup FSMC_Wait_Signal 
+  * @{
+  */
+
+#define FSMC_WaitSignal_Disable                         ((uint32_t)0x00000000)
+#define FSMC_WaitSignal_Enable                          ((uint32_t)0x00002000) 
+#define IS_FSMC_WAITE_SIGNAL(SIGNAL) (((SIGNAL) == FSMC_WaitSignal_Disable) || \
+                                      ((SIGNAL) == FSMC_WaitSignal_Enable))
+/**
+  * @}
+  */
+
+/** @defgroup FSMC_Extended_Mode 
+  * @{
+  */
+
+#define FSMC_ExtendedMode_Disable                       ((uint32_t)0x00000000)
+#define FSMC_ExtendedMode_Enable                        ((uint32_t)0x00004000)
+
+#define IS_FSMC_EXTENDED_MODE(MODE) (((MODE) == FSMC_ExtendedMode_Disable) || \
+                                     ((MODE) == FSMC_ExtendedMode_Enable)) 
+
+/**
+  * @}
+  */
+
+/** @defgroup FSMC_Write_Burst 
+  * @{
+  */
+
+#define FSMC_WriteBurst_Disable                         ((uint32_t)0x00000000)
+#define FSMC_WriteBurst_Enable                          ((uint32_t)0x00080000) 
+#define IS_FSMC_WRITE_BURST(BURST) (((BURST) == FSMC_WriteBurst_Disable) || \
+                                    ((BURST) == FSMC_WriteBurst_Enable))
+/**
+  * @}
+  */
+
+/** @defgroup FSMC_Address_Setup_Time 
+  * @{
+  */
+
+#define IS_FSMC_ADDRESS_SETUP_TIME(TIME) ((TIME) <= 0xF)
+
+/**
+  * @}
+  */
+
+/** @defgroup FSMC_Address_Hold_Time 
+  * @{
+  */
+
+#define IS_FSMC_ADDRESS_HOLD_TIME(TIME) ((TIME) <= 0xF)
+
+/**
+  * @}
+  */
+
+/** @defgroup FSMC_Data_Setup_Time 
+  * @{
+  */
+
+#define IS_FSMC_DATASETUP_TIME(TIME) (((TIME) > 0) && ((TIME) <= 0xFF))
+
+/**
+  * @}
+  */
+
+/** @defgroup FSMC_Bus_Turn_around_Duration 
+  * @{
+  */
+
+#define IS_FSMC_TURNAROUND_TIME(TIME) ((TIME) <= 0xF)
+
+/**
+  * @}
+  */
+
+/** @defgroup FSMC_CLK_Division 
+  * @{
+  */
+
+#define IS_FSMC_CLK_DIV(DIV) ((DIV) <= 0xF)
+
+/**
+  * @}
+  */
+
+/** @defgroup FSMC_Data_Latency 
+  * @{
+  */
+
+#define IS_FSMC_DATA_LATENCY(LATENCY) ((LATENCY) <= 0xF)
+
+/**
+  * @}
+  */
+
+/** @defgroup FSMC_Access_Mode 
+  * @{
+  */
+
+#define FSMC_AccessMode_A                               ((uint32_t)0x00000000)
+#define FSMC_AccessMode_B                               ((uint32_t)0x10000000) 
+#define FSMC_AccessMode_C                               ((uint32_t)0x20000000)
+#define FSMC_AccessMode_D                               ((uint32_t)0x30000000)
+#define IS_FSMC_ACCESS_MODE(MODE) (((MODE) == FSMC_AccessMode_A) || \
+                                   ((MODE) == FSMC_AccessMode_B) || \
+                                   ((MODE) == FSMC_AccessMode_C) || \
+                                   ((MODE) == FSMC_AccessMode_D)) 
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+  
+/** @defgroup NAND_PCCARD_Controller 
+  * @{
+  */
+
+/** @defgroup FSMC_Wait_feature 
+  * @{
+  */
+
+#define FSMC_Waitfeature_Disable                        ((uint32_t)0x00000000)
+#define FSMC_Waitfeature_Enable                         ((uint32_t)0x00000002)
+#define IS_FSMC_WAIT_FEATURE(FEATURE) (((FEATURE) == FSMC_Waitfeature_Disable) || \
+                                       ((FEATURE) == FSMC_Waitfeature_Enable))
+
+/**
+  * @}
+  */
+
+
+/** @defgroup FSMC_ECC 
+  * @{
+  */
+
+#define FSMC_ECC_Disable                                ((uint32_t)0x00000000)
+#define FSMC_ECC_Enable                                 ((uint32_t)0x00000040)
+#define IS_FSMC_ECC_STATE(STATE) (((STATE) == FSMC_ECC_Disable) || \
+                                  ((STATE) == FSMC_ECC_Enable))
+
+/**
+  * @}
+  */
+
+/** @defgroup FSMC_ECC_Page_Size 
+  * @{
+  */
+
+#define FSMC_ECCPageSize_256Bytes                       ((uint32_t)0x00000000)
+#define FSMC_ECCPageSize_512Bytes                       ((uint32_t)0x00020000)
+#define FSMC_ECCPageSize_1024Bytes                      ((uint32_t)0x00040000)
+#define FSMC_ECCPageSize_2048Bytes                      ((uint32_t)0x00060000)
+#define FSMC_ECCPageSize_4096Bytes                      ((uint32_t)0x00080000)
+#define FSMC_ECCPageSize_8192Bytes                      ((uint32_t)0x000A0000)
+#define IS_FSMC_ECCPAGE_SIZE(SIZE) (((SIZE) == FSMC_ECCPageSize_256Bytes) || \
+                                    ((SIZE) == FSMC_ECCPageSize_512Bytes) || \
+                                    ((SIZE) == FSMC_ECCPageSize_1024Bytes) || \
+                                    ((SIZE) == FSMC_ECCPageSize_2048Bytes) || \
+                                    ((SIZE) == FSMC_ECCPageSize_4096Bytes) || \
+                                    ((SIZE) == FSMC_ECCPageSize_8192Bytes))
+
+/**
+  * @}
+  */
+
+/** @defgroup FSMC_TCLR_Setup_Time 
+  * @{
+  */
+
+#define IS_FSMC_TCLR_TIME(TIME) ((TIME) <= 0xFF)
+
+/**
+  * @}
+  */
+
+/** @defgroup FSMC_TAR_Setup_Time 
+  * @{
+  */
+
+#define IS_FSMC_TAR_TIME(TIME) ((TIME) <= 0xFF)
+
+/**
+  * @}
+  */
+
+/** @defgroup FSMC_Setup_Time 
+  * @{
+  */
+
+#define IS_FSMC_SETUP_TIME(TIME) ((TIME) <= 0xFF)
+
+/**
+  * @}
+  */
+
+/** @defgroup FSMC_Wait_Setup_Time 
+  * @{
+  */
+
+#define IS_FSMC_WAIT_TIME(TIME) ((TIME) <= 0xFF)
+
+/**
+  * @}
+  */
+
+/** @defgroup FSMC_Hold_Setup_Time 
+  * @{
+  */
+
+#define IS_FSMC_HOLD_TIME(TIME) ((TIME) <= 0xFF)
+
+/**
+  * @}
+  */
+
+/** @defgroup FSMC_HiZ_Setup_Time 
+  * @{
+  */
+
+#define IS_FSMC_HIZ_TIME(TIME) ((TIME) <= 0xFF)
+
+/**
+  * @}
+  */
+
+/** @defgroup FSMC_Interrupt_sources 
+  * @{
+  */
+
+#define FSMC_IT_RisingEdge                              ((uint32_t)0x00000008)
+#define FSMC_IT_Level                                   ((uint32_t)0x00000010)
+#define FSMC_IT_FallingEdge                             ((uint32_t)0x00000020)
+#define IS_FSMC_IT(IT) ((((IT) & (uint32_t)0xFFFFFFC7) == 0x00000000) && ((IT) != 0x00000000))
+#define IS_FSMC_GET_IT(IT) (((IT) == FSMC_IT_RisingEdge) || \
+                            ((IT) == FSMC_IT_Level) || \
+                            ((IT) == FSMC_IT_FallingEdge)) 
+/**
+  * @}
+  */
+
+/** @defgroup FSMC_Flags 
+  * @{
+  */
+
+#define FSMC_FLAG_RisingEdge                            ((uint32_t)0x00000001)
+#define FSMC_FLAG_Level                                 ((uint32_t)0x00000002)
+#define FSMC_FLAG_FallingEdge                           ((uint32_t)0x00000004)
+#define FSMC_FLAG_FEMPT                                 ((uint32_t)0x00000040)
+#define IS_FSMC_GET_FLAG(FLAG) (((FLAG) == FSMC_FLAG_RisingEdge) || \
+                                ((FLAG) == FSMC_FLAG_Level) || \
+                                ((FLAG) == FSMC_FLAG_FallingEdge) || \
+                                ((FLAG) == FSMC_FLAG_FEMPT))
+
+#define IS_FSMC_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFFFFF8) == 0x00000000) && ((FLAG) != 0x00000000))
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup FSMC_Exported_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup FSMC_Exported_Functions
+  * @{
+  */
+
+void FSMC_NORSRAMDeInit(uint32_t FSMC_Bank);
+void FSMC_NANDDeInit(uint32_t FSMC_Bank);
+void FSMC_PCCARDDeInit(void);
+void FSMC_NORSRAMInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct);
+void FSMC_NANDInit(FSMC_NANDInitTypeDef* FSMC_NANDInitStruct);
+void FSMC_PCCARDInit(FSMC_PCCARDInitTypeDef* FSMC_PCCARDInitStruct);
+void FSMC_NORSRAMStructInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct);
+void FSMC_NANDStructInit(FSMC_NANDInitTypeDef* FSMC_NANDInitStruct);
+void FSMC_PCCARDStructInit(FSMC_PCCARDInitTypeDef* FSMC_PCCARDInitStruct);
+void FSMC_NORSRAMCmd(uint32_t FSMC_Bank, FunctionalState NewState);
+void FSMC_NANDCmd(uint32_t FSMC_Bank, FunctionalState NewState);
+void FSMC_PCCARDCmd(FunctionalState NewState);
+void FSMC_NANDECCCmd(uint32_t FSMC_Bank, FunctionalState NewState);
+uint32_t FSMC_GetECC(uint32_t FSMC_Bank);
+void FSMC_ITConfig(uint32_t FSMC_Bank, uint32_t FSMC_IT, FunctionalState NewState);
+FlagStatus FSMC_GetFlagStatus(uint32_t FSMC_Bank, uint32_t FSMC_FLAG);
+void FSMC_ClearFlag(uint32_t FSMC_Bank, uint32_t FSMC_FLAG);
+ITStatus FSMC_GetITStatus(uint32_t FSMC_Bank, uint32_t FSMC_IT);
+void FSMC_ClearITPendingBit(uint32_t FSMC_Bank, uint32_t FSMC_IT);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__STM32F10x_FSMC_H */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */ 
+
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/STM32_4路称重_Git提交精简工程/src/STM32F10x_FWLib/inc/stm32f10x_gpio.h b/STM32_4路称重_Git提交精简工程/src/STM32F10x_FWLib/inc/stm32f10x_gpio.h
new file mode 100755
index 0000000..b8aa49a
--- /dev/null
+++ b/STM32_4路称重_Git提交精简工程/src/STM32F10x_FWLib/inc/stm32f10x_gpio.h
@@ -0,0 +1,385 @@
+/**
+  ******************************************************************************
+  * @file    stm32f10x_gpio.h
+  * @author  MCD Application Team
+  * @version V3.5.0
+  * @date    11-March-2011
+  * @brief   This file contains all the functions prototypes for the GPIO 
+  *          firmware library.
+  ******************************************************************************
+  * @attention
+  *
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+  *
+  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F10x_GPIO_H
+#define __STM32F10x_GPIO_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x.h"
+
+/** @addtogroup STM32F10x_StdPeriph_Driver
+  * @{
+  */
+
+/** @addtogroup GPIO
+  * @{
+  */
+
+/** @defgroup GPIO_Exported_Types
+  * @{
+  */
+
+#define IS_GPIO_ALL_PERIPH(PERIPH) (((PERIPH) == GPIOA) || \
+                                    ((PERIPH) == GPIOB) || \
+                                    ((PERIPH) == GPIOC) || \
+                                    ((PERIPH) == GPIOD) || \
+                                    ((PERIPH) == GPIOE) || \
+                                    ((PERIPH) == GPIOF) || \
+                                    ((PERIPH) == GPIOG))
+                                     
+/** 
+  * @brief  Output Maximum frequency selection  
+  */
+
+typedef enum
+{ 
+  GPIO_Speed_10MHz = 1,
+  GPIO_Speed_2MHz, 
+  GPIO_Speed_50MHz
+}GPIOSpeed_TypeDef;
+#define IS_GPIO_SPEED(SPEED) (((SPEED) == GPIO_Speed_10MHz) || ((SPEED) == GPIO_Speed_2MHz) || \
+                              ((SPEED) == GPIO_Speed_50MHz))
+
+/** 
+  * @brief  Configuration Mode enumeration  
+  */
+
+typedef enum
+{ GPIO_Mode_AIN = 0x0,
+  GPIO_Mode_IN_FLOATING = 0x04,
+  GPIO_Mode_IPD = 0x28,
+  GPIO_Mode_IPU = 0x48,
+  GPIO_Mode_Out_OD = 0x14,
+  GPIO_Mode_Out_PP = 0x10,
+  GPIO_Mode_AF_OD = 0x1C,
+  GPIO_Mode_AF_PP = 0x18
+}GPIOMode_TypeDef;
+
+#define IS_GPIO_MODE(MODE) (((MODE) == GPIO_Mode_AIN) || ((MODE) == GPIO_Mode_IN_FLOATING) || \
+                            ((MODE) == GPIO_Mode_IPD) || ((MODE) == GPIO_Mode_IPU) || \
+                            ((MODE) == GPIO_Mode_Out_OD) || ((MODE) == GPIO_Mode_Out_PP) || \
+                            ((MODE) == GPIO_Mode_AF_OD) || ((MODE) == GPIO_Mode_AF_PP))
+
+/** 
+  * @brief  GPIO Init structure definition  
+  */
+
+typedef struct
+{
+  uint16_t GPIO_Pin;             /*!< Specifies the GPIO pins to be configured.
+                                      This parameter can be any value of @ref GPIO_pins_define */
+
+  GPIOSpeed_TypeDef GPIO_Speed;  /*!< Specifies the speed for the selected pins.
+                                      This parameter can be a value of @ref GPIOSpeed_TypeDef */
+
+  GPIOMode_TypeDef GPIO_Mode;    /*!< Specifies the operating mode for the selected pins.
+                                      This parameter can be a value of @ref GPIOMode_TypeDef */
+}GPIO_InitTypeDef;
+
+
+/** 
+  * @brief  Bit_SET and Bit_RESET enumeration  
+  */
+
+typedef enum
+{ Bit_RESET = 0,
+  Bit_SET
+}BitAction;
+
+#define IS_GPIO_BIT_ACTION(ACTION) (((ACTION) == Bit_RESET) || ((ACTION) == Bit_SET))
+
+/**
+  * @}
+  */
+
+/** @defgroup GPIO_Exported_Constants
+  * @{
+  */
+
+/** @defgroup GPIO_pins_define 
+  * @{
+  */
+
+#define GPIO_Pin_0                 ((uint16_t)0x0001)  /*!< Pin 0 selected */
+#define GPIO_Pin_1                 ((uint16_t)0x0002)  /*!< Pin 1 selected */
+#define GPIO_Pin_2                 ((uint16_t)0x0004)  /*!< Pin 2 selected */
+#define GPIO_Pin_3                 ((uint16_t)0x0008)  /*!< Pin 3 selected */
+#define GPIO_Pin_4                 ((uint16_t)0x0010)  /*!< Pin 4 selected */
+#define GPIO_Pin_5                 ((uint16_t)0x0020)  /*!< Pin 5 selected */
+#define GPIO_Pin_6                 ((uint16_t)0x0040)  /*!< Pin 6 selected */
+#define GPIO_Pin_7                 ((uint16_t)0x0080)  /*!< Pin 7 selected */
+#define GPIO_Pin_8                 ((uint16_t)0x0100)  /*!< Pin 8 selected */
+#define GPIO_Pin_9                 ((uint16_t)0x0200)  /*!< Pin 9 selected */
+#define GPIO_Pin_10                ((uint16_t)0x0400)  /*!< Pin 10 selected */
+#define GPIO_Pin_11                ((uint16_t)0x0800)  /*!< Pin 11 selected */
+#define GPIO_Pin_12                ((uint16_t)0x1000)  /*!< Pin 12 selected */
+#define GPIO_Pin_13                ((uint16_t)0x2000)  /*!< Pin 13 selected */
+#define GPIO_Pin_14                ((uint16_t)0x4000)  /*!< Pin 14 selected */
+#define GPIO_Pin_15                ((uint16_t)0x8000)  /*!< Pin 15 selected */
+#define GPIO_Pin_All               ((uint16_t)0xFFFF)  /*!< All pins selected */
+
+#define IS_GPIO_PIN(PIN) ((((PIN) & (uint16_t)0x00) == 0x00) && ((PIN) != (uint16_t)0x00))
+
+#define IS_GET_GPIO_PIN(PIN) (((PIN) == GPIO_Pin_0) || \
+                              ((PIN) == GPIO_Pin_1) || \
+                              ((PIN) == GPIO_Pin_2) || \
+                              ((PIN) == GPIO_Pin_3) || \
+                              ((PIN) == GPIO_Pin_4) || \
+                              ((PIN) == GPIO_Pin_5) || \
+                              ((PIN) == GPIO_Pin_6) || \
+                              ((PIN) == GPIO_Pin_7) || \
+                              ((PIN) == GPIO_Pin_8) || \
+                              ((PIN) == GPIO_Pin_9) || \
+                              ((PIN) == GPIO_Pin_10) || \
+                              ((PIN) == GPIO_Pin_11) || \
+                              ((PIN) == GPIO_Pin_12) || \
+                              ((PIN) == GPIO_Pin_13) || \
+                              ((PIN) == GPIO_Pin_14) || \
+                              ((PIN) == GPIO_Pin_15))
+
+/**
+  * @}
+  */
+
+/** @defgroup GPIO_Remap_define 
+  * @{
+  */
+
+#define GPIO_Remap_SPI1             ((uint32_t)0x00000001)  /*!< SPI1 Alternate Function mapping */
+#define GPIO_Remap_I2C1             ((uint32_t)0x00000002)  /*!< I2C1 Alternate Function mapping */
+#define GPIO_Remap_USART1           ((uint32_t)0x00000004)  /*!< USART1 Alternate Function mapping */
+#define GPIO_Remap_USART2           ((uint32_t)0x00000008)  /*!< USART2 Alternate Function mapping */
+#define GPIO_PartialRemap_USART3    ((uint32_t)0x00140010)  /*!< USART3 Partial Alternate Function mapping */
+#define GPIO_FullRemap_USART3       ((uint32_t)0x00140030)  /*!< USART3 Full Alternate Function mapping */
+#define GPIO_PartialRemap_TIM1      ((uint32_t)0x00160040)  /*!< TIM1 Partial Alternate Function mapping */
+#define GPIO_FullRemap_TIM1         ((uint32_t)0x001600C0)  /*!< TIM1 Full Alternate Function mapping */
+#define GPIO_PartialRemap1_TIM2     ((uint32_t)0x00180100)  /*!< TIM2 Partial1 Alternate Function mapping */
+#define GPIO_PartialRemap2_TIM2     ((uint32_t)0x00180200)  /*!< TIM2 Partial2 Alternate Function mapping */
+#define GPIO_FullRemap_TIM2         ((uint32_t)0x00180300)  /*!< TIM2 Full Alternate Function mapping */
+#define GPIO_PartialRemap_TIM3      ((uint32_t)0x001A0800)  /*!< TIM3 Partial Alternate Function mapping */
+#define GPIO_FullRemap_TIM3         ((uint32_t)0x001A0C00)  /*!< TIM3 Full Alternate Function mapping */
+#define GPIO_Remap_TIM4             ((uint32_t)0x00001000)  /*!< TIM4 Alternate Function mapping */
+#define GPIO_Remap1_CAN1            ((uint32_t)0x001D4000)  /*!< CAN1 Alternate Function mapping */
+#define GPIO_Remap2_CAN1            ((uint32_t)0x001D6000)  /*!< CAN1 Alternate Function mapping */
+#define GPIO_Remap_PD01             ((uint32_t)0x00008000)  /*!< PD01 Alternate Function mapping */
+#define GPIO_Remap_TIM5CH4_LSI      ((uint32_t)0x00200001)  /*!< LSI connected to TIM5 Channel4 input capture for calibration */
+#define GPIO_Remap_ADC1_ETRGINJ     ((uint32_t)0x00200002)  /*!< ADC1 External Trigger Injected Conversion remapping */
+#define GPIO_Remap_ADC1_ETRGREG     ((uint32_t)0x00200004)  /*!< ADC1 External Trigger Regular Conversion remapping */
+#define GPIO_Remap_ADC2_ETRGINJ     ((uint32_t)0x00200008)  /*!< ADC2 External Trigger Injected Conversion remapping */
+#define GPIO_Remap_ADC2_ETRGREG     ((uint32_t)0x00200010)  /*!< ADC2 External Trigger Regular Conversion remapping */
+#define GPIO_Remap_ETH              ((uint32_t)0x00200020)  /*!< Ethernet remapping (only for Connectivity line devices) */
+#define GPIO_Remap_CAN2             ((uint32_t)0x00200040)  /*!< CAN2 remapping (only for Connectivity line devices) */
+#define GPIO_Remap_SWJ_NoJTRST      ((uint32_t)0x00300100)  /*!< Full SWJ Enabled (JTAG-DP + SW-DP) but without JTRST */
+#define GPIO_Remap_SWJ_JTAGDisable  ((uint32_t)0x00300200)  /*!< JTAG-DP Disabled and SW-DP Enabled */
+#define GPIO_Remap_SWJ_Disable      ((uint32_t)0x00300400)  /*!< Full SWJ Disabled (JTAG-DP + SW-DP) */
+#define GPIO_Remap_SPI3             ((uint32_t)0x00201100)  /*!< SPI3/I2S3 Alternate Function mapping (only for Connectivity line devices) */
+#define GPIO_Remap_TIM2ITR1_PTP_SOF ((uint32_t)0x00202000)  /*!< Ethernet PTP output or USB OTG SOF (Start of Frame) connected
+                                                                 to TIM2 Internal Trigger 1 for calibration
+                                                                 (only for Connectivity line devices) */
+#define GPIO_Remap_PTP_PPS          ((uint32_t)0x00204000)  /*!< Ethernet MAC PPS_PTS output on PB05 (only for Connectivity line devices) */
+
+#define GPIO_Remap_TIM15            ((uint32_t)0x80000001)  /*!< TIM15 Alternate Function mapping (only for Value line devices) */
+#define GPIO_Remap_TIM16            ((uint32_t)0x80000002)  /*!< TIM16 Alternate Function mapping (only for Value line devices) */
+#define GPIO_Remap_TIM17            ((uint32_t)0x80000004)  /*!< TIM17 Alternate Function mapping (only for Value line devices) */
+#define GPIO_Remap_CEC              ((uint32_t)0x80000008)  /*!< CEC Alternate Function mapping (only for Value line devices) */
+#define GPIO_Remap_TIM1_DMA         ((uint32_t)0x80000010)  /*!< TIM1 DMA requests mapping (only for Value line devices) */
+
+#define GPIO_Remap_TIM9             ((uint32_t)0x80000020)  /*!< TIM9 Alternate Function mapping (only for XL-density devices) */
+#define GPIO_Remap_TIM10            ((uint32_t)0x80000040)  /*!< TIM10 Alternate Function mapping (only for XL-density devices) */
+#define GPIO_Remap_TIM11            ((uint32_t)0x80000080)  /*!< TIM11 Alternate Function mapping (only for XL-density devices) */
+#define GPIO_Remap_TIM13            ((uint32_t)0x80000100)  /*!< TIM13 Alternate Function mapping (only for High density Value line and XL-density devices) */
+#define GPIO_Remap_TIM14            ((uint32_t)0x80000200)  /*!< TIM14 Alternate Function mapping (only for High density Value line and XL-density devices) */
+#define GPIO_Remap_FSMC_NADV        ((uint32_t)0x80000400)  /*!< FSMC_NADV Alternate Function mapping (only for High density Value line and XL-density devices) */
+
+#define GPIO_Remap_TIM67_DAC_DMA    ((uint32_t)0x80000800)  /*!< TIM6/TIM7 and DAC DMA requests remapping (only for High density Value line devices) */
+#define GPIO_Remap_TIM12            ((uint32_t)0x80001000)  /*!< TIM12 Alternate Function mapping (only for High density Value line devices) */
+#define GPIO_Remap_MISC             ((uint32_t)0x80002000)  /*!< Miscellaneous Remap (DMA2 Channel5 Position and DAC Trigger remapping, 
+                                                                 only for High density Value line devices) */                                                       
+
+#define IS_GPIO_REMAP(REMAP) (((REMAP) == GPIO_Remap_SPI1) || ((REMAP) == GPIO_Remap_I2C1) || \
+                              ((REMAP) == GPIO_Remap_USART1) || ((REMAP) == GPIO_Remap_USART2) || \
+                              ((REMAP) == GPIO_PartialRemap_USART3) || ((REMAP) == GPIO_FullRemap_USART3) || \
+                              ((REMAP) == GPIO_PartialRemap_TIM1) || ((REMAP) == GPIO_FullRemap_TIM1) || \
+                              ((REMAP) == GPIO_PartialRemap1_TIM2) || ((REMAP) == GPIO_PartialRemap2_TIM2) || \
+                              ((REMAP) == GPIO_FullRemap_TIM2) || ((REMAP) == GPIO_PartialRemap_TIM3) || \
+                              ((REMAP) == GPIO_FullRemap_TIM3) || ((REMAP) == GPIO_Remap_TIM4) || \
+                              ((REMAP) == GPIO_Remap1_CAN1) || ((REMAP) == GPIO_Remap2_CAN1) || \
+                              ((REMAP) == GPIO_Remap_PD01) || ((REMAP) == GPIO_Remap_TIM5CH4_LSI) || \
+                              ((REMAP) == GPIO_Remap_ADC1_ETRGINJ) ||((REMAP) == GPIO_Remap_ADC1_ETRGREG) || \
+                              ((REMAP) == GPIO_Remap_ADC2_ETRGINJ) ||((REMAP) == GPIO_Remap_ADC2_ETRGREG) || \
+                              ((REMAP) == GPIO_Remap_ETH) ||((REMAP) == GPIO_Remap_CAN2) || \
+                              ((REMAP) == GPIO_Remap_SWJ_NoJTRST) || ((REMAP) == GPIO_Remap_SWJ_JTAGDisable) || \
+                              ((REMAP) == GPIO_Remap_SWJ_Disable)|| ((REMAP) == GPIO_Remap_SPI3) || \
+                              ((REMAP) == GPIO_Remap_TIM2ITR1_PTP_SOF) || ((REMAP) == GPIO_Remap_PTP_PPS) || \
+                              ((REMAP) == GPIO_Remap_TIM15) || ((REMAP) == GPIO_Remap_TIM16) || \
+                              ((REMAP) == GPIO_Remap_TIM17) || ((REMAP) == GPIO_Remap_CEC) || \
+                              ((REMAP) == GPIO_Remap_TIM1_DMA) || ((REMAP) == GPIO_Remap_TIM9) || \
+                              ((REMAP) == GPIO_Remap_TIM10) || ((REMAP) == GPIO_Remap_TIM11) || \
+                              ((REMAP) == GPIO_Remap_TIM13) || ((REMAP) == GPIO_Remap_TIM14) || \
+                              ((REMAP) == GPIO_Remap_FSMC_NADV) || ((REMAP) == GPIO_Remap_TIM67_DAC_DMA) || \
+                              ((REMAP) == GPIO_Remap_TIM12) || ((REMAP) == GPIO_Remap_MISC))
+                              
+/**
+  * @}
+  */ 
+
+/** @defgroup GPIO_Port_Sources 
+  * @{
+  */
+
+#define GPIO_PortSourceGPIOA       ((uint8_t)0x00)
+#define GPIO_PortSourceGPIOB       ((uint8_t)0x01)
+#define GPIO_PortSourceGPIOC       ((uint8_t)0x02)
+#define GPIO_PortSourceGPIOD       ((uint8_t)0x03)
+#define GPIO_PortSourceGPIOE       ((uint8_t)0x04)
+#define GPIO_PortSourceGPIOF       ((uint8_t)0x05)
+#define GPIO_PortSourceGPIOG       ((uint8_t)0x06)
+#define IS_GPIO_EVENTOUT_PORT_SOURCE(PORTSOURCE) (((PORTSOURCE) == GPIO_PortSourceGPIOA) || \
+                                                  ((PORTSOURCE) == GPIO_PortSourceGPIOB) || \
+                                                  ((PORTSOURCE) == GPIO_PortSourceGPIOC) || \
+                                                  ((PORTSOURCE) == GPIO_PortSourceGPIOD) || \
+                                                  ((PORTSOURCE) == GPIO_PortSourceGPIOE))
+
+#define IS_GPIO_EXTI_PORT_SOURCE(PORTSOURCE) (((PORTSOURCE) == GPIO_PortSourceGPIOA) || \
+                                              ((PORTSOURCE) == GPIO_PortSourceGPIOB) || \
+                                              ((PORTSOURCE) == GPIO_PortSourceGPIOC) || \
+                                              ((PORTSOURCE) == GPIO_PortSourceGPIOD) || \
+                                              ((PORTSOURCE) == GPIO_PortSourceGPIOE) || \
+                                              ((PORTSOURCE) == GPIO_PortSourceGPIOF) || \
+                                              ((PORTSOURCE) == GPIO_PortSourceGPIOG))
+
+/**
+  * @}
+  */
+
+/** @defgroup GPIO_Pin_sources 
+  * @{
+  */
+
+#define GPIO_PinSource0            ((uint8_t)0x00)
+#define GPIO_PinSource1            ((uint8_t)0x01)
+#define GPIO_PinSource2            ((uint8_t)0x02)
+#define GPIO_PinSource3            ((uint8_t)0x03)
+#define GPIO_PinSource4            ((uint8_t)0x04)
+#define GPIO_PinSource5            ((uint8_t)0x05)
+#define GPIO_PinSource6            ((uint8_t)0x06)
+#define GPIO_PinSource7            ((uint8_t)0x07)
+#define GPIO_PinSource8            ((uint8_t)0x08)
+#define GPIO_PinSource9            ((uint8_t)0x09)
+#define GPIO_PinSource10           ((uint8_t)0x0A)
+#define GPIO_PinSource11           ((uint8_t)0x0B)
+#define GPIO_PinSource12           ((uint8_t)0x0C)
+#define GPIO_PinSource13           ((uint8_t)0x0D)
+#define GPIO_PinSource14           ((uint8_t)0x0E)
+#define GPIO_PinSource15           ((uint8_t)0x0F)
+
+#define IS_GPIO_PIN_SOURCE(PINSOURCE) (((PINSOURCE) == GPIO_PinSource0) || \
+                                       ((PINSOURCE) == GPIO_PinSource1) || \
+                                       ((PINSOURCE) == GPIO_PinSource2) || \
+                                       ((PINSOURCE) == GPIO_PinSource3) || \
+                                       ((PINSOURCE) == GPIO_PinSource4) || \
+                                       ((PINSOURCE) == GPIO_PinSource5) || \
+                                       ((PINSOURCE) == GPIO_PinSource6) || \
+                                       ((PINSOURCE) == GPIO_PinSource7) || \
+                                       ((PINSOURCE) == GPIO_PinSource8) || \
+                                       ((PINSOURCE) == GPIO_PinSource9) || \
+                                       ((PINSOURCE) == GPIO_PinSource10) || \
+                                       ((PINSOURCE) == GPIO_PinSource11) || \
+                                       ((PINSOURCE) == GPIO_PinSource12) || \
+                                       ((PINSOURCE) == GPIO_PinSource13) || \
+                                       ((PINSOURCE) == GPIO_PinSource14) || \
+                                       ((PINSOURCE) == GPIO_PinSource15))
+
+/**
+  * @}
+  */
+
+/** @defgroup Ethernet_Media_Interface 
+  * @{
+  */ 
+#define GPIO_ETH_MediaInterface_MII    ((u32)0x00000000) 
+#define GPIO_ETH_MediaInterface_RMII   ((u32)0x00000001)                                       
+
+#define IS_GPIO_ETH_MEDIA_INTERFACE(INTERFACE) (((INTERFACE) == GPIO_ETH_MediaInterface_MII) || \
+                                                ((INTERFACE) == GPIO_ETH_MediaInterface_RMII))
+
+/**
+  * @}
+  */                                                
+/**
+  * @}
+  */
+
+/** @defgroup GPIO_Exported_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup GPIO_Exported_Functions
+  * @{
+  */
+
+void GPIO_DeInit(GPIO_TypeDef* GPIOx);
+void GPIO_AFIODeInit(void);
+void GPIO_Init(GPIO_TypeDef* GPIOx, GPIO_InitTypeDef* GPIO_InitStruct);
+void GPIO_StructInit(GPIO_InitTypeDef* GPIO_InitStruct);
+uint8_t GPIO_ReadInputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
+uint16_t GPIO_ReadInputData(GPIO_TypeDef* GPIOx);
+uint8_t GPIO_ReadOutputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
+uint16_t GPIO_ReadOutputData(GPIO_TypeDef* GPIOx);
+void GPIO_SetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
+void GPIO_ResetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
+void GPIO_WriteBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, BitAction BitVal);
+void GPIO_Write(GPIO_TypeDef* GPIOx, uint16_t PortVal);
+void GPIO_PinLockConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
+void GPIO_EventOutputConfig(uint8_t GPIO_PortSource, uint8_t GPIO_PinSource);
+void GPIO_EventOutputCmd(FunctionalState NewState);
+void GPIO_PinRemapConfig(uint32_t GPIO_Remap, FunctionalState NewState);
+void GPIO_EXTILineConfig(uint8_t GPIO_PortSource, uint8_t GPIO_PinSource);
+void GPIO_ETH_MediaInterfaceConfig(uint32_t GPIO_ETH_MediaInterface);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F10x_GPIO_H */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/STM32_4路称重_Git提交精简工程/src/STM32F10x_FWLib/inc/stm32f10x_i2c.h b/STM32_4路称重_Git提交精简工程/src/STM32F10x_FWLib/inc/stm32f10x_i2c.h
new file mode 100755
index 0000000..2d42e5c
--- /dev/null
+++ b/STM32_4路称重_Git提交精简工程/src/STM32F10x_FWLib/inc/stm32f10x_i2c.h
@@ -0,0 +1,684 @@
+/**
+  ******************************************************************************
+  * @file    stm32f10x_i2c.h
+  * @author  MCD Application Team
+  * @version V3.5.0
+  * @date    11-March-2011
+  * @brief   This file contains all the functions prototypes for the I2C firmware 
+  *          library.
+  ******************************************************************************
+  * @attention
+  *
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+  *
+  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F10x_I2C_H
+#define __STM32F10x_I2C_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x.h"
+
+/** @addtogroup STM32F10x_StdPeriph_Driver
+  * @{
+  */
+
+/** @addtogroup I2C
+  * @{
+  */
+
+/** @defgroup I2C_Exported_Types
+  * @{
+  */
+
+/** 
+  * @brief  I2C Init structure definition  
+  */
+
+typedef struct
+{
+  uint32_t I2C_ClockSpeed;          /*!< Specifies the clock frequency.
+                                         This parameter must be set to a value lower than 400kHz */
+
+  uint16_t I2C_Mode;                /*!< Specifies the I2C mode.
+                                         This parameter can be a value of @ref I2C_mode */
+
+  uint16_t I2C_DutyCycle;           /*!< Specifies the I2C fast mode duty cycle.
+                                         This parameter can be a value of @ref I2C_duty_cycle_in_fast_mode */
+
+  uint16_t I2C_OwnAddress1;         /*!< Specifies the first device own address.
+                                         This parameter can be a 7-bit or 10-bit address. */
+
+  uint16_t I2C_Ack;                 /*!< Enables or disables the acknowledgement.
+                                         This parameter can be a value of @ref I2C_acknowledgement */
+
+  uint16_t I2C_AcknowledgedAddress; /*!< Specifies if 7-bit or 10-bit address is acknowledged.
+                                         This parameter can be a value of @ref I2C_acknowledged_address */
+}I2C_InitTypeDef;
+
+/**
+  * @}
+  */ 
+
+
+/** @defgroup I2C_Exported_Constants
+  * @{
+  */
+
+#define IS_I2C_ALL_PERIPH(PERIPH) (((PERIPH) == I2C1) || \
+                                   ((PERIPH) == I2C2))
+/** @defgroup I2C_mode 
+  * @{
+  */
+
+#define I2C_Mode_I2C                    ((uint16_t)0x0000)
+#define I2C_Mode_SMBusDevice            ((uint16_t)0x0002)  
+#define I2C_Mode_SMBusHost              ((uint16_t)0x000A)
+#define IS_I2C_MODE(MODE) (((MODE) == I2C_Mode_I2C) || \
+                           ((MODE) == I2C_Mode_SMBusDevice) || \
+                           ((MODE) == I2C_Mode_SMBusHost))
+/**
+  * @}
+  */
+
+/** @defgroup I2C_duty_cycle_in_fast_mode 
+  * @{
+  */
+
+#define I2C_DutyCycle_16_9              ((uint16_t)0x4000) /*!< I2C fast mode Tlow/Thigh = 16/9 */
+#define I2C_DutyCycle_2                 ((uint16_t)0xBFFF) /*!< I2C fast mode Tlow/Thigh = 2 */
+#define IS_I2C_DUTY_CYCLE(CYCLE) (((CYCLE) == I2C_DutyCycle_16_9) || \
+                                  ((CYCLE) == I2C_DutyCycle_2))
+/**
+  * @}
+  */ 
+
+/** @defgroup I2C_acknowledgement
+  * @{
+  */
+
+#define I2C_Ack_Enable                  ((uint16_t)0x0400)
+#define I2C_Ack_Disable                 ((uint16_t)0x0000)
+#define IS_I2C_ACK_STATE(STATE) (((STATE) == I2C_Ack_Enable) || \
+                                 ((STATE) == I2C_Ack_Disable))
+/**
+  * @}
+  */
+
+/** @defgroup I2C_transfer_direction 
+  * @{
+  */
+
+#define  I2C_Direction_Transmitter      ((uint8_t)0x00)
+#define  I2C_Direction_Receiver         ((uint8_t)0x01)
+#define IS_I2C_DIRECTION(DIRECTION) (((DIRECTION) == I2C_Direction_Transmitter) || \
+                                     ((DIRECTION) == I2C_Direction_Receiver))
+/**
+  * @}
+  */
+
+/** @defgroup I2C_acknowledged_address 
+  * @{
+  */
+
+#define I2C_AcknowledgedAddress_7bit    ((uint16_t)0x4000)
+#define I2C_AcknowledgedAddress_10bit   ((uint16_t)0xC000)
+#define IS_I2C_ACKNOWLEDGE_ADDRESS(ADDRESS) (((ADDRESS) == I2C_AcknowledgedAddress_7bit) || \
+                                             ((ADDRESS) == I2C_AcknowledgedAddress_10bit))
+/**
+  * @}
+  */ 
+
+/** @defgroup I2C_registers 
+  * @{
+  */
+
+#define I2C_Register_CR1                ((uint8_t)0x00)
+#define I2C_Register_CR2                ((uint8_t)0x04)
+#define I2C_Register_OAR1               ((uint8_t)0x08)
+#define I2C_Register_OAR2               ((uint8_t)0x0C)
+#define I2C_Register_DR                 ((uint8_t)0x10)
+#define I2C_Register_SR1                ((uint8_t)0x14)
+#define I2C_Register_SR2                ((uint8_t)0x18)
+#define I2C_Register_CCR                ((uint8_t)0x1C)
+#define I2C_Register_TRISE              ((uint8_t)0x20)
+#define IS_I2C_REGISTER(REGISTER) (((REGISTER) == I2C_Register_CR1) || \
+                                   ((REGISTER) == I2C_Register_CR2) || \
+                                   ((REGISTER) == I2C_Register_OAR1) || \
+                                   ((REGISTER) == I2C_Register_OAR2) || \
+                                   ((REGISTER) == I2C_Register_DR) || \
+                                   ((REGISTER) == I2C_Register_SR1) || \
+                                   ((REGISTER) == I2C_Register_SR2) || \
+                                   ((REGISTER) == I2C_Register_CCR) || \
+                                   ((REGISTER) == I2C_Register_TRISE))
+/**
+  * @}
+  */
+
+/** @defgroup I2C_SMBus_alert_pin_level 
+  * @{
+  */
+
+#define I2C_SMBusAlert_Low              ((uint16_t)0x2000)
+#define I2C_SMBusAlert_High             ((uint16_t)0xDFFF)
+#define IS_I2C_SMBUS_ALERT(ALERT) (((ALERT) == I2C_SMBusAlert_Low) || \
+                                   ((ALERT) == I2C_SMBusAlert_High))
+/**
+  * @}
+  */
+
+/** @defgroup I2C_PEC_position 
+  * @{
+  */
+
+#define I2C_PECPosition_Next            ((uint16_t)0x0800)
+#define I2C_PECPosition_Current         ((uint16_t)0xF7FF)
+#define IS_I2C_PEC_POSITION(POSITION) (((POSITION) == I2C_PECPosition_Next) || \
+                                       ((POSITION) == I2C_PECPosition_Current))
+/**
+  * @}
+  */ 
+
+/** @defgroup I2C_NCAK_position 
+  * @{
+  */
+
+#define I2C_NACKPosition_Next           ((uint16_t)0x0800)
+#define I2C_NACKPosition_Current        ((uint16_t)0xF7FF)
+#define IS_I2C_NACK_POSITION(POSITION)  (((POSITION) == I2C_NACKPosition_Next) || \
+                                         ((POSITION) == I2C_NACKPosition_Current))
+/**
+  * @}
+  */ 
+
+/** @defgroup I2C_interrupts_definition 
+  * @{
+  */
+
+#define I2C_IT_BUF                      ((uint16_t)0x0400)
+#define I2C_IT_EVT                      ((uint16_t)0x0200)
+#define I2C_IT_ERR                      ((uint16_t)0x0100)
+#define IS_I2C_CONFIG_IT(IT) ((((IT) & (uint16_t)0xF8FF) == 0x00) && ((IT) != 0x00))
+/**
+  * @}
+  */ 
+
+/** @defgroup I2C_interrupts_definition 
+  * @{
+  */
+
+#define I2C_IT_SMBALERT                 ((uint32_t)0x01008000)
+#define I2C_IT_TIMEOUT                  ((uint32_t)0x01004000)
+#define I2C_IT_PECERR                   ((uint32_t)0x01001000)
+#define I2C_IT_OVR                      ((uint32_t)0x01000800)
+#define I2C_IT_AF                       ((uint32_t)0x01000400)
+#define I2C_IT_ARLO                     ((uint32_t)0x01000200)
+#define I2C_IT_BERR                     ((uint32_t)0x01000100)
+#define I2C_IT_TXE                      ((uint32_t)0x06000080)
+#define I2C_IT_RXNE                     ((uint32_t)0x06000040)
+#define I2C_IT_STOPF                    ((uint32_t)0x02000010)
+#define I2C_IT_ADD10                    ((uint32_t)0x02000008)
+#define I2C_IT_BTF                      ((uint32_t)0x02000004)
+#define I2C_IT_ADDR                     ((uint32_t)0x02000002)
+#define I2C_IT_SB                       ((uint32_t)0x02000001)
+
+#define IS_I2C_CLEAR_IT(IT) ((((IT) & (uint16_t)0x20FF) == 0x00) && ((IT) != (uint16_t)0x00))
+
+#define IS_I2C_GET_IT(IT) (((IT) == I2C_IT_SMBALERT) || ((IT) == I2C_IT_TIMEOUT) || \
+                           ((IT) == I2C_IT_PECERR) || ((IT) == I2C_IT_OVR) || \
+                           ((IT) == I2C_IT_AF) || ((IT) == I2C_IT_ARLO) || \
+                           ((IT) == I2C_IT_BERR) || ((IT) == I2C_IT_TXE) || \
+                           ((IT) == I2C_IT_RXNE) || ((IT) == I2C_IT_STOPF) || \
+                           ((IT) == I2C_IT_ADD10) || ((IT) == I2C_IT_BTF) || \
+                           ((IT) == I2C_IT_ADDR) || ((IT) == I2C_IT_SB))
+/**
+  * @}
+  */
+
+/** @defgroup I2C_flags_definition 
+  * @{
+  */
+
+/** 
+  * @brief  SR2 register flags  
+  */
+
+#define I2C_FLAG_DUALF                  ((uint32_t)0x00800000)
+#define I2C_FLAG_SMBHOST                ((uint32_t)0x00400000)
+#define I2C_FLAG_SMBDEFAULT             ((uint32_t)0x00200000)
+#define I2C_FLAG_GENCALL                ((uint32_t)0x00100000)
+#define I2C_FLAG_TRA                    ((uint32_t)0x00040000)
+#define I2C_FLAG_BUSY                   ((uint32_t)0x00020000)
+#define I2C_FLAG_MSL                    ((uint32_t)0x00010000)
+
+/** 
+  * @brief  SR1 register flags  
+  */
+
+#define I2C_FLAG_SMBALERT               ((uint32_t)0x10008000)
+#define I2C_FLAG_TIMEOUT                ((uint32_t)0x10004000)
+#define I2C_FLAG_PECERR                 ((uint32_t)0x10001000)
+#define I2C_FLAG_OVR                    ((uint32_t)0x10000800)
+#define I2C_FLAG_AF                     ((uint32_t)0x10000400)
+#define I2C_FLAG_ARLO                   ((uint32_t)0x10000200)
+#define I2C_FLAG_BERR                   ((uint32_t)0x10000100)
+#define I2C_FLAG_TXE                    ((uint32_t)0x10000080)
+#define I2C_FLAG_RXNE                   ((uint32_t)0x10000040)
+#define I2C_FLAG_STOPF                  ((uint32_t)0x10000010)
+#define I2C_FLAG_ADD10                  ((uint32_t)0x10000008)
+#define I2C_FLAG_BTF                    ((uint32_t)0x10000004)
+#define I2C_FLAG_ADDR                   ((uint32_t)0x10000002)
+#define I2C_FLAG_SB                     ((uint32_t)0x10000001)
+
+#define IS_I2C_CLEAR_FLAG(FLAG) ((((FLAG) & (uint16_t)0x20FF) == 0x00) && ((FLAG) != (uint16_t)0x00))
+
+#define IS_I2C_GET_FLAG(FLAG) (((FLAG) == I2C_FLAG_DUALF) || ((FLAG) == I2C_FLAG_SMBHOST) || \
+                               ((FLAG) == I2C_FLAG_SMBDEFAULT) || ((FLAG) == I2C_FLAG_GENCALL) || \
+                               ((FLAG) == I2C_FLAG_TRA) || ((FLAG) == I2C_FLAG_BUSY) || \
+                               ((FLAG) == I2C_FLAG_MSL) || ((FLAG) == I2C_FLAG_SMBALERT) || \
+                               ((FLAG) == I2C_FLAG_TIMEOUT) || ((FLAG) == I2C_FLAG_PECERR) || \
+                               ((FLAG) == I2C_FLAG_OVR) || ((FLAG) == I2C_FLAG_AF) || \
+                               ((FLAG) == I2C_FLAG_ARLO) || ((FLAG) == I2C_FLAG_BERR) || \
+                               ((FLAG) == I2C_FLAG_TXE) || ((FLAG) == I2C_FLAG_RXNE) || \
+                               ((FLAG) == I2C_FLAG_STOPF) || ((FLAG) == I2C_FLAG_ADD10) || \
+                               ((FLAG) == I2C_FLAG_BTF) || ((FLAG) == I2C_FLAG_ADDR) || \
+                               ((FLAG) == I2C_FLAG_SB))
+/**
+  * @}
+  */
+
+/** @defgroup I2C_Events 
+  * @{
+  */
+
+/*========================================
+     
+                     I2C Master Events (Events grouped in order of communication)
+                                                        ==========================================*/
+/** 
+  * @brief  Communication start
+  * 
+  * After sending the START condition (I2C_GenerateSTART() function) the master 
+  * has to wait for this event. It means that the Start condition has been correctly 
+  * released on the I2C bus (the bus is free, no other devices is communicating).
+  * 
+  */
+/* --EV5 */
+#define  I2C_EVENT_MASTER_MODE_SELECT                      ((uint32_t)0x00030001)  /* BUSY, MSL and SB flag */
+
+/** 
+  * @brief  Address Acknowledge
+  * 
+  * After checking on EV5 (start condition correctly released on the bus), the 
+  * master sends the address of the slave(s) with which it will communicate 
+  * (I2C_Send7bitAddress() function, it also determines the direction of the communication: 
+  * Master transmitter or Receiver). Then the master has to wait that a slave acknowledges 
+  * his address. If an acknowledge is sent on the bus, one of the following events will 
+  * be set:
+  * 
+  *  1) In case of Master Receiver (7-bit addressing): the I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED 
+  *     event is set.
+  *  
+  *  2) In case of Master Transmitter (7-bit addressing): the I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED 
+  *     is set
+  *  
+  *  3) In case of 10-Bit addressing mode, the master (just after generating the START 
+  *  and checking on EV5) has to send the header of 10-bit addressing mode (I2C_SendData() 
+  *  function). Then master should wait on EV9. It means that the 10-bit addressing 
+  *  header has been correctly sent on the bus. Then master should send the second part of 
+  *  the 10-bit address (LSB) using the function I2C_Send7bitAddress(). Then master 
+  *  should wait for event EV6. 
+  *     
+  */
+
+/* --EV6 */
+#define  I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED        ((uint32_t)0x00070082)  /* BUSY, MSL, ADDR, TXE and TRA flags */
+#define  I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED           ((uint32_t)0x00030002)  /* BUSY, MSL and ADDR flags */
+/* --EV9 */
+#define  I2C_EVENT_MASTER_MODE_ADDRESS10                   ((uint32_t)0x00030008)  /* BUSY, MSL and ADD10 flags */
+
+/** 
+  * @brief Communication events
+  * 
+  * If a communication is established (START condition generated and slave address 
+  * acknowledged) then the master has to check on one of the following events for 
+  * communication procedures:
+  *  
+  * 1) Master Receiver mode: The master has to wait on the event EV7 then to read 
+  *    the data received from the slave (I2C_ReceiveData() function).
+  * 
+  * 2) Master Transmitter mode: The master has to send data (I2C_SendData() 
+  *    function) then to wait on event EV8 or EV8_2.
+  *    These two events are similar: 
+  *     - EV8 means that the data has been written in the data register and is 
+  *       being shifted out.
+  *     - EV8_2 means that the data has been physically shifted out and output 
+  *       on the bus.
+  *     In most cases, using EV8 is sufficient for the application.
+  *     Using EV8_2 leads to a slower communication but ensure more reliable test.
+  *     EV8_2 is also more suitable than EV8 for testing on the last data transmission 
+  *     (before Stop condition generation).
+  *     
+  *  @note In case the  user software does not guarantee that this event EV7 is 
+  *  managed before the current byte end of transfer, then user may check on EV7 
+  *  and BTF flag at the same time (ie. (I2C_EVENT_MASTER_BYTE_RECEIVED | I2C_FLAG_BTF)).
+  *  In this case the communication may be slower.
+  * 
+  */
+
+/* Master RECEIVER mode -----------------------------*/ 
+/* --EV7 */
+#define  I2C_EVENT_MASTER_BYTE_RECEIVED                    ((uint32_t)0x00030040)  /* BUSY, MSL and RXNE flags */
+
+/* Master TRANSMITTER mode --------------------------*/
+/* --EV8 */
+#define I2C_EVENT_MASTER_BYTE_TRANSMITTING                 ((uint32_t)0x00070080) /* TRA, BUSY, MSL, TXE flags */
+/* --EV8_2 */
+#define  I2C_EVENT_MASTER_BYTE_TRANSMITTED                 ((uint32_t)0x00070084)  /* TRA, BUSY, MSL, TXE and BTF flags */
+
+
+/*========================================
+     
+                     I2C Slave Events (Events grouped in order of communication)
+                                                        ==========================================*/
+
+/** 
+  * @brief  Communication start events
+  * 
+  * Wait on one of these events at the start of the communication. It means that 
+  * the I2C peripheral detected a Start condition on the bus (generated by master 
+  * device) followed by the peripheral address. The peripheral generates an ACK 
+  * condition on the bus (if the acknowledge feature is enabled through function 
+  * I2C_AcknowledgeConfig()) and the events listed above are set :
+  *  
+  * 1) In normal case (only one address managed by the slave), when the address 
+  *   sent by the master matches the own address of the peripheral (configured by 
+  *   I2C_OwnAddress1 field) the I2C_EVENT_SLAVE_XXX_ADDRESS_MATCHED event is set 
+  *   (where XXX could be TRANSMITTER or RECEIVER).
+  *    
+  * 2) In case the address sent by the master matches the second address of the 
+  *   peripheral (configured by the function I2C_OwnAddress2Config() and enabled 
+  *   by the function I2C_DualAddressCmd()) the events I2C_EVENT_SLAVE_XXX_SECONDADDRESS_MATCHED 
+  *   (where XXX could be TRANSMITTER or RECEIVER) are set.
+  *   
+  * 3) In case the address sent by the master is General Call (address 0x00) and 
+  *   if the General Call is enabled for the peripheral (using function I2C_GeneralCallCmd()) 
+  *   the following event is set I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED.   
+  * 
+  */
+
+/* --EV1  (all the events below are variants of EV1) */   
+/* 1) Case of One Single Address managed by the slave */
+#define  I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED          ((uint32_t)0x00020002) /* BUSY and ADDR flags */
+#define  I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED       ((uint32_t)0x00060082) /* TRA, BUSY, TXE and ADDR flags */
+
+/* 2) Case of Dual address managed by the slave */
+#define  I2C_EVENT_SLAVE_RECEIVER_SECONDADDRESS_MATCHED    ((uint32_t)0x00820000)  /* DUALF and BUSY flags */
+#define  I2C_EVENT_SLAVE_TRANSMITTER_SECONDADDRESS_MATCHED ((uint32_t)0x00860080)  /* DUALF, TRA, BUSY and TXE flags */
+
+/* 3) Case of General Call enabled for the slave */
+#define  I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED        ((uint32_t)0x00120000)  /* GENCALL and BUSY flags */
+
+/** 
+  * @brief  Communication events
+  * 
+  * Wait on one of these events when EV1 has already been checked and: 
+  * 
+  * - Slave RECEIVER mode:
+  *     - EV2: When the application is expecting a data byte to be received. 
+  *     - EV4: When the application is expecting the end of the communication: master 
+  *       sends a stop condition and data transmission is stopped.
+  *    
+  * - Slave Transmitter mode:
+  *    - EV3: When a byte has been transmitted by the slave and the application is expecting 
+  *      the end of the byte transmission. The two events I2C_EVENT_SLAVE_BYTE_TRANSMITTED and
+  *      I2C_EVENT_SLAVE_BYTE_TRANSMITTING are similar. The second one can optionally be 
+  *      used when the user software doesn't guarantee the EV3 is managed before the
+  *      current byte end of transfer.
+  *    - EV3_2: When the master sends a NACK in order to tell slave that data transmission 
+  *      shall end (before sending the STOP condition). In this case slave has to stop sending 
+  *      data bytes and expect a Stop condition on the bus.
+  *      
+  *  @note In case the  user software does not guarantee that the event EV2 is 
+  *  managed before the current byte end of transfer, then user may check on EV2 
+  *  and BTF flag at the same time (ie. (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_BTF)).
+  * In this case the communication may be slower.
+  *
+  */
+
+/* Slave RECEIVER mode --------------------------*/ 
+/* --EV2 */
+#define  I2C_EVENT_SLAVE_BYTE_RECEIVED                     ((uint32_t)0x00020040)  /* BUSY and RXNE flags */
+/* --EV4  */
+#define  I2C_EVENT_SLAVE_STOP_DETECTED                     ((uint32_t)0x00000010)  /* STOPF flag */
+
+/* Slave TRANSMITTER mode -----------------------*/
+/* --EV3 */
+#define  I2C_EVENT_SLAVE_BYTE_TRANSMITTED                  ((uint32_t)0x00060084)  /* TRA, BUSY, TXE and BTF flags */
+#define  I2C_EVENT_SLAVE_BYTE_TRANSMITTING                 ((uint32_t)0x00060080)  /* TRA, BUSY and TXE flags */
+/* --EV3_2 */
+#define  I2C_EVENT_SLAVE_ACK_FAILURE                       ((uint32_t)0x00000400)  /* AF flag */
+
+/*===========================      End of Events Description           ==========================================*/
+
+#define IS_I2C_EVENT(EVENT) (((EVENT) == I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED) || \
+                             ((EVENT) == I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED) || \
+                             ((EVENT) == I2C_EVENT_SLAVE_TRANSMITTER_SECONDADDRESS_MATCHED) || \
+                             ((EVENT) == I2C_EVENT_SLAVE_RECEIVER_SECONDADDRESS_MATCHED) || \
+                             ((EVENT) == I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED) || \
+                             ((EVENT) == I2C_EVENT_SLAVE_BYTE_RECEIVED) || \
+                             ((EVENT) == (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_DUALF)) || \
+                             ((EVENT) == (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_GENCALL)) || \
+                             ((EVENT) == I2C_EVENT_SLAVE_BYTE_TRANSMITTED) || \
+                             ((EVENT) == (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | I2C_FLAG_DUALF)) || \
+                             ((EVENT) == (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | I2C_FLAG_GENCALL)) || \
+                             ((EVENT) == I2C_EVENT_SLAVE_STOP_DETECTED) || \
+                             ((EVENT) == I2C_EVENT_MASTER_MODE_SELECT) || \
+                             ((EVENT) == I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED) || \
+                             ((EVENT) == I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED) || \
+                             ((EVENT) == I2C_EVENT_MASTER_BYTE_RECEIVED) || \
+                             ((EVENT) == I2C_EVENT_MASTER_BYTE_TRANSMITTED) || \
+                             ((EVENT) == I2C_EVENT_MASTER_BYTE_TRANSMITTING) || \
+                             ((EVENT) == I2C_EVENT_MASTER_MODE_ADDRESS10) || \
+                             ((EVENT) == I2C_EVENT_SLAVE_ACK_FAILURE))
+/**
+  * @}
+  */
+
+/** @defgroup I2C_own_address1 
+  * @{
+  */
+
+#define IS_I2C_OWN_ADDRESS1(ADDRESS1) ((ADDRESS1) <= 0x3FF)
+/**
+  * @}
+  */
+
+/** @defgroup I2C_clock_speed 
+  * @{
+  */
+
+#define IS_I2C_CLOCK_SPEED(SPEED) (((SPEED) >= 0x1) && ((SPEED) <= 400000))
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup I2C_Exported_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup I2C_Exported_Functions
+  * @{
+  */
+
+void I2C_DeInit(I2C_TypeDef* I2Cx);
+void I2C_Init(I2C_TypeDef* I2Cx, I2C_InitTypeDef* I2C_InitStruct);
+void I2C_StructInit(I2C_InitTypeDef* I2C_InitStruct);
+void I2C_Cmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
+void I2C_DMACmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
+void I2C_DMALastTransferCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
+void I2C_GenerateSTART(I2C_TypeDef* I2Cx, FunctionalState NewState);
+void I2C_GenerateSTOP(I2C_TypeDef* I2Cx, FunctionalState NewState);
+void I2C_AcknowledgeConfig(I2C_TypeDef* I2Cx, FunctionalState NewState);
+void I2C_OwnAddress2Config(I2C_TypeDef* I2Cx, uint8_t Address);
+void I2C_DualAddressCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
+void I2C_GeneralCallCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
+void I2C_ITConfig(I2C_TypeDef* I2Cx, uint16_t I2C_IT, FunctionalState NewState);
+void I2C_SendData(I2C_TypeDef* I2Cx, uint8_t Data);
+uint8_t I2C_ReceiveData(I2C_TypeDef* I2Cx);
+void I2C_Send7bitAddress(I2C_TypeDef* I2Cx, uint8_t Address, uint8_t I2C_Direction);
+uint16_t I2C_ReadRegister(I2C_TypeDef* I2Cx, uint8_t I2C_Register);
+void I2C_SoftwareResetCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
+void I2C_NACKPositionConfig(I2C_TypeDef* I2Cx, uint16_t I2C_NACKPosition);
+void I2C_SMBusAlertConfig(I2C_TypeDef* I2Cx, uint16_t I2C_SMBusAlert);
+void I2C_TransmitPEC(I2C_TypeDef* I2Cx, FunctionalState NewState);
+void I2C_PECPositionConfig(I2C_TypeDef* I2Cx, uint16_t I2C_PECPosition);
+void I2C_CalculatePEC(I2C_TypeDef* I2Cx, FunctionalState NewState);
+uint8_t I2C_GetPEC(I2C_TypeDef* I2Cx);
+void I2C_ARPCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
+void I2C_StretchClockCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
+void I2C_FastModeDutyCycleConfig(I2C_TypeDef* I2Cx, uint16_t I2C_DutyCycle);
+
+/**
+ * @brief
+ ****************************************************************************************
+ *
+ *                         I2C State Monitoring Functions
+ *                       
+ ****************************************************************************************   
+ * This I2C driver provides three different ways for I2C state monitoring
+ *  depending on the application requirements and constraints:
+ *        
+ *  
+ * 1) Basic state monitoring:
+ *    Using I2C_CheckEvent() function:
+ *    It compares the status registers (SR1 and SR2) content to a given event
+ *    (can be the combination of one or more flags).
+ *    It returns SUCCESS if the current status includes the given flags 
+ *    and returns ERROR if one or more flags are missing in the current status.
+ *    - When to use:
+ *      - This function is suitable for most applications as well as for startup 
+ *      activity since the events are fully described in the product reference manual 
+ *      (RM0008).
+ *      - It is also suitable for users who need to define their own events.
+ *    - Limitations:
+ *      - If an error occurs (ie. error flags are set besides to the monitored flags),
+ *        the I2C_CheckEvent() function may return SUCCESS despite the communication
+ *        hold or corrupted real state. 
+ *        In this case, it is advised to use error interrupts to monitor the error
+ *        events and handle them in the interrupt IRQ handler.
+ *        
+ *        @note 
+ *        For error management, it is advised to use the following functions:
+ *          - I2C_ITConfig() to configure and enable the error interrupts (I2C_IT_ERR).
+ *          - I2Cx_ER_IRQHandler() which is called when the error interrupt occurs.
+ *            Where x is the peripheral instance (I2C1, I2C2 ...)
+ *          - I2C_GetFlagStatus() or I2C_GetITStatus() to be called into I2Cx_ER_IRQHandler()
+ *            in order to determine which error occurred.
+ *          - I2C_ClearFlag() or I2C_ClearITPendingBit() and/or I2C_SoftwareResetCmd()
+ *            and/or I2C_GenerateStop() in order to clear the error flag and source,
+ *            and return to correct communication status.
+ *            
+ *
+ *  2) Advanced state monitoring:
+ *     Using the function I2C_GetLastEvent() which returns the image of both status 
+ *     registers in a single word (uint32_t) (Status Register 2 value is shifted left 
+ *     by 16 bits and concatenated to Status Register 1).
+ *     - When to use:
+ *       - This function is suitable for the same applications above but it allows to
+ *         overcome the limitations of I2C_GetFlagStatus() function (see below).
+ *         The returned value could be compared to events already defined in the 
+ *         library (stm32f10x_i2c.h) or to custom values defined by user.
+ *       - This function is suitable when multiple flags are monitored at the same time.
+ *       - At the opposite of I2C_CheckEvent() function, this function allows user to
+ *         choose when an event is accepted (when all events flags are set and no 
+ *         other flags are set or just when the needed flags are set like 
+ *         I2C_CheckEvent() function).
+ *     - Limitations:
+ *       - User may need to define his own events.
+ *       - Same remark concerning the error management is applicable for this 
+ *         function if user decides to check only regular communication flags (and 
+ *         ignores error flags).
+ *     
+ *
+ *  3) Flag-based state monitoring:
+ *     Using the function I2C_GetFlagStatus() which simply returns the status of 
+ *     one single flag (ie. I2C_FLAG_RXNE ...). 
+ *     - When to use:
+ *        - This function could be used for specific applications or in debug phase.
+ *        - It is suitable when only one flag checking is needed (most I2C events 
+ *          are monitored through multiple flags).
+ *     - Limitations: 
+ *        - When calling this function, the Status register is accessed. Some flags are
+ *          cleared when the status register is accessed. So checking the status
+ *          of one Flag, may clear other ones.
+ *        - Function may need to be called twice or more in order to monitor one 
+ *          single event.
+ *            
+ */
+
+/**
+ * 
+ *  1) Basic state monitoring
+ *******************************************************************************
+ */
+ErrorStatus I2C_CheckEvent(I2C_TypeDef* I2Cx, uint32_t I2C_EVENT);
+/**
+ * 
+ *  2) Advanced state monitoring
+ *******************************************************************************
+ */
+uint32_t I2C_GetLastEvent(I2C_TypeDef* I2Cx);
+/**
+ * 
+ *  3) Flag-based state monitoring
+ *******************************************************************************
+ */
+FlagStatus I2C_GetFlagStatus(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG);
+/**
+ *
+ *******************************************************************************
+ */
+
+void I2C_ClearFlag(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG);
+ITStatus I2C_GetITStatus(I2C_TypeDef* I2Cx, uint32_t I2C_IT);
+void I2C_ClearITPendingBit(I2C_TypeDef* I2Cx, uint32_t I2C_IT);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__STM32F10x_I2C_H */
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/STM32_4路称重_Git提交精简工程/src/STM32F10x_FWLib/inc/stm32f10x_iwdg.h b/STM32_4路称重_Git提交精简工程/src/STM32F10x_FWLib/inc/stm32f10x_iwdg.h
new file mode 100755
index 0000000..7f5ab76
--- /dev/null
+++ b/STM32_4路称重_Git提交精简工程/src/STM32F10x_FWLib/inc/stm32f10x_iwdg.h
@@ -0,0 +1,140 @@
+/**
+  ******************************************************************************
+  * @file    stm32f10x_iwdg.h
+  * @author  MCD Application Team
+  * @version V3.5.0
+  * @date    11-March-2011
+  * @brief   This file contains all the functions prototypes for the IWDG 
+  *          firmware library.
+  ******************************************************************************
+  * @attention
+  *
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+  *
+  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F10x_IWDG_H
+#define __STM32F10x_IWDG_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x.h"
+
+/** @addtogroup STM32F10x_StdPeriph_Driver
+  * @{
+  */
+
+/** @addtogroup IWDG
+  * @{
+  */
+
+/** @defgroup IWDG_Exported_Types
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup IWDG_Exported_Constants
+  * @{
+  */
+
+/** @defgroup IWDG_WriteAccess
+  * @{
+  */
+
+#define IWDG_WriteAccess_Enable     ((uint16_t)0x5555)
+#define IWDG_WriteAccess_Disable    ((uint16_t)0x0000)
+#define IS_IWDG_WRITE_ACCESS(ACCESS) (((ACCESS) == IWDG_WriteAccess_Enable) || \
+                                      ((ACCESS) == IWDG_WriteAccess_Disable))
+/**
+  * @}
+  */
+
+/** @defgroup IWDG_prescaler 
+  * @{
+  */
+
+#define IWDG_Prescaler_4            ((uint8_t)0x00)
+#define IWDG_Prescaler_8            ((uint8_t)0x01)
+#define IWDG_Prescaler_16           ((uint8_t)0x02)
+#define IWDG_Prescaler_32           ((uint8_t)0x03)
+#define IWDG_Prescaler_64           ((uint8_t)0x04)
+#define IWDG_Prescaler_128          ((uint8_t)0x05)
+#define IWDG_Prescaler_256          ((uint8_t)0x06)
+#define IS_IWDG_PRESCALER(PRESCALER) (((PRESCALER) == IWDG_Prescaler_4)  || \
+                                      ((PRESCALER) == IWDG_Prescaler_8)  || \
+                                      ((PRESCALER) == IWDG_Prescaler_16) || \
+                                      ((PRESCALER) == IWDG_Prescaler_32) || \
+                                      ((PRESCALER) == IWDG_Prescaler_64) || \
+                                      ((PRESCALER) == IWDG_Prescaler_128)|| \
+                                      ((PRESCALER) == IWDG_Prescaler_256))
+/**
+  * @}
+  */
+
+/** @defgroup IWDG_Flag 
+  * @{
+  */
+
+#define IWDG_FLAG_PVU               ((uint16_t)0x0001)
+#define IWDG_FLAG_RVU               ((uint16_t)0x0002)
+#define IS_IWDG_FLAG(FLAG) (((FLAG) == IWDG_FLAG_PVU) || ((FLAG) == IWDG_FLAG_RVU))
+#define IS_IWDG_RELOAD(RELOAD) ((RELOAD) <= 0xFFF)
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup IWDG_Exported_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup IWDG_Exported_Functions
+  * @{
+  */
+
+void IWDG_WriteAccessCmd(uint16_t IWDG_WriteAccess);
+void IWDG_SetPrescaler(uint8_t IWDG_Prescaler);
+void IWDG_SetReload(uint16_t Reload);
+void IWDG_ReloadCounter(void);
+void IWDG_Enable(void);
+FlagStatus IWDG_GetFlagStatus(uint16_t IWDG_FLAG);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F10x_IWDG_H */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/STM32_4路称重_Git提交精简工程/src/STM32F10x_FWLib/inc/stm32f10x_pwr.h b/STM32_4路称重_Git提交精简工程/src/STM32F10x_FWLib/inc/stm32f10x_pwr.h
new file mode 100755
index 0000000..76e6ce9
--- /dev/null
+++ b/STM32_4路称重_Git提交精简工程/src/STM32F10x_FWLib/inc/stm32f10x_pwr.h
@@ -0,0 +1,156 @@
+/**
+  ******************************************************************************
+  * @file    stm32f10x_pwr.h
+  * @author  MCD Application Team
+  * @version V3.5.0
+  * @date    11-March-2011
+  * @brief   This file contains all the functions prototypes for the PWR firmware 
+  *          library.
+  ******************************************************************************
+  * @attention
+  *
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+  *
+  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F10x_PWR_H
+#define __STM32F10x_PWR_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x.h"
+
+/** @addtogroup STM32F10x_StdPeriph_Driver
+  * @{
+  */
+
+/** @addtogroup PWR
+  * @{
+  */ 
+
+/** @defgroup PWR_Exported_Types
+  * @{
+  */ 
+
+/**
+  * @}
+  */ 
+
+/** @defgroup PWR_Exported_Constants
+  * @{
+  */ 
+
+/** @defgroup PVD_detection_level 
+  * @{
+  */ 
+
+#define PWR_PVDLevel_2V2          ((uint32_t)0x00000000)
+#define PWR_PVDLevel_2V3          ((uint32_t)0x00000020)
+#define PWR_PVDLevel_2V4          ((uint32_t)0x00000040)
+#define PWR_PVDLevel_2V5          ((uint32_t)0x00000060)
+#define PWR_PVDLevel_2V6          ((uint32_t)0x00000080)
+#define PWR_PVDLevel_2V7          ((uint32_t)0x000000A0)
+#define PWR_PVDLevel_2V8          ((uint32_t)0x000000C0)
+#define PWR_PVDLevel_2V9          ((uint32_t)0x000000E0)
+#define IS_PWR_PVD_LEVEL(LEVEL) (((LEVEL) == PWR_PVDLevel_2V2) || ((LEVEL) == PWR_PVDLevel_2V3)|| \
+                                 ((LEVEL) == PWR_PVDLevel_2V4) || ((LEVEL) == PWR_PVDLevel_2V5)|| \
+                                 ((LEVEL) == PWR_PVDLevel_2V6) || ((LEVEL) == PWR_PVDLevel_2V7)|| \
+                                 ((LEVEL) == PWR_PVDLevel_2V8) || ((LEVEL) == PWR_PVDLevel_2V9))
+/**
+  * @}
+  */
+
+/** @defgroup Regulator_state_is_STOP_mode 
+  * @{
+  */
+
+#define PWR_Regulator_ON          ((uint32_t)0x00000000)
+#define PWR_Regulator_LowPower    ((uint32_t)0x00000001)
+#define IS_PWR_REGULATOR(REGULATOR) (((REGULATOR) == PWR_Regulator_ON) || \
+                                     ((REGULATOR) == PWR_Regulator_LowPower))
+/**
+  * @}
+  */
+
+/** @defgroup STOP_mode_entry 
+  * @{
+  */
+
+#define PWR_STOPEntry_WFI         ((uint8_t)0x01)
+#define PWR_STOPEntry_WFE         ((uint8_t)0x02)
+#define IS_PWR_STOP_ENTRY(ENTRY) (((ENTRY) == PWR_STOPEntry_WFI) || ((ENTRY) == PWR_STOPEntry_WFE))
+ 
+/**
+  * @}
+  */
+
+/** @defgroup PWR_Flag 
+  * @{
+  */
+
+#define PWR_FLAG_WU               ((uint32_t)0x00000001)
+#define PWR_FLAG_SB               ((uint32_t)0x00000002)
+#define PWR_FLAG_PVDO             ((uint32_t)0x00000004)
+#define IS_PWR_GET_FLAG(FLAG) (((FLAG) == PWR_FLAG_WU) || ((FLAG) == PWR_FLAG_SB) || \
+                               ((FLAG) == PWR_FLAG_PVDO))
+
+#define IS_PWR_CLEAR_FLAG(FLAG) (((FLAG) == PWR_FLAG_WU) || ((FLAG) == PWR_FLAG_SB))
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup PWR_Exported_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup PWR_Exported_Functions
+  * @{
+  */
+
+void PWR_DeInit(void);
+void PWR_BackupAccessCmd(FunctionalState NewState);
+void PWR_PVDCmd(FunctionalState NewState);
+void PWR_PVDLevelConfig(uint32_t PWR_PVDLevel);
+void PWR_WakeUpPinCmd(FunctionalState NewState);
+void PWR_EnterSTOPMode(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry);
+void PWR_EnterSTANDBYMode(void);
+FlagStatus PWR_GetFlagStatus(uint32_t PWR_FLAG);
+void PWR_ClearFlag(uint32_t PWR_FLAG);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F10x_PWR_H */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/STM32_4路称重_Git提交精简工程/src/STM32F10x_FWLib/inc/stm32f10x_rcc.h b/STM32_4路称重_Git提交精简工程/src/STM32F10x_FWLib/inc/stm32f10x_rcc.h
new file mode 100755
index 0000000..b3b7d82
--- /dev/null
+++ b/STM32_4路称重_Git提交精简工程/src/STM32F10x_FWLib/inc/stm32f10x_rcc.h
@@ -0,0 +1,727 @@
+/**
+  ******************************************************************************
+  * @file    stm32f10x_rcc.h
+  * @author  MCD Application Team
+  * @version V3.5.0
+  * @date    11-March-2011
+  * @brief   This file contains all the functions prototypes for the RCC firmware 
+  *          library.
+  ******************************************************************************
+  * @attention
+  *
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+  *
+  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F10x_RCC_H
+#define __STM32F10x_RCC_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x.h"
+
+/** @addtogroup STM32F10x_StdPeriph_Driver
+  * @{
+  */
+
+/** @addtogroup RCC
+  * @{
+  */
+
+/** @defgroup RCC_Exported_Types
+  * @{
+  */
+
+typedef struct
+{
+  uint32_t SYSCLK_Frequency;  /*!< returns SYSCLK clock frequency expressed in Hz */
+  uint32_t HCLK_Frequency;    /*!< returns HCLK clock frequency expressed in Hz */
+  uint32_t PCLK1_Frequency;   /*!< returns PCLK1 clock frequency expressed in Hz */
+  uint32_t PCLK2_Frequency;   /*!< returns PCLK2 clock frequency expressed in Hz */
+  uint32_t ADCCLK_Frequency;  /*!< returns ADCCLK clock frequency expressed in Hz */
+}RCC_ClocksTypeDef;
+
+/**
+  * @}
+  */
+
+/** @defgroup RCC_Exported_Constants
+  * @{
+  */
+
+/** @defgroup HSE_configuration 
+  * @{
+  */
+
+#define RCC_HSE_OFF                      ((uint32_t)0x00000000)
+#define RCC_HSE_ON                       ((uint32_t)0x00010000)
+#define RCC_HSE_Bypass                   ((uint32_t)0x00040000)
+#define IS_RCC_HSE(HSE) (((HSE) == RCC_HSE_OFF) || ((HSE) == RCC_HSE_ON) || \
+                         ((HSE) == RCC_HSE_Bypass))
+
+/**
+  * @}
+  */ 
+
+/** @defgroup PLL_entry_clock_source 
+  * @{
+  */
+
+#define RCC_PLLSource_HSI_Div2           ((uint32_t)0x00000000)
+
+#if !defined (STM32F10X_LD_VL) && !defined (STM32F10X_MD_VL) && !defined (STM32F10X_HD_VL) && !defined (STM32F10X_CL)
+ #define RCC_PLLSource_HSE_Div1           ((uint32_t)0x00010000)
+ #define RCC_PLLSource_HSE_Div2           ((uint32_t)0x00030000)
+ #define IS_RCC_PLL_SOURCE(SOURCE) (((SOURCE) == RCC_PLLSource_HSI_Div2) || \
+                                   ((SOURCE) == RCC_PLLSource_HSE_Div1) || \
+                                   ((SOURCE) == RCC_PLLSource_HSE_Div2))
+#else
+ #define RCC_PLLSource_PREDIV1            ((uint32_t)0x00010000)
+ #define IS_RCC_PLL_SOURCE(SOURCE) (((SOURCE) == RCC_PLLSource_HSI_Div2) || \
+                                   ((SOURCE) == RCC_PLLSource_PREDIV1))
+#endif /* STM32F10X_CL */ 
+
+/**
+  * @}
+  */ 
+
+/** @defgroup PLL_multiplication_factor 
+  * @{
+  */
+#ifndef STM32F10X_CL
+ #define RCC_PLLMul_2                    ((uint32_t)0x00000000)
+ #define RCC_PLLMul_3                    ((uint32_t)0x00040000)
+ #define RCC_PLLMul_4                    ((uint32_t)0x00080000)
+ #define RCC_PLLMul_5                    ((uint32_t)0x000C0000)
+ #define RCC_PLLMul_6                    ((uint32_t)0x00100000)
+ #define RCC_PLLMul_7                    ((uint32_t)0x00140000)
+ #define RCC_PLLMul_8                    ((uint32_t)0x00180000)
+ #define RCC_PLLMul_9                    ((uint32_t)0x001C0000)
+ #define RCC_PLLMul_10                   ((uint32_t)0x00200000)
+ #define RCC_PLLMul_11                   ((uint32_t)0x00240000)
+ #define RCC_PLLMul_12                   ((uint32_t)0x00280000)
+ #define RCC_PLLMul_13                   ((uint32_t)0x002C0000)
+ #define RCC_PLLMul_14                   ((uint32_t)0x00300000)
+ #define RCC_PLLMul_15                   ((uint32_t)0x00340000)
+ #define RCC_PLLMul_16                   ((uint32_t)0x00380000)
+ #define IS_RCC_PLL_MUL(MUL) (((MUL) == RCC_PLLMul_2) || ((MUL) == RCC_PLLMul_3)   || \
+                              ((MUL) == RCC_PLLMul_4) || ((MUL) == RCC_PLLMul_5)   || \
+                              ((MUL) == RCC_PLLMul_6) || ((MUL) == RCC_PLLMul_7)   || \
+                              ((MUL) == RCC_PLLMul_8) || ((MUL) == RCC_PLLMul_9)   || \
+                              ((MUL) == RCC_PLLMul_10) || ((MUL) == RCC_PLLMul_11) || \
+                              ((MUL) == RCC_PLLMul_12) || ((MUL) == RCC_PLLMul_13) || \
+                              ((MUL) == RCC_PLLMul_14) || ((MUL) == RCC_PLLMul_15) || \
+                              ((MUL) == RCC_PLLMul_16))
+
+#else
+ #define RCC_PLLMul_4                    ((uint32_t)0x00080000)
+ #define RCC_PLLMul_5                    ((uint32_t)0x000C0000)
+ #define RCC_PLLMul_6                    ((uint32_t)0x00100000)
+ #define RCC_PLLMul_7                    ((uint32_t)0x00140000)
+ #define RCC_PLLMul_8                    ((uint32_t)0x00180000)
+ #define RCC_PLLMul_9                    ((uint32_t)0x001C0000)
+ #define RCC_PLLMul_6_5                  ((uint32_t)0x00340000)
+
+ #define IS_RCC_PLL_MUL(MUL) (((MUL) == RCC_PLLMul_4) || ((MUL) == RCC_PLLMul_5) || \
+                              ((MUL) == RCC_PLLMul_6) || ((MUL) == RCC_PLLMul_7) || \
+                              ((MUL) == RCC_PLLMul_8) || ((MUL) == RCC_PLLMul_9) || \
+                              ((MUL) == RCC_PLLMul_6_5))
+#endif /* STM32F10X_CL */                              
+/**
+  * @}
+  */
+
+/** @defgroup PREDIV1_division_factor
+  * @{
+  */
+#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) || defined (STM32F10X_CL)
+ #define  RCC_PREDIV1_Div1               ((uint32_t)0x00000000)
+ #define  RCC_PREDIV1_Div2               ((uint32_t)0x00000001)
+ #define  RCC_PREDIV1_Div3               ((uint32_t)0x00000002)
+ #define  RCC_PREDIV1_Div4               ((uint32_t)0x00000003)
+ #define  RCC_PREDIV1_Div5               ((uint32_t)0x00000004)
+ #define  RCC_PREDIV1_Div6               ((uint32_t)0x00000005)
+ #define  RCC_PREDIV1_Div7               ((uint32_t)0x00000006)
+ #define  RCC_PREDIV1_Div8               ((uint32_t)0x00000007)
+ #define  RCC_PREDIV1_Div9               ((uint32_t)0x00000008)
+ #define  RCC_PREDIV1_Div10              ((uint32_t)0x00000009)
+ #define  RCC_PREDIV1_Div11              ((uint32_t)0x0000000A)
+ #define  RCC_PREDIV1_Div12              ((uint32_t)0x0000000B)
+ #define  RCC_PREDIV1_Div13              ((uint32_t)0x0000000C)
+ #define  RCC_PREDIV1_Div14              ((uint32_t)0x0000000D)
+ #define  RCC_PREDIV1_Div15              ((uint32_t)0x0000000E)
+ #define  RCC_PREDIV1_Div16              ((uint32_t)0x0000000F)
+
+ #define IS_RCC_PREDIV1(PREDIV1) (((PREDIV1) == RCC_PREDIV1_Div1) || ((PREDIV1) == RCC_PREDIV1_Div2) || \
+                                  ((PREDIV1) == RCC_PREDIV1_Div3) || ((PREDIV1) == RCC_PREDIV1_Div4) || \
+                                  ((PREDIV1) == RCC_PREDIV1_Div5) || ((PREDIV1) == RCC_PREDIV1_Div6) || \
+                                  ((PREDIV1) == RCC_PREDIV1_Div7) || ((PREDIV1) == RCC_PREDIV1_Div8) || \
+                                  ((PREDIV1) == RCC_PREDIV1_Div9) || ((PREDIV1) == RCC_PREDIV1_Div10) || \
+                                  ((PREDIV1) == RCC_PREDIV1_Div11) || ((PREDIV1) == RCC_PREDIV1_Div12) || \
+                                  ((PREDIV1) == RCC_PREDIV1_Div13) || ((PREDIV1) == RCC_PREDIV1_Div14) || \
+                                  ((PREDIV1) == RCC_PREDIV1_Div15) || ((PREDIV1) == RCC_PREDIV1_Div16))
+#endif
+/**
+  * @}
+  */
+
+
+/** @defgroup PREDIV1_clock_source
+  * @{
+  */
+#ifdef STM32F10X_CL
+/* PREDIV1 clock source (for STM32 connectivity line devices) */
+ #define  RCC_PREDIV1_Source_HSE         ((uint32_t)0x00000000) 
+ #define  RCC_PREDIV1_Source_PLL2        ((uint32_t)0x00010000) 
+
+ #define IS_RCC_PREDIV1_SOURCE(SOURCE) (((SOURCE) == RCC_PREDIV1_Source_HSE) || \
+                                        ((SOURCE) == RCC_PREDIV1_Source_PLL2)) 
+#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
+/* PREDIV1 clock source (for STM32 Value line devices) */
+ #define  RCC_PREDIV1_Source_HSE         ((uint32_t)0x00000000) 
+
+ #define IS_RCC_PREDIV1_SOURCE(SOURCE) (((SOURCE) == RCC_PREDIV1_Source_HSE)) 
+#endif
+/**
+  * @}
+  */
+
+#ifdef STM32F10X_CL
+/** @defgroup PREDIV2_division_factor
+  * @{
+  */
+  
+ #define  RCC_PREDIV2_Div1               ((uint32_t)0x00000000)
+ #define  RCC_PREDIV2_Div2               ((uint32_t)0x00000010)
+ #define  RCC_PREDIV2_Div3               ((uint32_t)0x00000020)
+ #define  RCC_PREDIV2_Div4               ((uint32_t)0x00000030)
+ #define  RCC_PREDIV2_Div5               ((uint32_t)0x00000040)
+ #define  RCC_PREDIV2_Div6               ((uint32_t)0x00000050)
+ #define  RCC_PREDIV2_Div7               ((uint32_t)0x00000060)
+ #define  RCC_PREDIV2_Div8               ((uint32_t)0x00000070)
+ #define  RCC_PREDIV2_Div9               ((uint32_t)0x00000080)
+ #define  RCC_PREDIV2_Div10              ((uint32_t)0x00000090)
+ #define  RCC_PREDIV2_Div11              ((uint32_t)0x000000A0)
+ #define  RCC_PREDIV2_Div12              ((uint32_t)0x000000B0)
+ #define  RCC_PREDIV2_Div13              ((uint32_t)0x000000C0)
+ #define  RCC_PREDIV2_Div14              ((uint32_t)0x000000D0)
+ #define  RCC_PREDIV2_Div15              ((uint32_t)0x000000E0)
+ #define  RCC_PREDIV2_Div16              ((uint32_t)0x000000F0)
+
+ #define IS_RCC_PREDIV2(PREDIV2) (((PREDIV2) == RCC_PREDIV2_Div1) || ((PREDIV2) == RCC_PREDIV2_Div2) || \
+                                  ((PREDIV2) == RCC_PREDIV2_Div3) || ((PREDIV2) == RCC_PREDIV2_Div4) || \
+                                  ((PREDIV2) == RCC_PREDIV2_Div5) || ((PREDIV2) == RCC_PREDIV2_Div6) || \
+                                  ((PREDIV2) == RCC_PREDIV2_Div7) || ((PREDIV2) == RCC_PREDIV2_Div8) || \
+                                  ((PREDIV2) == RCC_PREDIV2_Div9) || ((PREDIV2) == RCC_PREDIV2_Div10) || \
+                                  ((PREDIV2) == RCC_PREDIV2_Div11) || ((PREDIV2) == RCC_PREDIV2_Div12) || \
+                                  ((PREDIV2) == RCC_PREDIV2_Div13) || ((PREDIV2) == RCC_PREDIV2_Div14) || \
+                                  ((PREDIV2) == RCC_PREDIV2_Div15) || ((PREDIV2) == RCC_PREDIV2_Div16))
+/**
+  * @}
+  */
+
+
+/** @defgroup PLL2_multiplication_factor
+  * @{
+  */
+  
+ #define  RCC_PLL2Mul_8                  ((uint32_t)0x00000600)
+ #define  RCC_PLL2Mul_9                  ((uint32_t)0x00000700)
+ #define  RCC_PLL2Mul_10                 ((uint32_t)0x00000800)
+ #define  RCC_PLL2Mul_11                 ((uint32_t)0x00000900)
+ #define  RCC_PLL2Mul_12                 ((uint32_t)0x00000A00)
+ #define  RCC_PLL2Mul_13                 ((uint32_t)0x00000B00)
+ #define  RCC_PLL2Mul_14                 ((uint32_t)0x00000C00)
+ #define  RCC_PLL2Mul_16                 ((uint32_t)0x00000E00)
+ #define  RCC_PLL2Mul_20                 ((uint32_t)0x00000F00)
+
+ #define IS_RCC_PLL2_MUL(MUL) (((MUL) == RCC_PLL2Mul_8) || ((MUL) == RCC_PLL2Mul_9)  || \
+                               ((MUL) == RCC_PLL2Mul_10) || ((MUL) == RCC_PLL2Mul_11) || \
+                               ((MUL) == RCC_PLL2Mul_12) || ((MUL) == RCC_PLL2Mul_13) || \
+                               ((MUL) == RCC_PLL2Mul_14) || ((MUL) == RCC_PLL2Mul_16) || \
+                               ((MUL) == RCC_PLL2Mul_20))
+/**
+  * @}
+  */
+
+
+/** @defgroup PLL3_multiplication_factor
+  * @{
+  */
+
+ #define  RCC_PLL3Mul_8                  ((uint32_t)0x00006000)
+ #define  RCC_PLL3Mul_9                  ((uint32_t)0x00007000)
+ #define  RCC_PLL3Mul_10                 ((uint32_t)0x00008000)
+ #define  RCC_PLL3Mul_11                 ((uint32_t)0x00009000)
+ #define  RCC_PLL3Mul_12                 ((uint32_t)0x0000A000)
+ #define  RCC_PLL3Mul_13                 ((uint32_t)0x0000B000)
+ #define  RCC_PLL3Mul_14                 ((uint32_t)0x0000C000)
+ #define  RCC_PLL3Mul_16                 ((uint32_t)0x0000E000)
+ #define  RCC_PLL3Mul_20                 ((uint32_t)0x0000F000)
+
+ #define IS_RCC_PLL3_MUL(MUL) (((MUL) == RCC_PLL3Mul_8) || ((MUL) == RCC_PLL3Mul_9)  || \
+                               ((MUL) == RCC_PLL3Mul_10) || ((MUL) == RCC_PLL3Mul_11) || \
+                               ((MUL) == RCC_PLL3Mul_12) || ((MUL) == RCC_PLL3Mul_13) || \
+                               ((MUL) == RCC_PLL3Mul_14) || ((MUL) == RCC_PLL3Mul_16) || \
+                               ((MUL) == RCC_PLL3Mul_20))
+/**
+  * @}
+  */
+
+#endif /* STM32F10X_CL */
+
+
+/** @defgroup System_clock_source 
+  * @{
+  */
+
+#define RCC_SYSCLKSource_HSI             ((uint32_t)0x00000000)
+#define RCC_SYSCLKSource_HSE             ((uint32_t)0x00000001)
+#define RCC_SYSCLKSource_PLLCLK          ((uint32_t)0x00000002)
+#define IS_RCC_SYSCLK_SOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSource_HSI) || \
+                                      ((SOURCE) == RCC_SYSCLKSource_HSE) || \
+                                      ((SOURCE) == RCC_SYSCLKSource_PLLCLK))
+/**
+  * @}
+  */
+
+/** @defgroup AHB_clock_source 
+  * @{
+  */
+
+#define RCC_SYSCLK_Div1                  ((uint32_t)0x00000000)
+#define RCC_SYSCLK_Div2                  ((uint32_t)0x00000080)
+#define RCC_SYSCLK_Div4                  ((uint32_t)0x00000090)
+#define RCC_SYSCLK_Div8                  ((uint32_t)0x000000A0)
+#define RCC_SYSCLK_Div16                 ((uint32_t)0x000000B0)
+#define RCC_SYSCLK_Div64                 ((uint32_t)0x000000C0)
+#define RCC_SYSCLK_Div128                ((uint32_t)0x000000D0)
+#define RCC_SYSCLK_Div256                ((uint32_t)0x000000E0)
+#define RCC_SYSCLK_Div512                ((uint32_t)0x000000F0)
+#define IS_RCC_HCLK(HCLK) (((HCLK) == RCC_SYSCLK_Div1) || ((HCLK) == RCC_SYSCLK_Div2) || \
+                           ((HCLK) == RCC_SYSCLK_Div4) || ((HCLK) == RCC_SYSCLK_Div8) || \
+                           ((HCLK) == RCC_SYSCLK_Div16) || ((HCLK) == RCC_SYSCLK_Div64) || \
+                           ((HCLK) == RCC_SYSCLK_Div128) || ((HCLK) == RCC_SYSCLK_Div256) || \
+                           ((HCLK) == RCC_SYSCLK_Div512))
+/**
+  * @}
+  */ 
+
+/** @defgroup APB1_APB2_clock_source 
+  * @{
+  */
+
+#define RCC_HCLK_Div1                    ((uint32_t)0x00000000)
+#define RCC_HCLK_Div2                    ((uint32_t)0x00000400)
+#define RCC_HCLK_Div4                    ((uint32_t)0x00000500)
+#define RCC_HCLK_Div8                    ((uint32_t)0x00000600)
+#define RCC_HCLK_Div16                   ((uint32_t)0x00000700)
+#define IS_RCC_PCLK(PCLK) (((PCLK) == RCC_HCLK_Div1) || ((PCLK) == RCC_HCLK_Div2) || \
+                           ((PCLK) == RCC_HCLK_Div4) || ((PCLK) == RCC_HCLK_Div8) || \
+                           ((PCLK) == RCC_HCLK_Div16))
+/**
+  * @}
+  */
+
+/** @defgroup RCC_Interrupt_source 
+  * @{
+  */
+
+#define RCC_IT_LSIRDY                    ((uint8_t)0x01)
+#define RCC_IT_LSERDY                    ((uint8_t)0x02)
+#define RCC_IT_HSIRDY                    ((uint8_t)0x04)
+#define RCC_IT_HSERDY                    ((uint8_t)0x08)
+#define RCC_IT_PLLRDY                    ((uint8_t)0x10)
+#define RCC_IT_CSS                       ((uint8_t)0x80)
+
+#ifndef STM32F10X_CL
+ #define IS_RCC_IT(IT) ((((IT) & (uint8_t)0xE0) == 0x00) && ((IT) != 0x00))
+ #define IS_RCC_GET_IT(IT) (((IT) == RCC_IT_LSIRDY) || ((IT) == RCC_IT_LSERDY) || \
+                            ((IT) == RCC_IT_HSIRDY) || ((IT) == RCC_IT_HSERDY) || \
+                            ((IT) == RCC_IT_PLLRDY) || ((IT) == RCC_IT_CSS))
+ #define IS_RCC_CLEAR_IT(IT) ((((IT) & (uint8_t)0x60) == 0x00) && ((IT) != 0x00))
+#else
+ #define RCC_IT_PLL2RDY                  ((uint8_t)0x20)
+ #define RCC_IT_PLL3RDY                  ((uint8_t)0x40)
+ #define IS_RCC_IT(IT) ((((IT) & (uint8_t)0x80) == 0x00) && ((IT) != 0x00))
+ #define IS_RCC_GET_IT(IT) (((IT) == RCC_IT_LSIRDY) || ((IT) == RCC_IT_LSERDY) || \
+                            ((IT) == RCC_IT_HSIRDY) || ((IT) == RCC_IT_HSERDY) || \
+                            ((IT) == RCC_IT_PLLRDY) || ((IT) == RCC_IT_CSS) || \
+                            ((IT) == RCC_IT_PLL2RDY) || ((IT) == RCC_IT_PLL3RDY))
+ #define IS_RCC_CLEAR_IT(IT) ((IT) != 0x00)
+#endif /* STM32F10X_CL */ 
+
+
+/**
+  * @}
+  */
+
+#ifndef STM32F10X_CL
+/** @defgroup USB_Device_clock_source 
+  * @{
+  */
+
+ #define RCC_USBCLKSource_PLLCLK_1Div5   ((uint8_t)0x00)
+ #define RCC_USBCLKSource_PLLCLK_Div1    ((uint8_t)0x01)
+
+ #define IS_RCC_USBCLK_SOURCE(SOURCE) (((SOURCE) == RCC_USBCLKSource_PLLCLK_1Div5) || \
+                                      ((SOURCE) == RCC_USBCLKSource_PLLCLK_Div1))
+/**
+  * @}
+  */
+#else
+/** @defgroup USB_OTG_FS_clock_source 
+  * @{
+  */
+ #define RCC_OTGFSCLKSource_PLLVCO_Div3    ((uint8_t)0x00)
+ #define RCC_OTGFSCLKSource_PLLVCO_Div2    ((uint8_t)0x01)
+
+ #define IS_RCC_OTGFSCLK_SOURCE(SOURCE) (((SOURCE) == RCC_OTGFSCLKSource_PLLVCO_Div3) || \
+                                         ((SOURCE) == RCC_OTGFSCLKSource_PLLVCO_Div2))
+/**
+  * @}
+  */
+#endif /* STM32F10X_CL */ 
+
+
+#ifdef STM32F10X_CL
+/** @defgroup I2S2_clock_source 
+  * @{
+  */
+ #define RCC_I2S2CLKSource_SYSCLK        ((uint8_t)0x00)
+ #define RCC_I2S2CLKSource_PLL3_VCO      ((uint8_t)0x01)
+
+ #define IS_RCC_I2S2CLK_SOURCE(SOURCE) (((SOURCE) == RCC_I2S2CLKSource_SYSCLK) || \
+                                        ((SOURCE) == RCC_I2S2CLKSource_PLL3_VCO))
+/**
+  * @}
+  */
+
+/** @defgroup I2S3_clock_source 
+  * @{
+  */
+ #define RCC_I2S3CLKSource_SYSCLK        ((uint8_t)0x00)
+ #define RCC_I2S3CLKSource_PLL3_VCO      ((uint8_t)0x01)
+
+ #define IS_RCC_I2S3CLK_SOURCE(SOURCE) (((SOURCE) == RCC_I2S3CLKSource_SYSCLK) || \
+                                        ((SOURCE) == RCC_I2S3CLKSource_PLL3_VCO))    
+/**
+  * @}
+  */
+#endif /* STM32F10X_CL */  
+  
+
+/** @defgroup ADC_clock_source 
+  * @{
+  */
+
+#define RCC_PCLK2_Div2                   ((uint32_t)0x00000000)
+#define RCC_PCLK2_Div4                   ((uint32_t)0x00004000)
+#define RCC_PCLK2_Div6                   ((uint32_t)0x00008000)
+#define RCC_PCLK2_Div8                   ((uint32_t)0x0000C000)
+#define IS_RCC_ADCCLK(ADCCLK) (((ADCCLK) == RCC_PCLK2_Div2) || ((ADCCLK) == RCC_PCLK2_Div4) || \
+                               ((ADCCLK) == RCC_PCLK2_Div6) || ((ADCCLK) == RCC_PCLK2_Div8))
+/**
+  * @}
+  */
+
+/** @defgroup LSE_configuration 
+  * @{
+  */
+
+#define RCC_LSE_OFF                      ((uint8_t)0x00)
+#define RCC_LSE_ON                       ((uint8_t)0x01)
+#define RCC_LSE_Bypass                   ((uint8_t)0x04)
+#define IS_RCC_LSE(LSE) (((LSE) == RCC_LSE_OFF) || ((LSE) == RCC_LSE_ON) || \
+                         ((LSE) == RCC_LSE_Bypass))
+/**
+  * @}
+  */
+
+/** @defgroup RTC_clock_source 
+  * @{
+  */
+
+#define RCC_RTCCLKSource_LSE             ((uint32_t)0x00000100)
+#define RCC_RTCCLKSource_LSI             ((uint32_t)0x00000200)
+#define RCC_RTCCLKSource_HSE_Div128      ((uint32_t)0x00000300)
+#define IS_RCC_RTCCLK_SOURCE(SOURCE) (((SOURCE) == RCC_RTCCLKSource_LSE) || \
+                                      ((SOURCE) == RCC_RTCCLKSource_LSI) || \
+                                      ((SOURCE) == RCC_RTCCLKSource_HSE_Div128))
+/**
+  * @}
+  */
+
+/** @defgroup AHB_peripheral 
+  * @{
+  */
+
+#define RCC_AHBPeriph_DMA1               ((uint32_t)0x00000001)
+#define RCC_AHBPeriph_DMA2               ((uint32_t)0x00000002)
+#define RCC_AHBPeriph_SRAM               ((uint32_t)0x00000004)
+#define RCC_AHBPeriph_FLITF              ((uint32_t)0x00000010)
+#define RCC_AHBPeriph_CRC                ((uint32_t)0x00000040)
+
+#ifndef STM32F10X_CL
+ #define RCC_AHBPeriph_FSMC              ((uint32_t)0x00000100)
+ #define RCC_AHBPeriph_SDIO              ((uint32_t)0x00000400)
+ #define IS_RCC_AHB_PERIPH(PERIPH) ((((PERIPH) & 0xFFFFFAA8) == 0x00) && ((PERIPH) != 0x00))
+#else
+ #define RCC_AHBPeriph_OTG_FS            ((uint32_t)0x00001000)
+ #define RCC_AHBPeriph_ETH_MAC           ((uint32_t)0x00004000)
+ #define RCC_AHBPeriph_ETH_MAC_Tx        ((uint32_t)0x00008000)
+ #define RCC_AHBPeriph_ETH_MAC_Rx        ((uint32_t)0x00010000)
+
+ #define IS_RCC_AHB_PERIPH(PERIPH) ((((PERIPH) & 0xFFFE2FA8) == 0x00) && ((PERIPH) != 0x00))
+ #define IS_RCC_AHB_PERIPH_RESET(PERIPH) ((((PERIPH) & 0xFFFFAFFF) == 0x00) && ((PERIPH) != 0x00))
+#endif /* STM32F10X_CL */
+/**
+  * @}
+  */
+
+/** @defgroup APB2_peripheral 
+  * @{
+  */
+
+#define RCC_APB2Periph_AFIO              ((uint32_t)0x00000001)
+#define RCC_APB2Periph_GPIOA             ((uint32_t)0x00000004)
+#define RCC_APB2Periph_GPIOB             ((uint32_t)0x00000008)
+#define RCC_APB2Periph_GPIOC             ((uint32_t)0x00000010)
+#define RCC_APB2Periph_GPIOD             ((uint32_t)0x00000020)
+#define RCC_APB2Periph_GPIOE             ((uint32_t)0x00000040)
+#define RCC_APB2Periph_GPIOF             ((uint32_t)0x00000080)
+#define RCC_APB2Periph_GPIOG             ((uint32_t)0x00000100)
+#define RCC_APB2Periph_ADC1              ((uint32_t)0x00000200)
+#define RCC_APB2Periph_ADC2              ((uint32_t)0x00000400)
+#define RCC_APB2Periph_TIM1              ((uint32_t)0x00000800)
+#define RCC_APB2Periph_SPI1              ((uint32_t)0x00001000)
+#define RCC_APB2Periph_TIM8              ((uint32_t)0x00002000)
+#define RCC_APB2Periph_USART1            ((uint32_t)0x00004000)
+#define RCC_APB2Periph_ADC3              ((uint32_t)0x00008000)
+#define RCC_APB2Periph_TIM15             ((uint32_t)0x00010000)
+#define RCC_APB2Periph_TIM16             ((uint32_t)0x00020000)
+#define RCC_APB2Periph_TIM17             ((uint32_t)0x00040000)
+#define RCC_APB2Periph_TIM9              ((uint32_t)0x00080000)
+#define RCC_APB2Periph_TIM10             ((uint32_t)0x00100000)
+#define RCC_APB2Periph_TIM11             ((uint32_t)0x00200000)
+
+#define IS_RCC_APB2_PERIPH(PERIPH) ((((PERIPH) & 0xFFC00002) == 0x00) && ((PERIPH) != 0x00))
+/**
+  * @}
+  */ 
+
+/** @defgroup APB1_peripheral 
+  * @{
+  */
+
+#define RCC_APB1Periph_TIM2              ((uint32_t)0x00000001)
+#define RCC_APB1Periph_TIM3              ((uint32_t)0x00000002)
+#define RCC_APB1Periph_TIM4              ((uint32_t)0x00000004)
+#define RCC_APB1Periph_TIM5              ((uint32_t)0x00000008)
+#define RCC_APB1Periph_TIM6              ((uint32_t)0x00000010)
+#define RCC_APB1Periph_TIM7              ((uint32_t)0x00000020)
+#define RCC_APB1Periph_TIM12             ((uint32_t)0x00000040)
+#define RCC_APB1Periph_TIM13             ((uint32_t)0x00000080)
+#define RCC_APB1Periph_TIM14             ((uint32_t)0x00000100)
+#define RCC_APB1Periph_WWDG              ((uint32_t)0x00000800)
+#define RCC_APB1Periph_SPI2              ((uint32_t)0x00004000)
+#define RCC_APB1Periph_SPI3              ((uint32_t)0x00008000)
+#define RCC_APB1Periph_USART2            ((uint32_t)0x00020000)
+#define RCC_APB1Periph_USART3            ((uint32_t)0x00040000)
+#define RCC_APB1Periph_UART4             ((uint32_t)0x00080000)
+#define RCC_APB1Periph_UART5             ((uint32_t)0x00100000)
+#define RCC_APB1Periph_I2C1              ((uint32_t)0x00200000)
+#define RCC_APB1Periph_I2C2              ((uint32_t)0x00400000)
+#define RCC_APB1Periph_USB               ((uint32_t)0x00800000)
+#define RCC_APB1Periph_CAN1              ((uint32_t)0x02000000)
+#define RCC_APB1Periph_CAN2              ((uint32_t)0x04000000)
+#define RCC_APB1Periph_BKP               ((uint32_t)0x08000000)
+#define RCC_APB1Periph_PWR               ((uint32_t)0x10000000)
+#define RCC_APB1Periph_DAC               ((uint32_t)0x20000000)
+#define RCC_APB1Periph_CEC               ((uint32_t)0x40000000)
+ 
+#define IS_RCC_APB1_PERIPH(PERIPH) ((((PERIPH) & 0x81013600) == 0x00) && ((PERIPH) != 0x00))
+
+/**
+  * @}
+  */
+
+/** @defgroup Clock_source_to_output_on_MCO_pin 
+  * @{
+  */
+
+#define RCC_MCO_NoClock                  ((uint8_t)0x00)
+#define RCC_MCO_SYSCLK                   ((uint8_t)0x04)
+#define RCC_MCO_HSI                      ((uint8_t)0x05)
+#define RCC_MCO_HSE                      ((uint8_t)0x06)
+#define RCC_MCO_PLLCLK_Div2              ((uint8_t)0x07)
+
+#ifndef STM32F10X_CL
+ #define IS_RCC_MCO(MCO) (((MCO) == RCC_MCO_NoClock) || ((MCO) == RCC_MCO_HSI) || \
+                          ((MCO) == RCC_MCO_SYSCLK)  || ((MCO) == RCC_MCO_HSE) || \
+                          ((MCO) == RCC_MCO_PLLCLK_Div2))
+#else
+ #define RCC_MCO_PLL2CLK                 ((uint8_t)0x08)
+ #define RCC_MCO_PLL3CLK_Div2            ((uint8_t)0x09)
+ #define RCC_MCO_XT1                     ((uint8_t)0x0A)
+ #define RCC_MCO_PLL3CLK                 ((uint8_t)0x0B)
+
+ #define IS_RCC_MCO(MCO) (((MCO) == RCC_MCO_NoClock) || ((MCO) == RCC_MCO_HSI) || \
+                          ((MCO) == RCC_MCO_SYSCLK)  || ((MCO) == RCC_MCO_HSE) || \
+                          ((MCO) == RCC_MCO_PLLCLK_Div2) || ((MCO) == RCC_MCO_PLL2CLK) || \
+                          ((MCO) == RCC_MCO_PLL3CLK_Div2) || ((MCO) == RCC_MCO_XT1) || \
+                          ((MCO) == RCC_MCO_PLL3CLK))
+#endif /* STM32F10X_CL */ 
+
+/**
+  * @}
+  */
+
+/** @defgroup RCC_Flag 
+  * @{
+  */
+
+#define RCC_FLAG_HSIRDY                  ((uint8_t)0x21)
+#define RCC_FLAG_HSERDY                  ((uint8_t)0x31)
+#define RCC_FLAG_PLLRDY                  ((uint8_t)0x39)
+#define RCC_FLAG_LSERDY                  ((uint8_t)0x41)
+#define RCC_FLAG_LSIRDY                  ((uint8_t)0x61)
+#define RCC_FLAG_PINRST                  ((uint8_t)0x7A)
+#define RCC_FLAG_PORRST                  ((uint8_t)0x7B)
+#define RCC_FLAG_SFTRST                  ((uint8_t)0x7C)
+#define RCC_FLAG_IWDGRST                 ((uint8_t)0x7D)
+#define RCC_FLAG_WWDGRST                 ((uint8_t)0x7E)
+#define RCC_FLAG_LPWRRST                 ((uint8_t)0x7F)
+
+#ifndef STM32F10X_CL
+ #define IS_RCC_FLAG(FLAG) (((FLAG) == RCC_FLAG_HSIRDY) || ((FLAG) == RCC_FLAG_HSERDY) || \
+                            ((FLAG) == RCC_FLAG_PLLRDY) || ((FLAG) == RCC_FLAG_LSERDY) || \
+                            ((FLAG) == RCC_FLAG_LSIRDY) || ((FLAG) == RCC_FLAG_PINRST) || \
+                            ((FLAG) == RCC_FLAG_PORRST) || ((FLAG) == RCC_FLAG_SFTRST) || \
+                            ((FLAG) == RCC_FLAG_IWDGRST)|| ((FLAG) == RCC_FLAG_WWDGRST)|| \
+                            ((FLAG) == RCC_FLAG_LPWRRST))
+#else
+ #define RCC_FLAG_PLL2RDY                ((uint8_t)0x3B) 
+ #define RCC_FLAG_PLL3RDY                ((uint8_t)0x3D) 
+ #define IS_RCC_FLAG(FLAG) (((FLAG) == RCC_FLAG_HSIRDY) || ((FLAG) == RCC_FLAG_HSERDY) || \
+                            ((FLAG) == RCC_FLAG_PLLRDY) || ((FLAG) == RCC_FLAG_LSERDY) || \
+                            ((FLAG) == RCC_FLAG_PLL2RDY) || ((FLAG) == RCC_FLAG_PLL3RDY) || \
+                            ((FLAG) == RCC_FLAG_LSIRDY) || ((FLAG) == RCC_FLAG_PINRST) || \
+                            ((FLAG) == RCC_FLAG_PORRST) || ((FLAG) == RCC_FLAG_SFTRST) || \
+                            ((FLAG) == RCC_FLAG_IWDGRST)|| ((FLAG) == RCC_FLAG_WWDGRST)|| \
+                            ((FLAG) == RCC_FLAG_LPWRRST))
+#endif /* STM32F10X_CL */ 
+
+#define IS_RCC_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x1F)
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup RCC_Exported_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup RCC_Exported_Functions
+  * @{
+  */
+
+void RCC_DeInit(void);
+void RCC_HSEConfig(uint32_t RCC_HSE);
+ErrorStatus RCC_WaitForHSEStartUp(void);
+void RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue);
+void RCC_HSICmd(FunctionalState NewState);
+void RCC_PLLConfig(uint32_t RCC_PLLSource, uint32_t RCC_PLLMul);
+void RCC_PLLCmd(FunctionalState NewState);
+
+#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) || defined (STM32F10X_CL)
+ void RCC_PREDIV1Config(uint32_t RCC_PREDIV1_Source, uint32_t RCC_PREDIV1_Div);
+#endif
+
+#ifdef  STM32F10X_CL
+ void RCC_PREDIV2Config(uint32_t RCC_PREDIV2_Div);
+ void RCC_PLL2Config(uint32_t RCC_PLL2Mul);
+ void RCC_PLL2Cmd(FunctionalState NewState);
+ void RCC_PLL3Config(uint32_t RCC_PLL3Mul);
+ void RCC_PLL3Cmd(FunctionalState NewState);
+#endif /* STM32F10X_CL */ 
+
+void RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource);
+uint8_t RCC_GetSYSCLKSource(void);
+void RCC_HCLKConfig(uint32_t RCC_SYSCLK);
+void RCC_PCLK1Config(uint32_t RCC_HCLK);
+void RCC_PCLK2Config(uint32_t RCC_HCLK);
+void RCC_ITConfig(uint8_t RCC_IT, FunctionalState NewState);
+
+#ifndef STM32F10X_CL
+ void RCC_USBCLKConfig(uint32_t RCC_USBCLKSource);
+#else
+ void RCC_OTGFSCLKConfig(uint32_t RCC_OTGFSCLKSource);
+#endif /* STM32F10X_CL */ 
+
+void RCC_ADCCLKConfig(uint32_t RCC_PCLK2);
+
+#ifdef STM32F10X_CL
+ void RCC_I2S2CLKConfig(uint32_t RCC_I2S2CLKSource);                                  
+ void RCC_I2S3CLKConfig(uint32_t RCC_I2S3CLKSource);
+#endif /* STM32F10X_CL */ 
+
+void RCC_LSEConfig(uint8_t RCC_LSE);
+void RCC_LSICmd(FunctionalState NewState);
+void RCC_RTCCLKConfig(uint32_t RCC_RTCCLKSource);
+void RCC_RTCCLKCmd(FunctionalState NewState);
+void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks);
+void RCC_AHBPeriphClockCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState);
+void RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph, FunctionalState NewState);
+void RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph, FunctionalState NewState);
+
+#ifdef STM32F10X_CL
+void RCC_AHBPeriphResetCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState);
+#endif /* STM32F10X_CL */ 
+
+void RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph, FunctionalState NewState);
+void RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph, FunctionalState NewState);
+void RCC_BackupResetCmd(FunctionalState NewState);
+void RCC_ClockSecuritySystemCmd(FunctionalState NewState);
+void RCC_MCOConfig(uint8_t RCC_MCO);
+FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG);
+void RCC_ClearFlag(void);
+ITStatus RCC_GetITStatus(uint8_t RCC_IT);
+void RCC_ClearITPendingBit(uint8_t RCC_IT);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F10x_RCC_H */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */ 
+
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/STM32_4路称重_Git提交精简工程/src/STM32F10x_FWLib/inc/stm32f10x_rtc.h b/STM32_4路称重_Git提交精简工程/src/STM32F10x_FWLib/inc/stm32f10x_rtc.h
new file mode 100755
index 0000000..214a589
--- /dev/null
+++ b/STM32_4路称重_Git提交精简工程/src/STM32F10x_FWLib/inc/stm32f10x_rtc.h
@@ -0,0 +1,135 @@
+/**
+  ******************************************************************************
+  * @file    stm32f10x_rtc.h
+  * @author  MCD Application Team
+  * @version V3.5.0
+  * @date    11-March-2011
+  * @brief   This file contains all the functions prototypes for the RTC firmware 
+  *          library.
+  ******************************************************************************
+  * @attention
+  *
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+  *
+  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F10x_RTC_H
+#define __STM32F10x_RTC_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x.h"
+
+/** @addtogroup STM32F10x_StdPeriph_Driver
+  * @{
+  */
+
+/** @addtogroup RTC
+  * @{
+  */ 
+
+/** @defgroup RTC_Exported_Types
+  * @{
+  */ 
+
+/**
+  * @}
+  */ 
+
+/** @defgroup RTC_Exported_Constants
+  * @{
+  */
+
+/** @defgroup RTC_interrupts_define 
+  * @{
+  */
+
+#define RTC_IT_OW            ((uint16_t)0x0004)  /*!< Overflow interrupt */
+#define RTC_IT_ALR           ((uint16_t)0x0002)  /*!< Alarm interrupt */
+#define RTC_IT_SEC           ((uint16_t)0x0001)  /*!< Second interrupt */
+#define IS_RTC_IT(IT) ((((IT) & (uint16_t)0xFFF8) == 0x00) && ((IT) != 0x00))
+#define IS_RTC_GET_IT(IT) (((IT) == RTC_IT_OW) || ((IT) == RTC_IT_ALR) || \
+                           ((IT) == RTC_IT_SEC))
+/**
+  * @}
+  */ 
+
+/** @defgroup RTC_interrupts_flags 
+  * @{
+  */
+
+#define RTC_FLAG_RTOFF       ((uint16_t)0x0020)  /*!< RTC Operation OFF flag */
+#define RTC_FLAG_RSF         ((uint16_t)0x0008)  /*!< Registers Synchronized flag */
+#define RTC_FLAG_OW          ((uint16_t)0x0004)  /*!< Overflow flag */
+#define RTC_FLAG_ALR         ((uint16_t)0x0002)  /*!< Alarm flag */
+#define RTC_FLAG_SEC         ((uint16_t)0x0001)  /*!< Second flag */
+#define IS_RTC_CLEAR_FLAG(FLAG) ((((FLAG) & (uint16_t)0xFFF0) == 0x00) && ((FLAG) != 0x00))
+#define IS_RTC_GET_FLAG(FLAG) (((FLAG) == RTC_FLAG_RTOFF) || ((FLAG) == RTC_FLAG_RSF) || \
+                               ((FLAG) == RTC_FLAG_OW) || ((FLAG) == RTC_FLAG_ALR) || \
+                               ((FLAG) == RTC_FLAG_SEC))
+#define IS_RTC_PRESCALER(PRESCALER) ((PRESCALER) <= 0xFFFFF)
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup RTC_Exported_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup RTC_Exported_Functions
+  * @{
+  */
+
+void RTC_ITConfig(uint16_t RTC_IT, FunctionalState NewState);
+void RTC_EnterConfigMode(void);
+void RTC_ExitConfigMode(void);
+uint32_t  RTC_GetCounter(void);
+void RTC_SetCounter(uint32_t CounterValue);
+void RTC_SetPrescaler(uint32_t PrescalerValue);
+void RTC_SetAlarm(uint32_t AlarmValue);
+uint32_t  RTC_GetDivider(void);
+void RTC_WaitForLastTask(void);
+void RTC_WaitForSynchro(void);
+FlagStatus RTC_GetFlagStatus(uint16_t RTC_FLAG);
+void RTC_ClearFlag(uint16_t RTC_FLAG);
+ITStatus RTC_GetITStatus(uint16_t RTC_IT);
+void RTC_ClearITPendingBit(uint16_t RTC_IT);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F10x_RTC_H */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/STM32_4路称重_Git提交精简工程/src/STM32F10x_FWLib/inc/stm32f10x_sdio.h b/STM32_4路称重_Git提交精简工程/src/STM32F10x_FWLib/inc/stm32f10x_sdio.h
new file mode 100755
index 0000000..40cfded
--- /dev/null
+++ b/STM32_4路称重_Git提交精简工程/src/STM32F10x_FWLib/inc/stm32f10x_sdio.h
@@ -0,0 +1,531 @@
+/**
+  ******************************************************************************
+  * @file    stm32f10x_sdio.h
+  * @author  MCD Application Team
+  * @version V3.5.0
+  * @date    11-March-2011
+  * @brief   This file contains all the functions prototypes for the SDIO firmware
+  *          library.
+  ******************************************************************************
+  * @attention
+  *
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+  *
+  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F10x_SDIO_H
+#define __STM32F10x_SDIO_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x.h"
+
+/** @addtogroup STM32F10x_StdPeriph_Driver
+  * @{
+  */
+
+/** @addtogroup SDIO
+  * @{
+  */
+
+/** @defgroup SDIO_Exported_Types
+  * @{
+  */
+
+typedef struct
+{
+  uint32_t SDIO_ClockEdge;            /*!< Specifies the clock transition on which the bit capture is made.
+                                           This parameter can be a value of @ref SDIO_Clock_Edge */
+
+  uint32_t SDIO_ClockBypass;          /*!< Specifies whether the SDIO Clock divider bypass is
+                                           enabled or disabled.
+                                           This parameter can be a value of @ref SDIO_Clock_Bypass */
+
+  uint32_t SDIO_ClockPowerSave;       /*!< Specifies whether SDIO Clock output is enabled or
+                                           disabled when the bus is idle.
+                                           This parameter can be a value of @ref SDIO_Clock_Power_Save */
+
+  uint32_t SDIO_BusWide;              /*!< Specifies the SDIO bus width.
+                                           This parameter can be a value of @ref SDIO_Bus_Wide */
+
+  uint32_t SDIO_HardwareFlowControl;  /*!< Specifies whether the SDIO hardware flow control is enabled or disabled.
+                                           This parameter can be a value of @ref SDIO_Hardware_Flow_Control */
+
+  uint8_t SDIO_ClockDiv;              /*!< Specifies the clock frequency of the SDIO controller.
+                                           This parameter can be a value between 0x00 and 0xFF. */
+                                           
+} SDIO_InitTypeDef;
+
+typedef struct
+{
+  uint32_t SDIO_Argument;  /*!< Specifies the SDIO command argument which is sent
+                                to a card as part of a command message. If a command
+                                contains an argument, it must be loaded into this register
+                                before writing the command to the command register */
+
+  uint32_t SDIO_CmdIndex;  /*!< Specifies the SDIO command index. It must be lower than 0x40. */
+
+  uint32_t SDIO_Response;  /*!< Specifies the SDIO response type.
+                                This parameter can be a value of @ref SDIO_Response_Type */
+
+  uint32_t SDIO_Wait;      /*!< Specifies whether SDIO wait-for-interrupt request is enabled or disabled.
+                                This parameter can be a value of @ref SDIO_Wait_Interrupt_State */
+
+  uint32_t SDIO_CPSM;      /*!< Specifies whether SDIO Command path state machine (CPSM)
+                                is enabled or disabled.
+                                This parameter can be a value of @ref SDIO_CPSM_State */
+} SDIO_CmdInitTypeDef;
+
+typedef struct
+{
+  uint32_t SDIO_DataTimeOut;    /*!< Specifies the data timeout period in card bus clock periods. */
+
+  uint32_t SDIO_DataLength;     /*!< Specifies the number of data bytes to be transferred. */
+ 
+  uint32_t SDIO_DataBlockSize;  /*!< Specifies the data block size for block transfer.
+                                     This parameter can be a value of @ref SDIO_Data_Block_Size */
+ 
+  uint32_t SDIO_TransferDir;    /*!< Specifies the data transfer direction, whether the transfer
+                                     is a read or write.
+                                     This parameter can be a value of @ref SDIO_Transfer_Direction */
+ 
+  uint32_t SDIO_TransferMode;   /*!< Specifies whether data transfer is in stream or block mode.
+                                     This parameter can be a value of @ref SDIO_Transfer_Type */
+ 
+  uint32_t SDIO_DPSM;           /*!< Specifies whether SDIO Data path state machine (DPSM)
+                                     is enabled or disabled.
+                                     This parameter can be a value of @ref SDIO_DPSM_State */
+} SDIO_DataInitTypeDef;
+
+/**
+  * @}
+  */ 
+
+/** @defgroup SDIO_Exported_Constants
+  * @{
+  */
+
+/** @defgroup SDIO_Clock_Edge 
+  * @{
+  */
+
+#define SDIO_ClockEdge_Rising               ((uint32_t)0x00000000)
+#define SDIO_ClockEdge_Falling              ((uint32_t)0x00002000)
+#define IS_SDIO_CLOCK_EDGE(EDGE) (((EDGE) == SDIO_ClockEdge_Rising) || \
+                                  ((EDGE) == SDIO_ClockEdge_Falling))
+/**
+  * @}
+  */
+
+/** @defgroup SDIO_Clock_Bypass 
+  * @{
+  */
+
+#define SDIO_ClockBypass_Disable             ((uint32_t)0x00000000)
+#define SDIO_ClockBypass_Enable              ((uint32_t)0x00000400)    
+#define IS_SDIO_CLOCK_BYPASS(BYPASS) (((BYPASS) == SDIO_ClockBypass_Disable) || \
+                                     ((BYPASS) == SDIO_ClockBypass_Enable))
+/**
+  * @}
+  */ 
+
+/** @defgroup SDIO_Clock_Power_Save 
+  * @{
+  */
+
+#define SDIO_ClockPowerSave_Disable         ((uint32_t)0x00000000)
+#define SDIO_ClockPowerSave_Enable          ((uint32_t)0x00000200) 
+#define IS_SDIO_CLOCK_POWER_SAVE(SAVE) (((SAVE) == SDIO_ClockPowerSave_Disable) || \
+                                        ((SAVE) == SDIO_ClockPowerSave_Enable))
+/**
+  * @}
+  */
+
+/** @defgroup SDIO_Bus_Wide 
+  * @{
+  */
+
+#define SDIO_BusWide_1b                     ((uint32_t)0x00000000)
+#define SDIO_BusWide_4b                     ((uint32_t)0x00000800)
+#define SDIO_BusWide_8b                     ((uint32_t)0x00001000)
+#define IS_SDIO_BUS_WIDE(WIDE) (((WIDE) == SDIO_BusWide_1b) || ((WIDE) == SDIO_BusWide_4b) || \
+                                ((WIDE) == SDIO_BusWide_8b))
+
+/**
+  * @}
+  */
+
+/** @defgroup SDIO_Hardware_Flow_Control 
+  * @{
+  */
+
+#define SDIO_HardwareFlowControl_Disable    ((uint32_t)0x00000000)
+#define SDIO_HardwareFlowControl_Enable     ((uint32_t)0x00004000)
+#define IS_SDIO_HARDWARE_FLOW_CONTROL(CONTROL) (((CONTROL) == SDIO_HardwareFlowControl_Disable) || \
+                                                ((CONTROL) == SDIO_HardwareFlowControl_Enable))
+/**
+  * @}
+  */
+
+/** @defgroup SDIO_Power_State 
+  * @{
+  */
+
+#define SDIO_PowerState_OFF                 ((uint32_t)0x00000000)
+#define SDIO_PowerState_ON                  ((uint32_t)0x00000003)
+#define IS_SDIO_POWER_STATE(STATE) (((STATE) == SDIO_PowerState_OFF) || ((STATE) == SDIO_PowerState_ON)) 
+/**
+  * @}
+  */ 
+
+
+/** @defgroup SDIO_Interrupt_sources 
+  * @{
+  */
+
+#define SDIO_IT_CCRCFAIL                    ((uint32_t)0x00000001)
+#define SDIO_IT_DCRCFAIL                    ((uint32_t)0x00000002)
+#define SDIO_IT_CTIMEOUT                    ((uint32_t)0x00000004)
+#define SDIO_IT_DTIMEOUT                    ((uint32_t)0x00000008)
+#define SDIO_IT_TXUNDERR                    ((uint32_t)0x00000010)
+#define SDIO_IT_RXOVERR                     ((uint32_t)0x00000020)
+#define SDIO_IT_CMDREND                     ((uint32_t)0x00000040)
+#define SDIO_IT_CMDSENT                     ((uint32_t)0x00000080)
+#define SDIO_IT_DATAEND                     ((uint32_t)0x00000100)
+#define SDIO_IT_STBITERR                    ((uint32_t)0x00000200)
+#define SDIO_IT_DBCKEND                     ((uint32_t)0x00000400)
+#define SDIO_IT_CMDACT                      ((uint32_t)0x00000800)
+#define SDIO_IT_TXACT                       ((uint32_t)0x00001000)
+#define SDIO_IT_RXACT                       ((uint32_t)0x00002000)
+#define SDIO_IT_TXFIFOHE                    ((uint32_t)0x00004000)
+#define SDIO_IT_RXFIFOHF                    ((uint32_t)0x00008000)
+#define SDIO_IT_TXFIFOF                     ((uint32_t)0x00010000)
+#define SDIO_IT_RXFIFOF                     ((uint32_t)0x00020000)
+#define SDIO_IT_TXFIFOE                     ((uint32_t)0x00040000)
+#define SDIO_IT_RXFIFOE                     ((uint32_t)0x00080000)
+#define SDIO_IT_TXDAVL                      ((uint32_t)0x00100000)
+#define SDIO_IT_RXDAVL                      ((uint32_t)0x00200000)
+#define SDIO_IT_SDIOIT                      ((uint32_t)0x00400000)
+#define SDIO_IT_CEATAEND                    ((uint32_t)0x00800000)
+#define IS_SDIO_IT(IT) ((((IT) & (uint32_t)0xFF000000) == 0x00) && ((IT) != (uint32_t)0x00))
+/**
+  * @}
+  */ 
+
+/** @defgroup SDIO_Command_Index
+  * @{
+  */
+
+#define IS_SDIO_CMD_INDEX(INDEX)            ((INDEX) < 0x40)
+/**
+  * @}
+  */
+
+/** @defgroup SDIO_Response_Type 
+  * @{
+  */
+
+#define SDIO_Response_No                    ((uint32_t)0x00000000)
+#define SDIO_Response_Short                 ((uint32_t)0x00000040)
+#define SDIO_Response_Long                  ((uint32_t)0x000000C0)
+#define IS_SDIO_RESPONSE(RESPONSE) (((RESPONSE) == SDIO_Response_No) || \
+                                    ((RESPONSE) == SDIO_Response_Short) || \
+                                    ((RESPONSE) == SDIO_Response_Long))
+/**
+  * @}
+  */
+
+/** @defgroup SDIO_Wait_Interrupt_State 
+  * @{
+  */
+
+#define SDIO_Wait_No                        ((uint32_t)0x00000000) /*!< SDIO No Wait, TimeOut is enabled */
+#define SDIO_Wait_IT                        ((uint32_t)0x00000100) /*!< SDIO Wait Interrupt Request */
+#define SDIO_Wait_Pend                      ((uint32_t)0x00000200) /*!< SDIO Wait End of transfer */
+#define IS_SDIO_WAIT(WAIT) (((WAIT) == SDIO_Wait_No) || ((WAIT) == SDIO_Wait_IT) || \
+                            ((WAIT) == SDIO_Wait_Pend))
+/**
+  * @}
+  */
+
+/** @defgroup SDIO_CPSM_State 
+  * @{
+  */
+
+#define SDIO_CPSM_Disable                    ((uint32_t)0x00000000)
+#define SDIO_CPSM_Enable                     ((uint32_t)0x00000400)
+#define IS_SDIO_CPSM(CPSM) (((CPSM) == SDIO_CPSM_Enable) || ((CPSM) == SDIO_CPSM_Disable))
+/**
+  * @}
+  */ 
+
+/** @defgroup SDIO_Response_Registers 
+  * @{
+  */
+
+#define SDIO_RESP1                          ((uint32_t)0x00000000)
+#define SDIO_RESP2                          ((uint32_t)0x00000004)
+#define SDIO_RESP3                          ((uint32_t)0x00000008)
+#define SDIO_RESP4                          ((uint32_t)0x0000000C)
+#define IS_SDIO_RESP(RESP) (((RESP) == SDIO_RESP1) || ((RESP) == SDIO_RESP2) || \
+                            ((RESP) == SDIO_RESP3) || ((RESP) == SDIO_RESP4))
+/**
+  * @}
+  */
+
+/** @defgroup SDIO_Data_Length 
+  * @{
+  */
+
+#define IS_SDIO_DATA_LENGTH(LENGTH) ((LENGTH) <= 0x01FFFFFF)
+/**
+  * @}
+  */
+
+/** @defgroup SDIO_Data_Block_Size 
+  * @{
+  */
+
+#define SDIO_DataBlockSize_1b               ((uint32_t)0x00000000)
+#define SDIO_DataBlockSize_2b               ((uint32_t)0x00000010)
+#define SDIO_DataBlockSize_4b               ((uint32_t)0x00000020)
+#define SDIO_DataBlockSize_8b               ((uint32_t)0x00000030)
+#define SDIO_DataBlockSize_16b              ((uint32_t)0x00000040)
+#define SDIO_DataBlockSize_32b              ((uint32_t)0x00000050)
+#define SDIO_DataBlockSize_64b              ((uint32_t)0x00000060)
+#define SDIO_DataBlockSize_128b             ((uint32_t)0x00000070)
+#define SDIO_DataBlockSize_256b             ((uint32_t)0x00000080)
+#define SDIO_DataBlockSize_512b             ((uint32_t)0x00000090)
+#define SDIO_DataBlockSize_1024b            ((uint32_t)0x000000A0)
+#define SDIO_DataBlockSize_2048b            ((uint32_t)0x000000B0)
+#define SDIO_DataBlockSize_4096b            ((uint32_t)0x000000C0)
+#define SDIO_DataBlockSize_8192b            ((uint32_t)0x000000D0)
+#define SDIO_DataBlockSize_16384b           ((uint32_t)0x000000E0)
+#define IS_SDIO_BLOCK_SIZE(SIZE) (((SIZE) == SDIO_DataBlockSize_1b) || \
+                                  ((SIZE) == SDIO_DataBlockSize_2b) || \
+                                  ((SIZE) == SDIO_DataBlockSize_4b) || \
+                                  ((SIZE) == SDIO_DataBlockSize_8b) || \
+                                  ((SIZE) == SDIO_DataBlockSize_16b) || \
+                                  ((SIZE) == SDIO_DataBlockSize_32b) || \
+                                  ((SIZE) == SDIO_DataBlockSize_64b) || \
+                                  ((SIZE) == SDIO_DataBlockSize_128b) || \
+                                  ((SIZE) == SDIO_DataBlockSize_256b) || \
+                                  ((SIZE) == SDIO_DataBlockSize_512b) || \
+                                  ((SIZE) == SDIO_DataBlockSize_1024b) || \
+                                  ((SIZE) == SDIO_DataBlockSize_2048b) || \
+                                  ((SIZE) == SDIO_DataBlockSize_4096b) || \
+                                  ((SIZE) == SDIO_DataBlockSize_8192b) || \
+                                  ((SIZE) == SDIO_DataBlockSize_16384b)) 
+/**
+  * @}
+  */
+
+/** @defgroup SDIO_Transfer_Direction 
+  * @{
+  */
+
+#define SDIO_TransferDir_ToCard             ((uint32_t)0x00000000)
+#define SDIO_TransferDir_ToSDIO             ((uint32_t)0x00000002)
+#define IS_SDIO_TRANSFER_DIR(DIR) (((DIR) == SDIO_TransferDir_ToCard) || \
+                                   ((DIR) == SDIO_TransferDir_ToSDIO))
+/**
+  * @}
+  */
+
+/** @defgroup SDIO_Transfer_Type 
+  * @{
+  */
+
+#define SDIO_TransferMode_Block             ((uint32_t)0x00000000)
+#define SDIO_TransferMode_Stream            ((uint32_t)0x00000004)
+#define IS_SDIO_TRANSFER_MODE(MODE) (((MODE) == SDIO_TransferMode_Stream) || \
+                                     ((MODE) == SDIO_TransferMode_Block))
+/**
+  * @}
+  */
+
+/** @defgroup SDIO_DPSM_State 
+  * @{
+  */
+
+#define SDIO_DPSM_Disable                    ((uint32_t)0x00000000)
+#define SDIO_DPSM_Enable                     ((uint32_t)0x00000001)
+#define IS_SDIO_DPSM(DPSM) (((DPSM) == SDIO_DPSM_Enable) || ((DPSM) == SDIO_DPSM_Disable))
+/**
+  * @}
+  */
+
+/** @defgroup SDIO_Flags 
+  * @{
+  */
+
+#define SDIO_FLAG_CCRCFAIL                  ((uint32_t)0x00000001)
+#define SDIO_FLAG_DCRCFAIL                  ((uint32_t)0x00000002)
+#define SDIO_FLAG_CTIMEOUT                  ((uint32_t)0x00000004)
+#define SDIO_FLAG_DTIMEOUT                  ((uint32_t)0x00000008)
+#define SDIO_FLAG_TXUNDERR                  ((uint32_t)0x00000010)
+#define SDIO_FLAG_RXOVERR                   ((uint32_t)0x00000020)
+#define SDIO_FLAG_CMDREND                   ((uint32_t)0x00000040)
+#define SDIO_FLAG_CMDSENT                   ((uint32_t)0x00000080)
+#define SDIO_FLAG_DATAEND                   ((uint32_t)0x00000100)
+#define SDIO_FLAG_STBITERR                  ((uint32_t)0x00000200)
+#define SDIO_FLAG_DBCKEND                   ((uint32_t)0x00000400)
+#define SDIO_FLAG_CMDACT                    ((uint32_t)0x00000800)
+#define SDIO_FLAG_TXACT                     ((uint32_t)0x00001000)
+#define SDIO_FLAG_RXACT                     ((uint32_t)0x00002000)
+#define SDIO_FLAG_TXFIFOHE                  ((uint32_t)0x00004000)
+#define SDIO_FLAG_RXFIFOHF                  ((uint32_t)0x00008000)
+#define SDIO_FLAG_TXFIFOF                   ((uint32_t)0x00010000)
+#define SDIO_FLAG_RXFIFOF                   ((uint32_t)0x00020000)
+#define SDIO_FLAG_TXFIFOE                   ((uint32_t)0x00040000)
+#define SDIO_FLAG_RXFIFOE                   ((uint32_t)0x00080000)
+#define SDIO_FLAG_TXDAVL                    ((uint32_t)0x00100000)
+#define SDIO_FLAG_RXDAVL                    ((uint32_t)0x00200000)
+#define SDIO_FLAG_SDIOIT                    ((uint32_t)0x00400000)
+#define SDIO_FLAG_CEATAEND                  ((uint32_t)0x00800000)
+#define IS_SDIO_FLAG(FLAG) (((FLAG)  == SDIO_FLAG_CCRCFAIL) || \
+                            ((FLAG)  == SDIO_FLAG_DCRCFAIL) || \
+                            ((FLAG)  == SDIO_FLAG_CTIMEOUT) || \
+                            ((FLAG)  == SDIO_FLAG_DTIMEOUT) || \
+                            ((FLAG)  == SDIO_FLAG_TXUNDERR) || \
+                            ((FLAG)  == SDIO_FLAG_RXOVERR) || \
+                            ((FLAG)  == SDIO_FLAG_CMDREND) || \
+                            ((FLAG)  == SDIO_FLAG_CMDSENT) || \
+                            ((FLAG)  == SDIO_FLAG_DATAEND) || \
+                            ((FLAG)  == SDIO_FLAG_STBITERR) || \
+                            ((FLAG)  == SDIO_FLAG_DBCKEND) || \
+                            ((FLAG)  == SDIO_FLAG_CMDACT) || \
+                            ((FLAG)  == SDIO_FLAG_TXACT) || \
+                            ((FLAG)  == SDIO_FLAG_RXACT) || \
+                            ((FLAG)  == SDIO_FLAG_TXFIFOHE) || \
+                            ((FLAG)  == SDIO_FLAG_RXFIFOHF) || \
+                            ((FLAG)  == SDIO_FLAG_TXFIFOF) || \
+                            ((FLAG)  == SDIO_FLAG_RXFIFOF) || \
+                            ((FLAG)  == SDIO_FLAG_TXFIFOE) || \
+                            ((FLAG)  == SDIO_FLAG_RXFIFOE) || \
+                            ((FLAG)  == SDIO_FLAG_TXDAVL) || \
+                            ((FLAG)  == SDIO_FLAG_RXDAVL) || \
+                            ((FLAG)  == SDIO_FLAG_SDIOIT) || \
+                            ((FLAG)  == SDIO_FLAG_CEATAEND))
+
+#define IS_SDIO_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFF3FF800) == 0x00) && ((FLAG) != (uint32_t)0x00))
+
+#define IS_SDIO_GET_IT(IT) (((IT)  == SDIO_IT_CCRCFAIL) || \
+                            ((IT)  == SDIO_IT_DCRCFAIL) || \
+                            ((IT)  == SDIO_IT_CTIMEOUT) || \
+                            ((IT)  == SDIO_IT_DTIMEOUT) || \
+                            ((IT)  == SDIO_IT_TXUNDERR) || \
+                            ((IT)  == SDIO_IT_RXOVERR) || \
+                            ((IT)  == SDIO_IT_CMDREND) || \
+                            ((IT)  == SDIO_IT_CMDSENT) || \
+                            ((IT)  == SDIO_IT_DATAEND) || \
+                            ((IT)  == SDIO_IT_STBITERR) || \
+                            ((IT)  == SDIO_IT_DBCKEND) || \
+                            ((IT)  == SDIO_IT_CMDACT) || \
+                            ((IT)  == SDIO_IT_TXACT) || \
+                            ((IT)  == SDIO_IT_RXACT) || \
+                            ((IT)  == SDIO_IT_TXFIFOHE) || \
+                            ((IT)  == SDIO_IT_RXFIFOHF) || \
+                            ((IT)  == SDIO_IT_TXFIFOF) || \
+                            ((IT)  == SDIO_IT_RXFIFOF) || \
+                            ((IT)  == SDIO_IT_TXFIFOE) || \
+                            ((IT)  == SDIO_IT_RXFIFOE) || \
+                            ((IT)  == SDIO_IT_TXDAVL) || \
+                            ((IT)  == SDIO_IT_RXDAVL) || \
+                            ((IT)  == SDIO_IT_SDIOIT) || \
+                            ((IT)  == SDIO_IT_CEATAEND))
+
+#define IS_SDIO_CLEAR_IT(IT) ((((IT) & (uint32_t)0xFF3FF800) == 0x00) && ((IT) != (uint32_t)0x00))
+
+/**
+  * @}
+  */
+
+/** @defgroup SDIO_Read_Wait_Mode 
+  * @{
+  */
+
+#define SDIO_ReadWaitMode_CLK               ((uint32_t)0x00000001)
+#define SDIO_ReadWaitMode_DATA2             ((uint32_t)0x00000000)
+#define IS_SDIO_READWAIT_MODE(MODE) (((MODE) == SDIO_ReadWaitMode_CLK) || \
+                                     ((MODE) == SDIO_ReadWaitMode_DATA2))
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup SDIO_Exported_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup SDIO_Exported_Functions
+  * @{
+  */
+
+void SDIO_DeInit(void);
+void SDIO_Init(SDIO_InitTypeDef* SDIO_InitStruct);
+void SDIO_StructInit(SDIO_InitTypeDef* SDIO_InitStruct);
+void SDIO_ClockCmd(FunctionalState NewState);
+void SDIO_SetPowerState(uint32_t SDIO_PowerState);
+uint32_t SDIO_GetPowerState(void);
+void SDIO_ITConfig(uint32_t SDIO_IT, FunctionalState NewState);
+void SDIO_DMACmd(FunctionalState NewState);
+void SDIO_SendCommand(SDIO_CmdInitTypeDef *SDIO_CmdInitStruct);
+void SDIO_CmdStructInit(SDIO_CmdInitTypeDef* SDIO_CmdInitStruct);
+uint8_t SDIO_GetCommandResponse(void);
+uint32_t SDIO_GetResponse(uint32_t SDIO_RESP);
+void SDIO_DataConfig(SDIO_DataInitTypeDef* SDIO_DataInitStruct);
+void SDIO_DataStructInit(SDIO_DataInitTypeDef* SDIO_DataInitStruct);
+uint32_t SDIO_GetDataCounter(void);
+uint32_t SDIO_ReadData(void);
+void SDIO_WriteData(uint32_t Data);
+uint32_t SDIO_GetFIFOCount(void);
+void SDIO_StartSDIOReadWait(FunctionalState NewState);
+void SDIO_StopSDIOReadWait(FunctionalState NewState);
+void SDIO_SetSDIOReadWaitMode(uint32_t SDIO_ReadWaitMode);
+void SDIO_SetSDIOOperation(FunctionalState NewState);
+void SDIO_SendSDIOSuspendCmd(FunctionalState NewState);
+void SDIO_CommandCompletionCmd(FunctionalState NewState);
+void SDIO_CEATAITCmd(FunctionalState NewState);
+void SDIO_SendCEATACmd(FunctionalState NewState);
+FlagStatus SDIO_GetFlagStatus(uint32_t SDIO_FLAG);
+void SDIO_ClearFlag(uint32_t SDIO_FLAG);
+ITStatus SDIO_GetITStatus(uint32_t SDIO_IT);
+void SDIO_ClearITPendingBit(uint32_t SDIO_IT);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F10x_SDIO_H */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/STM32_4路称重_Git提交精简工程/src/STM32F10x_FWLib/inc/stm32f10x_spi.h b/STM32_4路称重_Git提交精简工程/src/STM32F10x_FWLib/inc/stm32f10x_spi.h
new file mode 100755
index 0000000..6056c4c
--- /dev/null
+++ b/STM32_4路称重_Git提交精简工程/src/STM32F10x_FWLib/inc/stm32f10x_spi.h
@@ -0,0 +1,487 @@
+/**
+  ******************************************************************************
+  * @file    stm32f10x_spi.h
+  * @author  MCD Application Team
+  * @version V3.5.0
+  * @date    11-March-2011
+  * @brief   This file contains all the functions prototypes for the SPI firmware 
+  *          library.
+  ******************************************************************************
+  * @attention
+  *
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+  *
+  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F10x_SPI_H
+#define __STM32F10x_SPI_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x.h"
+
+/** @addtogroup STM32F10x_StdPeriph_Driver
+  * @{
+  */
+
+/** @addtogroup SPI
+  * @{
+  */ 
+
+/** @defgroup SPI_Exported_Types
+  * @{
+  */
+
+/** 
+  * @brief  SPI Init structure definition  
+  */
+
+typedef struct
+{
+  uint16_t SPI_Direction;           /*!< Specifies the SPI unidirectional or bidirectional data mode.
+                                         This parameter can be a value of @ref SPI_data_direction */
+
+  uint16_t SPI_Mode;                /*!< Specifies the SPI operating mode.
+                                         This parameter can be a value of @ref SPI_mode */
+
+  uint16_t SPI_DataSize;            /*!< Specifies the SPI data size.
+                                         This parameter can be a value of @ref SPI_data_size */
+
+  uint16_t SPI_CPOL;                /*!< Specifies the serial clock steady state.
+                                         This parameter can be a value of @ref SPI_Clock_Polarity */
+
+  uint16_t SPI_CPHA;                /*!< Specifies the clock active edge for the bit capture.
+                                         This parameter can be a value of @ref SPI_Clock_Phase */
+
+  uint16_t SPI_NSS;                 /*!< Specifies whether the NSS signal is managed by
+                                         hardware (NSS pin) or by software using the SSI bit.
+                                         This parameter can be a value of @ref SPI_Slave_Select_management */
+ 
+  uint16_t SPI_BaudRatePrescaler;   /*!< Specifies the Baud Rate prescaler value which will be
+                                         used to configure the transmit and receive SCK clock.
+                                         This parameter can be a value of @ref SPI_BaudRate_Prescaler.
+                                         @note The communication clock is derived from the master
+                                               clock. The slave clock does not need to be set. */
+
+  uint16_t SPI_FirstBit;            /*!< Specifies whether data transfers start from MSB or LSB bit.
+                                         This parameter can be a value of @ref SPI_MSB_LSB_transmission */
+
+  uint16_t SPI_CRCPolynomial;       /*!< Specifies the polynomial used for the CRC calculation. */
+}SPI_InitTypeDef;
+
+/** 
+  * @brief  I2S Init structure definition  
+  */
+
+typedef struct
+{
+
+  uint16_t I2S_Mode;         /*!< Specifies the I2S operating mode.
+                                  This parameter can be a value of @ref I2S_Mode */
+
+  uint16_t I2S_Standard;     /*!< Specifies the standard used for the I2S communication.
+                                  This parameter can be a value of @ref I2S_Standard */
+
+  uint16_t I2S_DataFormat;   /*!< Specifies the data format for the I2S communication.
+                                  This parameter can be a value of @ref I2S_Data_Format */
+
+  uint16_t I2S_MCLKOutput;   /*!< Specifies whether the I2S MCLK output is enabled or not.
+                                  This parameter can be a value of @ref I2S_MCLK_Output */
+
+  uint32_t I2S_AudioFreq;    /*!< Specifies the frequency selected for the I2S communication.
+                                  This parameter can be a value of @ref I2S_Audio_Frequency */
+
+  uint16_t I2S_CPOL;         /*!< Specifies the idle state of the I2S clock.
+                                  This parameter can be a value of @ref I2S_Clock_Polarity */
+}I2S_InitTypeDef;
+
+/**
+  * @}
+  */
+
+/** @defgroup SPI_Exported_Constants
+  * @{
+  */
+
+#define IS_SPI_ALL_PERIPH(PERIPH) (((PERIPH) == SPI1) || \
+                                   ((PERIPH) == SPI2) || \
+                                   ((PERIPH) == SPI3))
+
+#define IS_SPI_23_PERIPH(PERIPH) (((PERIPH) == SPI2) || \
+                                  ((PERIPH) == SPI3))
+
+/** @defgroup SPI_data_direction 
+  * @{
+  */
+  
+#define SPI_Direction_2Lines_FullDuplex ((uint16_t)0x0000)
+#define SPI_Direction_2Lines_RxOnly     ((uint16_t)0x0400)
+#define SPI_Direction_1Line_Rx          ((uint16_t)0x8000)
+#define SPI_Direction_1Line_Tx          ((uint16_t)0xC000)
+#define IS_SPI_DIRECTION_MODE(MODE) (((MODE) == SPI_Direction_2Lines_FullDuplex) || \
+                                     ((MODE) == SPI_Direction_2Lines_RxOnly) || \
+                                     ((MODE) == SPI_Direction_1Line_Rx) || \
+                                     ((MODE) == SPI_Direction_1Line_Tx))
+/**
+  * @}
+  */
+
+/** @defgroup SPI_mode 
+  * @{
+  */
+
+#define SPI_Mode_Master                 ((uint16_t)0x0104)
+#define SPI_Mode_Slave                  ((uint16_t)0x0000)
+#define IS_SPI_MODE(MODE) (((MODE) == SPI_Mode_Master) || \
+                           ((MODE) == SPI_Mode_Slave))
+/**
+  * @}
+  */
+
+/** @defgroup SPI_data_size 
+  * @{
+  */
+
+#define SPI_DataSize_16b                ((uint16_t)0x0800)
+#define SPI_DataSize_8b                 ((uint16_t)0x0000)
+#define IS_SPI_DATASIZE(DATASIZE) (((DATASIZE) == SPI_DataSize_16b) || \
+                                   ((DATASIZE) == SPI_DataSize_8b))
+/**
+  * @}
+  */ 
+
+/** @defgroup SPI_Clock_Polarity 
+  * @{
+  */
+
+#define SPI_CPOL_Low                    ((uint16_t)0x0000)
+#define SPI_CPOL_High                   ((uint16_t)0x0002)
+#define IS_SPI_CPOL(CPOL) (((CPOL) == SPI_CPOL_Low) || \
+                           ((CPOL) == SPI_CPOL_High))
+/**
+  * @}
+  */
+
+/** @defgroup SPI_Clock_Phase 
+  * @{
+  */
+
+#define SPI_CPHA_1Edge                  ((uint16_t)0x0000)
+#define SPI_CPHA_2Edge                  ((uint16_t)0x0001)
+#define IS_SPI_CPHA(CPHA) (((CPHA) == SPI_CPHA_1Edge) || \
+                           ((CPHA) == SPI_CPHA_2Edge))
+/**
+  * @}
+  */
+
+/** @defgroup SPI_Slave_Select_management 
+  * @{
+  */
+
+#define SPI_NSS_Soft                    ((uint16_t)0x0200)
+#define SPI_NSS_Hard                    ((uint16_t)0x0000)
+#define IS_SPI_NSS(NSS) (((NSS) == SPI_NSS_Soft) || \
+                         ((NSS) == SPI_NSS_Hard))
+/**
+  * @}
+  */ 
+
+/** @defgroup SPI_BaudRate_Prescaler 
+  * @{
+  */
+
+#define SPI_BaudRatePrescaler_2         ((uint16_t)0x0000)
+#define SPI_BaudRatePrescaler_4         ((uint16_t)0x0008)
+#define SPI_BaudRatePrescaler_8         ((uint16_t)0x0010)
+#define SPI_BaudRatePrescaler_16        ((uint16_t)0x0018)
+#define SPI_BaudRatePrescaler_32        ((uint16_t)0x0020)
+#define SPI_BaudRatePrescaler_64        ((uint16_t)0x0028)
+#define SPI_BaudRatePrescaler_128       ((uint16_t)0x0030)
+#define SPI_BaudRatePrescaler_256       ((uint16_t)0x0038)
+#define IS_SPI_BAUDRATE_PRESCALER(PRESCALER) (((PRESCALER) == SPI_BaudRatePrescaler_2) || \
+                                              ((PRESCALER) == SPI_BaudRatePrescaler_4) || \
+                                              ((PRESCALER) == SPI_BaudRatePrescaler_8) || \
+                                              ((PRESCALER) == SPI_BaudRatePrescaler_16) || \
+                                              ((PRESCALER) == SPI_BaudRatePrescaler_32) || \
+                                              ((PRESCALER) == SPI_BaudRatePrescaler_64) || \
+                                              ((PRESCALER) == SPI_BaudRatePrescaler_128) || \
+                                              ((PRESCALER) == SPI_BaudRatePrescaler_256))
+/**
+  * @}
+  */ 
+
+/** @defgroup SPI_MSB_LSB_transmission 
+  * @{
+  */
+
+#define SPI_FirstBit_MSB                ((uint16_t)0x0000)
+#define SPI_FirstBit_LSB                ((uint16_t)0x0080)
+#define IS_SPI_FIRST_BIT(BIT) (((BIT) == SPI_FirstBit_MSB) || \
+                               ((BIT) == SPI_FirstBit_LSB))
+/**
+  * @}
+  */
+
+/** @defgroup I2S_Mode 
+  * @{
+  */
+
+#define I2S_Mode_SlaveTx                ((uint16_t)0x0000)
+#define I2S_Mode_SlaveRx                ((uint16_t)0x0100)
+#define I2S_Mode_MasterTx               ((uint16_t)0x0200)
+#define I2S_Mode_MasterRx               ((uint16_t)0x0300)
+#define IS_I2S_MODE(MODE) (((MODE) == I2S_Mode_SlaveTx) || \
+                           ((MODE) == I2S_Mode_SlaveRx) || \
+                           ((MODE) == I2S_Mode_MasterTx) || \
+                           ((MODE) == I2S_Mode_MasterRx) )
+/**
+  * @}
+  */
+
+/** @defgroup I2S_Standard 
+  * @{
+  */
+
+#define I2S_Standard_Phillips           ((uint16_t)0x0000)
+#define I2S_Standard_MSB                ((uint16_t)0x0010)
+#define I2S_Standard_LSB                ((uint16_t)0x0020)
+#define I2S_Standard_PCMShort           ((uint16_t)0x0030)
+#define I2S_Standard_PCMLong            ((uint16_t)0x00B0)
+#define IS_I2S_STANDARD(STANDARD) (((STANDARD) == I2S_Standard_Phillips) || \
+                                   ((STANDARD) == I2S_Standard_MSB) || \
+                                   ((STANDARD) == I2S_Standard_LSB) || \
+                                   ((STANDARD) == I2S_Standard_PCMShort) || \
+                                   ((STANDARD) == I2S_Standard_PCMLong))
+/**
+  * @}
+  */
+
+/** @defgroup I2S_Data_Format 
+  * @{
+  */
+
+#define I2S_DataFormat_16b              ((uint16_t)0x0000)
+#define I2S_DataFormat_16bextended      ((uint16_t)0x0001)
+#define I2S_DataFormat_24b              ((uint16_t)0x0003)
+#define I2S_DataFormat_32b              ((uint16_t)0x0005)
+#define IS_I2S_DATA_FORMAT(FORMAT) (((FORMAT) == I2S_DataFormat_16b) || \
+                                    ((FORMAT) == I2S_DataFormat_16bextended) || \
+                                    ((FORMAT) == I2S_DataFormat_24b) || \
+                                    ((FORMAT) == I2S_DataFormat_32b))
+/**
+  * @}
+  */ 
+
+/** @defgroup I2S_MCLK_Output 
+  * @{
+  */
+
+#define I2S_MCLKOutput_Enable           ((uint16_t)0x0200)
+#define I2S_MCLKOutput_Disable          ((uint16_t)0x0000)
+#define IS_I2S_MCLK_OUTPUT(OUTPUT) (((OUTPUT) == I2S_MCLKOutput_Enable) || \
+                                    ((OUTPUT) == I2S_MCLKOutput_Disable))
+/**
+  * @}
+  */
+
+/** @defgroup I2S_Audio_Frequency 
+  * @{
+  */
+
+#define I2S_AudioFreq_192k               ((uint32_t)192000)
+#define I2S_AudioFreq_96k                ((uint32_t)96000)
+#define I2S_AudioFreq_48k                ((uint32_t)48000)
+#define I2S_AudioFreq_44k                ((uint32_t)44100)
+#define I2S_AudioFreq_32k                ((uint32_t)32000)
+#define I2S_AudioFreq_22k                ((uint32_t)22050)
+#define I2S_AudioFreq_16k                ((uint32_t)16000)
+#define I2S_AudioFreq_11k                ((uint32_t)11025)
+#define I2S_AudioFreq_8k                 ((uint32_t)8000)
+#define I2S_AudioFreq_Default            ((uint32_t)2)
+
+#define IS_I2S_AUDIO_FREQ(FREQ) ((((FREQ) >= I2S_AudioFreq_8k) && \
+                                  ((FREQ) <= I2S_AudioFreq_192k)) || \
+                                 ((FREQ) == I2S_AudioFreq_Default))
+/**
+  * @}
+  */ 
+
+/** @defgroup I2S_Clock_Polarity 
+  * @{
+  */
+
+#define I2S_CPOL_Low                    ((uint16_t)0x0000)
+#define I2S_CPOL_High                   ((uint16_t)0x0008)
+#define IS_I2S_CPOL(CPOL) (((CPOL) == I2S_CPOL_Low) || \
+                           ((CPOL) == I2S_CPOL_High))
+/**
+  * @}
+  */
+
+/** @defgroup SPI_I2S_DMA_transfer_requests 
+  * @{
+  */
+
+#define SPI_I2S_DMAReq_Tx               ((uint16_t)0x0002)
+#define SPI_I2S_DMAReq_Rx               ((uint16_t)0x0001)
+#define IS_SPI_I2S_DMAREQ(DMAREQ) ((((DMAREQ) & (uint16_t)0xFFFC) == 0x00) && ((DMAREQ) != 0x00))
+/**
+  * @}
+  */
+
+/** @defgroup SPI_NSS_internal_software_management 
+  * @{
+  */
+
+#define SPI_NSSInternalSoft_Set         ((uint16_t)0x0100)
+#define SPI_NSSInternalSoft_Reset       ((uint16_t)0xFEFF)
+#define IS_SPI_NSS_INTERNAL(INTERNAL) (((INTERNAL) == SPI_NSSInternalSoft_Set) || \
+                                       ((INTERNAL) == SPI_NSSInternalSoft_Reset))
+/**
+  * @}
+  */
+
+/** @defgroup SPI_CRC_Transmit_Receive 
+  * @{
+  */
+
+#define SPI_CRC_Tx                      ((uint8_t)0x00)
+#define SPI_CRC_Rx                      ((uint8_t)0x01)
+#define IS_SPI_CRC(CRC) (((CRC) == SPI_CRC_Tx) || ((CRC) == SPI_CRC_Rx))
+/**
+  * @}
+  */
+
+/** @defgroup SPI_direction_transmit_receive 
+  * @{
+  */
+
+#define SPI_Direction_Rx                ((uint16_t)0xBFFF)
+#define SPI_Direction_Tx                ((uint16_t)0x4000)
+#define IS_SPI_DIRECTION(DIRECTION) (((DIRECTION) == SPI_Direction_Rx) || \
+                                     ((DIRECTION) == SPI_Direction_Tx))
+/**
+  * @}
+  */
+
+/** @defgroup SPI_I2S_interrupts_definition 
+  * @{
+  */
+
+#define SPI_I2S_IT_TXE                  ((uint8_t)0x71)
+#define SPI_I2S_IT_RXNE                 ((uint8_t)0x60)
+#define SPI_I2S_IT_ERR                  ((uint8_t)0x50)
+#define IS_SPI_I2S_CONFIG_IT(IT) (((IT) == SPI_I2S_IT_TXE) || \
+                                 ((IT) == SPI_I2S_IT_RXNE) || \
+                                 ((IT) == SPI_I2S_IT_ERR))
+#define SPI_I2S_IT_OVR                  ((uint8_t)0x56)
+#define SPI_IT_MODF                     ((uint8_t)0x55)
+#define SPI_IT_CRCERR                   ((uint8_t)0x54)
+#define I2S_IT_UDR                      ((uint8_t)0x53)
+#define IS_SPI_I2S_CLEAR_IT(IT) (((IT) == SPI_IT_CRCERR))
+#define IS_SPI_I2S_GET_IT(IT) (((IT) == SPI_I2S_IT_RXNE) || ((IT) == SPI_I2S_IT_TXE) || \
+                               ((IT) == I2S_IT_UDR) || ((IT) == SPI_IT_CRCERR) || \
+                               ((IT) == SPI_IT_MODF) || ((IT) == SPI_I2S_IT_OVR))
+/**
+  * @}
+  */
+
+/** @defgroup SPI_I2S_flags_definition 
+  * @{
+  */
+
+#define SPI_I2S_FLAG_RXNE               ((uint16_t)0x0001)
+#define SPI_I2S_FLAG_TXE                ((uint16_t)0x0002)
+#define I2S_FLAG_CHSIDE                 ((uint16_t)0x0004)
+#define I2S_FLAG_UDR                    ((uint16_t)0x0008)
+#define SPI_FLAG_CRCERR                 ((uint16_t)0x0010)
+#define SPI_FLAG_MODF                   ((uint16_t)0x0020)
+#define SPI_I2S_FLAG_OVR                ((uint16_t)0x0040)
+#define SPI_I2S_FLAG_BSY                ((uint16_t)0x0080)
+#define IS_SPI_I2S_CLEAR_FLAG(FLAG) (((FLAG) == SPI_FLAG_CRCERR))
+#define IS_SPI_I2S_GET_FLAG(FLAG) (((FLAG) == SPI_I2S_FLAG_BSY) || ((FLAG) == SPI_I2S_FLAG_OVR) || \
+                                   ((FLAG) == SPI_FLAG_MODF) || ((FLAG) == SPI_FLAG_CRCERR) || \
+                                   ((FLAG) == I2S_FLAG_UDR) || ((FLAG) == I2S_FLAG_CHSIDE) || \
+                                   ((FLAG) == SPI_I2S_FLAG_TXE) || ((FLAG) == SPI_I2S_FLAG_RXNE))
+/**
+  * @}
+  */
+
+/** @defgroup SPI_CRC_polynomial 
+  * @{
+  */
+
+#define IS_SPI_CRC_POLYNOMIAL(POLYNOMIAL) ((POLYNOMIAL) >= 0x1)
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup SPI_Exported_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup SPI_Exported_Functions
+  * @{
+  */
+
+void SPI_I2S_DeInit(SPI_TypeDef* SPIx);
+void SPI_Init(SPI_TypeDef* SPIx, SPI_InitTypeDef* SPI_InitStruct);
+void I2S_Init(SPI_TypeDef* SPIx, I2S_InitTypeDef* I2S_InitStruct);
+void SPI_StructInit(SPI_InitTypeDef* SPI_InitStruct);
+void I2S_StructInit(I2S_InitTypeDef* I2S_InitStruct);
+void SPI_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState);
+void I2S_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState);
+void SPI_I2S_ITConfig(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT, FunctionalState NewState);
+void SPI_I2S_DMACmd(SPI_TypeDef* SPIx, uint16_t SPI_I2S_DMAReq, FunctionalState NewState);
+void SPI_I2S_SendData(SPI_TypeDef* SPIx, uint16_t Data);
+uint16_t SPI_I2S_ReceiveData(SPI_TypeDef* SPIx);
+void SPI_NSSInternalSoftwareConfig(SPI_TypeDef* SPIx, uint16_t SPI_NSSInternalSoft);
+void SPI_SSOutputCmd(SPI_TypeDef* SPIx, FunctionalState NewState);
+void SPI_DataSizeConfig(SPI_TypeDef* SPIx, uint16_t SPI_DataSize);
+void SPI_TransmitCRC(SPI_TypeDef* SPIx);
+void SPI_CalculateCRC(SPI_TypeDef* SPIx, FunctionalState NewState);
+uint16_t SPI_GetCRC(SPI_TypeDef* SPIx, uint8_t SPI_CRC);
+uint16_t SPI_GetCRCPolynomial(SPI_TypeDef* SPIx);
+void SPI_BiDirectionalLineConfig(SPI_TypeDef* SPIx, uint16_t SPI_Direction);
+FlagStatus SPI_I2S_GetFlagStatus(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG);
+void SPI_I2S_ClearFlag(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG);
+ITStatus SPI_I2S_GetITStatus(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT);
+void SPI_I2S_ClearITPendingBit(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__STM32F10x_SPI_H */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/STM32_4路称重_Git提交精简工程/src/STM32F10x_FWLib/inc/stm32f10x_tim.h b/STM32_4路称重_Git提交精简工程/src/STM32F10x_FWLib/inc/stm32f10x_tim.h
new file mode 100755
index 0000000..cd7ac3e
--- /dev/null
+++ b/STM32_4路称重_Git提交精简工程/src/STM32F10x_FWLib/inc/stm32f10x_tim.h
@@ -0,0 +1,1164 @@
+/**
+  ******************************************************************************
+  * @file    stm32f10x_tim.h
+  * @author  MCD Application Team
+  * @version V3.5.0
+  * @date    11-March-2011
+  * @brief   This file contains all the functions prototypes for the TIM firmware 
+  *          library.
+  ******************************************************************************
+  * @attention
+  *
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+  *
+  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F10x_TIM_H
+#define __STM32F10x_TIM_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x.h"
+
+/** @addtogroup STM32F10x_StdPeriph_Driver
+  * @{
+  */
+
+/** @addtogroup TIM
+  * @{
+  */ 
+
+/** @defgroup TIM_Exported_Types
+  * @{
+  */ 
+
+/** 
+  * @brief  TIM Time Base Init structure definition
+  * @note   This structure is used with all TIMx except for TIM6 and TIM7.    
+  */
+
+typedef struct
+{
+  uint16_t TIM_Prescaler;         /*!< Specifies the prescaler value used to divide the TIM clock.
+                                       This parameter can be a number between 0x0000 and 0xFFFF */
+
+  uint16_t TIM_CounterMode;       /*!< Specifies the counter mode.
+                                       This parameter can be a value of @ref TIM_Counter_Mode */
+
+  uint16_t TIM_Period;            /*!< Specifies the period value to be loaded into the active
+                                       Auto-Reload Register at the next update event.
+                                       This parameter must be a number between 0x0000 and 0xFFFF.  */ 
+
+  uint16_t TIM_ClockDivision;     /*!< Specifies the clock division.
+                                      This parameter can be a value of @ref TIM_Clock_Division_CKD */
+
+  uint8_t TIM_RepetitionCounter;  /*!< Specifies the repetition counter value. Each time the RCR downcounter
+                                       reaches zero, an update event is generated and counting restarts
+                                       from the RCR value (N).
+                                       This means in PWM mode that (N+1) corresponds to:
+                                          - the number of PWM periods in edge-aligned mode
+                                          - the number of half PWM period in center-aligned mode
+                                       This parameter must be a number between 0x00 and 0xFF. 
+                                       @note This parameter is valid only for TIM1 and TIM8. */
+} TIM_TimeBaseInitTypeDef;       
+
+/** 
+  * @brief  TIM Output Compare Init structure definition  
+  */
+
+typedef struct
+{
+  uint16_t TIM_OCMode;        /*!< Specifies the TIM mode.
+                                   This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */
+
+  uint16_t TIM_OutputState;   /*!< Specifies the TIM Output Compare state.
+                                   This parameter can be a value of @ref TIM_Output_Compare_state */
+
+  uint16_t TIM_OutputNState;  /*!< Specifies the TIM complementary Output Compare state.
+                                   This parameter can be a value of @ref TIM_Output_Compare_N_state
+                                   @note This parameter is valid only for TIM1 and TIM8. */
+
+  uint16_t TIM_Pulse;         /*!< Specifies the pulse value to be loaded into the Capture Compare Register. 
+                                   This parameter can be a number between 0x0000 and 0xFFFF */
+
+  uint16_t TIM_OCPolarity;    /*!< Specifies the output polarity.
+                                   This parameter can be a value of @ref TIM_Output_Compare_Polarity */
+
+  uint16_t TIM_OCNPolarity;   /*!< Specifies the complementary output polarity.
+                                   This parameter can be a value of @ref TIM_Output_Compare_N_Polarity
+                                   @note This parameter is valid only for TIM1 and TIM8. */
+
+  uint16_t TIM_OCIdleState;   /*!< Specifies the TIM Output Compare pin state during Idle state.
+                                   This parameter can be a value of @ref TIM_Output_Compare_Idle_State
+                                   @note This parameter is valid only for TIM1 and TIM8. */
+
+  uint16_t TIM_OCNIdleState;  /*!< Specifies the TIM Output Compare pin state during Idle state.
+                                   This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State
+                                   @note This parameter is valid only for TIM1 and TIM8. */
+} TIM_OCInitTypeDef;
+
+/** 
+  * @brief  TIM Input Capture Init structure definition  
+  */
+
+typedef struct
+{
+
+  uint16_t TIM_Channel;      /*!< Specifies the TIM channel.
+                                  This parameter can be a value of @ref TIM_Channel */
+
+  uint16_t TIM_ICPolarity;   /*!< Specifies the active edge of the input signal.
+                                  This parameter can be a value of @ref TIM_Input_Capture_Polarity */
+
+  uint16_t TIM_ICSelection;  /*!< Specifies the input.
+                                  This parameter can be a value of @ref TIM_Input_Capture_Selection */
+
+  uint16_t TIM_ICPrescaler;  /*!< Specifies the Input Capture Prescaler.
+                                  This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
+
+  uint16_t TIM_ICFilter;     /*!< Specifies the input capture filter.
+                                  This parameter can be a number between 0x0 and 0xF */
+} TIM_ICInitTypeDef;
+
+/** 
+  * @brief  BDTR structure definition 
+  * @note   This structure is used only with TIM1 and TIM8.    
+  */
+
+typedef struct
+{
+
+  uint16_t TIM_OSSRState;        /*!< Specifies the Off-State selection used in Run mode.
+                                      This parameter can be a value of @ref OSSR_Off_State_Selection_for_Run_mode_state */
+
+  uint16_t TIM_OSSIState;        /*!< Specifies the Off-State used in Idle state.
+                                      This parameter can be a value of @ref OSSI_Off_State_Selection_for_Idle_mode_state */
+
+  uint16_t TIM_LOCKLevel;        /*!< Specifies the LOCK level parameters.
+                                      This parameter can be a value of @ref Lock_level */ 
+
+  uint16_t TIM_DeadTime;         /*!< Specifies the delay time between the switching-off and the
+                                      switching-on of the outputs.
+                                      This parameter can be a number between 0x00 and 0xFF  */
+
+  uint16_t TIM_Break;            /*!< Specifies whether the TIM Break input is enabled or not. 
+                                      This parameter can be a value of @ref Break_Input_enable_disable */
+
+  uint16_t TIM_BreakPolarity;    /*!< Specifies the TIM Break Input pin polarity.
+                                      This parameter can be a value of @ref Break_Polarity */
+
+  uint16_t TIM_AutomaticOutput;  /*!< Specifies whether the TIM Automatic Output feature is enabled or not. 
+                                      This parameter can be a value of @ref TIM_AOE_Bit_Set_Reset */
+} TIM_BDTRInitTypeDef;
+
+/** @defgroup TIM_Exported_constants 
+  * @{
+  */
+
+#define IS_TIM_ALL_PERIPH(PERIPH) (((PERIPH) == TIM1) || \
+                                   ((PERIPH) == TIM2) || \
+                                   ((PERIPH) == TIM3) || \
+                                   ((PERIPH) == TIM4) || \
+                                   ((PERIPH) == TIM5) || \
+                                   ((PERIPH) == TIM6) || \
+                                   ((PERIPH) == TIM7) || \
+                                   ((PERIPH) == TIM8) || \
+                                   ((PERIPH) == TIM9) || \
+                                   ((PERIPH) == TIM10)|| \
+                                   ((PERIPH) == TIM11)|| \
+                                   ((PERIPH) == TIM12)|| \
+                                   ((PERIPH) == TIM13)|| \
+                                   ((PERIPH) == TIM14)|| \
+                                   ((PERIPH) == TIM15)|| \
+                                   ((PERIPH) == TIM16)|| \
+                                   ((PERIPH) == TIM17))
+
+/* LIST1: TIM 1 and 8 */
+#define IS_TIM_LIST1_PERIPH(PERIPH)  (((PERIPH) == TIM1) || \
+                                      ((PERIPH) == TIM8))
+
+/* LIST2: TIM 1, 8, 15 16 and 17 */
+#define IS_TIM_LIST2_PERIPH(PERIPH) (((PERIPH) == TIM1) || \
+                                     ((PERIPH) == TIM8) || \
+                                     ((PERIPH) == TIM15)|| \
+                                     ((PERIPH) == TIM16)|| \
+                                     ((PERIPH) == TIM17)) 
+
+/* LIST3: TIM 1, 2, 3, 4, 5 and 8 */
+#define IS_TIM_LIST3_PERIPH(PERIPH) (((PERIPH) == TIM1) || \
+                                     ((PERIPH) == TIM2) || \
+                                     ((PERIPH) == TIM3) || \
+                                     ((PERIPH) == TIM4) || \
+                                     ((PERIPH) == TIM5) || \
+                                     ((PERIPH) == TIM8)) 
+									                                 
+/* LIST4: TIM 1, 2, 3, 4, 5, 8, 15, 16 and 17 */
+#define IS_TIM_LIST4_PERIPH(PERIPH) (((PERIPH) == TIM1) || \
+                                     ((PERIPH) == TIM2) || \
+                                     ((PERIPH) == TIM3) || \
+                                     ((PERIPH) == TIM4) || \
+                                     ((PERIPH) == TIM5) || \
+                                     ((PERIPH) == TIM8) || \
+                                     ((PERIPH) == TIM15)|| \
+                                     ((PERIPH) == TIM16)|| \
+                                     ((PERIPH) == TIM17))
+
+/* LIST5: TIM 1, 2, 3, 4, 5, 8 and 15 */                                            
+#define IS_TIM_LIST5_PERIPH(PERIPH) (((PERIPH) == TIM1) || \
+                                     ((PERIPH) == TIM2) || \
+                                     ((PERIPH) == TIM3) || \
+                                     ((PERIPH) == TIM4) || \
+                                     ((PERIPH) == TIM5) || \
+                                     ((PERIPH) == TIM8) || \
+                                     ((PERIPH) == TIM15)) 
+
+/* LIST6: TIM 1, 2, 3, 4, 5, 8, 9, 12 and 15 */
+#define IS_TIM_LIST6_PERIPH(PERIPH)  (((PERIPH) == TIM1) || \
+                                      ((PERIPH) == TIM2) || \
+                                      ((PERIPH) == TIM3) || \
+                                      ((PERIPH) == TIM4) || \
+                                      ((PERIPH) == TIM5) || \
+                                      ((PERIPH) == TIM8) || \
+                                      ((PERIPH) == TIM9) || \
+									  ((PERIPH) == TIM12)|| \
+                                      ((PERIPH) == TIM15))
+
+/* LIST7: TIM 1, 2, 3, 4, 5, 6, 7, 8, 9, 12 and 15 */
+#define IS_TIM_LIST7_PERIPH(PERIPH)  (((PERIPH) == TIM1) || \
+                                      ((PERIPH) == TIM2) || \
+                                      ((PERIPH) == TIM3) || \
+                                      ((PERIPH) == TIM4) || \
+                                      ((PERIPH) == TIM5) || \
+                                      ((PERIPH) == TIM6) || \
+                                      ((PERIPH) == TIM7) || \
+                                      ((PERIPH) == TIM8) || \
+                                      ((PERIPH) == TIM9) || \
+                                      ((PERIPH) == TIM12)|| \
+                                      ((PERIPH) == TIM15))                                    
+
+/* LIST8: TIM 1, 2, 3, 4, 5, 8, 9, 10, 11, 12, 13, 14, 15, 16 and 17 */                                        
+#define IS_TIM_LIST8_PERIPH(PERIPH)  (((PERIPH) == TIM1) || \
+                                      ((PERIPH) == TIM2) || \
+                                      ((PERIPH) == TIM3) || \
+                                      ((PERIPH) == TIM4) || \
+                                      ((PERIPH) == TIM5) || \
+                                      ((PERIPH) == TIM8) || \
+                                      ((PERIPH) == TIM9) || \
+                                      ((PERIPH) == TIM10)|| \
+                                      ((PERIPH) == TIM11)|| \
+                                      ((PERIPH) == TIM12)|| \
+                                      ((PERIPH) == TIM13)|| \
+                                      ((PERIPH) == TIM14)|| \
+                                      ((PERIPH) == TIM15)|| \
+                                      ((PERIPH) == TIM16)|| \
+                                      ((PERIPH) == TIM17))
+
+/* LIST9: TIM 1, 2, 3, 4, 5, 6, 7, 8, 15, 16, and 17 */
+#define IS_TIM_LIST9_PERIPH(PERIPH)  (((PERIPH) == TIM1) || \
+                                      ((PERIPH) == TIM2) || \
+                                      ((PERIPH) == TIM3) || \
+                                      ((PERIPH) == TIM4) || \
+                                      ((PERIPH) == TIM5) || \
+                                      ((PERIPH) == TIM6) || \
+                                      ((PERIPH) == TIM7) || \
+                                      ((PERIPH) == TIM8) || \
+                                      ((PERIPH) == TIM15)|| \
+                                      ((PERIPH) == TIM16)|| \
+                                      ((PERIPH) == TIM17))  
+                                                                                                                                                                                                                          
+/**
+  * @}
+  */ 
+
+/** @defgroup TIM_Output_Compare_and_PWM_modes 
+  * @{
+  */
+
+#define TIM_OCMode_Timing                  ((uint16_t)0x0000)
+#define TIM_OCMode_Active                  ((uint16_t)0x0010)
+#define TIM_OCMode_Inactive                ((uint16_t)0x0020)
+#define TIM_OCMode_Toggle                  ((uint16_t)0x0030)
+#define TIM_OCMode_PWM1                    ((uint16_t)0x0060)
+#define TIM_OCMode_PWM2                    ((uint16_t)0x0070)
+#define IS_TIM_OC_MODE(MODE) (((MODE) == TIM_OCMode_Timing) || \
+                              ((MODE) == TIM_OCMode_Active) || \
+                              ((MODE) == TIM_OCMode_Inactive) || \
+                              ((MODE) == TIM_OCMode_Toggle)|| \
+                              ((MODE) == TIM_OCMode_PWM1) || \
+                              ((MODE) == TIM_OCMode_PWM2))
+#define IS_TIM_OCM(MODE) (((MODE) == TIM_OCMode_Timing) || \
+                          ((MODE) == TIM_OCMode_Active) || \
+                          ((MODE) == TIM_OCMode_Inactive) || \
+                          ((MODE) == TIM_OCMode_Toggle)|| \
+                          ((MODE) == TIM_OCMode_PWM1) || \
+                          ((MODE) == TIM_OCMode_PWM2) ||	\
+                          ((MODE) == TIM_ForcedAction_Active) || \
+                          ((MODE) == TIM_ForcedAction_InActive))
+/**
+  * @}
+  */
+
+/** @defgroup TIM_One_Pulse_Mode 
+  * @{
+  */
+
+#define TIM_OPMode_Single                  ((uint16_t)0x0008)
+#define TIM_OPMode_Repetitive              ((uint16_t)0x0000)
+#define IS_TIM_OPM_MODE(MODE) (((MODE) == TIM_OPMode_Single) || \
+                               ((MODE) == TIM_OPMode_Repetitive))
+/**
+  * @}
+  */ 
+
+/** @defgroup TIM_Channel 
+  * @{
+  */
+
+#define TIM_Channel_1                      ((uint16_t)0x0000)
+#define TIM_Channel_2                      ((uint16_t)0x0004)
+#define TIM_Channel_3                      ((uint16_t)0x0008)
+#define TIM_Channel_4                      ((uint16_t)0x000C)
+#define IS_TIM_CHANNEL(CHANNEL) (((CHANNEL) == TIM_Channel_1) || \
+                                 ((CHANNEL) == TIM_Channel_2) || \
+                                 ((CHANNEL) == TIM_Channel_3) || \
+                                 ((CHANNEL) == TIM_Channel_4))
+#define IS_TIM_PWMI_CHANNEL(CHANNEL) (((CHANNEL) == TIM_Channel_1) || \
+                                      ((CHANNEL) == TIM_Channel_2))
+#define IS_TIM_COMPLEMENTARY_CHANNEL(CHANNEL) (((CHANNEL) == TIM_Channel_1) || \
+                                               ((CHANNEL) == TIM_Channel_2) || \
+                                               ((CHANNEL) == TIM_Channel_3))
+/**
+  * @}
+  */ 
+
+/** @defgroup TIM_Clock_Division_CKD 
+  * @{
+  */
+
+#define TIM_CKD_DIV1                       ((uint16_t)0x0000)
+#define TIM_CKD_DIV2                       ((uint16_t)0x0100)
+#define TIM_CKD_DIV4                       ((uint16_t)0x0200)
+#define IS_TIM_CKD_DIV(DIV) (((DIV) == TIM_CKD_DIV1) || \
+                             ((DIV) == TIM_CKD_DIV2) || \
+                             ((DIV) == TIM_CKD_DIV4))
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Counter_Mode 
+  * @{
+  */
+
+#define TIM_CounterMode_Up                 ((uint16_t)0x0000)
+#define TIM_CounterMode_Down               ((uint16_t)0x0010)
+#define TIM_CounterMode_CenterAligned1     ((uint16_t)0x0020)
+#define TIM_CounterMode_CenterAligned2     ((uint16_t)0x0040)
+#define TIM_CounterMode_CenterAligned3     ((uint16_t)0x0060)
+#define IS_TIM_COUNTER_MODE(MODE) (((MODE) == TIM_CounterMode_Up) ||  \
+                                   ((MODE) == TIM_CounterMode_Down) || \
+                                   ((MODE) == TIM_CounterMode_CenterAligned1) || \
+                                   ((MODE) == TIM_CounterMode_CenterAligned2) || \
+                                   ((MODE) == TIM_CounterMode_CenterAligned3))
+/**
+  * @}
+  */ 
+
+/** @defgroup TIM_Output_Compare_Polarity 
+  * @{
+  */
+
+#define TIM_OCPolarity_High                ((uint16_t)0x0000)
+#define TIM_OCPolarity_Low                 ((uint16_t)0x0002)
+#define IS_TIM_OC_POLARITY(POLARITY) (((POLARITY) == TIM_OCPolarity_High) || \
+                                      ((POLARITY) == TIM_OCPolarity_Low))
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Output_Compare_N_Polarity 
+  * @{
+  */
+  
+#define TIM_OCNPolarity_High               ((uint16_t)0x0000)
+#define TIM_OCNPolarity_Low                ((uint16_t)0x0008)
+#define IS_TIM_OCN_POLARITY(POLARITY) (((POLARITY) == TIM_OCNPolarity_High) || \
+                                       ((POLARITY) == TIM_OCNPolarity_Low))
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Output_Compare_state 
+  * @{
+  */
+
+#define TIM_OutputState_Disable            ((uint16_t)0x0000)
+#define TIM_OutputState_Enable             ((uint16_t)0x0001)
+#define IS_TIM_OUTPUT_STATE(STATE) (((STATE) == TIM_OutputState_Disable) || \
+                                    ((STATE) == TIM_OutputState_Enable))
+/**
+  * @}
+  */ 
+
+/** @defgroup TIM_Output_Compare_N_state 
+  * @{
+  */
+
+#define TIM_OutputNState_Disable           ((uint16_t)0x0000)
+#define TIM_OutputNState_Enable            ((uint16_t)0x0004)
+#define IS_TIM_OUTPUTN_STATE(STATE) (((STATE) == TIM_OutputNState_Disable) || \
+                                     ((STATE) == TIM_OutputNState_Enable))
+/**
+  * @}
+  */ 
+
+/** @defgroup TIM_Capture_Compare_state 
+  * @{
+  */
+
+#define TIM_CCx_Enable                      ((uint16_t)0x0001)
+#define TIM_CCx_Disable                     ((uint16_t)0x0000)
+#define IS_TIM_CCX(CCX) (((CCX) == TIM_CCx_Enable) || \
+                         ((CCX) == TIM_CCx_Disable))
+/**
+  * @}
+  */ 
+
+/** @defgroup TIM_Capture_Compare_N_state 
+  * @{
+  */
+
+#define TIM_CCxN_Enable                     ((uint16_t)0x0004)
+#define TIM_CCxN_Disable                    ((uint16_t)0x0000)
+#define IS_TIM_CCXN(CCXN) (((CCXN) == TIM_CCxN_Enable) || \
+                           ((CCXN) == TIM_CCxN_Disable))
+/**
+  * @}
+  */ 
+
+/** @defgroup Break_Input_enable_disable 
+  * @{
+  */
+
+#define TIM_Break_Enable                   ((uint16_t)0x1000)
+#define TIM_Break_Disable                  ((uint16_t)0x0000)
+#define IS_TIM_BREAK_STATE(STATE) (((STATE) == TIM_Break_Enable) || \
+                                   ((STATE) == TIM_Break_Disable))
+/**
+  * @}
+  */ 
+
+/** @defgroup Break_Polarity 
+  * @{
+  */
+
+#define TIM_BreakPolarity_Low              ((uint16_t)0x0000)
+#define TIM_BreakPolarity_High             ((uint16_t)0x2000)
+#define IS_TIM_BREAK_POLARITY(POLARITY) (((POLARITY) == TIM_BreakPolarity_Low) || \
+                                         ((POLARITY) == TIM_BreakPolarity_High))
+/**
+  * @}
+  */ 
+
+/** @defgroup TIM_AOE_Bit_Set_Reset 
+  * @{
+  */
+
+#define TIM_AutomaticOutput_Enable         ((uint16_t)0x4000)
+#define TIM_AutomaticOutput_Disable        ((uint16_t)0x0000)
+#define IS_TIM_AUTOMATIC_OUTPUT_STATE(STATE) (((STATE) == TIM_AutomaticOutput_Enable) || \
+                                              ((STATE) == TIM_AutomaticOutput_Disable))
+/**
+  * @}
+  */ 
+
+/** @defgroup Lock_level 
+  * @{
+  */
+
+#define TIM_LOCKLevel_OFF                  ((uint16_t)0x0000)
+#define TIM_LOCKLevel_1                    ((uint16_t)0x0100)
+#define TIM_LOCKLevel_2                    ((uint16_t)0x0200)
+#define TIM_LOCKLevel_3                    ((uint16_t)0x0300)
+#define IS_TIM_LOCK_LEVEL(LEVEL) (((LEVEL) == TIM_LOCKLevel_OFF) || \
+                                  ((LEVEL) == TIM_LOCKLevel_1) || \
+                                  ((LEVEL) == TIM_LOCKLevel_2) || \
+                                  ((LEVEL) == TIM_LOCKLevel_3))
+/**
+  * @}
+  */ 
+
+/** @defgroup OSSI_Off_State_Selection_for_Idle_mode_state 
+  * @{
+  */
+
+#define TIM_OSSIState_Enable               ((uint16_t)0x0400)
+#define TIM_OSSIState_Disable              ((uint16_t)0x0000)
+#define IS_TIM_OSSI_STATE(STATE) (((STATE) == TIM_OSSIState_Enable) || \
+                                  ((STATE) == TIM_OSSIState_Disable))
+/**
+  * @}
+  */
+
+/** @defgroup OSSR_Off_State_Selection_for_Run_mode_state 
+  * @{
+  */
+
+#define TIM_OSSRState_Enable               ((uint16_t)0x0800)
+#define TIM_OSSRState_Disable              ((uint16_t)0x0000)
+#define IS_TIM_OSSR_STATE(STATE) (((STATE) == TIM_OSSRState_Enable) || \
+                                  ((STATE) == TIM_OSSRState_Disable))
+/**
+  * @}
+  */ 
+
+/** @defgroup TIM_Output_Compare_Idle_State 
+  * @{
+  */
+
+#define TIM_OCIdleState_Set                ((uint16_t)0x0100)
+#define TIM_OCIdleState_Reset              ((uint16_t)0x0000)
+#define IS_TIM_OCIDLE_STATE(STATE) (((STATE) == TIM_OCIdleState_Set) || \
+                                    ((STATE) == TIM_OCIdleState_Reset))
+/**
+  * @}
+  */ 
+
+/** @defgroup TIM_Output_Compare_N_Idle_State 
+  * @{
+  */
+
+#define TIM_OCNIdleState_Set               ((uint16_t)0x0200)
+#define TIM_OCNIdleState_Reset             ((uint16_t)0x0000)
+#define IS_TIM_OCNIDLE_STATE(STATE) (((STATE) == TIM_OCNIdleState_Set) || \
+                                     ((STATE) == TIM_OCNIdleState_Reset))
+/**
+  * @}
+  */ 
+
+/** @defgroup TIM_Input_Capture_Polarity 
+  * @{
+  */
+
+#define  TIM_ICPolarity_Rising             ((uint16_t)0x0000)
+#define  TIM_ICPolarity_Falling            ((uint16_t)0x0002)
+#define  TIM_ICPolarity_BothEdge           ((uint16_t)0x000A)
+#define IS_TIM_IC_POLARITY(POLARITY) (((POLARITY) == TIM_ICPolarity_Rising) || \
+                                      ((POLARITY) == TIM_ICPolarity_Falling))
+#define IS_TIM_IC_POLARITY_LITE(POLARITY) (((POLARITY) == TIM_ICPolarity_Rising) || \
+                                           ((POLARITY) == TIM_ICPolarity_Falling)|| \
+                                           ((POLARITY) == TIM_ICPolarity_BothEdge))                                      
+/**
+  * @}
+  */ 
+
+/** @defgroup TIM_Input_Capture_Selection 
+  * @{
+  */
+
+#define TIM_ICSelection_DirectTI           ((uint16_t)0x0001) /*!< TIM Input 1, 2, 3 or 4 is selected to be 
+                                                                   connected to IC1, IC2, IC3 or IC4, respectively */
+#define TIM_ICSelection_IndirectTI         ((uint16_t)0x0002) /*!< TIM Input 1, 2, 3 or 4 is selected to be
+                                                                   connected to IC2, IC1, IC4 or IC3, respectively. */
+#define TIM_ICSelection_TRC                ((uint16_t)0x0003) /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to TRC. */
+#define IS_TIM_IC_SELECTION(SELECTION) (((SELECTION) == TIM_ICSelection_DirectTI) || \
+                                        ((SELECTION) == TIM_ICSelection_IndirectTI) || \
+                                        ((SELECTION) == TIM_ICSelection_TRC))
+/**
+  * @}
+  */ 
+
+/** @defgroup TIM_Input_Capture_Prescaler 
+  * @{
+  */
+
+#define TIM_ICPSC_DIV1                     ((uint16_t)0x0000) /*!< Capture performed each time an edge is detected on the capture input. */
+#define TIM_ICPSC_DIV2                     ((uint16_t)0x0004) /*!< Capture performed once every 2 events. */
+#define TIM_ICPSC_DIV4                     ((uint16_t)0x0008) /*!< Capture performed once every 4 events. */
+#define TIM_ICPSC_DIV8                     ((uint16_t)0x000C) /*!< Capture performed once every 8 events. */
+#define IS_TIM_IC_PRESCALER(PRESCALER) (((PRESCALER) == TIM_ICPSC_DIV1) || \
+                                        ((PRESCALER) == TIM_ICPSC_DIV2) || \
+                                        ((PRESCALER) == TIM_ICPSC_DIV4) || \
+                                        ((PRESCALER) == TIM_ICPSC_DIV8))
+/**
+  * @}
+  */ 
+
+/** @defgroup TIM_interrupt_sources 
+  * @{
+  */
+
+#define TIM_IT_Update                      ((uint16_t)0x0001)
+#define TIM_IT_CC1                         ((uint16_t)0x0002)
+#define TIM_IT_CC2                         ((uint16_t)0x0004)
+#define TIM_IT_CC3                         ((uint16_t)0x0008)
+#define TIM_IT_CC4                         ((uint16_t)0x0010)
+#define TIM_IT_COM                         ((uint16_t)0x0020)
+#define TIM_IT_Trigger                     ((uint16_t)0x0040)
+#define TIM_IT_Break                       ((uint16_t)0x0080)
+#define IS_TIM_IT(IT) ((((IT) & (uint16_t)0xFF00) == 0x0000) && ((IT) != 0x0000))
+
+#define IS_TIM_GET_IT(IT) (((IT) == TIM_IT_Update) || \
+                           ((IT) == TIM_IT_CC1) || \
+                           ((IT) == TIM_IT_CC2) || \
+                           ((IT) == TIM_IT_CC3) || \
+                           ((IT) == TIM_IT_CC4) || \
+                           ((IT) == TIM_IT_COM) || \
+                           ((IT) == TIM_IT_Trigger) || \
+                           ((IT) == TIM_IT_Break))
+/**
+  * @}
+  */ 
+
+/** @defgroup TIM_DMA_Base_address 
+  * @{
+  */
+
+#define TIM_DMABase_CR1                    ((uint16_t)0x0000)
+#define TIM_DMABase_CR2                    ((uint16_t)0x0001)
+#define TIM_DMABase_SMCR                   ((uint16_t)0x0002)
+#define TIM_DMABase_DIER                   ((uint16_t)0x0003)
+#define TIM_DMABase_SR                     ((uint16_t)0x0004)
+#define TIM_DMABase_EGR                    ((uint16_t)0x0005)
+#define TIM_DMABase_CCMR1                  ((uint16_t)0x0006)
+#define TIM_DMABase_CCMR2                  ((uint16_t)0x0007)
+#define TIM_DMABase_CCER                   ((uint16_t)0x0008)
+#define TIM_DMABase_CNT                    ((uint16_t)0x0009)
+#define TIM_DMABase_PSC                    ((uint16_t)0x000A)
+#define TIM_DMABase_ARR                    ((uint16_t)0x000B)
+#define TIM_DMABase_RCR                    ((uint16_t)0x000C)
+#define TIM_DMABase_CCR1                   ((uint16_t)0x000D)
+#define TIM_DMABase_CCR2                   ((uint16_t)0x000E)
+#define TIM_DMABase_CCR3                   ((uint16_t)0x000F)
+#define TIM_DMABase_CCR4                   ((uint16_t)0x0010)
+#define TIM_DMABase_BDTR                   ((uint16_t)0x0011)
+#define TIM_DMABase_DCR                    ((uint16_t)0x0012)
+#define IS_TIM_DMA_BASE(BASE) (((BASE) == TIM_DMABase_CR1) || \
+                               ((BASE) == TIM_DMABase_CR2) || \
+                               ((BASE) == TIM_DMABase_SMCR) || \
+                               ((BASE) == TIM_DMABase_DIER) || \
+                               ((BASE) == TIM_DMABase_SR) || \
+                               ((BASE) == TIM_DMABase_EGR) || \
+                               ((BASE) == TIM_DMABase_CCMR1) || \
+                               ((BASE) == TIM_DMABase_CCMR2) || \
+                               ((BASE) == TIM_DMABase_CCER) || \
+                               ((BASE) == TIM_DMABase_CNT) || \
+                               ((BASE) == TIM_DMABase_PSC) || \
+                               ((BASE) == TIM_DMABase_ARR) || \
+                               ((BASE) == TIM_DMABase_RCR) || \
+                               ((BASE) == TIM_DMABase_CCR1) || \
+                               ((BASE) == TIM_DMABase_CCR2) || \
+                               ((BASE) == TIM_DMABase_CCR3) || \
+                               ((BASE) == TIM_DMABase_CCR4) || \
+                               ((BASE) == TIM_DMABase_BDTR) || \
+                               ((BASE) == TIM_DMABase_DCR))
+/**
+  * @}
+  */ 
+
+/** @defgroup TIM_DMA_Burst_Length 
+  * @{
+  */
+
+#define TIM_DMABurstLength_1Transfer           ((uint16_t)0x0000)
+#define TIM_DMABurstLength_2Transfers          ((uint16_t)0x0100)
+#define TIM_DMABurstLength_3Transfers          ((uint16_t)0x0200)
+#define TIM_DMABurstLength_4Transfers          ((uint16_t)0x0300)
+#define TIM_DMABurstLength_5Transfers          ((uint16_t)0x0400)
+#define TIM_DMABurstLength_6Transfers          ((uint16_t)0x0500)
+#define TIM_DMABurstLength_7Transfers          ((uint16_t)0x0600)
+#define TIM_DMABurstLength_8Transfers          ((uint16_t)0x0700)
+#define TIM_DMABurstLength_9Transfers          ((uint16_t)0x0800)
+#define TIM_DMABurstLength_10Transfers         ((uint16_t)0x0900)
+#define TIM_DMABurstLength_11Transfers         ((uint16_t)0x0A00)
+#define TIM_DMABurstLength_12Transfers         ((uint16_t)0x0B00)
+#define TIM_DMABurstLength_13Transfers         ((uint16_t)0x0C00)
+#define TIM_DMABurstLength_14Transfers         ((uint16_t)0x0D00)
+#define TIM_DMABurstLength_15Transfers         ((uint16_t)0x0E00)
+#define TIM_DMABurstLength_16Transfers         ((uint16_t)0x0F00)
+#define TIM_DMABurstLength_17Transfers         ((uint16_t)0x1000)
+#define TIM_DMABurstLength_18Transfers         ((uint16_t)0x1100)
+#define IS_TIM_DMA_LENGTH(LENGTH) (((LENGTH) == TIM_DMABurstLength_1Transfer) || \
+                                   ((LENGTH) == TIM_DMABurstLength_2Transfers) || \
+                                   ((LENGTH) == TIM_DMABurstLength_3Transfers) || \
+                                   ((LENGTH) == TIM_DMABurstLength_4Transfers) || \
+                                   ((LENGTH) == TIM_DMABurstLength_5Transfers) || \
+                                   ((LENGTH) == TIM_DMABurstLength_6Transfers) || \
+                                   ((LENGTH) == TIM_DMABurstLength_7Transfers) || \
+                                   ((LENGTH) == TIM_DMABurstLength_8Transfers) || \
+                                   ((LENGTH) == TIM_DMABurstLength_9Transfers) || \
+                                   ((LENGTH) == TIM_DMABurstLength_10Transfers) || \
+                                   ((LENGTH) == TIM_DMABurstLength_11Transfers) || \
+                                   ((LENGTH) == TIM_DMABurstLength_12Transfers) || \
+                                   ((LENGTH) == TIM_DMABurstLength_13Transfers) || \
+                                   ((LENGTH) == TIM_DMABurstLength_14Transfers) || \
+                                   ((LENGTH) == TIM_DMABurstLength_15Transfers) || \
+                                   ((LENGTH) == TIM_DMABurstLength_16Transfers) || \
+                                   ((LENGTH) == TIM_DMABurstLength_17Transfers) || \
+                                   ((LENGTH) == TIM_DMABurstLength_18Transfers))
+/**
+  * @}
+  */ 
+
+/** @defgroup TIM_DMA_sources 
+  * @{
+  */
+
+#define TIM_DMA_Update                     ((uint16_t)0x0100)
+#define TIM_DMA_CC1                        ((uint16_t)0x0200)
+#define TIM_DMA_CC2                        ((uint16_t)0x0400)
+#define TIM_DMA_CC3                        ((uint16_t)0x0800)
+#define TIM_DMA_CC4                        ((uint16_t)0x1000)
+#define TIM_DMA_COM                        ((uint16_t)0x2000)
+#define TIM_DMA_Trigger                    ((uint16_t)0x4000)
+#define IS_TIM_DMA_SOURCE(SOURCE) ((((SOURCE) & (uint16_t)0x80FF) == 0x0000) && ((SOURCE) != 0x0000))
+
+/**
+  * @}
+  */ 
+
+/** @defgroup TIM_External_Trigger_Prescaler 
+  * @{
+  */
+
+#define TIM_ExtTRGPSC_OFF                  ((uint16_t)0x0000)
+#define TIM_ExtTRGPSC_DIV2                 ((uint16_t)0x1000)
+#define TIM_ExtTRGPSC_DIV4                 ((uint16_t)0x2000)
+#define TIM_ExtTRGPSC_DIV8                 ((uint16_t)0x3000)
+#define IS_TIM_EXT_PRESCALER(PRESCALER) (((PRESCALER) == TIM_ExtTRGPSC_OFF) || \
+                                         ((PRESCALER) == TIM_ExtTRGPSC_DIV2) || \
+                                         ((PRESCALER) == TIM_ExtTRGPSC_DIV4) || \
+                                         ((PRESCALER) == TIM_ExtTRGPSC_DIV8))
+/**
+  * @}
+  */ 
+
+/** @defgroup TIM_Internal_Trigger_Selection 
+  * @{
+  */
+
+#define TIM_TS_ITR0                        ((uint16_t)0x0000)
+#define TIM_TS_ITR1                        ((uint16_t)0x0010)
+#define TIM_TS_ITR2                        ((uint16_t)0x0020)
+#define TIM_TS_ITR3                        ((uint16_t)0x0030)
+#define TIM_TS_TI1F_ED                     ((uint16_t)0x0040)
+#define TIM_TS_TI1FP1                      ((uint16_t)0x0050)
+#define TIM_TS_TI2FP2                      ((uint16_t)0x0060)
+#define TIM_TS_ETRF                        ((uint16_t)0x0070)
+#define IS_TIM_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \
+                                             ((SELECTION) == TIM_TS_ITR1) || \
+                                             ((SELECTION) == TIM_TS_ITR2) || \
+                                             ((SELECTION) == TIM_TS_ITR3) || \
+                                             ((SELECTION) == TIM_TS_TI1F_ED) || \
+                                             ((SELECTION) == TIM_TS_TI1FP1) || \
+                                             ((SELECTION) == TIM_TS_TI2FP2) || \
+                                             ((SELECTION) == TIM_TS_ETRF))
+#define IS_TIM_INTERNAL_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \
+                                                      ((SELECTION) == TIM_TS_ITR1) || \
+                                                      ((SELECTION) == TIM_TS_ITR2) || \
+                                                      ((SELECTION) == TIM_TS_ITR3))
+/**
+  * @}
+  */ 
+
+/** @defgroup TIM_TIx_External_Clock_Source 
+  * @{
+  */
+
+#define TIM_TIxExternalCLK1Source_TI1      ((uint16_t)0x0050)
+#define TIM_TIxExternalCLK1Source_TI2      ((uint16_t)0x0060)
+#define TIM_TIxExternalCLK1Source_TI1ED    ((uint16_t)0x0040)
+#define IS_TIM_TIXCLK_SOURCE(SOURCE) (((SOURCE) == TIM_TIxExternalCLK1Source_TI1) || \
+                                      ((SOURCE) == TIM_TIxExternalCLK1Source_TI2) || \
+                                      ((SOURCE) == TIM_TIxExternalCLK1Source_TI1ED))
+/**
+  * @}
+  */ 
+
+/** @defgroup TIM_External_Trigger_Polarity 
+  * @{
+  */ 
+#define TIM_ExtTRGPolarity_Inverted        ((uint16_t)0x8000)
+#define TIM_ExtTRGPolarity_NonInverted     ((uint16_t)0x0000)
+#define IS_TIM_EXT_POLARITY(POLARITY) (((POLARITY) == TIM_ExtTRGPolarity_Inverted) || \
+                                       ((POLARITY) == TIM_ExtTRGPolarity_NonInverted))
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Prescaler_Reload_Mode 
+  * @{
+  */
+
+#define TIM_PSCReloadMode_Update           ((uint16_t)0x0000)
+#define TIM_PSCReloadMode_Immediate        ((uint16_t)0x0001)
+#define IS_TIM_PRESCALER_RELOAD(RELOAD) (((RELOAD) == TIM_PSCReloadMode_Update) || \
+                                         ((RELOAD) == TIM_PSCReloadMode_Immediate))
+/**
+  * @}
+  */ 
+
+/** @defgroup TIM_Forced_Action 
+  * @{
+  */
+
+#define TIM_ForcedAction_Active            ((uint16_t)0x0050)
+#define TIM_ForcedAction_InActive          ((uint16_t)0x0040)
+#define IS_TIM_FORCED_ACTION(ACTION) (((ACTION) == TIM_ForcedAction_Active) || \
+                                      ((ACTION) == TIM_ForcedAction_InActive))
+/**
+  * @}
+  */ 
+
+/** @defgroup TIM_Encoder_Mode 
+  * @{
+  */
+
+#define TIM_EncoderMode_TI1                ((uint16_t)0x0001)
+#define TIM_EncoderMode_TI2                ((uint16_t)0x0002)
+#define TIM_EncoderMode_TI12               ((uint16_t)0x0003)
+#define IS_TIM_ENCODER_MODE(MODE) (((MODE) == TIM_EncoderMode_TI1) || \
+                                   ((MODE) == TIM_EncoderMode_TI2) || \
+                                   ((MODE) == TIM_EncoderMode_TI12))
+/**
+  * @}
+  */ 
+
+
+/** @defgroup TIM_Event_Source 
+  * @{
+  */
+
+#define TIM_EventSource_Update             ((uint16_t)0x0001)
+#define TIM_EventSource_CC1                ((uint16_t)0x0002)
+#define TIM_EventSource_CC2                ((uint16_t)0x0004)
+#define TIM_EventSource_CC3                ((uint16_t)0x0008)
+#define TIM_EventSource_CC4                ((uint16_t)0x0010)
+#define TIM_EventSource_COM                ((uint16_t)0x0020)
+#define TIM_EventSource_Trigger            ((uint16_t)0x0040)
+#define TIM_EventSource_Break              ((uint16_t)0x0080)
+#define IS_TIM_EVENT_SOURCE(SOURCE) ((((SOURCE) & (uint16_t)0xFF00) == 0x0000) && ((SOURCE) != 0x0000))
+
+/**
+  * @}
+  */ 
+
+/** @defgroup TIM_Update_Source 
+  * @{
+  */
+
+#define TIM_UpdateSource_Global            ((uint16_t)0x0000) /*!< Source of update is the counter overflow/underflow
+                                                                   or the setting of UG bit, or an update generation
+                                                                   through the slave mode controller. */
+#define TIM_UpdateSource_Regular           ((uint16_t)0x0001) /*!< Source of update is counter overflow/underflow. */
+#define IS_TIM_UPDATE_SOURCE(SOURCE) (((SOURCE) == TIM_UpdateSource_Global) || \
+                                      ((SOURCE) == TIM_UpdateSource_Regular))
+/**
+  * @}
+  */ 
+
+/** @defgroup TIM_Output_Compare_Preload_State 
+  * @{
+  */
+
+#define TIM_OCPreload_Enable               ((uint16_t)0x0008)
+#define TIM_OCPreload_Disable              ((uint16_t)0x0000)
+#define IS_TIM_OCPRELOAD_STATE(STATE) (((STATE) == TIM_OCPreload_Enable) || \
+                                       ((STATE) == TIM_OCPreload_Disable))
+/**
+  * @}
+  */ 
+
+/** @defgroup TIM_Output_Compare_Fast_State 
+  * @{
+  */
+
+#define TIM_OCFast_Enable                  ((uint16_t)0x0004)
+#define TIM_OCFast_Disable                 ((uint16_t)0x0000)
+#define IS_TIM_OCFAST_STATE(STATE) (((STATE) == TIM_OCFast_Enable) || \
+                                    ((STATE) == TIM_OCFast_Disable))
+                                     
+/**
+  * @}
+  */ 
+
+/** @defgroup TIM_Output_Compare_Clear_State 
+  * @{
+  */
+
+#define TIM_OCClear_Enable                 ((uint16_t)0x0080)
+#define TIM_OCClear_Disable                ((uint16_t)0x0000)
+#define IS_TIM_OCCLEAR_STATE(STATE) (((STATE) == TIM_OCClear_Enable) || \
+                                     ((STATE) == TIM_OCClear_Disable))
+/**
+  * @}
+  */ 
+
+/** @defgroup TIM_Trigger_Output_Source 
+  * @{
+  */
+
+#define TIM_TRGOSource_Reset               ((uint16_t)0x0000)
+#define TIM_TRGOSource_Enable              ((uint16_t)0x0010)
+#define TIM_TRGOSource_Update              ((uint16_t)0x0020)
+#define TIM_TRGOSource_OC1                 ((uint16_t)0x0030)
+#define TIM_TRGOSource_OC1Ref              ((uint16_t)0x0040)
+#define TIM_TRGOSource_OC2Ref              ((uint16_t)0x0050)
+#define TIM_TRGOSource_OC3Ref              ((uint16_t)0x0060)
+#define TIM_TRGOSource_OC4Ref              ((uint16_t)0x0070)
+#define IS_TIM_TRGO_SOURCE(SOURCE) (((SOURCE) == TIM_TRGOSource_Reset) || \
+                                    ((SOURCE) == TIM_TRGOSource_Enable) || \
+                                    ((SOURCE) == TIM_TRGOSource_Update) || \
+                                    ((SOURCE) == TIM_TRGOSource_OC1) || \
+                                    ((SOURCE) == TIM_TRGOSource_OC1Ref) || \
+                                    ((SOURCE) == TIM_TRGOSource_OC2Ref) || \
+                                    ((SOURCE) == TIM_TRGOSource_OC3Ref) || \
+                                    ((SOURCE) == TIM_TRGOSource_OC4Ref))
+/**
+  * @}
+  */ 
+
+/** @defgroup TIM_Slave_Mode 
+  * @{
+  */
+
+#define TIM_SlaveMode_Reset                ((uint16_t)0x0004)
+#define TIM_SlaveMode_Gated                ((uint16_t)0x0005)
+#define TIM_SlaveMode_Trigger              ((uint16_t)0x0006)
+#define TIM_SlaveMode_External1            ((uint16_t)0x0007)
+#define IS_TIM_SLAVE_MODE(MODE) (((MODE) == TIM_SlaveMode_Reset) || \
+                                 ((MODE) == TIM_SlaveMode_Gated) || \
+                                 ((MODE) == TIM_SlaveMode_Trigger) || \
+                                 ((MODE) == TIM_SlaveMode_External1))
+/**
+  * @}
+  */ 
+
+/** @defgroup TIM_Master_Slave_Mode 
+  * @{
+  */
+
+#define TIM_MasterSlaveMode_Enable         ((uint16_t)0x0080)
+#define TIM_MasterSlaveMode_Disable        ((uint16_t)0x0000)
+#define IS_TIM_MSM_STATE(STATE) (((STATE) == TIM_MasterSlaveMode_Enable) || \
+                                 ((STATE) == TIM_MasterSlaveMode_Disable))
+/**
+  * @}
+  */ 
+
+/** @defgroup TIM_Flags 
+  * @{
+  */
+
+#define TIM_FLAG_Update                    ((uint16_t)0x0001)
+#define TIM_FLAG_CC1                       ((uint16_t)0x0002)
+#define TIM_FLAG_CC2                       ((uint16_t)0x0004)
+#define TIM_FLAG_CC3                       ((uint16_t)0x0008)
+#define TIM_FLAG_CC4                       ((uint16_t)0x0010)
+#define TIM_FLAG_COM                       ((uint16_t)0x0020)
+#define TIM_FLAG_Trigger                   ((uint16_t)0x0040)
+#define TIM_FLAG_Break                     ((uint16_t)0x0080)
+#define TIM_FLAG_CC1OF                     ((uint16_t)0x0200)
+#define TIM_FLAG_CC2OF                     ((uint16_t)0x0400)
+#define TIM_FLAG_CC3OF                     ((uint16_t)0x0800)
+#define TIM_FLAG_CC4OF                     ((uint16_t)0x1000)
+#define IS_TIM_GET_FLAG(FLAG) (((FLAG) == TIM_FLAG_Update) || \
+                               ((FLAG) == TIM_FLAG_CC1) || \
+                               ((FLAG) == TIM_FLAG_CC2) || \
+                               ((FLAG) == TIM_FLAG_CC3) || \
+                               ((FLAG) == TIM_FLAG_CC4) || \
+                               ((FLAG) == TIM_FLAG_COM) || \
+                               ((FLAG) == TIM_FLAG_Trigger) || \
+                               ((FLAG) == TIM_FLAG_Break) || \
+                               ((FLAG) == TIM_FLAG_CC1OF) || \
+                               ((FLAG) == TIM_FLAG_CC2OF) || \
+                               ((FLAG) == TIM_FLAG_CC3OF) || \
+                               ((FLAG) == TIM_FLAG_CC4OF))
+                               
+                               
+#define IS_TIM_CLEAR_FLAG(TIM_FLAG) ((((TIM_FLAG) & (uint16_t)0xE100) == 0x0000) && ((TIM_FLAG) != 0x0000))
+/**
+  * @}
+  */ 
+
+/** @defgroup TIM_Input_Capture_Filer_Value 
+  * @{
+  */
+
+#define IS_TIM_IC_FILTER(ICFILTER) ((ICFILTER) <= 0xF) 
+/**
+  * @}
+  */ 
+
+/** @defgroup TIM_External_Trigger_Filter 
+  * @{
+  */
+
+#define IS_TIM_EXT_FILTER(EXTFILTER) ((EXTFILTER) <= 0xF)
+/**
+  * @}
+  */ 
+
+/** @defgroup TIM_Legacy 
+  * @{
+  */
+
+#define TIM_DMABurstLength_1Byte           TIM_DMABurstLength_1Transfer
+#define TIM_DMABurstLength_2Bytes          TIM_DMABurstLength_2Transfers
+#define TIM_DMABurstLength_3Bytes          TIM_DMABurstLength_3Transfers
+#define TIM_DMABurstLength_4Bytes          TIM_DMABurstLength_4Transfers
+#define TIM_DMABurstLength_5Bytes          TIM_DMABurstLength_5Transfers
+#define TIM_DMABurstLength_6Bytes          TIM_DMABurstLength_6Transfers
+#define TIM_DMABurstLength_7Bytes          TIM_DMABurstLength_7Transfers
+#define TIM_DMABurstLength_8Bytes          TIM_DMABurstLength_8Transfers
+#define TIM_DMABurstLength_9Bytes          TIM_DMABurstLength_9Transfers
+#define TIM_DMABurstLength_10Bytes         TIM_DMABurstLength_10Transfers
+#define TIM_DMABurstLength_11Bytes         TIM_DMABurstLength_11Transfers
+#define TIM_DMABurstLength_12Bytes         TIM_DMABurstLength_12Transfers
+#define TIM_DMABurstLength_13Bytes         TIM_DMABurstLength_13Transfers
+#define TIM_DMABurstLength_14Bytes         TIM_DMABurstLength_14Transfers
+#define TIM_DMABurstLength_15Bytes         TIM_DMABurstLength_15Transfers
+#define TIM_DMABurstLength_16Bytes         TIM_DMABurstLength_16Transfers
+#define TIM_DMABurstLength_17Bytes         TIM_DMABurstLength_17Transfers
+#define TIM_DMABurstLength_18Bytes         TIM_DMABurstLength_18Transfers
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Exported_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */ 
+
+/** @defgroup TIM_Exported_Functions
+  * @{
+  */
+
+void TIM_DeInit(TIM_TypeDef* TIMx);
+void TIM_TimeBaseInit(TIM_TypeDef* TIMx, TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct);
+void TIM_OC1Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct);
+void TIM_OC2Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct);
+void TIM_OC3Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct);
+void TIM_OC4Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct);
+void TIM_ICInit(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct);
+void TIM_PWMIConfig(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct);
+void TIM_BDTRConfig(TIM_TypeDef* TIMx, TIM_BDTRInitTypeDef *TIM_BDTRInitStruct);
+void TIM_TimeBaseStructInit(TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct);
+void TIM_OCStructInit(TIM_OCInitTypeDef* TIM_OCInitStruct);
+void TIM_ICStructInit(TIM_ICInitTypeDef* TIM_ICInitStruct);
+void TIM_BDTRStructInit(TIM_BDTRInitTypeDef* TIM_BDTRInitStruct);
+void TIM_Cmd(TIM_TypeDef* TIMx, FunctionalState NewState);
+void TIM_CtrlPWMOutputs(TIM_TypeDef* TIMx, FunctionalState NewState);
+void TIM_ITConfig(TIM_TypeDef* TIMx, uint16_t TIM_IT, FunctionalState NewState);
+void TIM_GenerateEvent(TIM_TypeDef* TIMx, uint16_t TIM_EventSource);
+void TIM_DMAConfig(TIM_TypeDef* TIMx, uint16_t TIM_DMABase, uint16_t TIM_DMABurstLength);
+void TIM_DMACmd(TIM_TypeDef* TIMx, uint16_t TIM_DMASource, FunctionalState NewState);
+void TIM_InternalClockConfig(TIM_TypeDef* TIMx);
+void TIM_ITRxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource);
+void TIM_TIxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_TIxExternalCLKSource,
+                                uint16_t TIM_ICPolarity, uint16_t ICFilter);
+void TIM_ETRClockMode1Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity,
+                             uint16_t ExtTRGFilter);
+void TIM_ETRClockMode2Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, 
+                             uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter);
+void TIM_ETRConfig(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity,
+                   uint16_t ExtTRGFilter);
+void TIM_PrescalerConfig(TIM_TypeDef* TIMx, uint16_t Prescaler, uint16_t TIM_PSCReloadMode);
+void TIM_CounterModeConfig(TIM_TypeDef* TIMx, uint16_t TIM_CounterMode);
+void TIM_SelectInputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource);
+void TIM_EncoderInterfaceConfig(TIM_TypeDef* TIMx, uint16_t TIM_EncoderMode,
+                                uint16_t TIM_IC1Polarity, uint16_t TIM_IC2Polarity);
+void TIM_ForcedOC1Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction);
+void TIM_ForcedOC2Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction);
+void TIM_ForcedOC3Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction);
+void TIM_ForcedOC4Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction);
+void TIM_ARRPreloadConfig(TIM_TypeDef* TIMx, FunctionalState NewState);
+void TIM_SelectCOM(TIM_TypeDef* TIMx, FunctionalState NewState);
+void TIM_SelectCCDMA(TIM_TypeDef* TIMx, FunctionalState NewState);
+void TIM_CCPreloadControl(TIM_TypeDef* TIMx, FunctionalState NewState);
+void TIM_OC1PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload);
+void TIM_OC2PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload);
+void TIM_OC3PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload);
+void TIM_OC4PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload);
+void TIM_OC1FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast);
+void TIM_OC2FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast);
+void TIM_OC3FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast);
+void TIM_OC4FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast);
+void TIM_ClearOC1Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear);
+void TIM_ClearOC2Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear);
+void TIM_ClearOC3Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear);
+void TIM_ClearOC4Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear);
+void TIM_OC1PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity);
+void TIM_OC1NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity);
+void TIM_OC2PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity);
+void TIM_OC2NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity);
+void TIM_OC3PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity);
+void TIM_OC3NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity);
+void TIM_OC4PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity);
+void TIM_CCxCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCx);
+void TIM_CCxNCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCxN);
+void TIM_SelectOCxM(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_OCMode);
+void TIM_UpdateDisableConfig(TIM_TypeDef* TIMx, FunctionalState NewState);
+void TIM_UpdateRequestConfig(TIM_TypeDef* TIMx, uint16_t TIM_UpdateSource);
+void TIM_SelectHallSensor(TIM_TypeDef* TIMx, FunctionalState NewState);
+void TIM_SelectOnePulseMode(TIM_TypeDef* TIMx, uint16_t TIM_OPMode);
+void TIM_SelectOutputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_TRGOSource);
+void TIM_SelectSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_SlaveMode);
+void TIM_SelectMasterSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_MasterSlaveMode);
+void TIM_SetCounter(TIM_TypeDef* TIMx, uint16_t Counter);
+void TIM_SetAutoreload(TIM_TypeDef* TIMx, uint16_t Autoreload);
+void TIM_SetCompare1(TIM_TypeDef* TIMx, uint16_t Compare1);
+void TIM_SetCompare2(TIM_TypeDef* TIMx, uint16_t Compare2);
+void TIM_SetCompare3(TIM_TypeDef* TIMx, uint16_t Compare3);
+void TIM_SetCompare4(TIM_TypeDef* TIMx, uint16_t Compare4);
+void TIM_SetIC1Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC);
+void TIM_SetIC2Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC);
+void TIM_SetIC3Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC);
+void TIM_SetIC4Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC);
+void TIM_SetClockDivision(TIM_TypeDef* TIMx, uint16_t TIM_CKD);
+uint16_t TIM_GetCapture1(TIM_TypeDef* TIMx);
+uint16_t TIM_GetCapture2(TIM_TypeDef* TIMx);
+uint16_t TIM_GetCapture3(TIM_TypeDef* TIMx);
+uint16_t TIM_GetCapture4(TIM_TypeDef* TIMx);
+uint16_t TIM_GetCounter(TIM_TypeDef* TIMx);
+uint16_t TIM_GetPrescaler(TIM_TypeDef* TIMx);
+FlagStatus TIM_GetFlagStatus(TIM_TypeDef* TIMx, uint16_t TIM_FLAG);
+void TIM_ClearFlag(TIM_TypeDef* TIMx, uint16_t TIM_FLAG);
+ITStatus TIM_GetITStatus(TIM_TypeDef* TIMx, uint16_t TIM_IT);
+void TIM_ClearITPendingBit(TIM_TypeDef* TIMx, uint16_t TIM_IT);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__STM32F10x_TIM_H */
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */
+
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/STM32_4路称重_Git提交精简工程/src/STM32F10x_FWLib/inc/stm32f10x_usart.h b/STM32_4路称重_Git提交精简工程/src/STM32F10x_FWLib/inc/stm32f10x_usart.h
new file mode 100755
index 0000000..61ae249
--- /dev/null
+++ b/STM32_4路称重_Git提交精简工程/src/STM32F10x_FWLib/inc/stm32f10x_usart.h
@@ -0,0 +1,412 @@
+/**
+  ******************************************************************************
+  * @file    stm32f10x_usart.h
+  * @author  MCD Application Team
+  * @version V3.5.0
+  * @date    11-March-2011
+  * @brief   This file contains all the functions prototypes for the USART 
+  *          firmware library.
+  ******************************************************************************
+  * @attention
+  *
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+  *
+  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F10x_USART_H
+#define __STM32F10x_USART_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x.h"
+
+/** @addtogroup STM32F10x_StdPeriph_Driver
+  * @{
+  */
+
+/** @addtogroup USART
+  * @{
+  */ 
+
+/** @defgroup USART_Exported_Types
+  * @{
+  */ 
+
+/** 
+  * @brief  USART Init Structure definition  
+  */ 
+  
+typedef struct
+{
+  uint32_t USART_BaudRate;            /*!< This member configures the USART communication baud rate.
+                                           The baud rate is computed using the following formula:
+                                            - IntegerDivider = ((PCLKx) / (16 * (USART_InitStruct->USART_BaudRate)))
+                                            - FractionalDivider = ((IntegerDivider - ((u32) IntegerDivider)) * 16) + 0.5 */
+
+  uint16_t USART_WordLength;          /*!< Specifies the number of data bits transmitted or received in a frame.
+                                           This parameter can be a value of @ref USART_Word_Length */
+
+  uint16_t USART_StopBits;            /*!< Specifies the number of stop bits transmitted.
+                                           This parameter can be a value of @ref USART_Stop_Bits */
+
+  uint16_t USART_Parity;              /*!< Specifies the parity mode.
+                                           This parameter can be a value of @ref USART_Parity
+                                           @note When parity is enabled, the computed parity is inserted
+                                                 at the MSB position of the transmitted data (9th bit when
+                                                 the word length is set to 9 data bits; 8th bit when the
+                                                 word length is set to 8 data bits). */
+ 
+  uint16_t USART_Mode;                /*!< Specifies wether the Receive or Transmit mode is enabled or disabled.
+                                           This parameter can be a value of @ref USART_Mode */
+
+  uint16_t USART_HardwareFlowControl; /*!< Specifies wether the hardware flow control mode is enabled
+                                           or disabled.
+                                           This parameter can be a value of @ref USART_Hardware_Flow_Control */
+} USART_InitTypeDef;
+
+/** 
+  * @brief  USART Clock Init Structure definition  
+  */ 
+  
+typedef struct
+{
+
+  uint16_t USART_Clock;   /*!< Specifies whether the USART clock is enabled or disabled.
+                               This parameter can be a value of @ref USART_Clock */
+
+  uint16_t USART_CPOL;    /*!< Specifies the steady state value of the serial clock.
+                               This parameter can be a value of @ref USART_Clock_Polarity */
+
+  uint16_t USART_CPHA;    /*!< Specifies the clock transition on which the bit capture is made.
+                               This parameter can be a value of @ref USART_Clock_Phase */
+
+  uint16_t USART_LastBit; /*!< Specifies whether the clock pulse corresponding to the last transmitted
+                               data bit (MSB) has to be output on the SCLK pin in synchronous mode.
+                               This parameter can be a value of @ref USART_Last_Bit */
+} USART_ClockInitTypeDef;
+
+/**
+  * @}
+  */ 
+
+/** @defgroup USART_Exported_Constants
+  * @{
+  */ 
+  
+#define IS_USART_ALL_PERIPH(PERIPH) (((PERIPH) == USART1) || \
+                                     ((PERIPH) == USART2) || \
+                                     ((PERIPH) == USART3) || \
+                                     ((PERIPH) == UART4) || \
+                                     ((PERIPH) == UART5))
+
+#define IS_USART_123_PERIPH(PERIPH) (((PERIPH) == USART1) || \
+                                     ((PERIPH) == USART2) || \
+                                     ((PERIPH) == USART3))
+
+#define IS_USART_1234_PERIPH(PERIPH) (((PERIPH) == USART1) || \
+                                      ((PERIPH) == USART2) || \
+                                      ((PERIPH) == USART3) || \
+                                      ((PERIPH) == UART4))
+/** @defgroup USART_Word_Length 
+  * @{
+  */ 
+  
+#define USART_WordLength_8b                  ((uint16_t)0x0000)
+#define USART_WordLength_9b                  ((uint16_t)0x1000)
+                                    
+#define IS_USART_WORD_LENGTH(LENGTH) (((LENGTH) == USART_WordLength_8b) || \
+                                      ((LENGTH) == USART_WordLength_9b))
+/**
+  * @}
+  */ 
+
+/** @defgroup USART_Stop_Bits 
+  * @{
+  */ 
+  
+#define USART_StopBits_1                     ((uint16_t)0x0000)
+#define USART_StopBits_0_5                   ((uint16_t)0x1000)
+#define USART_StopBits_2                     ((uint16_t)0x2000)
+#define USART_StopBits_1_5                   ((uint16_t)0x3000)
+#define IS_USART_STOPBITS(STOPBITS) (((STOPBITS) == USART_StopBits_1) || \
+                                     ((STOPBITS) == USART_StopBits_0_5) || \
+                                     ((STOPBITS) == USART_StopBits_2) || \
+                                     ((STOPBITS) == USART_StopBits_1_5))
+/**
+  * @}
+  */ 
+
+/** @defgroup USART_Parity 
+  * @{
+  */ 
+  
+#define USART_Parity_No                      ((uint16_t)0x0000)
+#define USART_Parity_Even                    ((uint16_t)0x0400)
+#define USART_Parity_Odd                     ((uint16_t)0x0600) 
+#define IS_USART_PARITY(PARITY) (((PARITY) == USART_Parity_No) || \
+                                 ((PARITY) == USART_Parity_Even) || \
+                                 ((PARITY) == USART_Parity_Odd))
+/**
+  * @}
+  */ 
+
+/** @defgroup USART_Mode 
+  * @{
+  */ 
+  
+#define USART_Mode_Rx                        ((uint16_t)0x0004)
+#define USART_Mode_Tx                        ((uint16_t)0x0008)
+#define IS_USART_MODE(MODE) ((((MODE) & (uint16_t)0xFFF3) == 0x00) && ((MODE) != (uint16_t)0x00))
+/**
+  * @}
+  */ 
+
+/** @defgroup USART_Hardware_Flow_Control 
+  * @{
+  */ 
+#define USART_HardwareFlowControl_None       ((uint16_t)0x0000)
+#define USART_HardwareFlowControl_RTS        ((uint16_t)0x0100)
+#define USART_HardwareFlowControl_CTS        ((uint16_t)0x0200)
+#define USART_HardwareFlowControl_RTS_CTS    ((uint16_t)0x0300)
+#define IS_USART_HARDWARE_FLOW_CONTROL(CONTROL)\
+                              (((CONTROL) == USART_HardwareFlowControl_None) || \
+                               ((CONTROL) == USART_HardwareFlowControl_RTS) || \
+                               ((CONTROL) == USART_HardwareFlowControl_CTS) || \
+                               ((CONTROL) == USART_HardwareFlowControl_RTS_CTS))
+/**
+  * @}
+  */ 
+
+/** @defgroup USART_Clock 
+  * @{
+  */ 
+#define USART_Clock_Disable                  ((uint16_t)0x0000)
+#define USART_Clock_Enable                   ((uint16_t)0x0800)
+#define IS_USART_CLOCK(CLOCK) (((CLOCK) == USART_Clock_Disable) || \
+                               ((CLOCK) == USART_Clock_Enable))
+/**
+  * @}
+  */ 
+
+/** @defgroup USART_Clock_Polarity 
+  * @{
+  */
+  
+#define USART_CPOL_Low                       ((uint16_t)0x0000)
+#define USART_CPOL_High                      ((uint16_t)0x0400)
+#define IS_USART_CPOL(CPOL) (((CPOL) == USART_CPOL_Low) || ((CPOL) == USART_CPOL_High))
+
+/**
+  * @}
+  */ 
+
+/** @defgroup USART_Clock_Phase
+  * @{
+  */
+
+#define USART_CPHA_1Edge                     ((uint16_t)0x0000)
+#define USART_CPHA_2Edge                     ((uint16_t)0x0200)
+#define IS_USART_CPHA(CPHA) (((CPHA) == USART_CPHA_1Edge) || ((CPHA) == USART_CPHA_2Edge))
+
+/**
+  * @}
+  */
+
+/** @defgroup USART_Last_Bit
+  * @{
+  */
+
+#define USART_LastBit_Disable                ((uint16_t)0x0000)
+#define USART_LastBit_Enable                 ((uint16_t)0x0100)
+#define IS_USART_LASTBIT(LASTBIT) (((LASTBIT) == USART_LastBit_Disable) || \
+                                   ((LASTBIT) == USART_LastBit_Enable))
+/**
+  * @}
+  */ 
+
+/** @defgroup USART_Interrupt_definition 
+  * @{
+  */
+  
+#define USART_IT_PE                          ((uint16_t)0x0028)
+#define USART_IT_TXE                         ((uint16_t)0x0727)
+#define USART_IT_TC                          ((uint16_t)0x0626)
+#define USART_IT_RXNE                        ((uint16_t)0x0525)
+#define USART_IT_IDLE                        ((uint16_t)0x0424)
+#define USART_IT_LBD                         ((uint16_t)0x0846)
+#define USART_IT_CTS                         ((uint16_t)0x096A)
+#define USART_IT_ERR                         ((uint16_t)0x0060)
+#define USART_IT_ORE                         ((uint16_t)0x0360)
+#define USART_IT_NE                          ((uint16_t)0x0260)
+#define USART_IT_FE                          ((uint16_t)0x0160)
+#define IS_USART_CONFIG_IT(IT) (((IT) == USART_IT_PE) || ((IT) == USART_IT_TXE) || \
+                               ((IT) == USART_IT_TC) || ((IT) == USART_IT_RXNE) || \
+                               ((IT) == USART_IT_IDLE) || ((IT) == USART_IT_LBD) || \
+                               ((IT) == USART_IT_CTS) || ((IT) == USART_IT_ERR))
+#define IS_USART_GET_IT(IT) (((IT) == USART_IT_PE) || ((IT) == USART_IT_TXE) || \
+                            ((IT) == USART_IT_TC) || ((IT) == USART_IT_RXNE) || \
+                            ((IT) == USART_IT_IDLE) || ((IT) == USART_IT_LBD) || \
+                            ((IT) == USART_IT_CTS) || ((IT) == USART_IT_ORE) || \
+                            ((IT) == USART_IT_NE) || ((IT) == USART_IT_FE))
+#define IS_USART_CLEAR_IT(IT) (((IT) == USART_IT_TC) || ((IT) == USART_IT_RXNE) || \
+                               ((IT) == USART_IT_LBD) || ((IT) == USART_IT_CTS))
+/**
+  * @}
+  */
+
+/** @defgroup USART_DMA_Requests 
+  * @{
+  */
+
+#define USART_DMAReq_Tx                      ((uint16_t)0x0080)
+#define USART_DMAReq_Rx                      ((uint16_t)0x0040)
+#define IS_USART_DMAREQ(DMAREQ) ((((DMAREQ) & (uint16_t)0xFF3F) == 0x00) && ((DMAREQ) != (uint16_t)0x00))
+
+/**
+  * @}
+  */ 
+
+/** @defgroup USART_WakeUp_methods
+  * @{
+  */
+
+#define USART_WakeUp_IdleLine                ((uint16_t)0x0000)
+#define USART_WakeUp_AddressMark             ((uint16_t)0x0800)
+#define IS_USART_WAKEUP(WAKEUP) (((WAKEUP) == USART_WakeUp_IdleLine) || \
+                                 ((WAKEUP) == USART_WakeUp_AddressMark))
+/**
+  * @}
+  */
+
+/** @defgroup USART_LIN_Break_Detection_Length 
+  * @{
+  */
+  
+#define USART_LINBreakDetectLength_10b      ((uint16_t)0x0000)
+#define USART_LINBreakDetectLength_11b      ((uint16_t)0x0020)
+#define IS_USART_LIN_BREAK_DETECT_LENGTH(LENGTH) \
+                               (((LENGTH) == USART_LINBreakDetectLength_10b) || \
+                                ((LENGTH) == USART_LINBreakDetectLength_11b))
+/**
+  * @}
+  */
+
+/** @defgroup USART_IrDA_Low_Power 
+  * @{
+  */
+
+#define USART_IrDAMode_LowPower              ((uint16_t)0x0004)
+#define USART_IrDAMode_Normal                ((uint16_t)0x0000)
+#define IS_USART_IRDA_MODE(MODE) (((MODE) == USART_IrDAMode_LowPower) || \
+                                  ((MODE) == USART_IrDAMode_Normal))
+/**
+  * @}
+  */ 
+
+/** @defgroup USART_Flags 
+  * @{
+  */
+
+#define USART_FLAG_CTS                       ((uint16_t)0x0200)
+#define USART_FLAG_LBD                       ((uint16_t)0x0100)
+#define USART_FLAG_TXE                       ((uint16_t)0x0080)
+#define USART_FLAG_TC                        ((uint16_t)0x0040)
+#define USART_FLAG_RXNE                      ((uint16_t)0x0020)
+#define USART_FLAG_IDLE                      ((uint16_t)0x0010)
+#define USART_FLAG_ORE                       ((uint16_t)0x0008)
+#define USART_FLAG_NE                        ((uint16_t)0x0004)
+#define USART_FLAG_FE                        ((uint16_t)0x0002)
+#define USART_FLAG_PE                        ((uint16_t)0x0001)
+#define IS_USART_FLAG(FLAG) (((FLAG) == USART_FLAG_PE) || ((FLAG) == USART_FLAG_TXE) || \
+                             ((FLAG) == USART_FLAG_TC) || ((FLAG) == USART_FLAG_RXNE) || \
+                             ((FLAG) == USART_FLAG_IDLE) || ((FLAG) == USART_FLAG_LBD) || \
+                             ((FLAG) == USART_FLAG_CTS) || ((FLAG) == USART_FLAG_ORE) || \
+                             ((FLAG) == USART_FLAG_NE) || ((FLAG) == USART_FLAG_FE))
+                              
+#define IS_USART_CLEAR_FLAG(FLAG) ((((FLAG) & (uint16_t)0xFC9F) == 0x00) && ((FLAG) != (uint16_t)0x00))
+#define IS_USART_PERIPH_FLAG(PERIPH, USART_FLAG) ((((*(uint32_t*)&(PERIPH)) != UART4_BASE) &&\
+                                                  ((*(uint32_t*)&(PERIPH)) != UART5_BASE)) \
+                                                  || ((USART_FLAG) != USART_FLAG_CTS)) 
+#define IS_USART_BAUDRATE(BAUDRATE) (((BAUDRATE) > 0) && ((BAUDRATE) < 0x0044AA21))
+#define IS_USART_ADDRESS(ADDRESS) ((ADDRESS) <= 0xF)
+#define IS_USART_DATA(DATA) ((DATA) <= 0x1FF)
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+
+/** @defgroup USART_Exported_Macros
+  * @{
+  */ 
+
+/**
+  * @}
+  */ 
+
+/** @defgroup USART_Exported_Functions
+  * @{
+  */
+
+void USART_DeInit(USART_TypeDef* USARTx);
+void USART_Init(USART_TypeDef* USARTx, USART_InitTypeDef* USART_InitStruct);
+void USART_StructInit(USART_InitTypeDef* USART_InitStruct);
+void USART_ClockInit(USART_TypeDef* USARTx, USART_ClockInitTypeDef* USART_ClockInitStruct);
+void USART_ClockStructInit(USART_ClockInitTypeDef* USART_ClockInitStruct);
+void USART_Cmd(USART_TypeDef* USARTx, FunctionalState NewState);
+void USART_ITConfig(USART_TypeDef* USARTx, uint16_t USART_IT, FunctionalState NewState);
+void USART_DMACmd(USART_TypeDef* USARTx, uint16_t USART_DMAReq, FunctionalState NewState);
+void USART_SetAddress(USART_TypeDef* USARTx, uint8_t USART_Address);
+void USART_WakeUpConfig(USART_TypeDef* USARTx, uint16_t USART_WakeUp);
+void USART_ReceiverWakeUpCmd(USART_TypeDef* USARTx, FunctionalState NewState);
+void USART_LINBreakDetectLengthConfig(USART_TypeDef* USARTx, uint16_t USART_LINBreakDetectLength);
+void USART_LINCmd(USART_TypeDef* USARTx, FunctionalState NewState);
+void USART_SendData(USART_TypeDef* USARTx, uint16_t Data);
+uint16_t USART_ReceiveData(USART_TypeDef* USARTx);
+void USART_SendBreak(USART_TypeDef* USARTx);
+void USART_SetGuardTime(USART_TypeDef* USARTx, uint8_t USART_GuardTime);
+void USART_SetPrescaler(USART_TypeDef* USARTx, uint8_t USART_Prescaler);
+void USART_SmartCardCmd(USART_TypeDef* USARTx, FunctionalState NewState);
+void USART_SmartCardNACKCmd(USART_TypeDef* USARTx, FunctionalState NewState);
+void USART_HalfDuplexCmd(USART_TypeDef* USARTx, FunctionalState NewState);
+void USART_OverSampling8Cmd(USART_TypeDef* USARTx, FunctionalState NewState);
+void USART_OneBitMethodCmd(USART_TypeDef* USARTx, FunctionalState NewState);
+void USART_IrDAConfig(USART_TypeDef* USARTx, uint16_t USART_IrDAMode);
+void USART_IrDACmd(USART_TypeDef* USARTx, FunctionalState NewState);
+FlagStatus USART_GetFlagStatus(USART_TypeDef* USARTx, uint16_t USART_FLAG);
+void USART_ClearFlag(USART_TypeDef* USARTx, uint16_t USART_FLAG);
+ITStatus USART_GetITStatus(USART_TypeDef* USARTx, uint16_t USART_IT);
+void USART_ClearITPendingBit(USART_TypeDef* USARTx, uint16_t USART_IT);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F10x_USART_H */
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/STM32_4路称重_Git提交精简工程/src/STM32F10x_FWLib/inc/stm32f10x_wwdg.h b/STM32_4路称重_Git提交精简工程/src/STM32F10x_FWLib/inc/stm32f10x_wwdg.h
new file mode 100755
index 0000000..cd573da
--- /dev/null
+++ b/STM32_4路称重_Git提交精简工程/src/STM32F10x_FWLib/inc/stm32f10x_wwdg.h
@@ -0,0 +1,115 @@
+/**
+  ******************************************************************************
+  * @file    stm32f10x_wwdg.h
+  * @author  MCD Application Team
+  * @version V3.5.0
+  * @date    11-March-2011
+  * @brief   This file contains all the functions prototypes for the WWDG firmware
+  *          library.
+  ******************************************************************************
+  * @attention
+  *
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+  *
+  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F10x_WWDG_H
+#define __STM32F10x_WWDG_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x.h"
+
+/** @addtogroup STM32F10x_StdPeriph_Driver
+  * @{
+  */
+
+/** @addtogroup WWDG
+  * @{
+  */ 
+
+/** @defgroup WWDG_Exported_Types
+  * @{
+  */ 
+  
+/**
+  * @}
+  */ 
+
+/** @defgroup WWDG_Exported_Constants
+  * @{
+  */ 
+  
+/** @defgroup WWDG_Prescaler 
+  * @{
+  */ 
+  
+#define WWDG_Prescaler_1    ((uint32_t)0x00000000)
+#define WWDG_Prescaler_2    ((uint32_t)0x00000080)
+#define WWDG_Prescaler_4    ((uint32_t)0x00000100)
+#define WWDG_Prescaler_8    ((uint32_t)0x00000180)
+#define IS_WWDG_PRESCALER(PRESCALER) (((PRESCALER) == WWDG_Prescaler_1) || \
+                                      ((PRESCALER) == WWDG_Prescaler_2) || \
+                                      ((PRESCALER) == WWDG_Prescaler_4) || \
+                                      ((PRESCALER) == WWDG_Prescaler_8))
+#define IS_WWDG_WINDOW_VALUE(VALUE) ((VALUE) <= 0x7F)
+#define IS_WWDG_COUNTER(COUNTER) (((COUNTER) >= 0x40) && ((COUNTER) <= 0x7F))
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+
+/** @defgroup WWDG_Exported_Macros
+  * @{
+  */ 
+/**
+  * @}
+  */ 
+
+/** @defgroup WWDG_Exported_Functions
+  * @{
+  */ 
+  
+void WWDG_DeInit(void);
+void WWDG_SetPrescaler(uint32_t WWDG_Prescaler);
+void WWDG_SetWindowValue(uint8_t WindowValue);
+void WWDG_EnableIT(void);
+void WWDG_SetCounter(uint8_t Counter);
+void WWDG_Enable(uint8_t Counter);
+FlagStatus WWDG_GetFlagStatus(void);
+void WWDG_ClearFlag(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F10x_WWDG_H */
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/STM32_4路称重_Git提交精简工程/src/STM32F10x_FWLib/src/misc.c b/STM32_4路称重_Git提交精简工程/src/STM32F10x_FWLib/src/misc.c
new file mode 100755
index 0000000..ec9165f
--- /dev/null
+++ b/STM32_4路称重_Git提交精简工程/src/STM32F10x_FWLib/src/misc.c
@@ -0,0 +1,225 @@
+/**
+  ******************************************************************************
+  * @file    misc.c
+  * @author  MCD Application Team
+  * @version V3.5.0
+  * @date    11-March-2011
+  * @brief   This file provides all the miscellaneous firmware functions (add-on
+  *          to CMSIS functions).
+  ******************************************************************************
+  * @attention
+  *
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+  *
+  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "misc.h"
+
+/** @addtogroup STM32F10x_StdPeriph_Driver
+  * @{
+  */
+
+/** @defgroup MISC 
+  * @brief MISC driver modules
+  * @{
+  */
+
+/** @defgroup MISC_Private_TypesDefinitions
+  * @{
+  */
+
+/**
+  * @}
+  */ 
+
+/** @defgroup MISC_Private_Defines
+  * @{
+  */
+
+#define AIRCR_VECTKEY_MASK    ((uint32_t)0x05FA0000)
+/**
+  * @}
+  */
+
+/** @defgroup MISC_Private_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup MISC_Private_Variables
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup MISC_Private_FunctionPrototypes
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup MISC_Private_Functions
+  * @{
+  */
+
+/**
+  * @brief  Configures the priority grouping: pre-emption priority and subpriority.
+  * @param  NVIC_PriorityGroup: specifies the priority grouping bits length. 
+  *   This parameter can be one of the following values:
+  *     @arg NVIC_PriorityGroup_0: 0 bits for pre-emption priority
+  *                                4 bits for subpriority
+  *     @arg NVIC_PriorityGroup_1: 1 bits for pre-emption priority
+  *                                3 bits for subpriority
+  *     @arg NVIC_PriorityGroup_2: 2 bits for pre-emption priority
+  *                                2 bits for subpriority
+  *     @arg NVIC_PriorityGroup_3: 3 bits for pre-emption priority
+  *                                1 bits for subpriority
+  *     @arg NVIC_PriorityGroup_4: 4 bits for pre-emption priority
+  *                                0 bits for subpriority
+  * @retval None
+  */
+void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup)
+{
+  /* Check the parameters */
+  assert_param(IS_NVIC_PRIORITY_GROUP(NVIC_PriorityGroup));
+  
+  /* Set the PRIGROUP[10:8] bits according to NVIC_PriorityGroup value */
+  SCB->AIRCR = AIRCR_VECTKEY_MASK | NVIC_PriorityGroup;
+}
+
+/**
+  * @brief  Initializes the NVIC peripheral according to the specified
+  *         parameters in the NVIC_InitStruct.
+  * @param  NVIC_InitStruct: pointer to a NVIC_InitTypeDef structure that contains
+  *         the configuration information for the specified NVIC peripheral.
+  * @retval None
+  */
+void NVIC_Init(NVIC_InitTypeDef* NVIC_InitStruct)
+{
+  uint32_t tmppriority = 0x00, tmppre = 0x00, tmpsub = 0x0F;
+  
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NVIC_InitStruct->NVIC_IRQChannelCmd));
+  assert_param(IS_NVIC_PREEMPTION_PRIORITY(NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority));  
+  assert_param(IS_NVIC_SUB_PRIORITY(NVIC_InitStruct->NVIC_IRQChannelSubPriority));
+    
+  if (NVIC_InitStruct->NVIC_IRQChannelCmd != DISABLE)
+  {
+    /* Compute the Corresponding IRQ Priority --------------------------------*/    
+    tmppriority = (0x700 - ((SCB->AIRCR) & (uint32_t)0x700))>> 0x08;
+    tmppre = (0x4 - tmppriority);
+    tmpsub = tmpsub >> tmppriority;
+
+    tmppriority = (uint32_t)NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority << tmppre;
+    tmppriority |=  NVIC_InitStruct->NVIC_IRQChannelSubPriority & tmpsub;
+    tmppriority = tmppriority << 0x04;
+        
+    NVIC->IP[NVIC_InitStruct->NVIC_IRQChannel] = tmppriority;
+    
+    /* Enable the Selected IRQ Channels --------------------------------------*/
+    NVIC->ISER[NVIC_InitStruct->NVIC_IRQChannel >> 0x05] =
+      (uint32_t)0x01 << (NVIC_InitStruct->NVIC_IRQChannel & (uint8_t)0x1F);
+  }
+  else
+  {
+    /* Disable the Selected IRQ Channels -------------------------------------*/
+    NVIC->ICER[NVIC_InitStruct->NVIC_IRQChannel >> 0x05] =
+      (uint32_t)0x01 << (NVIC_InitStruct->NVIC_IRQChannel & (uint8_t)0x1F);
+  }
+}
+
+/**
+  * @brief  Sets the vector table location and Offset.
+  * @param  NVIC_VectTab: specifies if the vector table is in RAM or FLASH memory.
+  *   This parameter can be one of the following values:
+  *     @arg NVIC_VectTab_RAM
+  *     @arg NVIC_VectTab_FLASH
+  * @param  Offset: Vector Table base offset field. This value must be a multiple 
+  *         of 0x200.
+  * @retval None
+  */
+void NVIC_SetVectorTable(uint32_t NVIC_VectTab, uint32_t Offset)
+{ 
+  /* Check the parameters */
+  assert_param(IS_NVIC_VECTTAB(NVIC_VectTab));
+  assert_param(IS_NVIC_OFFSET(Offset));  
+   
+  SCB->VTOR = NVIC_VectTab | (Offset & (uint32_t)0x1FFFFF80);
+}
+
+/**
+  * @brief  Selects the condition for the system to enter low power mode.
+  * @param  LowPowerMode: Specifies the new mode for the system to enter low power mode.
+  *   This parameter can be one of the following values:
+  *     @arg NVIC_LP_SEVONPEND
+  *     @arg NVIC_LP_SLEEPDEEP
+  *     @arg NVIC_LP_SLEEPONEXIT
+  * @param  NewState: new state of LP condition. This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void NVIC_SystemLPConfig(uint8_t LowPowerMode, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_NVIC_LP(LowPowerMode));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));  
+  
+  if (NewState != DISABLE)
+  {
+    SCB->SCR |= LowPowerMode;
+  }
+  else
+  {
+    SCB->SCR &= (uint32_t)(~(uint32_t)LowPowerMode);
+  }
+}
+
+/**
+  * @brief  Configures the SysTick clock source.
+  * @param  SysTick_CLKSource: specifies the SysTick clock source.
+  *   This parameter can be one of the following values:
+  *     @arg SysTick_CLKSource_HCLK_Div8: AHB clock divided by 8 selected as SysTick clock source.
+  *     @arg SysTick_CLKSource_HCLK: AHB clock selected as SysTick clock source.
+  * @retval None
+  */
+void SysTick_CLKSourceConfig(uint32_t SysTick_CLKSource)
+{
+  /* Check the parameters */
+  assert_param(IS_SYSTICK_CLK_SOURCE(SysTick_CLKSource));
+  if (SysTick_CLKSource == SysTick_CLKSource_HCLK)
+  {
+    SysTick->CTRL |= SysTick_CLKSource_HCLK;
+  }
+  else
+  {
+    SysTick->CTRL &= SysTick_CLKSource_HCLK_Div8;
+  }
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/STM32_4路称重_Git提交精简工程/src/STM32F10x_FWLib/src/stm32f10x_adc.c b/STM32_4路称重_Git提交精简工程/src/STM32F10x_FWLib/src/stm32f10x_adc.c
new file mode 100755
index 0000000..916a096
--- /dev/null
+++ b/STM32_4路称重_Git提交精简工程/src/STM32F10x_FWLib/src/stm32f10x_adc.c
@@ -0,0 +1,1307 @@
+/**
+  ******************************************************************************
+  * @file    stm32f10x_adc.c
+  * @author  MCD Application Team
+  * @version V3.5.0
+  * @date    11-March-2011
+  * @brief   This file provides all the ADC firmware functions.
+  ******************************************************************************
+  * @attention
+  *
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+  *
+  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x_adc.h"
+#include "stm32f10x_rcc.h"
+
+/** @addtogroup STM32F10x_StdPeriph_Driver
+  * @{
+  */
+
+/** @defgroup ADC 
+  * @brief ADC driver modules
+  * @{
+  */
+
+/** @defgroup ADC_Private_TypesDefinitions
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup ADC_Private_Defines
+  * @{
+  */
+
+/* ADC DISCNUM mask */
+#define CR1_DISCNUM_Reset           ((uint32_t)0xFFFF1FFF)
+
+/* ADC DISCEN mask */
+#define CR1_DISCEN_Set              ((uint32_t)0x00000800)
+#define CR1_DISCEN_Reset            ((uint32_t)0xFFFFF7FF)
+
+/* ADC JAUTO mask */
+#define CR1_JAUTO_Set               ((uint32_t)0x00000400)
+#define CR1_JAUTO_Reset             ((uint32_t)0xFFFFFBFF)
+
+/* ADC JDISCEN mask */
+#define CR1_JDISCEN_Set             ((uint32_t)0x00001000)
+#define CR1_JDISCEN_Reset           ((uint32_t)0xFFFFEFFF)
+
+/* ADC AWDCH mask */
+#define CR1_AWDCH_Reset             ((uint32_t)0xFFFFFFE0)
+
+/* ADC Analog watchdog enable mode mask */
+#define CR1_AWDMode_Reset           ((uint32_t)0xFF3FFDFF)
+
+/* CR1 register Mask */
+#define CR1_CLEAR_Mask              ((uint32_t)0xFFF0FEFF)
+
+/* ADC ADON mask */
+#define CR2_ADON_Set                ((uint32_t)0x00000001)
+#define CR2_ADON_Reset              ((uint32_t)0xFFFFFFFE)
+
+/* ADC DMA mask */
+#define CR2_DMA_Set                 ((uint32_t)0x00000100)
+#define CR2_DMA_Reset               ((uint32_t)0xFFFFFEFF)
+
+/* ADC RSTCAL mask */
+#define CR2_RSTCAL_Set              ((uint32_t)0x00000008)
+
+/* ADC CAL mask */
+#define CR2_CAL_Set                 ((uint32_t)0x00000004)
+
+/* ADC SWSTART mask */
+#define CR2_SWSTART_Set             ((uint32_t)0x00400000)
+
+/* ADC EXTTRIG mask */
+#define CR2_EXTTRIG_Set             ((uint32_t)0x00100000)
+#define CR2_EXTTRIG_Reset           ((uint32_t)0xFFEFFFFF)
+
+/* ADC Software start mask */
+#define CR2_EXTTRIG_SWSTART_Set     ((uint32_t)0x00500000)
+#define CR2_EXTTRIG_SWSTART_Reset   ((uint32_t)0xFFAFFFFF)
+
+/* ADC JEXTSEL mask */
+#define CR2_JEXTSEL_Reset           ((uint32_t)0xFFFF8FFF)
+
+/* ADC JEXTTRIG mask */
+#define CR2_JEXTTRIG_Set            ((uint32_t)0x00008000)
+#define CR2_JEXTTRIG_Reset          ((uint32_t)0xFFFF7FFF)
+
+/* ADC JSWSTART mask */
+#define CR2_JSWSTART_Set            ((uint32_t)0x00200000)
+
+/* ADC injected software start mask */
+#define CR2_JEXTTRIG_JSWSTART_Set   ((uint32_t)0x00208000)
+#define CR2_JEXTTRIG_JSWSTART_Reset ((uint32_t)0xFFDF7FFF)
+
+/* ADC TSPD mask */
+#define CR2_TSVREFE_Set             ((uint32_t)0x00800000)
+#define CR2_TSVREFE_Reset           ((uint32_t)0xFF7FFFFF)
+
+/* CR2 register Mask */
+#define CR2_CLEAR_Mask              ((uint32_t)0xFFF1F7FD)
+
+/* ADC SQx mask */
+#define SQR3_SQ_Set                 ((uint32_t)0x0000001F)
+#define SQR2_SQ_Set                 ((uint32_t)0x0000001F)
+#define SQR1_SQ_Set                 ((uint32_t)0x0000001F)
+
+/* SQR1 register Mask */
+#define SQR1_CLEAR_Mask             ((uint32_t)0xFF0FFFFF)
+
+/* ADC JSQx mask */
+#define JSQR_JSQ_Set                ((uint32_t)0x0000001F)
+
+/* ADC JL mask */
+#define JSQR_JL_Set                 ((uint32_t)0x00300000)
+#define JSQR_JL_Reset               ((uint32_t)0xFFCFFFFF)
+
+/* ADC SMPx mask */
+#define SMPR1_SMP_Set               ((uint32_t)0x00000007)
+#define SMPR2_SMP_Set               ((uint32_t)0x00000007)
+
+/* ADC JDRx registers offset */
+#define JDR_Offset                  ((uint8_t)0x28)
+
+/* ADC1 DR register base address */
+#define DR_ADDRESS                  ((uint32_t)0x4001244C)
+
+/**
+  * @}
+  */
+
+/** @defgroup ADC_Private_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup ADC_Private_Variables
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup ADC_Private_FunctionPrototypes
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup ADC_Private_Functions
+  * @{
+  */
+
+/**
+  * @brief  Deinitializes the ADCx peripheral registers to their default reset values.
+  * @param  ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
+  * @retval None
+  */
+void ADC_DeInit(ADC_TypeDef* ADCx)
+{
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_PERIPH(ADCx));
+  
+  if (ADCx == ADC1)
+  {
+    /* Enable ADC1 reset state */
+    RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC1, ENABLE);
+    /* Release ADC1 from reset state */
+    RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC1, DISABLE);
+  }
+  else if (ADCx == ADC2)
+  {
+    /* Enable ADC2 reset state */
+    RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC2, ENABLE);
+    /* Release ADC2 from reset state */
+    RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC2, DISABLE);
+  }
+  else
+  {
+    if (ADCx == ADC3)
+    {
+      /* Enable ADC3 reset state */
+      RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC3, ENABLE);
+      /* Release ADC3 from reset state */
+      RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC3, DISABLE);
+    }
+  }
+}
+
+/**
+  * @brief  Initializes the ADCx peripheral according to the specified parameters
+  *         in the ADC_InitStruct.
+  * @param  ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
+  * @param  ADC_InitStruct: pointer to an ADC_InitTypeDef structure that contains
+  *         the configuration information for the specified ADC peripheral.
+  * @retval None
+  */
+void ADC_Init(ADC_TypeDef* ADCx, ADC_InitTypeDef* ADC_InitStruct)
+{
+  uint32_t tmpreg1 = 0;
+  uint8_t tmpreg2 = 0;
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_PERIPH(ADCx));
+  assert_param(IS_ADC_MODE(ADC_InitStruct->ADC_Mode));
+  assert_param(IS_FUNCTIONAL_STATE(ADC_InitStruct->ADC_ScanConvMode));
+  assert_param(IS_FUNCTIONAL_STATE(ADC_InitStruct->ADC_ContinuousConvMode));
+  assert_param(IS_ADC_EXT_TRIG(ADC_InitStruct->ADC_ExternalTrigConv));   
+  assert_param(IS_ADC_DATA_ALIGN(ADC_InitStruct->ADC_DataAlign)); 
+  assert_param(IS_ADC_REGULAR_LENGTH(ADC_InitStruct->ADC_NbrOfChannel));
+
+  /*---------------------------- ADCx CR1 Configuration -----------------*/
+  /* Get the ADCx CR1 value */
+  tmpreg1 = ADCx->CR1;
+  /* Clear DUALMOD and SCAN bits */
+  tmpreg1 &= CR1_CLEAR_Mask;
+  /* Configure ADCx: Dual mode and scan conversion mode */
+  /* Set DUALMOD bits according to ADC_Mode value */
+  /* Set SCAN bit according to ADC_ScanConvMode value */
+  tmpreg1 |= (uint32_t)(ADC_InitStruct->ADC_Mode | ((uint32_t)ADC_InitStruct->ADC_ScanConvMode << 8));
+  /* Write to ADCx CR1 */
+  ADCx->CR1 = tmpreg1;
+
+  /*---------------------------- ADCx CR2 Configuration -----------------*/
+  /* Get the ADCx CR2 value */
+  tmpreg1 = ADCx->CR2;
+  /* Clear CONT, ALIGN and EXTSEL bits */
+  tmpreg1 &= CR2_CLEAR_Mask;
+  /* Configure ADCx: external trigger event and continuous conversion mode */
+  /* Set ALIGN bit according to ADC_DataAlign value */
+  /* Set EXTSEL bits according to ADC_ExternalTrigConv value */
+  /* Set CONT bit according to ADC_ContinuousConvMode value */
+  tmpreg1 |= (uint32_t)(ADC_InitStruct->ADC_DataAlign | ADC_InitStruct->ADC_ExternalTrigConv |
+            ((uint32_t)ADC_InitStruct->ADC_ContinuousConvMode << 1));
+  /* Write to ADCx CR2 */
+  ADCx->CR2 = tmpreg1;
+
+  /*---------------------------- ADCx SQR1 Configuration -----------------*/
+  /* Get the ADCx SQR1 value */
+  tmpreg1 = ADCx->SQR1;
+  /* Clear L bits */
+  tmpreg1 &= SQR1_CLEAR_Mask;
+  /* Configure ADCx: regular channel sequence length */
+  /* Set L bits according to ADC_NbrOfChannel value */
+  tmpreg2 |= (uint8_t) (ADC_InitStruct->ADC_NbrOfChannel - (uint8_t)1);
+  tmpreg1 |= (uint32_t)tmpreg2 << 20;
+  /* Write to ADCx SQR1 */
+  ADCx->SQR1 = tmpreg1;
+}
+
+/**
+  * @brief  Fills each ADC_InitStruct member with its default value.
+  * @param  ADC_InitStruct : pointer to an ADC_InitTypeDef structure which will be initialized.
+  * @retval None
+  */
+void ADC_StructInit(ADC_InitTypeDef* ADC_InitStruct)
+{
+  /* Reset ADC init structure parameters values */
+  /* Initialize the ADC_Mode member */
+  ADC_InitStruct->ADC_Mode = ADC_Mode_Independent;
+  /* initialize the ADC_ScanConvMode member */
+  ADC_InitStruct->ADC_ScanConvMode = DISABLE;
+  /* Initialize the ADC_ContinuousConvMode member */
+  ADC_InitStruct->ADC_ContinuousConvMode = DISABLE;
+  /* Initialize the ADC_ExternalTrigConv member */
+  ADC_InitStruct->ADC_ExternalTrigConv = ADC_ExternalTrigConv_T1_CC1;
+  /* Initialize the ADC_DataAlign member */
+  ADC_InitStruct->ADC_DataAlign = ADC_DataAlign_Right;
+  /* Initialize the ADC_NbrOfChannel member */
+  ADC_InitStruct->ADC_NbrOfChannel = 1;
+}
+
+/**
+  * @brief  Enables or disables the specified ADC peripheral.
+  * @param  ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
+  * @param  NewState: new state of the ADCx peripheral.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void ADC_Cmd(ADC_TypeDef* ADCx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_PERIPH(ADCx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  if (NewState != DISABLE)
+  {
+    /* Set the ADON bit to wake up the ADC from power down mode */
+    ADCx->CR2 |= CR2_ADON_Set;
+  }
+  else
+  {
+    /* Disable the selected ADC peripheral */
+    ADCx->CR2 &= CR2_ADON_Reset;
+  }
+}
+
+/**
+  * @brief  Enables or disables the specified ADC DMA request.
+  * @param  ADCx: where x can be 1 or 3 to select the ADC peripheral.
+  *   Note: ADC2 hasn't a DMA capability.
+  * @param  NewState: new state of the selected ADC DMA transfer.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void ADC_DMACmd(ADC_TypeDef* ADCx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_ADC_DMA_PERIPH(ADCx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  if (NewState != DISABLE)
+  {
+    /* Enable the selected ADC DMA request */
+    ADCx->CR2 |= CR2_DMA_Set;
+  }
+  else
+  {
+    /* Disable the selected ADC DMA request */
+    ADCx->CR2 &= CR2_DMA_Reset;
+  }
+}
+
+/**
+  * @brief  Enables or disables the specified ADC interrupts.
+  * @param  ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
+  * @param  ADC_IT: specifies the ADC interrupt sources to be enabled or disabled. 
+  *   This parameter can be any combination of the following values:
+  *     @arg ADC_IT_EOC: End of conversion interrupt mask
+  *     @arg ADC_IT_AWD: Analog watchdog interrupt mask
+  *     @arg ADC_IT_JEOC: End of injected conversion interrupt mask
+  * @param  NewState: new state of the specified ADC interrupts.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void ADC_ITConfig(ADC_TypeDef* ADCx, uint16_t ADC_IT, FunctionalState NewState)
+{
+  uint8_t itmask = 0;
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_PERIPH(ADCx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  assert_param(IS_ADC_IT(ADC_IT));
+  /* Get the ADC IT index */
+  itmask = (uint8_t)ADC_IT;
+  if (NewState != DISABLE)
+  {
+    /* Enable the selected ADC interrupts */
+    ADCx->CR1 |= itmask;
+  }
+  else
+  {
+    /* Disable the selected ADC interrupts */
+    ADCx->CR1 &= (~(uint32_t)itmask);
+  }
+}
+
+/**
+  * @brief  Resets the selected ADC calibration registers.
+  * @param  ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
+  * @retval None
+  */
+void ADC_ResetCalibration(ADC_TypeDef* ADCx)
+{
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_PERIPH(ADCx));
+  /* Resets the selected ADC calibration registers */  
+  ADCx->CR2 |= CR2_RSTCAL_Set;
+}
+
+/**
+  * @brief  Gets the selected ADC reset calibration registers status.
+  * @param  ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
+  * @retval The new state of ADC reset calibration registers (SET or RESET).
+  */
+FlagStatus ADC_GetResetCalibrationStatus(ADC_TypeDef* ADCx)
+{
+  FlagStatus bitstatus = RESET;
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_PERIPH(ADCx));
+  /* Check the status of RSTCAL bit */
+  if ((ADCx->CR2 & CR2_RSTCAL_Set) != (uint32_t)RESET)
+  {
+    /* RSTCAL bit is set */
+    bitstatus = SET;
+  }
+  else
+  {
+    /* RSTCAL bit is reset */
+    bitstatus = RESET;
+  }
+  /* Return the RSTCAL bit status */
+  return  bitstatus;
+}
+
+/**
+  * @brief  Starts the selected ADC calibration process.
+  * @param  ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
+  * @retval None
+  */
+void ADC_StartCalibration(ADC_TypeDef* ADCx)
+{
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_PERIPH(ADCx));
+  /* Enable the selected ADC calibration process */  
+  ADCx->CR2 |= CR2_CAL_Set;
+}
+
+/**
+  * @brief  Gets the selected ADC calibration status.
+  * @param  ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
+  * @retval The new state of ADC calibration (SET or RESET).
+  */
+FlagStatus ADC_GetCalibrationStatus(ADC_TypeDef* ADCx)
+{
+  FlagStatus bitstatus = RESET;
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_PERIPH(ADCx));
+  /* Check the status of CAL bit */
+  if ((ADCx->CR2 & CR2_CAL_Set) != (uint32_t)RESET)
+  {
+    /* CAL bit is set: calibration on going */
+    bitstatus = SET;
+  }
+  else
+  {
+    /* CAL bit is reset: end of calibration */
+    bitstatus = RESET;
+  }
+  /* Return the CAL bit status */
+  return  bitstatus;
+}
+
+/**
+  * @brief  Enables or disables the selected ADC software start conversion .
+  * @param  ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
+  * @param  NewState: new state of the selected ADC software start conversion.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void ADC_SoftwareStartConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_PERIPH(ADCx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  if (NewState != DISABLE)
+  {
+    /* Enable the selected ADC conversion on external event and start the selected
+       ADC conversion */
+    ADCx->CR2 |= CR2_EXTTRIG_SWSTART_Set;
+  }
+  else
+  {
+    /* Disable the selected ADC conversion on external event and stop the selected
+       ADC conversion */
+    ADCx->CR2 &= CR2_EXTTRIG_SWSTART_Reset;
+  }
+}
+
+/**
+  * @brief  Gets the selected ADC Software start conversion Status.
+  * @param  ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
+  * @retval The new state of ADC software start conversion (SET or RESET).
+  */
+FlagStatus ADC_GetSoftwareStartConvStatus(ADC_TypeDef* ADCx)
+{
+  FlagStatus bitstatus = RESET;
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_PERIPH(ADCx));
+  /* Check the status of SWSTART bit */
+  if ((ADCx->CR2 & CR2_SWSTART_Set) != (uint32_t)RESET)
+  {
+    /* SWSTART bit is set */
+    bitstatus = SET;
+  }
+  else
+  {
+    /* SWSTART bit is reset */
+    bitstatus = RESET;
+  }
+  /* Return the SWSTART bit status */
+  return  bitstatus;
+}
+
+/**
+  * @brief  Configures the discontinuous mode for the selected ADC regular
+  *         group channel.
+  * @param  ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
+  * @param  Number: specifies the discontinuous mode regular channel
+  *         count value. This number must be between 1 and 8.
+  * @retval None
+  */
+void ADC_DiscModeChannelCountConfig(ADC_TypeDef* ADCx, uint8_t Number)
+{
+  uint32_t tmpreg1 = 0;
+  uint32_t tmpreg2 = 0;
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_PERIPH(ADCx));
+  assert_param(IS_ADC_REGULAR_DISC_NUMBER(Number));
+  /* Get the old register value */
+  tmpreg1 = ADCx->CR1;
+  /* Clear the old discontinuous mode channel count */
+  tmpreg1 &= CR1_DISCNUM_Reset;
+  /* Set the discontinuous mode channel count */
+  tmpreg2 = Number - 1;
+  tmpreg1 |= tmpreg2 << 13;
+  /* Store the new register value */
+  ADCx->CR1 = tmpreg1;
+}
+
+/**
+  * @brief  Enables or disables the discontinuous mode on regular group
+  *         channel for the specified ADC
+  * @param  ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
+  * @param  NewState: new state of the selected ADC discontinuous mode
+  *         on regular group channel.
+  *         This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void ADC_DiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_PERIPH(ADCx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  if (NewState != DISABLE)
+  {
+    /* Enable the selected ADC regular discontinuous mode */
+    ADCx->CR1 |= CR1_DISCEN_Set;
+  }
+  else
+  {
+    /* Disable the selected ADC regular discontinuous mode */
+    ADCx->CR1 &= CR1_DISCEN_Reset;
+  }
+}
+
+/**
+  * @brief  Configures for the selected ADC regular channel its corresponding
+  *         rank in the sequencer and its sample time.
+  * @param  ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
+  * @param  ADC_Channel: the ADC channel to configure. 
+  *   This parameter can be one of the following values:
+  *     @arg ADC_Channel_0: ADC Channel0 selected
+  *     @arg ADC_Channel_1: ADC Channel1 selected
+  *     @arg ADC_Channel_2: ADC Channel2 selected
+  *     @arg ADC_Channel_3: ADC Channel3 selected
+  *     @arg ADC_Channel_4: ADC Channel4 selected
+  *     @arg ADC_Channel_5: ADC Channel5 selected
+  *     @arg ADC_Channel_6: ADC Channel6 selected
+  *     @arg ADC_Channel_7: ADC Channel7 selected
+  *     @arg ADC_Channel_8: ADC Channel8 selected
+  *     @arg ADC_Channel_9: ADC Channel9 selected
+  *     @arg ADC_Channel_10: ADC Channel10 selected
+  *     @arg ADC_Channel_11: ADC Channel11 selected
+  *     @arg ADC_Channel_12: ADC Channel12 selected
+  *     @arg ADC_Channel_13: ADC Channel13 selected
+  *     @arg ADC_Channel_14: ADC Channel14 selected
+  *     @arg ADC_Channel_15: ADC Channel15 selected
+  *     @arg ADC_Channel_16: ADC Channel16 selected
+  *     @arg ADC_Channel_17: ADC Channel17 selected
+  * @param  Rank: The rank in the regular group sequencer. This parameter must be between 1 to 16.
+  * @param  ADC_SampleTime: The sample time value to be set for the selected channel. 
+  *   This parameter can be one of the following values:
+  *     @arg ADC_SampleTime_1Cycles5: Sample time equal to 1.5 cycles
+  *     @arg ADC_SampleTime_7Cycles5: Sample time equal to 7.5 cycles
+  *     @arg ADC_SampleTime_13Cycles5: Sample time equal to 13.5 cycles
+  *     @arg ADC_SampleTime_28Cycles5: Sample time equal to 28.5 cycles	
+  *     @arg ADC_SampleTime_41Cycles5: Sample time equal to 41.5 cycles	
+  *     @arg ADC_SampleTime_55Cycles5: Sample time equal to 55.5 cycles	
+  *     @arg ADC_SampleTime_71Cycles5: Sample time equal to 71.5 cycles	
+  *     @arg ADC_SampleTime_239Cycles5: Sample time equal to 239.5 cycles	
+  * @retval None
+  */
+void ADC_RegularChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime)
+{
+  uint32_t tmpreg1 = 0, tmpreg2 = 0;
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_PERIPH(ADCx));
+  assert_param(IS_ADC_CHANNEL(ADC_Channel));
+  assert_param(IS_ADC_REGULAR_RANK(Rank));
+  assert_param(IS_ADC_SAMPLE_TIME(ADC_SampleTime));
+  /* if ADC_Channel_10 ... ADC_Channel_17 is selected */
+  if (ADC_Channel > ADC_Channel_9)
+  {
+    /* Get the old register value */
+    tmpreg1 = ADCx->SMPR1;
+    /* Calculate the mask to clear */
+    tmpreg2 = SMPR1_SMP_Set << (3 * (ADC_Channel - 10));
+    /* Clear the old channel sample time */
+    tmpreg1 &= ~tmpreg2;
+    /* Calculate the mask to set */
+    tmpreg2 = (uint32_t)ADC_SampleTime << (3 * (ADC_Channel - 10));
+    /* Set the new channel sample time */
+    tmpreg1 |= tmpreg2;
+    /* Store the new register value */
+    ADCx->SMPR1 = tmpreg1;
+  }
+  else /* ADC_Channel include in ADC_Channel_[0..9] */
+  {
+    /* Get the old register value */
+    tmpreg1 = ADCx->SMPR2;
+    /* Calculate the mask to clear */
+    tmpreg2 = SMPR2_SMP_Set << (3 * ADC_Channel);
+    /* Clear the old channel sample time */
+    tmpreg1 &= ~tmpreg2;
+    /* Calculate the mask to set */
+    tmpreg2 = (uint32_t)ADC_SampleTime << (3 * ADC_Channel);
+    /* Set the new channel sample time */
+    tmpreg1 |= tmpreg2;
+    /* Store the new register value */
+    ADCx->SMPR2 = tmpreg1;
+  }
+  /* For Rank 1 to 6 */
+  if (Rank < 7)
+  {
+    /* Get the old register value */
+    tmpreg1 = ADCx->SQR3;
+    /* Calculate the mask to clear */
+    tmpreg2 = SQR3_SQ_Set << (5 * (Rank - 1));
+    /* Clear the old SQx bits for the selected rank */
+    tmpreg1 &= ~tmpreg2;
+    /* Calculate the mask to set */
+    tmpreg2 = (uint32_t)ADC_Channel << (5 * (Rank - 1));
+    /* Set the SQx bits for the selected rank */
+    tmpreg1 |= tmpreg2;
+    /* Store the new register value */
+    ADCx->SQR3 = tmpreg1;
+  }
+  /* For Rank 7 to 12 */
+  else if (Rank < 13)
+  {
+    /* Get the old register value */
+    tmpreg1 = ADCx->SQR2;
+    /* Calculate the mask to clear */
+    tmpreg2 = SQR2_SQ_Set << (5 * (Rank - 7));
+    /* Clear the old SQx bits for the selected rank */
+    tmpreg1 &= ~tmpreg2;
+    /* Calculate the mask to set */
+    tmpreg2 = (uint32_t)ADC_Channel << (5 * (Rank - 7));
+    /* Set the SQx bits for the selected rank */
+    tmpreg1 |= tmpreg2;
+    /* Store the new register value */
+    ADCx->SQR2 = tmpreg1;
+  }
+  /* For Rank 13 to 16 */
+  else
+  {
+    /* Get the old register value */
+    tmpreg1 = ADCx->SQR1;
+    /* Calculate the mask to clear */
+    tmpreg2 = SQR1_SQ_Set << (5 * (Rank - 13));
+    /* Clear the old SQx bits for the selected rank */
+    tmpreg1 &= ~tmpreg2;
+    /* Calculate the mask to set */
+    tmpreg2 = (uint32_t)ADC_Channel << (5 * (Rank - 13));
+    /* Set the SQx bits for the selected rank */
+    tmpreg1 |= tmpreg2;
+    /* Store the new register value */
+    ADCx->SQR1 = tmpreg1;
+  }
+}
+
+/**
+  * @brief  Enables or disables the ADCx conversion through external trigger.
+  * @param  ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
+  * @param  NewState: new state of the selected ADC external trigger start of conversion.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void ADC_ExternalTrigConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_PERIPH(ADCx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  if (NewState != DISABLE)
+  {
+    /* Enable the selected ADC conversion on external event */
+    ADCx->CR2 |= CR2_EXTTRIG_Set;
+  }
+  else
+  {
+    /* Disable the selected ADC conversion on external event */
+    ADCx->CR2 &= CR2_EXTTRIG_Reset;
+  }
+}
+
+/**
+  * @brief  Returns the last ADCx conversion result data for regular channel.
+  * @param  ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
+  * @retval The Data conversion value.
+  */
+uint16_t ADC_GetConversionValue(ADC_TypeDef* ADCx)
+{
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_PERIPH(ADCx));
+  /* Return the selected ADC conversion value */
+  return (uint16_t) ADCx->DR;
+}
+
+/**
+  * @brief  Returns the last ADC1 and ADC2 conversion result data in dual mode.
+  * @retval The Data conversion value.
+  */
+uint32_t ADC_GetDualModeConversionValue(void)
+{
+  /* Return the dual mode conversion value */
+  return (*(__IO uint32_t *) DR_ADDRESS);
+}
+
+/**
+  * @brief  Enables or disables the selected ADC automatic injected group
+  *         conversion after regular one.
+  * @param  ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
+  * @param  NewState: new state of the selected ADC auto injected conversion
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void ADC_AutoInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_PERIPH(ADCx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  if (NewState != DISABLE)
+  {
+    /* Enable the selected ADC automatic injected group conversion */
+    ADCx->CR1 |= CR1_JAUTO_Set;
+  }
+  else
+  {
+    /* Disable the selected ADC automatic injected group conversion */
+    ADCx->CR1 &= CR1_JAUTO_Reset;
+  }
+}
+
+/**
+  * @brief  Enables or disables the discontinuous mode for injected group
+  *         channel for the specified ADC
+  * @param  ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
+  * @param  NewState: new state of the selected ADC discontinuous mode
+  *         on injected group channel.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void ADC_InjectedDiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_PERIPH(ADCx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  if (NewState != DISABLE)
+  {
+    /* Enable the selected ADC injected discontinuous mode */
+    ADCx->CR1 |= CR1_JDISCEN_Set;
+  }
+  else
+  {
+    /* Disable the selected ADC injected discontinuous mode */
+    ADCx->CR1 &= CR1_JDISCEN_Reset;
+  }
+}
+
+/**
+  * @brief  Configures the ADCx external trigger for injected channels conversion.
+  * @param  ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
+  * @param  ADC_ExternalTrigInjecConv: specifies the ADC trigger to start injected conversion. 
+  *   This parameter can be one of the following values:
+  *     @arg ADC_ExternalTrigInjecConv_T1_TRGO: Timer1 TRGO event selected (for ADC1, ADC2 and ADC3)
+  *     @arg ADC_ExternalTrigInjecConv_T1_CC4: Timer1 capture compare4 selected (for ADC1, ADC2 and ADC3)
+  *     @arg ADC_ExternalTrigInjecConv_T2_TRGO: Timer2 TRGO event selected (for ADC1 and ADC2)
+  *     @arg ADC_ExternalTrigInjecConv_T2_CC1: Timer2 capture compare1 selected (for ADC1 and ADC2)
+  *     @arg ADC_ExternalTrigInjecConv_T3_CC4: Timer3 capture compare4 selected (for ADC1 and ADC2)
+  *     @arg ADC_ExternalTrigInjecConv_T4_TRGO: Timer4 TRGO event selected (for ADC1 and ADC2)
+  *     @arg ADC_ExternalTrigInjecConv_Ext_IT15_TIM8_CC4: External interrupt line 15 or Timer8
+  *                                                       capture compare4 event selected (for ADC1 and ADC2)                       
+  *     @arg ADC_ExternalTrigInjecConv_T4_CC3: Timer4 capture compare3 selected (for ADC3 only)
+  *     @arg ADC_ExternalTrigInjecConv_T8_CC2: Timer8 capture compare2 selected (for ADC3 only)                         
+  *     @arg ADC_ExternalTrigInjecConv_T8_CC4: Timer8 capture compare4 selected (for ADC3 only)
+  *     @arg ADC_ExternalTrigInjecConv_T5_TRGO: Timer5 TRGO event selected (for ADC3 only)                         
+  *     @arg ADC_ExternalTrigInjecConv_T5_CC4: Timer5 capture compare4 selected (for ADC3 only)                        
+  *     @arg ADC_ExternalTrigInjecConv_None: Injected conversion started by software and not
+  *                                          by external trigger (for ADC1, ADC2 and ADC3)
+  * @retval None
+  */
+void ADC_ExternalTrigInjectedConvConfig(ADC_TypeDef* ADCx, uint32_t ADC_ExternalTrigInjecConv)
+{
+  uint32_t tmpreg = 0;
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_PERIPH(ADCx));
+  assert_param(IS_ADC_EXT_INJEC_TRIG(ADC_ExternalTrigInjecConv));
+  /* Get the old register value */
+  tmpreg = ADCx->CR2;
+  /* Clear the old external event selection for injected group */
+  tmpreg &= CR2_JEXTSEL_Reset;
+  /* Set the external event selection for injected group */
+  tmpreg |= ADC_ExternalTrigInjecConv;
+  /* Store the new register value */
+  ADCx->CR2 = tmpreg;
+}
+
+/**
+  * @brief  Enables or disables the ADCx injected channels conversion through
+  *         external trigger
+  * @param  ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
+  * @param  NewState: new state of the selected ADC external trigger start of
+  *         injected conversion.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void ADC_ExternalTrigInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_PERIPH(ADCx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  if (NewState != DISABLE)
+  {
+    /* Enable the selected ADC external event selection for injected group */
+    ADCx->CR2 |= CR2_JEXTTRIG_Set;
+  }
+  else
+  {
+    /* Disable the selected ADC external event selection for injected group */
+    ADCx->CR2 &= CR2_JEXTTRIG_Reset;
+  }
+}
+
+/**
+  * @brief  Enables or disables the selected ADC start of the injected 
+  *         channels conversion.
+  * @param  ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
+  * @param  NewState: new state of the selected ADC software start injected conversion.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void ADC_SoftwareStartInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_PERIPH(ADCx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  if (NewState != DISABLE)
+  {
+    /* Enable the selected ADC conversion for injected group on external event and start the selected
+       ADC injected conversion */
+    ADCx->CR2 |= CR2_JEXTTRIG_JSWSTART_Set;
+  }
+  else
+  {
+    /* Disable the selected ADC conversion on external event for injected group and stop the selected
+       ADC injected conversion */
+    ADCx->CR2 &= CR2_JEXTTRIG_JSWSTART_Reset;
+  }
+}
+
+/**
+  * @brief  Gets the selected ADC Software start injected conversion Status.
+  * @param  ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
+  * @retval The new state of ADC software start injected conversion (SET or RESET).
+  */
+FlagStatus ADC_GetSoftwareStartInjectedConvCmdStatus(ADC_TypeDef* ADCx)
+{
+  FlagStatus bitstatus = RESET;
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_PERIPH(ADCx));
+  /* Check the status of JSWSTART bit */
+  if ((ADCx->CR2 & CR2_JSWSTART_Set) != (uint32_t)RESET)
+  {
+    /* JSWSTART bit is set */
+    bitstatus = SET;
+  }
+  else
+  {
+    /* JSWSTART bit is reset */
+    bitstatus = RESET;
+  }
+  /* Return the JSWSTART bit status */
+  return  bitstatus;
+}
+
+/**
+  * @brief  Configures for the selected ADC injected channel its corresponding
+  *         rank in the sequencer and its sample time.
+  * @param  ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
+  * @param  ADC_Channel: the ADC channel to configure. 
+  *   This parameter can be one of the following values:
+  *     @arg ADC_Channel_0: ADC Channel0 selected
+  *     @arg ADC_Channel_1: ADC Channel1 selected
+  *     @arg ADC_Channel_2: ADC Channel2 selected
+  *     @arg ADC_Channel_3: ADC Channel3 selected
+  *     @arg ADC_Channel_4: ADC Channel4 selected
+  *     @arg ADC_Channel_5: ADC Channel5 selected
+  *     @arg ADC_Channel_6: ADC Channel6 selected
+  *     @arg ADC_Channel_7: ADC Channel7 selected
+  *     @arg ADC_Channel_8: ADC Channel8 selected
+  *     @arg ADC_Channel_9: ADC Channel9 selected
+  *     @arg ADC_Channel_10: ADC Channel10 selected
+  *     @arg ADC_Channel_11: ADC Channel11 selected
+  *     @arg ADC_Channel_12: ADC Channel12 selected
+  *     @arg ADC_Channel_13: ADC Channel13 selected
+  *     @arg ADC_Channel_14: ADC Channel14 selected
+  *     @arg ADC_Channel_15: ADC Channel15 selected
+  *     @arg ADC_Channel_16: ADC Channel16 selected
+  *     @arg ADC_Channel_17: ADC Channel17 selected
+  * @param  Rank: The rank in the injected group sequencer. This parameter must be between 1 and 4.
+  * @param  ADC_SampleTime: The sample time value to be set for the selected channel. 
+  *   This parameter can be one of the following values:
+  *     @arg ADC_SampleTime_1Cycles5: Sample time equal to 1.5 cycles
+  *     @arg ADC_SampleTime_7Cycles5: Sample time equal to 7.5 cycles
+  *     @arg ADC_SampleTime_13Cycles5: Sample time equal to 13.5 cycles
+  *     @arg ADC_SampleTime_28Cycles5: Sample time equal to 28.5 cycles	
+  *     @arg ADC_SampleTime_41Cycles5: Sample time equal to 41.5 cycles	
+  *     @arg ADC_SampleTime_55Cycles5: Sample time equal to 55.5 cycles	
+  *     @arg ADC_SampleTime_71Cycles5: Sample time equal to 71.5 cycles	
+  *     @arg ADC_SampleTime_239Cycles5: Sample time equal to 239.5 cycles	
+  * @retval None
+  */
+void ADC_InjectedChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime)
+{
+  uint32_t tmpreg1 = 0, tmpreg2 = 0, tmpreg3 = 0;
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_PERIPH(ADCx));
+  assert_param(IS_ADC_CHANNEL(ADC_Channel));
+  assert_param(IS_ADC_INJECTED_RANK(Rank));
+  assert_param(IS_ADC_SAMPLE_TIME(ADC_SampleTime));
+  /* if ADC_Channel_10 ... ADC_Channel_17 is selected */
+  if (ADC_Channel > ADC_Channel_9)
+  {
+    /* Get the old register value */
+    tmpreg1 = ADCx->SMPR1;
+    /* Calculate the mask to clear */
+    tmpreg2 = SMPR1_SMP_Set << (3*(ADC_Channel - 10));
+    /* Clear the old channel sample time */
+    tmpreg1 &= ~tmpreg2;
+    /* Calculate the mask to set */
+    tmpreg2 = (uint32_t)ADC_SampleTime << (3*(ADC_Channel - 10));
+    /* Set the new channel sample time */
+    tmpreg1 |= tmpreg2;
+    /* Store the new register value */
+    ADCx->SMPR1 = tmpreg1;
+  }
+  else /* ADC_Channel include in ADC_Channel_[0..9] */
+  {
+    /* Get the old register value */
+    tmpreg1 = ADCx->SMPR2;
+    /* Calculate the mask to clear */
+    tmpreg2 = SMPR2_SMP_Set << (3 * ADC_Channel);
+    /* Clear the old channel sample time */
+    tmpreg1 &= ~tmpreg2;
+    /* Calculate the mask to set */
+    tmpreg2 = (uint32_t)ADC_SampleTime << (3 * ADC_Channel);
+    /* Set the new channel sample time */
+    tmpreg1 |= tmpreg2;
+    /* Store the new register value */
+    ADCx->SMPR2 = tmpreg1;
+  }
+  /* Rank configuration */
+  /* Get the old register value */
+  tmpreg1 = ADCx->JSQR;
+  /* Get JL value: Number = JL+1 */
+  tmpreg3 =  (tmpreg1 & JSQR_JL_Set)>> 20;
+  /* Calculate the mask to clear: ((Rank-1)+(4-JL-1)) */
+  tmpreg2 = JSQR_JSQ_Set << (5 * (uint8_t)((Rank + 3) - (tmpreg3 + 1)));
+  /* Clear the old JSQx bits for the selected rank */
+  tmpreg1 &= ~tmpreg2;
+  /* Calculate the mask to set: ((Rank-1)+(4-JL-1)) */
+  tmpreg2 = (uint32_t)ADC_Channel << (5 * (uint8_t)((Rank + 3) - (tmpreg3 + 1)));
+  /* Set the JSQx bits for the selected rank */
+  tmpreg1 |= tmpreg2;
+  /* Store the new register value */
+  ADCx->JSQR = tmpreg1;
+}
+
+/**
+  * @brief  Configures the sequencer length for injected channels
+  * @param  ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
+  * @param  Length: The sequencer length. 
+  *   This parameter must be a number between 1 to 4.
+  * @retval None
+  */
+void ADC_InjectedSequencerLengthConfig(ADC_TypeDef* ADCx, uint8_t Length)
+{
+  uint32_t tmpreg1 = 0;
+  uint32_t tmpreg2 = 0;
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_PERIPH(ADCx));
+  assert_param(IS_ADC_INJECTED_LENGTH(Length));
+  
+  /* Get the old register value */
+  tmpreg1 = ADCx->JSQR;
+  /* Clear the old injected sequnence lenght JL bits */
+  tmpreg1 &= JSQR_JL_Reset;
+  /* Set the injected sequnence lenght JL bits */
+  tmpreg2 = Length - 1; 
+  tmpreg1 |= tmpreg2 << 20;
+  /* Store the new register value */
+  ADCx->JSQR = tmpreg1;
+}
+
+/**
+  * @brief  Set the injected channels conversion value offset
+  * @param  ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
+  * @param  ADC_InjectedChannel: the ADC injected channel to set its offset. 
+  *   This parameter can be one of the following values:
+  *     @arg ADC_InjectedChannel_1: Injected Channel1 selected
+  *     @arg ADC_InjectedChannel_2: Injected Channel2 selected
+  *     @arg ADC_InjectedChannel_3: Injected Channel3 selected
+  *     @arg ADC_InjectedChannel_4: Injected Channel4 selected
+  * @param  Offset: the offset value for the selected ADC injected channel
+  *   This parameter must be a 12bit value.
+  * @retval None
+  */
+void ADC_SetInjectedOffset(ADC_TypeDef* ADCx, uint8_t ADC_InjectedChannel, uint16_t Offset)
+{
+  __IO uint32_t tmp = 0;
+  
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_PERIPH(ADCx));
+  assert_param(IS_ADC_INJECTED_CHANNEL(ADC_InjectedChannel));
+  assert_param(IS_ADC_OFFSET(Offset));  
+  
+  tmp = (uint32_t)ADCx;
+  tmp += ADC_InjectedChannel;
+  
+  /* Set the selected injected channel data offset */
+  *(__IO uint32_t *) tmp = (uint32_t)Offset;
+}
+
+/**
+  * @brief  Returns the ADC injected channel conversion result
+  * @param  ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
+  * @param  ADC_InjectedChannel: the converted ADC injected channel.
+  *   This parameter can be one of the following values:
+  *     @arg ADC_InjectedChannel_1: Injected Channel1 selected
+  *     @arg ADC_InjectedChannel_2: Injected Channel2 selected
+  *     @arg ADC_InjectedChannel_3: Injected Channel3 selected
+  *     @arg ADC_InjectedChannel_4: Injected Channel4 selected
+  * @retval The Data conversion value.
+  */
+uint16_t ADC_GetInjectedConversionValue(ADC_TypeDef* ADCx, uint8_t ADC_InjectedChannel)
+{
+  __IO uint32_t tmp = 0;
+  
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_PERIPH(ADCx));
+  assert_param(IS_ADC_INJECTED_CHANNEL(ADC_InjectedChannel));
+
+  tmp = (uint32_t)ADCx;
+  tmp += ADC_InjectedChannel + JDR_Offset;
+  
+  /* Returns the selected injected channel conversion data value */
+  return (uint16_t) (*(__IO uint32_t*)  tmp);   
+}
+
+/**
+  * @brief  Enables or disables the analog watchdog on single/all regular
+  *         or injected channels
+  * @param  ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
+  * @param  ADC_AnalogWatchdog: the ADC analog watchdog configuration.
+  *   This parameter can be one of the following values:
+  *     @arg ADC_AnalogWatchdog_SingleRegEnable: Analog watchdog on a single regular channel
+  *     @arg ADC_AnalogWatchdog_SingleInjecEnable: Analog watchdog on a single injected channel
+  *     @arg ADC_AnalogWatchdog_SingleRegOrInjecEnable: Analog watchdog on a single regular or injected channel
+  *     @arg ADC_AnalogWatchdog_AllRegEnable: Analog watchdog on  all regular channel
+  *     @arg ADC_AnalogWatchdog_AllInjecEnable: Analog watchdog on  all injected channel
+  *     @arg ADC_AnalogWatchdog_AllRegAllInjecEnable: Analog watchdog on all regular and injected channels
+  *     @arg ADC_AnalogWatchdog_None: No channel guarded by the analog watchdog
+  * @retval None	  
+  */
+void ADC_AnalogWatchdogCmd(ADC_TypeDef* ADCx, uint32_t ADC_AnalogWatchdog)
+{
+  uint32_t tmpreg = 0;
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_PERIPH(ADCx));
+  assert_param(IS_ADC_ANALOG_WATCHDOG(ADC_AnalogWatchdog));
+  /* Get the old register value */
+  tmpreg = ADCx->CR1;
+  /* Clear AWDEN, AWDENJ and AWDSGL bits */
+  tmpreg &= CR1_AWDMode_Reset;
+  /* Set the analog watchdog enable mode */
+  tmpreg |= ADC_AnalogWatchdog;
+  /* Store the new register value */
+  ADCx->CR1 = tmpreg;
+}
+
+/**
+  * @brief  Configures the high and low thresholds of the analog watchdog.
+  * @param  ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
+  * @param  HighThreshold: the ADC analog watchdog High threshold value.
+  *   This parameter must be a 12bit value.
+  * @param  LowThreshold: the ADC analog watchdog Low threshold value.
+  *   This parameter must be a 12bit value.
+  * @retval None
+  */
+void ADC_AnalogWatchdogThresholdsConfig(ADC_TypeDef* ADCx, uint16_t HighThreshold,
+                                        uint16_t LowThreshold)
+{
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_PERIPH(ADCx));
+  assert_param(IS_ADC_THRESHOLD(HighThreshold));
+  assert_param(IS_ADC_THRESHOLD(LowThreshold));
+  /* Set the ADCx high threshold */
+  ADCx->HTR = HighThreshold;
+  /* Set the ADCx low threshold */
+  ADCx->LTR = LowThreshold;
+}
+
+/**
+  * @brief  Configures the analog watchdog guarded single channel
+  * @param  ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
+  * @param  ADC_Channel: the ADC channel to configure for the analog watchdog. 
+  *   This parameter can be one of the following values:
+  *     @arg ADC_Channel_0: ADC Channel0 selected
+  *     @arg ADC_Channel_1: ADC Channel1 selected
+  *     @arg ADC_Channel_2: ADC Channel2 selected
+  *     @arg ADC_Channel_3: ADC Channel3 selected
+  *     @arg ADC_Channel_4: ADC Channel4 selected
+  *     @arg ADC_Channel_5: ADC Channel5 selected
+  *     @arg ADC_Channel_6: ADC Channel6 selected
+  *     @arg ADC_Channel_7: ADC Channel7 selected
+  *     @arg ADC_Channel_8: ADC Channel8 selected
+  *     @arg ADC_Channel_9: ADC Channel9 selected
+  *     @arg ADC_Channel_10: ADC Channel10 selected
+  *     @arg ADC_Channel_11: ADC Channel11 selected
+  *     @arg ADC_Channel_12: ADC Channel12 selected
+  *     @arg ADC_Channel_13: ADC Channel13 selected
+  *     @arg ADC_Channel_14: ADC Channel14 selected
+  *     @arg ADC_Channel_15: ADC Channel15 selected
+  *     @arg ADC_Channel_16: ADC Channel16 selected
+  *     @arg ADC_Channel_17: ADC Channel17 selected
+  * @retval None
+  */
+void ADC_AnalogWatchdogSingleChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel)
+{
+  uint32_t tmpreg = 0;
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_PERIPH(ADCx));
+  assert_param(IS_ADC_CHANNEL(ADC_Channel));
+  /* Get the old register value */
+  tmpreg = ADCx->CR1;
+  /* Clear the Analog watchdog channel select bits */
+  tmpreg &= CR1_AWDCH_Reset;
+  /* Set the Analog watchdog channel */
+  tmpreg |= ADC_Channel;
+  /* Store the new register value */
+  ADCx->CR1 = tmpreg;
+}
+
+/**
+  * @brief  Enables or disables the temperature sensor and Vrefint channel.
+  * @param  NewState: new state of the temperature sensor.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void ADC_TempSensorVrefintCmd(FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  if (NewState != DISABLE)
+  {
+    /* Enable the temperature sensor and Vrefint channel*/
+    ADC1->CR2 |= CR2_TSVREFE_Set;
+  }
+  else
+  {
+    /* Disable the temperature sensor and Vrefint channel*/
+    ADC1->CR2 &= CR2_TSVREFE_Reset;
+  }
+}
+
+/**
+  * @brief  Checks whether the specified ADC flag is set or not.
+  * @param  ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
+  * @param  ADC_FLAG: specifies the flag to check. 
+  *   This parameter can be one of the following values:
+  *     @arg ADC_FLAG_AWD: Analog watchdog flag
+  *     @arg ADC_FLAG_EOC: End of conversion flag
+  *     @arg ADC_FLAG_JEOC: End of injected group conversion flag
+  *     @arg ADC_FLAG_JSTRT: Start of injected group conversion flag
+  *     @arg ADC_FLAG_STRT: Start of regular group conversion flag
+  * @retval The new state of ADC_FLAG (SET or RESET).
+  */
+FlagStatus ADC_GetFlagStatus(ADC_TypeDef* ADCx, uint8_t ADC_FLAG)
+{
+  FlagStatus bitstatus = RESET;
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_PERIPH(ADCx));
+  assert_param(IS_ADC_GET_FLAG(ADC_FLAG));
+  /* Check the status of the specified ADC flag */
+  if ((ADCx->SR & ADC_FLAG) != (uint8_t)RESET)
+  {
+    /* ADC_FLAG is set */
+    bitstatus = SET;
+  }
+  else
+  {
+    /* ADC_FLAG is reset */
+    bitstatus = RESET;
+  }
+  /* Return the ADC_FLAG status */
+  return  bitstatus;
+}
+
+/**
+  * @brief  Clears the ADCx's pending flags.
+  * @param  ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
+  * @param  ADC_FLAG: specifies the flag to clear. 
+  *   This parameter can be any combination of the following values:
+  *     @arg ADC_FLAG_AWD: Analog watchdog flag
+  *     @arg ADC_FLAG_EOC: End of conversion flag
+  *     @arg ADC_FLAG_JEOC: End of injected group conversion flag
+  *     @arg ADC_FLAG_JSTRT: Start of injected group conversion flag
+  *     @arg ADC_FLAG_STRT: Start of regular group conversion flag
+  * @retval None
+  */
+void ADC_ClearFlag(ADC_TypeDef* ADCx, uint8_t ADC_FLAG)
+{
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_PERIPH(ADCx));
+  assert_param(IS_ADC_CLEAR_FLAG(ADC_FLAG));
+  /* Clear the selected ADC flags */
+  ADCx->SR = ~(uint32_t)ADC_FLAG;
+}
+
+/**
+  * @brief  Checks whether the specified ADC interrupt has occurred or not.
+  * @param  ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
+  * @param  ADC_IT: specifies the ADC interrupt source to check. 
+  *   This parameter can be one of the following values:
+  *     @arg ADC_IT_EOC: End of conversion interrupt mask
+  *     @arg ADC_IT_AWD: Analog watchdog interrupt mask
+  *     @arg ADC_IT_JEOC: End of injected conversion interrupt mask
+  * @retval The new state of ADC_IT (SET or RESET).
+  */
+ITStatus ADC_GetITStatus(ADC_TypeDef* ADCx, uint16_t ADC_IT)
+{
+  ITStatus bitstatus = RESET;
+  uint32_t itmask = 0, enablestatus = 0;
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_PERIPH(ADCx));
+  assert_param(IS_ADC_GET_IT(ADC_IT));
+  /* Get the ADC IT index */
+  itmask = ADC_IT >> 8;
+  /* Get the ADC_IT enable bit status */
+  enablestatus = (ADCx->CR1 & (uint8_t)ADC_IT) ;
+  /* Check the status of the specified ADC interrupt */
+  if (((ADCx->SR & itmask) != (uint32_t)RESET) && enablestatus)
+  {
+    /* ADC_IT is set */
+    bitstatus = SET;
+  }
+  else
+  {
+    /* ADC_IT is reset */
+    bitstatus = RESET;
+  }
+  /* Return the ADC_IT status */
+  return  bitstatus;
+}
+
+/**
+  * @brief  Clears the ADCx's interrupt pending bits.
+  * @param  ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
+  * @param  ADC_IT: specifies the ADC interrupt pending bit to clear.
+  *   This parameter can be any combination of the following values:
+  *     @arg ADC_IT_EOC: End of conversion interrupt mask
+  *     @arg ADC_IT_AWD: Analog watchdog interrupt mask
+  *     @arg ADC_IT_JEOC: End of injected conversion interrupt mask
+  * @retval None
+  */
+void ADC_ClearITPendingBit(ADC_TypeDef* ADCx, uint16_t ADC_IT)
+{
+  uint8_t itmask = 0;
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_PERIPH(ADCx));
+  assert_param(IS_ADC_IT(ADC_IT));
+  /* Get the ADC IT index */
+  itmask = (uint8_t)(ADC_IT >> 8);
+  /* Clear the selected ADC interrupt pending bits */
+  ADCx->SR = ~(uint32_t)itmask;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/STM32_4路称重_Git提交精简工程/src/STM32F10x_FWLib/src/stm32f10x_bkp.c b/STM32_4路称重_Git提交精简工程/src/STM32F10x_FWLib/src/stm32f10x_bkp.c
new file mode 100755
index 0000000..3004b9e
--- /dev/null
+++ b/STM32_4路称重_Git提交精简工程/src/STM32F10x_FWLib/src/stm32f10x_bkp.c
@@ -0,0 +1,308 @@
+/**
+  ******************************************************************************
+  * @file    stm32f10x_bkp.c
+  * @author  MCD Application Team
+  * @version V3.5.0
+  * @date    11-March-2011
+  * @brief   This file provides all the BKP firmware functions.
+  ******************************************************************************
+  * @attention
+  *
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+  *
+  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x_bkp.h"
+#include "stm32f10x_rcc.h"
+
+/** @addtogroup STM32F10x_StdPeriph_Driver
+  * @{
+  */
+
+/** @defgroup BKP 
+  * @brief BKP driver modules
+  * @{
+  */
+
+/** @defgroup BKP_Private_TypesDefinitions
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup BKP_Private_Defines
+  * @{
+  */
+
+/* ------------ BKP registers bit address in the alias region --------------- */
+#define BKP_OFFSET        (BKP_BASE - PERIPH_BASE)
+
+/* --- CR Register ----*/
+
+/* Alias word address of TPAL bit */
+#define CR_OFFSET         (BKP_OFFSET + 0x30)
+#define TPAL_BitNumber    0x01
+#define CR_TPAL_BB        (PERIPH_BB_BASE + (CR_OFFSET * 32) + (TPAL_BitNumber * 4))
+
+/* Alias word address of TPE bit */
+#define TPE_BitNumber     0x00
+#define CR_TPE_BB         (PERIPH_BB_BASE + (CR_OFFSET * 32) + (TPE_BitNumber * 4))
+
+/* --- CSR Register ---*/
+
+/* Alias word address of TPIE bit */
+#define CSR_OFFSET        (BKP_OFFSET + 0x34)
+#define TPIE_BitNumber    0x02
+#define CSR_TPIE_BB       (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (TPIE_BitNumber * 4))
+
+/* Alias word address of TIF bit */
+#define TIF_BitNumber     0x09
+#define CSR_TIF_BB        (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (TIF_BitNumber * 4))
+
+/* Alias word address of TEF bit */
+#define TEF_BitNumber     0x08
+#define CSR_TEF_BB        (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (TEF_BitNumber * 4))
+
+/* ---------------------- BKP registers bit mask ------------------------ */
+
+/* RTCCR register bit mask */
+#define RTCCR_CAL_MASK    ((uint16_t)0xFF80)
+#define RTCCR_MASK        ((uint16_t)0xFC7F)
+
+/**
+  * @}
+  */ 
+
+
+/** @defgroup BKP_Private_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup BKP_Private_Variables
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup BKP_Private_FunctionPrototypes
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup BKP_Private_Functions
+  * @{
+  */
+
+/**
+  * @brief  Deinitializes the BKP peripheral registers to their default reset values.
+  * @param  None
+  * @retval None
+  */
+void BKP_DeInit(void)
+{
+  RCC_BackupResetCmd(ENABLE);
+  RCC_BackupResetCmd(DISABLE);
+}
+
+/**
+  * @brief  Configures the Tamper Pin active level.
+  * @param  BKP_TamperPinLevel: specifies the Tamper Pin active level.
+  *   This parameter can be one of the following values:
+  *     @arg BKP_TamperPinLevel_High: Tamper pin active on high level
+  *     @arg BKP_TamperPinLevel_Low: Tamper pin active on low level
+  * @retval None
+  */
+void BKP_TamperPinLevelConfig(uint16_t BKP_TamperPinLevel)
+{
+  /* Check the parameters */
+  assert_param(IS_BKP_TAMPER_PIN_LEVEL(BKP_TamperPinLevel));
+  *(__IO uint32_t *) CR_TPAL_BB = BKP_TamperPinLevel;
+}
+
+/**
+  * @brief  Enables or disables the Tamper Pin activation.
+  * @param  NewState: new state of the Tamper Pin activation.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void BKP_TamperPinCmd(FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  *(__IO uint32_t *) CR_TPE_BB = (uint32_t)NewState;
+}
+
+/**
+  * @brief  Enables or disables the Tamper Pin Interrupt.
+  * @param  NewState: new state of the Tamper Pin Interrupt.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void BKP_ITConfig(FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  *(__IO uint32_t *) CSR_TPIE_BB = (uint32_t)NewState;
+}
+
+/**
+  * @brief  Select the RTC output source to output on the Tamper pin.
+  * @param  BKP_RTCOutputSource: specifies the RTC output source.
+  *   This parameter can be one of the following values:
+  *     @arg BKP_RTCOutputSource_None: no RTC output on the Tamper pin.
+  *     @arg BKP_RTCOutputSource_CalibClock: output the RTC clock with frequency
+  *                                          divided by 64 on the Tamper pin.
+  *     @arg BKP_RTCOutputSource_Alarm: output the RTC Alarm pulse signal on
+  *                                     the Tamper pin.
+  *     @arg BKP_RTCOutputSource_Second: output the RTC Second pulse signal on
+  *                                      the Tamper pin.  
+  * @retval None
+  */
+void BKP_RTCOutputConfig(uint16_t BKP_RTCOutputSource)
+{
+  uint16_t tmpreg = 0;
+  /* Check the parameters */
+  assert_param(IS_BKP_RTC_OUTPUT_SOURCE(BKP_RTCOutputSource));
+  tmpreg = BKP->RTCCR;
+  /* Clear CCO, ASOE and ASOS bits */
+  tmpreg &= RTCCR_MASK;
+  
+  /* Set CCO, ASOE and ASOS bits according to BKP_RTCOutputSource value */
+  tmpreg |= BKP_RTCOutputSource;
+  /* Store the new value */
+  BKP->RTCCR = tmpreg;
+}
+
+/**
+  * @brief  Sets RTC Clock Calibration value.
+  * @param  CalibrationValue: specifies the RTC Clock Calibration value.
+  *   This parameter must be a number between 0 and 0x7F.
+  * @retval None
+  */
+void BKP_SetRTCCalibrationValue(uint8_t CalibrationValue)
+{
+  uint16_t tmpreg = 0;
+  /* Check the parameters */
+  assert_param(IS_BKP_CALIBRATION_VALUE(CalibrationValue));
+  tmpreg = BKP->RTCCR;
+  /* Clear CAL[6:0] bits */
+  tmpreg &= RTCCR_CAL_MASK;
+  /* Set CAL[6:0] bits according to CalibrationValue value */
+  tmpreg |= CalibrationValue;
+  /* Store the new value */
+  BKP->RTCCR = tmpreg;
+}
+
+/**
+  * @brief  Writes user data to the specified Data Backup Register.
+  * @param  BKP_DR: specifies the Data Backup Register.
+  *   This parameter can be BKP_DRx where x:[1, 42]
+  * @param  Data: data to write
+  * @retval None
+  */
+void BKP_WriteBackupRegister(uint16_t BKP_DR, uint16_t Data)
+{
+  __IO uint32_t tmp = 0;
+
+  /* Check the parameters */
+  assert_param(IS_BKP_DR(BKP_DR));
+
+  tmp = (uint32_t)BKP_BASE; 
+  tmp += BKP_DR;
+
+  *(__IO uint32_t *) tmp = Data;
+}
+
+/**
+  * @brief  Reads data from the specified Data Backup Register.
+  * @param  BKP_DR: specifies the Data Backup Register.
+  *   This parameter can be BKP_DRx where x:[1, 42]
+  * @retval The content of the specified Data Backup Register
+  */
+uint16_t BKP_ReadBackupRegister(uint16_t BKP_DR)
+{
+  __IO uint32_t tmp = 0;
+
+  /* Check the parameters */
+  assert_param(IS_BKP_DR(BKP_DR));
+
+  tmp = (uint32_t)BKP_BASE; 
+  tmp += BKP_DR;
+
+  return (*(__IO uint16_t *) tmp);
+}
+
+/**
+  * @brief  Checks whether the Tamper Pin Event flag is set or not.
+  * @param  None
+  * @retval The new state of the Tamper Pin Event flag (SET or RESET).
+  */
+FlagStatus BKP_GetFlagStatus(void)
+{
+  return (FlagStatus)(*(__IO uint32_t *) CSR_TEF_BB);
+}
+
+/**
+  * @brief  Clears Tamper Pin Event pending flag.
+  * @param  None
+  * @retval None
+  */
+void BKP_ClearFlag(void)
+{
+  /* Set CTE bit to clear Tamper Pin Event flag */
+  BKP->CSR |= BKP_CSR_CTE;
+}
+
+/**
+  * @brief  Checks whether the Tamper Pin Interrupt has occurred or not.
+  * @param  None
+  * @retval The new state of the Tamper Pin Interrupt (SET or RESET).
+  */
+ITStatus BKP_GetITStatus(void)
+{
+  return (ITStatus)(*(__IO uint32_t *) CSR_TIF_BB);
+}
+
+/**
+  * @brief  Clears Tamper Pin Interrupt pending bit.
+  * @param  None
+  * @retval None
+  */
+void BKP_ClearITPendingBit(void)
+{
+  /* Set CTI bit to clear Tamper Pin Interrupt pending bit */
+  BKP->CSR |= BKP_CSR_CTI;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/STM32_4路称重_Git提交精简工程/src/STM32F10x_FWLib/src/stm32f10x_can.c b/STM32_4路称重_Git提交精简工程/src/STM32F10x_FWLib/src/stm32f10x_can.c
new file mode 100755
index 0000000..607d692
--- /dev/null
+++ b/STM32_4路称重_Git提交精简工程/src/STM32F10x_FWLib/src/stm32f10x_can.c
@@ -0,0 +1,1415 @@
+/**
+  ******************************************************************************
+  * @file    stm32f10x_can.c
+  * @author  MCD Application Team
+  * @version V3.5.0
+  * @date    11-March-2011
+  * @brief   This file provides all the CAN firmware functions.
+  ******************************************************************************
+  * @attention
+  *
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+  *
+  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x_can.h"
+#include "stm32f10x_rcc.h"
+
+/** @addtogroup STM32F10x_StdPeriph_Driver
+  * @{
+  */
+
+/** @defgroup CAN 
+  * @brief CAN driver modules
+  * @{
+  */ 
+
+/** @defgroup CAN_Private_TypesDefinitions
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup CAN_Private_Defines
+  * @{
+  */
+
+/* CAN Master Control Register bits */
+
+#define MCR_DBF      ((uint32_t)0x00010000) /* software master reset */
+
+/* CAN Mailbox Transmit Request */
+#define TMIDxR_TXRQ  ((uint32_t)0x00000001) /* Transmit mailbox request */
+
+/* CAN Filter Master Register bits */
+#define FMR_FINIT    ((uint32_t)0x00000001) /* Filter init mode */
+
+/* Time out for INAK bit */
+#define INAK_TIMEOUT        ((uint32_t)0x0000FFFF)
+/* Time out for SLAK bit */
+#define SLAK_TIMEOUT        ((uint32_t)0x0000FFFF)
+
+
+
+/* Flags in TSR register */
+#define CAN_FLAGS_TSR              ((uint32_t)0x08000000) 
+/* Flags in RF1R register */
+#define CAN_FLAGS_RF1R             ((uint32_t)0x04000000) 
+/* Flags in RF0R register */
+#define CAN_FLAGS_RF0R             ((uint32_t)0x02000000) 
+/* Flags in MSR register */
+#define CAN_FLAGS_MSR              ((uint32_t)0x01000000) 
+/* Flags in ESR register */
+#define CAN_FLAGS_ESR              ((uint32_t)0x00F00000) 
+
+/* Mailboxes definition */
+#define CAN_TXMAILBOX_0                   ((uint8_t)0x00)
+#define CAN_TXMAILBOX_1                   ((uint8_t)0x01)
+#define CAN_TXMAILBOX_2                   ((uint8_t)0x02) 
+
+
+
+#define CAN_MODE_MASK              ((uint32_t) 0x00000003)
+/**
+  * @}
+  */
+
+/** @defgroup CAN_Private_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup CAN_Private_Variables
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup CAN_Private_FunctionPrototypes
+  * @{
+  */
+
+static ITStatus CheckITStatus(uint32_t CAN_Reg, uint32_t It_Bit);
+
+/**
+  * @}
+  */
+
+/** @defgroup CAN_Private_Functions
+  * @{
+  */
+
+/**
+  * @brief  Deinitializes the CAN peripheral registers to their default reset values.
+  * @param  CANx: where x can be 1 or 2 to select the CAN peripheral.
+  * @retval None.
+  */
+void CAN_DeInit(CAN_TypeDef* CANx)
+{
+  /* Check the parameters */
+  assert_param(IS_CAN_ALL_PERIPH(CANx));
+ 
+  if (CANx == CAN1)
+  {
+    /* Enable CAN1 reset state */
+    RCC_APB1PeriphResetCmd(RCC_APB1Periph_CAN1, ENABLE);
+    /* Release CAN1 from reset state */
+    RCC_APB1PeriphResetCmd(RCC_APB1Periph_CAN1, DISABLE);
+  }
+  else
+  {  
+    /* Enable CAN2 reset state */
+    RCC_APB1PeriphResetCmd(RCC_APB1Periph_CAN2, ENABLE);
+    /* Release CAN2 from reset state */
+    RCC_APB1PeriphResetCmd(RCC_APB1Periph_CAN2, DISABLE);
+  }
+}
+
+/**
+  * @brief  Initializes the CAN peripheral according to the specified
+  *         parameters in the CAN_InitStruct.
+  * @param  CANx:           where x can be 1 or 2 to to select the CAN 
+  *                         peripheral.
+  * @param  CAN_InitStruct: pointer to a CAN_InitTypeDef structure that
+  *                         contains the configuration information for the 
+  *                         CAN peripheral.
+  * @retval Constant indicates initialization succeed which will be 
+  *         CAN_InitStatus_Failed or CAN_InitStatus_Success.
+  */
+uint8_t CAN_Init(CAN_TypeDef* CANx, CAN_InitTypeDef* CAN_InitStruct)
+{
+  uint8_t InitStatus = CAN_InitStatus_Failed;
+  uint32_t wait_ack = 0x00000000;
+  /* Check the parameters */
+  assert_param(IS_CAN_ALL_PERIPH(CANx));
+  assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_TTCM));
+  assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_ABOM));
+  assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_AWUM));
+  assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_NART));
+  assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_RFLM));
+  assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_TXFP));
+  assert_param(IS_CAN_MODE(CAN_InitStruct->CAN_Mode));
+  assert_param(IS_CAN_SJW(CAN_InitStruct->CAN_SJW));
+  assert_param(IS_CAN_BS1(CAN_InitStruct->CAN_BS1));
+  assert_param(IS_CAN_BS2(CAN_InitStruct->CAN_BS2));
+  assert_param(IS_CAN_PRESCALER(CAN_InitStruct->CAN_Prescaler));
+
+  /* Exit from sleep mode */
+  CANx->MCR &= (~(uint32_t)CAN_MCR_SLEEP);
+
+  /* Request initialisation */
+  CANx->MCR |= CAN_MCR_INRQ ;
+
+  /* Wait the acknowledge */
+  while (((CANx->MSR & CAN_MSR_INAK) != CAN_MSR_INAK) && (wait_ack != INAK_TIMEOUT))
+  {
+    wait_ack++;
+  }
+
+  /* Check acknowledge */
+  if ((CANx->MSR & CAN_MSR_INAK) != CAN_MSR_INAK)
+  {
+    InitStatus = CAN_InitStatus_Failed;
+  }
+  else 
+  {
+    /* Set the time triggered communication mode */
+    if (CAN_InitStruct->CAN_TTCM == ENABLE)
+    {
+      CANx->MCR |= CAN_MCR_TTCM;
+    }
+    else
+    {
+      CANx->MCR &= ~(uint32_t)CAN_MCR_TTCM;
+    }
+
+    /* Set the automatic bus-off management */
+    if (CAN_InitStruct->CAN_ABOM == ENABLE)
+    {
+      CANx->MCR |= CAN_MCR_ABOM;
+    }
+    else
+    {
+      CANx->MCR &= ~(uint32_t)CAN_MCR_ABOM;
+    }
+
+    /* Set the automatic wake-up mode */
+    if (CAN_InitStruct->CAN_AWUM == ENABLE)
+    {
+      CANx->MCR |= CAN_MCR_AWUM;
+    }
+    else
+    {
+      CANx->MCR &= ~(uint32_t)CAN_MCR_AWUM;
+    }
+
+    /* Set the no automatic retransmission */
+    if (CAN_InitStruct->CAN_NART == ENABLE)
+    {
+      CANx->MCR |= CAN_MCR_NART;
+    }
+    else
+    {
+      CANx->MCR &= ~(uint32_t)CAN_MCR_NART;
+    }
+
+    /* Set the receive FIFO locked mode */
+    if (CAN_InitStruct->CAN_RFLM == ENABLE)
+    {
+      CANx->MCR |= CAN_MCR_RFLM;
+    }
+    else
+    {
+      CANx->MCR &= ~(uint32_t)CAN_MCR_RFLM;
+    }
+
+    /* Set the transmit FIFO priority */
+    if (CAN_InitStruct->CAN_TXFP == ENABLE)
+    {
+      CANx->MCR |= CAN_MCR_TXFP;
+    }
+    else
+    {
+      CANx->MCR &= ~(uint32_t)CAN_MCR_TXFP;
+    }
+
+    /* Set the bit timing register */
+    CANx->BTR = (uint32_t)((uint32_t)CAN_InitStruct->CAN_Mode << 30) | \
+                ((uint32_t)CAN_InitStruct->CAN_SJW << 24) | \
+                ((uint32_t)CAN_InitStruct->CAN_BS1 << 16) | \
+                ((uint32_t)CAN_InitStruct->CAN_BS2 << 20) | \
+               ((uint32_t)CAN_InitStruct->CAN_Prescaler - 1);
+
+    /* Request leave initialisation */
+    CANx->MCR &= ~(uint32_t)CAN_MCR_INRQ;
+
+   /* Wait the acknowledge */
+   wait_ack = 0;
+
+   while (((CANx->MSR & CAN_MSR_INAK) == CAN_MSR_INAK) && (wait_ack != INAK_TIMEOUT))
+   {
+     wait_ack++;
+   }
+
+    /* ...and check acknowledged */
+    if ((CANx->MSR & CAN_MSR_INAK) == CAN_MSR_INAK)
+    {
+      InitStatus = CAN_InitStatus_Failed;
+    }
+    else
+    {
+      InitStatus = CAN_InitStatus_Success ;
+    }
+  }
+
+  /* At this step, return the status of initialization */
+  return InitStatus;
+}
+
+/**
+  * @brief  Initializes the CAN peripheral according to the specified
+  *         parameters in the CAN_FilterInitStruct.
+  * @param  CAN_FilterInitStruct: pointer to a CAN_FilterInitTypeDef
+  *                               structure that contains the configuration 
+  *                               information.
+  * @retval None.
+  */
+void CAN_FilterInit(CAN_FilterInitTypeDef* CAN_FilterInitStruct)
+{
+  uint32_t filter_number_bit_pos = 0;
+  /* Check the parameters */
+  assert_param(IS_CAN_FILTER_NUMBER(CAN_FilterInitStruct->CAN_FilterNumber));
+  assert_param(IS_CAN_FILTER_MODE(CAN_FilterInitStruct->CAN_FilterMode));
+  assert_param(IS_CAN_FILTER_SCALE(CAN_FilterInitStruct->CAN_FilterScale));
+  assert_param(IS_CAN_FILTER_FIFO(CAN_FilterInitStruct->CAN_FilterFIFOAssignment));
+  assert_param(IS_FUNCTIONAL_STATE(CAN_FilterInitStruct->CAN_FilterActivation));
+
+  filter_number_bit_pos = ((uint32_t)1) << CAN_FilterInitStruct->CAN_FilterNumber;
+
+  /* Initialisation mode for the filter */
+  CAN1->FMR |= FMR_FINIT;
+
+  /* Filter Deactivation */
+  CAN1->FA1R &= ~(uint32_t)filter_number_bit_pos;
+
+  /* Filter Scale */
+  if (CAN_FilterInitStruct->CAN_FilterScale == CAN_FilterScale_16bit)
+  {
+    /* 16-bit scale for the filter */
+    CAN1->FS1R &= ~(uint32_t)filter_number_bit_pos;
+
+    /* First 16-bit identifier and First 16-bit mask */
+    /* Or First 16-bit identifier and Second 16-bit identifier */
+    CAN1->sFilterRegister[CAN_FilterInitStruct->CAN_FilterNumber].FR1 = 
+    ((0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterMaskIdLow) << 16) |
+        (0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterIdLow);
+
+    /* Second 16-bit identifier and Second 16-bit mask */
+    /* Or Third 16-bit identifier and Fourth 16-bit identifier */
+    CAN1->sFilterRegister[CAN_FilterInitStruct->CAN_FilterNumber].FR2 = 
+    ((0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterMaskIdHigh) << 16) |
+        (0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterIdHigh);
+  }
+
+  if (CAN_FilterInitStruct->CAN_FilterScale == CAN_FilterScale_32bit)
+  {
+    /* 32-bit scale for the filter */
+    CAN1->FS1R |= filter_number_bit_pos;
+    /* 32-bit identifier or First 32-bit identifier */
+    CAN1->sFilterRegister[CAN_FilterInitStruct->CAN_FilterNumber].FR1 = 
+    ((0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterIdHigh) << 16) |
+        (0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterIdLow);
+    /* 32-bit mask or Second 32-bit identifier */
+    CAN1->sFilterRegister[CAN_FilterInitStruct->CAN_FilterNumber].FR2 = 
+    ((0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterMaskIdHigh) << 16) |
+        (0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterMaskIdLow);
+  }
+
+  /* Filter Mode */
+  if (CAN_FilterInitStruct->CAN_FilterMode == CAN_FilterMode_IdMask)
+  {
+    /*Id/Mask mode for the filter*/
+    CAN1->FM1R &= ~(uint32_t)filter_number_bit_pos;
+  }
+  else /* CAN_FilterInitStruct->CAN_FilterMode == CAN_FilterMode_IdList */
+  {
+    /*Identifier list mode for the filter*/
+    CAN1->FM1R |= (uint32_t)filter_number_bit_pos;
+  }
+
+  /* Filter FIFO assignment */
+  if (CAN_FilterInitStruct->CAN_FilterFIFOAssignment == CAN_Filter_FIFO0)
+  {
+    /* FIFO 0 assignation for the filter */
+    CAN1->FFA1R &= ~(uint32_t)filter_number_bit_pos;
+  }
+
+  if (CAN_FilterInitStruct->CAN_FilterFIFOAssignment == CAN_Filter_FIFO1)
+  {
+    /* FIFO 1 assignation for the filter */
+    CAN1->FFA1R |= (uint32_t)filter_number_bit_pos;
+  }
+  
+  /* Filter activation */
+  if (CAN_FilterInitStruct->CAN_FilterActivation == ENABLE)
+  {
+    CAN1->FA1R |= filter_number_bit_pos;
+  }
+
+  /* Leave the initialisation mode for the filter */
+  CAN1->FMR &= ~FMR_FINIT;
+}
+
+/**
+  * @brief  Fills each CAN_InitStruct member with its default value.
+  * @param  CAN_InitStruct: pointer to a CAN_InitTypeDef structure which
+  *                         will be initialized.
+  * @retval None.
+  */
+void CAN_StructInit(CAN_InitTypeDef* CAN_InitStruct)
+{
+  /* Reset CAN init structure parameters values */
+  
+  /* Initialize the time triggered communication mode */
+  CAN_InitStruct->CAN_TTCM = DISABLE;
+  
+  /* Initialize the automatic bus-off management */
+  CAN_InitStruct->CAN_ABOM = DISABLE;
+  
+  /* Initialize the automatic wake-up mode */
+  CAN_InitStruct->CAN_AWUM = DISABLE;
+  
+  /* Initialize the no automatic retransmission */
+  CAN_InitStruct->CAN_NART = DISABLE;
+  
+  /* Initialize the receive FIFO locked mode */
+  CAN_InitStruct->CAN_RFLM = DISABLE;
+  
+  /* Initialize the transmit FIFO priority */
+  CAN_InitStruct->CAN_TXFP = DISABLE;
+  
+  /* Initialize the CAN_Mode member */
+  CAN_InitStruct->CAN_Mode = CAN_Mode_Normal;
+  
+  /* Initialize the CAN_SJW member */
+  CAN_InitStruct->CAN_SJW = CAN_SJW_1tq;
+  
+  /* Initialize the CAN_BS1 member */
+  CAN_InitStruct->CAN_BS1 = CAN_BS1_4tq;
+  
+  /* Initialize the CAN_BS2 member */
+  CAN_InitStruct->CAN_BS2 = CAN_BS2_3tq;
+  
+  /* Initialize the CAN_Prescaler member */
+  CAN_InitStruct->CAN_Prescaler = 1;
+}
+
+/**
+  * @brief  Select the start bank filter for slave CAN.
+  * @note   This function applies only to STM32 Connectivity line devices.
+  * @param  CAN_BankNumber: Select the start slave bank filter from 1..27.
+  * @retval None.
+  */
+void CAN_SlaveStartBank(uint8_t CAN_BankNumber) 
+{
+  /* Check the parameters */
+  assert_param(IS_CAN_BANKNUMBER(CAN_BankNumber));
+  
+  /* Enter Initialisation mode for the filter */
+  CAN1->FMR |= FMR_FINIT;
+  
+  /* Select the start slave bank */
+  CAN1->FMR &= (uint32_t)0xFFFFC0F1 ;
+  CAN1->FMR |= (uint32_t)(CAN_BankNumber)<<8;
+  
+  /* Leave Initialisation mode for the filter */
+  CAN1->FMR &= ~FMR_FINIT;
+}
+
+/**
+  * @brief  Enables or disables the DBG Freeze for CAN.
+  * @param  CANx:     where x can be 1 or 2 to to select the CAN peripheral.
+  * @param  NewState: new state of the CAN peripheral. This parameter can 
+  *                   be: ENABLE or DISABLE.
+  * @retval None.
+  */
+void CAN_DBGFreeze(CAN_TypeDef* CANx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_CAN_ALL_PERIPH(CANx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  
+  if (NewState != DISABLE)
+  {
+    /* Enable Debug Freeze  */
+    CANx->MCR |= MCR_DBF;
+  }
+  else
+  {
+    /* Disable Debug Freeze */
+    CANx->MCR &= ~MCR_DBF;
+  }
+}
+
+
+/**
+  * @brief  Enables or disabes the CAN Time TriggerOperation communication mode.
+  * @param  CANx:      where x can be 1 or 2 to to select the CAN peripheral.
+  * @param  NewState : Mode new state , can be one of @ref FunctionalState.
+  * @note   when enabled, Time stamp (TIME[15:0]) value is sent in the last 
+  *         two data bytes of the 8-byte message: TIME[7:0] in data byte 6 
+  *         and TIME[15:8] in data byte 7 
+  * @note   DLC must be programmed as 8 in order Time Stamp (2 bytes) to be 
+  *         sent over the CAN bus.  
+  * @retval None
+  */
+void CAN_TTComModeCmd(CAN_TypeDef* CANx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_CAN_ALL_PERIPH(CANx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  if (NewState != DISABLE)
+  {
+    /* Enable the TTCM mode */
+    CANx->MCR |= CAN_MCR_TTCM;
+
+    /* Set TGT bits */
+    CANx->sTxMailBox[0].TDTR |= ((uint32_t)CAN_TDT0R_TGT);
+    CANx->sTxMailBox[1].TDTR |= ((uint32_t)CAN_TDT1R_TGT);
+    CANx->sTxMailBox[2].TDTR |= ((uint32_t)CAN_TDT2R_TGT);
+  }
+  else
+  {
+    /* Disable the TTCM mode */
+    CANx->MCR &= (uint32_t)(~(uint32_t)CAN_MCR_TTCM);
+
+    /* Reset TGT bits */
+    CANx->sTxMailBox[0].TDTR &= ((uint32_t)~CAN_TDT0R_TGT);
+    CANx->sTxMailBox[1].TDTR &= ((uint32_t)~CAN_TDT1R_TGT);
+    CANx->sTxMailBox[2].TDTR &= ((uint32_t)~CAN_TDT2R_TGT);
+  }
+}
+/**
+  * @brief  Initiates the transmission of a message.
+  * @param  CANx:      where x can be 1 or 2 to to select the CAN peripheral.
+  * @param  TxMessage: pointer to a structure which contains CAN Id, CAN
+  *                    DLC and CAN data.
+  * @retval The number of the mailbox that is used for transmission
+  *                    or CAN_TxStatus_NoMailBox if there is no empty mailbox.
+  */
+uint8_t CAN_Transmit(CAN_TypeDef* CANx, CanTxMsg* TxMessage)
+{
+  uint8_t transmit_mailbox = 0;
+  /* Check the parameters */
+  assert_param(IS_CAN_ALL_PERIPH(CANx));
+  assert_param(IS_CAN_IDTYPE(TxMessage->IDE));
+  assert_param(IS_CAN_RTR(TxMessage->RTR));
+  assert_param(IS_CAN_DLC(TxMessage->DLC));
+
+  /* Select one empty transmit mailbox */
+  if ((CANx->TSR&CAN_TSR_TME0) == CAN_TSR_TME0)
+  {
+    transmit_mailbox = 0;
+  }
+  else if ((CANx->TSR&CAN_TSR_TME1) == CAN_TSR_TME1)
+  {
+    transmit_mailbox = 1;
+  }
+  else if ((CANx->TSR&CAN_TSR_TME2) == CAN_TSR_TME2)
+  {
+    transmit_mailbox = 2;
+  }
+  else
+  {
+    transmit_mailbox = CAN_TxStatus_NoMailBox;
+  }
+
+  if (transmit_mailbox != CAN_TxStatus_NoMailBox)
+  {
+    /* Set up the Id */
+    CANx->sTxMailBox[transmit_mailbox].TIR &= TMIDxR_TXRQ;
+    if (TxMessage->IDE == CAN_Id_Standard)
+    {
+      assert_param(IS_CAN_STDID(TxMessage->StdId));  
+      CANx->sTxMailBox[transmit_mailbox].TIR |= ((TxMessage->StdId << 21) | \
+                                                  TxMessage->RTR);
+    }
+    else
+    {
+      assert_param(IS_CAN_EXTID(TxMessage->ExtId));
+      CANx->sTxMailBox[transmit_mailbox].TIR |= ((TxMessage->ExtId << 3) | \
+                                                  TxMessage->IDE | \
+                                                  TxMessage->RTR);
+    }
+    
+    /* Set up the DLC */
+    TxMessage->DLC &= (uint8_t)0x0000000F;
+    CANx->sTxMailBox[transmit_mailbox].TDTR &= (uint32_t)0xFFFFFFF0;
+    CANx->sTxMailBox[transmit_mailbox].TDTR |= TxMessage->DLC;
+
+    /* Set up the data field */
+    CANx->sTxMailBox[transmit_mailbox].TDLR = (((uint32_t)TxMessage->Data[3] << 24) | 
+                                             ((uint32_t)TxMessage->Data[2] << 16) |
+                                             ((uint32_t)TxMessage->Data[1] << 8) | 
+                                             ((uint32_t)TxMessage->Data[0]));
+    CANx->sTxMailBox[transmit_mailbox].TDHR = (((uint32_t)TxMessage->Data[7] << 24) | 
+                                             ((uint32_t)TxMessage->Data[6] << 16) |
+                                             ((uint32_t)TxMessage->Data[5] << 8) |
+                                             ((uint32_t)TxMessage->Data[4]));
+    /* Request transmission */
+    CANx->sTxMailBox[transmit_mailbox].TIR |= TMIDxR_TXRQ;
+  }
+  return transmit_mailbox;
+}
+
+/**
+  * @brief  Checks the transmission of a message.
+  * @param  CANx:            where x can be 1 or 2 to to select the 
+  *                          CAN peripheral.
+  * @param  TransmitMailbox: the number of the mailbox that is used for 
+  *                          transmission.
+  * @retval CAN_TxStatus_Ok if the CAN driver transmits the message, CAN_TxStatus_Failed 
+  *         in an other case.
+  */
+uint8_t CAN_TransmitStatus(CAN_TypeDef* CANx, uint8_t TransmitMailbox)
+{
+  uint32_t state = 0;
+
+  /* Check the parameters */
+  assert_param(IS_CAN_ALL_PERIPH(CANx));
+  assert_param(IS_CAN_TRANSMITMAILBOX(TransmitMailbox));
+ 
+  switch (TransmitMailbox)
+  {
+    case (CAN_TXMAILBOX_0): 
+      state =   CANx->TSR &  (CAN_TSR_RQCP0 | CAN_TSR_TXOK0 | CAN_TSR_TME0);
+      break;
+    case (CAN_TXMAILBOX_1): 
+      state =   CANx->TSR &  (CAN_TSR_RQCP1 | CAN_TSR_TXOK1 | CAN_TSR_TME1);
+      break;
+    case (CAN_TXMAILBOX_2): 
+      state =   CANx->TSR &  (CAN_TSR_RQCP2 | CAN_TSR_TXOK2 | CAN_TSR_TME2);
+      break;
+    default:
+      state = CAN_TxStatus_Failed;
+      break;
+  }
+  switch (state)
+  {
+      /* transmit pending  */
+    case (0x0): state = CAN_TxStatus_Pending;
+      break;
+      /* transmit failed  */
+     case (CAN_TSR_RQCP0 | CAN_TSR_TME0): state = CAN_TxStatus_Failed;
+      break;
+     case (CAN_TSR_RQCP1 | CAN_TSR_TME1): state = CAN_TxStatus_Failed;
+      break;
+     case (CAN_TSR_RQCP2 | CAN_TSR_TME2): state = CAN_TxStatus_Failed;
+      break;
+      /* transmit succeeded  */
+    case (CAN_TSR_RQCP0 | CAN_TSR_TXOK0 | CAN_TSR_TME0):state = CAN_TxStatus_Ok;
+      break;
+    case (CAN_TSR_RQCP1 | CAN_TSR_TXOK1 | CAN_TSR_TME1):state = CAN_TxStatus_Ok;
+      break;
+    case (CAN_TSR_RQCP2 | CAN_TSR_TXOK2 | CAN_TSR_TME2):state = CAN_TxStatus_Ok;
+      break;
+    default: state = CAN_TxStatus_Failed;
+      break;
+  }
+  return (uint8_t) state;
+}
+
+/**
+  * @brief  Cancels a transmit request.
+  * @param  CANx:     where x can be 1 or 2 to to select the CAN peripheral. 
+  * @param  Mailbox:  Mailbox number.
+  * @retval None.
+  */
+void CAN_CancelTransmit(CAN_TypeDef* CANx, uint8_t Mailbox)
+{
+  /* Check the parameters */
+  assert_param(IS_CAN_ALL_PERIPH(CANx));
+  assert_param(IS_CAN_TRANSMITMAILBOX(Mailbox));
+  /* abort transmission */
+  switch (Mailbox)
+  {
+    case (CAN_TXMAILBOX_0): CANx->TSR |= CAN_TSR_ABRQ0;
+      break;
+    case (CAN_TXMAILBOX_1): CANx->TSR |= CAN_TSR_ABRQ1;
+      break;
+    case (CAN_TXMAILBOX_2): CANx->TSR |= CAN_TSR_ABRQ2;
+      break;
+    default:
+      break;
+  }
+}
+
+
+/**
+  * @brief  Receives a message.
+  * @param  CANx:       where x can be 1 or 2 to to select the CAN peripheral.
+  * @param  FIFONumber: Receive FIFO number, CAN_FIFO0 or CAN_FIFO1.
+  * @param  RxMessage:  pointer to a structure receive message which contains 
+  *                     CAN Id, CAN DLC, CAN datas and FMI number.
+  * @retval None.
+  */
+void CAN_Receive(CAN_TypeDef* CANx, uint8_t FIFONumber, CanRxMsg* RxMessage)
+{
+  /* Check the parameters */
+  assert_param(IS_CAN_ALL_PERIPH(CANx));
+  assert_param(IS_CAN_FIFO(FIFONumber));
+  /* Get the Id */
+  RxMessage->IDE = (uint8_t)0x04 & CANx->sFIFOMailBox[FIFONumber].RIR;
+  if (RxMessage->IDE == CAN_Id_Standard)
+  {
+    RxMessage->StdId = (uint32_t)0x000007FF & (CANx->sFIFOMailBox[FIFONumber].RIR >> 21);
+  }
+  else
+  {
+    RxMessage->ExtId = (uint32_t)0x1FFFFFFF & (CANx->sFIFOMailBox[FIFONumber].RIR >> 3);
+  }
+  
+  RxMessage->RTR = (uint8_t)0x02 & CANx->sFIFOMailBox[FIFONumber].RIR;
+  /* Get the DLC */
+  RxMessage->DLC = (uint8_t)0x0F & CANx->sFIFOMailBox[FIFONumber].RDTR;
+  /* Get the FMI */
+  RxMessage->FMI = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDTR >> 8);
+  /* Get the data field */
+  RxMessage->Data[0] = (uint8_t)0xFF & CANx->sFIFOMailBox[FIFONumber].RDLR;
+  RxMessage->Data[1] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDLR >> 8);
+  RxMessage->Data[2] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDLR >> 16);
+  RxMessage->Data[3] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDLR >> 24);
+  RxMessage->Data[4] = (uint8_t)0xFF & CANx->sFIFOMailBox[FIFONumber].RDHR;
+  RxMessage->Data[5] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDHR >> 8);
+  RxMessage->Data[6] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDHR >> 16);
+  RxMessage->Data[7] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDHR >> 24);
+  /* Release the FIFO */
+  /* Release FIFO0 */
+  if (FIFONumber == CAN_FIFO0)
+  {
+    CANx->RF0R |= CAN_RF0R_RFOM0;
+  }
+  /* Release FIFO1 */
+  else /* FIFONumber == CAN_FIFO1 */
+  {
+    CANx->RF1R |= CAN_RF1R_RFOM1;
+  }
+}
+
+/**
+  * @brief  Releases the specified FIFO.
+  * @param  CANx:       where x can be 1 or 2 to to select the CAN peripheral. 
+  * @param  FIFONumber: FIFO to release, CAN_FIFO0 or CAN_FIFO1.
+  * @retval None.
+  */
+void CAN_FIFORelease(CAN_TypeDef* CANx, uint8_t FIFONumber)
+{
+  /* Check the parameters */
+  assert_param(IS_CAN_ALL_PERIPH(CANx));
+  assert_param(IS_CAN_FIFO(FIFONumber));
+  /* Release FIFO0 */
+  if (FIFONumber == CAN_FIFO0)
+  {
+    CANx->RF0R |= CAN_RF0R_RFOM0;
+  }
+  /* Release FIFO1 */
+  else /* FIFONumber == CAN_FIFO1 */
+  {
+    CANx->RF1R |= CAN_RF1R_RFOM1;
+  }
+}
+
+/**
+  * @brief  Returns the number of pending messages.
+  * @param  CANx:       where x can be 1 or 2 to to select the CAN peripheral.
+  * @param  FIFONumber: Receive FIFO number, CAN_FIFO0 or CAN_FIFO1.
+  * @retval NbMessage : which is the number of pending message.
+  */
+uint8_t CAN_MessagePending(CAN_TypeDef* CANx, uint8_t FIFONumber)
+{
+  uint8_t message_pending=0;
+  /* Check the parameters */
+  assert_param(IS_CAN_ALL_PERIPH(CANx));
+  assert_param(IS_CAN_FIFO(FIFONumber));
+  if (FIFONumber == CAN_FIFO0)
+  {
+    message_pending = (uint8_t)(CANx->RF0R&(uint32_t)0x03);
+  }
+  else if (FIFONumber == CAN_FIFO1)
+  {
+    message_pending = (uint8_t)(CANx->RF1R&(uint32_t)0x03);
+  }
+  else
+  {
+    message_pending = 0;
+  }
+  return message_pending;
+}
+
+
+/**
+  * @brief   Select the CAN Operation mode.
+  * @param CAN_OperatingMode : CAN Operating Mode. This parameter can be one 
+  *                            of @ref CAN_OperatingMode_TypeDef enumeration.
+  * @retval status of the requested mode which can be 
+  *         - CAN_ModeStatus_Failed    CAN failed entering the specific mode 
+  *         - CAN_ModeStatus_Success   CAN Succeed entering the specific mode 
+
+  */
+uint8_t CAN_OperatingModeRequest(CAN_TypeDef* CANx, uint8_t CAN_OperatingMode)
+{
+  uint8_t status = CAN_ModeStatus_Failed;
+  
+  /* Timeout for INAK or also for SLAK bits*/
+  uint32_t timeout = INAK_TIMEOUT; 
+
+  /* Check the parameters */
+  assert_param(IS_CAN_ALL_PERIPH(CANx));
+  assert_param(IS_CAN_OPERATING_MODE(CAN_OperatingMode));
+
+  if (CAN_OperatingMode == CAN_OperatingMode_Initialization)
+  {
+    /* Request initialisation */
+    CANx->MCR = (uint32_t)((CANx->MCR & (uint32_t)(~(uint32_t)CAN_MCR_SLEEP)) | CAN_MCR_INRQ);
+
+    /* Wait the acknowledge */
+    while (((CANx->MSR & CAN_MODE_MASK) != CAN_MSR_INAK) && (timeout != 0))
+    {
+      timeout--;
+    }
+    if ((CANx->MSR & CAN_MODE_MASK) != CAN_MSR_INAK)
+    {
+      status = CAN_ModeStatus_Failed;
+    }
+    else
+    {
+      status = CAN_ModeStatus_Success;
+    }
+  }
+  else  if (CAN_OperatingMode == CAN_OperatingMode_Normal)
+  {
+    /* Request leave initialisation and sleep mode  and enter Normal mode */
+    CANx->MCR &= (uint32_t)(~(CAN_MCR_SLEEP|CAN_MCR_INRQ));
+
+    /* Wait the acknowledge */
+    while (((CANx->MSR & CAN_MODE_MASK) != 0) && (timeout!=0))
+    {
+      timeout--;
+    }
+    if ((CANx->MSR & CAN_MODE_MASK) != 0)
+    {
+      status = CAN_ModeStatus_Failed;
+    }
+    else
+    {
+      status = CAN_ModeStatus_Success;
+    }
+  }
+  else  if (CAN_OperatingMode == CAN_OperatingMode_Sleep)
+  {
+    /* Request Sleep mode */
+    CANx->MCR = (uint32_t)((CANx->MCR & (uint32_t)(~(uint32_t)CAN_MCR_INRQ)) | CAN_MCR_SLEEP);
+
+    /* Wait the acknowledge */
+    while (((CANx->MSR & CAN_MODE_MASK) != CAN_MSR_SLAK) && (timeout!=0))
+    {
+      timeout--;
+    }
+    if ((CANx->MSR & CAN_MODE_MASK) != CAN_MSR_SLAK)
+    {
+      status = CAN_ModeStatus_Failed;
+    }
+    else
+    {
+      status = CAN_ModeStatus_Success;
+    }
+  }
+  else
+  {
+    status = CAN_ModeStatus_Failed;
+  }
+
+  return  (uint8_t) status;
+}
+
+/**
+  * @brief  Enters the low power mode.
+  * @param  CANx:   where x can be 1 or 2 to to select the CAN peripheral.
+  * @retval status: CAN_Sleep_Ok if sleep entered, CAN_Sleep_Failed in an 
+  *                 other case.
+  */
+uint8_t CAN_Sleep(CAN_TypeDef* CANx)
+{
+  uint8_t sleepstatus = CAN_Sleep_Failed;
+  
+  /* Check the parameters */
+  assert_param(IS_CAN_ALL_PERIPH(CANx));
+    
+  /* Request Sleep mode */
+   CANx->MCR = (((CANx->MCR) & (uint32_t)(~(uint32_t)CAN_MCR_INRQ)) | CAN_MCR_SLEEP);
+   
+  /* Sleep mode status */
+  if ((CANx->MSR & (CAN_MSR_SLAK|CAN_MSR_INAK)) == CAN_MSR_SLAK)
+  {
+    /* Sleep mode not entered */
+    sleepstatus =  CAN_Sleep_Ok;
+  }
+  /* return sleep mode status */
+   return (uint8_t)sleepstatus;
+}
+
+/**
+  * @brief  Wakes the CAN up.
+  * @param  CANx:    where x can be 1 or 2 to to select the CAN peripheral.
+  * @retval status:  CAN_WakeUp_Ok if sleep mode left, CAN_WakeUp_Failed in an 
+  *                  other case.
+  */
+uint8_t CAN_WakeUp(CAN_TypeDef* CANx)
+{
+  uint32_t wait_slak = SLAK_TIMEOUT;
+  uint8_t wakeupstatus = CAN_WakeUp_Failed;
+  
+  /* Check the parameters */
+  assert_param(IS_CAN_ALL_PERIPH(CANx));
+    
+  /* Wake up request */
+  CANx->MCR &= ~(uint32_t)CAN_MCR_SLEEP;
+    
+  /* Sleep mode status */
+  while(((CANx->MSR & CAN_MSR_SLAK) == CAN_MSR_SLAK)&&(wait_slak!=0x00))
+  {
+   wait_slak--;
+  }
+  if((CANx->MSR & CAN_MSR_SLAK) != CAN_MSR_SLAK)
+  {
+   /* wake up done : Sleep mode exited */
+    wakeupstatus = CAN_WakeUp_Ok;
+  }
+  /* return wakeup status */
+  return (uint8_t)wakeupstatus;
+}
+
+
+/**
+  * @brief  Returns the CANx's last error code (LEC).
+  * @param  CANx:          where x can be 1 or 2 to to select the CAN peripheral.  
+  * @retval CAN_ErrorCode: specifies the Error code : 
+  *                        - CAN_ERRORCODE_NoErr            No Error  
+  *                        - CAN_ERRORCODE_StuffErr         Stuff Error
+  *                        - CAN_ERRORCODE_FormErr          Form Error
+  *                        - CAN_ERRORCODE_ACKErr           Acknowledgment Error
+  *                        - CAN_ERRORCODE_BitRecessiveErr  Bit Recessive Error
+  *                        - CAN_ERRORCODE_BitDominantErr   Bit Dominant Error
+  *                        - CAN_ERRORCODE_CRCErr           CRC Error
+  *                        - CAN_ERRORCODE_SoftwareSetErr   Software Set Error  
+  */
+ 
+uint8_t CAN_GetLastErrorCode(CAN_TypeDef* CANx)
+{
+  uint8_t errorcode=0;
+  
+  /* Check the parameters */
+  assert_param(IS_CAN_ALL_PERIPH(CANx));
+  
+  /* Get the error code*/
+  errorcode = (((uint8_t)CANx->ESR) & (uint8_t)CAN_ESR_LEC);
+  
+  /* Return the error code*/
+  return errorcode;
+}
+/**
+  * @brief  Returns the CANx Receive Error Counter (REC).
+  * @note   In case of an error during reception, this counter is incremented 
+  *         by 1 or by 8 depending on the error condition as defined by the CAN 
+  *         standard. After every successful reception, the counter is 
+  *         decremented by 1 or reset to 120 if its value was higher than 128. 
+  *         When the counter value exceeds 127, the CAN controller enters the 
+  *         error passive state.  
+  * @param  CANx: where x can be 1 or 2 to to select the CAN peripheral.  
+  * @retval CAN Receive Error Counter. 
+  */
+uint8_t CAN_GetReceiveErrorCounter(CAN_TypeDef* CANx)
+{
+  uint8_t counter=0;
+  
+  /* Check the parameters */
+  assert_param(IS_CAN_ALL_PERIPH(CANx));
+  
+  /* Get the Receive Error Counter*/
+  counter = (uint8_t)((CANx->ESR & CAN_ESR_REC)>> 24);
+  
+  /* Return the Receive Error Counter*/
+  return counter;
+}
+
+
+/**
+  * @brief  Returns the LSB of the 9-bit CANx Transmit Error Counter(TEC).
+  * @param  CANx:   where x can be 1 or 2 to to select the CAN peripheral.  
+  * @retval LSB of the 9-bit CAN Transmit Error Counter. 
+  */
+uint8_t CAN_GetLSBTransmitErrorCounter(CAN_TypeDef* CANx)
+{
+  uint8_t counter=0;
+  
+  /* Check the parameters */
+  assert_param(IS_CAN_ALL_PERIPH(CANx));
+  
+  /* Get the LSB of the 9-bit CANx Transmit Error Counter(TEC) */
+  counter = (uint8_t)((CANx->ESR & CAN_ESR_TEC)>> 16);
+  
+  /* Return the LSB of the 9-bit CANx Transmit Error Counter(TEC) */
+  return counter;
+}
+
+
+/**
+  * @brief  Enables or disables the specified CANx interrupts.
+  * @param  CANx:   where x can be 1 or 2 to to select the CAN peripheral.
+  * @param  CAN_IT: specifies the CAN interrupt sources to be enabled or disabled.
+  *                 This parameter can be: 
+  *                 - CAN_IT_TME, 
+  *                 - CAN_IT_FMP0, 
+  *                 - CAN_IT_FF0,
+  *                 - CAN_IT_FOV0, 
+  *                 - CAN_IT_FMP1, 
+  *                 - CAN_IT_FF1,
+  *                 - CAN_IT_FOV1, 
+  *                 - CAN_IT_EWG, 
+  *                 - CAN_IT_EPV,
+  *                 - CAN_IT_LEC, 
+  *                 - CAN_IT_ERR, 
+  *                 - CAN_IT_WKU or 
+  *                 - CAN_IT_SLK.
+  * @param  NewState: new state of the CAN interrupts.
+  *                   This parameter can be: ENABLE or DISABLE.
+  * @retval None.
+  */
+void CAN_ITConfig(CAN_TypeDef* CANx, uint32_t CAN_IT, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_CAN_ALL_PERIPH(CANx));
+  assert_param(IS_CAN_IT(CAN_IT));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Enable the selected CANx interrupt */
+    CANx->IER |= CAN_IT;
+  }
+  else
+  {
+    /* Disable the selected CANx interrupt */
+    CANx->IER &= ~CAN_IT;
+  }
+}
+/**
+  * @brief  Checks whether the specified CAN flag is set or not.
+  * @param  CANx:     where x can be 1 or 2 to to select the CAN peripheral.
+  * @param  CAN_FLAG: specifies the flag to check.
+  *                   This parameter can be one of the following flags: 
+  *                  - CAN_FLAG_EWG
+  *                  - CAN_FLAG_EPV 
+  *                  - CAN_FLAG_BOF
+  *                  - CAN_FLAG_RQCP0
+  *                  - CAN_FLAG_RQCP1
+  *                  - CAN_FLAG_RQCP2
+  *                  - CAN_FLAG_FMP1   
+  *                  - CAN_FLAG_FF1       
+  *                  - CAN_FLAG_FOV1   
+  *                  - CAN_FLAG_FMP0   
+  *                  - CAN_FLAG_FF0       
+  *                  - CAN_FLAG_FOV0   
+  *                  - CAN_FLAG_WKU 
+  *                  - CAN_FLAG_SLAK  
+  *                  - CAN_FLAG_LEC       
+  * @retval The new state of CAN_FLAG (SET or RESET).
+  */
+FlagStatus CAN_GetFlagStatus(CAN_TypeDef* CANx, uint32_t CAN_FLAG)
+{
+  FlagStatus bitstatus = RESET;
+  
+  /* Check the parameters */
+  assert_param(IS_CAN_ALL_PERIPH(CANx));
+  assert_param(IS_CAN_GET_FLAG(CAN_FLAG));
+  
+
+  if((CAN_FLAG & CAN_FLAGS_ESR) != (uint32_t)RESET)
+  { 
+    /* Check the status of the specified CAN flag */
+    if ((CANx->ESR & (CAN_FLAG & 0x000FFFFF)) != (uint32_t)RESET)
+    { 
+      /* CAN_FLAG is set */
+      bitstatus = SET;
+    }
+    else
+    { 
+      /* CAN_FLAG is reset */
+      bitstatus = RESET;
+    }
+  }
+  else if((CAN_FLAG & CAN_FLAGS_MSR) != (uint32_t)RESET)
+  { 
+    /* Check the status of the specified CAN flag */
+    if ((CANx->MSR & (CAN_FLAG & 0x000FFFFF)) != (uint32_t)RESET)
+    { 
+      /* CAN_FLAG is set */
+      bitstatus = SET;
+    }
+    else
+    { 
+      /* CAN_FLAG is reset */
+      bitstatus = RESET;
+    }
+  }
+  else if((CAN_FLAG & CAN_FLAGS_TSR) != (uint32_t)RESET)
+  { 
+    /* Check the status of the specified CAN flag */
+    if ((CANx->TSR & (CAN_FLAG & 0x000FFFFF)) != (uint32_t)RESET)
+    { 
+      /* CAN_FLAG is set */
+      bitstatus = SET;
+    }
+    else
+    { 
+      /* CAN_FLAG is reset */
+      bitstatus = RESET;
+    }
+  }
+  else if((CAN_FLAG & CAN_FLAGS_RF0R) != (uint32_t)RESET)
+  { 
+    /* Check the status of the specified CAN flag */
+    if ((CANx->RF0R & (CAN_FLAG & 0x000FFFFF)) != (uint32_t)RESET)
+    { 
+      /* CAN_FLAG is set */
+      bitstatus = SET;
+    }
+    else
+    { 
+      /* CAN_FLAG is reset */
+      bitstatus = RESET;
+    }
+  }
+  else /* If(CAN_FLAG & CAN_FLAGS_RF1R != (uint32_t)RESET) */
+  { 
+    /* Check the status of the specified CAN flag */
+    if ((uint32_t)(CANx->RF1R & (CAN_FLAG & 0x000FFFFF)) != (uint32_t)RESET)
+    { 
+      /* CAN_FLAG is set */
+      bitstatus = SET;
+    }
+    else
+    { 
+      /* CAN_FLAG is reset */
+      bitstatus = RESET;
+    }
+  }
+  /* Return the CAN_FLAG status */
+  return  bitstatus;
+}
+
+/**
+  * @brief  Clears the CAN's pending flags.
+  * @param  CANx:     where x can be 1 or 2 to to select the CAN peripheral.
+  * @param  CAN_FLAG: specifies the flag to clear.
+  *                   This parameter can be one of the following flags: 
+  *                    - CAN_FLAG_RQCP0
+  *                    - CAN_FLAG_RQCP1
+  *                    - CAN_FLAG_RQCP2
+  *                    - CAN_FLAG_FF1       
+  *                    - CAN_FLAG_FOV1   
+  *                    - CAN_FLAG_FF0       
+  *                    - CAN_FLAG_FOV0   
+  *                    - CAN_FLAG_WKU   
+  *                    - CAN_FLAG_SLAK    
+  *                    - CAN_FLAG_LEC       
+  * @retval None.
+  */
+void CAN_ClearFlag(CAN_TypeDef* CANx, uint32_t CAN_FLAG)
+{
+  uint32_t flagtmp=0;
+  /* Check the parameters */
+  assert_param(IS_CAN_ALL_PERIPH(CANx));
+  assert_param(IS_CAN_CLEAR_FLAG(CAN_FLAG));
+  
+  if (CAN_FLAG == CAN_FLAG_LEC) /* ESR register */
+  {
+    /* Clear the selected CAN flags */
+    CANx->ESR = (uint32_t)RESET;
+  }
+  else /* MSR or TSR or RF0R or RF1R */
+  {
+    flagtmp = CAN_FLAG & 0x000FFFFF;
+
+    if ((CAN_FLAG & CAN_FLAGS_RF0R)!=(uint32_t)RESET)
+    {
+      /* Receive Flags */
+      CANx->RF0R = (uint32_t)(flagtmp);
+    }
+    else if ((CAN_FLAG & CAN_FLAGS_RF1R)!=(uint32_t)RESET)
+    {
+      /* Receive Flags */
+      CANx->RF1R = (uint32_t)(flagtmp);
+    }
+    else if ((CAN_FLAG & CAN_FLAGS_TSR)!=(uint32_t)RESET)
+    {
+      /* Transmit Flags */
+      CANx->TSR = (uint32_t)(flagtmp);
+    }
+    else /* If((CAN_FLAG & CAN_FLAGS_MSR)!=(uint32_t)RESET) */
+    {
+      /* Operating mode Flags */
+      CANx->MSR = (uint32_t)(flagtmp);
+    }
+  }
+}
+
+/**
+  * @brief  Checks whether the specified CANx interrupt has occurred or not.
+  * @param  CANx:    where x can be 1 or 2 to to select the CAN peripheral.
+  * @param  CAN_IT:  specifies the CAN interrupt source to check.
+  *                  This parameter can be one of the following flags: 
+  *                 -  CAN_IT_TME               
+  *                 -  CAN_IT_FMP0              
+  *                 -  CAN_IT_FF0               
+  *                 -  CAN_IT_FOV0              
+  *                 -  CAN_IT_FMP1              
+  *                 -  CAN_IT_FF1               
+  *                 -  CAN_IT_FOV1              
+  *                 -  CAN_IT_WKU  
+  *                 -  CAN_IT_SLK  
+  *                 -  CAN_IT_EWG    
+  *                 -  CAN_IT_EPV    
+  *                 -  CAN_IT_BOF    
+  *                 -  CAN_IT_LEC    
+  *                 -  CAN_IT_ERR 
+  * @retval The current state of CAN_IT (SET or RESET).
+  */
+ITStatus CAN_GetITStatus(CAN_TypeDef* CANx, uint32_t CAN_IT)
+{
+  ITStatus itstatus = RESET;
+  /* Check the parameters */
+  assert_param(IS_CAN_ALL_PERIPH(CANx));
+  assert_param(IS_CAN_IT(CAN_IT));
+  
+  /* check the enable interrupt bit */
+ if((CANx->IER & CAN_IT) != RESET)
+ {
+   /* in case the Interrupt is enabled, .... */
+    switch (CAN_IT)
+    {
+      case CAN_IT_TME:
+               /* Check CAN_TSR_RQCPx bits */
+	             itstatus = CheckITStatus(CANx->TSR, CAN_TSR_RQCP0|CAN_TSR_RQCP1|CAN_TSR_RQCP2);  
+	      break;
+      case CAN_IT_FMP0:
+               /* Check CAN_RF0R_FMP0 bit */
+	             itstatus = CheckITStatus(CANx->RF0R, CAN_RF0R_FMP0);  
+	      break;
+      case CAN_IT_FF0:
+               /* Check CAN_RF0R_FULL0 bit */
+               itstatus = CheckITStatus(CANx->RF0R, CAN_RF0R_FULL0);  
+	      break;
+      case CAN_IT_FOV0:
+               /* Check CAN_RF0R_FOVR0 bit */
+               itstatus = CheckITStatus(CANx->RF0R, CAN_RF0R_FOVR0);  
+	      break;
+      case CAN_IT_FMP1:
+               /* Check CAN_RF1R_FMP1 bit */
+               itstatus = CheckITStatus(CANx->RF1R, CAN_RF1R_FMP1);  
+	      break;
+      case CAN_IT_FF1:
+               /* Check CAN_RF1R_FULL1 bit */
+	             itstatus = CheckITStatus(CANx->RF1R, CAN_RF1R_FULL1);  
+	      break;
+      case CAN_IT_FOV1:
+               /* Check CAN_RF1R_FOVR1 bit */
+	             itstatus = CheckITStatus(CANx->RF1R, CAN_RF1R_FOVR1);  
+	      break;
+      case CAN_IT_WKU:
+               /* Check CAN_MSR_WKUI bit */
+               itstatus = CheckITStatus(CANx->MSR, CAN_MSR_WKUI);  
+	      break;
+      case CAN_IT_SLK:
+               /* Check CAN_MSR_SLAKI bit */
+	             itstatus = CheckITStatus(CANx->MSR, CAN_MSR_SLAKI);  
+	      break;
+      case CAN_IT_EWG:
+               /* Check CAN_ESR_EWGF bit */
+	             itstatus = CheckITStatus(CANx->ESR, CAN_ESR_EWGF);  
+	      break;
+      case CAN_IT_EPV:
+               /* Check CAN_ESR_EPVF bit */
+	             itstatus = CheckITStatus(CANx->ESR, CAN_ESR_EPVF);  
+	      break;
+      case CAN_IT_BOF:
+               /* Check CAN_ESR_BOFF bit */
+	             itstatus = CheckITStatus(CANx->ESR, CAN_ESR_BOFF);  
+	      break;
+      case CAN_IT_LEC:
+               /* Check CAN_ESR_LEC bit */
+	             itstatus = CheckITStatus(CANx->ESR, CAN_ESR_LEC);  
+	      break;
+      case CAN_IT_ERR:
+               /* Check CAN_MSR_ERRI bit */ 
+               itstatus = CheckITStatus(CANx->MSR, CAN_MSR_ERRI); 
+	      break;
+      default :
+               /* in case of error, return RESET */
+              itstatus = RESET;
+              break;
+    }
+  }
+  else
+  {
+   /* in case the Interrupt is not enabled, return RESET */
+    itstatus  = RESET;
+  }
+  
+  /* Return the CAN_IT status */
+  return  itstatus;
+}
+
+/**
+  * @brief  Clears the CANx's interrupt pending bits.
+  * @param  CANx:    where x can be 1 or 2 to to select the CAN peripheral.
+  * @param  CAN_IT: specifies the interrupt pending bit to clear.
+  *                  -  CAN_IT_TME                     
+  *                  -  CAN_IT_FF0               
+  *                  -  CAN_IT_FOV0                     
+  *                  -  CAN_IT_FF1               
+  *                  -  CAN_IT_FOV1              
+  *                  -  CAN_IT_WKU  
+  *                  -  CAN_IT_SLK  
+  *                  -  CAN_IT_EWG    
+  *                  -  CAN_IT_EPV    
+  *                  -  CAN_IT_BOF    
+  *                  -  CAN_IT_LEC    
+  *                  -  CAN_IT_ERR 
+  * @retval None.
+  */
+void CAN_ClearITPendingBit(CAN_TypeDef* CANx, uint32_t CAN_IT)
+{
+  /* Check the parameters */
+  assert_param(IS_CAN_ALL_PERIPH(CANx));
+  assert_param(IS_CAN_CLEAR_IT(CAN_IT));
+
+  switch (CAN_IT)
+  {
+      case CAN_IT_TME:
+              /* Clear CAN_TSR_RQCPx (rc_w1)*/
+	      CANx->TSR = CAN_TSR_RQCP0|CAN_TSR_RQCP1|CAN_TSR_RQCP2;  
+	      break;
+      case CAN_IT_FF0:
+              /* Clear CAN_RF0R_FULL0 (rc_w1)*/
+	      CANx->RF0R = CAN_RF0R_FULL0; 
+	      break;
+      case CAN_IT_FOV0:
+              /* Clear CAN_RF0R_FOVR0 (rc_w1)*/
+	      CANx->RF0R = CAN_RF0R_FOVR0; 
+	      break;
+      case CAN_IT_FF1:
+              /* Clear CAN_RF1R_FULL1 (rc_w1)*/
+	      CANx->RF1R = CAN_RF1R_FULL1;  
+	      break;
+      case CAN_IT_FOV1:
+              /* Clear CAN_RF1R_FOVR1 (rc_w1)*/
+	      CANx->RF1R = CAN_RF1R_FOVR1; 
+	      break;
+      case CAN_IT_WKU:
+              /* Clear CAN_MSR_WKUI (rc_w1)*/
+	      CANx->MSR = CAN_MSR_WKUI;  
+	      break;
+      case CAN_IT_SLK:
+              /* Clear CAN_MSR_SLAKI (rc_w1)*/ 
+	      CANx->MSR = CAN_MSR_SLAKI;   
+	      break;
+      case CAN_IT_EWG:
+              /* Clear CAN_MSR_ERRI (rc_w1) */
+	      CANx->MSR = CAN_MSR_ERRI;
+              /* Note : the corresponding Flag is cleared by hardware depending 
+                        of the CAN Bus status*/ 
+	      break;
+      case CAN_IT_EPV:
+              /* Clear CAN_MSR_ERRI (rc_w1) */
+	      CANx->MSR = CAN_MSR_ERRI; 
+              /* Note : the corresponding Flag is cleared by hardware depending 
+                        of the CAN Bus status*/
+	      break;
+      case CAN_IT_BOF:
+              /* Clear CAN_MSR_ERRI (rc_w1) */ 
+	      CANx->MSR = CAN_MSR_ERRI; 
+              /* Note : the corresponding Flag is cleared by hardware depending 
+                        of the CAN Bus status*/
+	      break;
+      case CAN_IT_LEC:
+              /*  Clear LEC bits */
+	      CANx->ESR = RESET; 
+              /* Clear CAN_MSR_ERRI (rc_w1) */
+	      CANx->MSR = CAN_MSR_ERRI; 
+	      break;
+      case CAN_IT_ERR:
+              /*Clear LEC bits */
+	      CANx->ESR = RESET; 
+              /* Clear CAN_MSR_ERRI (rc_w1) */
+	      CANx->MSR = CAN_MSR_ERRI; 
+	      /* Note : BOFF, EPVF and EWGF Flags are cleared by hardware depending 
+                  of the CAN Bus status*/
+	      break;
+      default :
+	      break;
+   }
+}
+
+/**
+  * @brief  Checks whether the CAN interrupt has occurred or not.
+  * @param  CAN_Reg: specifies the CAN interrupt register to check.
+  * @param  It_Bit:  specifies the interrupt source bit to check.
+  * @retval The new state of the CAN Interrupt (SET or RESET).
+  */
+static ITStatus CheckITStatus(uint32_t CAN_Reg, uint32_t It_Bit)
+{
+  ITStatus pendingbitstatus = RESET;
+  
+  if ((CAN_Reg & It_Bit) != (uint32_t)RESET)
+  {
+    /* CAN_IT is set */
+    pendingbitstatus = SET;
+  }
+  else
+  {
+    /* CAN_IT is reset */
+    pendingbitstatus = RESET;
+  }
+  return pendingbitstatus;
+}
+
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/STM32_4路称重_Git提交精简工程/src/STM32F10x_FWLib/src/stm32f10x_cec.c b/STM32_4路称重_Git提交精简工程/src/STM32F10x_FWLib/src/stm32f10x_cec.c
new file mode 100755
index 0000000..08b501a
--- /dev/null
+++ b/STM32_4路称重_Git提交精简工程/src/STM32F10x_FWLib/src/stm32f10x_cec.c
@@ -0,0 +1,433 @@
+/**
+  ******************************************************************************
+  * @file    stm32f10x_cec.c
+  * @author  MCD Application Team
+  * @version V3.5.0
+  * @date    11-March-2011
+  * @brief   This file provides all the CEC firmware functions.
+  ******************************************************************************
+  * @attention
+  *
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+  *
+  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x_cec.h"
+#include "stm32f10x_rcc.h"
+
+/** @addtogroup STM32F10x_StdPeriph_Driver
+  * @{
+  */
+
+/** @defgroup CEC 
+  * @brief CEC driver modules
+  * @{
+  */
+
+/** @defgroup CEC_Private_TypesDefinitions
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+
+/** @defgroup CEC_Private_Defines
+  * @{
+  */ 
+
+/* ------------ CEC registers bit address in the alias region ----------- */
+#define CEC_OFFSET                (CEC_BASE - PERIPH_BASE)
+
+/* --- CFGR Register ---*/
+
+/* Alias word address of PE bit */
+#define CFGR_OFFSET                 (CEC_OFFSET + 0x00)
+#define PE_BitNumber                0x00
+#define CFGR_PE_BB                  (PERIPH_BB_BASE + (CFGR_OFFSET * 32) + (PE_BitNumber * 4))
+
+/* Alias word address of IE bit */
+#define IE_BitNumber                0x01
+#define CFGR_IE_BB                  (PERIPH_BB_BASE + (CFGR_OFFSET * 32) + (IE_BitNumber * 4))
+
+/* --- CSR Register ---*/
+
+/* Alias word address of TSOM bit */
+#define CSR_OFFSET                  (CEC_OFFSET + 0x10)
+#define TSOM_BitNumber              0x00
+#define CSR_TSOM_BB                 (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (TSOM_BitNumber * 4))
+
+/* Alias word address of TEOM bit */
+#define TEOM_BitNumber              0x01
+#define CSR_TEOM_BB                 (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (TEOM_BitNumber * 4))
+  
+#define CFGR_CLEAR_Mask            (uint8_t)(0xF3)        /* CFGR register Mask */
+#define FLAG_Mask                  ((uint32_t)0x00FFFFFF) /* CEC FLAG mask */
+ 
+/**
+  * @}
+  */ 
+
+
+/** @defgroup CEC_Private_Macros
+  * @{
+  */ 
+
+/**
+  * @}
+  */ 
+
+
+/** @defgroup CEC_Private_Variables
+  * @{
+  */ 
+
+/**
+  * @}
+  */ 
+
+
+/** @defgroup CEC_Private_FunctionPrototypes
+  * @{
+  */
+ 
+/**
+  * @}
+  */ 
+
+
+/** @defgroup CEC_Private_Functions
+  * @{
+  */ 
+
+/**
+  * @brief  Deinitializes the CEC peripheral registers to their default reset 
+  *         values.
+  * @param  None
+  * @retval None
+  */
+void CEC_DeInit(void)
+{
+  /* Enable CEC reset state */
+  RCC_APB1PeriphResetCmd(RCC_APB1Periph_CEC, ENABLE);  
+  /* Release CEC from reset state */
+  RCC_APB1PeriphResetCmd(RCC_APB1Periph_CEC, DISABLE); 
+}
+
+
+/**
+  * @brief  Initializes the CEC peripheral according to the specified 
+  *         parameters in the CEC_InitStruct.
+  * @param  CEC_InitStruct: pointer to an CEC_InitTypeDef structure that
+  *         contains the configuration information for the specified
+  *         CEC peripheral.
+  * @retval None
+  */
+void CEC_Init(CEC_InitTypeDef* CEC_InitStruct)
+{
+  uint16_t tmpreg = 0;
+ 
+  /* Check the parameters */
+  assert_param(IS_CEC_BIT_TIMING_ERROR_MODE(CEC_InitStruct->CEC_BitTimingMode)); 
+  assert_param(IS_CEC_BIT_PERIOD_ERROR_MODE(CEC_InitStruct->CEC_BitPeriodMode));
+     
+  /*---------------------------- CEC CFGR Configuration -----------------*/
+  /* Get the CEC CFGR value */
+  tmpreg = CEC->CFGR;
+  
+  /* Clear BTEM and BPEM bits */
+  tmpreg &= CFGR_CLEAR_Mask;
+  
+  /* Configure CEC: Bit Timing Error and Bit Period Error */
+  tmpreg |= (uint16_t)(CEC_InitStruct->CEC_BitTimingMode | CEC_InitStruct->CEC_BitPeriodMode);
+
+  /* Write to CEC CFGR  register*/
+  CEC->CFGR = tmpreg;
+  
+}
+
+/**
+  * @brief  Enables or disables the specified CEC peripheral.
+  * @param  NewState: new state of the CEC peripheral. 
+  *     This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void CEC_Cmd(FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  *(__IO uint32_t *) CFGR_PE_BB = (uint32_t)NewState;
+
+  if(NewState == DISABLE)
+  {
+    /* Wait until the PE bit is cleared by hardware (Idle Line detected) */
+    while((CEC->CFGR & CEC_CFGR_PE) != (uint32_t)RESET)
+    {
+    }  
+  }  
+}
+
+/**
+  * @brief  Enables or disables the CEC interrupt.
+  * @param  NewState: new state of the CEC interrupt.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void CEC_ITConfig(FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  *(__IO uint32_t *) CFGR_IE_BB = (uint32_t)NewState;
+}
+
+/**
+  * @brief  Defines the Own Address of the CEC device.
+  * @param  CEC_OwnAddress: The CEC own address
+  * @retval None
+  */
+void CEC_OwnAddressConfig(uint8_t CEC_OwnAddress)
+{
+  /* Check the parameters */
+  assert_param(IS_CEC_ADDRESS(CEC_OwnAddress));
+
+  /* Set the CEC own address */
+  CEC->OAR = CEC_OwnAddress;
+}
+
+/**
+  * @brief  Sets the CEC prescaler value.
+  * @param  CEC_Prescaler: CEC prescaler new value
+  * @retval None
+  */
+void CEC_SetPrescaler(uint16_t CEC_Prescaler)
+{
+  /* Check the parameters */
+  assert_param(IS_CEC_PRESCALER(CEC_Prescaler));
+
+  /* Set the  Prescaler value*/
+  CEC->PRES = CEC_Prescaler;
+}
+
+/**
+  * @brief  Transmits single data through the CEC peripheral.
+  * @param  Data: the data to transmit.
+  * @retval None
+  */
+void CEC_SendDataByte(uint8_t Data)
+{  
+  /* Transmit Data */
+  CEC->TXD = Data ;
+}
+
+
+/**
+  * @brief  Returns the most recent received data by the CEC peripheral.
+  * @param  None
+  * @retval The received data.
+  */
+uint8_t CEC_ReceiveDataByte(void)
+{
+  /* Receive Data */
+  return (uint8_t)(CEC->RXD);
+}
+
+/**
+  * @brief  Starts a new message.
+  * @param  None
+  * @retval None
+  */
+void CEC_StartOfMessage(void)
+{  
+  /* Starts of new message */
+  *(__IO uint32_t *) CSR_TSOM_BB = (uint32_t)0x1;
+}
+
+/**
+  * @brief  Transmits message with or without an EOM bit.
+  * @param  NewState: new state of the CEC Tx End Of Message. 
+  *     This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void CEC_EndOfMessageCmd(FunctionalState NewState)
+{   
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  
+  /* The data byte will be transmitted with or without an EOM bit*/
+  *(__IO uint32_t *) CSR_TEOM_BB = (uint32_t)NewState;
+}
+
+/**
+  * @brief  Gets the CEC flag status
+  * @param  CEC_FLAG: specifies the CEC flag to check. 
+  *   This parameter can be one of the following values:
+  *     @arg CEC_FLAG_BTE: Bit Timing Error
+  *     @arg CEC_FLAG_BPE: Bit Period Error
+  *     @arg CEC_FLAG_RBTFE: Rx Block Transfer Finished Error
+  *     @arg CEC_FLAG_SBE: Start Bit Error
+  *     @arg CEC_FLAG_ACKE: Block Acknowledge Error
+  *     @arg CEC_FLAG_LINE: Line Error
+  *     @arg CEC_FLAG_TBTFE: Tx Block Transfer Finished Error
+  *     @arg CEC_FLAG_TEOM: Tx End Of Message 
+  *     @arg CEC_FLAG_TERR: Tx Error
+  *     @arg CEC_FLAG_TBTRF: Tx Byte Transfer Request or Block Transfer Finished
+  *     @arg CEC_FLAG_RSOM: Rx Start Of Message
+  *     @arg CEC_FLAG_REOM: Rx End Of Message
+  *     @arg CEC_FLAG_RERR: Rx Error
+  *     @arg CEC_FLAG_RBTF: Rx Byte/Block Transfer Finished
+  * @retval The new state of CEC_FLAG (SET or RESET)
+  */
+FlagStatus CEC_GetFlagStatus(uint32_t CEC_FLAG) 
+{
+  FlagStatus bitstatus = RESET;
+  uint32_t cecreg = 0, cecbase = 0;
+  
+  /* Check the parameters */
+  assert_param(IS_CEC_GET_FLAG(CEC_FLAG));
+ 
+  /* Get the CEC peripheral base address */
+  cecbase = (uint32_t)(CEC_BASE);
+  
+  /* Read flag register index */
+  cecreg = CEC_FLAG >> 28;
+  
+  /* Get bit[23:0] of the flag */
+  CEC_FLAG &= FLAG_Mask;
+  
+  if(cecreg != 0)
+  {
+    /* Flag in CEC ESR Register */
+    CEC_FLAG = (uint32_t)(CEC_FLAG >> 16);
+    
+    /* Get the CEC ESR register address */
+    cecbase += 0xC;
+  }
+  else
+  {
+    /* Get the CEC CSR register address */
+    cecbase += 0x10;
+  }
+  
+  if(((*(__IO uint32_t *)cecbase) & CEC_FLAG) != (uint32_t)RESET)
+  {
+    /* CEC_FLAG is set */
+    bitstatus = SET;
+  }
+  else
+  {
+    /* CEC_FLAG is reset */
+    bitstatus = RESET;
+  }
+  
+  /* Return the CEC_FLAG status */
+  return  bitstatus;
+}
+
+/**
+  * @brief  Clears the CEC's pending flags.
+  * @param  CEC_FLAG: specifies the flag to clear. 
+  *   This parameter can be any combination of the following values:
+  *     @arg CEC_FLAG_TERR: Tx Error
+  *     @arg CEC_FLAG_TBTRF: Tx Byte Transfer Request or Block Transfer Finished
+  *     @arg CEC_FLAG_RSOM: Rx Start Of Message
+  *     @arg CEC_FLAG_REOM: Rx End Of Message
+  *     @arg CEC_FLAG_RERR: Rx Error
+  *     @arg CEC_FLAG_RBTF: Rx Byte/Block Transfer Finished
+  * @retval None
+  */
+void CEC_ClearFlag(uint32_t CEC_FLAG)
+{ 
+  uint32_t tmp = 0x0;
+  
+  /* Check the parameters */
+  assert_param(IS_CEC_CLEAR_FLAG(CEC_FLAG));
+
+  tmp = CEC->CSR & 0x2;
+       
+  /* Clear the selected CEC flags */
+  CEC->CSR &= (uint32_t)(((~(uint32_t)CEC_FLAG) & 0xFFFFFFFC) | tmp);
+}
+
+/**
+  * @brief  Checks whether the specified CEC interrupt has occurred or not.
+  * @param  CEC_IT: specifies the CEC interrupt source to check. 
+  *   This parameter can be one of the following values:
+  *     @arg CEC_IT_TERR: Tx Error
+  *     @arg CEC_IT_TBTF: Tx Block Transfer Finished
+  *     @arg CEC_IT_RERR: Rx Error
+  *     @arg CEC_IT_RBTF: Rx Block Transfer Finished
+  * @retval The new state of CEC_IT (SET or RESET).
+  */
+ITStatus CEC_GetITStatus(uint8_t CEC_IT)
+{
+  ITStatus bitstatus = RESET;
+  uint32_t enablestatus = 0;
+  
+  /* Check the parameters */
+   assert_param(IS_CEC_GET_IT(CEC_IT));
+   
+  /* Get the CEC IT enable bit status */
+  enablestatus = (CEC->CFGR & (uint8_t)CEC_CFGR_IE) ;
+  
+  /* Check the status of the specified CEC interrupt */
+  if (((CEC->CSR & CEC_IT) != (uint32_t)RESET) && enablestatus)
+  {
+    /* CEC_IT is set */
+    bitstatus = SET;
+  }
+  else
+  {
+    /* CEC_IT is reset */
+    bitstatus = RESET;
+  }
+  /* Return the CEC_IT status */
+  return  bitstatus;
+}
+
+/**
+  * @brief  Clears the CEC's interrupt pending bits.
+  * @param  CEC_IT: specifies the CEC interrupt pending bit to clear.
+  *   This parameter can be any combination of the following values:
+  *     @arg CEC_IT_TERR: Tx Error
+  *     @arg CEC_IT_TBTF: Tx Block Transfer Finished
+  *     @arg CEC_IT_RERR: Rx Error
+  *     @arg CEC_IT_RBTF: Rx Block Transfer Finished
+  * @retval None
+  */
+void CEC_ClearITPendingBit(uint16_t CEC_IT)
+{
+  uint32_t tmp = 0x0;
+  
+  /* Check the parameters */
+  assert_param(IS_CEC_GET_IT(CEC_IT));
+  
+  tmp = CEC->CSR & 0x2;
+  
+  /* Clear the selected CEC interrupt pending bits */
+  CEC->CSR &= (uint32_t)(((~(uint32_t)CEC_IT) & 0xFFFFFFFC) | tmp);
+}
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/STM32_4路称重_Git提交精简工程/src/STM32F10x_FWLib/src/stm32f10x_crc.c b/STM32_4路称重_Git提交精简工程/src/STM32F10x_FWLib/src/stm32f10x_crc.c
new file mode 100755
index 0000000..ef0c047
--- /dev/null
+++ b/STM32_4路称重_Git提交精简工程/src/STM32F10x_FWLib/src/stm32f10x_crc.c
@@ -0,0 +1,160 @@
+/**
+  ******************************************************************************
+  * @file    stm32f10x_crc.c
+  * @author  MCD Application Team
+  * @version V3.5.0
+  * @date    11-March-2011
+  * @brief   This file provides all the CRC firmware functions.
+  ******************************************************************************
+  * @attention
+  *
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+  *
+  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x_crc.h"
+
+/** @addtogroup STM32F10x_StdPeriph_Driver
+  * @{
+  */
+
+/** @defgroup CRC 
+  * @brief CRC driver modules
+  * @{
+  */
+
+/** @defgroup CRC_Private_TypesDefinitions
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup CRC_Private_Defines
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup CRC_Private_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup CRC_Private_Variables
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup CRC_Private_FunctionPrototypes
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup CRC_Private_Functions
+  * @{
+  */
+
+/**
+  * @brief  Resets the CRC Data register (DR).
+  * @param  None
+  * @retval None
+  */
+void CRC_ResetDR(void)
+{
+  /* Reset CRC generator */
+  CRC->CR = CRC_CR_RESET;
+}
+
+/**
+  * @brief  Computes the 32-bit CRC of a given data word(32-bit).
+  * @param  Data: data word(32-bit) to compute its CRC
+  * @retval 32-bit CRC
+  */
+uint32_t CRC_CalcCRC(uint32_t Data)
+{
+  CRC->DR = Data;
+  
+  return (CRC->DR);
+}
+
+/**
+  * @brief  Computes the 32-bit CRC of a given buffer of data word(32-bit).
+  * @param  pBuffer: pointer to the buffer containing the data to be computed
+  * @param  BufferLength: length of the buffer to be computed					
+  * @retval 32-bit CRC
+  */
+uint32_t CRC_CalcBlockCRC(uint32_t pBuffer[], uint32_t BufferLength)
+{
+  uint32_t index = 0;
+  
+  for(index = 0; index < BufferLength; index++)
+  {
+    CRC->DR = pBuffer[index];
+  }
+  return (CRC->DR);
+}
+
+/**
+  * @brief  Returns the current CRC value.
+  * @param  None
+  * @retval 32-bit CRC
+  */
+uint32_t CRC_GetCRC(void)
+{
+  return (CRC->DR);
+}
+
+/**
+  * @brief  Stores a 8-bit data in the Independent Data(ID) register.
+  * @param  IDValue: 8-bit value to be stored in the ID register 					
+  * @retval None
+  */
+void CRC_SetIDRegister(uint8_t IDValue)
+{
+  CRC->IDR = IDValue;
+}
+
+/**
+  * @brief  Returns the 8-bit data stored in the Independent Data(ID) register
+  * @param  None
+  * @retval 8-bit value of the ID register 
+  */
+uint8_t CRC_GetIDRegister(void)
+{
+  return (CRC->IDR);
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/STM32_4路称重_Git提交精简工程/src/STM32F10x_FWLib/src/stm32f10x_dac.c b/STM32_4路称重_Git提交精简工程/src/STM32F10x_FWLib/src/stm32f10x_dac.c
new file mode 100755
index 0000000..025b8e2
--- /dev/null
+++ b/STM32_4路称重_Git提交精简工程/src/STM32F10x_FWLib/src/stm32f10x_dac.c
@@ -0,0 +1,571 @@
+/**
+  ******************************************************************************
+  * @file    stm32f10x_dac.c
+  * @author  MCD Application Team
+  * @version V3.5.0
+  * @date    11-March-2011
+  * @brief   This file provides all the DAC firmware functions.
+  ******************************************************************************
+  * @attention
+  *
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+  *
+  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x_dac.h"
+#include "stm32f10x_rcc.h"
+
+/** @addtogroup STM32F10x_StdPeriph_Driver
+  * @{
+  */
+
+/** @defgroup DAC 
+  * @brief DAC driver modules
+  * @{
+  */ 
+
+/** @defgroup DAC_Private_TypesDefinitions
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup DAC_Private_Defines
+  * @{
+  */
+
+/* CR register Mask */
+#define CR_CLEAR_MASK              ((uint32_t)0x00000FFE)
+
+/* DAC Dual Channels SWTRIG masks */
+#define DUAL_SWTRIG_SET            ((uint32_t)0x00000003)
+#define DUAL_SWTRIG_RESET          ((uint32_t)0xFFFFFFFC)
+
+/* DHR registers offsets */
+#define DHR12R1_OFFSET             ((uint32_t)0x00000008)
+#define DHR12R2_OFFSET             ((uint32_t)0x00000014)
+#define DHR12RD_OFFSET             ((uint32_t)0x00000020)
+
+/* DOR register offset */
+#define DOR_OFFSET                 ((uint32_t)0x0000002C)
+/**
+  * @}
+  */
+
+/** @defgroup DAC_Private_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup DAC_Private_Variables
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup DAC_Private_FunctionPrototypes
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup DAC_Private_Functions
+  * @{
+  */
+
+/**
+  * @brief  Deinitializes the DAC peripheral registers to their default reset values.
+  * @param  None
+  * @retval None
+  */
+void DAC_DeInit(void)
+{
+  /* Enable DAC reset state */
+  RCC_APB1PeriphResetCmd(RCC_APB1Periph_DAC, ENABLE);
+  /* Release DAC from reset state */
+  RCC_APB1PeriphResetCmd(RCC_APB1Periph_DAC, DISABLE);
+}
+
+/**
+  * @brief  Initializes the DAC peripheral according to the specified 
+  *         parameters in the DAC_InitStruct.
+  * @param  DAC_Channel: the selected DAC channel. 
+  *   This parameter can be one of the following values:
+  *     @arg DAC_Channel_1: DAC Channel1 selected
+  *     @arg DAC_Channel_2: DAC Channel2 selected
+  * @param  DAC_InitStruct: pointer to a DAC_InitTypeDef structure that
+  *        contains the configuration information for the specified DAC channel.
+  * @retval None
+  */
+void DAC_Init(uint32_t DAC_Channel, DAC_InitTypeDef* DAC_InitStruct)
+{
+  uint32_t tmpreg1 = 0, tmpreg2 = 0;
+  /* Check the DAC parameters */
+  assert_param(IS_DAC_TRIGGER(DAC_InitStruct->DAC_Trigger));
+  assert_param(IS_DAC_GENERATE_WAVE(DAC_InitStruct->DAC_WaveGeneration));
+  assert_param(IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(DAC_InitStruct->DAC_LFSRUnmask_TriangleAmplitude));
+  assert_param(IS_DAC_OUTPUT_BUFFER_STATE(DAC_InitStruct->DAC_OutputBuffer));
+/*---------------------------- DAC CR Configuration --------------------------*/
+  /* Get the DAC CR value */
+  tmpreg1 = DAC->CR;
+  /* Clear BOFFx, TENx, TSELx, WAVEx and MAMPx bits */
+  tmpreg1 &= ~(CR_CLEAR_MASK << DAC_Channel);
+  /* Configure for the selected DAC channel: buffer output, trigger, wave generation,
+     mask/amplitude for wave generation */
+  /* Set TSELx and TENx bits according to DAC_Trigger value */
+  /* Set WAVEx bits according to DAC_WaveGeneration value */
+  /* Set MAMPx bits according to DAC_LFSRUnmask_TriangleAmplitude value */ 
+  /* Set BOFFx bit according to DAC_OutputBuffer value */   
+  tmpreg2 = (DAC_InitStruct->DAC_Trigger | DAC_InitStruct->DAC_WaveGeneration |
+             DAC_InitStruct->DAC_LFSRUnmask_TriangleAmplitude | DAC_InitStruct->DAC_OutputBuffer);
+  /* Calculate CR register value depending on DAC_Channel */
+  tmpreg1 |= tmpreg2 << DAC_Channel;
+  /* Write to DAC CR */
+  DAC->CR = tmpreg1;
+}
+
+/**
+  * @brief  Fills each DAC_InitStruct member with its default value.
+  * @param  DAC_InitStruct : pointer to a DAC_InitTypeDef structure which will
+  *         be initialized.
+  * @retval None
+  */
+void DAC_StructInit(DAC_InitTypeDef* DAC_InitStruct)
+{
+/*--------------- Reset DAC init structure parameters values -----------------*/
+  /* Initialize the DAC_Trigger member */
+  DAC_InitStruct->DAC_Trigger = DAC_Trigger_None;
+  /* Initialize the DAC_WaveGeneration member */
+  DAC_InitStruct->DAC_WaveGeneration = DAC_WaveGeneration_None;
+  /* Initialize the DAC_LFSRUnmask_TriangleAmplitude member */
+  DAC_InitStruct->DAC_LFSRUnmask_TriangleAmplitude = DAC_LFSRUnmask_Bit0;
+  /* Initialize the DAC_OutputBuffer member */
+  DAC_InitStruct->DAC_OutputBuffer = DAC_OutputBuffer_Enable;
+}
+
+/**
+  * @brief  Enables or disables the specified DAC channel.
+  * @param  DAC_Channel: the selected DAC channel. 
+  *   This parameter can be one of the following values:
+  *     @arg DAC_Channel_1: DAC Channel1 selected
+  *     @arg DAC_Channel_2: DAC Channel2 selected
+  * @param  NewState: new state of the DAC channel. 
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void DAC_Cmd(uint32_t DAC_Channel, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_DAC_CHANNEL(DAC_Channel));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  if (NewState != DISABLE)
+  {
+    /* Enable the selected DAC channel */
+    DAC->CR |= (DAC_CR_EN1 << DAC_Channel);
+  }
+  else
+  {
+    /* Disable the selected DAC channel */
+    DAC->CR &= ~(DAC_CR_EN1 << DAC_Channel);
+  }
+}
+#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
+/**
+  * @brief  Enables or disables the specified DAC interrupts.
+  * @param  DAC_Channel: the selected DAC channel. 
+  *   This parameter can be one of the following values:
+  *     @arg DAC_Channel_1: DAC Channel1 selected
+  *     @arg DAC_Channel_2: DAC Channel2 selected
+  * @param  DAC_IT: specifies the DAC interrupt sources to be enabled or disabled. 
+  *   This parameter can be the following values:
+  *     @arg DAC_IT_DMAUDR: DMA underrun interrupt mask                      
+  * @param  NewState: new state of the specified DAC interrupts.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */ 
+void DAC_ITConfig(uint32_t DAC_Channel, uint32_t DAC_IT, FunctionalState NewState)  
+{
+  /* Check the parameters */
+  assert_param(IS_DAC_CHANNEL(DAC_Channel));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  assert_param(IS_DAC_IT(DAC_IT)); 
+
+  if (NewState != DISABLE)
+  {
+    /* Enable the selected DAC interrupts */
+    DAC->CR |=  (DAC_IT << DAC_Channel);
+  }
+  else
+  {
+    /* Disable the selected DAC interrupts */
+    DAC->CR &= (~(uint32_t)(DAC_IT << DAC_Channel));
+  }
+}
+#endif
+
+/**
+  * @brief  Enables or disables the specified DAC channel DMA request.
+  * @param  DAC_Channel: the selected DAC channel. 
+  *   This parameter can be one of the following values:
+  *     @arg DAC_Channel_1: DAC Channel1 selected
+  *     @arg DAC_Channel_2: DAC Channel2 selected
+  * @param  NewState: new state of the selected DAC channel DMA request.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void DAC_DMACmd(uint32_t DAC_Channel, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_DAC_CHANNEL(DAC_Channel));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  if (NewState != DISABLE)
+  {
+    /* Enable the selected DAC channel DMA request */
+    DAC->CR |= (DAC_CR_DMAEN1 << DAC_Channel);
+  }
+  else
+  {
+    /* Disable the selected DAC channel DMA request */
+    DAC->CR &= ~(DAC_CR_DMAEN1 << DAC_Channel);
+  }
+}
+
+/**
+  * @brief  Enables or disables the selected DAC channel software trigger.
+  * @param  DAC_Channel: the selected DAC channel. 
+  *   This parameter can be one of the following values:
+  *     @arg DAC_Channel_1: DAC Channel1 selected
+  *     @arg DAC_Channel_2: DAC Channel2 selected
+  * @param  NewState: new state of the selected DAC channel software trigger.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void DAC_SoftwareTriggerCmd(uint32_t DAC_Channel, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_DAC_CHANNEL(DAC_Channel));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  if (NewState != DISABLE)
+  {
+    /* Enable software trigger for the selected DAC channel */
+    DAC->SWTRIGR |= (uint32_t)DAC_SWTRIGR_SWTRIG1 << (DAC_Channel >> 4);
+  }
+  else
+  {
+    /* Disable software trigger for the selected DAC channel */
+    DAC->SWTRIGR &= ~((uint32_t)DAC_SWTRIGR_SWTRIG1 << (DAC_Channel >> 4));
+  }
+}
+
+/**
+  * @brief  Enables or disables simultaneously the two DAC channels software
+  *   triggers.
+  * @param  NewState: new state of the DAC channels software triggers.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void DAC_DualSoftwareTriggerCmd(FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  if (NewState != DISABLE)
+  {
+    /* Enable software trigger for both DAC channels */
+    DAC->SWTRIGR |= DUAL_SWTRIG_SET ;
+  }
+  else
+  {
+    /* Disable software trigger for both DAC channels */
+    DAC->SWTRIGR &= DUAL_SWTRIG_RESET;
+  }
+}
+
+/**
+  * @brief  Enables or disables the selected DAC channel wave generation.
+  * @param  DAC_Channel: the selected DAC channel. 
+  *   This parameter can be one of the following values:
+  *     @arg DAC_Channel_1: DAC Channel1 selected
+  *     @arg DAC_Channel_2: DAC Channel2 selected
+  * @param  DAC_Wave: Specifies the wave type to enable or disable.
+  *   This parameter can be one of the following values:
+  *     @arg DAC_Wave_Noise: noise wave generation
+  *     @arg DAC_Wave_Triangle: triangle wave generation
+  * @param  NewState: new state of the selected DAC channel wave generation.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void DAC_WaveGenerationCmd(uint32_t DAC_Channel, uint32_t DAC_Wave, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_DAC_CHANNEL(DAC_Channel));
+  assert_param(IS_DAC_WAVE(DAC_Wave)); 
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  if (NewState != DISABLE)
+  {
+    /* Enable the selected wave generation for the selected DAC channel */
+    DAC->CR |= DAC_Wave << DAC_Channel;
+  }
+  else
+  {
+    /* Disable the selected wave generation for the selected DAC channel */
+    DAC->CR &= ~(DAC_Wave << DAC_Channel);
+  }
+}
+
+/**
+  * @brief  Set the specified data holding register value for DAC channel1.
+  * @param  DAC_Align: Specifies the data alignment for DAC channel1.
+  *   This parameter can be one of the following values:
+  *     @arg DAC_Align_8b_R: 8bit right data alignment selected
+  *     @arg DAC_Align_12b_L: 12bit left data alignment selected
+  *     @arg DAC_Align_12b_R: 12bit right data alignment selected
+  * @param  Data : Data to be loaded in the selected data holding register.
+  * @retval None
+  */
+void DAC_SetChannel1Data(uint32_t DAC_Align, uint16_t Data)
+{  
+  __IO uint32_t tmp = 0;
+  
+  /* Check the parameters */
+  assert_param(IS_DAC_ALIGN(DAC_Align));
+  assert_param(IS_DAC_DATA(Data));
+  
+  tmp = (uint32_t)DAC_BASE; 
+  tmp += DHR12R1_OFFSET + DAC_Align;
+
+  /* Set the DAC channel1 selected data holding register */
+  *(__IO uint32_t *) tmp = Data;
+}
+
+/**
+  * @brief  Set the specified data holding register value for DAC channel2.
+  * @param  DAC_Align: Specifies the data alignment for DAC channel2.
+  *   This parameter can be one of the following values:
+  *     @arg DAC_Align_8b_R: 8bit right data alignment selected
+  *     @arg DAC_Align_12b_L: 12bit left data alignment selected
+  *     @arg DAC_Align_12b_R: 12bit right data alignment selected
+  * @param  Data : Data to be loaded in the selected data holding register.
+  * @retval None
+  */
+void DAC_SetChannel2Data(uint32_t DAC_Align, uint16_t Data)
+{
+  __IO uint32_t tmp = 0;
+
+  /* Check the parameters */
+  assert_param(IS_DAC_ALIGN(DAC_Align));
+  assert_param(IS_DAC_DATA(Data));
+  
+  tmp = (uint32_t)DAC_BASE;
+  tmp += DHR12R2_OFFSET + DAC_Align;
+
+  /* Set the DAC channel2 selected data holding register */
+  *(__IO uint32_t *)tmp = Data;
+}
+
+/**
+  * @brief  Set the specified data holding register value for dual channel
+  *   DAC.
+  * @param  DAC_Align: Specifies the data alignment for dual channel DAC.
+  *   This parameter can be one of the following values:
+  *     @arg DAC_Align_8b_R: 8bit right data alignment selected
+  *     @arg DAC_Align_12b_L: 12bit left data alignment selected
+  *     @arg DAC_Align_12b_R: 12bit right data alignment selected
+  * @param  Data2: Data for DAC Channel2 to be loaded in the selected data 
+  *   holding register.
+  * @param  Data1: Data for DAC Channel1 to be loaded in the selected data 
+  *   holding register.
+  * @retval None
+  */
+void DAC_SetDualChannelData(uint32_t DAC_Align, uint16_t Data2, uint16_t Data1)
+{
+  uint32_t data = 0, tmp = 0;
+  
+  /* Check the parameters */
+  assert_param(IS_DAC_ALIGN(DAC_Align));
+  assert_param(IS_DAC_DATA(Data1));
+  assert_param(IS_DAC_DATA(Data2));
+  
+  /* Calculate and set dual DAC data holding register value */
+  if (DAC_Align == DAC_Align_8b_R)
+  {
+    data = ((uint32_t)Data2 << 8) | Data1; 
+  }
+  else
+  {
+    data = ((uint32_t)Data2 << 16) | Data1;
+  }
+  
+  tmp = (uint32_t)DAC_BASE;
+  tmp += DHR12RD_OFFSET + DAC_Align;
+
+  /* Set the dual DAC selected data holding register */
+  *(__IO uint32_t *)tmp = data;
+}
+
+/**
+  * @brief  Returns the last data output value of the selected DAC channel.
+  * @param  DAC_Channel: the selected DAC channel. 
+  *   This parameter can be one of the following values:
+  *     @arg DAC_Channel_1: DAC Channel1 selected
+  *     @arg DAC_Channel_2: DAC Channel2 selected
+  * @retval The selected DAC channel data output value.
+  */
+uint16_t DAC_GetDataOutputValue(uint32_t DAC_Channel)
+{
+  __IO uint32_t tmp = 0;
+  
+  /* Check the parameters */
+  assert_param(IS_DAC_CHANNEL(DAC_Channel));
+  
+  tmp = (uint32_t) DAC_BASE ;
+  tmp += DOR_OFFSET + ((uint32_t)DAC_Channel >> 2);
+  
+  /* Returns the DAC channel data output register value */
+  return (uint16_t) (*(__IO uint32_t*) tmp);
+}
+
+#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
+/**
+  * @brief  Checks whether the specified DAC flag is set or not.
+  * @param  DAC_Channel: thee selected DAC channel. 
+  *   This parameter can be one of the following values:
+  *     @arg DAC_Channel_1: DAC Channel1 selected
+  *     @arg DAC_Channel_2: DAC Channel2 selected
+  * @param  DAC_FLAG: specifies the flag to check. 
+  *   This parameter can be only of the following value:
+  *     @arg DAC_FLAG_DMAUDR: DMA underrun flag                                                 
+  * @retval The new state of DAC_FLAG (SET or RESET).
+  */
+FlagStatus DAC_GetFlagStatus(uint32_t DAC_Channel, uint32_t DAC_FLAG)
+{
+  FlagStatus bitstatus = RESET;
+  /* Check the parameters */
+  assert_param(IS_DAC_CHANNEL(DAC_Channel));
+  assert_param(IS_DAC_FLAG(DAC_FLAG));
+
+  /* Check the status of the specified DAC flag */
+  if ((DAC->SR & (DAC_FLAG << DAC_Channel)) != (uint8_t)RESET)
+  {
+    /* DAC_FLAG is set */
+    bitstatus = SET;
+  }
+  else
+  {
+    /* DAC_FLAG is reset */
+    bitstatus = RESET;
+  }
+  /* Return the DAC_FLAG status */
+  return  bitstatus;
+}
+
+/**
+  * @brief  Clears the DAC channelx's pending flags.
+  * @param  DAC_Channel: the selected DAC channel. 
+  *   This parameter can be one of the following values:
+  *     @arg DAC_Channel_1: DAC Channel1 selected
+  *     @arg DAC_Channel_2: DAC Channel2 selected
+  * @param  DAC_FLAG: specifies the flag to clear. 
+  *   This parameter can be of the following value:
+  *     @arg DAC_FLAG_DMAUDR: DMA underrun flag                           
+  * @retval None
+  */
+void DAC_ClearFlag(uint32_t DAC_Channel, uint32_t DAC_FLAG)
+{
+  /* Check the parameters */
+  assert_param(IS_DAC_CHANNEL(DAC_Channel));
+  assert_param(IS_DAC_FLAG(DAC_FLAG));
+
+  /* Clear the selected DAC flags */
+  DAC->SR = (DAC_FLAG << DAC_Channel);
+}
+
+/**
+  * @brief  Checks whether the specified DAC interrupt has occurred or not.
+  * @param  DAC_Channel: the selected DAC channel. 
+  *   This parameter can be one of the following values:
+  *     @arg DAC_Channel_1: DAC Channel1 selected
+  *     @arg DAC_Channel_2: DAC Channel2 selected
+  * @param  DAC_IT: specifies the DAC interrupt source to check. 
+  *   This parameter can be the following values:
+  *     @arg DAC_IT_DMAUDR: DMA underrun interrupt mask                       
+  * @retval The new state of DAC_IT (SET or RESET).
+  */
+ITStatus DAC_GetITStatus(uint32_t DAC_Channel, uint32_t DAC_IT)
+{
+  ITStatus bitstatus = RESET;
+  uint32_t enablestatus = 0;
+  
+  /* Check the parameters */
+  assert_param(IS_DAC_CHANNEL(DAC_Channel));
+  assert_param(IS_DAC_IT(DAC_IT));
+
+  /* Get the DAC_IT enable bit status */
+  enablestatus = (DAC->CR & (DAC_IT << DAC_Channel)) ;
+  
+  /* Check the status of the specified DAC interrupt */
+  if (((DAC->SR & (DAC_IT << DAC_Channel)) != (uint32_t)RESET) && enablestatus)
+  {
+    /* DAC_IT is set */
+    bitstatus = SET;
+  }
+  else
+  {
+    /* DAC_IT is reset */
+    bitstatus = RESET;
+  }
+  /* Return the DAC_IT status */
+  return  bitstatus;
+}
+
+/**
+  * @brief  Clears the DAC channelx's interrupt pending bits.
+  * @param  DAC_Channel: the selected DAC channel. 
+  *   This parameter can be one of the following values:
+  *     @arg DAC_Channel_1: DAC Channel1 selected
+  *     @arg DAC_Channel_2: DAC Channel2 selected
+  * @param  DAC_IT: specifies the DAC interrupt pending bit to clear.
+  *   This parameter can be the following values:
+  *     @arg DAC_IT_DMAUDR: DMA underrun interrupt mask                         
+  * @retval None
+  */
+void DAC_ClearITPendingBit(uint32_t DAC_Channel, uint32_t DAC_IT)
+{
+  /* Check the parameters */
+  assert_param(IS_DAC_CHANNEL(DAC_Channel));
+  assert_param(IS_DAC_IT(DAC_IT)); 
+
+  /* Clear the selected DAC interrupt pending bits */
+  DAC->SR = (DAC_IT << DAC_Channel);
+}
+#endif
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/STM32_4路称重_Git提交精简工程/src/STM32F10x_FWLib/src/stm32f10x_dbgmcu.c b/STM32_4路称重_Git提交精简工程/src/STM32F10x_FWLib/src/stm32f10x_dbgmcu.c
new file mode 100755
index 0000000..d34307b
--- /dev/null
+++ b/STM32_4路称重_Git提交精简工程/src/STM32F10x_FWLib/src/stm32f10x_dbgmcu.c
@@ -0,0 +1,162 @@
+/**
+  ******************************************************************************
+  * @file    stm32f10x_dbgmcu.c
+  * @author  MCD Application Team
+  * @version V3.5.0
+  * @date    11-March-2011
+  * @brief   This file provides all the DBGMCU firmware functions.
+  ******************************************************************************
+  * @attention
+  *
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+  *
+  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x_dbgmcu.h"
+
+/** @addtogroup STM32F10x_StdPeriph_Driver
+  * @{
+  */
+
+/** @defgroup DBGMCU 
+  * @brief DBGMCU driver modules
+  * @{
+  */ 
+
+/** @defgroup DBGMCU_Private_TypesDefinitions
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup DBGMCU_Private_Defines
+  * @{
+  */
+
+#define IDCODE_DEVID_MASK    ((uint32_t)0x00000FFF)
+/**
+  * @}
+  */
+
+/** @defgroup DBGMCU_Private_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup DBGMCU_Private_Variables
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup DBGMCU_Private_FunctionPrototypes
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup DBGMCU_Private_Functions
+  * @{
+  */
+
+/**
+  * @brief  Returns the device revision identifier.
+  * @param  None
+  * @retval Device revision identifier
+  */
+uint32_t DBGMCU_GetREVID(void)
+{
+   return(DBGMCU->IDCODE >> 16);
+}
+
+/**
+  * @brief  Returns the device identifier.
+  * @param  None
+  * @retval Device identifier
+  */
+uint32_t DBGMCU_GetDEVID(void)
+{
+   return(DBGMCU->IDCODE & IDCODE_DEVID_MASK);
+}
+
+/**
+  * @brief  Configures the specified peripheral and low power mode behavior
+  *   when the MCU under Debug mode.
+  * @param  DBGMCU_Periph: specifies the peripheral and low power mode.
+  *   This parameter can be any combination of the following values:
+  *     @arg DBGMCU_SLEEP: Keep debugger connection during SLEEP mode              
+  *     @arg DBGMCU_STOP: Keep debugger connection during STOP mode               
+  *     @arg DBGMCU_STANDBY: Keep debugger connection during STANDBY mode            
+  *     @arg DBGMCU_IWDG_STOP: Debug IWDG stopped when Core is halted          
+  *     @arg DBGMCU_WWDG_STOP: Debug WWDG stopped when Core is halted          
+  *     @arg DBGMCU_TIM1_STOP: TIM1 counter stopped when Core is halted          
+  *     @arg DBGMCU_TIM2_STOP: TIM2 counter stopped when Core is halted          
+  *     @arg DBGMCU_TIM3_STOP: TIM3 counter stopped when Core is halted          
+  *     @arg DBGMCU_TIM4_STOP: TIM4 counter stopped when Core is halted          
+  *     @arg DBGMCU_CAN1_STOP: Debug CAN2 stopped when Core is halted           
+  *     @arg DBGMCU_I2C1_SMBUS_TIMEOUT: I2C1 SMBUS timeout mode stopped when Core is halted
+  *     @arg DBGMCU_I2C2_SMBUS_TIMEOUT: I2C2 SMBUS timeout mode stopped when Core is halted
+  *     @arg DBGMCU_TIM5_STOP: TIM5 counter stopped when Core is halted          
+  *     @arg DBGMCU_TIM6_STOP: TIM6 counter stopped when Core is halted          
+  *     @arg DBGMCU_TIM7_STOP: TIM7 counter stopped when Core is halted          
+  *     @arg DBGMCU_TIM8_STOP: TIM8 counter stopped when Core is halted
+  *     @arg DBGMCU_CAN2_STOP: Debug CAN2 stopped when Core is halted 
+  *     @arg DBGMCU_TIM15_STOP: TIM15 counter stopped when Core is halted
+  *     @arg DBGMCU_TIM16_STOP: TIM16 counter stopped when Core is halted
+  *     @arg DBGMCU_TIM17_STOP: TIM17 counter stopped when Core is halted                
+  *     @arg DBGMCU_TIM9_STOP: TIM9 counter stopped when Core is halted
+  *     @arg DBGMCU_TIM10_STOP: TIM10 counter stopped when Core is halted
+  *     @arg DBGMCU_TIM11_STOP: TIM11 counter stopped when Core is halted
+  *     @arg DBGMCU_TIM12_STOP: TIM12 counter stopped when Core is halted
+  *     @arg DBGMCU_TIM13_STOP: TIM13 counter stopped when Core is halted
+  *     @arg DBGMCU_TIM14_STOP: TIM14 counter stopped when Core is halted
+  * @param  NewState: new state of the specified peripheral in Debug mode.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void DBGMCU_Config(uint32_t DBGMCU_Periph, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_DBGMCU_PERIPH(DBGMCU_Periph));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    DBGMCU->CR |= DBGMCU_Periph;
+  }
+  else
+  {
+    DBGMCU->CR &= ~DBGMCU_Periph;
+  }
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/STM32_4路称重_Git提交精简工程/src/STM32F10x_FWLib/src/stm32f10x_dma.c b/STM32_4路称重_Git提交精简工程/src/STM32F10x_FWLib/src/stm32f10x_dma.c
new file mode 100755
index 0000000..0c86f90
--- /dev/null
+++ b/STM32_4路称重_Git提交精简工程/src/STM32F10x_FWLib/src/stm32f10x_dma.c
@@ -0,0 +1,714 @@
+/**
+  ******************************************************************************
+  * @file    stm32f10x_dma.c
+  * @author  MCD Application Team
+  * @version V3.5.0
+  * @date    11-March-2011
+  * @brief   This file provides all the DMA firmware functions.
+  ******************************************************************************
+  * @attention
+  *
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+  *
+  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x_dma.h"
+#include "stm32f10x_rcc.h"
+
+/** @addtogroup STM32F10x_StdPeriph_Driver
+  * @{
+  */
+
+/** @defgroup DMA 
+  * @brief DMA driver modules
+  * @{
+  */ 
+
+/** @defgroup DMA_Private_TypesDefinitions
+  * @{
+  */ 
+/**
+  * @}
+  */
+
+/** @defgroup DMA_Private_Defines
+  * @{
+  */
+
+
+/* DMA1 Channelx interrupt pending bit masks */
+#define DMA1_Channel1_IT_Mask    ((uint32_t)(DMA_ISR_GIF1 | DMA_ISR_TCIF1 | DMA_ISR_HTIF1 | DMA_ISR_TEIF1))
+#define DMA1_Channel2_IT_Mask    ((uint32_t)(DMA_ISR_GIF2 | DMA_ISR_TCIF2 | DMA_ISR_HTIF2 | DMA_ISR_TEIF2))
+#define DMA1_Channel3_IT_Mask    ((uint32_t)(DMA_ISR_GIF3 | DMA_ISR_TCIF3 | DMA_ISR_HTIF3 | DMA_ISR_TEIF3))
+#define DMA1_Channel4_IT_Mask    ((uint32_t)(DMA_ISR_GIF4 | DMA_ISR_TCIF4 | DMA_ISR_HTIF4 | DMA_ISR_TEIF4))
+#define DMA1_Channel5_IT_Mask    ((uint32_t)(DMA_ISR_GIF5 | DMA_ISR_TCIF5 | DMA_ISR_HTIF5 | DMA_ISR_TEIF5))
+#define DMA1_Channel6_IT_Mask    ((uint32_t)(DMA_ISR_GIF6 | DMA_ISR_TCIF6 | DMA_ISR_HTIF6 | DMA_ISR_TEIF6))
+#define DMA1_Channel7_IT_Mask    ((uint32_t)(DMA_ISR_GIF7 | DMA_ISR_TCIF7 | DMA_ISR_HTIF7 | DMA_ISR_TEIF7))
+
+/* DMA2 Channelx interrupt pending bit masks */
+#define DMA2_Channel1_IT_Mask    ((uint32_t)(DMA_ISR_GIF1 | DMA_ISR_TCIF1 | DMA_ISR_HTIF1 | DMA_ISR_TEIF1))
+#define DMA2_Channel2_IT_Mask    ((uint32_t)(DMA_ISR_GIF2 | DMA_ISR_TCIF2 | DMA_ISR_HTIF2 | DMA_ISR_TEIF2))
+#define DMA2_Channel3_IT_Mask    ((uint32_t)(DMA_ISR_GIF3 | DMA_ISR_TCIF3 | DMA_ISR_HTIF3 | DMA_ISR_TEIF3))
+#define DMA2_Channel4_IT_Mask    ((uint32_t)(DMA_ISR_GIF4 | DMA_ISR_TCIF4 | DMA_ISR_HTIF4 | DMA_ISR_TEIF4))
+#define DMA2_Channel5_IT_Mask    ((uint32_t)(DMA_ISR_GIF5 | DMA_ISR_TCIF5 | DMA_ISR_HTIF5 | DMA_ISR_TEIF5))
+
+/* DMA2 FLAG mask */
+#define FLAG_Mask                ((uint32_t)0x10000000)
+
+/* DMA registers Masks */
+#define CCR_CLEAR_Mask           ((uint32_t)0xFFFF800F)
+
+/**
+  * @}
+  */
+
+/** @defgroup DMA_Private_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup DMA_Private_Variables
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup DMA_Private_FunctionPrototypes
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup DMA_Private_Functions
+  * @{
+  */
+
+/**
+  * @brief  Deinitializes the DMAy Channelx registers to their default reset
+  *         values.
+  * @param  DMAy_Channelx: where y can be 1 or 2 to select the DMA and
+  *   x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel.
+  * @retval None
+  */
+void DMA_DeInit(DMA_Channel_TypeDef* DMAy_Channelx)
+{
+  /* Check the parameters */
+  assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));
+  
+  /* Disable the selected DMAy Channelx */
+  DMAy_Channelx->CCR &= (uint16_t)(~DMA_CCR1_EN);
+  
+  /* Reset DMAy Channelx control register */
+  DMAy_Channelx->CCR  = 0;
+  
+  /* Reset DMAy Channelx remaining bytes register */
+  DMAy_Channelx->CNDTR = 0;
+  
+  /* Reset DMAy Channelx peripheral address register */
+  DMAy_Channelx->CPAR  = 0;
+  
+  /* Reset DMAy Channelx memory address register */
+  DMAy_Channelx->CMAR = 0;
+  
+  if (DMAy_Channelx == DMA1_Channel1)
+  {
+    /* Reset interrupt pending bits for DMA1 Channel1 */
+    DMA1->IFCR |= DMA1_Channel1_IT_Mask;
+  }
+  else if (DMAy_Channelx == DMA1_Channel2)
+  {
+    /* Reset interrupt pending bits for DMA1 Channel2 */
+    DMA1->IFCR |= DMA1_Channel2_IT_Mask;
+  }
+  else if (DMAy_Channelx == DMA1_Channel3)
+  {
+    /* Reset interrupt pending bits for DMA1 Channel3 */
+    DMA1->IFCR |= DMA1_Channel3_IT_Mask;
+  }
+  else if (DMAy_Channelx == DMA1_Channel4)
+  {
+    /* Reset interrupt pending bits for DMA1 Channel4 */
+    DMA1->IFCR |= DMA1_Channel4_IT_Mask;
+  }
+  else if (DMAy_Channelx == DMA1_Channel5)
+  {
+    /* Reset interrupt pending bits for DMA1 Channel5 */
+    DMA1->IFCR |= DMA1_Channel5_IT_Mask;
+  }
+  else if (DMAy_Channelx == DMA1_Channel6)
+  {
+    /* Reset interrupt pending bits for DMA1 Channel6 */
+    DMA1->IFCR |= DMA1_Channel6_IT_Mask;
+  }
+  else if (DMAy_Channelx == DMA1_Channel7)
+  {
+    /* Reset interrupt pending bits for DMA1 Channel7 */
+    DMA1->IFCR |= DMA1_Channel7_IT_Mask;
+  }
+  else if (DMAy_Channelx == DMA2_Channel1)
+  {
+    /* Reset interrupt pending bits for DMA2 Channel1 */
+    DMA2->IFCR |= DMA2_Channel1_IT_Mask;
+  }
+  else if (DMAy_Channelx == DMA2_Channel2)
+  {
+    /* Reset interrupt pending bits for DMA2 Channel2 */
+    DMA2->IFCR |= DMA2_Channel2_IT_Mask;
+  }
+  else if (DMAy_Channelx == DMA2_Channel3)
+  {
+    /* Reset interrupt pending bits for DMA2 Channel3 */
+    DMA2->IFCR |= DMA2_Channel3_IT_Mask;
+  }
+  else if (DMAy_Channelx == DMA2_Channel4)
+  {
+    /* Reset interrupt pending bits for DMA2 Channel4 */
+    DMA2->IFCR |= DMA2_Channel4_IT_Mask;
+  }
+  else
+  { 
+    if (DMAy_Channelx == DMA2_Channel5)
+    {
+      /* Reset interrupt pending bits for DMA2 Channel5 */
+      DMA2->IFCR |= DMA2_Channel5_IT_Mask;
+    }
+  }
+}
+
+/**
+  * @brief  Initializes the DMAy Channelx according to the specified
+  *         parameters in the DMA_InitStruct.
+  * @param  DMAy_Channelx: where y can be 1 or 2 to select the DMA and 
+  *   x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel.
+  * @param  DMA_InitStruct: pointer to a DMA_InitTypeDef structure that
+  *         contains the configuration information for the specified DMA Channel.
+  * @retval None
+  */
+void DMA_Init(DMA_Channel_TypeDef* DMAy_Channelx, DMA_InitTypeDef* DMA_InitStruct)
+{
+  uint32_t tmpreg = 0;
+
+  /* Check the parameters */
+  assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));
+  assert_param(IS_DMA_DIR(DMA_InitStruct->DMA_DIR));
+  assert_param(IS_DMA_BUFFER_SIZE(DMA_InitStruct->DMA_BufferSize));
+  assert_param(IS_DMA_PERIPHERAL_INC_STATE(DMA_InitStruct->DMA_PeripheralInc));
+  assert_param(IS_DMA_MEMORY_INC_STATE(DMA_InitStruct->DMA_MemoryInc));   
+  assert_param(IS_DMA_PERIPHERAL_DATA_SIZE(DMA_InitStruct->DMA_PeripheralDataSize));
+  assert_param(IS_DMA_MEMORY_DATA_SIZE(DMA_InitStruct->DMA_MemoryDataSize));
+  assert_param(IS_DMA_MODE(DMA_InitStruct->DMA_Mode));
+  assert_param(IS_DMA_PRIORITY(DMA_InitStruct->DMA_Priority));
+  assert_param(IS_DMA_M2M_STATE(DMA_InitStruct->DMA_M2M));
+
+/*--------------------------- DMAy Channelx CCR Configuration -----------------*/
+  /* Get the DMAy_Channelx CCR value */
+  tmpreg = DMAy_Channelx->CCR;
+  /* Clear MEM2MEM, PL, MSIZE, PSIZE, MINC, PINC, CIRC and DIR bits */
+  tmpreg &= CCR_CLEAR_Mask;
+  /* Configure DMAy Channelx: data transfer, data size, priority level and mode */
+  /* Set DIR bit according to DMA_DIR value */
+  /* Set CIRC bit according to DMA_Mode value */
+  /* Set PINC bit according to DMA_PeripheralInc value */
+  /* Set MINC bit according to DMA_MemoryInc value */
+  /* Set PSIZE bits according to DMA_PeripheralDataSize value */
+  /* Set MSIZE bits according to DMA_MemoryDataSize value */
+  /* Set PL bits according to DMA_Priority value */
+  /* Set the MEM2MEM bit according to DMA_M2M value */
+  tmpreg |= DMA_InitStruct->DMA_DIR | DMA_InitStruct->DMA_Mode |
+            DMA_InitStruct->DMA_PeripheralInc | DMA_InitStruct->DMA_MemoryInc |
+            DMA_InitStruct->DMA_PeripheralDataSize | DMA_InitStruct->DMA_MemoryDataSize |
+            DMA_InitStruct->DMA_Priority | DMA_InitStruct->DMA_M2M;
+
+  /* Write to DMAy Channelx CCR */
+  DMAy_Channelx->CCR = tmpreg;
+
+/*--------------------------- DMAy Channelx CNDTR Configuration ---------------*/
+  /* Write to DMAy Channelx CNDTR */
+  DMAy_Channelx->CNDTR = DMA_InitStruct->DMA_BufferSize;
+
+/*--------------------------- DMAy Channelx CPAR Configuration ----------------*/
+  /* Write to DMAy Channelx CPAR */
+  DMAy_Channelx->CPAR = DMA_InitStruct->DMA_PeripheralBaseAddr;
+
+/*--------------------------- DMAy Channelx CMAR Configuration ----------------*/
+  /* Write to DMAy Channelx CMAR */
+  DMAy_Channelx->CMAR = DMA_InitStruct->DMA_MemoryBaseAddr;
+}
+
+/**
+  * @brief  Fills each DMA_InitStruct member with its default value.
+  * @param  DMA_InitStruct : pointer to a DMA_InitTypeDef structure which will
+  *         be initialized.
+  * @retval None
+  */
+void DMA_StructInit(DMA_InitTypeDef* DMA_InitStruct)
+{
+/*-------------- Reset DMA init structure parameters values ------------------*/
+  /* Initialize the DMA_PeripheralBaseAddr member */
+  DMA_InitStruct->DMA_PeripheralBaseAddr = 0;
+  /* Initialize the DMA_MemoryBaseAddr member */
+  DMA_InitStruct->DMA_MemoryBaseAddr = 0;
+  /* Initialize the DMA_DIR member */
+  DMA_InitStruct->DMA_DIR = DMA_DIR_PeripheralSRC;
+  /* Initialize the DMA_BufferSize member */
+  DMA_InitStruct->DMA_BufferSize = 0;
+  /* Initialize the DMA_PeripheralInc member */
+  DMA_InitStruct->DMA_PeripheralInc = DMA_PeripheralInc_Disable;
+  /* Initialize the DMA_MemoryInc member */
+  DMA_InitStruct->DMA_MemoryInc = DMA_MemoryInc_Disable;
+  /* Initialize the DMA_PeripheralDataSize member */
+  DMA_InitStruct->DMA_PeripheralDataSize = DMA_PeripheralDataSize_Byte;
+  /* Initialize the DMA_MemoryDataSize member */
+  DMA_InitStruct->DMA_MemoryDataSize = DMA_MemoryDataSize_Byte;
+  /* Initialize the DMA_Mode member */
+  DMA_InitStruct->DMA_Mode = DMA_Mode_Normal;
+  /* Initialize the DMA_Priority member */
+  DMA_InitStruct->DMA_Priority = DMA_Priority_Low;
+  /* Initialize the DMA_M2M member */
+  DMA_InitStruct->DMA_M2M = DMA_M2M_Disable;
+}
+
+/**
+  * @brief  Enables or disables the specified DMAy Channelx.
+  * @param  DMAy_Channelx: where y can be 1 or 2 to select the DMA and 
+  *   x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel.
+  * @param  NewState: new state of the DMAy Channelx. 
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void DMA_Cmd(DMA_Channel_TypeDef* DMAy_Channelx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Enable the selected DMAy Channelx */
+    DMAy_Channelx->CCR |= DMA_CCR1_EN;
+  }
+  else
+  {
+    /* Disable the selected DMAy Channelx */
+    DMAy_Channelx->CCR &= (uint16_t)(~DMA_CCR1_EN);
+  }
+}
+
+/**
+  * @brief  Enables or disables the specified DMAy Channelx interrupts.
+  * @param  DMAy_Channelx: where y can be 1 or 2 to select the DMA and 
+  *   x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel.
+  * @param  DMA_IT: specifies the DMA interrupts sources to be enabled
+  *   or disabled. 
+  *   This parameter can be any combination of the following values:
+  *     @arg DMA_IT_TC:  Transfer complete interrupt mask
+  *     @arg DMA_IT_HT:  Half transfer interrupt mask
+  *     @arg DMA_IT_TE:  Transfer error interrupt mask
+  * @param  NewState: new state of the specified DMA interrupts.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void DMA_ITConfig(DMA_Channel_TypeDef* DMAy_Channelx, uint32_t DMA_IT, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));
+  assert_param(IS_DMA_CONFIG_IT(DMA_IT));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  if (NewState != DISABLE)
+  {
+    /* Enable the selected DMA interrupts */
+    DMAy_Channelx->CCR |= DMA_IT;
+  }
+  else
+  {
+    /* Disable the selected DMA interrupts */
+    DMAy_Channelx->CCR &= ~DMA_IT;
+  }
+}
+
+/**
+  * @brief  Sets the number of data units in the current DMAy Channelx transfer.
+  * @param  DMAy_Channelx: where y can be 1 or 2 to select the DMA and 
+  *         x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel.
+  * @param  DataNumber: The number of data units in the current DMAy Channelx
+  *         transfer.   
+  * @note   This function can only be used when the DMAy_Channelx is disabled.                 
+  * @retval None.
+  */
+void DMA_SetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx, uint16_t DataNumber)
+{
+  /* Check the parameters */
+  assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));
+  
+/*--------------------------- DMAy Channelx CNDTR Configuration ---------------*/
+  /* Write to DMAy Channelx CNDTR */
+  DMAy_Channelx->CNDTR = DataNumber;  
+}
+
+/**
+  * @brief  Returns the number of remaining data units in the current
+  *         DMAy Channelx transfer.
+  * @param  DMAy_Channelx: where y can be 1 or 2 to select the DMA and 
+  *   x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel.
+  * @retval The number of remaining data units in the current DMAy Channelx
+  *         transfer.
+  */
+uint16_t DMA_GetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx)
+{
+  /* Check the parameters */
+  assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));
+  /* Return the number of remaining data units for DMAy Channelx */
+  return ((uint16_t)(DMAy_Channelx->CNDTR));
+}
+
+/**
+  * @brief  Checks whether the specified DMAy Channelx flag is set or not.
+  * @param  DMAy_FLAG: specifies the flag to check.
+  *   This parameter can be one of the following values:
+  *     @arg DMA1_FLAG_GL1: DMA1 Channel1 global flag.
+  *     @arg DMA1_FLAG_TC1: DMA1 Channel1 transfer complete flag.
+  *     @arg DMA1_FLAG_HT1: DMA1 Channel1 half transfer flag.
+  *     @arg DMA1_FLAG_TE1: DMA1 Channel1 transfer error flag.
+  *     @arg DMA1_FLAG_GL2: DMA1 Channel2 global flag.
+  *     @arg DMA1_FLAG_TC2: DMA1 Channel2 transfer complete flag.
+  *     @arg DMA1_FLAG_HT2: DMA1 Channel2 half transfer flag.
+  *     @arg DMA1_FLAG_TE2: DMA1 Channel2 transfer error flag.
+  *     @arg DMA1_FLAG_GL3: DMA1 Channel3 global flag.
+  *     @arg DMA1_FLAG_TC3: DMA1 Channel3 transfer complete flag.
+  *     @arg DMA1_FLAG_HT3: DMA1 Channel3 half transfer flag.
+  *     @arg DMA1_FLAG_TE3: DMA1 Channel3 transfer error flag.
+  *     @arg DMA1_FLAG_GL4: DMA1 Channel4 global flag.
+  *     @arg DMA1_FLAG_TC4: DMA1 Channel4 transfer complete flag.
+  *     @arg DMA1_FLAG_HT4: DMA1 Channel4 half transfer flag.
+  *     @arg DMA1_FLAG_TE4: DMA1 Channel4 transfer error flag.
+  *     @arg DMA1_FLAG_GL5: DMA1 Channel5 global flag.
+  *     @arg DMA1_FLAG_TC5: DMA1 Channel5 transfer complete flag.
+  *     @arg DMA1_FLAG_HT5: DMA1 Channel5 half transfer flag.
+  *     @arg DMA1_FLAG_TE5: DMA1 Channel5 transfer error flag.
+  *     @arg DMA1_FLAG_GL6: DMA1 Channel6 global flag.
+  *     @arg DMA1_FLAG_TC6: DMA1 Channel6 transfer complete flag.
+  *     @arg DMA1_FLAG_HT6: DMA1 Channel6 half transfer flag.
+  *     @arg DMA1_FLAG_TE6: DMA1 Channel6 transfer error flag.
+  *     @arg DMA1_FLAG_GL7: DMA1 Channel7 global flag.
+  *     @arg DMA1_FLAG_TC7: DMA1 Channel7 transfer complete flag.
+  *     @arg DMA1_FLAG_HT7: DMA1 Channel7 half transfer flag.
+  *     @arg DMA1_FLAG_TE7: DMA1 Channel7 transfer error flag.
+  *     @arg DMA2_FLAG_GL1: DMA2 Channel1 global flag.
+  *     @arg DMA2_FLAG_TC1: DMA2 Channel1 transfer complete flag.
+  *     @arg DMA2_FLAG_HT1: DMA2 Channel1 half transfer flag.
+  *     @arg DMA2_FLAG_TE1: DMA2 Channel1 transfer error flag.
+  *     @arg DMA2_FLAG_GL2: DMA2 Channel2 global flag.
+  *     @arg DMA2_FLAG_TC2: DMA2 Channel2 transfer complete flag.
+  *     @arg DMA2_FLAG_HT2: DMA2 Channel2 half transfer flag.
+  *     @arg DMA2_FLAG_TE2: DMA2 Channel2 transfer error flag.
+  *     @arg DMA2_FLAG_GL3: DMA2 Channel3 global flag.
+  *     @arg DMA2_FLAG_TC3: DMA2 Channel3 transfer complete flag.
+  *     @arg DMA2_FLAG_HT3: DMA2 Channel3 half transfer flag.
+  *     @arg DMA2_FLAG_TE3: DMA2 Channel3 transfer error flag.
+  *     @arg DMA2_FLAG_GL4: DMA2 Channel4 global flag.
+  *     @arg DMA2_FLAG_TC4: DMA2 Channel4 transfer complete flag.
+  *     @arg DMA2_FLAG_HT4: DMA2 Channel4 half transfer flag.
+  *     @arg DMA2_FLAG_TE4: DMA2 Channel4 transfer error flag.
+  *     @arg DMA2_FLAG_GL5: DMA2 Channel5 global flag.
+  *     @arg DMA2_FLAG_TC5: DMA2 Channel5 transfer complete flag.
+  *     @arg DMA2_FLAG_HT5: DMA2 Channel5 half transfer flag.
+  *     @arg DMA2_FLAG_TE5: DMA2 Channel5 transfer error flag.
+  * @retval The new state of DMAy_FLAG (SET or RESET).
+  */
+FlagStatus DMA_GetFlagStatus(uint32_t DMAy_FLAG)
+{
+  FlagStatus bitstatus = RESET;
+  uint32_t tmpreg = 0;
+  
+  /* Check the parameters */
+  assert_param(IS_DMA_GET_FLAG(DMAy_FLAG));
+
+  /* Calculate the used DMAy */
+  if ((DMAy_FLAG & FLAG_Mask) != (uint32_t)RESET)
+  {
+    /* Get DMA2 ISR register value */
+    tmpreg = DMA2->ISR ;
+  }
+  else
+  {
+    /* Get DMA1 ISR register value */
+    tmpreg = DMA1->ISR ;
+  }
+
+  /* Check the status of the specified DMAy flag */
+  if ((tmpreg & DMAy_FLAG) != (uint32_t)RESET)
+  {
+    /* DMAy_FLAG is set */
+    bitstatus = SET;
+  }
+  else
+  {
+    /* DMAy_FLAG is reset */
+    bitstatus = RESET;
+  }
+  
+  /* Return the DMAy_FLAG status */
+  return  bitstatus;
+}
+
+/**
+  * @brief  Clears the DMAy Channelx's pending flags.
+  * @param  DMAy_FLAG: specifies the flag to clear.
+  *   This parameter can be any combination (for the same DMA) of the following values:
+  *     @arg DMA1_FLAG_GL1: DMA1 Channel1 global flag.
+  *     @arg DMA1_FLAG_TC1: DMA1 Channel1 transfer complete flag.
+  *     @arg DMA1_FLAG_HT1: DMA1 Channel1 half transfer flag.
+  *     @arg DMA1_FLAG_TE1: DMA1 Channel1 transfer error flag.
+  *     @arg DMA1_FLAG_GL2: DMA1 Channel2 global flag.
+  *     @arg DMA1_FLAG_TC2: DMA1 Channel2 transfer complete flag.
+  *     @arg DMA1_FLAG_HT2: DMA1 Channel2 half transfer flag.
+  *     @arg DMA1_FLAG_TE2: DMA1 Channel2 transfer error flag.
+  *     @arg DMA1_FLAG_GL3: DMA1 Channel3 global flag.
+  *     @arg DMA1_FLAG_TC3: DMA1 Channel3 transfer complete flag.
+  *     @arg DMA1_FLAG_HT3: DMA1 Channel3 half transfer flag.
+  *     @arg DMA1_FLAG_TE3: DMA1 Channel3 transfer error flag.
+  *     @arg DMA1_FLAG_GL4: DMA1 Channel4 global flag.
+  *     @arg DMA1_FLAG_TC4: DMA1 Channel4 transfer complete flag.
+  *     @arg DMA1_FLAG_HT4: DMA1 Channel4 half transfer flag.
+  *     @arg DMA1_FLAG_TE4: DMA1 Channel4 transfer error flag.
+  *     @arg DMA1_FLAG_GL5: DMA1 Channel5 global flag.
+  *     @arg DMA1_FLAG_TC5: DMA1 Channel5 transfer complete flag.
+  *     @arg DMA1_FLAG_HT5: DMA1 Channel5 half transfer flag.
+  *     @arg DMA1_FLAG_TE5: DMA1 Channel5 transfer error flag.
+  *     @arg DMA1_FLAG_GL6: DMA1 Channel6 global flag.
+  *     @arg DMA1_FLAG_TC6: DMA1 Channel6 transfer complete flag.
+  *     @arg DMA1_FLAG_HT6: DMA1 Channel6 half transfer flag.
+  *     @arg DMA1_FLAG_TE6: DMA1 Channel6 transfer error flag.
+  *     @arg DMA1_FLAG_GL7: DMA1 Channel7 global flag.
+  *     @arg DMA1_FLAG_TC7: DMA1 Channel7 transfer complete flag.
+  *     @arg DMA1_FLAG_HT7: DMA1 Channel7 half transfer flag.
+  *     @arg DMA1_FLAG_TE7: DMA1 Channel7 transfer error flag.
+  *     @arg DMA2_FLAG_GL1: DMA2 Channel1 global flag.
+  *     @arg DMA2_FLAG_TC1: DMA2 Channel1 transfer complete flag.
+  *     @arg DMA2_FLAG_HT1: DMA2 Channel1 half transfer flag.
+  *     @arg DMA2_FLAG_TE1: DMA2 Channel1 transfer error flag.
+  *     @arg DMA2_FLAG_GL2: DMA2 Channel2 global flag.
+  *     @arg DMA2_FLAG_TC2: DMA2 Channel2 transfer complete flag.
+  *     @arg DMA2_FLAG_HT2: DMA2 Channel2 half transfer flag.
+  *     @arg DMA2_FLAG_TE2: DMA2 Channel2 transfer error flag.
+  *     @arg DMA2_FLAG_GL3: DMA2 Channel3 global flag.
+  *     @arg DMA2_FLAG_TC3: DMA2 Channel3 transfer complete flag.
+  *     @arg DMA2_FLAG_HT3: DMA2 Channel3 half transfer flag.
+  *     @arg DMA2_FLAG_TE3: DMA2 Channel3 transfer error flag.
+  *     @arg DMA2_FLAG_GL4: DMA2 Channel4 global flag.
+  *     @arg DMA2_FLAG_TC4: DMA2 Channel4 transfer complete flag.
+  *     @arg DMA2_FLAG_HT4: DMA2 Channel4 half transfer flag.
+  *     @arg DMA2_FLAG_TE4: DMA2 Channel4 transfer error flag.
+  *     @arg DMA2_FLAG_GL5: DMA2 Channel5 global flag.
+  *     @arg DMA2_FLAG_TC5: DMA2 Channel5 transfer complete flag.
+  *     @arg DMA2_FLAG_HT5: DMA2 Channel5 half transfer flag.
+  *     @arg DMA2_FLAG_TE5: DMA2 Channel5 transfer error flag.
+  * @retval None
+  */
+void DMA_ClearFlag(uint32_t DMAy_FLAG)
+{
+  /* Check the parameters */
+  assert_param(IS_DMA_CLEAR_FLAG(DMAy_FLAG));
+
+  /* Calculate the used DMAy */
+  if ((DMAy_FLAG & FLAG_Mask) != (uint32_t)RESET)
+  {
+    /* Clear the selected DMAy flags */
+    DMA2->IFCR = DMAy_FLAG;
+  }
+  else
+  {
+    /* Clear the selected DMAy flags */
+    DMA1->IFCR = DMAy_FLAG;
+  }
+}
+
+/**
+  * @brief  Checks whether the specified DMAy Channelx interrupt has occurred or not.
+  * @param  DMAy_IT: specifies the DMAy interrupt source to check. 
+  *   This parameter can be one of the following values:
+  *     @arg DMA1_IT_GL1: DMA1 Channel1 global interrupt.
+  *     @arg DMA1_IT_TC1: DMA1 Channel1 transfer complete interrupt.
+  *     @arg DMA1_IT_HT1: DMA1 Channel1 half transfer interrupt.
+  *     @arg DMA1_IT_TE1: DMA1 Channel1 transfer error interrupt.
+  *     @arg DMA1_IT_GL2: DMA1 Channel2 global interrupt.
+  *     @arg DMA1_IT_TC2: DMA1 Channel2 transfer complete interrupt.
+  *     @arg DMA1_IT_HT2: DMA1 Channel2 half transfer interrupt.
+  *     @arg DMA1_IT_TE2: DMA1 Channel2 transfer error interrupt.
+  *     @arg DMA1_IT_GL3: DMA1 Channel3 global interrupt.
+  *     @arg DMA1_IT_TC3: DMA1 Channel3 transfer complete interrupt.
+  *     @arg DMA1_IT_HT3: DMA1 Channel3 half transfer interrupt.
+  *     @arg DMA1_IT_TE3: DMA1 Channel3 transfer error interrupt.
+  *     @arg DMA1_IT_GL4: DMA1 Channel4 global interrupt.
+  *     @arg DMA1_IT_TC4: DMA1 Channel4 transfer complete interrupt.
+  *     @arg DMA1_IT_HT4: DMA1 Channel4 half transfer interrupt.
+  *     @arg DMA1_IT_TE4: DMA1 Channel4 transfer error interrupt.
+  *     @arg DMA1_IT_GL5: DMA1 Channel5 global interrupt.
+  *     @arg DMA1_IT_TC5: DMA1 Channel5 transfer complete interrupt.
+  *     @arg DMA1_IT_HT5: DMA1 Channel5 half transfer interrupt.
+  *     @arg DMA1_IT_TE5: DMA1 Channel5 transfer error interrupt.
+  *     @arg DMA1_IT_GL6: DMA1 Channel6 global interrupt.
+  *     @arg DMA1_IT_TC6: DMA1 Channel6 transfer complete interrupt.
+  *     @arg DMA1_IT_HT6: DMA1 Channel6 half transfer interrupt.
+  *     @arg DMA1_IT_TE6: DMA1 Channel6 transfer error interrupt.
+  *     @arg DMA1_IT_GL7: DMA1 Channel7 global interrupt.
+  *     @arg DMA1_IT_TC7: DMA1 Channel7 transfer complete interrupt.
+  *     @arg DMA1_IT_HT7: DMA1 Channel7 half transfer interrupt.
+  *     @arg DMA1_IT_TE7: DMA1 Channel7 transfer error interrupt.
+  *     @arg DMA2_IT_GL1: DMA2 Channel1 global interrupt.
+  *     @arg DMA2_IT_TC1: DMA2 Channel1 transfer complete interrupt.
+  *     @arg DMA2_IT_HT1: DMA2 Channel1 half transfer interrupt.
+  *     @arg DMA2_IT_TE1: DMA2 Channel1 transfer error interrupt.
+  *     @arg DMA2_IT_GL2: DMA2 Channel2 global interrupt.
+  *     @arg DMA2_IT_TC2: DMA2 Channel2 transfer complete interrupt.
+  *     @arg DMA2_IT_HT2: DMA2 Channel2 half transfer interrupt.
+  *     @arg DMA2_IT_TE2: DMA2 Channel2 transfer error interrupt.
+  *     @arg DMA2_IT_GL3: DMA2 Channel3 global interrupt.
+  *     @arg DMA2_IT_TC3: DMA2 Channel3 transfer complete interrupt.
+  *     @arg DMA2_IT_HT3: DMA2 Channel3 half transfer interrupt.
+  *     @arg DMA2_IT_TE3: DMA2 Channel3 transfer error interrupt.
+  *     @arg DMA2_IT_GL4: DMA2 Channel4 global interrupt.
+  *     @arg DMA2_IT_TC4: DMA2 Channel4 transfer complete interrupt.
+  *     @arg DMA2_IT_HT4: DMA2 Channel4 half transfer interrupt.
+  *     @arg DMA2_IT_TE4: DMA2 Channel4 transfer error interrupt.
+  *     @arg DMA2_IT_GL5: DMA2 Channel5 global interrupt.
+  *     @arg DMA2_IT_TC5: DMA2 Channel5 transfer complete interrupt.
+  *     @arg DMA2_IT_HT5: DMA2 Channel5 half transfer interrupt.
+  *     @arg DMA2_IT_TE5: DMA2 Channel5 transfer error interrupt.
+  * @retval The new state of DMAy_IT (SET or RESET).
+  */
+ITStatus DMA_GetITStatus(uint32_t DMAy_IT)
+{
+  ITStatus bitstatus = RESET;
+  uint32_t tmpreg = 0;
+
+  /* Check the parameters */
+  assert_param(IS_DMA_GET_IT(DMAy_IT));
+
+  /* Calculate the used DMA */
+  if ((DMAy_IT & FLAG_Mask) != (uint32_t)RESET)
+  {
+    /* Get DMA2 ISR register value */
+    tmpreg = DMA2->ISR;
+  }
+  else
+  {
+    /* Get DMA1 ISR register value */
+    tmpreg = DMA1->ISR;
+  }
+
+  /* Check the status of the specified DMAy interrupt */
+  if ((tmpreg & DMAy_IT) != (uint32_t)RESET)
+  {
+    /* DMAy_IT is set */
+    bitstatus = SET;
+  }
+  else
+  {
+    /* DMAy_IT is reset */
+    bitstatus = RESET;
+  }
+  /* Return the DMA_IT status */
+  return  bitstatus;
+}
+
+/**
+  * @brief  Clears the DMAy Channelx's interrupt pending bits.
+  * @param  DMAy_IT: specifies the DMAy interrupt pending bit to clear.
+  *   This parameter can be any combination (for the same DMA) of the following values:
+  *     @arg DMA1_IT_GL1: DMA1 Channel1 global interrupt.
+  *     @arg DMA1_IT_TC1: DMA1 Channel1 transfer complete interrupt.
+  *     @arg DMA1_IT_HT1: DMA1 Channel1 half transfer interrupt.
+  *     @arg DMA1_IT_TE1: DMA1 Channel1 transfer error interrupt.
+  *     @arg DMA1_IT_GL2: DMA1 Channel2 global interrupt.
+  *     @arg DMA1_IT_TC2: DMA1 Channel2 transfer complete interrupt.
+  *     @arg DMA1_IT_HT2: DMA1 Channel2 half transfer interrupt.
+  *     @arg DMA1_IT_TE2: DMA1 Channel2 transfer error interrupt.
+  *     @arg DMA1_IT_GL3: DMA1 Channel3 global interrupt.
+  *     @arg DMA1_IT_TC3: DMA1 Channel3 transfer complete interrupt.
+  *     @arg DMA1_IT_HT3: DMA1 Channel3 half transfer interrupt.
+  *     @arg DMA1_IT_TE3: DMA1 Channel3 transfer error interrupt.
+  *     @arg DMA1_IT_GL4: DMA1 Channel4 global interrupt.
+  *     @arg DMA1_IT_TC4: DMA1 Channel4 transfer complete interrupt.
+  *     @arg DMA1_IT_HT4: DMA1 Channel4 half transfer interrupt.
+  *     @arg DMA1_IT_TE4: DMA1 Channel4 transfer error interrupt.
+  *     @arg DMA1_IT_GL5: DMA1 Channel5 global interrupt.
+  *     @arg DMA1_IT_TC5: DMA1 Channel5 transfer complete interrupt.
+  *     @arg DMA1_IT_HT5: DMA1 Channel5 half transfer interrupt.
+  *     @arg DMA1_IT_TE5: DMA1 Channel5 transfer error interrupt.
+  *     @arg DMA1_IT_GL6: DMA1 Channel6 global interrupt.
+  *     @arg DMA1_IT_TC6: DMA1 Channel6 transfer complete interrupt.
+  *     @arg DMA1_IT_HT6: DMA1 Channel6 half transfer interrupt.
+  *     @arg DMA1_IT_TE6: DMA1 Channel6 transfer error interrupt.
+  *     @arg DMA1_IT_GL7: DMA1 Channel7 global interrupt.
+  *     @arg DMA1_IT_TC7: DMA1 Channel7 transfer complete interrupt.
+  *     @arg DMA1_IT_HT7: DMA1 Channel7 half transfer interrupt.
+  *     @arg DMA1_IT_TE7: DMA1 Channel7 transfer error interrupt.
+  *     @arg DMA2_IT_GL1: DMA2 Channel1 global interrupt.
+  *     @arg DMA2_IT_TC1: DMA2 Channel1 transfer complete interrupt.
+  *     @arg DMA2_IT_HT1: DMA2 Channel1 half transfer interrupt.
+  *     @arg DMA2_IT_TE1: DMA2 Channel1 transfer error interrupt.
+  *     @arg DMA2_IT_GL2: DMA2 Channel2 global interrupt.
+  *     @arg DMA2_IT_TC2: DMA2 Channel2 transfer complete interrupt.
+  *     @arg DMA2_IT_HT2: DMA2 Channel2 half transfer interrupt.
+  *     @arg DMA2_IT_TE2: DMA2 Channel2 transfer error interrupt.
+  *     @arg DMA2_IT_GL3: DMA2 Channel3 global interrupt.
+  *     @arg DMA2_IT_TC3: DMA2 Channel3 transfer complete interrupt.
+  *     @arg DMA2_IT_HT3: DMA2 Channel3 half transfer interrupt.
+  *     @arg DMA2_IT_TE3: DMA2 Channel3 transfer error interrupt.
+  *     @arg DMA2_IT_GL4: DMA2 Channel4 global interrupt.
+  *     @arg DMA2_IT_TC4: DMA2 Channel4 transfer complete interrupt.
+  *     @arg DMA2_IT_HT4: DMA2 Channel4 half transfer interrupt.
+  *     @arg DMA2_IT_TE4: DMA2 Channel4 transfer error interrupt.
+  *     @arg DMA2_IT_GL5: DMA2 Channel5 global interrupt.
+  *     @arg DMA2_IT_TC5: DMA2 Channel5 transfer complete interrupt.
+  *     @arg DMA2_IT_HT5: DMA2 Channel5 half transfer interrupt.
+  *     @arg DMA2_IT_TE5: DMA2 Channel5 transfer error interrupt.
+  * @retval None
+  */
+void DMA_ClearITPendingBit(uint32_t DMAy_IT)
+{
+  /* Check the parameters */
+  assert_param(IS_DMA_CLEAR_IT(DMAy_IT));
+
+  /* Calculate the used DMAy */
+  if ((DMAy_IT & FLAG_Mask) != (uint32_t)RESET)
+  {
+    /* Clear the selected DMAy interrupt pending bits */
+    DMA2->IFCR = DMAy_IT;
+  }
+  else
+  {
+    /* Clear the selected DMAy interrupt pending bits */
+    DMA1->IFCR = DMAy_IT;
+  }
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/STM32_4路称重_Git提交精简工程/src/STM32F10x_FWLib/src/stm32f10x_exti.c b/STM32_4路称重_Git提交精简工程/src/STM32F10x_FWLib/src/stm32f10x_exti.c
new file mode 100755
index 0000000..ab73462
--- /dev/null
+++ b/STM32_4路称重_Git提交精简工程/src/STM32F10x_FWLib/src/stm32f10x_exti.c
@@ -0,0 +1,269 @@
+/**
+  ******************************************************************************
+  * @file    stm32f10x_exti.c
+  * @author  MCD Application Team
+  * @version V3.5.0
+  * @date    11-March-2011
+  * @brief   This file provides all the EXTI firmware functions.
+  ******************************************************************************
+  * @attention
+  *
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+  *
+  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x_exti.h"
+
+/** @addtogroup STM32F10x_StdPeriph_Driver
+  * @{
+  */
+
+/** @defgroup EXTI 
+  * @brief EXTI driver modules
+  * @{
+  */
+
+/** @defgroup EXTI_Private_TypesDefinitions
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup EXTI_Private_Defines
+  * @{
+  */
+
+#define EXTI_LINENONE    ((uint32_t)0x00000)  /* No interrupt selected */
+
+/**
+  * @}
+  */
+
+/** @defgroup EXTI_Private_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup EXTI_Private_Variables
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup EXTI_Private_FunctionPrototypes
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup EXTI_Private_Functions
+  * @{
+  */
+
+/**
+  * @brief  Deinitializes the EXTI peripheral registers to their default reset values.
+  * @param  None
+  * @retval None
+  */
+void EXTI_DeInit(void)
+{
+  EXTI->IMR = 0x00000000;
+  EXTI->EMR = 0x00000000;
+  EXTI->RTSR = 0x00000000; 
+  EXTI->FTSR = 0x00000000; 
+  EXTI->PR = 0x000FFFFF;
+}
+
+/**
+  * @brief  Initializes the EXTI peripheral according to the specified
+  *         parameters in the EXTI_InitStruct.
+  * @param  EXTI_InitStruct: pointer to a EXTI_InitTypeDef structure
+  *         that contains the configuration information for the EXTI peripheral.
+  * @retval None
+  */
+void EXTI_Init(EXTI_InitTypeDef* EXTI_InitStruct)
+{
+  uint32_t tmp = 0;
+
+  /* Check the parameters */
+  assert_param(IS_EXTI_MODE(EXTI_InitStruct->EXTI_Mode));
+  assert_param(IS_EXTI_TRIGGER(EXTI_InitStruct->EXTI_Trigger));
+  assert_param(IS_EXTI_LINE(EXTI_InitStruct->EXTI_Line));  
+  assert_param(IS_FUNCTIONAL_STATE(EXTI_InitStruct->EXTI_LineCmd));
+
+  tmp = (uint32_t)EXTI_BASE;
+     
+  if (EXTI_InitStruct->EXTI_LineCmd != DISABLE)
+  {
+    /* Clear EXTI line configuration */
+    EXTI->IMR &= ~EXTI_InitStruct->EXTI_Line;
+    EXTI->EMR &= ~EXTI_InitStruct->EXTI_Line;
+    
+    tmp += EXTI_InitStruct->EXTI_Mode;
+
+    *(__IO uint32_t *) tmp |= EXTI_InitStruct->EXTI_Line;
+
+    /* Clear Rising Falling edge configuration */
+    EXTI->RTSR &= ~EXTI_InitStruct->EXTI_Line;
+    EXTI->FTSR &= ~EXTI_InitStruct->EXTI_Line;
+    
+    /* Select the trigger for the selected external interrupts */
+    if (EXTI_InitStruct->EXTI_Trigger == EXTI_Trigger_Rising_Falling)
+    {
+      /* Rising Falling edge */
+      EXTI->RTSR |= EXTI_InitStruct->EXTI_Line;
+      EXTI->FTSR |= EXTI_InitStruct->EXTI_Line;
+    }
+    else
+    {
+      tmp = (uint32_t)EXTI_BASE;
+      tmp += EXTI_InitStruct->EXTI_Trigger;
+
+      *(__IO uint32_t *) tmp |= EXTI_InitStruct->EXTI_Line;
+    }
+  }
+  else
+  {
+    tmp += EXTI_InitStruct->EXTI_Mode;
+
+    /* Disable the selected external lines */
+    *(__IO uint32_t *) tmp &= ~EXTI_InitStruct->EXTI_Line;
+  }
+}
+
+/**
+  * @brief  Fills each EXTI_InitStruct member with its reset value.
+  * @param  EXTI_InitStruct: pointer to a EXTI_InitTypeDef structure which will
+  *         be initialized.
+  * @retval None
+  */
+void EXTI_StructInit(EXTI_InitTypeDef* EXTI_InitStruct)
+{
+  EXTI_InitStruct->EXTI_Line = EXTI_LINENONE;
+  EXTI_InitStruct->EXTI_Mode = EXTI_Mode_Interrupt;
+  EXTI_InitStruct->EXTI_Trigger = EXTI_Trigger_Falling;
+  EXTI_InitStruct->EXTI_LineCmd = DISABLE;
+}
+
+/**
+  * @brief  Generates a Software interrupt.
+  * @param  EXTI_Line: specifies the EXTI lines to be enabled or disabled.
+  *   This parameter can be any combination of EXTI_Linex where x can be (0..19).
+  * @retval None
+  */
+void EXTI_GenerateSWInterrupt(uint32_t EXTI_Line)
+{
+  /* Check the parameters */
+  assert_param(IS_EXTI_LINE(EXTI_Line));
+  
+  EXTI->SWIER |= EXTI_Line;
+}
+
+/**
+  * @brief  Checks whether the specified EXTI line flag is set or not.
+  * @param  EXTI_Line: specifies the EXTI line flag to check.
+  *   This parameter can be:
+  *     @arg EXTI_Linex: External interrupt line x where x(0..19)
+  * @retval The new state of EXTI_Line (SET or RESET).
+  */
+FlagStatus EXTI_GetFlagStatus(uint32_t EXTI_Line)
+{
+  FlagStatus bitstatus = RESET;
+  /* Check the parameters */
+  assert_param(IS_GET_EXTI_LINE(EXTI_Line));
+  
+  if ((EXTI->PR & EXTI_Line) != (uint32_t)RESET)
+  {
+    bitstatus = SET;
+  }
+  else
+  {
+    bitstatus = RESET;
+  }
+  return bitstatus;
+}
+
+/**
+  * @brief  Clears the EXTI's line pending flags.
+  * @param  EXTI_Line: specifies the EXTI lines flags to clear.
+  *   This parameter can be any combination of EXTI_Linex where x can be (0..19).
+  * @retval None
+  */
+void EXTI_ClearFlag(uint32_t EXTI_Line)
+{
+  /* Check the parameters */
+  assert_param(IS_EXTI_LINE(EXTI_Line));
+  
+  EXTI->PR = EXTI_Line;
+}
+
+/**
+  * @brief  Checks whether the specified EXTI line is asserted or not.
+  * @param  EXTI_Line: specifies the EXTI line to check.
+  *   This parameter can be:
+  *     @arg EXTI_Linex: External interrupt line x where x(0..19)
+  * @retval The new state of EXTI_Line (SET or RESET).
+  */
+ITStatus EXTI_GetITStatus(uint32_t EXTI_Line)
+{
+  ITStatus bitstatus = RESET;
+  uint32_t enablestatus = 0;
+  /* Check the parameters */
+  assert_param(IS_GET_EXTI_LINE(EXTI_Line));
+  
+  enablestatus =  EXTI->IMR & EXTI_Line;
+  if (((EXTI->PR & EXTI_Line) != (uint32_t)RESET) && (enablestatus != (uint32_t)RESET))
+  {
+    bitstatus = SET;
+  }
+  else
+  {
+    bitstatus = RESET;
+  }
+  return bitstatus;
+}
+
+/**
+  * @brief  Clears the EXTI's line pending bits.
+  * @param  EXTI_Line: specifies the EXTI lines to clear.
+  *   This parameter can be any combination of EXTI_Linex where x can be (0..19).
+  * @retval None
+  */
+void EXTI_ClearITPendingBit(uint32_t EXTI_Line)
+{
+  /* Check the parameters */
+  assert_param(IS_EXTI_LINE(EXTI_Line));
+  
+  EXTI->PR = EXTI_Line;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/STM32_4路称重_Git提交精简工程/src/STM32F10x_FWLib/src/stm32f10x_flash.c b/STM32_4路称重_Git提交精简工程/src/STM32F10x_FWLib/src/stm32f10x_flash.c
new file mode 100755
index 0000000..f6c7bf1
--- /dev/null
+++ b/STM32_4路称重_Git提交精简工程/src/STM32F10x_FWLib/src/stm32f10x_flash.c
@@ -0,0 +1,1684 @@
+/**
+  ******************************************************************************
+  * @file    stm32f10x_flash.c
+  * @author  MCD Application Team
+  * @version V3.5.0
+  * @date    11-March-2011
+  * @brief   This file provides all the FLASH firmware functions.
+  ******************************************************************************
+  * @attention
+  *
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+  *
+  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x_flash.h"
+
+/** @addtogroup STM32F10x_StdPeriph_Driver
+  * @{
+  */
+
+/** @defgroup FLASH 
+  * @brief FLASH driver modules
+  * @{
+  */ 
+
+/** @defgroup FLASH_Private_TypesDefinitions
+  * @{
+  */
+
+/**
+  * @}
+  */ 
+
+/** @defgroup FLASH_Private_Defines
+  * @{
+  */ 
+
+/* Flash Access Control Register bits */
+#define ACR_LATENCY_Mask         ((uint32_t)0x00000038)
+#define ACR_HLFCYA_Mask          ((uint32_t)0xFFFFFFF7)
+#define ACR_PRFTBE_Mask          ((uint32_t)0xFFFFFFEF)
+
+/* Flash Access Control Register bits */
+#define ACR_PRFTBS_Mask          ((uint32_t)0x00000020) 
+
+/* Flash Control Register bits */
+#define CR_PG_Set                ((uint32_t)0x00000001)
+#define CR_PG_Reset              ((uint32_t)0x00001FFE) 
+#define CR_PER_Set               ((uint32_t)0x00000002)
+#define CR_PER_Reset             ((uint32_t)0x00001FFD)
+#define CR_MER_Set               ((uint32_t)0x00000004)
+#define CR_MER_Reset             ((uint32_t)0x00001FFB)
+#define CR_OPTPG_Set             ((uint32_t)0x00000010)
+#define CR_OPTPG_Reset           ((uint32_t)0x00001FEF)
+#define CR_OPTER_Set             ((uint32_t)0x00000020)
+#define CR_OPTER_Reset           ((uint32_t)0x00001FDF)
+#define CR_STRT_Set              ((uint32_t)0x00000040)
+#define CR_LOCK_Set              ((uint32_t)0x00000080)
+
+/* FLASH Mask */
+#define RDPRT_Mask               ((uint32_t)0x00000002)
+#define WRP0_Mask                ((uint32_t)0x000000FF)
+#define WRP1_Mask                ((uint32_t)0x0000FF00)
+#define WRP2_Mask                ((uint32_t)0x00FF0000)
+#define WRP3_Mask                ((uint32_t)0xFF000000)
+#define OB_USER_BFB2             ((uint16_t)0x0008)
+
+/* FLASH Keys */
+#define RDP_Key                  ((uint16_t)0x00A5)
+#define FLASH_KEY1               ((uint32_t)0x45670123)
+#define FLASH_KEY2               ((uint32_t)0xCDEF89AB)
+
+/* FLASH BANK address */
+#define FLASH_BANK1_END_ADDRESS   ((uint32_t)0x807FFFF)
+
+/* Delay definition */   
+#define EraseTimeout          ((uint32_t)0x000B0000)
+#define ProgramTimeout        ((uint32_t)0x00002000)
+/**
+  * @}
+  */ 
+
+/** @defgroup FLASH_Private_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */ 
+
+/** @defgroup FLASH_Private_Variables
+  * @{
+  */
+
+/**
+  * @}
+  */ 
+
+/** @defgroup FLASH_Private_FunctionPrototypes
+  * @{
+  */
+  
+/**
+  * @}
+  */
+
+/** @defgroup FLASH_Private_Functions
+  * @{
+  */
+
+/**
+@code  
+ 
+ This driver provides functions to configure and program the Flash memory of all STM32F10x devices,
+ including the latest STM32F10x_XL density devices. 
+
+ STM32F10x_XL devices feature up to 1 Mbyte with dual bank architecture for read-while-write (RWW) capability:
+    - bank1: fixed size of 512 Kbytes (256 pages of 2Kbytes each)
+    - bank2: up to 512 Kbytes (up to 256 pages of 2Kbytes each)
+ While other STM32F10x devices features only one bank with memory up to 512 Kbytes.
+
+ In version V3.3.0, some functions were updated and new ones were added to support
+ STM32F10x_XL devices. Thus some functions manages all devices, while other are 
+ dedicated for XL devices only.
+ 
+ The table below presents the list of available functions depending on the used STM32F10x devices.  
+      
+   ***************************************************
+   * Legacy functions used for all STM32F10x devices *
+   ***************************************************
+   +----------------------------------------------------------------------------------------------------------------------------------+
+   |       Functions prototypes         |STM32F10x_XL|Other STM32F10x|    Comments                                                    |
+   |                                    |   devices  |  devices      |                                                                |
+   |----------------------------------------------------------------------------------------------------------------------------------|
+   |FLASH_SetLatency                    |    Yes     |      Yes      | No change                                                      |
+   |----------------------------------------------------------------------------------------------------------------------------------|
+   |FLASH_HalfCycleAccessCmd            |    Yes     |      Yes      | No change                                                      |
+   |----------------------------------------------------------------------------------------------------------------------------------|
+   |FLASH_PrefetchBufferCmd             |    Yes     |      Yes      | No change                                                      |
+   |----------------------------------------------------------------------------------------------------------------------------------|
+   |FLASH_Unlock                        |    Yes     |      Yes      | - For STM32F10X_XL devices: unlock Bank1 and Bank2.            |
+   |                                    |            |               | - For other devices: unlock Bank1 and it is equivalent         |
+   |                                    |            |               |   to FLASH_UnlockBank1 function.                               |
+   |----------------------------------------------------------------------------------------------------------------------------------|
+   |FLASH_Lock                          |    Yes     |      Yes      | - For STM32F10X_XL devices: lock Bank1 and Bank2.              |
+   |                                    |            |               | - For other devices: lock Bank1 and it is equivalent           |
+   |                                    |            |               |   to FLASH_LockBank1 function.                                 |
+   |----------------------------------------------------------------------------------------------------------------------------------|
+   |FLASH_ErasePage                     |    Yes     |      Yes      | - For STM32F10x_XL devices: erase a page in Bank1 and Bank2    |
+   |                                    |            |               | - For other devices: erase a page in Bank1                     |
+   |----------------------------------------------------------------------------------------------------------------------------------|
+   |FLASH_EraseAllPages                 |    Yes     |      Yes      | - For STM32F10x_XL devices: erase all pages in Bank1 and Bank2 |
+   |                                    |            |               | - For other devices: erase all pages in Bank1                  |
+   |----------------------------------------------------------------------------------------------------------------------------------|
+   |FLASH_EraseOptionBytes              |    Yes     |      Yes      | No change                                                      |
+   |----------------------------------------------------------------------------------------------------------------------------------|
+   |FLASH_ProgramWord                   |    Yes     |      Yes      | Updated to program up to 1MByte (depending on the used device) |
+   |----------------------------------------------------------------------------------------------------------------------------------|
+   |FLASH_ProgramHalfWord               |    Yes     |      Yes      | Updated to program up to 1MByte (depending on the used device) |
+   |----------------------------------------------------------------------------------------------------------------------------------|
+   |FLASH_ProgramOptionByteData         |    Yes     |      Yes      | No change                                                      |
+   |----------------------------------------------------------------------------------------------------------------------------------|
+   |FLASH_EnableWriteProtection         |    Yes     |      Yes      | No change                                                      |
+   |----------------------------------------------------------------------------------------------------------------------------------|
+   |FLASH_ReadOutProtection             |    Yes     |      Yes      | No change                                                      |
+   |----------------------------------------------------------------------------------------------------------------------------------|
+   |FLASH_UserOptionByteConfig          |    Yes     |      Yes      | No change                                                      |
+   |----------------------------------------------------------------------------------------------------------------------------------|
+   |FLASH_GetUserOptionByte             |    Yes     |      Yes      | No change                                                      |
+   |----------------------------------------------------------------------------------------------------------------------------------|
+   |FLASH_GetWriteProtectionOptionByte  |    Yes     |      Yes      | No change                                                      |
+   |----------------------------------------------------------------------------------------------------------------------------------|
+   |FLASH_GetReadOutProtectionStatus    |    Yes     |      Yes      | No change                                                      |
+   |----------------------------------------------------------------------------------------------------------------------------------|
+   |FLASH_GetPrefetchBufferStatus       |    Yes     |      Yes      | No change                                                      |
+   |----------------------------------------------------------------------------------------------------------------------------------|
+   |FLASH_ITConfig                      |    Yes     |      Yes      | - For STM32F10x_XL devices: enable Bank1 and Bank2's interrupts|
+   |                                    |            |               | - For other devices: enable Bank1's interrupts                 |
+   |----------------------------------------------------------------------------------------------------------------------------------|
+   |FLASH_GetFlagStatus                 |    Yes     |      Yes      | - For STM32F10x_XL devices: return Bank1 and Bank2's flag status|
+   |                                    |            |               | - For other devices: return Bank1's flag status                |
+   |----------------------------------------------------------------------------------------------------------------------------------|
+   |FLASH_ClearFlag                     |    Yes     |      Yes      | - For STM32F10x_XL devices: clear Bank1 and Bank2's flag       |
+   |                                    |            |               | - For other devices: clear Bank1's flag                        |
+   |----------------------------------------------------------------------------------------------------------------------------------|
+   |FLASH_GetStatus                     |    Yes     |      Yes      | - Return the status of Bank1 (for all devices)                 |
+   |                                    |            |               |   equivalent to FLASH_GetBank1Status function                  |
+   |----------------------------------------------------------------------------------------------------------------------------------|
+   |FLASH_WaitForLastOperation          |    Yes     |      Yes      | - Wait for Bank1 last operation (for all devices)              |
+   |                                    |            |               |   equivalent to: FLASH_WaitForLastBank1Operation function      |
+   +----------------------------------------------------------------------------------------------------------------------------------+
+
+   ************************************************************************************************************************
+   * New functions used for all STM32F10x devices to manage Bank1:                                                        *
+   *   - These functions are mainly useful for STM32F10x_XL density devices, to have separate control for Bank1 and bank2 *
+   *   - For other devices, these functions are optional (covered by functions listed above)                              *
+   ************************************************************************************************************************
+   +----------------------------------------------------------------------------------------------------------------------------------+
+   |       Functions prototypes         |STM32F10x_XL|Other STM32F10x|    Comments                                                    |
+   |                                    |   devices  |  devices      |                                                                |
+   |----------------------------------------------------------------------------------------------------------------------------------|
+   | FLASH_UnlockBank1                  |    Yes     |      Yes      | - Unlock Bank1                                                 |
+   |----------------------------------------------------------------------------------------------------------------------------------|
+   |FLASH_LockBank1                     |    Yes     |      Yes      | - Lock Bank1                                                   |
+   |----------------------------------------------------------------------------------------------------------------------------------|
+   | FLASH_EraseAllBank1Pages           |    Yes     |      Yes      | - Erase all pages in Bank1                                     |
+   |----------------------------------------------------------------------------------------------------------------------------------|
+   | FLASH_GetBank1Status               |    Yes     |      Yes      | - Return the status of Bank1                                   |
+   |----------------------------------------------------------------------------------------------------------------------------------|
+   | FLASH_WaitForLastBank1Operation    |    Yes     |      Yes      | - Wait for Bank1 last operation                                |
+   +----------------------------------------------------------------------------------------------------------------------------------+
+
+   *****************************************************************************
+   * New Functions used only with STM32F10x_XL density devices to manage Bank2 *
+   *****************************************************************************
+   +----------------------------------------------------------------------------------------------------------------------------------+
+   |       Functions prototypes         |STM32F10x_XL|Other STM32F10x|    Comments                                                    |
+   |                                    |   devices  |  devices      |                                                                |
+   |----------------------------------------------------------------------------------------------------------------------------------|
+   | FLASH_UnlockBank2                  |    Yes     |      No       | - Unlock Bank2                                                 |
+   |----------------------------------------------------------------------------------------------------------------------------------|
+   |FLASH_LockBank2                     |    Yes     |      No       | - Lock Bank2                                                   |
+   |----------------------------------------------------------------------------------------------------------------------------------|
+   | FLASH_EraseAllBank2Pages           |    Yes     |      No       | - Erase all pages in Bank2                                     |
+   |----------------------------------------------------------------------------------------------------------------------------------|
+   | FLASH_GetBank2Status               |    Yes     |      No       | - Return the status of Bank2                                   |
+   |----------------------------------------------------------------------------------------------------------------------------------|
+   | FLASH_WaitForLastBank2Operation    |    Yes     |      No       | - Wait for Bank2 last operation                                |
+   |----------------------------------------------------------------------------------------------------------------------------------|
+   | FLASH_BootConfig                   |    Yes     |      No       | - Configure to boot from Bank1 or Bank2                        |
+   +----------------------------------------------------------------------------------------------------------------------------------+
+@endcode
+*/
+
+
+/**
+  * @brief  Sets the code latency value.
+  * @note   This function can be used for all STM32F10x devices.
+  * @param  FLASH_Latency: specifies the FLASH Latency value.
+  *   This parameter can be one of the following values:
+  *     @arg FLASH_Latency_0: FLASH Zero Latency cycle
+  *     @arg FLASH_Latency_1: FLASH One Latency cycle
+  *     @arg FLASH_Latency_2: FLASH Two Latency cycles
+  * @retval None
+  */
+void FLASH_SetLatency(uint32_t FLASH_Latency)
+{
+  uint32_t tmpreg = 0;
+  
+  /* Check the parameters */
+  assert_param(IS_FLASH_LATENCY(FLASH_Latency));
+  
+  /* Read the ACR register */
+  tmpreg = FLASH->ACR;  
+  
+  /* Sets the Latency value */
+  tmpreg &= ACR_LATENCY_Mask;
+  tmpreg |= FLASH_Latency;
+  
+  /* Write the ACR register */
+  FLASH->ACR = tmpreg;
+}
+
+/**
+  * @brief  Enables or disables the Half cycle flash access.
+  * @note   This function can be used for all STM32F10x devices.
+  * @param  FLASH_HalfCycleAccess: specifies the FLASH Half cycle Access mode.
+  *   This parameter can be one of the following values:
+  *     @arg FLASH_HalfCycleAccess_Enable: FLASH Half Cycle Enable
+  *     @arg FLASH_HalfCycleAccess_Disable: FLASH Half Cycle Disable
+  * @retval None
+  */
+void FLASH_HalfCycleAccessCmd(uint32_t FLASH_HalfCycleAccess)
+{
+  /* Check the parameters */
+  assert_param(IS_FLASH_HALFCYCLEACCESS_STATE(FLASH_HalfCycleAccess));
+  
+  /* Enable or disable the Half cycle access */
+  FLASH->ACR &= ACR_HLFCYA_Mask;
+  FLASH->ACR |= FLASH_HalfCycleAccess;
+}
+
+/**
+  * @brief  Enables or disables the Prefetch Buffer.
+  * @note   This function can be used for all STM32F10x devices.
+  * @param  FLASH_PrefetchBuffer: specifies the Prefetch buffer status.
+  *   This parameter can be one of the following values:
+  *     @arg FLASH_PrefetchBuffer_Enable: FLASH Prefetch Buffer Enable
+  *     @arg FLASH_PrefetchBuffer_Disable: FLASH Prefetch Buffer Disable
+  * @retval None
+  */
+void FLASH_PrefetchBufferCmd(uint32_t FLASH_PrefetchBuffer)
+{
+  /* Check the parameters */
+  assert_param(IS_FLASH_PREFETCHBUFFER_STATE(FLASH_PrefetchBuffer));
+  
+  /* Enable or disable the Prefetch Buffer */
+  FLASH->ACR &= ACR_PRFTBE_Mask;
+  FLASH->ACR |= FLASH_PrefetchBuffer;
+}
+
+/**
+  * @brief  Unlocks the FLASH Program Erase Controller.
+  * @note   This function can be used for all STM32F10x devices.
+  *         - For STM32F10X_XL devices this function unlocks Bank1 and Bank2.
+  *         - For all other devices it unlocks Bank1 and it is equivalent 
+  *           to FLASH_UnlockBank1 function.. 
+  * @param  None
+  * @retval None
+  */
+void FLASH_Unlock(void)
+{
+  /* Authorize the FPEC of Bank1 Access */
+  FLASH->KEYR = FLASH_KEY1;
+  FLASH->KEYR = FLASH_KEY2;
+
+#ifdef STM32F10X_XL
+  /* Authorize the FPEC of Bank2 Access */
+  FLASH->KEYR2 = FLASH_KEY1;
+  FLASH->KEYR2 = FLASH_KEY2;
+#endif /* STM32F10X_XL */
+}
+/**
+  * @brief  Unlocks the FLASH Bank1 Program Erase Controller.
+  * @note   This function can be used for all STM32F10x devices.
+  *         - For STM32F10X_XL devices this function unlocks Bank1.
+  *         - For all other devices it unlocks Bank1 and it is 
+  *           equivalent to FLASH_Unlock function.
+  * @param  None
+  * @retval None
+  */
+void FLASH_UnlockBank1(void)
+{
+  /* Authorize the FPEC of Bank1 Access */
+  FLASH->KEYR = FLASH_KEY1;
+  FLASH->KEYR = FLASH_KEY2;
+}
+
+#ifdef STM32F10X_XL
+/**
+  * @brief  Unlocks the FLASH Bank2 Program Erase Controller.
+  * @note   This function can be used only for STM32F10X_XL density devices.
+  * @param  None
+  * @retval None
+  */
+void FLASH_UnlockBank2(void)
+{
+  /* Authorize the FPEC of Bank2 Access */
+  FLASH->KEYR2 = FLASH_KEY1;
+  FLASH->KEYR2 = FLASH_KEY2;
+
+}
+#endif /* STM32F10X_XL */
+
+/**
+  * @brief  Locks the FLASH Program Erase Controller.
+  * @note   This function can be used for all STM32F10x devices.
+  *         - For STM32F10X_XL devices this function Locks Bank1 and Bank2.
+  *         - For all other devices it Locks Bank1 and it is equivalent 
+  *           to FLASH_LockBank1 function.
+  * @param  None
+  * @retval None
+  */
+void FLASH_Lock(void)
+{
+  /* Set the Lock Bit to lock the FPEC and the CR of  Bank1 */
+  FLASH->CR |= CR_LOCK_Set;
+
+#ifdef STM32F10X_XL
+  /* Set the Lock Bit to lock the FPEC and the CR of  Bank2 */
+  FLASH->CR2 |= CR_LOCK_Set;
+#endif /* STM32F10X_XL */
+}
+
+/**
+  * @brief  Locks the FLASH Bank1 Program Erase Controller.
+  * @note   this function can be used for all STM32F10x devices.
+  *         - For STM32F10X_XL devices this function Locks Bank1.
+  *         - For all other devices it Locks Bank1 and it is equivalent 
+  *           to FLASH_Lock function.
+  * @param  None
+  * @retval None
+  */
+void FLASH_LockBank1(void)
+{
+  /* Set the Lock Bit to lock the FPEC and the CR of  Bank1 */
+  FLASH->CR |= CR_LOCK_Set;
+}
+
+#ifdef STM32F10X_XL
+/**
+  * @brief  Locks the FLASH Bank2 Program Erase Controller.
+  * @note   This function can be used only for STM32F10X_XL density devices.
+  * @param  None
+  * @retval None
+  */
+void FLASH_LockBank2(void)
+{
+  /* Set the Lock Bit to lock the FPEC and the CR of  Bank2 */
+  FLASH->CR2 |= CR_LOCK_Set;
+}
+#endif /* STM32F10X_XL */
+
+/**
+  * @brief  Erases a specified FLASH page.
+  * @note   This function can be used for all STM32F10x devices.
+  * @param  Page_Address: The page address to be erased.
+  * @retval FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERROR_PG,
+  *         FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
+  */
+FLASH_Status FLASH_ErasePage(uint32_t Page_Address)
+{
+  FLASH_Status status = FLASH_COMPLETE;
+  /* Check the parameters */
+  assert_param(IS_FLASH_ADDRESS(Page_Address));
+
+#ifdef STM32F10X_XL
+  if(Page_Address < FLASH_BANK1_END_ADDRESS)  
+  {
+    /* Wait for last operation to be completed */
+    status = FLASH_WaitForLastBank1Operation(EraseTimeout);
+    if(status == FLASH_COMPLETE)
+    { 
+      /* if the previous operation is completed, proceed to erase the page */
+      FLASH->CR|= CR_PER_Set;
+      FLASH->AR = Page_Address; 
+      FLASH->CR|= CR_STRT_Set;
+    
+      /* Wait for last operation to be completed */
+      status = FLASH_WaitForLastBank1Operation(EraseTimeout);
+
+      /* Disable the PER Bit */
+      FLASH->CR &= CR_PER_Reset;
+    }
+  }
+  else
+  {
+    /* Wait for last operation to be completed */
+    status = FLASH_WaitForLastBank2Operation(EraseTimeout);
+    if(status == FLASH_COMPLETE)
+    { 
+      /* if the previous operation is completed, proceed to erase the page */
+      FLASH->CR2|= CR_PER_Set;
+      FLASH->AR2 = Page_Address; 
+      FLASH->CR2|= CR_STRT_Set;
+    
+      /* Wait for last operation to be completed */
+      status = FLASH_WaitForLastBank2Operation(EraseTimeout);
+      
+      /* Disable the PER Bit */
+      FLASH->CR2 &= CR_PER_Reset;
+    }
+  }
+#else
+  /* Wait for last operation to be completed */
+  status = FLASH_WaitForLastOperation(EraseTimeout);
+  
+  if(status == FLASH_COMPLETE)
+  { 
+    /* if the previous operation is completed, proceed to erase the page */
+    FLASH->CR|= CR_PER_Set;
+    FLASH->AR = Page_Address; 
+    FLASH->CR|= CR_STRT_Set;
+    
+    /* Wait for last operation to be completed */
+    status = FLASH_WaitForLastOperation(EraseTimeout);
+    
+    /* Disable the PER Bit */
+    FLASH->CR &= CR_PER_Reset;
+  }
+#endif /* STM32F10X_XL */
+
+  /* Return the Erase Status */
+  return status;
+}
+
+/**
+  * @brief  Erases all FLASH pages.
+  * @note   This function can be used for all STM32F10x devices.
+  * @param  None
+  * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG,
+  *         FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
+  */
+FLASH_Status FLASH_EraseAllPages(void)
+{
+  FLASH_Status status = FLASH_COMPLETE;
+
+#ifdef STM32F10X_XL
+  /* Wait for last operation to be completed */
+  status = FLASH_WaitForLastBank1Operation(EraseTimeout);
+  
+  if(status == FLASH_COMPLETE)
+  {
+    /* if the previous operation is completed, proceed to erase all pages */
+     FLASH->CR |= CR_MER_Set;
+     FLASH->CR |= CR_STRT_Set;
+    
+    /* Wait for last operation to be completed */
+    status = FLASH_WaitForLastBank1Operation(EraseTimeout);
+    
+    /* Disable the MER Bit */
+    FLASH->CR &= CR_MER_Reset;
+  }    
+  if(status == FLASH_COMPLETE)
+  {
+    /* if the previous operation is completed, proceed to erase all pages */
+     FLASH->CR2 |= CR_MER_Set;
+     FLASH->CR2 |= CR_STRT_Set;
+    
+    /* Wait for last operation to be completed */
+    status = FLASH_WaitForLastBank2Operation(EraseTimeout);
+    
+    /* Disable the MER Bit */
+    FLASH->CR2 &= CR_MER_Reset;
+  }
+#else
+  /* Wait for last operation to be completed */
+  status = FLASH_WaitForLastOperation(EraseTimeout);
+  if(status == FLASH_COMPLETE)
+  {
+    /* if the previous operation is completed, proceed to erase all pages */
+     FLASH->CR |= CR_MER_Set;
+     FLASH->CR |= CR_STRT_Set;
+    
+    /* Wait for last operation to be completed */
+    status = FLASH_WaitForLastOperation(EraseTimeout);
+
+    /* Disable the MER Bit */
+    FLASH->CR &= CR_MER_Reset;
+  }
+#endif /* STM32F10X_XL */
+
+  /* Return the Erase Status */
+  return status;
+}
+
+/**
+  * @brief  Erases all Bank1 FLASH pages.
+  * @note   This function can be used for all STM32F10x devices.
+  *         - For STM32F10X_XL devices this function erases all Bank1 pages.
+  *         - For all other devices it erases all Bank1 pages and it is equivalent 
+  *           to FLASH_EraseAllPages function.
+  * @param  None
+  * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG,
+  *         FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
+  */
+FLASH_Status FLASH_EraseAllBank1Pages(void)
+{
+  FLASH_Status status = FLASH_COMPLETE;
+  /* Wait for last operation to be completed */
+  status = FLASH_WaitForLastBank1Operation(EraseTimeout);
+  
+  if(status == FLASH_COMPLETE)
+  {
+    /* if the previous operation is completed, proceed to erase all pages */
+     FLASH->CR |= CR_MER_Set;
+     FLASH->CR |= CR_STRT_Set;
+    
+    /* Wait for last operation to be completed */
+    status = FLASH_WaitForLastBank1Operation(EraseTimeout);
+    
+    /* Disable the MER Bit */
+    FLASH->CR &= CR_MER_Reset;
+  }    
+  /* Return the Erase Status */
+  return status;
+}
+
+#ifdef STM32F10X_XL
+/**
+  * @brief  Erases all Bank2 FLASH pages.
+  * @note   This function can be used only for STM32F10x_XL density devices.
+  * @param  None
+  * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG,
+  *         FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
+  */
+FLASH_Status FLASH_EraseAllBank2Pages(void)
+{
+  FLASH_Status status = FLASH_COMPLETE;
+  /* Wait for last operation to be completed */
+  status = FLASH_WaitForLastBank2Operation(EraseTimeout);
+  
+  if(status == FLASH_COMPLETE)
+  {
+    /* if the previous operation is completed, proceed to erase all pages */
+     FLASH->CR2 |= CR_MER_Set;
+     FLASH->CR2 |= CR_STRT_Set;
+    
+    /* Wait for last operation to be completed */
+    status = FLASH_WaitForLastBank2Operation(EraseTimeout);
+
+    /* Disable the MER Bit */
+    FLASH->CR2 &= CR_MER_Reset;
+  }    
+  /* Return the Erase Status */
+  return status;
+}
+#endif /* STM32F10X_XL */
+
+/**
+  * @brief  Erases the FLASH option bytes.
+  * @note   This functions erases all option bytes except the Read protection (RDP). 
+  * @note   This function can be used for all STM32F10x devices.
+  * @param  None
+  * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG,
+  *         FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
+  */
+FLASH_Status FLASH_EraseOptionBytes(void)
+{
+  uint16_t rdptmp = RDP_Key;
+
+  FLASH_Status status = FLASH_COMPLETE;
+
+  /* Get the actual read protection Option Byte value */ 
+  if(FLASH_GetReadOutProtectionStatus() != RESET)
+  {
+    rdptmp = 0x00;  
+  }
+
+  /* Wait for last operation to be completed */
+  status = FLASH_WaitForLastOperation(EraseTimeout);
+  if(status == FLASH_COMPLETE)
+  {
+    /* Authorize the small information block programming */
+    FLASH->OPTKEYR = FLASH_KEY1;
+    FLASH->OPTKEYR = FLASH_KEY2;
+    
+    /* if the previous operation is completed, proceed to erase the option bytes */
+    FLASH->CR |= CR_OPTER_Set;
+    FLASH->CR |= CR_STRT_Set;
+    /* Wait for last operation to be completed */
+    status = FLASH_WaitForLastOperation(EraseTimeout);
+    
+    if(status == FLASH_COMPLETE)
+    {
+      /* if the erase operation is completed, disable the OPTER Bit */
+      FLASH->CR &= CR_OPTER_Reset;
+       
+      /* Enable the Option Bytes Programming operation */
+      FLASH->CR |= CR_OPTPG_Set;
+      /* Restore the last read protection Option Byte value */
+      OB->RDP = (uint16_t)rdptmp; 
+      /* Wait for last operation to be completed */
+      status = FLASH_WaitForLastOperation(ProgramTimeout);
+ 
+      if(status != FLASH_TIMEOUT)
+      {
+        /* if the program operation is completed, disable the OPTPG Bit */
+        FLASH->CR &= CR_OPTPG_Reset;
+      }
+    }
+    else
+    {
+      if (status != FLASH_TIMEOUT)
+      {
+        /* Disable the OPTPG Bit */
+        FLASH->CR &= CR_OPTPG_Reset;
+      }
+    }  
+  }
+  /* Return the erase status */
+  return status;
+}
+
+/**
+  * @brief  Programs a word at a specified address.
+  * @note   This function can be used for all STM32F10x devices.
+  * @param  Address: specifies the address to be programmed.
+  * @param  Data: specifies the data to be programmed.
+  * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG,
+  *         FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. 
+  */
+FLASH_Status FLASH_ProgramWord(uint32_t Address, uint32_t Data)
+{
+  FLASH_Status status = FLASH_COMPLETE;
+  __IO uint32_t tmp = 0;
+
+  /* Check the parameters */
+  assert_param(IS_FLASH_ADDRESS(Address));
+
+#ifdef STM32F10X_XL
+  if(Address < FLASH_BANK1_END_ADDRESS - 2)
+  { 
+    /* Wait for last operation to be completed */
+    status = FLASH_WaitForLastBank1Operation(ProgramTimeout); 
+    if(status == FLASH_COMPLETE)
+    {
+      /* if the previous operation is completed, proceed to program the new first 
+        half word */
+      FLASH->CR |= CR_PG_Set;
+  
+      *(__IO uint16_t*)Address = (uint16_t)Data;
+      /* Wait for last operation to be completed */
+      status = FLASH_WaitForLastOperation(ProgramTimeout);
+ 
+      if(status == FLASH_COMPLETE)
+      {
+        /* if the previous operation is completed, proceed to program the new second 
+        half word */
+        tmp = Address + 2;
+
+        *(__IO uint16_t*) tmp = Data >> 16;
+    
+        /* Wait for last operation to be completed */
+        status = FLASH_WaitForLastOperation(ProgramTimeout);
+        
+        /* Disable the PG Bit */
+        FLASH->CR &= CR_PG_Reset;
+      }
+      else
+      {
+        /* Disable the PG Bit */
+        FLASH->CR &= CR_PG_Reset;
+       }
+    }
+  }
+  else if(Address == (FLASH_BANK1_END_ADDRESS - 1))
+  {
+    /* Wait for last operation to be completed */
+    status = FLASH_WaitForLastBank1Operation(ProgramTimeout);
+
+    if(status == FLASH_COMPLETE)
+    {
+      /* if the previous operation is completed, proceed to program the new first 
+        half word */
+      FLASH->CR |= CR_PG_Set;
+  
+      *(__IO uint16_t*)Address = (uint16_t)Data;
+
+      /* Wait for last operation to be completed */
+      status = FLASH_WaitForLastBank1Operation(ProgramTimeout);
+      
+	  /* Disable the PG Bit */
+      FLASH->CR &= CR_PG_Reset;
+    }
+    else
+    {
+      /* Disable the PG Bit */
+      FLASH->CR &= CR_PG_Reset;
+    }
+
+    /* Wait for last operation to be completed */
+    status = FLASH_WaitForLastBank2Operation(ProgramTimeout);
+
+    if(status == FLASH_COMPLETE)
+    {
+      /* if the previous operation is completed, proceed to program the new second 
+      half word */
+      FLASH->CR2 |= CR_PG_Set;
+      tmp = Address + 2;
+
+      *(__IO uint16_t*) tmp = Data >> 16;
+    
+      /* Wait for last operation to be completed */
+      status = FLASH_WaitForLastBank2Operation(ProgramTimeout);
+        
+      /* Disable the PG Bit */
+      FLASH->CR2 &= CR_PG_Reset;
+    }
+    else
+    {
+      /* Disable the PG Bit */
+      FLASH->CR2 &= CR_PG_Reset;
+    }
+  }
+  else
+  {
+    /* Wait for last operation to be completed */
+    status = FLASH_WaitForLastBank2Operation(ProgramTimeout);
+
+    if(status == FLASH_COMPLETE)
+    {
+      /* if the previous operation is completed, proceed to program the new first 
+        half word */
+      FLASH->CR2 |= CR_PG_Set;
+  
+      *(__IO uint16_t*)Address = (uint16_t)Data;
+      /* Wait for last operation to be completed */
+      status = FLASH_WaitForLastBank2Operation(ProgramTimeout);
+ 
+      if(status == FLASH_COMPLETE)
+      {
+        /* if the previous operation is completed, proceed to program the new second 
+        half word */
+        tmp = Address + 2;
+
+        *(__IO uint16_t*) tmp = Data >> 16;
+    
+        /* Wait for last operation to be completed */
+        status = FLASH_WaitForLastBank2Operation(ProgramTimeout);
+        
+        /* Disable the PG Bit */
+        FLASH->CR2 &= CR_PG_Reset;
+      }
+      else
+      {
+        /* Disable the PG Bit */
+        FLASH->CR2 &= CR_PG_Reset;
+      }
+    }
+  }
+#else
+  /* Wait for last operation to be completed */
+  status = FLASH_WaitForLastOperation(ProgramTimeout);
+  
+  if(status == FLASH_COMPLETE)
+  {
+    /* if the previous operation is completed, proceed to program the new first 
+    half word */
+    FLASH->CR |= CR_PG_Set;
+  
+    *(__IO uint16_t*)Address = (uint16_t)Data;
+    /* Wait for last operation to be completed */
+    status = FLASH_WaitForLastOperation(ProgramTimeout);
+ 
+    if(status == FLASH_COMPLETE)
+    {
+      /* if the previous operation is completed, proceed to program the new second 
+      half word */
+      tmp = Address + 2;
+
+      *(__IO uint16_t*) tmp = Data >> 16;
+    
+      /* Wait for last operation to be completed */
+      status = FLASH_WaitForLastOperation(ProgramTimeout);
+        
+      /* Disable the PG Bit */
+      FLASH->CR &= CR_PG_Reset;
+    }
+    else
+    {
+      /* Disable the PG Bit */
+      FLASH->CR &= CR_PG_Reset;
+    }
+  }         
+#endif /* STM32F10X_XL */
+   
+  /* Return the Program Status */
+  return status;
+}
+
+/**
+  * @brief  Programs a half word at a specified address.
+  * @note   This function can be used for all STM32F10x devices.
+  * @param  Address: specifies the address to be programmed.
+  * @param  Data: specifies the data to be programmed.
+  * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG,
+  *         FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. 
+  */
+FLASH_Status FLASH_ProgramHalfWord(uint32_t Address, uint16_t Data)
+{
+  FLASH_Status status = FLASH_COMPLETE;
+  /* Check the parameters */
+  assert_param(IS_FLASH_ADDRESS(Address));
+
+#ifdef STM32F10X_XL
+  /* Wait for last operation to be completed */
+  status = FLASH_WaitForLastOperation(ProgramTimeout);
+  
+  if(Address < FLASH_BANK1_END_ADDRESS)
+  {
+    if(status == FLASH_COMPLETE)
+    {
+      /* if the previous operation is completed, proceed to program the new data */
+      FLASH->CR |= CR_PG_Set;
+  
+      *(__IO uint16_t*)Address = Data;
+      /* Wait for last operation to be completed */
+      status = FLASH_WaitForLastBank1Operation(ProgramTimeout);
+
+      /* Disable the PG Bit */
+      FLASH->CR &= CR_PG_Reset;
+    }
+  }
+  else
+  {
+    if(status == FLASH_COMPLETE)
+    {
+      /* if the previous operation is completed, proceed to program the new data */
+      FLASH->CR2 |= CR_PG_Set;
+  
+      *(__IO uint16_t*)Address = Data;
+      /* Wait for last operation to be completed */
+      status = FLASH_WaitForLastBank2Operation(ProgramTimeout);
+
+      /* Disable the PG Bit */
+      FLASH->CR2 &= CR_PG_Reset;
+    }
+  }
+#else
+  /* Wait for last operation to be completed */
+  status = FLASH_WaitForLastOperation(ProgramTimeout);
+  
+  if(status == FLASH_COMPLETE)
+  {
+    /* if the previous operation is completed, proceed to program the new data */
+    FLASH->CR |= CR_PG_Set;
+  
+    *(__IO uint16_t*)Address = Data;
+    /* Wait for last operation to be completed */
+    status = FLASH_WaitForLastOperation(ProgramTimeout);
+    
+    /* Disable the PG Bit */
+    FLASH->CR &= CR_PG_Reset;
+  } 
+#endif  /* STM32F10X_XL */
+  
+  /* Return the Program Status */
+  return status;
+}
+
+/**
+  * @brief  Programs a half word at a specified Option Byte Data address.
+  * @note   This function can be used for all STM32F10x devices.
+  * @param  Address: specifies the address to be programmed.
+  *   This parameter can be 0x1FFFF804 or 0x1FFFF806. 
+  * @param  Data: specifies the data to be programmed.
+  * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG,
+  *         FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. 
+  */
+FLASH_Status FLASH_ProgramOptionByteData(uint32_t Address, uint8_t Data)
+{
+  FLASH_Status status = FLASH_COMPLETE;
+  /* Check the parameters */
+  assert_param(IS_OB_DATA_ADDRESS(Address));
+  status = FLASH_WaitForLastOperation(ProgramTimeout);
+
+  if(status == FLASH_COMPLETE)
+  {
+    /* Authorize the small information block programming */
+    FLASH->OPTKEYR = FLASH_KEY1;
+    FLASH->OPTKEYR = FLASH_KEY2;
+    /* Enables the Option Bytes Programming operation */
+    FLASH->CR |= CR_OPTPG_Set; 
+    *(__IO uint16_t*)Address = Data;
+    
+    /* Wait for last operation to be completed */
+    status = FLASH_WaitForLastOperation(ProgramTimeout);
+    if(status != FLASH_TIMEOUT)
+    {
+      /* if the program operation is completed, disable the OPTPG Bit */
+      FLASH->CR &= CR_OPTPG_Reset;
+    }
+  }
+  /* Return the Option Byte Data Program Status */
+  return status;
+}
+
+/**
+  * @brief  Write protects the desired pages
+  * @note   This function can be used for all STM32F10x devices.
+  * @param  FLASH_Pages: specifies the address of the pages to be write protected.
+  *   This parameter can be:
+  *     @arg For @b STM32_Low-density_devices: value between FLASH_WRProt_Pages0to3 and FLASH_WRProt_Pages28to31  
+  *     @arg For @b STM32_Medium-density_devices: value between FLASH_WRProt_Pages0to3
+  *       and FLASH_WRProt_Pages124to127
+  *     @arg For @b STM32_High-density_devices: value between FLASH_WRProt_Pages0to1 and
+  *       FLASH_WRProt_Pages60to61 or FLASH_WRProt_Pages62to255
+  *     @arg For @b STM32_Connectivity_line_devices: value between FLASH_WRProt_Pages0to1 and
+  *       FLASH_WRProt_Pages60to61 or FLASH_WRProt_Pages62to127    
+  *     @arg For @b STM32_XL-density_devices: value between FLASH_WRProt_Pages0to1 and
+  *       FLASH_WRProt_Pages60to61 or FLASH_WRProt_Pages62to511
+  *     @arg FLASH_WRProt_AllPages
+  * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG,
+  *         FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
+  */
+FLASH_Status FLASH_EnableWriteProtection(uint32_t FLASH_Pages)
+{
+  uint16_t WRP0_Data = 0xFFFF, WRP1_Data = 0xFFFF, WRP2_Data = 0xFFFF, WRP3_Data = 0xFFFF;
+  
+  FLASH_Status status = FLASH_COMPLETE;
+  
+  /* Check the parameters */
+  assert_param(IS_FLASH_WRPROT_PAGE(FLASH_Pages));
+  
+  FLASH_Pages = (uint32_t)(~FLASH_Pages);
+  WRP0_Data = (uint16_t)(FLASH_Pages & WRP0_Mask);
+  WRP1_Data = (uint16_t)((FLASH_Pages & WRP1_Mask) >> 8);
+  WRP2_Data = (uint16_t)((FLASH_Pages & WRP2_Mask) >> 16);
+  WRP3_Data = (uint16_t)((FLASH_Pages & WRP3_Mask) >> 24);
+  
+  /* Wait for last operation to be completed */
+  status = FLASH_WaitForLastOperation(ProgramTimeout);
+  
+  if(status == FLASH_COMPLETE)
+  {
+    /* Authorizes the small information block programming */
+    FLASH->OPTKEYR = FLASH_KEY1;
+    FLASH->OPTKEYR = FLASH_KEY2;
+    FLASH->CR |= CR_OPTPG_Set;
+    if(WRP0_Data != 0xFF)
+    {
+      OB->WRP0 = WRP0_Data;
+      
+      /* Wait for last operation to be completed */
+      status = FLASH_WaitForLastOperation(ProgramTimeout);
+    }
+    if((status == FLASH_COMPLETE) && (WRP1_Data != 0xFF))
+    {
+      OB->WRP1 = WRP1_Data;
+      
+      /* Wait for last operation to be completed */
+      status = FLASH_WaitForLastOperation(ProgramTimeout);
+    }
+    if((status == FLASH_COMPLETE) && (WRP2_Data != 0xFF))
+    {
+      OB->WRP2 = WRP2_Data;
+      
+      /* Wait for last operation to be completed */
+      status = FLASH_WaitForLastOperation(ProgramTimeout);
+    }
+    
+    if((status == FLASH_COMPLETE)&& (WRP3_Data != 0xFF))
+    {
+      OB->WRP3 = WRP3_Data;
+     
+      /* Wait for last operation to be completed */
+      status = FLASH_WaitForLastOperation(ProgramTimeout);
+    }
+          
+    if(status != FLASH_TIMEOUT)
+    {
+      /* if the program operation is completed, disable the OPTPG Bit */
+      FLASH->CR &= CR_OPTPG_Reset;
+    }
+  } 
+  /* Return the write protection operation Status */
+  return status;       
+}
+
+/**
+  * @brief  Enables or disables the read out protection.
+  * @note   If the user has already programmed the other option bytes before calling 
+  *   this function, he must re-program them since this function erases all option bytes.
+  * @note   This function can be used for all STM32F10x devices.
+  * @param  Newstate: new state of the ReadOut Protection.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG,
+  *         FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
+  */
+FLASH_Status FLASH_ReadOutProtection(FunctionalState NewState)
+{
+  FLASH_Status status = FLASH_COMPLETE;
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  status = FLASH_WaitForLastOperation(EraseTimeout);
+  if(status == FLASH_COMPLETE)
+  {
+    /* Authorizes the small information block programming */
+    FLASH->OPTKEYR = FLASH_KEY1;
+    FLASH->OPTKEYR = FLASH_KEY2;
+    FLASH->CR |= CR_OPTER_Set;
+    FLASH->CR |= CR_STRT_Set;
+    /* Wait for last operation to be completed */
+    status = FLASH_WaitForLastOperation(EraseTimeout);
+    if(status == FLASH_COMPLETE)
+    {
+      /* if the erase operation is completed, disable the OPTER Bit */
+      FLASH->CR &= CR_OPTER_Reset;
+      /* Enable the Option Bytes Programming operation */
+      FLASH->CR |= CR_OPTPG_Set; 
+      if(NewState != DISABLE)
+      {
+        OB->RDP = 0x00;
+      }
+      else
+      {
+        OB->RDP = RDP_Key;  
+      }
+      /* Wait for last operation to be completed */
+      status = FLASH_WaitForLastOperation(EraseTimeout); 
+    
+      if(status != FLASH_TIMEOUT)
+      {
+        /* if the program operation is completed, disable the OPTPG Bit */
+        FLASH->CR &= CR_OPTPG_Reset;
+      }
+    }
+    else 
+    {
+      if(status != FLASH_TIMEOUT)
+      {
+        /* Disable the OPTER Bit */
+        FLASH->CR &= CR_OPTER_Reset;
+      }
+    }
+  }
+  /* Return the protection operation Status */
+  return status;       
+}
+
+/**
+  * @brief  Programs the FLASH User Option Byte: IWDG_SW / RST_STOP / RST_STDBY.
+  * @note   This function can be used for all STM32F10x devices.
+  * @param  OB_IWDG: Selects the IWDG mode
+  *   This parameter can be one of the following values:
+  *     @arg OB_IWDG_SW: Software IWDG selected
+  *     @arg OB_IWDG_HW: Hardware IWDG selected
+  * @param  OB_STOP: Reset event when entering STOP mode.
+  *   This parameter can be one of the following values:
+  *     @arg OB_STOP_NoRST: No reset generated when entering in STOP
+  *     @arg OB_STOP_RST: Reset generated when entering in STOP
+  * @param  OB_STDBY: Reset event when entering Standby mode.
+  *   This parameter can be one of the following values:
+  *     @arg OB_STDBY_NoRST: No reset generated when entering in STANDBY
+  *     @arg OB_STDBY_RST: Reset generated when entering in STANDBY
+  * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG, 
+  *         FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
+  */
+FLASH_Status FLASH_UserOptionByteConfig(uint16_t OB_IWDG, uint16_t OB_STOP, uint16_t OB_STDBY)
+{
+  FLASH_Status status = FLASH_COMPLETE; 
+
+  /* Check the parameters */
+  assert_param(IS_OB_IWDG_SOURCE(OB_IWDG));
+  assert_param(IS_OB_STOP_SOURCE(OB_STOP));
+  assert_param(IS_OB_STDBY_SOURCE(OB_STDBY));
+
+  /* Authorize the small information block programming */
+  FLASH->OPTKEYR = FLASH_KEY1;
+  FLASH->OPTKEYR = FLASH_KEY2;
+  
+  /* Wait for last operation to be completed */
+  status = FLASH_WaitForLastOperation(ProgramTimeout);
+  
+  if(status == FLASH_COMPLETE)
+  {  
+    /* Enable the Option Bytes Programming operation */
+    FLASH->CR |= CR_OPTPG_Set; 
+           
+    OB->USER = OB_IWDG | (uint16_t)(OB_STOP | (uint16_t)(OB_STDBY | ((uint16_t)0xF8))); 
+  
+    /* Wait for last operation to be completed */
+    status = FLASH_WaitForLastOperation(ProgramTimeout);
+    if(status != FLASH_TIMEOUT)
+    {
+      /* if the program operation is completed, disable the OPTPG Bit */
+      FLASH->CR &= CR_OPTPG_Reset;
+    }
+  }    
+  /* Return the Option Byte program Status */
+  return status;
+}
+
+#ifdef STM32F10X_XL
+/**
+  * @brief  Configures to boot from Bank1 or Bank2.  
+  * @note   This function can be used only for STM32F10x_XL density devices.
+  * @param  FLASH_BOOT: select the FLASH Bank to boot from.
+  *   This parameter can be one of the following values:
+  *     @arg FLASH_BOOT_Bank1: At startup, if boot pins are set in boot from user Flash
+  *        position and this parameter is selected the device will boot from Bank1(Default).
+  *     @arg FLASH_BOOT_Bank2: At startup, if boot pins are set in boot from user Flash
+  *        position and this parameter is selected the device will boot from Bank2 or Bank1,
+  *        depending on the activation of the bank. The active banks are checked in
+  *        the following order: Bank2, followed by Bank1.
+  *        The active bank is recognized by the value programmed at the base address
+  *        of the respective bank (corresponding to the initial stack pointer value
+  *        in the interrupt vector table).
+  *        For more information, please refer to AN2606 from www.st.com.    
+  * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG, 
+  *         FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
+  */
+FLASH_Status FLASH_BootConfig(uint16_t FLASH_BOOT)
+{ 
+  FLASH_Status status = FLASH_COMPLETE; 
+  assert_param(IS_FLASH_BOOT(FLASH_BOOT));
+  /* Authorize the small information block programming */
+  FLASH->OPTKEYR = FLASH_KEY1;
+  FLASH->OPTKEYR = FLASH_KEY2;
+  
+  /* Wait for last operation to be completed */
+  status = FLASH_WaitForLastOperation(ProgramTimeout);
+  
+  if(status == FLASH_COMPLETE)
+  {  
+    /* Enable the Option Bytes Programming operation */
+    FLASH->CR |= CR_OPTPG_Set; 
+
+    if(FLASH_BOOT == FLASH_BOOT_Bank1)
+    {
+      OB->USER |= OB_USER_BFB2;
+    }
+    else
+    {
+      OB->USER &= (uint16_t)(~(uint16_t)(OB_USER_BFB2));
+    }
+    /* Wait for last operation to be completed */
+    status = FLASH_WaitForLastOperation(ProgramTimeout);
+    if(status != FLASH_TIMEOUT)
+    {
+      /* if the program operation is completed, disable the OPTPG Bit */
+      FLASH->CR &= CR_OPTPG_Reset;
+    }
+  }    
+  /* Return the Option Byte program Status */
+  return status;
+}
+#endif /* STM32F10X_XL */
+
+/**
+  * @brief  Returns the FLASH User Option Bytes values.
+  * @note   This function can be used for all STM32F10x devices.
+  * @param  None
+  * @retval The FLASH User Option Bytes values:IWDG_SW(Bit0), RST_STOP(Bit1)
+  *         and RST_STDBY(Bit2).
+  */
+uint32_t FLASH_GetUserOptionByte(void)
+{
+  /* Return the User Option Byte */
+  return (uint32_t)(FLASH->OBR >> 2);
+}
+
+/**
+  * @brief  Returns the FLASH Write Protection Option Bytes Register value.
+  * @note   This function can be used for all STM32F10x devices.
+  * @param  None
+  * @retval The FLASH Write Protection  Option Bytes Register value
+  */
+uint32_t FLASH_GetWriteProtectionOptionByte(void)
+{
+  /* Return the Flash write protection Register value */
+  return (uint32_t)(FLASH->WRPR);
+}
+
+/**
+  * @brief  Checks whether the FLASH Read Out Protection Status is set or not.
+  * @note   This function can be used for all STM32F10x devices.
+  * @param  None
+  * @retval FLASH ReadOut Protection Status(SET or RESET)
+  */
+FlagStatus FLASH_GetReadOutProtectionStatus(void)
+{
+  FlagStatus readoutstatus = RESET;
+  if ((FLASH->OBR & RDPRT_Mask) != (uint32_t)RESET)
+  {
+    readoutstatus = SET;
+  }
+  else
+  {
+    readoutstatus = RESET;
+  }
+  return readoutstatus;
+}
+
+/**
+  * @brief  Checks whether the FLASH Prefetch Buffer status is set or not.
+  * @note   This function can be used for all STM32F10x devices.
+  * @param  None
+  * @retval FLASH Prefetch Buffer Status (SET or RESET).
+  */
+FlagStatus FLASH_GetPrefetchBufferStatus(void)
+{
+  FlagStatus bitstatus = RESET;
+  
+  if ((FLASH->ACR & ACR_PRFTBS_Mask) != (uint32_t)RESET)
+  {
+    bitstatus = SET;
+  }
+  else
+  {
+    bitstatus = RESET;
+  }
+  /* Return the new state of FLASH Prefetch Buffer Status (SET or RESET) */
+  return bitstatus; 
+}
+
+/**
+  * @brief  Enables or disables the specified FLASH interrupts.
+  * @note   This function can be used for all STM32F10x devices.
+  *         - For STM32F10X_XL devices, enables or disables the specified FLASH interrupts
+              for Bank1 and Bank2.
+  *         - For other devices it enables or disables the specified FLASH interrupts for Bank1.
+  * @param  FLASH_IT: specifies the FLASH interrupt sources to be enabled or disabled.
+  *   This parameter can be any combination of the following values:
+  *     @arg FLASH_IT_ERROR: FLASH Error Interrupt
+  *     @arg FLASH_IT_EOP: FLASH end of operation Interrupt
+  * @param  NewState: new state of the specified Flash interrupts.
+  *   This parameter can be: ENABLE or DISABLE.      
+  * @retval None 
+  */
+void FLASH_ITConfig(uint32_t FLASH_IT, FunctionalState NewState)
+{
+#ifdef STM32F10X_XL
+  /* Check the parameters */
+  assert_param(IS_FLASH_IT(FLASH_IT)); 
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if((FLASH_IT & 0x80000000) != 0x0)
+  {
+    if(NewState != DISABLE)
+    {
+      /* Enable the interrupt sources */
+      FLASH->CR2 |= (FLASH_IT & 0x7FFFFFFF);
+    }
+    else
+    {
+      /* Disable the interrupt sources */
+      FLASH->CR2 &= ~(uint32_t)(FLASH_IT & 0x7FFFFFFF);
+    }
+  }
+  else
+  {
+    if(NewState != DISABLE)
+    {
+      /* Enable the interrupt sources */
+      FLASH->CR |= FLASH_IT;
+    }
+    else
+    {
+      /* Disable the interrupt sources */
+      FLASH->CR &= ~(uint32_t)FLASH_IT;
+    }
+  }
+#else
+  /* Check the parameters */
+  assert_param(IS_FLASH_IT(FLASH_IT)); 
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if(NewState != DISABLE)
+  {
+    /* Enable the interrupt sources */
+    FLASH->CR |= FLASH_IT;
+  }
+  else
+  {
+    /* Disable the interrupt sources */
+    FLASH->CR &= ~(uint32_t)FLASH_IT;
+  }
+#endif /* STM32F10X_XL */
+}
+
+/**
+  * @brief  Checks whether the specified FLASH flag is set or not.
+  * @note   This function can be used for all STM32F10x devices.
+  *         - For STM32F10X_XL devices, this function checks whether the specified 
+  *           Bank1 or Bank2 flag is set or not.
+  *         - For other devices, it checks whether the specified Bank1 flag is 
+  *           set or not.
+  * @param  FLASH_FLAG: specifies the FLASH flag to check.
+  *   This parameter can be one of the following values:
+  *     @arg FLASH_FLAG_BSY: FLASH Busy flag           
+  *     @arg FLASH_FLAG_PGERR: FLASH Program error flag       
+  *     @arg FLASH_FLAG_WRPRTERR: FLASH Write protected error flag      
+  *     @arg FLASH_FLAG_EOP: FLASH End of Operation flag           
+  *     @arg FLASH_FLAG_OPTERR:  FLASH Option Byte error flag     
+  * @retval The new state of FLASH_FLAG (SET or RESET).
+  */
+FlagStatus FLASH_GetFlagStatus(uint32_t FLASH_FLAG)
+{
+  FlagStatus bitstatus = RESET;
+
+#ifdef STM32F10X_XL
+  /* Check the parameters */
+  assert_param(IS_FLASH_GET_FLAG(FLASH_FLAG)) ;
+  if(FLASH_FLAG == FLASH_FLAG_OPTERR) 
+  {
+    if((FLASH->OBR & FLASH_FLAG_OPTERR) != (uint32_t)RESET)
+    {
+      bitstatus = SET;
+    }
+    else
+    {
+      bitstatus = RESET;
+    }
+  }
+  else
+  {
+    if((FLASH_FLAG & 0x80000000) != 0x0)
+    {
+      if((FLASH->SR2 & FLASH_FLAG) != (uint32_t)RESET)
+      {
+        bitstatus = SET;
+      }
+      else
+      {
+        bitstatus = RESET;
+      }
+    }
+    else
+    {
+      if((FLASH->SR & FLASH_FLAG) != (uint32_t)RESET)
+      {
+        bitstatus = SET;
+      }
+      else
+      {
+        bitstatus = RESET;
+      }
+    }
+  }
+#else
+  /* Check the parameters */
+  assert_param(IS_FLASH_GET_FLAG(FLASH_FLAG)) ;
+  if(FLASH_FLAG == FLASH_FLAG_OPTERR) 
+  {
+    if((FLASH->OBR & FLASH_FLAG_OPTERR) != (uint32_t)RESET)
+    {
+      bitstatus = SET;
+    }
+    else
+    {
+      bitstatus = RESET;
+    }
+  }
+  else
+  {
+   if((FLASH->SR & FLASH_FLAG) != (uint32_t)RESET)
+    {
+      bitstatus = SET;
+    }
+    else
+    {
+      bitstatus = RESET;
+    }
+  }
+#endif /* STM32F10X_XL */
+
+  /* Return the new state of FLASH_FLAG (SET or RESET) */
+  return bitstatus;
+}
+
+/**
+  * @brief  Clears the FLASH's pending flags.
+  * @note   This function can be used for all STM32F10x devices.
+  *         - For STM32F10X_XL devices, this function clears Bank1 or Bank2�s pending flags
+  *         - For other devices, it clears Bank1�s pending flags.
+  * @param  FLASH_FLAG: specifies the FLASH flags to clear.
+  *   This parameter can be any combination of the following values:         
+  *     @arg FLASH_FLAG_PGERR: FLASH Program error flag       
+  *     @arg FLASH_FLAG_WRPRTERR: FLASH Write protected error flag      
+  *     @arg FLASH_FLAG_EOP: FLASH End of Operation flag           
+  * @retval None
+  */
+void FLASH_ClearFlag(uint32_t FLASH_FLAG)
+{
+#ifdef STM32F10X_XL
+  /* Check the parameters */
+  assert_param(IS_FLASH_CLEAR_FLAG(FLASH_FLAG)) ;
+
+  if((FLASH_FLAG & 0x80000000) != 0x0)
+  {
+    /* Clear the flags */
+    FLASH->SR2 = FLASH_FLAG;
+  }
+  else
+  {
+    /* Clear the flags */
+    FLASH->SR = FLASH_FLAG;
+  }  
+
+#else
+  /* Check the parameters */
+  assert_param(IS_FLASH_CLEAR_FLAG(FLASH_FLAG)) ;
+  
+  /* Clear the flags */
+  FLASH->SR = FLASH_FLAG;
+#endif /* STM32F10X_XL */
+}
+
+/**
+  * @brief  Returns the FLASH Status.
+  * @note   This function can be used for all STM32F10x devices, it is equivalent
+  *         to FLASH_GetBank1Status function.
+  * @param  None
+  * @retval FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERROR_PG,
+  *         FLASH_ERROR_WRP or FLASH_COMPLETE
+  */
+FLASH_Status FLASH_GetStatus(void)
+{
+  FLASH_Status flashstatus = FLASH_COMPLETE;
+  
+  if((FLASH->SR & FLASH_FLAG_BSY) == FLASH_FLAG_BSY) 
+  {
+    flashstatus = FLASH_BUSY;
+  }
+  else 
+  {  
+    if((FLASH->SR & FLASH_FLAG_PGERR) != 0)
+    { 
+      flashstatus = FLASH_ERROR_PG;
+    }
+    else 
+    {
+      if((FLASH->SR & FLASH_FLAG_WRPRTERR) != 0 )
+      {
+        flashstatus = FLASH_ERROR_WRP;
+      }
+      else
+      {
+        flashstatus = FLASH_COMPLETE;
+      }
+    }
+  }
+  /* Return the Flash Status */
+  return flashstatus;
+}
+
+/**
+  * @brief  Returns the FLASH Bank1 Status.
+  * @note   This function can be used for all STM32F10x devices, it is equivalent
+  *         to FLASH_GetStatus function.
+  * @param  None
+  * @retval FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERROR_PG,
+  *         FLASH_ERROR_WRP or FLASH_COMPLETE
+  */
+FLASH_Status FLASH_GetBank1Status(void)
+{
+  FLASH_Status flashstatus = FLASH_COMPLETE;
+  
+  if((FLASH->SR & FLASH_FLAG_BANK1_BSY) == FLASH_FLAG_BSY) 
+  {
+    flashstatus = FLASH_BUSY;
+  }
+  else 
+  {  
+    if((FLASH->SR & FLASH_FLAG_BANK1_PGERR) != 0)
+    { 
+      flashstatus = FLASH_ERROR_PG;
+    }
+    else 
+    {
+      if((FLASH->SR & FLASH_FLAG_BANK1_WRPRTERR) != 0 )
+      {
+        flashstatus = FLASH_ERROR_WRP;
+      }
+      else
+      {
+        flashstatus = FLASH_COMPLETE;
+      }
+    }
+  }
+  /* Return the Flash Status */
+  return flashstatus;
+}
+
+#ifdef STM32F10X_XL
+/**
+  * @brief  Returns the FLASH Bank2 Status.
+  * @note   This function can be used for STM32F10x_XL density devices.
+  * @param  None
+  * @retval FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERROR_PG,
+  *        FLASH_ERROR_WRP or FLASH_COMPLETE
+  */
+FLASH_Status FLASH_GetBank2Status(void)
+{
+  FLASH_Status flashstatus = FLASH_COMPLETE;
+  
+  if((FLASH->SR2 & (FLASH_FLAG_BANK2_BSY & 0x7FFFFFFF)) == (FLASH_FLAG_BANK2_BSY & 0x7FFFFFFF)) 
+  {
+    flashstatus = FLASH_BUSY;
+  }
+  else 
+  {  
+    if((FLASH->SR2 & (FLASH_FLAG_BANK2_PGERR & 0x7FFFFFFF)) != 0)
+    { 
+      flashstatus = FLASH_ERROR_PG;
+    }
+    else 
+    {
+      if((FLASH->SR2 & (FLASH_FLAG_BANK2_WRPRTERR & 0x7FFFFFFF)) != 0 )
+      {
+        flashstatus = FLASH_ERROR_WRP;
+      }
+      else
+      {
+        flashstatus = FLASH_COMPLETE;
+      }
+    }
+  }
+  /* Return the Flash Status */
+  return flashstatus;
+}
+#endif /* STM32F10X_XL */
+/**
+  * @brief  Waits for a Flash operation to complete or a TIMEOUT to occur.
+  * @note   This function can be used for all STM32F10x devices, 
+  *         it is equivalent to FLASH_WaitForLastBank1Operation.
+  *         - For STM32F10X_XL devices this function waits for a Bank1 Flash operation
+  *           to complete or a TIMEOUT to occur.
+  *         - For all other devices it waits for a Flash operation to complete 
+  *           or a TIMEOUT to occur.
+  * @param  Timeout: FLASH programming Timeout
+  * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG,
+  *         FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
+  */
+FLASH_Status FLASH_WaitForLastOperation(uint32_t Timeout)
+{ 
+  FLASH_Status status = FLASH_COMPLETE;
+   
+  /* Check for the Flash Status */
+  status = FLASH_GetBank1Status();
+  /* Wait for a Flash operation to complete or a TIMEOUT to occur */
+  while((status == FLASH_BUSY) && (Timeout != 0x00))
+  {
+    status = FLASH_GetBank1Status();
+    Timeout--;
+  }
+  if(Timeout == 0x00 )
+  {
+    status = FLASH_TIMEOUT;
+  }
+  /* Return the operation status */
+  return status;
+}
+
+/**
+  * @brief  Waits for a Flash operation on Bank1 to complete or a TIMEOUT to occur.
+  * @note   This function can be used for all STM32F10x devices, 
+  *         it is equivalent to FLASH_WaitForLastOperation.
+  * @param  Timeout: FLASH programming Timeout
+  * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG,
+  *         FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
+  */
+FLASH_Status FLASH_WaitForLastBank1Operation(uint32_t Timeout)
+{ 
+  FLASH_Status status = FLASH_COMPLETE;
+   
+  /* Check for the Flash Status */
+  status = FLASH_GetBank1Status();
+  /* Wait for a Flash operation to complete or a TIMEOUT to occur */
+  while((status == FLASH_FLAG_BANK1_BSY) && (Timeout != 0x00))
+  {
+    status = FLASH_GetBank1Status();
+    Timeout--;
+  }
+  if(Timeout == 0x00 )
+  {
+    status = FLASH_TIMEOUT;
+  }
+  /* Return the operation status */
+  return status;
+}
+
+#ifdef STM32F10X_XL
+/**
+  * @brief  Waits for a Flash operation on Bank2 to complete or a TIMEOUT to occur.
+  * @note   This function can be used only for STM32F10x_XL density devices.
+  * @param  Timeout: FLASH programming Timeout
+  * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG,
+  *         FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
+  */
+FLASH_Status FLASH_WaitForLastBank2Operation(uint32_t Timeout)
+{ 
+  FLASH_Status status = FLASH_COMPLETE;
+   
+  /* Check for the Flash Status */
+  status = FLASH_GetBank2Status();
+  /* Wait for a Flash operation to complete or a TIMEOUT to occur */
+  while((status == (FLASH_FLAG_BANK2_BSY & 0x7FFFFFFF)) && (Timeout != 0x00))
+  {
+    status = FLASH_GetBank2Status();
+    Timeout--;
+  }
+  if(Timeout == 0x00 )
+  {
+    status = FLASH_TIMEOUT;
+  }
+  /* Return the operation status */
+  return status;
+}
+#endif /* STM32F10X_XL */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/STM32_4路称重_Git提交精简工程/src/STM32F10x_FWLib/src/stm32f10x_fsmc.c b/STM32_4路称重_Git提交精简工程/src/STM32F10x_FWLib/src/stm32f10x_fsmc.c
new file mode 100755
index 0000000..c75137c
--- /dev/null
+++ b/STM32_4路称重_Git提交精简工程/src/STM32F10x_FWLib/src/stm32f10x_fsmc.c
@@ -0,0 +1,866 @@
+/**
+  ******************************************************************************
+  * @file    stm32f10x_fsmc.c
+  * @author  MCD Application Team
+  * @version V3.5.0
+  * @date    11-March-2011
+  * @brief   This file provides all the FSMC firmware functions.
+  ******************************************************************************
+  * @attention
+  *
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+  *
+  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x_fsmc.h"
+#include "stm32f10x_rcc.h"
+
+/** @addtogroup STM32F10x_StdPeriph_Driver
+  * @{
+  */
+
+/** @defgroup FSMC 
+  * @brief FSMC driver modules
+  * @{
+  */ 
+
+/** @defgroup FSMC_Private_TypesDefinitions
+  * @{
+  */ 
+/**
+  * @}
+  */
+
+/** @defgroup FSMC_Private_Defines
+  * @{
+  */
+
+/* --------------------- FSMC registers bit mask ---------------------------- */
+
+/* FSMC BCRx Mask */
+#define BCR_MBKEN_Set                       ((uint32_t)0x00000001)
+#define BCR_MBKEN_Reset                     ((uint32_t)0x000FFFFE)
+#define BCR_FACCEN_Set                      ((uint32_t)0x00000040)
+
+/* FSMC PCRx Mask */
+#define PCR_PBKEN_Set                       ((uint32_t)0x00000004)
+#define PCR_PBKEN_Reset                     ((uint32_t)0x000FFFFB)
+#define PCR_ECCEN_Set                       ((uint32_t)0x00000040)
+#define PCR_ECCEN_Reset                     ((uint32_t)0x000FFFBF)
+#define PCR_MemoryType_NAND                 ((uint32_t)0x00000008)
+/**
+  * @}
+  */
+
+/** @defgroup FSMC_Private_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup FSMC_Private_Variables
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup FSMC_Private_FunctionPrototypes
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup FSMC_Private_Functions
+  * @{
+  */
+
+/**
+  * @brief  Deinitializes the FSMC NOR/SRAM Banks registers to their default 
+  *         reset values.
+  * @param  FSMC_Bank: specifies the FSMC Bank to be used
+  *   This parameter can be one of the following values:
+  *     @arg FSMC_Bank1_NORSRAM1: FSMC Bank1 NOR/SRAM1  
+  *     @arg FSMC_Bank1_NORSRAM2: FSMC Bank1 NOR/SRAM2 
+  *     @arg FSMC_Bank1_NORSRAM3: FSMC Bank1 NOR/SRAM3 
+  *     @arg FSMC_Bank1_NORSRAM4: FSMC Bank1 NOR/SRAM4 
+  * @retval None
+  */
+void FSMC_NORSRAMDeInit(uint32_t FSMC_Bank)
+{
+  /* Check the parameter */
+  assert_param(IS_FSMC_NORSRAM_BANK(FSMC_Bank));
+  
+  /* FSMC_Bank1_NORSRAM1 */
+  if(FSMC_Bank == FSMC_Bank1_NORSRAM1)
+  {
+    FSMC_Bank1->BTCR[FSMC_Bank] = 0x000030DB;    
+  }
+  /* FSMC_Bank1_NORSRAM2,  FSMC_Bank1_NORSRAM3 or FSMC_Bank1_NORSRAM4 */
+  else
+  {   
+    FSMC_Bank1->BTCR[FSMC_Bank] = 0x000030D2; 
+  }
+  FSMC_Bank1->BTCR[FSMC_Bank + 1] = 0x0FFFFFFF;
+  FSMC_Bank1E->BWTR[FSMC_Bank] = 0x0FFFFFFF;  
+}
+
+/**
+  * @brief  Deinitializes the FSMC NAND Banks registers to their default reset values.
+  * @param  FSMC_Bank: specifies the FSMC Bank to be used
+  *   This parameter can be one of the following values:
+  *     @arg FSMC_Bank2_NAND: FSMC Bank2 NAND 
+  *     @arg FSMC_Bank3_NAND: FSMC Bank3 NAND 
+  * @retval None
+  */
+void FSMC_NANDDeInit(uint32_t FSMC_Bank)
+{
+  /* Check the parameter */
+  assert_param(IS_FSMC_NAND_BANK(FSMC_Bank));
+  
+  if(FSMC_Bank == FSMC_Bank2_NAND)
+  {
+    /* Set the FSMC_Bank2 registers to their reset values */
+    FSMC_Bank2->PCR2 = 0x00000018;
+    FSMC_Bank2->SR2 = 0x00000040;
+    FSMC_Bank2->PMEM2 = 0xFCFCFCFC;
+    FSMC_Bank2->PATT2 = 0xFCFCFCFC;  
+  }
+  /* FSMC_Bank3_NAND */  
+  else
+  {
+    /* Set the FSMC_Bank3 registers to their reset values */
+    FSMC_Bank3->PCR3 = 0x00000018;
+    FSMC_Bank3->SR3 = 0x00000040;
+    FSMC_Bank3->PMEM3 = 0xFCFCFCFC;
+    FSMC_Bank3->PATT3 = 0xFCFCFCFC; 
+  }  
+}
+
+/**
+  * @brief  Deinitializes the FSMC PCCARD Bank registers to their default reset values.
+  * @param  None                       
+  * @retval None
+  */
+void FSMC_PCCARDDeInit(void)
+{
+  /* Set the FSMC_Bank4 registers to their reset values */
+  FSMC_Bank4->PCR4 = 0x00000018; 
+  FSMC_Bank4->SR4 = 0x00000000;	
+  FSMC_Bank4->PMEM4 = 0xFCFCFCFC;
+  FSMC_Bank4->PATT4 = 0xFCFCFCFC;
+  FSMC_Bank4->PIO4 = 0xFCFCFCFC;
+}
+
+/**
+  * @brief  Initializes the FSMC NOR/SRAM Banks according to the specified
+  *         parameters in the FSMC_NORSRAMInitStruct.
+  * @param  FSMC_NORSRAMInitStruct : pointer to a FSMC_NORSRAMInitTypeDef
+  *         structure that contains the configuration information for 
+  *        the FSMC NOR/SRAM specified Banks.                       
+  * @retval None
+  */
+void FSMC_NORSRAMInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct)
+{ 
+  /* Check the parameters */
+  assert_param(IS_FSMC_NORSRAM_BANK(FSMC_NORSRAMInitStruct->FSMC_Bank));
+  assert_param(IS_FSMC_MUX(FSMC_NORSRAMInitStruct->FSMC_DataAddressMux));
+  assert_param(IS_FSMC_MEMORY(FSMC_NORSRAMInitStruct->FSMC_MemoryType));
+  assert_param(IS_FSMC_MEMORY_WIDTH(FSMC_NORSRAMInitStruct->FSMC_MemoryDataWidth));
+  assert_param(IS_FSMC_BURSTMODE(FSMC_NORSRAMInitStruct->FSMC_BurstAccessMode));
+  assert_param(IS_FSMC_ASYNWAIT(FSMC_NORSRAMInitStruct->FSMC_AsynchronousWait));
+  assert_param(IS_FSMC_WAIT_POLARITY(FSMC_NORSRAMInitStruct->FSMC_WaitSignalPolarity));
+  assert_param(IS_FSMC_WRAP_MODE(FSMC_NORSRAMInitStruct->FSMC_WrapMode));
+  assert_param(IS_FSMC_WAIT_SIGNAL_ACTIVE(FSMC_NORSRAMInitStruct->FSMC_WaitSignalActive));
+  assert_param(IS_FSMC_WRITE_OPERATION(FSMC_NORSRAMInitStruct->FSMC_WriteOperation));
+  assert_param(IS_FSMC_WAITE_SIGNAL(FSMC_NORSRAMInitStruct->FSMC_WaitSignal));
+  assert_param(IS_FSMC_EXTENDED_MODE(FSMC_NORSRAMInitStruct->FSMC_ExtendedMode));
+  assert_param(IS_FSMC_WRITE_BURST(FSMC_NORSRAMInitStruct->FSMC_WriteBurst));  
+  assert_param(IS_FSMC_ADDRESS_SETUP_TIME(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressSetupTime));
+  assert_param(IS_FSMC_ADDRESS_HOLD_TIME(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressHoldTime));
+  assert_param(IS_FSMC_DATASETUP_TIME(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataSetupTime));
+  assert_param(IS_FSMC_TURNAROUND_TIME(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_BusTurnAroundDuration));
+  assert_param(IS_FSMC_CLK_DIV(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_CLKDivision));
+  assert_param(IS_FSMC_DATA_LATENCY(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataLatency));
+  assert_param(IS_FSMC_ACCESS_MODE(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AccessMode)); 
+  
+  /* Bank1 NOR/SRAM control register configuration */ 
+  FSMC_Bank1->BTCR[FSMC_NORSRAMInitStruct->FSMC_Bank] = 
+            (uint32_t)FSMC_NORSRAMInitStruct->FSMC_DataAddressMux |
+            FSMC_NORSRAMInitStruct->FSMC_MemoryType |
+            FSMC_NORSRAMInitStruct->FSMC_MemoryDataWidth |
+            FSMC_NORSRAMInitStruct->FSMC_BurstAccessMode |
+            FSMC_NORSRAMInitStruct->FSMC_AsynchronousWait |
+            FSMC_NORSRAMInitStruct->FSMC_WaitSignalPolarity |
+            FSMC_NORSRAMInitStruct->FSMC_WrapMode |
+            FSMC_NORSRAMInitStruct->FSMC_WaitSignalActive |
+            FSMC_NORSRAMInitStruct->FSMC_WriteOperation |
+            FSMC_NORSRAMInitStruct->FSMC_WaitSignal |
+            FSMC_NORSRAMInitStruct->FSMC_ExtendedMode |
+            FSMC_NORSRAMInitStruct->FSMC_WriteBurst;
+
+  if(FSMC_NORSRAMInitStruct->FSMC_MemoryType == FSMC_MemoryType_NOR)
+  {
+    FSMC_Bank1->BTCR[FSMC_NORSRAMInitStruct->FSMC_Bank] |= (uint32_t)BCR_FACCEN_Set;
+  }
+  
+  /* Bank1 NOR/SRAM timing register configuration */
+  FSMC_Bank1->BTCR[FSMC_NORSRAMInitStruct->FSMC_Bank+1] = 
+            (uint32_t)FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressSetupTime |
+            (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressHoldTime << 4) |
+            (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataSetupTime << 8) |
+            (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_BusTurnAroundDuration << 16) |
+            (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_CLKDivision << 20) |
+            (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataLatency << 24) |
+             FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AccessMode;
+            
+    
+  /* Bank1 NOR/SRAM timing register for write configuration, if extended mode is used */
+  if(FSMC_NORSRAMInitStruct->FSMC_ExtendedMode == FSMC_ExtendedMode_Enable)
+  {
+    assert_param(IS_FSMC_ADDRESS_SETUP_TIME(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressSetupTime));
+    assert_param(IS_FSMC_ADDRESS_HOLD_TIME(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressHoldTime));
+    assert_param(IS_FSMC_DATASETUP_TIME(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataSetupTime));
+    assert_param(IS_FSMC_CLK_DIV(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_CLKDivision));
+    assert_param(IS_FSMC_DATA_LATENCY(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataLatency));
+    assert_param(IS_FSMC_ACCESS_MODE(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AccessMode));
+    FSMC_Bank1E->BWTR[FSMC_NORSRAMInitStruct->FSMC_Bank] = 
+              (uint32_t)FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressSetupTime |
+              (FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressHoldTime << 4 )|
+              (FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataSetupTime << 8) |
+              (FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_CLKDivision << 20) |
+              (FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataLatency << 24) |
+               FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AccessMode;
+  }
+  else
+  {
+    FSMC_Bank1E->BWTR[FSMC_NORSRAMInitStruct->FSMC_Bank] = 0x0FFFFFFF;
+  }
+}
+
+/**
+  * @brief  Initializes the FSMC NAND Banks according to the specified 
+  *         parameters in the FSMC_NANDInitStruct.
+  * @param  FSMC_NANDInitStruct : pointer to a FSMC_NANDInitTypeDef 
+  *         structure that contains the configuration information for the FSMC 
+  *         NAND specified Banks.                       
+  * @retval None
+  */
+void FSMC_NANDInit(FSMC_NANDInitTypeDef* FSMC_NANDInitStruct)
+{
+  uint32_t tmppcr = 0x00000000, tmppmem = 0x00000000, tmppatt = 0x00000000; 
+    
+  /* Check the parameters */
+  assert_param( IS_FSMC_NAND_BANK(FSMC_NANDInitStruct->FSMC_Bank));
+  assert_param( IS_FSMC_WAIT_FEATURE(FSMC_NANDInitStruct->FSMC_Waitfeature));
+  assert_param( IS_FSMC_MEMORY_WIDTH(FSMC_NANDInitStruct->FSMC_MemoryDataWidth));
+  assert_param( IS_FSMC_ECC_STATE(FSMC_NANDInitStruct->FSMC_ECC));
+  assert_param( IS_FSMC_ECCPAGE_SIZE(FSMC_NANDInitStruct->FSMC_ECCPageSize));
+  assert_param( IS_FSMC_TCLR_TIME(FSMC_NANDInitStruct->FSMC_TCLRSetupTime));
+  assert_param( IS_FSMC_TAR_TIME(FSMC_NANDInitStruct->FSMC_TARSetupTime));
+  assert_param(IS_FSMC_SETUP_TIME(FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime));
+  assert_param(IS_FSMC_WAIT_TIME(FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime));
+  assert_param(IS_FSMC_HOLD_TIME(FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime));
+  assert_param(IS_FSMC_HIZ_TIME(FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime));
+  assert_param(IS_FSMC_SETUP_TIME(FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime));
+  assert_param(IS_FSMC_WAIT_TIME(FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime));
+  assert_param(IS_FSMC_HOLD_TIME(FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime));
+  assert_param(IS_FSMC_HIZ_TIME(FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime));
+  
+  /* Set the tmppcr value according to FSMC_NANDInitStruct parameters */
+  tmppcr = (uint32_t)FSMC_NANDInitStruct->FSMC_Waitfeature |
+            PCR_MemoryType_NAND |
+            FSMC_NANDInitStruct->FSMC_MemoryDataWidth |
+            FSMC_NANDInitStruct->FSMC_ECC |
+            FSMC_NANDInitStruct->FSMC_ECCPageSize |
+            (FSMC_NANDInitStruct->FSMC_TCLRSetupTime << 9 )|
+            (FSMC_NANDInitStruct->FSMC_TARSetupTime << 13);
+            
+  /* Set tmppmem value according to FSMC_CommonSpaceTimingStructure parameters */
+  tmppmem = (uint32_t)FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime |
+            (FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime << 8) |
+            (FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime << 16)|
+            (FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime << 24); 
+            
+  /* Set tmppatt value according to FSMC_AttributeSpaceTimingStructure parameters */
+  tmppatt = (uint32_t)FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime |
+            (FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime << 8) |
+            (FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime << 16)|
+            (FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime << 24);
+  
+  if(FSMC_NANDInitStruct->FSMC_Bank == FSMC_Bank2_NAND)
+  {
+    /* FSMC_Bank2_NAND registers configuration */
+    FSMC_Bank2->PCR2 = tmppcr;
+    FSMC_Bank2->PMEM2 = tmppmem;
+    FSMC_Bank2->PATT2 = tmppatt;
+  }
+  else
+  {
+    /* FSMC_Bank3_NAND registers configuration */
+    FSMC_Bank3->PCR3 = tmppcr;
+    FSMC_Bank3->PMEM3 = tmppmem;
+    FSMC_Bank3->PATT3 = tmppatt;
+  }
+}
+
+/**
+  * @brief  Initializes the FSMC PCCARD Bank according to the specified 
+  *         parameters in the FSMC_PCCARDInitStruct.
+  * @param  FSMC_PCCARDInitStruct : pointer to a FSMC_PCCARDInitTypeDef
+  *         structure that contains the configuration information for the FSMC 
+  *         PCCARD Bank.                       
+  * @retval None
+  */
+void FSMC_PCCARDInit(FSMC_PCCARDInitTypeDef* FSMC_PCCARDInitStruct)
+{
+  /* Check the parameters */
+  assert_param(IS_FSMC_WAIT_FEATURE(FSMC_PCCARDInitStruct->FSMC_Waitfeature));
+  assert_param(IS_FSMC_TCLR_TIME(FSMC_PCCARDInitStruct->FSMC_TCLRSetupTime));
+  assert_param(IS_FSMC_TAR_TIME(FSMC_PCCARDInitStruct->FSMC_TARSetupTime));
+ 
+  assert_param(IS_FSMC_SETUP_TIME(FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime));
+  assert_param(IS_FSMC_WAIT_TIME(FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime));
+  assert_param(IS_FSMC_HOLD_TIME(FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime));
+  assert_param(IS_FSMC_HIZ_TIME(FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime));
+  
+  assert_param(IS_FSMC_SETUP_TIME(FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime));
+  assert_param(IS_FSMC_WAIT_TIME(FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime));
+  assert_param(IS_FSMC_HOLD_TIME(FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime));
+  assert_param(IS_FSMC_HIZ_TIME(FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime));
+  assert_param(IS_FSMC_SETUP_TIME(FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_SetupTime));
+  assert_param(IS_FSMC_WAIT_TIME(FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_WaitSetupTime));
+  assert_param(IS_FSMC_HOLD_TIME(FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HoldSetupTime));
+  assert_param(IS_FSMC_HIZ_TIME(FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HiZSetupTime));
+  
+  /* Set the PCR4 register value according to FSMC_PCCARDInitStruct parameters */
+  FSMC_Bank4->PCR4 = (uint32_t)FSMC_PCCARDInitStruct->FSMC_Waitfeature |
+                     FSMC_MemoryDataWidth_16b |  
+                     (FSMC_PCCARDInitStruct->FSMC_TCLRSetupTime << 9) |
+                     (FSMC_PCCARDInitStruct->FSMC_TARSetupTime << 13);
+            
+  /* Set PMEM4 register value according to FSMC_CommonSpaceTimingStructure parameters */
+  FSMC_Bank4->PMEM4 = (uint32_t)FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime |
+                      (FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime << 8) |
+                      (FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime << 16)|
+                      (FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime << 24); 
+            
+  /* Set PATT4 register value according to FSMC_AttributeSpaceTimingStructure parameters */
+  FSMC_Bank4->PATT4 = (uint32_t)FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime |
+                      (FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime << 8) |
+                      (FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime << 16)|
+                      (FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime << 24);	
+            
+  /* Set PIO4 register value according to FSMC_IOSpaceTimingStructure parameters */
+  FSMC_Bank4->PIO4 = (uint32_t)FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_SetupTime |
+                     (FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_WaitSetupTime << 8) |
+                     (FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HoldSetupTime << 16)|
+                     (FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HiZSetupTime << 24);             
+}
+
+/**
+  * @brief  Fills each FSMC_NORSRAMInitStruct member with its default value.
+  * @param  FSMC_NORSRAMInitStruct: pointer to a FSMC_NORSRAMInitTypeDef 
+  *         structure which will be initialized.
+  * @retval None
+  */
+void FSMC_NORSRAMStructInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct)
+{  
+  /* Reset NOR/SRAM Init structure parameters values */
+  FSMC_NORSRAMInitStruct->FSMC_Bank = FSMC_Bank1_NORSRAM1;
+  FSMC_NORSRAMInitStruct->FSMC_DataAddressMux = FSMC_DataAddressMux_Enable;
+  FSMC_NORSRAMInitStruct->FSMC_MemoryType = FSMC_MemoryType_SRAM;
+  FSMC_NORSRAMInitStruct->FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_8b;
+  FSMC_NORSRAMInitStruct->FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable;
+  FSMC_NORSRAMInitStruct->FSMC_AsynchronousWait = FSMC_AsynchronousWait_Disable;
+  FSMC_NORSRAMInitStruct->FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low;
+  FSMC_NORSRAMInitStruct->FSMC_WrapMode = FSMC_WrapMode_Disable;
+  FSMC_NORSRAMInitStruct->FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState;
+  FSMC_NORSRAMInitStruct->FSMC_WriteOperation = FSMC_WriteOperation_Enable;
+  FSMC_NORSRAMInitStruct->FSMC_WaitSignal = FSMC_WaitSignal_Enable;
+  FSMC_NORSRAMInitStruct->FSMC_ExtendedMode = FSMC_ExtendedMode_Disable;
+  FSMC_NORSRAMInitStruct->FSMC_WriteBurst = FSMC_WriteBurst_Disable;
+  FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressSetupTime = 0xF;
+  FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressHoldTime = 0xF;
+  FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataSetupTime = 0xFF;
+  FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_BusTurnAroundDuration = 0xF;
+  FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_CLKDivision = 0xF;
+  FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataLatency = 0xF;
+  FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AccessMode = FSMC_AccessMode_A; 
+  FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressSetupTime = 0xF;
+  FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressHoldTime = 0xF;
+  FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataSetupTime = 0xFF;
+  FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_BusTurnAroundDuration = 0xF;
+  FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_CLKDivision = 0xF;
+  FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataLatency = 0xF;
+  FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AccessMode = FSMC_AccessMode_A;
+}
+
+/**
+  * @brief  Fills each FSMC_NANDInitStruct member with its default value.
+  * @param  FSMC_NANDInitStruct: pointer to a FSMC_NANDInitTypeDef 
+  *         structure which will be initialized.
+  * @retval None
+  */
+void FSMC_NANDStructInit(FSMC_NANDInitTypeDef* FSMC_NANDInitStruct)
+{ 
+  /* Reset NAND Init structure parameters values */
+  FSMC_NANDInitStruct->FSMC_Bank = FSMC_Bank2_NAND;
+  FSMC_NANDInitStruct->FSMC_Waitfeature = FSMC_Waitfeature_Disable;
+  FSMC_NANDInitStruct->FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_8b;
+  FSMC_NANDInitStruct->FSMC_ECC = FSMC_ECC_Disable;
+  FSMC_NANDInitStruct->FSMC_ECCPageSize = FSMC_ECCPageSize_256Bytes;
+  FSMC_NANDInitStruct->FSMC_TCLRSetupTime = 0x0;
+  FSMC_NANDInitStruct->FSMC_TARSetupTime = 0x0;
+  FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime = 0xFC;
+  FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC;
+  FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC;
+  FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC;
+  FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime = 0xFC;
+  FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC;
+  FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC;
+  FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC;	  
+}
+
+/**
+  * @brief  Fills each FSMC_PCCARDInitStruct member with its default value.
+  * @param  FSMC_PCCARDInitStruct: pointer to a FSMC_PCCARDInitTypeDef 
+  *         structure which will be initialized.
+  * @retval None
+  */
+void FSMC_PCCARDStructInit(FSMC_PCCARDInitTypeDef* FSMC_PCCARDInitStruct)
+{
+  /* Reset PCCARD Init structure parameters values */
+  FSMC_PCCARDInitStruct->FSMC_Waitfeature = FSMC_Waitfeature_Disable;
+  FSMC_PCCARDInitStruct->FSMC_TCLRSetupTime = 0x0;
+  FSMC_PCCARDInitStruct->FSMC_TARSetupTime = 0x0;
+  FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime = 0xFC;
+  FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC;
+  FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC;
+  FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC;
+  FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime = 0xFC;
+  FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC;
+  FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC;
+  FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC;	
+  FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_SetupTime = 0xFC;
+  FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC;
+  FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC;
+  FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC;
+}
+
+/**
+  * @brief  Enables or disables the specified NOR/SRAM Memory Bank.
+  * @param  FSMC_Bank: specifies the FSMC Bank to be used
+  *   This parameter can be one of the following values:
+  *     @arg FSMC_Bank1_NORSRAM1: FSMC Bank1 NOR/SRAM1  
+  *     @arg FSMC_Bank1_NORSRAM2: FSMC Bank1 NOR/SRAM2 
+  *     @arg FSMC_Bank1_NORSRAM3: FSMC Bank1 NOR/SRAM3 
+  *     @arg FSMC_Bank1_NORSRAM4: FSMC Bank1 NOR/SRAM4 
+  * @param  NewState: new state of the FSMC_Bank. This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void FSMC_NORSRAMCmd(uint32_t FSMC_Bank, FunctionalState NewState)
+{
+  assert_param(IS_FSMC_NORSRAM_BANK(FSMC_Bank));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  
+  if (NewState != DISABLE)
+  {
+    /* Enable the selected NOR/SRAM Bank by setting the PBKEN bit in the BCRx register */
+    FSMC_Bank1->BTCR[FSMC_Bank] |= BCR_MBKEN_Set;
+  }
+  else
+  {
+    /* Disable the selected NOR/SRAM Bank by clearing the PBKEN bit in the BCRx register */
+    FSMC_Bank1->BTCR[FSMC_Bank] &= BCR_MBKEN_Reset;
+  }
+}
+
+/**
+  * @brief  Enables or disables the specified NAND Memory Bank.
+  * @param  FSMC_Bank: specifies the FSMC Bank to be used
+  *   This parameter can be one of the following values:
+  *     @arg FSMC_Bank2_NAND: FSMC Bank2 NAND 
+  *     @arg FSMC_Bank3_NAND: FSMC Bank3 NAND
+  * @param  NewState: new state of the FSMC_Bank. This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void FSMC_NANDCmd(uint32_t FSMC_Bank, FunctionalState NewState)
+{
+  assert_param(IS_FSMC_NAND_BANK(FSMC_Bank));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  
+  if (NewState != DISABLE)
+  {
+    /* Enable the selected NAND Bank by setting the PBKEN bit in the PCRx register */
+    if(FSMC_Bank == FSMC_Bank2_NAND)
+    {
+      FSMC_Bank2->PCR2 |= PCR_PBKEN_Set;
+    }
+    else
+    {
+      FSMC_Bank3->PCR3 |= PCR_PBKEN_Set;
+    }
+  }
+  else
+  {
+    /* Disable the selected NAND Bank by clearing the PBKEN bit in the PCRx register */
+    if(FSMC_Bank == FSMC_Bank2_NAND)
+    {
+      FSMC_Bank2->PCR2 &= PCR_PBKEN_Reset;
+    }
+    else
+    {
+      FSMC_Bank3->PCR3 &= PCR_PBKEN_Reset;
+    }
+  }
+}
+
+/**
+  * @brief  Enables or disables the PCCARD Memory Bank.
+  * @param  NewState: new state of the PCCARD Memory Bank.  
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void FSMC_PCCARDCmd(FunctionalState NewState)
+{
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  
+  if (NewState != DISABLE)
+  {
+    /* Enable the PCCARD Bank by setting the PBKEN bit in the PCR4 register */
+    FSMC_Bank4->PCR4 |= PCR_PBKEN_Set;
+  }
+  else
+  {
+    /* Disable the PCCARD Bank by clearing the PBKEN bit in the PCR4 register */
+    FSMC_Bank4->PCR4 &= PCR_PBKEN_Reset;
+  }
+}
+
+/**
+  * @brief  Enables or disables the FSMC NAND ECC feature.
+  * @param  FSMC_Bank: specifies the FSMC Bank to be used
+  *   This parameter can be one of the following values:
+  *     @arg FSMC_Bank2_NAND: FSMC Bank2 NAND 
+  *     @arg FSMC_Bank3_NAND: FSMC Bank3 NAND
+  * @param  NewState: new state of the FSMC NAND ECC feature.  
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void FSMC_NANDECCCmd(uint32_t FSMC_Bank, FunctionalState NewState)
+{
+  assert_param(IS_FSMC_NAND_BANK(FSMC_Bank));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  
+  if (NewState != DISABLE)
+  {
+    /* Enable the selected NAND Bank ECC function by setting the ECCEN bit in the PCRx register */
+    if(FSMC_Bank == FSMC_Bank2_NAND)
+    {
+      FSMC_Bank2->PCR2 |= PCR_ECCEN_Set;
+    }
+    else
+    {
+      FSMC_Bank3->PCR3 |= PCR_ECCEN_Set;
+    }
+  }
+  else
+  {
+    /* Disable the selected NAND Bank ECC function by clearing the ECCEN bit in the PCRx register */
+    if(FSMC_Bank == FSMC_Bank2_NAND)
+    {
+      FSMC_Bank2->PCR2 &= PCR_ECCEN_Reset;
+    }
+    else
+    {
+      FSMC_Bank3->PCR3 &= PCR_ECCEN_Reset;
+    }
+  }
+}
+
+/**
+  * @brief  Returns the error correction code register value.
+  * @param  FSMC_Bank: specifies the FSMC Bank to be used
+  *   This parameter can be one of the following values:
+  *     @arg FSMC_Bank2_NAND: FSMC Bank2 NAND 
+  *     @arg FSMC_Bank3_NAND: FSMC Bank3 NAND
+  * @retval The Error Correction Code (ECC) value.
+  */
+uint32_t FSMC_GetECC(uint32_t FSMC_Bank)
+{
+  uint32_t eccval = 0x00000000;
+  
+  if(FSMC_Bank == FSMC_Bank2_NAND)
+  {
+    /* Get the ECCR2 register value */
+    eccval = FSMC_Bank2->ECCR2;
+  }
+  else
+  {
+    /* Get the ECCR3 register value */
+    eccval = FSMC_Bank3->ECCR3;
+  }
+  /* Return the error correction code value */
+  return(eccval);
+}
+
+/**
+  * @brief  Enables or disables the specified FSMC interrupts.
+  * @param  FSMC_Bank: specifies the FSMC Bank to be used
+  *   This parameter can be one of the following values:
+  *     @arg FSMC_Bank2_NAND: FSMC Bank2 NAND 
+  *     @arg FSMC_Bank3_NAND: FSMC Bank3 NAND
+  *     @arg FSMC_Bank4_PCCARD: FSMC Bank4 PCCARD
+  * @param  FSMC_IT: specifies the FSMC interrupt sources to be enabled or disabled.
+  *   This parameter can be any combination of the following values:
+  *     @arg FSMC_IT_RisingEdge: Rising edge detection interrupt. 
+  *     @arg FSMC_IT_Level: Level edge detection interrupt.
+  *     @arg FSMC_IT_FallingEdge: Falling edge detection interrupt.
+  * @param  NewState: new state of the specified FSMC interrupts.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void FSMC_ITConfig(uint32_t FSMC_Bank, uint32_t FSMC_IT, FunctionalState NewState)
+{
+  assert_param(IS_FSMC_IT_BANK(FSMC_Bank));
+  assert_param(IS_FSMC_IT(FSMC_IT));	
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  
+  if (NewState != DISABLE)
+  {
+    /* Enable the selected FSMC_Bank2 interrupts */
+    if(FSMC_Bank == FSMC_Bank2_NAND)
+    {
+      FSMC_Bank2->SR2 |= FSMC_IT;
+    }
+    /* Enable the selected FSMC_Bank3 interrupts */
+    else if (FSMC_Bank == FSMC_Bank3_NAND)
+    {
+      FSMC_Bank3->SR3 |= FSMC_IT;
+    }
+    /* Enable the selected FSMC_Bank4 interrupts */
+    else
+    {
+      FSMC_Bank4->SR4 |= FSMC_IT;    
+    }
+  }
+  else
+  {
+    /* Disable the selected FSMC_Bank2 interrupts */
+    if(FSMC_Bank == FSMC_Bank2_NAND)
+    {
+      
+      FSMC_Bank2->SR2 &= (uint32_t)~FSMC_IT;
+    }
+    /* Disable the selected FSMC_Bank3 interrupts */
+    else if (FSMC_Bank == FSMC_Bank3_NAND)
+    {
+      FSMC_Bank3->SR3 &= (uint32_t)~FSMC_IT;
+    }
+    /* Disable the selected FSMC_Bank4 interrupts */
+    else
+    {
+      FSMC_Bank4->SR4 &= (uint32_t)~FSMC_IT;    
+    }
+  }
+}
+
+/**
+  * @brief  Checks whether the specified FSMC flag is set or not.
+  * @param  FSMC_Bank: specifies the FSMC Bank to be used
+  *   This parameter can be one of the following values:
+  *     @arg FSMC_Bank2_NAND: FSMC Bank2 NAND 
+  *     @arg FSMC_Bank3_NAND: FSMC Bank3 NAND
+  *     @arg FSMC_Bank4_PCCARD: FSMC Bank4 PCCARD
+  * @param  FSMC_FLAG: specifies the flag to check.
+  *   This parameter can be one of the following values:
+  *     @arg FSMC_FLAG_RisingEdge: Rising egde detection Flag.
+  *     @arg FSMC_FLAG_Level: Level detection Flag.
+  *     @arg FSMC_FLAG_FallingEdge: Falling egde detection Flag.
+  *     @arg FSMC_FLAG_FEMPT: Fifo empty Flag. 
+  * @retval The new state of FSMC_FLAG (SET or RESET).
+  */
+FlagStatus FSMC_GetFlagStatus(uint32_t FSMC_Bank, uint32_t FSMC_FLAG)
+{
+  FlagStatus bitstatus = RESET;
+  uint32_t tmpsr = 0x00000000;
+  
+  /* Check the parameters */
+  assert_param(IS_FSMC_GETFLAG_BANK(FSMC_Bank));
+  assert_param(IS_FSMC_GET_FLAG(FSMC_FLAG));
+  
+  if(FSMC_Bank == FSMC_Bank2_NAND)
+  {
+    tmpsr = FSMC_Bank2->SR2;
+  }  
+  else if(FSMC_Bank == FSMC_Bank3_NAND)
+  {
+    tmpsr = FSMC_Bank3->SR3;
+  }
+  /* FSMC_Bank4_PCCARD*/
+  else
+  {
+    tmpsr = FSMC_Bank4->SR4;
+  } 
+  
+  /* Get the flag status */
+  if ((tmpsr & FSMC_FLAG) != (uint16_t)RESET )
+  {
+    bitstatus = SET;
+  }
+  else
+  {
+    bitstatus = RESET;
+  }
+  /* Return the flag status */
+  return bitstatus;
+}
+
+/**
+  * @brief  Clears the FSMC's pending flags.
+  * @param  FSMC_Bank: specifies the FSMC Bank to be used
+  *   This parameter can be one of the following values:
+  *     @arg FSMC_Bank2_NAND: FSMC Bank2 NAND 
+  *     @arg FSMC_Bank3_NAND: FSMC Bank3 NAND
+  *     @arg FSMC_Bank4_PCCARD: FSMC Bank4 PCCARD
+  * @param  FSMC_FLAG: specifies the flag to clear.
+  *   This parameter can be any combination of the following values:
+  *     @arg FSMC_FLAG_RisingEdge: Rising egde detection Flag.
+  *     @arg FSMC_FLAG_Level: Level detection Flag.
+  *     @arg FSMC_FLAG_FallingEdge: Falling egde detection Flag.
+  * @retval None
+  */
+void FSMC_ClearFlag(uint32_t FSMC_Bank, uint32_t FSMC_FLAG)
+{
+ /* Check the parameters */
+  assert_param(IS_FSMC_GETFLAG_BANK(FSMC_Bank));
+  assert_param(IS_FSMC_CLEAR_FLAG(FSMC_FLAG)) ;
+    
+  if(FSMC_Bank == FSMC_Bank2_NAND)
+  {
+    FSMC_Bank2->SR2 &= ~FSMC_FLAG; 
+  }  
+  else if(FSMC_Bank == FSMC_Bank3_NAND)
+  {
+    FSMC_Bank3->SR3 &= ~FSMC_FLAG;
+  }
+  /* FSMC_Bank4_PCCARD*/
+  else
+  {
+    FSMC_Bank4->SR4 &= ~FSMC_FLAG;
+  }
+}
+
+/**
+  * @brief  Checks whether the specified FSMC interrupt has occurred or not.
+  * @param  FSMC_Bank: specifies the FSMC Bank to be used
+  *   This parameter can be one of the following values:
+  *     @arg FSMC_Bank2_NAND: FSMC Bank2 NAND 
+  *     @arg FSMC_Bank3_NAND: FSMC Bank3 NAND
+  *     @arg FSMC_Bank4_PCCARD: FSMC Bank4 PCCARD
+  * @param  FSMC_IT: specifies the FSMC interrupt source to check.
+  *   This parameter can be one of the following values:
+  *     @arg FSMC_IT_RisingEdge: Rising edge detection interrupt. 
+  *     @arg FSMC_IT_Level: Level edge detection interrupt.
+  *     @arg FSMC_IT_FallingEdge: Falling edge detection interrupt. 
+  * @retval The new state of FSMC_IT (SET or RESET).
+  */
+ITStatus FSMC_GetITStatus(uint32_t FSMC_Bank, uint32_t FSMC_IT)
+{
+  ITStatus bitstatus = RESET;
+  uint32_t tmpsr = 0x0, itstatus = 0x0, itenable = 0x0; 
+  
+  /* Check the parameters */
+  assert_param(IS_FSMC_IT_BANK(FSMC_Bank));
+  assert_param(IS_FSMC_GET_IT(FSMC_IT));
+  
+  if(FSMC_Bank == FSMC_Bank2_NAND)
+  {
+    tmpsr = FSMC_Bank2->SR2;
+  }  
+  else if(FSMC_Bank == FSMC_Bank3_NAND)
+  {
+    tmpsr = FSMC_Bank3->SR3;
+  }
+  /* FSMC_Bank4_PCCARD*/
+  else
+  {
+    tmpsr = FSMC_Bank4->SR4;
+  } 
+  
+  itstatus = tmpsr & FSMC_IT;
+  
+  itenable = tmpsr & (FSMC_IT >> 3);
+  if ((itstatus != (uint32_t)RESET)  && (itenable != (uint32_t)RESET))
+  {
+    bitstatus = SET;
+  }
+  else
+  {
+    bitstatus = RESET;
+  }
+  return bitstatus; 
+}
+
+/**
+  * @brief  Clears the FSMC's interrupt pending bits.
+  * @param  FSMC_Bank: specifies the FSMC Bank to be used
+  *   This parameter can be one of the following values:
+  *     @arg FSMC_Bank2_NAND: FSMC Bank2 NAND 
+  *     @arg FSMC_Bank3_NAND: FSMC Bank3 NAND
+  *     @arg FSMC_Bank4_PCCARD: FSMC Bank4 PCCARD
+  * @param  FSMC_IT: specifies the interrupt pending bit to clear.
+  *   This parameter can be any combination of the following values:
+  *     @arg FSMC_IT_RisingEdge: Rising edge detection interrupt. 
+  *     @arg FSMC_IT_Level: Level edge detection interrupt.
+  *     @arg FSMC_IT_FallingEdge: Falling edge detection interrupt.
+  * @retval None
+  */
+void FSMC_ClearITPendingBit(uint32_t FSMC_Bank, uint32_t FSMC_IT)
+{
+  /* Check the parameters */
+  assert_param(IS_FSMC_IT_BANK(FSMC_Bank));
+  assert_param(IS_FSMC_IT(FSMC_IT));
+    
+  if(FSMC_Bank == FSMC_Bank2_NAND)
+  {
+    FSMC_Bank2->SR2 &= ~(FSMC_IT >> 3); 
+  }  
+  else if(FSMC_Bank == FSMC_Bank3_NAND)
+  {
+    FSMC_Bank3->SR3 &= ~(FSMC_IT >> 3);
+  }
+  /* FSMC_Bank4_PCCARD*/
+  else
+  {
+    FSMC_Bank4->SR4 &= ~(FSMC_IT >> 3);
+  }
+}
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/STM32_4路称重_Git提交精简工程/src/STM32F10x_FWLib/src/stm32f10x_gpio.c b/STM32_4路称重_Git提交精简工程/src/STM32F10x_FWLib/src/stm32f10x_gpio.c
new file mode 100755
index 0000000..93dbcd7
--- /dev/null
+++ b/STM32_4路称重_Git提交精简工程/src/STM32F10x_FWLib/src/stm32f10x_gpio.c
@@ -0,0 +1,650 @@
+/**
+  ******************************************************************************
+  * @file    stm32f10x_gpio.c
+  * @author  MCD Application Team
+  * @version V3.5.0
+  * @date    11-March-2011
+  * @brief   This file provides all the GPIO firmware functions.
+  ******************************************************************************
+  * @attention
+  *
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+  *
+  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x_gpio.h"
+#include "stm32f10x_rcc.h"
+
+/** @addtogroup STM32F10x_StdPeriph_Driver
+  * @{
+  */
+
+/** @defgroup GPIO 
+  * @brief GPIO driver modules
+  * @{
+  */ 
+
+/** @defgroup GPIO_Private_TypesDefinitions
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup GPIO_Private_Defines
+  * @{
+  */
+
+/* ------------ RCC registers bit address in the alias region ----------------*/
+#define AFIO_OFFSET                 (AFIO_BASE - PERIPH_BASE)
+
+/* --- EVENTCR Register -----*/
+
+/* Alias word address of EVOE bit */
+#define EVCR_OFFSET                 (AFIO_OFFSET + 0x00)
+#define EVOE_BitNumber              ((uint8_t)0x07)
+#define EVCR_EVOE_BB                (PERIPH_BB_BASE + (EVCR_OFFSET * 32) + (EVOE_BitNumber * 4))
+
+
+/* ---  MAPR Register ---*/ 
+/* Alias word address of MII_RMII_SEL bit */ 
+#define MAPR_OFFSET                 (AFIO_OFFSET + 0x04) 
+#define MII_RMII_SEL_BitNumber      ((u8)0x17) 
+#define MAPR_MII_RMII_SEL_BB        (PERIPH_BB_BASE + (MAPR_OFFSET * 32) + (MII_RMII_SEL_BitNumber * 4))
+
+
+#define EVCR_PORTPINCONFIG_MASK     ((uint16_t)0xFF80)
+#define LSB_MASK                    ((uint16_t)0xFFFF)
+#define DBGAFR_POSITION_MASK        ((uint32_t)0x000F0000)
+#define DBGAFR_SWJCFG_MASK          ((uint32_t)0xF0FFFFFF)
+#define DBGAFR_LOCATION_MASK        ((uint32_t)0x00200000)
+#define DBGAFR_NUMBITS_MASK         ((uint32_t)0x00100000)
+/**
+  * @}
+  */
+
+/** @defgroup GPIO_Private_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup GPIO_Private_Variables
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup GPIO_Private_FunctionPrototypes
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup GPIO_Private_Functions
+  * @{
+  */
+
+/**
+  * @brief  Deinitializes the GPIOx peripheral registers to their default reset values.
+  * @param  GPIOx: where x can be (A..G) to select the GPIO peripheral.
+  * @retval None
+  */
+void GPIO_DeInit(GPIO_TypeDef* GPIOx)
+{
+  /* Check the parameters */
+  assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
+  
+  if (GPIOx == GPIOA)
+  {
+    RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOA, ENABLE);
+    RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOA, DISABLE);
+  }
+  else if (GPIOx == GPIOB)
+  {
+    RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOB, ENABLE);
+    RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOB, DISABLE);
+  }
+  else if (GPIOx == GPIOC)
+  {
+    RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOC, ENABLE);
+    RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOC, DISABLE);
+  }
+  else if (GPIOx == GPIOD)
+  {
+    RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOD, ENABLE);
+    RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOD, DISABLE);
+  }    
+  else if (GPIOx == GPIOE)
+  {
+    RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOE, ENABLE);
+    RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOE, DISABLE);
+  } 
+  else if (GPIOx == GPIOF)
+  {
+    RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOF, ENABLE);
+    RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOF, DISABLE);
+  }
+  else
+  {
+    if (GPIOx == GPIOG)
+    {
+      RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOG, ENABLE);
+      RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOG, DISABLE);
+    }
+  }
+}
+
+/**
+  * @brief  Deinitializes the Alternate Functions (remap, event control
+  *   and EXTI configuration) registers to their default reset values.
+  * @param  None
+  * @retval None
+  */
+void GPIO_AFIODeInit(void)
+{
+  RCC_APB2PeriphResetCmd(RCC_APB2Periph_AFIO, ENABLE);
+  RCC_APB2PeriphResetCmd(RCC_APB2Periph_AFIO, DISABLE);
+}
+
+/**
+  * @brief  Initializes the GPIOx peripheral according to the specified
+  *         parameters in the GPIO_InitStruct.
+  * @param  GPIOx: where x can be (A..G) to select the GPIO peripheral.
+  * @param  GPIO_InitStruct: pointer to a GPIO_InitTypeDef structure that
+  *         contains the configuration information for the specified GPIO peripheral.
+  * @retval None
+  */
+void GPIO_Init(GPIO_TypeDef* GPIOx, GPIO_InitTypeDef* GPIO_InitStruct)
+{
+  uint32_t currentmode = 0x00, currentpin = 0x00, pinpos = 0x00, pos = 0x00;
+  uint32_t tmpreg = 0x00, pinmask = 0x00;
+  /* Check the parameters */
+  assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
+  assert_param(IS_GPIO_MODE(GPIO_InitStruct->GPIO_Mode));
+  assert_param(IS_GPIO_PIN(GPIO_InitStruct->GPIO_Pin));  
+  
+/*---------------------------- GPIO Mode Configuration -----------------------*/
+  currentmode = ((uint32_t)GPIO_InitStruct->GPIO_Mode) & ((uint32_t)0x0F);
+  if ((((uint32_t)GPIO_InitStruct->GPIO_Mode) & ((uint32_t)0x10)) != 0x00)
+  { 
+    /* Check the parameters */
+    assert_param(IS_GPIO_SPEED(GPIO_InitStruct->GPIO_Speed));
+    /* Output mode */
+    currentmode |= (uint32_t)GPIO_InitStruct->GPIO_Speed;
+  }
+/*---------------------------- GPIO CRL Configuration ------------------------*/
+  /* Configure the eight low port pins */
+  if (((uint32_t)GPIO_InitStruct->GPIO_Pin & ((uint32_t)0x00FF)) != 0x00)
+  {
+    tmpreg = GPIOx->CRL;
+    for (pinpos = 0x00; pinpos < 0x08; pinpos++)
+    {
+      pos = ((uint32_t)0x01) << pinpos;
+      /* Get the port pins position */
+      currentpin = (GPIO_InitStruct->GPIO_Pin) & pos;
+      if (currentpin == pos)
+      {
+        pos = pinpos << 2;
+        /* Clear the corresponding low control register bits */
+        pinmask = ((uint32_t)0x0F) << pos;
+        tmpreg &= ~pinmask;
+        /* Write the mode configuration in the corresponding bits */
+        tmpreg |= (currentmode << pos);
+        /* Reset the corresponding ODR bit */
+        if (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPD)
+        {
+          GPIOx->BRR = (((uint32_t)0x01) << pinpos);
+        }
+        else
+        {
+          /* Set the corresponding ODR bit */
+          if (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPU)
+          {
+            GPIOx->BSRR = (((uint32_t)0x01) << pinpos);
+          }
+        }
+      }
+    }
+    GPIOx->CRL = tmpreg;
+  }
+/*---------------------------- GPIO CRH Configuration ------------------------*/
+  /* Configure the eight high port pins */
+  if (GPIO_InitStruct->GPIO_Pin > 0x00FF)
+  {
+    tmpreg = GPIOx->CRH;
+    for (pinpos = 0x00; pinpos < 0x08; pinpos++)
+    {
+      pos = (((uint32_t)0x01) << (pinpos + 0x08));
+      /* Get the port pins position */
+      currentpin = ((GPIO_InitStruct->GPIO_Pin) & pos);
+      if (currentpin == pos)
+      {
+        pos = pinpos << 2;
+        /* Clear the corresponding high control register bits */
+        pinmask = ((uint32_t)0x0F) << pos;
+        tmpreg &= ~pinmask;
+        /* Write the mode configuration in the corresponding bits */
+        tmpreg |= (currentmode << pos);
+        /* Reset the corresponding ODR bit */
+        if (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPD)
+        {
+          GPIOx->BRR = (((uint32_t)0x01) << (pinpos + 0x08));
+        }
+        /* Set the corresponding ODR bit */
+        if (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPU)
+        {
+          GPIOx->BSRR = (((uint32_t)0x01) << (pinpos + 0x08));
+        }
+      }
+    }
+    GPIOx->CRH = tmpreg;
+  }
+}
+
+/**
+  * @brief  Fills each GPIO_InitStruct member with its default value.
+  * @param  GPIO_InitStruct : pointer to a GPIO_InitTypeDef structure which will
+  *         be initialized.
+  * @retval None
+  */
+void GPIO_StructInit(GPIO_InitTypeDef* GPIO_InitStruct)
+{
+  /* Reset GPIO init structure parameters values */
+  GPIO_InitStruct->GPIO_Pin  = GPIO_Pin_All;
+  GPIO_InitStruct->GPIO_Speed = GPIO_Speed_2MHz;
+  GPIO_InitStruct->GPIO_Mode = GPIO_Mode_IN_FLOATING;
+}
+
+/**
+  * @brief  Reads the specified input port pin.
+  * @param  GPIOx: where x can be (A..G) to select the GPIO peripheral.
+  * @param  GPIO_Pin:  specifies the port bit to read.
+  *   This parameter can be GPIO_Pin_x where x can be (0..15).
+  * @retval The input port pin value.
+  */
+uint8_t GPIO_ReadInputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
+{
+  uint8_t bitstatus = 0x00;
+  
+  /* Check the parameters */
+  assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
+  assert_param(IS_GET_GPIO_PIN(GPIO_Pin)); 
+  
+  if ((GPIOx->IDR & GPIO_Pin) != (uint32_t)Bit_RESET)
+  {
+    bitstatus = (uint8_t)Bit_SET;
+  }
+  else
+  {
+    bitstatus = (uint8_t)Bit_RESET;
+  }
+  return bitstatus;
+}
+
+/**
+  * @brief  Reads the specified GPIO input data port.
+  * @param  GPIOx: where x can be (A..G) to select the GPIO peripheral.
+  * @retval GPIO input data port value.
+  */
+uint16_t GPIO_ReadInputData(GPIO_TypeDef* GPIOx)
+{
+  /* Check the parameters */
+  assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
+  
+  return ((uint16_t)GPIOx->IDR);
+}
+
+/**
+  * @brief  Reads the specified output data port bit.
+  * @param  GPIOx: where x can be (A..G) to select the GPIO peripheral.
+  * @param  GPIO_Pin:  specifies the port bit to read.
+  *   This parameter can be GPIO_Pin_x where x can be (0..15).
+  * @retval The output port pin value.
+  */
+uint8_t GPIO_ReadOutputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
+{
+  uint8_t bitstatus = 0x00;
+  /* Check the parameters */
+  assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
+  assert_param(IS_GET_GPIO_PIN(GPIO_Pin)); 
+  
+  if ((GPIOx->ODR & GPIO_Pin) != (uint32_t)Bit_RESET)
+  {
+    bitstatus = (uint8_t)Bit_SET;
+  }
+  else
+  {
+    bitstatus = (uint8_t)Bit_RESET;
+  }
+  return bitstatus;
+}
+
+/**
+  * @brief  Reads the specified GPIO output data port.
+  * @param  GPIOx: where x can be (A..G) to select the GPIO peripheral.
+  * @retval GPIO output data port value.
+  */
+uint16_t GPIO_ReadOutputData(GPIO_TypeDef* GPIOx)
+{
+  /* Check the parameters */
+  assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
+    
+  return ((uint16_t)GPIOx->ODR);
+}
+
+/**
+  * @brief  Sets the selected data port bits.
+  * @param  GPIOx: where x can be (A..G) to select the GPIO peripheral.
+  * @param  GPIO_Pin: specifies the port bits to be written.
+  *   This parameter can be any combination of GPIO_Pin_x where x can be (0..15).
+  * @retval None
+  */
+void GPIO_SetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
+{
+  /* Check the parameters */
+  assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
+  assert_param(IS_GPIO_PIN(GPIO_Pin));
+  
+  GPIOx->BSRR = GPIO_Pin;
+}
+
+/**
+  * @brief  Clears the selected data port bits.
+  * @param  GPIOx: where x can be (A..G) to select the GPIO peripheral.
+  * @param  GPIO_Pin: specifies the port bits to be written.
+  *   This parameter can be any combination of GPIO_Pin_x where x can be (0..15).
+  * @retval None
+  */
+void GPIO_ResetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
+{
+  /* Check the parameters */
+  assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
+  assert_param(IS_GPIO_PIN(GPIO_Pin));
+  
+  GPIOx->BRR = GPIO_Pin;
+}
+
+/**
+  * @brief  Sets or clears the selected data port bit.
+  * @param  GPIOx: where x can be (A..G) to select the GPIO peripheral.
+  * @param  GPIO_Pin: specifies the port bit to be written.
+  *   This parameter can be one of GPIO_Pin_x where x can be (0..15).
+  * @param  BitVal: specifies the value to be written to the selected bit.
+  *   This parameter can be one of the BitAction enum values:
+  *     @arg Bit_RESET: to clear the port pin
+  *     @arg Bit_SET: to set the port pin
+  * @retval None
+  */
+void GPIO_WriteBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, BitAction BitVal)
+{
+  /* Check the parameters */
+  assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
+  assert_param(IS_GET_GPIO_PIN(GPIO_Pin));
+  assert_param(IS_GPIO_BIT_ACTION(BitVal)); 
+  
+  if (BitVal != Bit_RESET)
+  {
+    GPIOx->BSRR = GPIO_Pin;
+  }
+  else
+  {
+    GPIOx->BRR = GPIO_Pin;
+  }
+}
+
+/**
+  * @brief  Writes data to the specified GPIO data port.
+  * @param  GPIOx: where x can be (A..G) to select the GPIO peripheral.
+  * @param  PortVal: specifies the value to be written to the port output data register.
+  * @retval None
+  */
+void GPIO_Write(GPIO_TypeDef* GPIOx, uint16_t PortVal)
+{
+  /* Check the parameters */
+  assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
+  
+  GPIOx->ODR = PortVal;
+}
+
+/**
+  * @brief  Locks GPIO Pins configuration registers.
+  * @param  GPIOx: where x can be (A..G) to select the GPIO peripheral.
+  * @param  GPIO_Pin: specifies the port bit to be written.
+  *   This parameter can be any combination of GPIO_Pin_x where x can be (0..15).
+  * @retval None
+  */
+void GPIO_PinLockConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
+{
+  uint32_t tmp = 0x00010000;
+  
+  /* Check the parameters */
+  assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
+  assert_param(IS_GPIO_PIN(GPIO_Pin));
+  
+  tmp |= GPIO_Pin;
+  /* Set LCKK bit */
+  GPIOx->LCKR = tmp;
+  /* Reset LCKK bit */
+  GPIOx->LCKR =  GPIO_Pin;
+  /* Set LCKK bit */
+  GPIOx->LCKR = tmp;
+  /* Read LCKK bit*/
+  tmp = GPIOx->LCKR;
+  /* Read LCKK bit*/
+  tmp = GPIOx->LCKR;
+}
+
+/**
+  * @brief  Selects the GPIO pin used as Event output.
+  * @param  GPIO_PortSource: selects the GPIO port to be used as source
+  *   for Event output.
+  *   This parameter can be GPIO_PortSourceGPIOx where x can be (A..E).
+  * @param  GPIO_PinSource: specifies the pin for the Event output.
+  *   This parameter can be GPIO_PinSourcex where x can be (0..15).
+  * @retval None
+  */
+void GPIO_EventOutputConfig(uint8_t GPIO_PortSource, uint8_t GPIO_PinSource)
+{
+  uint32_t tmpreg = 0x00;
+  /* Check the parameters */
+  assert_param(IS_GPIO_EVENTOUT_PORT_SOURCE(GPIO_PortSource));
+  assert_param(IS_GPIO_PIN_SOURCE(GPIO_PinSource));
+    
+  tmpreg = AFIO->EVCR;
+  /* Clear the PORT[6:4] and PIN[3:0] bits */
+  tmpreg &= EVCR_PORTPINCONFIG_MASK;
+  tmpreg |= (uint32_t)GPIO_PortSource << 0x04;
+  tmpreg |= GPIO_PinSource;
+  AFIO->EVCR = tmpreg;
+}
+
+/**
+  * @brief  Enables or disables the Event Output.
+  * @param  NewState: new state of the Event output.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void GPIO_EventOutputCmd(FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  
+  *(__IO uint32_t *) EVCR_EVOE_BB = (uint32_t)NewState;
+}
+
+/**
+  * @brief  Changes the mapping of the specified pin.
+  * @param  GPIO_Remap: selects the pin to remap.
+  *   This parameter can be one of the following values:
+  *     @arg GPIO_Remap_SPI1             : SPI1 Alternate Function mapping
+  *     @arg GPIO_Remap_I2C1             : I2C1 Alternate Function mapping
+  *     @arg GPIO_Remap_USART1           : USART1 Alternate Function mapping
+  *     @arg GPIO_Remap_USART2           : USART2 Alternate Function mapping
+  *     @arg GPIO_PartialRemap_USART3    : USART3 Partial Alternate Function mapping
+  *     @arg GPIO_FullRemap_USART3       : USART3 Full Alternate Function mapping
+  *     @arg GPIO_PartialRemap_TIM1      : TIM1 Partial Alternate Function mapping
+  *     @arg GPIO_FullRemap_TIM1         : TIM1 Full Alternate Function mapping
+  *     @arg GPIO_PartialRemap1_TIM2     : TIM2 Partial1 Alternate Function mapping
+  *     @arg GPIO_PartialRemap2_TIM2     : TIM2 Partial2 Alternate Function mapping
+  *     @arg GPIO_FullRemap_TIM2         : TIM2 Full Alternate Function mapping
+  *     @arg GPIO_PartialRemap_TIM3      : TIM3 Partial Alternate Function mapping
+  *     @arg GPIO_FullRemap_TIM3         : TIM3 Full Alternate Function mapping
+  *     @arg GPIO_Remap_TIM4             : TIM4 Alternate Function mapping
+  *     @arg GPIO_Remap1_CAN1            : CAN1 Alternate Function mapping
+  *     @arg GPIO_Remap2_CAN1            : CAN1 Alternate Function mapping
+  *     @arg GPIO_Remap_PD01             : PD01 Alternate Function mapping
+  *     @arg GPIO_Remap_TIM5CH4_LSI      : LSI connected to TIM5 Channel4 input capture for calibration
+  *     @arg GPIO_Remap_ADC1_ETRGINJ     : ADC1 External Trigger Injected Conversion remapping
+  *     @arg GPIO_Remap_ADC1_ETRGREG     : ADC1 External Trigger Regular Conversion remapping
+  *     @arg GPIO_Remap_ADC2_ETRGINJ     : ADC2 External Trigger Injected Conversion remapping
+  *     @arg GPIO_Remap_ADC2_ETRGREG     : ADC2 External Trigger Regular Conversion remapping
+  *     @arg GPIO_Remap_ETH              : Ethernet remapping (only for Connectivity line devices)
+  *     @arg GPIO_Remap_CAN2             : CAN2 remapping (only for Connectivity line devices)
+  *     @arg GPIO_Remap_SWJ_NoJTRST      : Full SWJ Enabled (JTAG-DP + SW-DP) but without JTRST
+  *     @arg GPIO_Remap_SWJ_JTAGDisable  : JTAG-DP Disabled and SW-DP Enabled
+  *     @arg GPIO_Remap_SWJ_Disable      : Full SWJ Disabled (JTAG-DP + SW-DP)
+  *     @arg GPIO_Remap_SPI3             : SPI3/I2S3 Alternate Function mapping (only for Connectivity line devices)
+  *                                        When the SPI3/I2S3 is remapped using this function, the SWJ is configured
+  *                                        to Full SWJ Enabled (JTAG-DP + SW-DP) but without JTRST.   
+  *     @arg GPIO_Remap_TIM2ITR1_PTP_SOF : Ethernet PTP output or USB OTG SOF (Start of Frame) connected
+  *                                        to TIM2 Internal Trigger 1 for calibration (only for Connectivity line devices)
+  *                                        If the GPIO_Remap_TIM2ITR1_PTP_SOF is enabled the TIM2 ITR1 is connected to 
+  *                                        Ethernet PTP output. When Reset TIM2 ITR1 is connected to USB OTG SOF output.    
+  *     @arg GPIO_Remap_PTP_PPS          : Ethernet MAC PPS_PTS output on PB05 (only for Connectivity line devices)
+  *     @arg GPIO_Remap_TIM15            : TIM15 Alternate Function mapping (only for Value line devices)
+  *     @arg GPIO_Remap_TIM16            : TIM16 Alternate Function mapping (only for Value line devices)
+  *     @arg GPIO_Remap_TIM17            : TIM17 Alternate Function mapping (only for Value line devices)
+  *     @arg GPIO_Remap_CEC              : CEC Alternate Function mapping (only for Value line devices)
+  *     @arg GPIO_Remap_TIM1_DMA         : TIM1 DMA requests mapping (only for Value line devices)
+  *     @arg GPIO_Remap_TIM9             : TIM9 Alternate Function mapping (only for XL-density devices)
+  *     @arg GPIO_Remap_TIM10            : TIM10 Alternate Function mapping (only for XL-density devices)
+  *     @arg GPIO_Remap_TIM11            : TIM11 Alternate Function mapping (only for XL-density devices)
+  *     @arg GPIO_Remap_TIM13            : TIM13 Alternate Function mapping (only for High density Value line and XL-density devices)
+  *     @arg GPIO_Remap_TIM14            : TIM14 Alternate Function mapping (only for High density Value line and XL-density devices)
+  *     @arg GPIO_Remap_FSMC_NADV        : FSMC_NADV Alternate Function mapping (only for High density Value line and XL-density devices)
+  *     @arg GPIO_Remap_TIM67_DAC_DMA    : TIM6/TIM7 and DAC DMA requests remapping (only for High density Value line devices)
+  *     @arg GPIO_Remap_TIM12            : TIM12 Alternate Function mapping (only for High density Value line devices)
+  *     @arg GPIO_Remap_MISC             : Miscellaneous Remap (DMA2 Channel5 Position and DAC Trigger remapping, 
+  *                                        only for High density Value line devices)     
+  * @param  NewState: new state of the port pin remapping.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void GPIO_PinRemapConfig(uint32_t GPIO_Remap, FunctionalState NewState)
+{
+  uint32_t tmp = 0x00, tmp1 = 0x00, tmpreg = 0x00, tmpmask = 0x00;
+
+  /* Check the parameters */
+  assert_param(IS_GPIO_REMAP(GPIO_Remap));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));  
+  
+  if((GPIO_Remap & 0x80000000) == 0x80000000)
+  {
+    tmpreg = AFIO->MAPR2;
+  }
+  else
+  {
+    tmpreg = AFIO->MAPR;
+  }
+
+  tmpmask = (GPIO_Remap & DBGAFR_POSITION_MASK) >> 0x10;
+  tmp = GPIO_Remap & LSB_MASK;
+
+  if ((GPIO_Remap & (DBGAFR_LOCATION_MASK | DBGAFR_NUMBITS_MASK)) == (DBGAFR_LOCATION_MASK | DBGAFR_NUMBITS_MASK))
+  {
+    tmpreg &= DBGAFR_SWJCFG_MASK;
+    AFIO->MAPR &= DBGAFR_SWJCFG_MASK;
+  }
+  else if ((GPIO_Remap & DBGAFR_NUMBITS_MASK) == DBGAFR_NUMBITS_MASK)
+  {
+    tmp1 = ((uint32_t)0x03) << tmpmask;
+    tmpreg &= ~tmp1;
+    tmpreg |= ~DBGAFR_SWJCFG_MASK;
+  }
+  else
+  {
+    tmpreg &= ~(tmp << ((GPIO_Remap >> 0x15)*0x10));
+    tmpreg |= ~DBGAFR_SWJCFG_MASK;
+  }
+
+  if (NewState != DISABLE)
+  {
+    tmpreg |= (tmp << ((GPIO_Remap >> 0x15)*0x10));
+  }
+
+  if((GPIO_Remap & 0x80000000) == 0x80000000)
+  {
+    AFIO->MAPR2 = tmpreg;
+  }
+  else
+  {
+    AFIO->MAPR = tmpreg;
+  }  
+}
+
+/**
+  * @brief  Selects the GPIO pin used as EXTI Line.
+  * @param  GPIO_PortSource: selects the GPIO port to be used as source for EXTI lines.
+  *   This parameter can be GPIO_PortSourceGPIOx where x can be (A..G).
+  * @param  GPIO_PinSource: specifies the EXTI line to be configured.
+  *   This parameter can be GPIO_PinSourcex where x can be (0..15).
+  * @retval None
+  */
+void GPIO_EXTILineConfig(uint8_t GPIO_PortSource, uint8_t GPIO_PinSource)
+{
+  uint32_t tmp = 0x00;
+  /* Check the parameters */
+  assert_param(IS_GPIO_EXTI_PORT_SOURCE(GPIO_PortSource));
+  assert_param(IS_GPIO_PIN_SOURCE(GPIO_PinSource));
+  
+  tmp = ((uint32_t)0x0F) << (0x04 * (GPIO_PinSource & (uint8_t)0x03));
+  AFIO->EXTICR[GPIO_PinSource >> 0x02] &= ~tmp;
+  AFIO->EXTICR[GPIO_PinSource >> 0x02] |= (((uint32_t)GPIO_PortSource) << (0x04 * (GPIO_PinSource & (uint8_t)0x03)));
+}
+
+/**
+  * @brief  Selects the Ethernet media interface.
+  * @note   This function applies only to STM32 Connectivity line devices.  
+  * @param  GPIO_ETH_MediaInterface: specifies the Media Interface mode.
+  *   This parameter can be one of the following values:
+  *     @arg GPIO_ETH_MediaInterface_MII: MII mode
+  *     @arg GPIO_ETH_MediaInterface_RMII: RMII mode    
+  * @retval None
+  */
+void GPIO_ETH_MediaInterfaceConfig(uint32_t GPIO_ETH_MediaInterface) 
+{ 
+  assert_param(IS_GPIO_ETH_MEDIA_INTERFACE(GPIO_ETH_MediaInterface)); 
+
+  /* Configure MII_RMII selection bit */ 
+  *(__IO uint32_t *) MAPR_MII_RMII_SEL_BB = GPIO_ETH_MediaInterface; 
+}
+  
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/STM32_4路称重_Git提交精简工程/src/STM32F10x_FWLib/src/stm32f10x_i2c.c b/STM32_4路称重_Git提交精简工程/src/STM32F10x_FWLib/src/stm32f10x_i2c.c
new file mode 100755
index 0000000..8896726
--- /dev/null
+++ b/STM32_4路称重_Git提交精简工程/src/STM32F10x_FWLib/src/stm32f10x_i2c.c
@@ -0,0 +1,1331 @@
+/**
+  ******************************************************************************
+  * @file    stm32f10x_i2c.c
+  * @author  MCD Application Team
+  * @version V3.5.0
+  * @date    11-March-2011
+  * @brief   This file provides all the I2C firmware functions.
+  ******************************************************************************
+  * @attention
+  *
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+  *
+  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x_i2c.h"
+#include "stm32f10x_rcc.h"
+
+
+/** @addtogroup STM32F10x_StdPeriph_Driver
+  * @{
+  */
+
+/** @defgroup I2C 
+  * @brief I2C driver modules
+  * @{
+  */ 
+
+/** @defgroup I2C_Private_TypesDefinitions
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup I2C_Private_Defines
+  * @{
+  */
+
+/* I2C SPE mask */
+#define CR1_PE_Set              ((uint16_t)0x0001)
+#define CR1_PE_Reset            ((uint16_t)0xFFFE)
+
+/* I2C START mask */
+#define CR1_START_Set           ((uint16_t)0x0100)
+#define CR1_START_Reset         ((uint16_t)0xFEFF)
+
+/* I2C STOP mask */
+#define CR1_STOP_Set            ((uint16_t)0x0200)
+#define CR1_STOP_Reset          ((uint16_t)0xFDFF)
+
+/* I2C ACK mask */
+#define CR1_ACK_Set             ((uint16_t)0x0400)
+#define CR1_ACK_Reset           ((uint16_t)0xFBFF)
+
+/* I2C ENGC mask */
+#define CR1_ENGC_Set            ((uint16_t)0x0040)
+#define CR1_ENGC_Reset          ((uint16_t)0xFFBF)
+
+/* I2C SWRST mask */
+#define CR1_SWRST_Set           ((uint16_t)0x8000)
+#define CR1_SWRST_Reset         ((uint16_t)0x7FFF)
+
+/* I2C PEC mask */
+#define CR1_PEC_Set             ((uint16_t)0x1000)
+#define CR1_PEC_Reset           ((uint16_t)0xEFFF)
+
+/* I2C ENPEC mask */
+#define CR1_ENPEC_Set           ((uint16_t)0x0020)
+#define CR1_ENPEC_Reset         ((uint16_t)0xFFDF)
+
+/* I2C ENARP mask */
+#define CR1_ENARP_Set           ((uint16_t)0x0010)
+#define CR1_ENARP_Reset         ((uint16_t)0xFFEF)
+
+/* I2C NOSTRETCH mask */
+#define CR1_NOSTRETCH_Set       ((uint16_t)0x0080)
+#define CR1_NOSTRETCH_Reset     ((uint16_t)0xFF7F)
+
+/* I2C registers Masks */
+#define CR1_CLEAR_Mask          ((uint16_t)0xFBF5)
+
+/* I2C DMAEN mask */
+#define CR2_DMAEN_Set           ((uint16_t)0x0800)
+#define CR2_DMAEN_Reset         ((uint16_t)0xF7FF)
+
+/* I2C LAST mask */
+#define CR2_LAST_Set            ((uint16_t)0x1000)
+#define CR2_LAST_Reset          ((uint16_t)0xEFFF)
+
+/* I2C FREQ mask */
+#define CR2_FREQ_Reset          ((uint16_t)0xFFC0)
+
+/* I2C ADD0 mask */
+#define OAR1_ADD0_Set           ((uint16_t)0x0001)
+#define OAR1_ADD0_Reset         ((uint16_t)0xFFFE)
+
+/* I2C ENDUAL mask */
+#define OAR2_ENDUAL_Set         ((uint16_t)0x0001)
+#define OAR2_ENDUAL_Reset       ((uint16_t)0xFFFE)
+
+/* I2C ADD2 mask */
+#define OAR2_ADD2_Reset         ((uint16_t)0xFF01)
+
+/* I2C F/S mask */
+#define CCR_FS_Set              ((uint16_t)0x8000)
+
+/* I2C CCR mask */
+#define CCR_CCR_Set             ((uint16_t)0x0FFF)
+
+/* I2C FLAG mask */
+#define FLAG_Mask               ((uint32_t)0x00FFFFFF)
+
+/* I2C Interrupt Enable mask */
+#define ITEN_Mask               ((uint32_t)0x07000000)
+
+/**
+  * @}
+  */
+
+/** @defgroup I2C_Private_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup I2C_Private_Variables
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup I2C_Private_FunctionPrototypes
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup I2C_Private_Functions
+  * @{
+  */
+
+/**
+  * @brief  Deinitializes the I2Cx peripheral registers to their default reset values.
+  * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+  * @retval None
+  */
+void I2C_DeInit(I2C_TypeDef* I2Cx)
+{
+  /* Check the parameters */
+  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+
+  if (I2Cx == I2C1)
+  {
+    /* Enable I2C1 reset state */
+    RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2C1, ENABLE);
+    /* Release I2C1 from reset state */
+    RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2C1, DISABLE);
+  }
+  else
+  {
+    /* Enable I2C2 reset state */
+    RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2C2, ENABLE);
+    /* Release I2C2 from reset state */
+    RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2C2, DISABLE);
+  }
+}
+
+/**
+  * @brief  Initializes the I2Cx peripheral according to the specified 
+  *   parameters in the I2C_InitStruct.
+  * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+  * @param  I2C_InitStruct: pointer to a I2C_InitTypeDef structure that
+  *   contains the configuration information for the specified I2C peripheral.
+  * @retval None
+  */
+void I2C_Init(I2C_TypeDef* I2Cx, I2C_InitTypeDef* I2C_InitStruct)
+{
+  uint16_t tmpreg = 0, freqrange = 0;
+  uint16_t result = 0x04;
+  uint32_t pclk1 = 8000000;
+  RCC_ClocksTypeDef  rcc_clocks;
+  /* Check the parameters */
+  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+  assert_param(IS_I2C_CLOCK_SPEED(I2C_InitStruct->I2C_ClockSpeed));
+  assert_param(IS_I2C_MODE(I2C_InitStruct->I2C_Mode));
+  assert_param(IS_I2C_DUTY_CYCLE(I2C_InitStruct->I2C_DutyCycle));
+  assert_param(IS_I2C_OWN_ADDRESS1(I2C_InitStruct->I2C_OwnAddress1));
+  assert_param(IS_I2C_ACK_STATE(I2C_InitStruct->I2C_Ack));
+  assert_param(IS_I2C_ACKNOWLEDGE_ADDRESS(I2C_InitStruct->I2C_AcknowledgedAddress));
+
+/*---------------------------- I2Cx CR2 Configuration ------------------------*/
+  /* Get the I2Cx CR2 value */
+  tmpreg = I2Cx->CR2;
+  /* Clear frequency FREQ[5:0] bits */
+  tmpreg &= CR2_FREQ_Reset;
+  /* Get pclk1 frequency value */
+  RCC_GetClocksFreq(&rcc_clocks);
+  pclk1 = rcc_clocks.PCLK1_Frequency;
+  /* Set frequency bits depending on pclk1 value */
+  freqrange = (uint16_t)(pclk1 / 1000000);
+  tmpreg |= freqrange;
+  /* Write to I2Cx CR2 */
+  I2Cx->CR2 = tmpreg;
+
+/*---------------------------- I2Cx CCR Configuration ------------------------*/
+  /* Disable the selected I2C peripheral to configure TRISE */
+  I2Cx->CR1 &= CR1_PE_Reset;
+  /* Reset tmpreg value */
+  /* Clear F/S, DUTY and CCR[11:0] bits */
+  tmpreg = 0;
+
+  /* Configure speed in standard mode */
+  if (I2C_InitStruct->I2C_ClockSpeed <= 100000)
+  {
+    /* Standard mode speed calculate */
+    result = (uint16_t)(pclk1 / (I2C_InitStruct->I2C_ClockSpeed << 1));
+    /* Test if CCR value is under 0x4*/
+    if (result < 0x04)
+    {
+      /* Set minimum allowed value */
+      result = 0x04;  
+    }
+    /* Set speed value for standard mode */
+    tmpreg |= result;	  
+    /* Set Maximum Rise Time for standard mode */
+    I2Cx->TRISE = freqrange + 1; 
+  }
+  /* Configure speed in fast mode */
+  else /*(I2C_InitStruct->I2C_ClockSpeed <= 400000)*/
+  {
+    if (I2C_InitStruct->I2C_DutyCycle == I2C_DutyCycle_2)
+    {
+      /* Fast mode speed calculate: Tlow/Thigh = 2 */
+      result = (uint16_t)(pclk1 / (I2C_InitStruct->I2C_ClockSpeed * 3));
+    }
+    else /*I2C_InitStruct->I2C_DutyCycle == I2C_DutyCycle_16_9*/
+    {
+      /* Fast mode speed calculate: Tlow/Thigh = 16/9 */
+      result = (uint16_t)(pclk1 / (I2C_InitStruct->I2C_ClockSpeed * 25));
+      /* Set DUTY bit */
+      result |= I2C_DutyCycle_16_9;
+    }
+
+    /* Test if CCR value is under 0x1*/
+    if ((result & CCR_CCR_Set) == 0)
+    {
+      /* Set minimum allowed value */
+      result |= (uint16_t)0x0001;  
+    }
+    /* Set speed value and set F/S bit for fast mode */
+    tmpreg |= (uint16_t)(result | CCR_FS_Set);
+    /* Set Maximum Rise Time for fast mode */
+    I2Cx->TRISE = (uint16_t)(((freqrange * (uint16_t)300) / (uint16_t)1000) + (uint16_t)1);  
+  }
+
+  /* Write to I2Cx CCR */
+  I2Cx->CCR = tmpreg;
+  /* Enable the selected I2C peripheral */
+  I2Cx->CR1 |= CR1_PE_Set;
+
+/*---------------------------- I2Cx CR1 Configuration ------------------------*/
+  /* Get the I2Cx CR1 value */
+  tmpreg = I2Cx->CR1;
+  /* Clear ACK, SMBTYPE and  SMBUS bits */
+  tmpreg &= CR1_CLEAR_Mask;
+  /* Configure I2Cx: mode and acknowledgement */
+  /* Set SMBTYPE and SMBUS bits according to I2C_Mode value */
+  /* Set ACK bit according to I2C_Ack value */
+  tmpreg |= (uint16_t)((uint32_t)I2C_InitStruct->I2C_Mode | I2C_InitStruct->I2C_Ack);
+  /* Write to I2Cx CR1 */
+  I2Cx->CR1 = tmpreg;
+
+/*---------------------------- I2Cx OAR1 Configuration -----------------------*/
+  /* Set I2Cx Own Address1 and acknowledged address */
+  I2Cx->OAR1 = (I2C_InitStruct->I2C_AcknowledgedAddress | I2C_InitStruct->I2C_OwnAddress1);
+}
+
+/**
+  * @brief  Fills each I2C_InitStruct member with its default value.
+  * @param  I2C_InitStruct: pointer to an I2C_InitTypeDef structure which will be initialized.
+  * @retval None
+  */
+void I2C_StructInit(I2C_InitTypeDef* I2C_InitStruct)
+{
+/*---------------- Reset I2C init structure parameters values ----------------*/
+  /* initialize the I2C_ClockSpeed member */
+  I2C_InitStruct->I2C_ClockSpeed = 5000;
+  /* Initialize the I2C_Mode member */
+  I2C_InitStruct->I2C_Mode = I2C_Mode_I2C;
+  /* Initialize the I2C_DutyCycle member */
+  I2C_InitStruct->I2C_DutyCycle = I2C_DutyCycle_2;
+  /* Initialize the I2C_OwnAddress1 member */
+  I2C_InitStruct->I2C_OwnAddress1 = 0;
+  /* Initialize the I2C_Ack member */
+  I2C_InitStruct->I2C_Ack = I2C_Ack_Disable;
+  /* Initialize the I2C_AcknowledgedAddress member */
+  I2C_InitStruct->I2C_AcknowledgedAddress = I2C_AcknowledgedAddress_7bit;
+}
+
+/**
+  * @brief  Enables or disables the specified I2C peripheral.
+  * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+  * @param  NewState: new state of the I2Cx peripheral. 
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void I2C_Cmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  if (NewState != DISABLE)
+  {
+    /* Enable the selected I2C peripheral */
+    I2Cx->CR1 |= CR1_PE_Set;
+  }
+  else
+  {
+    /* Disable the selected I2C peripheral */
+    I2Cx->CR1 &= CR1_PE_Reset;
+  }
+}
+
+/**
+  * @brief  Enables or disables the specified I2C DMA requests.
+  * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+  * @param  NewState: new state of the I2C DMA transfer.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void I2C_DMACmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  if (NewState != DISABLE)
+  {
+    /* Enable the selected I2C DMA requests */
+    I2Cx->CR2 |= CR2_DMAEN_Set;
+  }
+  else
+  {
+    /* Disable the selected I2C DMA requests */
+    I2Cx->CR2 &= CR2_DMAEN_Reset;
+  }
+}
+
+/**
+  * @brief  Specifies if the next DMA transfer will be the last one.
+  * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+  * @param  NewState: new state of the I2C DMA last transfer.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void I2C_DMALastTransferCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  if (NewState != DISABLE)
+  {
+    /* Next DMA transfer is the last transfer */
+    I2Cx->CR2 |= CR2_LAST_Set;
+  }
+  else
+  {
+    /* Next DMA transfer is not the last transfer */
+    I2Cx->CR2 &= CR2_LAST_Reset;
+  }
+}
+
+/**
+  * @brief  Generates I2Cx communication START condition.
+  * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+  * @param  NewState: new state of the I2C START condition generation.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None.
+  */
+void I2C_GenerateSTART(I2C_TypeDef* I2Cx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  if (NewState != DISABLE)
+  {
+    /* Generate a START condition */
+    I2Cx->CR1 |= CR1_START_Set;
+  }
+  else
+  {
+    /* Disable the START condition generation */
+    I2Cx->CR1 &= CR1_START_Reset;
+  }
+}
+
+/**
+  * @brief  Generates I2Cx communication STOP condition.
+  * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+  * @param  NewState: new state of the I2C STOP condition generation.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None.
+  */
+void I2C_GenerateSTOP(I2C_TypeDef* I2Cx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  if (NewState != DISABLE)
+  {
+    /* Generate a STOP condition */
+    I2Cx->CR1 |= CR1_STOP_Set;
+  }
+  else
+  {
+    /* Disable the STOP condition generation */
+    I2Cx->CR1 &= CR1_STOP_Reset;
+  }
+}
+
+/**
+  * @brief  Enables or disables the specified I2C acknowledge feature.
+  * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+  * @param  NewState: new state of the I2C Acknowledgement.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None.
+  */
+void I2C_AcknowledgeConfig(I2C_TypeDef* I2Cx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  if (NewState != DISABLE)
+  {
+    /* Enable the acknowledgement */
+    I2Cx->CR1 |= CR1_ACK_Set;
+  }
+  else
+  {
+    /* Disable the acknowledgement */
+    I2Cx->CR1 &= CR1_ACK_Reset;
+  }
+}
+
+/**
+  * @brief  Configures the specified I2C own address2.
+  * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+  * @param  Address: specifies the 7bit I2C own address2.
+  * @retval None.
+  */
+void I2C_OwnAddress2Config(I2C_TypeDef* I2Cx, uint8_t Address)
+{
+  uint16_t tmpreg = 0;
+
+  /* Check the parameters */
+  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+
+  /* Get the old register value */
+  tmpreg = I2Cx->OAR2;
+
+  /* Reset I2Cx Own address2 bit [7:1] */
+  tmpreg &= OAR2_ADD2_Reset;
+
+  /* Set I2Cx Own address2 */
+  tmpreg |= (uint16_t)((uint16_t)Address & (uint16_t)0x00FE);
+
+  /* Store the new register value */
+  I2Cx->OAR2 = tmpreg;
+}
+
+/**
+  * @brief  Enables or disables the specified I2C dual addressing mode.
+  * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+  * @param  NewState: new state of the I2C dual addressing mode.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void I2C_DualAddressCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  if (NewState != DISABLE)
+  {
+    /* Enable dual addressing mode */
+    I2Cx->OAR2 |= OAR2_ENDUAL_Set;
+  }
+  else
+  {
+    /* Disable dual addressing mode */
+    I2Cx->OAR2 &= OAR2_ENDUAL_Reset;
+  }
+}
+
+/**
+  * @brief  Enables or disables the specified I2C general call feature.
+  * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+  * @param  NewState: new state of the I2C General call.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void I2C_GeneralCallCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  if (NewState != DISABLE)
+  {
+    /* Enable generall call */
+    I2Cx->CR1 |= CR1_ENGC_Set;
+  }
+  else
+  {
+    /* Disable generall call */
+    I2Cx->CR1 &= CR1_ENGC_Reset;
+  }
+}
+
+/**
+  * @brief  Enables or disables the specified I2C interrupts.
+  * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+  * @param  I2C_IT: specifies the I2C interrupts sources to be enabled or disabled. 
+  *   This parameter can be any combination of the following values:
+  *     @arg I2C_IT_BUF: Buffer interrupt mask
+  *     @arg I2C_IT_EVT: Event interrupt mask
+  *     @arg I2C_IT_ERR: Error interrupt mask
+  * @param  NewState: new state of the specified I2C interrupts.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void I2C_ITConfig(I2C_TypeDef* I2Cx, uint16_t I2C_IT, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  assert_param(IS_I2C_CONFIG_IT(I2C_IT));
+  
+  if (NewState != DISABLE)
+  {
+    /* Enable the selected I2C interrupts */
+    I2Cx->CR2 |= I2C_IT;
+  }
+  else
+  {
+    /* Disable the selected I2C interrupts */
+    I2Cx->CR2 &= (uint16_t)~I2C_IT;
+  }
+}
+
+/**
+  * @brief  Sends a data byte through the I2Cx peripheral.
+  * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+  * @param  Data: Byte to be transmitted..
+  * @retval None
+  */
+void I2C_SendData(I2C_TypeDef* I2Cx, uint8_t Data)
+{
+  /* Check the parameters */
+  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+  /* Write in the DR register the data to be sent */
+  I2Cx->DR = Data;
+}
+
+/**
+  * @brief  Returns the most recent received data by the I2Cx peripheral.
+  * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+  * @retval The value of the received data.
+  */
+uint8_t I2C_ReceiveData(I2C_TypeDef* I2Cx)
+{
+  /* Check the parameters */
+  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+  /* Return the data in the DR register */
+  return (uint8_t)I2Cx->DR;
+}
+
+/**
+  * @brief  Transmits the address byte to select the slave device.
+  * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+  * @param  Address: specifies the slave address which will be transmitted
+  * @param  I2C_Direction: specifies whether the I2C device will be a
+  *   Transmitter or a Receiver. This parameter can be one of the following values
+  *     @arg I2C_Direction_Transmitter: Transmitter mode
+  *     @arg I2C_Direction_Receiver: Receiver mode
+  * @retval None.
+  */
+void I2C_Send7bitAddress(I2C_TypeDef* I2Cx, uint8_t Address, uint8_t I2C_Direction)
+{
+  /* Check the parameters */
+  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+  assert_param(IS_I2C_DIRECTION(I2C_Direction));
+  /* Test on the direction to set/reset the read/write bit */
+  if (I2C_Direction != I2C_Direction_Transmitter)
+  {
+    /* Set the address bit0 for read */
+    Address |= OAR1_ADD0_Set;
+  }
+  else
+  {
+    /* Reset the address bit0 for write */
+    Address &= OAR1_ADD0_Reset;
+  }
+  /* Send the address */
+  I2Cx->DR = Address;
+}
+
+/**
+  * @brief  Reads the specified I2C register and returns its value.
+  * @param  I2C_Register: specifies the register to read.
+  *   This parameter can be one of the following values:
+  *     @arg I2C_Register_CR1:  CR1 register.
+  *     @arg I2C_Register_CR2:   CR2 register.
+  *     @arg I2C_Register_OAR1:  OAR1 register.
+  *     @arg I2C_Register_OAR2:  OAR2 register.
+  *     @arg I2C_Register_DR:    DR register.
+  *     @arg I2C_Register_SR1:   SR1 register.
+  *     @arg I2C_Register_SR2:   SR2 register.
+  *     @arg I2C_Register_CCR:   CCR register.
+  *     @arg I2C_Register_TRISE: TRISE register.
+  * @retval The value of the read register.
+  */
+uint16_t I2C_ReadRegister(I2C_TypeDef* I2Cx, uint8_t I2C_Register)
+{
+  __IO uint32_t tmp = 0;
+
+  /* Check the parameters */
+  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+  assert_param(IS_I2C_REGISTER(I2C_Register));
+
+  tmp = (uint32_t) I2Cx;
+  tmp += I2C_Register;
+
+  /* Return the selected register value */
+  return (*(__IO uint16_t *) tmp);
+}
+
+/**
+  * @brief  Enables or disables the specified I2C software reset.
+  * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+  * @param  NewState: new state of the I2C software reset.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void I2C_SoftwareResetCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  if (NewState != DISABLE)
+  {
+    /* Peripheral under reset */
+    I2Cx->CR1 |= CR1_SWRST_Set;
+  }
+  else
+  {
+    /* Peripheral not under reset */
+    I2Cx->CR1 &= CR1_SWRST_Reset;
+  }
+}
+
+/**
+  * @brief  Selects the specified I2C NACK position in master receiver mode.
+  *         This function is useful in I2C Master Receiver mode when the number
+  *         of data to be received is equal to 2. In this case, this function 
+  *         should be called (with parameter I2C_NACKPosition_Next) before data 
+  *         reception starts,as described in the 2-byte reception procedure 
+  *         recommended in Reference Manual in Section: Master receiver.                
+  * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+  * @param  I2C_NACKPosition: specifies the NACK position. 
+  *   This parameter can be one of the following values:
+  *     @arg I2C_NACKPosition_Next: indicates that the next byte will be the last
+  *          received byte.  
+  *     @arg I2C_NACKPosition_Current: indicates that current byte is the last 
+  *          received byte.
+  *            
+  * @note    This function configures the same bit (POS) as I2C_PECPositionConfig() 
+  *          but is intended to be used in I2C mode while I2C_PECPositionConfig() 
+  *          is intended to used in SMBUS mode. 
+  *            
+  * @retval None
+  */
+void I2C_NACKPositionConfig(I2C_TypeDef* I2Cx, uint16_t I2C_NACKPosition)
+{
+  /* Check the parameters */
+  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+  assert_param(IS_I2C_NACK_POSITION(I2C_NACKPosition));
+  
+  /* Check the input parameter */
+  if (I2C_NACKPosition == I2C_NACKPosition_Next)
+  {
+    /* Next byte in shift register is the last received byte */
+    I2Cx->CR1 |= I2C_NACKPosition_Next;
+  }
+  else
+  {
+    /* Current byte in shift register is the last received byte */
+    I2Cx->CR1 &= I2C_NACKPosition_Current;
+  }
+}
+
+/**
+  * @brief  Drives the SMBusAlert pin high or low for the specified I2C.
+  * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+  * @param  I2C_SMBusAlert: specifies SMBAlert pin level. 
+  *   This parameter can be one of the following values:
+  *     @arg I2C_SMBusAlert_Low: SMBAlert pin driven low
+  *     @arg I2C_SMBusAlert_High: SMBAlert pin driven high
+  * @retval None
+  */
+void I2C_SMBusAlertConfig(I2C_TypeDef* I2Cx, uint16_t I2C_SMBusAlert)
+{
+  /* Check the parameters */
+  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+  assert_param(IS_I2C_SMBUS_ALERT(I2C_SMBusAlert));
+  if (I2C_SMBusAlert == I2C_SMBusAlert_Low)
+  {
+    /* Drive the SMBusAlert pin Low */
+    I2Cx->CR1 |= I2C_SMBusAlert_Low;
+  }
+  else
+  {
+    /* Drive the SMBusAlert pin High  */
+    I2Cx->CR1 &= I2C_SMBusAlert_High;
+  }
+}
+
+/**
+  * @brief  Enables or disables the specified I2C PEC transfer.
+  * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+  * @param  NewState: new state of the I2C PEC transmission.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void I2C_TransmitPEC(I2C_TypeDef* I2Cx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  if (NewState != DISABLE)
+  {
+    /* Enable the selected I2C PEC transmission */
+    I2Cx->CR1 |= CR1_PEC_Set;
+  }
+  else
+  {
+    /* Disable the selected I2C PEC transmission */
+    I2Cx->CR1 &= CR1_PEC_Reset;
+  }
+}
+
+/**
+  * @brief  Selects the specified I2C PEC position.
+  * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+  * @param  I2C_PECPosition: specifies the PEC position. 
+  *   This parameter can be one of the following values:
+  *     @arg I2C_PECPosition_Next: indicates that the next byte is PEC
+  *     @arg I2C_PECPosition_Current: indicates that current byte is PEC
+  *       
+  * @note    This function configures the same bit (POS) as I2C_NACKPositionConfig()
+  *          but is intended to be used in SMBUS mode while I2C_NACKPositionConfig() 
+  *          is intended to used in I2C mode.
+  *               
+  * @retval None
+  */
+void I2C_PECPositionConfig(I2C_TypeDef* I2Cx, uint16_t I2C_PECPosition)
+{
+  /* Check the parameters */
+  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+  assert_param(IS_I2C_PEC_POSITION(I2C_PECPosition));
+  if (I2C_PECPosition == I2C_PECPosition_Next)
+  {
+    /* Next byte in shift register is PEC */
+    I2Cx->CR1 |= I2C_PECPosition_Next;
+  }
+  else
+  {
+    /* Current byte in shift register is PEC */
+    I2Cx->CR1 &= I2C_PECPosition_Current;
+  }
+}
+
+/**
+  * @brief  Enables or disables the PEC value calculation of the transferred bytes.
+  * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+  * @param  NewState: new state of the I2Cx PEC value calculation.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void I2C_CalculatePEC(I2C_TypeDef* I2Cx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  if (NewState != DISABLE)
+  {
+    /* Enable the selected I2C PEC calculation */
+    I2Cx->CR1 |= CR1_ENPEC_Set;
+  }
+  else
+  {
+    /* Disable the selected I2C PEC calculation */
+    I2Cx->CR1 &= CR1_ENPEC_Reset;
+  }
+}
+
+/**
+  * @brief  Returns the PEC value for the specified I2C.
+  * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+  * @retval The PEC value.
+  */
+uint8_t I2C_GetPEC(I2C_TypeDef* I2Cx)
+{
+  /* Check the parameters */
+  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+  /* Return the selected I2C PEC value */
+  return ((I2Cx->SR2) >> 8);
+}
+
+/**
+  * @brief  Enables or disables the specified I2C ARP.
+  * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+  * @param  NewState: new state of the I2Cx ARP. 
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void I2C_ARPCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  if (NewState != DISABLE)
+  {
+    /* Enable the selected I2C ARP */
+    I2Cx->CR1 |= CR1_ENARP_Set;
+  }
+  else
+  {
+    /* Disable the selected I2C ARP */
+    I2Cx->CR1 &= CR1_ENARP_Reset;
+  }
+}
+
+/**
+  * @brief  Enables or disables the specified I2C Clock stretching.
+  * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+  * @param  NewState: new state of the I2Cx Clock stretching.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void I2C_StretchClockCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  if (NewState == DISABLE)
+  {
+    /* Enable the selected I2C Clock stretching */
+    I2Cx->CR1 |= CR1_NOSTRETCH_Set;
+  }
+  else
+  {
+    /* Disable the selected I2C Clock stretching */
+    I2Cx->CR1 &= CR1_NOSTRETCH_Reset;
+  }
+}
+
+/**
+  * @brief  Selects the specified I2C fast mode duty cycle.
+  * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+  * @param  I2C_DutyCycle: specifies the fast mode duty cycle.
+  *   This parameter can be one of the following values:
+  *     @arg I2C_DutyCycle_2: I2C fast mode Tlow/Thigh = 2
+  *     @arg I2C_DutyCycle_16_9: I2C fast mode Tlow/Thigh = 16/9
+  * @retval None
+  */
+void I2C_FastModeDutyCycleConfig(I2C_TypeDef* I2Cx, uint16_t I2C_DutyCycle)
+{
+  /* Check the parameters */
+  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+  assert_param(IS_I2C_DUTY_CYCLE(I2C_DutyCycle));
+  if (I2C_DutyCycle != I2C_DutyCycle_16_9)
+  {
+    /* I2C fast mode Tlow/Thigh=2 */
+    I2Cx->CCR &= I2C_DutyCycle_2;
+  }
+  else
+  {
+    /* I2C fast mode Tlow/Thigh=16/9 */
+    I2Cx->CCR |= I2C_DutyCycle_16_9;
+  }
+}
+
+
+
+/**
+ * @brief
+ ****************************************************************************************
+ *
+ *                         I2C State Monitoring Functions
+ *                       
+ ****************************************************************************************   
+ * This I2C driver provides three different ways for I2C state monitoring
+ *  depending on the application requirements and constraints:
+ *        
+ *  
+ * 1) Basic state monitoring:
+ *    Using I2C_CheckEvent() function:
+ *    It compares the status registers (SR1 and SR2) content to a given event
+ *    (can be the combination of one or more flags).
+ *    It returns SUCCESS if the current status includes the given flags 
+ *    and returns ERROR if one or more flags are missing in the current status.
+ *    - When to use:
+ *      - This function is suitable for most applications as well as for startup 
+ *      activity since the events are fully described in the product reference manual 
+ *      (RM0008).
+ *      - It is also suitable for users who need to define their own events.
+ *    - Limitations:
+ *      - If an error occurs (ie. error flags are set besides to the monitored flags),
+ *        the I2C_CheckEvent() function may return SUCCESS despite the communication
+ *        hold or corrupted real state. 
+ *        In this case, it is advised to use error interrupts to monitor the error
+ *        events and handle them in the interrupt IRQ handler.
+ *        
+ *        @note 
+ *        For error management, it is advised to use the following functions:
+ *          - I2C_ITConfig() to configure and enable the error interrupts (I2C_IT_ERR).
+ *          - I2Cx_ER_IRQHandler() which is called when the error interrupt occurs.
+ *            Where x is the peripheral instance (I2C1, I2C2 ...)
+ *          - I2C_GetFlagStatus() or I2C_GetITStatus() to be called into I2Cx_ER_IRQHandler() 
+ *            in order to determine which error occured.
+ *          - I2C_ClearFlag() or I2C_ClearITPendingBit() and/or I2C_SoftwareResetCmd()
+ *            and/or I2C_GenerateStop() in order to clear the error flag and source,
+ *            and return to correct communication status.
+ *            
+ *
+ *  2) Advanced state monitoring:
+ *     Using the function I2C_GetLastEvent() which returns the image of both status 
+ *     registers in a single word (uint32_t) (Status Register 2 value is shifted left 
+ *     by 16 bits and concatenated to Status Register 1).
+ *     - When to use:
+ *       - This function is suitable for the same applications above but it allows to
+ *         overcome the mentioned limitation of I2C_GetFlagStatus() function.
+ *         The returned value could be compared to events already defined in the 
+ *         library (stm32f10x_i2c.h) or to custom values defined by user.
+ *       - This function is suitable when multiple flags are monitored at the same time.
+ *       - At the opposite of I2C_CheckEvent() function, this function allows user to
+ *         choose when an event is accepted (when all events flags are set and no 
+ *         other flags are set or just when the needed flags are set like 
+ *         I2C_CheckEvent() function).
+ *     - Limitations:
+ *       - User may need to define his own events.
+ *       - Same remark concerning the error management is applicable for this 
+ *         function if user decides to check only regular communication flags (and 
+ *         ignores error flags).
+ *     
+ *
+ *  3) Flag-based state monitoring:
+ *     Using the function I2C_GetFlagStatus() which simply returns the status of 
+ *     one single flag (ie. I2C_FLAG_RXNE ...). 
+ *     - When to use:
+ *        - This function could be used for specific applications or in debug phase.
+ *        - It is suitable when only one flag checking is needed (most I2C events 
+ *          are monitored through multiple flags).
+ *     - Limitations: 
+ *        - When calling this function, the Status register is accessed. Some flags are
+ *          cleared when the status register is accessed. So checking the status
+ *          of one Flag, may clear other ones.
+ *        - Function may need to be called twice or more in order to monitor one 
+ *          single event.
+ *
+ *  For detailed description of Events, please refer to section I2C_Events in 
+ *  stm32f10x_i2c.h file.
+ *  
+ */
+
+/**
+ * 
+ *  1) Basic state monitoring
+ *******************************************************************************
+ */
+
+/**
+  * @brief  Checks whether the last I2Cx Event is equal to the one passed
+  *   as parameter.
+  * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+  * @param  I2C_EVENT: specifies the event to be checked. 
+  *   This parameter can be one of the following values:
+  *     @arg I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED           : EV1
+  *     @arg I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED              : EV1
+  *     @arg I2C_EVENT_SLAVE_TRANSMITTER_SECONDADDRESS_MATCHED     : EV1
+  *     @arg I2C_EVENT_SLAVE_RECEIVER_SECONDADDRESS_MATCHED        : EV1
+  *     @arg I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED            : EV1
+  *     @arg I2C_EVENT_SLAVE_BYTE_RECEIVED                         : EV2
+  *     @arg (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_DUALF)      : EV2
+  *     @arg (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_GENCALL)    : EV2
+  *     @arg I2C_EVENT_SLAVE_BYTE_TRANSMITTED                      : EV3
+  *     @arg (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | I2C_FLAG_DUALF)   : EV3
+  *     @arg (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | I2C_FLAG_GENCALL) : EV3
+  *     @arg I2C_EVENT_SLAVE_ACK_FAILURE                           : EV3_2
+  *     @arg I2C_EVENT_SLAVE_STOP_DETECTED                         : EV4
+  *     @arg I2C_EVENT_MASTER_MODE_SELECT                          : EV5
+  *     @arg I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED            : EV6     
+  *     @arg I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED               : EV6
+  *     @arg I2C_EVENT_MASTER_BYTE_RECEIVED                        : EV7
+  *     @arg I2C_EVENT_MASTER_BYTE_TRANSMITTING                    : EV8
+  *     @arg I2C_EVENT_MASTER_BYTE_TRANSMITTED                     : EV8_2
+  *     @arg I2C_EVENT_MASTER_MODE_ADDRESS10                       : EV9
+  *     
+  * @note: For detailed description of Events, please refer to section 
+  *    I2C_Events in stm32f10x_i2c.h file.
+  *    
+  * @retval An ErrorStatus enumeration value:
+  * - SUCCESS: Last event is equal to the I2C_EVENT
+  * - ERROR: Last event is different from the I2C_EVENT
+  */
+ErrorStatus I2C_CheckEvent(I2C_TypeDef* I2Cx, uint32_t I2C_EVENT)
+{
+  uint32_t lastevent = 0;
+  uint32_t flag1 = 0, flag2 = 0;
+  ErrorStatus status = ERROR;
+
+  /* Check the parameters */
+  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+  assert_param(IS_I2C_EVENT(I2C_EVENT));
+
+  /* Read the I2Cx status register */
+  flag1 = I2Cx->SR1;
+  flag2 = I2Cx->SR2;
+  flag2 = flag2 << 16;
+
+  /* Get the last event value from I2C status register */
+  lastevent = (flag1 | flag2) & FLAG_Mask;
+
+  /* Check whether the last event contains the I2C_EVENT */
+  if ((lastevent & I2C_EVENT) == I2C_EVENT)
+  {
+    /* SUCCESS: last event is equal to I2C_EVENT */
+    status = SUCCESS;
+  }
+  else
+  {
+    /* ERROR: last event is different from I2C_EVENT */
+    status = ERROR;
+  }
+  /* Return status */
+  return status;
+}
+
+/**
+ * 
+ *  2) Advanced state monitoring
+ *******************************************************************************
+ */
+
+/**
+  * @brief  Returns the last I2Cx Event.
+  * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+  *     
+  * @note: For detailed description of Events, please refer to section 
+  *    I2C_Events in stm32f10x_i2c.h file.
+  *    
+  * @retval The last event
+  */
+uint32_t I2C_GetLastEvent(I2C_TypeDef* I2Cx)
+{
+  uint32_t lastevent = 0;
+  uint32_t flag1 = 0, flag2 = 0;
+
+  /* Check the parameters */
+  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+
+  /* Read the I2Cx status register */
+  flag1 = I2Cx->SR1;
+  flag2 = I2Cx->SR2;
+  flag2 = flag2 << 16;
+
+  /* Get the last event value from I2C status register */
+  lastevent = (flag1 | flag2) & FLAG_Mask;
+
+  /* Return status */
+  return lastevent;
+}
+
+/**
+ * 
+ *  3) Flag-based state monitoring
+ *******************************************************************************
+ */
+
+/**
+  * @brief  Checks whether the specified I2C flag is set or not.
+  * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+  * @param  I2C_FLAG: specifies the flag to check. 
+  *   This parameter can be one of the following values:
+  *     @arg I2C_FLAG_DUALF: Dual flag (Slave mode)
+  *     @arg I2C_FLAG_SMBHOST: SMBus host header (Slave mode)
+  *     @arg I2C_FLAG_SMBDEFAULT: SMBus default header (Slave mode)
+  *     @arg I2C_FLAG_GENCALL: General call header flag (Slave mode)
+  *     @arg I2C_FLAG_TRA: Transmitter/Receiver flag
+  *     @arg I2C_FLAG_BUSY: Bus busy flag
+  *     @arg I2C_FLAG_MSL: Master/Slave flag
+  *     @arg I2C_FLAG_SMBALERT: SMBus Alert flag
+  *     @arg I2C_FLAG_TIMEOUT: Timeout or Tlow error flag
+  *     @arg I2C_FLAG_PECERR: PEC error in reception flag
+  *     @arg I2C_FLAG_OVR: Overrun/Underrun flag (Slave mode)
+  *     @arg I2C_FLAG_AF: Acknowledge failure flag
+  *     @arg I2C_FLAG_ARLO: Arbitration lost flag (Master mode)
+  *     @arg I2C_FLAG_BERR: Bus error flag
+  *     @arg I2C_FLAG_TXE: Data register empty flag (Transmitter)
+  *     @arg I2C_FLAG_RXNE: Data register not empty (Receiver) flag
+  *     @arg I2C_FLAG_STOPF: Stop detection flag (Slave mode)
+  *     @arg I2C_FLAG_ADD10: 10-bit header sent flag (Master mode)
+  *     @arg I2C_FLAG_BTF: Byte transfer finished flag
+  *     @arg I2C_FLAG_ADDR: Address sent flag (Master mode) "ADSL"
+  *   Address matched flag (Slave mode)"ENDA"
+  *     @arg I2C_FLAG_SB: Start bit flag (Master mode)
+  * @retval The new state of I2C_FLAG (SET or RESET).
+  */
+FlagStatus I2C_GetFlagStatus(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG)
+{
+  FlagStatus bitstatus = RESET;
+  __IO uint32_t i2creg = 0, i2cxbase = 0;
+
+  /* Check the parameters */
+  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+  assert_param(IS_I2C_GET_FLAG(I2C_FLAG));
+
+  /* Get the I2Cx peripheral base address */
+  i2cxbase = (uint32_t)I2Cx;
+  
+  /* Read flag register index */
+  i2creg = I2C_FLAG >> 28;
+  
+  /* Get bit[23:0] of the flag */
+  I2C_FLAG &= FLAG_Mask;
+  
+  if(i2creg != 0)
+  {
+    /* Get the I2Cx SR1 register address */
+    i2cxbase += 0x14;
+  }
+  else
+  {
+    /* Flag in I2Cx SR2 Register */
+    I2C_FLAG = (uint32_t)(I2C_FLAG >> 16);
+    /* Get the I2Cx SR2 register address */
+    i2cxbase += 0x18;
+  }
+  
+  if(((*(__IO uint32_t *)i2cxbase) & I2C_FLAG) != (uint32_t)RESET)
+  {
+    /* I2C_FLAG is set */
+    bitstatus = SET;
+  }
+  else
+  {
+    /* I2C_FLAG is reset */
+    bitstatus = RESET;
+  }
+  
+  /* Return the I2C_FLAG status */
+  return  bitstatus;
+}
+
+
+
+/**
+  * @brief  Clears the I2Cx's pending flags.
+  * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+  * @param  I2C_FLAG: specifies the flag to clear. 
+  *   This parameter can be any combination of the following values:
+  *     @arg I2C_FLAG_SMBALERT: SMBus Alert flag
+  *     @arg I2C_FLAG_TIMEOUT: Timeout or Tlow error flag
+  *     @arg I2C_FLAG_PECERR: PEC error in reception flag
+  *     @arg I2C_FLAG_OVR: Overrun/Underrun flag (Slave mode)
+  *     @arg I2C_FLAG_AF: Acknowledge failure flag
+  *     @arg I2C_FLAG_ARLO: Arbitration lost flag (Master mode)
+  *     @arg I2C_FLAG_BERR: Bus error flag
+  *   
+  * @note
+  *   - STOPF (STOP detection) is cleared by software sequence: a read operation 
+  *     to I2C_SR1 register (I2C_GetFlagStatus()) followed by a write operation 
+  *     to I2C_CR1 register (I2C_Cmd() to re-enable the I2C peripheral).
+  *   - ADD10 (10-bit header sent) is cleared by software sequence: a read 
+  *     operation to I2C_SR1 (I2C_GetFlagStatus()) followed by writing the 
+  *     second byte of the address in DR register.
+  *   - BTF (Byte Transfer Finished) is cleared by software sequence: a read 
+  *     operation to I2C_SR1 register (I2C_GetFlagStatus()) followed by a 
+  *     read/write to I2C_DR register (I2C_SendData()).
+  *   - ADDR (Address sent) is cleared by software sequence: a read operation to 
+  *     I2C_SR1 register (I2C_GetFlagStatus()) followed by a read operation to 
+  *     I2C_SR2 register ((void)(I2Cx->SR2)).
+  *   - SB (Start Bit) is cleared software sequence: a read operation to I2C_SR1
+  *     register (I2C_GetFlagStatus()) followed by a write operation to I2C_DR
+  *     register  (I2C_SendData()).
+  * @retval None
+  */
+void I2C_ClearFlag(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG)
+{
+  uint32_t flagpos = 0;
+  /* Check the parameters */
+  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+  assert_param(IS_I2C_CLEAR_FLAG(I2C_FLAG));
+  /* Get the I2C flag position */
+  flagpos = I2C_FLAG & FLAG_Mask;
+  /* Clear the selected I2C flag */
+  I2Cx->SR1 = (uint16_t)~flagpos;
+}
+
+/**
+  * @brief  Checks whether the specified I2C interrupt has occurred or not.
+  * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+  * @param  I2C_IT: specifies the interrupt source to check. 
+  *   This parameter can be one of the following values:
+  *     @arg I2C_IT_SMBALERT: SMBus Alert flag
+  *     @arg I2C_IT_TIMEOUT: Timeout or Tlow error flag
+  *     @arg I2C_IT_PECERR: PEC error in reception flag
+  *     @arg I2C_IT_OVR: Overrun/Underrun flag (Slave mode)
+  *     @arg I2C_IT_AF: Acknowledge failure flag
+  *     @arg I2C_IT_ARLO: Arbitration lost flag (Master mode)
+  *     @arg I2C_IT_BERR: Bus error flag
+  *     @arg I2C_IT_TXE: Data register empty flag (Transmitter)
+  *     @arg I2C_IT_RXNE: Data register not empty (Receiver) flag
+  *     @arg I2C_IT_STOPF: Stop detection flag (Slave mode)
+  *     @arg I2C_IT_ADD10: 10-bit header sent flag (Master mode)
+  *     @arg I2C_IT_BTF: Byte transfer finished flag
+  *     @arg I2C_IT_ADDR: Address sent flag (Master mode) "ADSL"
+  *                       Address matched flag (Slave mode)"ENDAD"
+  *     @arg I2C_IT_SB: Start bit flag (Master mode)
+  * @retval The new state of I2C_IT (SET or RESET).
+  */
+ITStatus I2C_GetITStatus(I2C_TypeDef* I2Cx, uint32_t I2C_IT)
+{
+  ITStatus bitstatus = RESET;
+  uint32_t enablestatus = 0;
+
+  /* Check the parameters */
+  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+  assert_param(IS_I2C_GET_IT(I2C_IT));
+
+  /* Check if the interrupt source is enabled or not */
+  enablestatus = (uint32_t)(((I2C_IT & ITEN_Mask) >> 16) & (I2Cx->CR2)) ;
+  
+  /* Get bit[23:0] of the flag */
+  I2C_IT &= FLAG_Mask;
+
+  /* Check the status of the specified I2C flag */
+  if (((I2Cx->SR1 & I2C_IT) != (uint32_t)RESET) && enablestatus)
+  {
+    /* I2C_IT is set */
+    bitstatus = SET;
+  }
+  else
+  {
+    /* I2C_IT is reset */
+    bitstatus = RESET;
+  }
+  /* Return the I2C_IT status */
+  return  bitstatus;
+}
+
+/**
+  * @brief  Clears the I2Cx�s interrupt pending bits.
+  * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+  * @param  I2C_IT: specifies the interrupt pending bit to clear. 
+  *   This parameter can be any combination of the following values:
+  *     @arg I2C_IT_SMBALERT: SMBus Alert interrupt
+  *     @arg I2C_IT_TIMEOUT: Timeout or Tlow error interrupt
+  *     @arg I2C_IT_PECERR: PEC error in reception  interrupt
+  *     @arg I2C_IT_OVR: Overrun/Underrun interrupt (Slave mode)
+  *     @arg I2C_IT_AF: Acknowledge failure interrupt
+  *     @arg I2C_IT_ARLO: Arbitration lost interrupt (Master mode)
+  *     @arg I2C_IT_BERR: Bus error interrupt
+  *   
+  * @note
+  *   - STOPF (STOP detection) is cleared by software sequence: a read operation 
+  *     to I2C_SR1 register (I2C_GetITStatus()) followed by a write operation to 
+  *     I2C_CR1 register (I2C_Cmd() to re-enable the I2C peripheral).
+  *   - ADD10 (10-bit header sent) is cleared by software sequence: a read 
+  *     operation to I2C_SR1 (I2C_GetITStatus()) followed by writing the second 
+  *     byte of the address in I2C_DR register.
+  *   - BTF (Byte Transfer Finished) is cleared by software sequence: a read 
+  *     operation to I2C_SR1 register (I2C_GetITStatus()) followed by a 
+  *     read/write to I2C_DR register (I2C_SendData()).
+  *   - ADDR (Address sent) is cleared by software sequence: a read operation to 
+  *     I2C_SR1 register (I2C_GetITStatus()) followed by a read operation to 
+  *     I2C_SR2 register ((void)(I2Cx->SR2)).
+  *   - SB (Start Bit) is cleared by software sequence: a read operation to 
+  *     I2C_SR1 register (I2C_GetITStatus()) followed by a write operation to 
+  *     I2C_DR register (I2C_SendData()).
+  * @retval None
+  */
+void I2C_ClearITPendingBit(I2C_TypeDef* I2Cx, uint32_t I2C_IT)
+{
+  uint32_t flagpos = 0;
+  /* Check the parameters */
+  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+  assert_param(IS_I2C_CLEAR_IT(I2C_IT));
+  /* Get the I2C flag position */
+  flagpos = I2C_IT & FLAG_Mask;
+  /* Clear the selected I2C flag */
+  I2Cx->SR1 = (uint16_t)~flagpos;
+}
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/STM32_4路称重_Git提交精简工程/src/STM32F10x_FWLib/src/stm32f10x_iwdg.c b/STM32_4路称重_Git提交精简工程/src/STM32F10x_FWLib/src/stm32f10x_iwdg.c
new file mode 100755
index 0000000..9d3b0e8
--- /dev/null
+++ b/STM32_4路称重_Git提交精简工程/src/STM32F10x_FWLib/src/stm32f10x_iwdg.c
@@ -0,0 +1,190 @@
+/**
+  ******************************************************************************
+  * @file    stm32f10x_iwdg.c
+  * @author  MCD Application Team
+  * @version V3.5.0
+  * @date    11-March-2011
+  * @brief   This file provides all the IWDG firmware functions.
+  ******************************************************************************
+  * @attention
+  *
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+  *
+  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x_iwdg.h"
+
+/** @addtogroup STM32F10x_StdPeriph_Driver
+  * @{
+  */
+
+/** @defgroup IWDG 
+  * @brief IWDG driver modules
+  * @{
+  */ 
+
+/** @defgroup IWDG_Private_TypesDefinitions
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup IWDG_Private_Defines
+  * @{
+  */ 
+
+/* ---------------------- IWDG registers bit mask ----------------------------*/
+
+/* KR register bit mask */
+#define KR_KEY_Reload    ((uint16_t)0xAAAA)
+#define KR_KEY_Enable    ((uint16_t)0xCCCC)
+
+/**
+  * @}
+  */ 
+
+/** @defgroup IWDG_Private_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup IWDG_Private_Variables
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup IWDG_Private_FunctionPrototypes
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup IWDG_Private_Functions
+  * @{
+  */
+
+/**
+  * @brief  Enables or disables write access to IWDG_PR and IWDG_RLR registers.
+  * @param  IWDG_WriteAccess: new state of write access to IWDG_PR and IWDG_RLR registers.
+  *   This parameter can be one of the following values:
+  *     @arg IWDG_WriteAccess_Enable: Enable write access to IWDG_PR and IWDG_RLR registers
+  *     @arg IWDG_WriteAccess_Disable: Disable write access to IWDG_PR and IWDG_RLR registers
+  * @retval None
+  */
+void IWDG_WriteAccessCmd(uint16_t IWDG_WriteAccess)
+{
+  /* Check the parameters */
+  assert_param(IS_IWDG_WRITE_ACCESS(IWDG_WriteAccess));
+  IWDG->KR = IWDG_WriteAccess;
+}
+
+/**
+  * @brief  Sets IWDG Prescaler value.
+  * @param  IWDG_Prescaler: specifies the IWDG Prescaler value.
+  *   This parameter can be one of the following values:
+  *     @arg IWDG_Prescaler_4: IWDG prescaler set to 4
+  *     @arg IWDG_Prescaler_8: IWDG prescaler set to 8
+  *     @arg IWDG_Prescaler_16: IWDG prescaler set to 16
+  *     @arg IWDG_Prescaler_32: IWDG prescaler set to 32
+  *     @arg IWDG_Prescaler_64: IWDG prescaler set to 64
+  *     @arg IWDG_Prescaler_128: IWDG prescaler set to 128
+  *     @arg IWDG_Prescaler_256: IWDG prescaler set to 256
+  * @retval None
+  */
+void IWDG_SetPrescaler(uint8_t IWDG_Prescaler)
+{
+  /* Check the parameters */
+  assert_param(IS_IWDG_PRESCALER(IWDG_Prescaler));
+  IWDG->PR = IWDG_Prescaler;
+}
+
+/**
+  * @brief  Sets IWDG Reload value.
+  * @param  Reload: specifies the IWDG Reload value.
+  *   This parameter must be a number between 0 and 0x0FFF.
+  * @retval None
+  */
+void IWDG_SetReload(uint16_t Reload)
+{
+  /* Check the parameters */
+  assert_param(IS_IWDG_RELOAD(Reload));
+  IWDG->RLR = Reload;
+}
+
+/**
+  * @brief  Reloads IWDG counter with value defined in the reload register
+  *   (write access to IWDG_PR and IWDG_RLR registers disabled).
+  * @param  None
+  * @retval None
+  */
+void IWDG_ReloadCounter(void)
+{
+  IWDG->KR = KR_KEY_Reload;
+}
+
+/**
+  * @brief  Enables IWDG (write access to IWDG_PR and IWDG_RLR registers disabled).
+  * @param  None
+  * @retval None
+  */
+void IWDG_Enable(void)
+{
+  IWDG->KR = KR_KEY_Enable;
+}
+
+/**
+  * @brief  Checks whether the specified IWDG flag is set or not.
+  * @param  IWDG_FLAG: specifies the flag to check.
+  *   This parameter can be one of the following values:
+  *     @arg IWDG_FLAG_PVU: Prescaler Value Update on going
+  *     @arg IWDG_FLAG_RVU: Reload Value Update on going
+  * @retval The new state of IWDG_FLAG (SET or RESET).
+  */
+FlagStatus IWDG_GetFlagStatus(uint16_t IWDG_FLAG)
+{
+  FlagStatus bitstatus = RESET;
+  /* Check the parameters */
+  assert_param(IS_IWDG_FLAG(IWDG_FLAG));
+  if ((IWDG->SR & IWDG_FLAG) != (uint32_t)RESET)
+  {
+    bitstatus = SET;
+  }
+  else
+  {
+    bitstatus = RESET;
+  }
+  /* Return the flag status */
+  return bitstatus;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/STM32_4路称重_Git提交精简工程/src/STM32F10x_FWLib/src/stm32f10x_pwr.c b/STM32_4路称重_Git提交精简工程/src/STM32F10x_FWLib/src/stm32f10x_pwr.c
new file mode 100755
index 0000000..147bf0f
--- /dev/null
+++ b/STM32_4路称重_Git提交精简工程/src/STM32F10x_FWLib/src/stm32f10x_pwr.c
@@ -0,0 +1,307 @@
+/**
+  ******************************************************************************
+  * @file    stm32f10x_pwr.c
+  * @author  MCD Application Team
+  * @version V3.5.0
+  * @date    11-March-2011
+  * @brief   This file provides all the PWR firmware functions.
+  ******************************************************************************
+  * @attention
+  *
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+  *
+  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x_pwr.h"
+#include "stm32f10x_rcc.h"
+
+/** @addtogroup STM32F10x_StdPeriph_Driver
+  * @{
+  */
+
+/** @defgroup PWR 
+  * @brief PWR driver modules
+  * @{
+  */ 
+
+/** @defgroup PWR_Private_TypesDefinitions
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup PWR_Private_Defines
+  * @{
+  */
+
+/* --------- PWR registers bit address in the alias region ---------- */
+#define PWR_OFFSET               (PWR_BASE - PERIPH_BASE)
+
+/* --- CR Register ---*/
+
+/* Alias word address of DBP bit */
+#define CR_OFFSET                (PWR_OFFSET + 0x00)
+#define DBP_BitNumber            0x08
+#define CR_DBP_BB                (PERIPH_BB_BASE + (CR_OFFSET * 32) + (DBP_BitNumber * 4))
+
+/* Alias word address of PVDE bit */
+#define PVDE_BitNumber           0x04
+#define CR_PVDE_BB               (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PVDE_BitNumber * 4))
+
+/* --- CSR Register ---*/
+
+/* Alias word address of EWUP bit */
+#define CSR_OFFSET               (PWR_OFFSET + 0x04)
+#define EWUP_BitNumber           0x08
+#define CSR_EWUP_BB              (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (EWUP_BitNumber * 4))
+
+/* ------------------ PWR registers bit mask ------------------------ */
+
+/* CR register bit mask */
+#define CR_DS_MASK               ((uint32_t)0xFFFFFFFC)
+#define CR_PLS_MASK              ((uint32_t)0xFFFFFF1F)
+
+
+/**
+  * @}
+  */
+
+/** @defgroup PWR_Private_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup PWR_Private_Variables
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup PWR_Private_FunctionPrototypes
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup PWR_Private_Functions
+  * @{
+  */
+
+/**
+  * @brief  Deinitializes the PWR peripheral registers to their default reset values.
+  * @param  None
+  * @retval None
+  */
+void PWR_DeInit(void)
+{
+  RCC_APB1PeriphResetCmd(RCC_APB1Periph_PWR, ENABLE);
+  RCC_APB1PeriphResetCmd(RCC_APB1Periph_PWR, DISABLE);
+}
+
+/**
+  * @brief  Enables or disables access to the RTC and backup registers.
+  * @param  NewState: new state of the access to the RTC and backup registers.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void PWR_BackupAccessCmd(FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  *(__IO uint32_t *) CR_DBP_BB = (uint32_t)NewState;
+}
+
+/**
+  * @brief  Enables or disables the Power Voltage Detector(PVD).
+  * @param  NewState: new state of the PVD.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void PWR_PVDCmd(FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  *(__IO uint32_t *) CR_PVDE_BB = (uint32_t)NewState;
+}
+
+/**
+  * @brief  Configures the voltage threshold detected by the Power Voltage Detector(PVD).
+  * @param  PWR_PVDLevel: specifies the PVD detection level
+  *   This parameter can be one of the following values:
+  *     @arg PWR_PVDLevel_2V2: PVD detection level set to 2.2V
+  *     @arg PWR_PVDLevel_2V3: PVD detection level set to 2.3V
+  *     @arg PWR_PVDLevel_2V4: PVD detection level set to 2.4V
+  *     @arg PWR_PVDLevel_2V5: PVD detection level set to 2.5V
+  *     @arg PWR_PVDLevel_2V6: PVD detection level set to 2.6V
+  *     @arg PWR_PVDLevel_2V7: PVD detection level set to 2.7V
+  *     @arg PWR_PVDLevel_2V8: PVD detection level set to 2.8V
+  *     @arg PWR_PVDLevel_2V9: PVD detection level set to 2.9V
+  * @retval None
+  */
+void PWR_PVDLevelConfig(uint32_t PWR_PVDLevel)
+{
+  uint32_t tmpreg = 0;
+  /* Check the parameters */
+  assert_param(IS_PWR_PVD_LEVEL(PWR_PVDLevel));
+  tmpreg = PWR->CR;
+  /* Clear PLS[7:5] bits */
+  tmpreg &= CR_PLS_MASK;
+  /* Set PLS[7:5] bits according to PWR_PVDLevel value */
+  tmpreg |= PWR_PVDLevel;
+  /* Store the new value */
+  PWR->CR = tmpreg;
+}
+
+/**
+  * @brief  Enables or disables the WakeUp Pin functionality.
+  * @param  NewState: new state of the WakeUp Pin functionality.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void PWR_WakeUpPinCmd(FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  *(__IO uint32_t *) CSR_EWUP_BB = (uint32_t)NewState;
+}
+
+/**
+  * @brief  Enters STOP mode.
+  * @param  PWR_Regulator: specifies the regulator state in STOP mode.
+  *   This parameter can be one of the following values:
+  *     @arg PWR_Regulator_ON: STOP mode with regulator ON
+  *     @arg PWR_Regulator_LowPower: STOP mode with regulator in low power mode
+  * @param  PWR_STOPEntry: specifies if STOP mode in entered with WFI or WFE instruction.
+  *   This parameter can be one of the following values:
+  *     @arg PWR_STOPEntry_WFI: enter STOP mode with WFI instruction
+  *     @arg PWR_STOPEntry_WFE: enter STOP mode with WFE instruction
+  * @retval None
+  */
+void PWR_EnterSTOPMode(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry)
+{
+  uint32_t tmpreg = 0;
+  /* Check the parameters */
+  assert_param(IS_PWR_REGULATOR(PWR_Regulator));
+  assert_param(IS_PWR_STOP_ENTRY(PWR_STOPEntry));
+  
+  /* Select the regulator state in STOP mode ---------------------------------*/
+  tmpreg = PWR->CR;
+  /* Clear PDDS and LPDS bits */
+  tmpreg &= CR_DS_MASK;
+  /* Set LPDS bit according to PWR_Regulator value */
+  tmpreg |= PWR_Regulator;
+  /* Store the new value */
+  PWR->CR = tmpreg;
+  /* Set SLEEPDEEP bit of Cortex System Control Register */
+  SCB->SCR |= SCB_SCR_SLEEPDEEP;
+  
+  /* Select STOP mode entry --------------------------------------------------*/
+  if(PWR_STOPEntry == PWR_STOPEntry_WFI)
+  {   
+    /* Request Wait For Interrupt */
+    __WFI();
+  }
+  else
+  {
+    /* Request Wait For Event */
+    __WFE();
+  }
+  
+  /* Reset SLEEPDEEP bit of Cortex System Control Register */
+  SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP);  
+}
+
+/**
+  * @brief  Enters STANDBY mode.
+  * @param  None
+  * @retval None
+  */
+void PWR_EnterSTANDBYMode(void)
+{
+  /* Clear Wake-up flag */
+  PWR->CR |= PWR_CR_CWUF;
+  /* Select STANDBY mode */
+  PWR->CR |= PWR_CR_PDDS;
+  /* Set SLEEPDEEP bit of Cortex System Control Register */
+  SCB->SCR |= SCB_SCR_SLEEPDEEP;
+/* This option is used to ensure that store operations are completed */
+#if defined ( __CC_ARM   )
+  __force_stores();
+#endif
+  /* Request Wait For Interrupt */
+  __WFI();
+}
+
+/**
+  * @brief  Checks whether the specified PWR flag is set or not.
+  * @param  PWR_FLAG: specifies the flag to check.
+  *   This parameter can be one of the following values:
+  *     @arg PWR_FLAG_WU: Wake Up flag
+  *     @arg PWR_FLAG_SB: StandBy flag
+  *     @arg PWR_FLAG_PVDO: PVD Output
+  * @retval The new state of PWR_FLAG (SET or RESET).
+  */
+FlagStatus PWR_GetFlagStatus(uint32_t PWR_FLAG)
+{
+  FlagStatus bitstatus = RESET;
+  /* Check the parameters */
+  assert_param(IS_PWR_GET_FLAG(PWR_FLAG));
+  
+  if ((PWR->CSR & PWR_FLAG) != (uint32_t)RESET)
+  {
+    bitstatus = SET;
+  }
+  else
+  {
+    bitstatus = RESET;
+  }
+  /* Return the flag status */
+  return bitstatus;
+}
+
+/**
+  * @brief  Clears the PWR's pending flags.
+  * @param  PWR_FLAG: specifies the flag to clear.
+  *   This parameter can be one of the following values:
+  *     @arg PWR_FLAG_WU: Wake Up flag
+  *     @arg PWR_FLAG_SB: StandBy flag
+  * @retval None
+  */
+void PWR_ClearFlag(uint32_t PWR_FLAG)
+{
+  /* Check the parameters */
+  assert_param(IS_PWR_CLEAR_FLAG(PWR_FLAG));
+         
+  PWR->CR |=  PWR_FLAG << 2;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/STM32_4路称重_Git提交精简工程/src/STM32F10x_FWLib/src/stm32f10x_rcc.c b/STM32_4路称重_Git提交精简工程/src/STM32F10x_FWLib/src/stm32f10x_rcc.c
new file mode 100755
index 0000000..4b2ec1f
--- /dev/null
+++ b/STM32_4路称重_Git提交精简工程/src/STM32F10x_FWLib/src/stm32f10x_rcc.c
@@ -0,0 +1,1470 @@
+/**
+  ******************************************************************************
+  * @file    stm32f10x_rcc.c
+  * @author  MCD Application Team
+  * @version V3.5.0
+  * @date    11-March-2011
+  * @brief   This file provides all the RCC firmware functions.
+  ******************************************************************************
+  * @attention
+  *
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+  *
+  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x_rcc.h"
+
+/** @addtogroup STM32F10x_StdPeriph_Driver
+  * @{
+  */
+
+/** @defgroup RCC 
+  * @brief RCC driver modules
+  * @{
+  */ 
+
+/** @defgroup RCC_Private_TypesDefinitions
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup RCC_Private_Defines
+  * @{
+  */
+
+/* ------------ RCC registers bit address in the alias region ----------- */
+#define RCC_OFFSET                (RCC_BASE - PERIPH_BASE)
+
+/* --- CR Register ---*/
+
+/* Alias word address of HSION bit */
+#define CR_OFFSET                 (RCC_OFFSET + 0x00)
+#define HSION_BitNumber           0x00
+#define CR_HSION_BB               (PERIPH_BB_BASE + (CR_OFFSET * 32) + (HSION_BitNumber * 4))
+
+/* Alias word address of PLLON bit */
+#define PLLON_BitNumber           0x18
+#define CR_PLLON_BB               (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PLLON_BitNumber * 4))
+
+#ifdef STM32F10X_CL
+ /* Alias word address of PLL2ON bit */
+ #define PLL2ON_BitNumber          0x1A
+ #define CR_PLL2ON_BB              (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PLL2ON_BitNumber * 4))
+
+ /* Alias word address of PLL3ON bit */
+ #define PLL3ON_BitNumber          0x1C
+ #define CR_PLL3ON_BB              (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PLL3ON_BitNumber * 4))
+#endif /* STM32F10X_CL */ 
+
+/* Alias word address of CSSON bit */
+#define CSSON_BitNumber           0x13
+#define CR_CSSON_BB               (PERIPH_BB_BASE + (CR_OFFSET * 32) + (CSSON_BitNumber * 4))
+
+/* --- CFGR Register ---*/
+
+/* Alias word address of USBPRE bit */
+#define CFGR_OFFSET               (RCC_OFFSET + 0x04)
+
+#ifndef STM32F10X_CL
+ #define USBPRE_BitNumber          0x16
+ #define CFGR_USBPRE_BB            (PERIPH_BB_BASE + (CFGR_OFFSET * 32) + (USBPRE_BitNumber * 4))
+#else
+ #define OTGFSPRE_BitNumber        0x16
+ #define CFGR_OTGFSPRE_BB          (PERIPH_BB_BASE + (CFGR_OFFSET * 32) + (OTGFSPRE_BitNumber * 4))
+#endif /* STM32F10X_CL */ 
+
+/* --- BDCR Register ---*/
+
+/* Alias word address of RTCEN bit */
+#define BDCR_OFFSET               (RCC_OFFSET + 0x20)
+#define RTCEN_BitNumber           0x0F
+#define BDCR_RTCEN_BB             (PERIPH_BB_BASE + (BDCR_OFFSET * 32) + (RTCEN_BitNumber * 4))
+
+/* Alias word address of BDRST bit */
+#define BDRST_BitNumber           0x10
+#define BDCR_BDRST_BB             (PERIPH_BB_BASE + (BDCR_OFFSET * 32) + (BDRST_BitNumber * 4))
+
+/* --- CSR Register ---*/
+
+/* Alias word address of LSION bit */
+#define CSR_OFFSET                (RCC_OFFSET + 0x24)
+#define LSION_BitNumber           0x00
+#define CSR_LSION_BB              (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (LSION_BitNumber * 4))
+
+#ifdef STM32F10X_CL
+/* --- CFGR2 Register ---*/
+
+ /* Alias word address of I2S2SRC bit */
+ #define CFGR2_OFFSET              (RCC_OFFSET + 0x2C)
+ #define I2S2SRC_BitNumber         0x11
+ #define CFGR2_I2S2SRC_BB          (PERIPH_BB_BASE + (CFGR2_OFFSET * 32) + (I2S2SRC_BitNumber * 4))
+
+ /* Alias word address of I2S3SRC bit */
+ #define I2S3SRC_BitNumber         0x12
+ #define CFGR2_I2S3SRC_BB          (PERIPH_BB_BASE + (CFGR2_OFFSET * 32) + (I2S3SRC_BitNumber * 4))
+#endif /* STM32F10X_CL */
+
+/* ---------------------- RCC registers bit mask ------------------------ */
+
+/* CR register bit mask */
+#define CR_HSEBYP_Reset           ((uint32_t)0xFFFBFFFF)
+#define CR_HSEBYP_Set             ((uint32_t)0x00040000)
+#define CR_HSEON_Reset            ((uint32_t)0xFFFEFFFF)
+#define CR_HSEON_Set              ((uint32_t)0x00010000)
+#define CR_HSITRIM_Mask           ((uint32_t)0xFFFFFF07)
+
+/* CFGR register bit mask */
+#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) || defined (STM32F10X_CL) 
+ #define CFGR_PLL_Mask            ((uint32_t)0xFFC2FFFF)
+#else
+ #define CFGR_PLL_Mask            ((uint32_t)0xFFC0FFFF)
+#endif /* STM32F10X_CL */ 
+
+#define CFGR_PLLMull_Mask         ((uint32_t)0x003C0000)
+#define CFGR_PLLSRC_Mask          ((uint32_t)0x00010000)
+#define CFGR_PLLXTPRE_Mask        ((uint32_t)0x00020000)
+#define CFGR_SWS_Mask             ((uint32_t)0x0000000C)
+#define CFGR_SW_Mask              ((uint32_t)0xFFFFFFFC)
+#define CFGR_HPRE_Reset_Mask      ((uint32_t)0xFFFFFF0F)
+#define CFGR_HPRE_Set_Mask        ((uint32_t)0x000000F0)
+#define CFGR_PPRE1_Reset_Mask     ((uint32_t)0xFFFFF8FF)
+#define CFGR_PPRE1_Set_Mask       ((uint32_t)0x00000700)
+#define CFGR_PPRE2_Reset_Mask     ((uint32_t)0xFFFFC7FF)
+#define CFGR_PPRE2_Set_Mask       ((uint32_t)0x00003800)
+#define CFGR_ADCPRE_Reset_Mask    ((uint32_t)0xFFFF3FFF)
+#define CFGR_ADCPRE_Set_Mask      ((uint32_t)0x0000C000)
+
+/* CSR register bit mask */
+#define CSR_RMVF_Set              ((uint32_t)0x01000000)
+
+#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) || defined (STM32F10X_CL) 
+/* CFGR2 register bit mask */
+ #define CFGR2_PREDIV1SRC         ((uint32_t)0x00010000)
+ #define CFGR2_PREDIV1            ((uint32_t)0x0000000F)
+#endif
+#ifdef STM32F10X_CL
+ #define CFGR2_PREDIV2            ((uint32_t)0x000000F0)
+ #define CFGR2_PLL2MUL            ((uint32_t)0x00000F00)
+ #define CFGR2_PLL3MUL            ((uint32_t)0x0000F000)
+#endif /* STM32F10X_CL */ 
+
+/* RCC Flag Mask */
+#define FLAG_Mask                 ((uint8_t)0x1F)
+
+/* CIR register byte 2 (Bits[15:8]) base address */
+#define CIR_BYTE2_ADDRESS         ((uint32_t)0x40021009)
+
+/* CIR register byte 3 (Bits[23:16]) base address */
+#define CIR_BYTE3_ADDRESS         ((uint32_t)0x4002100A)
+
+/* CFGR register byte 4 (Bits[31:24]) base address */
+#define CFGR_BYTE4_ADDRESS        ((uint32_t)0x40021007)
+
+/* BDCR register base address */
+#define BDCR_ADDRESS              (PERIPH_BASE + BDCR_OFFSET)
+
+/**
+  * @}
+  */ 
+
+/** @defgroup RCC_Private_Macros
+  * @{
+  */ 
+
+/**
+  * @}
+  */ 
+
+/** @defgroup RCC_Private_Variables
+  * @{
+  */ 
+
+static __I uint8_t APBAHBPrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, 8, 9};
+static __I uint8_t ADCPrescTable[4] = {2, 4, 6, 8};
+
+/**
+  * @}
+  */
+
+/** @defgroup RCC_Private_FunctionPrototypes
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup RCC_Private_Functions
+  * @{
+  */
+
+/**
+  * @brief  Resets the RCC clock configuration to the default reset state.
+  * @param  None
+  * @retval None
+  */
+void RCC_DeInit(void)
+{
+  /* Set HSION bit */
+  RCC->CR |= (uint32_t)0x00000001;
+
+  /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */
+#ifndef STM32F10X_CL
+  RCC->CFGR &= (uint32_t)0xF8FF0000;
+#else
+  RCC->CFGR &= (uint32_t)0xF0FF0000;
+#endif /* STM32F10X_CL */   
+  
+  /* Reset HSEON, CSSON and PLLON bits */
+  RCC->CR &= (uint32_t)0xFEF6FFFF;
+
+  /* Reset HSEBYP bit */
+  RCC->CR &= (uint32_t)0xFFFBFFFF;
+
+  /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */
+  RCC->CFGR &= (uint32_t)0xFF80FFFF;
+
+#ifdef STM32F10X_CL
+  /* Reset PLL2ON and PLL3ON bits */
+  RCC->CR &= (uint32_t)0xEBFFFFFF;
+
+  /* Disable all interrupts and clear pending bits  */
+  RCC->CIR = 0x00FF0000;
+
+  /* Reset CFGR2 register */
+  RCC->CFGR2 = 0x00000000;
+#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
+  /* Disable all interrupts and clear pending bits  */
+  RCC->CIR = 0x009F0000;
+
+  /* Reset CFGR2 register */
+  RCC->CFGR2 = 0x00000000;      
+#else
+  /* Disable all interrupts and clear pending bits  */
+  RCC->CIR = 0x009F0000;
+#endif /* STM32F10X_CL */
+
+}
+
+/**
+  * @brief  Configures the External High Speed oscillator (HSE).
+  * @note   HSE can not be stopped if it is used directly or through the PLL as system clock.
+  * @param  RCC_HSE: specifies the new state of the HSE.
+  *   This parameter can be one of the following values:
+  *     @arg RCC_HSE_OFF: HSE oscillator OFF
+  *     @arg RCC_HSE_ON: HSE oscillator ON
+  *     @arg RCC_HSE_Bypass: HSE oscillator bypassed with external clock
+  * @retval None
+  */
+void RCC_HSEConfig(uint32_t RCC_HSE)
+{
+  /* Check the parameters */
+  assert_param(IS_RCC_HSE(RCC_HSE));
+  /* Reset HSEON and HSEBYP bits before configuring the HSE ------------------*/
+  /* Reset HSEON bit */
+  RCC->CR &= CR_HSEON_Reset;
+  /* Reset HSEBYP bit */
+  RCC->CR &= CR_HSEBYP_Reset;
+  /* Configure HSE (RCC_HSE_OFF is already covered by the code section above) */
+  switch(RCC_HSE)
+  {
+    case RCC_HSE_ON:
+      /* Set HSEON bit */
+      RCC->CR |= CR_HSEON_Set;
+      break;
+      
+    case RCC_HSE_Bypass:
+      /* Set HSEBYP and HSEON bits */
+      RCC->CR |= CR_HSEBYP_Set | CR_HSEON_Set;
+      break;
+      
+    default:
+      break;
+  }
+}
+
+/**
+  * @brief  Waits for HSE start-up.
+  * @param  None
+  * @retval An ErrorStatus enumuration value:
+  * - SUCCESS: HSE oscillator is stable and ready to use
+  * - ERROR: HSE oscillator not yet ready
+  */
+ErrorStatus RCC_WaitForHSEStartUp(void)
+{
+  __IO uint32_t StartUpCounter = 0;
+  ErrorStatus status = ERROR;
+  FlagStatus HSEStatus = RESET;
+  
+  /* Wait till HSE is ready and if Time out is reached exit */
+  do
+  {
+    HSEStatus = RCC_GetFlagStatus(RCC_FLAG_HSERDY);
+    StartUpCounter++;  
+  } while((StartUpCounter != HSE_STARTUP_TIMEOUT) && (HSEStatus == RESET));
+  
+  if (RCC_GetFlagStatus(RCC_FLAG_HSERDY) != RESET)
+  {
+    status = SUCCESS;
+  }
+  else
+  {
+    status = ERROR;
+  }  
+  return (status);
+}
+
+/**
+  * @brief  Adjusts the Internal High Speed oscillator (HSI) calibration value.
+  * @param  HSICalibrationValue: specifies the calibration trimming value.
+  *   This parameter must be a number between 0 and 0x1F.
+  * @retval None
+  */
+void RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue)
+{
+  uint32_t tmpreg = 0;
+  /* Check the parameters */
+  assert_param(IS_RCC_CALIBRATION_VALUE(HSICalibrationValue));
+  tmpreg = RCC->CR;
+  /* Clear HSITRIM[4:0] bits */
+  tmpreg &= CR_HSITRIM_Mask;
+  /* Set the HSITRIM[4:0] bits according to HSICalibrationValue value */
+  tmpreg |= (uint32_t)HSICalibrationValue << 3;
+  /* Store the new value */
+  RCC->CR = tmpreg;
+}
+
+/**
+  * @brief  Enables or disables the Internal High Speed oscillator (HSI).
+  * @note   HSI can not be stopped if it is used directly or through the PLL as system clock.
+  * @param  NewState: new state of the HSI. This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void RCC_HSICmd(FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  *(__IO uint32_t *) CR_HSION_BB = (uint32_t)NewState;
+}
+
+/**
+  * @brief  Configures the PLL clock source and multiplication factor.
+  * @note   This function must be used only when the PLL is disabled.
+  * @param  RCC_PLLSource: specifies the PLL entry clock source.
+  *   For @b STM32_Connectivity_line_devices or @b STM32_Value_line_devices, 
+  *   this parameter can be one of the following values:
+  *     @arg RCC_PLLSource_HSI_Div2: HSI oscillator clock divided by 2 selected as PLL clock entry
+  *     @arg RCC_PLLSource_PREDIV1: PREDIV1 clock selected as PLL clock entry
+  *   For @b other_STM32_devices, this parameter can be one of the following values:
+  *     @arg RCC_PLLSource_HSI_Div2: HSI oscillator clock divided by 2 selected as PLL clock entry
+  *     @arg RCC_PLLSource_HSE_Div1: HSE oscillator clock selected as PLL clock entry
+  *     @arg RCC_PLLSource_HSE_Div2: HSE oscillator clock divided by 2 selected as PLL clock entry 
+  * @param  RCC_PLLMul: specifies the PLL multiplication factor.
+  *   For @b STM32_Connectivity_line_devices, this parameter can be RCC_PLLMul_x where x:{[4,9], 6_5}
+  *   For @b other_STM32_devices, this parameter can be RCC_PLLMul_x where x:[2,16]  
+  * @retval None
+  */
+void RCC_PLLConfig(uint32_t RCC_PLLSource, uint32_t RCC_PLLMul)
+{
+  uint32_t tmpreg = 0;
+
+  /* Check the parameters */
+  assert_param(IS_RCC_PLL_SOURCE(RCC_PLLSource));
+  assert_param(IS_RCC_PLL_MUL(RCC_PLLMul));
+
+  tmpreg = RCC->CFGR;
+  /* Clear PLLSRC, PLLXTPRE and PLLMUL[3:0] bits */
+  tmpreg &= CFGR_PLL_Mask;
+  /* Set the PLL configuration bits */
+  tmpreg |= RCC_PLLSource | RCC_PLLMul;
+  /* Store the new value */
+  RCC->CFGR = tmpreg;
+}
+
+/**
+  * @brief  Enables or disables the PLL.
+  * @note   The PLL can not be disabled if it is used as system clock.
+  * @param  NewState: new state of the PLL. This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void RCC_PLLCmd(FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  *(__IO uint32_t *) CR_PLLON_BB = (uint32_t)NewState;
+}
+
+#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) || defined (STM32F10X_CL)
+/**
+  * @brief  Configures the PREDIV1 division factor.
+  * @note 
+  *   - This function must be used only when the PLL is disabled.
+  *   - This function applies only to STM32 Connectivity line and Value line 
+  *     devices.
+  * @param  RCC_PREDIV1_Source: specifies the PREDIV1 clock source.
+  *   This parameter can be one of the following values:
+  *     @arg RCC_PREDIV1_Source_HSE: HSE selected as PREDIV1 clock
+  *     @arg RCC_PREDIV1_Source_PLL2: PLL2 selected as PREDIV1 clock
+  * @note 
+  *   For @b STM32_Value_line_devices this parameter is always RCC_PREDIV1_Source_HSE  
+  * @param  RCC_PREDIV1_Div: specifies the PREDIV1 clock division factor.
+  *   This parameter can be RCC_PREDIV1_Divx where x:[1,16]
+  * @retval None
+  */
+void RCC_PREDIV1Config(uint32_t RCC_PREDIV1_Source, uint32_t RCC_PREDIV1_Div)
+{
+  uint32_t tmpreg = 0;
+  
+  /* Check the parameters */
+  assert_param(IS_RCC_PREDIV1_SOURCE(RCC_PREDIV1_Source));
+  assert_param(IS_RCC_PREDIV1(RCC_PREDIV1_Div));
+
+  tmpreg = RCC->CFGR2;
+  /* Clear PREDIV1[3:0] and PREDIV1SRC bits */
+  tmpreg &= ~(CFGR2_PREDIV1 | CFGR2_PREDIV1SRC);
+  /* Set the PREDIV1 clock source and division factor */
+  tmpreg |= RCC_PREDIV1_Source | RCC_PREDIV1_Div ;
+  /* Store the new value */
+  RCC->CFGR2 = tmpreg;
+}
+#endif
+
+#ifdef STM32F10X_CL
+/**
+  * @brief  Configures the PREDIV2 division factor.
+  * @note 
+  *   - This function must be used only when both PLL2 and PLL3 are disabled.
+  *   - This function applies only to STM32 Connectivity line devices.
+  * @param  RCC_PREDIV2_Div: specifies the PREDIV2 clock division factor.
+  *   This parameter can be RCC_PREDIV2_Divx where x:[1,16]
+  * @retval None
+  */
+void RCC_PREDIV2Config(uint32_t RCC_PREDIV2_Div)
+{
+  uint32_t tmpreg = 0;
+
+  /* Check the parameters */
+  assert_param(IS_RCC_PREDIV2(RCC_PREDIV2_Div));
+
+  tmpreg = RCC->CFGR2;
+  /* Clear PREDIV2[3:0] bits */
+  tmpreg &= ~CFGR2_PREDIV2;
+  /* Set the PREDIV2 division factor */
+  tmpreg |= RCC_PREDIV2_Div;
+  /* Store the new value */
+  RCC->CFGR2 = tmpreg;
+}
+
+/**
+  * @brief  Configures the PLL2 multiplication factor.
+  * @note
+  *   - This function must be used only when the PLL2 is disabled.
+  *   - This function applies only to STM32 Connectivity line devices.
+  * @param  RCC_PLL2Mul: specifies the PLL2 multiplication factor.
+  *   This parameter can be RCC_PLL2Mul_x where x:{[8,14], 16, 20}
+  * @retval None
+  */
+void RCC_PLL2Config(uint32_t RCC_PLL2Mul)
+{
+  uint32_t tmpreg = 0;
+
+  /* Check the parameters */
+  assert_param(IS_RCC_PLL2_MUL(RCC_PLL2Mul));
+
+  tmpreg = RCC->CFGR2;
+  /* Clear PLL2Mul[3:0] bits */
+  tmpreg &= ~CFGR2_PLL2MUL;
+  /* Set the PLL2 configuration bits */
+  tmpreg |= RCC_PLL2Mul;
+  /* Store the new value */
+  RCC->CFGR2 = tmpreg;
+}
+
+
+/**
+  * @brief  Enables or disables the PLL2.
+  * @note 
+  *   - The PLL2 can not be disabled if it is used indirectly as system clock
+  *     (i.e. it is used as PLL clock entry that is used as System clock).
+  *   - This function applies only to STM32 Connectivity line devices.
+  * @param  NewState: new state of the PLL2. This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void RCC_PLL2Cmd(FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  *(__IO uint32_t *) CR_PLL2ON_BB = (uint32_t)NewState;
+}
+
+
+/**
+  * @brief  Configures the PLL3 multiplication factor.
+  * @note 
+  *   - This function must be used only when the PLL3 is disabled.
+  *   - This function applies only to STM32 Connectivity line devices.
+  * @param  RCC_PLL3Mul: specifies the PLL3 multiplication factor.
+  *   This parameter can be RCC_PLL3Mul_x where x:{[8,14], 16, 20}
+  * @retval None
+  */
+void RCC_PLL3Config(uint32_t RCC_PLL3Mul)
+{
+  uint32_t tmpreg = 0;
+
+  /* Check the parameters */
+  assert_param(IS_RCC_PLL3_MUL(RCC_PLL3Mul));
+
+  tmpreg = RCC->CFGR2;
+  /* Clear PLL3Mul[3:0] bits */
+  tmpreg &= ~CFGR2_PLL3MUL;
+  /* Set the PLL3 configuration bits */
+  tmpreg |= RCC_PLL3Mul;
+  /* Store the new value */
+  RCC->CFGR2 = tmpreg;
+}
+
+
+/**
+  * @brief  Enables or disables the PLL3.
+  * @note   This function applies only to STM32 Connectivity line devices.
+  * @param  NewState: new state of the PLL3. This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void RCC_PLL3Cmd(FunctionalState NewState)
+{
+  /* Check the parameters */
+
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  *(__IO uint32_t *) CR_PLL3ON_BB = (uint32_t)NewState;
+}
+#endif /* STM32F10X_CL */
+
+/**
+  * @brief  Configures the system clock (SYSCLK).
+  * @param  RCC_SYSCLKSource: specifies the clock source used as system clock.
+  *   This parameter can be one of the following values:
+  *     @arg RCC_SYSCLKSource_HSI: HSI selected as system clock
+  *     @arg RCC_SYSCLKSource_HSE: HSE selected as system clock
+  *     @arg RCC_SYSCLKSource_PLLCLK: PLL selected as system clock
+  * @retval None
+  */
+void RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource)
+{
+  uint32_t tmpreg = 0;
+  /* Check the parameters */
+  assert_param(IS_RCC_SYSCLK_SOURCE(RCC_SYSCLKSource));
+  tmpreg = RCC->CFGR;
+  /* Clear SW[1:0] bits */
+  tmpreg &= CFGR_SW_Mask;
+  /* Set SW[1:0] bits according to RCC_SYSCLKSource value */
+  tmpreg |= RCC_SYSCLKSource;
+  /* Store the new value */
+  RCC->CFGR = tmpreg;
+}
+
+/**
+  * @brief  Returns the clock source used as system clock.
+  * @param  None
+  * @retval The clock source used as system clock. The returned value can
+  *   be one of the following:
+  *     - 0x00: HSI used as system clock
+  *     - 0x04: HSE used as system clock
+  *     - 0x08: PLL used as system clock
+  */
+uint8_t RCC_GetSYSCLKSource(void)
+{
+  return ((uint8_t)(RCC->CFGR & CFGR_SWS_Mask));
+}
+
+/**
+  * @brief  Configures the AHB clock (HCLK).
+  * @param  RCC_SYSCLK: defines the AHB clock divider. This clock is derived from 
+  *   the system clock (SYSCLK).
+  *   This parameter can be one of the following values:
+  *     @arg RCC_SYSCLK_Div1: AHB clock = SYSCLK
+  *     @arg RCC_SYSCLK_Div2: AHB clock = SYSCLK/2
+  *     @arg RCC_SYSCLK_Div4: AHB clock = SYSCLK/4
+  *     @arg RCC_SYSCLK_Div8: AHB clock = SYSCLK/8
+  *     @arg RCC_SYSCLK_Div16: AHB clock = SYSCLK/16
+  *     @arg RCC_SYSCLK_Div64: AHB clock = SYSCLK/64
+  *     @arg RCC_SYSCLK_Div128: AHB clock = SYSCLK/128
+  *     @arg RCC_SYSCLK_Div256: AHB clock = SYSCLK/256
+  *     @arg RCC_SYSCLK_Div512: AHB clock = SYSCLK/512
+  * @retval None
+  */
+void RCC_HCLKConfig(uint32_t RCC_SYSCLK)
+{
+  uint32_t tmpreg = 0;
+  /* Check the parameters */
+  assert_param(IS_RCC_HCLK(RCC_SYSCLK));
+  tmpreg = RCC->CFGR;
+  /* Clear HPRE[3:0] bits */
+  tmpreg &= CFGR_HPRE_Reset_Mask;
+  /* Set HPRE[3:0] bits according to RCC_SYSCLK value */
+  tmpreg |= RCC_SYSCLK;
+  /* Store the new value */
+  RCC->CFGR = tmpreg;
+}
+
+/**
+  * @brief  Configures the Low Speed APB clock (PCLK1).
+  * @param  RCC_HCLK: defines the APB1 clock divider. This clock is derived from 
+  *   the AHB clock (HCLK).
+  *   This parameter can be one of the following values:
+  *     @arg RCC_HCLK_Div1: APB1 clock = HCLK
+  *     @arg RCC_HCLK_Div2: APB1 clock = HCLK/2
+  *     @arg RCC_HCLK_Div4: APB1 clock = HCLK/4
+  *     @arg RCC_HCLK_Div8: APB1 clock = HCLK/8
+  *     @arg RCC_HCLK_Div16: APB1 clock = HCLK/16
+  * @retval None
+  */
+void RCC_PCLK1Config(uint32_t RCC_HCLK)
+{
+  uint32_t tmpreg = 0;
+  /* Check the parameters */
+  assert_param(IS_RCC_PCLK(RCC_HCLK));
+  tmpreg = RCC->CFGR;
+  /* Clear PPRE1[2:0] bits */
+  tmpreg &= CFGR_PPRE1_Reset_Mask;
+  /* Set PPRE1[2:0] bits according to RCC_HCLK value */
+  tmpreg |= RCC_HCLK;
+  /* Store the new value */
+  RCC->CFGR = tmpreg;
+}
+
+/**
+  * @brief  Configures the High Speed APB clock (PCLK2).
+  * @param  RCC_HCLK: defines the APB2 clock divider. This clock is derived from 
+  *   the AHB clock (HCLK).
+  *   This parameter can be one of the following values:
+  *     @arg RCC_HCLK_Div1: APB2 clock = HCLK
+  *     @arg RCC_HCLK_Div2: APB2 clock = HCLK/2
+  *     @arg RCC_HCLK_Div4: APB2 clock = HCLK/4
+  *     @arg RCC_HCLK_Div8: APB2 clock = HCLK/8
+  *     @arg RCC_HCLK_Div16: APB2 clock = HCLK/16
+  * @retval None
+  */
+void RCC_PCLK2Config(uint32_t RCC_HCLK)
+{
+  uint32_t tmpreg = 0;
+  /* Check the parameters */
+  assert_param(IS_RCC_PCLK(RCC_HCLK));
+  tmpreg = RCC->CFGR;
+  /* Clear PPRE2[2:0] bits */
+  tmpreg &= CFGR_PPRE2_Reset_Mask;
+  /* Set PPRE2[2:0] bits according to RCC_HCLK value */
+  tmpreg |= RCC_HCLK << 3;
+  /* Store the new value */
+  RCC->CFGR = tmpreg;
+}
+
+/**
+  * @brief  Enables or disables the specified RCC interrupts.
+  * @param  RCC_IT: specifies the RCC interrupt sources to be enabled or disabled.
+  * 
+  *   For @b STM32_Connectivity_line_devices, this parameter can be any combination
+  *   of the following values        
+  *     @arg RCC_IT_LSIRDY: LSI ready interrupt
+  *     @arg RCC_IT_LSERDY: LSE ready interrupt
+  *     @arg RCC_IT_HSIRDY: HSI ready interrupt
+  *     @arg RCC_IT_HSERDY: HSE ready interrupt
+  *     @arg RCC_IT_PLLRDY: PLL ready interrupt
+  *     @arg RCC_IT_PLL2RDY: PLL2 ready interrupt
+  *     @arg RCC_IT_PLL3RDY: PLL3 ready interrupt
+  * 
+  *   For @b other_STM32_devices, this parameter can be any combination of the 
+  *   following values        
+  *     @arg RCC_IT_LSIRDY: LSI ready interrupt
+  *     @arg RCC_IT_LSERDY: LSE ready interrupt
+  *     @arg RCC_IT_HSIRDY: HSI ready interrupt
+  *     @arg RCC_IT_HSERDY: HSE ready interrupt
+  *     @arg RCC_IT_PLLRDY: PLL ready interrupt
+  *       
+  * @param  NewState: new state of the specified RCC interrupts.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void RCC_ITConfig(uint8_t RCC_IT, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_RCC_IT(RCC_IT));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  if (NewState != DISABLE)
+  {
+    /* Perform Byte access to RCC_CIR bits to enable the selected interrupts */
+    *(__IO uint8_t *) CIR_BYTE2_ADDRESS |= RCC_IT;
+  }
+  else
+  {
+    /* Perform Byte access to RCC_CIR bits to disable the selected interrupts */
+    *(__IO uint8_t *) CIR_BYTE2_ADDRESS &= (uint8_t)~RCC_IT;
+  }
+}
+
+#ifndef STM32F10X_CL
+/**
+  * @brief  Configures the USB clock (USBCLK).
+  * @param  RCC_USBCLKSource: specifies the USB clock source. This clock is 
+  *   derived from the PLL output.
+  *   This parameter can be one of the following values:
+  *     @arg RCC_USBCLKSource_PLLCLK_1Div5: PLL clock divided by 1,5 selected as USB 
+  *                                     clock source
+  *     @arg RCC_USBCLKSource_PLLCLK_Div1: PLL clock selected as USB clock source
+  * @retval None
+  */
+void RCC_USBCLKConfig(uint32_t RCC_USBCLKSource)
+{
+  /* Check the parameters */
+  assert_param(IS_RCC_USBCLK_SOURCE(RCC_USBCLKSource));
+
+  *(__IO uint32_t *) CFGR_USBPRE_BB = RCC_USBCLKSource;
+}
+#else
+/**
+  * @brief  Configures the USB OTG FS clock (OTGFSCLK).
+  *   This function applies only to STM32 Connectivity line devices.
+  * @param  RCC_OTGFSCLKSource: specifies the USB OTG FS clock source.
+  *   This clock is derived from the PLL output.
+  *   This parameter can be one of the following values:
+  *     @arg  RCC_OTGFSCLKSource_PLLVCO_Div3: PLL VCO clock divided by 2 selected as USB OTG FS clock source
+  *     @arg  RCC_OTGFSCLKSource_PLLVCO_Div2: PLL VCO clock divided by 2 selected as USB OTG FS clock source
+  * @retval None
+  */
+void RCC_OTGFSCLKConfig(uint32_t RCC_OTGFSCLKSource)
+{
+  /* Check the parameters */
+  assert_param(IS_RCC_OTGFSCLK_SOURCE(RCC_OTGFSCLKSource));
+
+  *(__IO uint32_t *) CFGR_OTGFSPRE_BB = RCC_OTGFSCLKSource;
+}
+#endif /* STM32F10X_CL */ 
+
+/**
+  * @brief  Configures the ADC clock (ADCCLK).
+  * @param  RCC_PCLK2: defines the ADC clock divider. This clock is derived from 
+  *   the APB2 clock (PCLK2).
+  *   This parameter can be one of the following values:
+  *     @arg RCC_PCLK2_Div2: ADC clock = PCLK2/2
+  *     @arg RCC_PCLK2_Div4: ADC clock = PCLK2/4
+  *     @arg RCC_PCLK2_Div6: ADC clock = PCLK2/6
+  *     @arg RCC_PCLK2_Div8: ADC clock = PCLK2/8
+  * @retval None
+  */
+void RCC_ADCCLKConfig(uint32_t RCC_PCLK2)
+{
+  uint32_t tmpreg = 0;
+  /* Check the parameters */
+  assert_param(IS_RCC_ADCCLK(RCC_PCLK2));
+  tmpreg = RCC->CFGR;
+  /* Clear ADCPRE[1:0] bits */
+  tmpreg &= CFGR_ADCPRE_Reset_Mask;
+  /* Set ADCPRE[1:0] bits according to RCC_PCLK2 value */
+  tmpreg |= RCC_PCLK2;
+  /* Store the new value */
+  RCC->CFGR = tmpreg;
+}
+
+#ifdef STM32F10X_CL
+/**
+  * @brief  Configures the I2S2 clock source(I2S2CLK).
+  * @note
+  *   - This function must be called before enabling I2S2 APB clock.
+  *   - This function applies only to STM32 Connectivity line devices.
+  * @param  RCC_I2S2CLKSource: specifies the I2S2 clock source.
+  *   This parameter can be one of the following values:
+  *     @arg RCC_I2S2CLKSource_SYSCLK: system clock selected as I2S2 clock entry
+  *     @arg RCC_I2S2CLKSource_PLL3_VCO: PLL3 VCO clock selected as I2S2 clock entry
+  * @retval None
+  */
+void RCC_I2S2CLKConfig(uint32_t RCC_I2S2CLKSource)
+{
+  /* Check the parameters */
+  assert_param(IS_RCC_I2S2CLK_SOURCE(RCC_I2S2CLKSource));
+
+  *(__IO uint32_t *) CFGR2_I2S2SRC_BB = RCC_I2S2CLKSource;
+}
+
+/**
+  * @brief  Configures the I2S3 clock source(I2S2CLK).
+  * @note
+  *   - This function must be called before enabling I2S3 APB clock.
+  *   - This function applies only to STM32 Connectivity line devices.
+  * @param  RCC_I2S3CLKSource: specifies the I2S3 clock source.
+  *   This parameter can be one of the following values:
+  *     @arg RCC_I2S3CLKSource_SYSCLK: system clock selected as I2S3 clock entry
+  *     @arg RCC_I2S3CLKSource_PLL3_VCO: PLL3 VCO clock selected as I2S3 clock entry
+  * @retval None
+  */
+void RCC_I2S3CLKConfig(uint32_t RCC_I2S3CLKSource)
+{
+  /* Check the parameters */
+  assert_param(IS_RCC_I2S3CLK_SOURCE(RCC_I2S3CLKSource));
+
+  *(__IO uint32_t *) CFGR2_I2S3SRC_BB = RCC_I2S3CLKSource;
+}
+#endif /* STM32F10X_CL */
+
+/**
+  * @brief  Configures the External Low Speed oscillator (LSE).
+  * @param  RCC_LSE: specifies the new state of the LSE.
+  *   This parameter can be one of the following values:
+  *     @arg RCC_LSE_OFF: LSE oscillator OFF
+  *     @arg RCC_LSE_ON: LSE oscillator ON
+  *     @arg RCC_LSE_Bypass: LSE oscillator bypassed with external clock
+  * @retval None
+  */
+void RCC_LSEConfig(uint8_t RCC_LSE)
+{
+  /* Check the parameters */
+  assert_param(IS_RCC_LSE(RCC_LSE));
+  /* Reset LSEON and LSEBYP bits before configuring the LSE ------------------*/
+  /* Reset LSEON bit */
+  *(__IO uint8_t *) BDCR_ADDRESS = RCC_LSE_OFF;
+  /* Reset LSEBYP bit */
+  *(__IO uint8_t *) BDCR_ADDRESS = RCC_LSE_OFF;
+  /* Configure LSE (RCC_LSE_OFF is already covered by the code section above) */
+  switch(RCC_LSE)
+  {
+    case RCC_LSE_ON:
+      /* Set LSEON bit */
+      *(__IO uint8_t *) BDCR_ADDRESS = RCC_LSE_ON;
+      break;
+      
+    case RCC_LSE_Bypass:
+      /* Set LSEBYP and LSEON bits */
+      *(__IO uint8_t *) BDCR_ADDRESS = RCC_LSE_Bypass | RCC_LSE_ON;
+      break;            
+      
+    default:
+      break;      
+  }
+}
+
+/**
+  * @brief  Enables or disables the Internal Low Speed oscillator (LSI).
+  * @note   LSI can not be disabled if the IWDG is running.
+  * @param  NewState: new state of the LSI. This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void RCC_LSICmd(FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  *(__IO uint32_t *) CSR_LSION_BB = (uint32_t)NewState;
+}
+
+/**
+  * @brief  Configures the RTC clock (RTCCLK).
+  * @note   Once the RTC clock is selected it can't be changed unless the Backup domain is reset.
+  * @param  RCC_RTCCLKSource: specifies the RTC clock source.
+  *   This parameter can be one of the following values:
+  *     @arg RCC_RTCCLKSource_LSE: LSE selected as RTC clock
+  *     @arg RCC_RTCCLKSource_LSI: LSI selected as RTC clock
+  *     @arg RCC_RTCCLKSource_HSE_Div128: HSE clock divided by 128 selected as RTC clock
+  * @retval None
+  */
+void RCC_RTCCLKConfig(uint32_t RCC_RTCCLKSource)
+{
+  /* Check the parameters */
+  assert_param(IS_RCC_RTCCLK_SOURCE(RCC_RTCCLKSource));
+  /* Select the RTC clock source */
+  RCC->BDCR |= RCC_RTCCLKSource;
+}
+
+/**
+  * @brief  Enables or disables the RTC clock.
+  * @note   This function must be used only after the RTC clock was selected using the RCC_RTCCLKConfig function.
+  * @param  NewState: new state of the RTC clock. This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void RCC_RTCCLKCmd(FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  *(__IO uint32_t *) BDCR_RTCEN_BB = (uint32_t)NewState;
+}
+
+/**
+  * @brief  Returns the frequencies of different on chip clocks.
+  * @param  RCC_Clocks: pointer to a RCC_ClocksTypeDef structure which will hold
+  *         the clocks frequencies.
+  * @note   The result of this function could be not correct when using 
+  *         fractional value for HSE crystal.  
+  * @retval None
+  */
+void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks)
+{
+  uint32_t tmp = 0, pllmull = 0, pllsource = 0, presc = 0;
+
+#ifdef  STM32F10X_CL
+  uint32_t prediv1source = 0, prediv1factor = 0, prediv2factor = 0, pll2mull = 0;
+#endif /* STM32F10X_CL */
+
+#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
+  uint32_t prediv1factor = 0;
+#endif
+    
+  /* Get SYSCLK source -------------------------------------------------------*/
+  tmp = RCC->CFGR & CFGR_SWS_Mask;
+  
+  switch (tmp)
+  {
+    case 0x00:  /* HSI used as system clock */
+      RCC_Clocks->SYSCLK_Frequency = HSI_VALUE;
+      break;
+    case 0x04:  /* HSE used as system clock */
+      RCC_Clocks->SYSCLK_Frequency = HSE_VALUE;
+      break;
+    case 0x08:  /* PLL used as system clock */
+
+      /* Get PLL clock source and multiplication factor ----------------------*/
+      pllmull = RCC->CFGR & CFGR_PLLMull_Mask;
+      pllsource = RCC->CFGR & CFGR_PLLSRC_Mask;
+      
+#ifndef STM32F10X_CL      
+      pllmull = ( pllmull >> 18) + 2;
+      
+      if (pllsource == 0x00)
+      {/* HSI oscillator clock divided by 2 selected as PLL clock entry */
+        RCC_Clocks->SYSCLK_Frequency = (HSI_VALUE >> 1) * pllmull;
+      }
+      else
+      {
+ #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
+       prediv1factor = (RCC->CFGR2 & CFGR2_PREDIV1) + 1;
+       /* HSE oscillator clock selected as PREDIV1 clock entry */
+       RCC_Clocks->SYSCLK_Frequency = (HSE_VALUE / prediv1factor) * pllmull; 
+ #else
+        /* HSE selected as PLL clock entry */
+        if ((RCC->CFGR & CFGR_PLLXTPRE_Mask) != (uint32_t)RESET)
+        {/* HSE oscillator clock divided by 2 */
+          RCC_Clocks->SYSCLK_Frequency = (HSE_VALUE >> 1) * pllmull;
+        }
+        else
+        {
+          RCC_Clocks->SYSCLK_Frequency = HSE_VALUE * pllmull;
+        }
+ #endif
+      }
+#else
+      pllmull = pllmull >> 18;
+      
+      if (pllmull != 0x0D)
+      {
+         pllmull += 2;
+      }
+      else
+      { /* PLL multiplication factor = PLL input clock * 6.5 */
+        pllmull = 13 / 2; 
+      }
+            
+      if (pllsource == 0x00)
+      {/* HSI oscillator clock divided by 2 selected as PLL clock entry */
+        RCC_Clocks->SYSCLK_Frequency = (HSI_VALUE >> 1) * pllmull;
+      }
+      else
+      {/* PREDIV1 selected as PLL clock entry */
+        
+        /* Get PREDIV1 clock source and division factor */
+        prediv1source = RCC->CFGR2 & CFGR2_PREDIV1SRC;
+        prediv1factor = (RCC->CFGR2 & CFGR2_PREDIV1) + 1;
+        
+        if (prediv1source == 0)
+        { /* HSE oscillator clock selected as PREDIV1 clock entry */
+          RCC_Clocks->SYSCLK_Frequency = (HSE_VALUE / prediv1factor) * pllmull;          
+        }
+        else
+        {/* PLL2 clock selected as PREDIV1 clock entry */
+          
+          /* Get PREDIV2 division factor and PLL2 multiplication factor */
+          prediv2factor = ((RCC->CFGR2 & CFGR2_PREDIV2) >> 4) + 1;
+          pll2mull = ((RCC->CFGR2 & CFGR2_PLL2MUL) >> 8 ) + 2; 
+          RCC_Clocks->SYSCLK_Frequency = (((HSE_VALUE / prediv2factor) * pll2mull) / prediv1factor) * pllmull;                         
+        }
+      }
+#endif /* STM32F10X_CL */ 
+      break;
+
+    default:
+      RCC_Clocks->SYSCLK_Frequency = HSI_VALUE;
+      break;
+  }
+
+  /* Compute HCLK, PCLK1, PCLK2 and ADCCLK clocks frequencies ----------------*/
+  /* Get HCLK prescaler */
+  tmp = RCC->CFGR & CFGR_HPRE_Set_Mask;
+  tmp = tmp >> 4;
+  presc = APBAHBPrescTable[tmp];
+  /* HCLK clock frequency */
+  RCC_Clocks->HCLK_Frequency = RCC_Clocks->SYSCLK_Frequency >> presc;
+  /* Get PCLK1 prescaler */
+  tmp = RCC->CFGR & CFGR_PPRE1_Set_Mask;
+  tmp = tmp >> 8;
+  presc = APBAHBPrescTable[tmp];
+  /* PCLK1 clock frequency */
+  RCC_Clocks->PCLK1_Frequency = RCC_Clocks->HCLK_Frequency >> presc;
+  /* Get PCLK2 prescaler */
+  tmp = RCC->CFGR & CFGR_PPRE2_Set_Mask;
+  tmp = tmp >> 11;
+  presc = APBAHBPrescTable[tmp];
+  /* PCLK2 clock frequency */
+  RCC_Clocks->PCLK2_Frequency = RCC_Clocks->HCLK_Frequency >> presc;
+  /* Get ADCCLK prescaler */
+  tmp = RCC->CFGR & CFGR_ADCPRE_Set_Mask;
+  tmp = tmp >> 14;
+  presc = ADCPrescTable[tmp];
+  /* ADCCLK clock frequency */
+  RCC_Clocks->ADCCLK_Frequency = RCC_Clocks->PCLK2_Frequency / presc;
+}
+
+/**
+  * @brief  Enables or disables the AHB peripheral clock.
+  * @param  RCC_AHBPeriph: specifies the AHB peripheral to gates its clock.
+  *   
+  *   For @b STM32_Connectivity_line_devices, this parameter can be any combination
+  *   of the following values:        
+  *     @arg RCC_AHBPeriph_DMA1
+  *     @arg RCC_AHBPeriph_DMA2
+  *     @arg RCC_AHBPeriph_SRAM
+  *     @arg RCC_AHBPeriph_FLITF
+  *     @arg RCC_AHBPeriph_CRC
+  *     @arg RCC_AHBPeriph_OTG_FS    
+  *     @arg RCC_AHBPeriph_ETH_MAC   
+  *     @arg RCC_AHBPeriph_ETH_MAC_Tx
+  *     @arg RCC_AHBPeriph_ETH_MAC_Rx
+  * 
+  *   For @b other_STM32_devices, this parameter can be any combination of the 
+  *   following values:        
+  *     @arg RCC_AHBPeriph_DMA1
+  *     @arg RCC_AHBPeriph_DMA2
+  *     @arg RCC_AHBPeriph_SRAM
+  *     @arg RCC_AHBPeriph_FLITF
+  *     @arg RCC_AHBPeriph_CRC
+  *     @arg RCC_AHBPeriph_FSMC
+  *     @arg RCC_AHBPeriph_SDIO
+  *   
+  * @note SRAM and FLITF clock can be disabled only during sleep mode.
+  * @param  NewState: new state of the specified peripheral clock.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void RCC_AHBPeriphClockCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_RCC_AHB_PERIPH(RCC_AHBPeriph));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    RCC->AHBENR |= RCC_AHBPeriph;
+  }
+  else
+  {
+    RCC->AHBENR &= ~RCC_AHBPeriph;
+  }
+}
+
+/**
+  * @brief  Enables or disables the High Speed APB (APB2) peripheral clock.
+  * @param  RCC_APB2Periph: specifies the APB2 peripheral to gates its clock.
+  *   This parameter can be any combination of the following values:
+  *     @arg RCC_APB2Periph_AFIO, RCC_APB2Periph_GPIOA, RCC_APB2Periph_GPIOB,
+  *          RCC_APB2Periph_GPIOC, RCC_APB2Periph_GPIOD, RCC_APB2Periph_GPIOE,
+  *          RCC_APB2Periph_GPIOF, RCC_APB2Periph_GPIOG, RCC_APB2Periph_ADC1,
+  *          RCC_APB2Periph_ADC2, RCC_APB2Periph_TIM1, RCC_APB2Periph_SPI1,
+  *          RCC_APB2Periph_TIM8, RCC_APB2Periph_USART1, RCC_APB2Periph_ADC3,
+  *          RCC_APB2Periph_TIM15, RCC_APB2Periph_TIM16, RCC_APB2Periph_TIM17,
+  *          RCC_APB2Periph_TIM9, RCC_APB2Periph_TIM10, RCC_APB2Periph_TIM11     
+  * @param  NewState: new state of the specified peripheral clock.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_RCC_APB2_PERIPH(RCC_APB2Periph));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  if (NewState != DISABLE)
+  {
+    RCC->APB2ENR |= RCC_APB2Periph;
+  }
+  else
+  {
+    RCC->APB2ENR &= ~RCC_APB2Periph;
+  }
+}
+
+/**
+  * @brief  Enables or disables the Low Speed APB (APB1) peripheral clock.
+  * @param  RCC_APB1Periph: specifies the APB1 peripheral to gates its clock.
+  *   This parameter can be any combination of the following values:
+  *     @arg RCC_APB1Periph_TIM2, RCC_APB1Periph_TIM3, RCC_APB1Periph_TIM4,
+  *          RCC_APB1Periph_TIM5, RCC_APB1Periph_TIM6, RCC_APB1Periph_TIM7,
+  *          RCC_APB1Periph_WWDG, RCC_APB1Periph_SPI2, RCC_APB1Periph_SPI3,
+  *          RCC_APB1Periph_USART2, RCC_APB1Periph_USART3, RCC_APB1Periph_USART4, 
+  *          RCC_APB1Periph_USART5, RCC_APB1Periph_I2C1, RCC_APB1Periph_I2C2,
+  *          RCC_APB1Periph_USB, RCC_APB1Periph_CAN1, RCC_APB1Periph_BKP,
+  *          RCC_APB1Periph_PWR, RCC_APB1Periph_DAC, RCC_APB1Periph_CEC,
+  *          RCC_APB1Periph_TIM12, RCC_APB1Periph_TIM13, RCC_APB1Periph_TIM14
+  * @param  NewState: new state of the specified peripheral clock.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_RCC_APB1_PERIPH(RCC_APB1Periph));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  if (NewState != DISABLE)
+  {
+    RCC->APB1ENR |= RCC_APB1Periph;
+  }
+  else
+  {
+    RCC->APB1ENR &= ~RCC_APB1Periph;
+  }
+}
+
+#ifdef STM32F10X_CL
+/**
+  * @brief  Forces or releases AHB peripheral reset.
+  * @note   This function applies only to STM32 Connectivity line devices.
+  * @param  RCC_AHBPeriph: specifies the AHB peripheral to reset.
+  *   This parameter can be any combination of the following values:
+  *     @arg RCC_AHBPeriph_OTG_FS 
+  *     @arg RCC_AHBPeriph_ETH_MAC
+  * @param  NewState: new state of the specified peripheral reset.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void RCC_AHBPeriphResetCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_RCC_AHB_PERIPH_RESET(RCC_AHBPeriph));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    RCC->AHBRSTR |= RCC_AHBPeriph;
+  }
+  else
+  {
+    RCC->AHBRSTR &= ~RCC_AHBPeriph;
+  }
+}
+#endif /* STM32F10X_CL */ 
+
+/**
+  * @brief  Forces or releases High Speed APB (APB2) peripheral reset.
+  * @param  RCC_APB2Periph: specifies the APB2 peripheral to reset.
+  *   This parameter can be any combination of the following values:
+  *     @arg RCC_APB2Periph_AFIO, RCC_APB2Periph_GPIOA, RCC_APB2Periph_GPIOB,
+  *          RCC_APB2Periph_GPIOC, RCC_APB2Periph_GPIOD, RCC_APB2Periph_GPIOE,
+  *          RCC_APB2Periph_GPIOF, RCC_APB2Periph_GPIOG, RCC_APB2Periph_ADC1,
+  *          RCC_APB2Periph_ADC2, RCC_APB2Periph_TIM1, RCC_APB2Periph_SPI1,
+  *          RCC_APB2Periph_TIM8, RCC_APB2Periph_USART1, RCC_APB2Periph_ADC3,
+  *          RCC_APB2Periph_TIM15, RCC_APB2Periph_TIM16, RCC_APB2Periph_TIM17,
+  *          RCC_APB2Periph_TIM9, RCC_APB2Periph_TIM10, RCC_APB2Periph_TIM11  
+  * @param  NewState: new state of the specified peripheral reset.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_RCC_APB2_PERIPH(RCC_APB2Periph));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  if (NewState != DISABLE)
+  {
+    RCC->APB2RSTR |= RCC_APB2Periph;
+  }
+  else
+  {
+    RCC->APB2RSTR &= ~RCC_APB2Periph;
+  }
+}
+
+/**
+  * @brief  Forces or releases Low Speed APB (APB1) peripheral reset.
+  * @param  RCC_APB1Periph: specifies the APB1 peripheral to reset.
+  *   This parameter can be any combination of the following values:
+  *     @arg RCC_APB1Periph_TIM2, RCC_APB1Periph_TIM3, RCC_APB1Periph_TIM4,
+  *          RCC_APB1Periph_TIM5, RCC_APB1Periph_TIM6, RCC_APB1Periph_TIM7,
+  *          RCC_APB1Periph_WWDG, RCC_APB1Periph_SPI2, RCC_APB1Periph_SPI3,
+  *          RCC_APB1Periph_USART2, RCC_APB1Periph_USART3, RCC_APB1Periph_USART4, 
+  *          RCC_APB1Periph_USART5, RCC_APB1Periph_I2C1, RCC_APB1Periph_I2C2,
+  *          RCC_APB1Periph_USB, RCC_APB1Periph_CAN1, RCC_APB1Periph_BKP,
+  *          RCC_APB1Periph_PWR, RCC_APB1Periph_DAC, RCC_APB1Periph_CEC,
+  *          RCC_APB1Periph_TIM12, RCC_APB1Periph_TIM13, RCC_APB1Periph_TIM14  
+  * @param  NewState: new state of the specified peripheral clock.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_RCC_APB1_PERIPH(RCC_APB1Periph));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  if (NewState != DISABLE)
+  {
+    RCC->APB1RSTR |= RCC_APB1Periph;
+  }
+  else
+  {
+    RCC->APB1RSTR &= ~RCC_APB1Periph;
+  }
+}
+
+/**
+  * @brief  Forces or releases the Backup domain reset.
+  * @param  NewState: new state of the Backup domain reset.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void RCC_BackupResetCmd(FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  *(__IO uint32_t *) BDCR_BDRST_BB = (uint32_t)NewState;
+}
+
+/**
+  * @brief  Enables or disables the Clock Security System.
+  * @param  NewState: new state of the Clock Security System..
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void RCC_ClockSecuritySystemCmd(FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  *(__IO uint32_t *) CR_CSSON_BB = (uint32_t)NewState;
+}
+
+/**
+  * @brief  Selects the clock source to output on MCO pin.
+  * @param  RCC_MCO: specifies the clock source to output.
+  *   
+  *   For @b STM32_Connectivity_line_devices, this parameter can be one of the
+  *   following values:       
+  *     @arg RCC_MCO_NoClock: No clock selected
+  *     @arg RCC_MCO_SYSCLK: System clock selected
+  *     @arg RCC_MCO_HSI: HSI oscillator clock selected
+  *     @arg RCC_MCO_HSE: HSE oscillator clock selected
+  *     @arg RCC_MCO_PLLCLK_Div2: PLL clock divided by 2 selected
+  *     @arg RCC_MCO_PLL2CLK: PLL2 clock selected                     
+  *     @arg RCC_MCO_PLL3CLK_Div2: PLL3 clock divided by 2 selected   
+  *     @arg RCC_MCO_XT1: External 3-25 MHz oscillator clock selected  
+  *     @arg RCC_MCO_PLL3CLK: PLL3 clock selected 
+  * 
+  *   For  @b other_STM32_devices, this parameter can be one of the following values:        
+  *     @arg RCC_MCO_NoClock: No clock selected
+  *     @arg RCC_MCO_SYSCLK: System clock selected
+  *     @arg RCC_MCO_HSI: HSI oscillator clock selected
+  *     @arg RCC_MCO_HSE: HSE oscillator clock selected
+  *     @arg RCC_MCO_PLLCLK_Div2: PLL clock divided by 2 selected
+  *   
+  * @retval None
+  */
+void RCC_MCOConfig(uint8_t RCC_MCO)
+{
+  /* Check the parameters */
+  assert_param(IS_RCC_MCO(RCC_MCO));
+
+  /* Perform Byte access to MCO bits to select the MCO source */
+  *(__IO uint8_t *) CFGR_BYTE4_ADDRESS = RCC_MCO;
+}
+
+/**
+  * @brief  Checks whether the specified RCC flag is set or not.
+  * @param  RCC_FLAG: specifies the flag to check.
+  *   
+  *   For @b STM32_Connectivity_line_devices, this parameter can be one of the
+  *   following values:
+  *     @arg RCC_FLAG_HSIRDY: HSI oscillator clock ready
+  *     @arg RCC_FLAG_HSERDY: HSE oscillator clock ready
+  *     @arg RCC_FLAG_PLLRDY: PLL clock ready
+  *     @arg RCC_FLAG_PLL2RDY: PLL2 clock ready      
+  *     @arg RCC_FLAG_PLL3RDY: PLL3 clock ready                           
+  *     @arg RCC_FLAG_LSERDY: LSE oscillator clock ready
+  *     @arg RCC_FLAG_LSIRDY: LSI oscillator clock ready
+  *     @arg RCC_FLAG_PINRST: Pin reset
+  *     @arg RCC_FLAG_PORRST: POR/PDR reset
+  *     @arg RCC_FLAG_SFTRST: Software reset
+  *     @arg RCC_FLAG_IWDGRST: Independent Watchdog reset
+  *     @arg RCC_FLAG_WWDGRST: Window Watchdog reset
+  *     @arg RCC_FLAG_LPWRRST: Low Power reset
+  * 
+  *   For @b other_STM32_devices, this parameter can be one of the following values:        
+  *     @arg RCC_FLAG_HSIRDY: HSI oscillator clock ready
+  *     @arg RCC_FLAG_HSERDY: HSE oscillator clock ready
+  *     @arg RCC_FLAG_PLLRDY: PLL clock ready
+  *     @arg RCC_FLAG_LSERDY: LSE oscillator clock ready
+  *     @arg RCC_FLAG_LSIRDY: LSI oscillator clock ready
+  *     @arg RCC_FLAG_PINRST: Pin reset
+  *     @arg RCC_FLAG_PORRST: POR/PDR reset
+  *     @arg RCC_FLAG_SFTRST: Software reset
+  *     @arg RCC_FLAG_IWDGRST: Independent Watchdog reset
+  *     @arg RCC_FLAG_WWDGRST: Window Watchdog reset
+  *     @arg RCC_FLAG_LPWRRST: Low Power reset
+  *   
+  * @retval The new state of RCC_FLAG (SET or RESET).
+  */
+FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG)
+{
+  uint32_t tmp = 0;
+  uint32_t statusreg = 0;
+  FlagStatus bitstatus = RESET;
+  /* Check the parameters */
+  assert_param(IS_RCC_FLAG(RCC_FLAG));
+
+  /* Get the RCC register index */
+  tmp = RCC_FLAG >> 5;
+  if (tmp == 1)               /* The flag to check is in CR register */
+  {
+    statusreg = RCC->CR;
+  }
+  else if (tmp == 2)          /* The flag to check is in BDCR register */
+  {
+    statusreg = RCC->BDCR;
+  }
+  else                       /* The flag to check is in CSR register */
+  {
+    statusreg = RCC->CSR;
+  }
+
+  /* Get the flag position */
+  tmp = RCC_FLAG & FLAG_Mask;
+  if ((statusreg & ((uint32_t)1 << tmp)) != (uint32_t)RESET)
+  {
+    bitstatus = SET;
+  }
+  else
+  {
+    bitstatus = RESET;
+  }
+
+  /* Return the flag status */
+  return bitstatus;
+}
+
+/**
+  * @brief  Clears the RCC reset flags.
+  * @note   The reset flags are: RCC_FLAG_PINRST, RCC_FLAG_PORRST, RCC_FLAG_SFTRST,
+  *   RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST, RCC_FLAG_LPWRRST
+  * @param  None
+  * @retval None
+  */
+void RCC_ClearFlag(void)
+{
+  /* Set RMVF bit to clear the reset flags */
+  RCC->CSR |= CSR_RMVF_Set;
+}
+
+/**
+  * @brief  Checks whether the specified RCC interrupt has occurred or not.
+  * @param  RCC_IT: specifies the RCC interrupt source to check.
+  *   
+  *   For @b STM32_Connectivity_line_devices, this parameter can be one of the
+  *   following values:
+  *     @arg RCC_IT_LSIRDY: LSI ready interrupt
+  *     @arg RCC_IT_LSERDY: LSE ready interrupt
+  *     @arg RCC_IT_HSIRDY: HSI ready interrupt
+  *     @arg RCC_IT_HSERDY: HSE ready interrupt
+  *     @arg RCC_IT_PLLRDY: PLL ready interrupt
+  *     @arg RCC_IT_PLL2RDY: PLL2 ready interrupt 
+  *     @arg RCC_IT_PLL3RDY: PLL3 ready interrupt                      
+  *     @arg RCC_IT_CSS: Clock Security System interrupt
+  * 
+  *   For @b other_STM32_devices, this parameter can be one of the following values:        
+  *     @arg RCC_IT_LSIRDY: LSI ready interrupt
+  *     @arg RCC_IT_LSERDY: LSE ready interrupt
+  *     @arg RCC_IT_HSIRDY: HSI ready interrupt
+  *     @arg RCC_IT_HSERDY: HSE ready interrupt
+  *     @arg RCC_IT_PLLRDY: PLL ready interrupt
+  *     @arg RCC_IT_CSS: Clock Security System interrupt
+  *   
+  * @retval The new state of RCC_IT (SET or RESET).
+  */
+ITStatus RCC_GetITStatus(uint8_t RCC_IT)
+{
+  ITStatus bitstatus = RESET;
+  /* Check the parameters */
+  assert_param(IS_RCC_GET_IT(RCC_IT));
+
+  /* Check the status of the specified RCC interrupt */
+  if ((RCC->CIR & RCC_IT) != (uint32_t)RESET)
+  {
+    bitstatus = SET;
+  }
+  else
+  {
+    bitstatus = RESET;
+  }
+
+  /* Return the RCC_IT status */
+  return  bitstatus;
+}
+
+/**
+  * @brief  Clears the RCC's interrupt pending bits.
+  * @param  RCC_IT: specifies the interrupt pending bit to clear.
+  *   
+  *   For @b STM32_Connectivity_line_devices, this parameter can be any combination
+  *   of the following values:
+  *     @arg RCC_IT_LSIRDY: LSI ready interrupt
+  *     @arg RCC_IT_LSERDY: LSE ready interrupt
+  *     @arg RCC_IT_HSIRDY: HSI ready interrupt
+  *     @arg RCC_IT_HSERDY: HSE ready interrupt
+  *     @arg RCC_IT_PLLRDY: PLL ready interrupt
+  *     @arg RCC_IT_PLL2RDY: PLL2 ready interrupt 
+  *     @arg RCC_IT_PLL3RDY: PLL3 ready interrupt                      
+  *     @arg RCC_IT_CSS: Clock Security System interrupt
+  * 
+  *   For @b other_STM32_devices, this parameter can be any combination of the
+  *   following values:        
+  *     @arg RCC_IT_LSIRDY: LSI ready interrupt
+  *     @arg RCC_IT_LSERDY: LSE ready interrupt
+  *     @arg RCC_IT_HSIRDY: HSI ready interrupt
+  *     @arg RCC_IT_HSERDY: HSE ready interrupt
+  *     @arg RCC_IT_PLLRDY: PLL ready interrupt
+  *   
+  *     @arg RCC_IT_CSS: Clock Security System interrupt
+  * @retval None
+  */
+void RCC_ClearITPendingBit(uint8_t RCC_IT)
+{
+  /* Check the parameters */
+  assert_param(IS_RCC_CLEAR_IT(RCC_IT));
+
+  /* Perform Byte access to RCC_CIR[23:16] bits to clear the selected interrupt
+     pending bits */
+  *(__IO uint8_t *) CIR_BYTE3_ADDRESS = RCC_IT;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/STM32_4路称重_Git提交精简工程/src/STM32F10x_FWLib/src/stm32f10x_rtc.c b/STM32_4路称重_Git提交精简工程/src/STM32F10x_FWLib/src/stm32f10x_rtc.c
new file mode 100755
index 0000000..f798d2b
--- /dev/null
+++ b/STM32_4路称重_Git提交精简工程/src/STM32F10x_FWLib/src/stm32f10x_rtc.c
@@ -0,0 +1,339 @@
+/**
+  ******************************************************************************
+  * @file    stm32f10x_rtc.c
+  * @author  MCD Application Team
+  * @version V3.5.0
+  * @date    11-March-2011
+  * @brief   This file provides all the RTC firmware functions.
+  ******************************************************************************
+  * @attention
+  *
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+  *
+  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x_rtc.h"
+
+/** @addtogroup STM32F10x_StdPeriph_Driver
+  * @{
+  */
+
+/** @defgroup RTC 
+  * @brief RTC driver modules
+  * @{
+  */
+
+/** @defgroup RTC_Private_TypesDefinitions
+  * @{
+  */ 
+/**
+  * @}
+  */
+
+/** @defgroup RTC_Private_Defines
+  * @{
+  */
+#define RTC_LSB_MASK     ((uint32_t)0x0000FFFF)  /*!< RTC LSB Mask */
+#define PRLH_MSB_MASK    ((uint32_t)0x000F0000)  /*!< RTC Prescaler MSB Mask */
+
+/**
+  * @}
+  */
+
+/** @defgroup RTC_Private_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup RTC_Private_Variables
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup RTC_Private_FunctionPrototypes
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup RTC_Private_Functions
+  * @{
+  */
+
+/**
+  * @brief  Enables or disables the specified RTC interrupts.
+  * @param  RTC_IT: specifies the RTC interrupts sources to be enabled or disabled.
+  *   This parameter can be any combination of the following values:
+  *     @arg RTC_IT_OW: Overflow interrupt
+  *     @arg RTC_IT_ALR: Alarm interrupt
+  *     @arg RTC_IT_SEC: Second interrupt
+  * @param  NewState: new state of the specified RTC interrupts.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void RTC_ITConfig(uint16_t RTC_IT, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_RTC_IT(RTC_IT));  
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  
+  if (NewState != DISABLE)
+  {
+    RTC->CRH |= RTC_IT;
+  }
+  else
+  {
+    RTC->CRH &= (uint16_t)~RTC_IT;
+  }
+}
+
+/**
+  * @brief  Enters the RTC configuration mode.
+  * @param  None
+  * @retval None
+  */
+void RTC_EnterConfigMode(void)
+{
+  /* Set the CNF flag to enter in the Configuration Mode */
+  RTC->CRL |= RTC_CRL_CNF;
+}
+
+/**
+  * @brief  Exits from the RTC configuration mode.
+  * @param  None
+  * @retval None
+  */
+void RTC_ExitConfigMode(void)
+{
+  /* Reset the CNF flag to exit from the Configuration Mode */
+  RTC->CRL &= (uint16_t)~((uint16_t)RTC_CRL_CNF); 
+}
+
+/**
+  * @brief  Gets the RTC counter value.
+  * @param  None
+  * @retval RTC counter value.
+  */
+uint32_t RTC_GetCounter(void)
+{
+  uint16_t tmp = 0;
+  tmp = RTC->CNTL;
+  return (((uint32_t)RTC->CNTH << 16 ) | tmp) ;
+}
+
+/**
+  * @brief  Sets the RTC counter value.
+  * @param  CounterValue: RTC counter new value.
+  * @retval None
+  */
+void RTC_SetCounter(uint32_t CounterValue)
+{ 
+  RTC_EnterConfigMode();
+  /* Set RTC COUNTER MSB word */
+  RTC->CNTH = CounterValue >> 16;
+  /* Set RTC COUNTER LSB word */
+  RTC->CNTL = (CounterValue & RTC_LSB_MASK);
+  RTC_ExitConfigMode();
+}
+
+/**
+  * @brief  Sets the RTC prescaler value.
+  * @param  PrescalerValue: RTC prescaler new value.
+  * @retval None
+  */
+void RTC_SetPrescaler(uint32_t PrescalerValue)
+{
+  /* Check the parameters */
+  assert_param(IS_RTC_PRESCALER(PrescalerValue));
+  
+  RTC_EnterConfigMode();
+  /* Set RTC PRESCALER MSB word */
+  RTC->PRLH = (PrescalerValue & PRLH_MSB_MASK) >> 16;
+  /* Set RTC PRESCALER LSB word */
+  RTC->PRLL = (PrescalerValue & RTC_LSB_MASK);
+  RTC_ExitConfigMode();
+}
+
+/**
+  * @brief  Sets the RTC alarm value.
+  * @param  AlarmValue: RTC alarm new value.
+  * @retval None
+  */
+void RTC_SetAlarm(uint32_t AlarmValue)
+{  
+  RTC_EnterConfigMode();
+  /* Set the ALARM MSB word */
+  RTC->ALRH = AlarmValue >> 16;
+  /* Set the ALARM LSB word */
+  RTC->ALRL = (AlarmValue & RTC_LSB_MASK);
+  RTC_ExitConfigMode();
+}
+
+/**
+  * @brief  Gets the RTC divider value.
+  * @param  None
+  * @retval RTC Divider value.
+  */
+uint32_t RTC_GetDivider(void)
+{
+  uint32_t tmp = 0x00;
+  tmp = ((uint32_t)RTC->DIVH & (uint32_t)0x000F) << 16;
+  tmp |= RTC->DIVL;
+  return tmp;
+}
+
+/**
+  * @brief  Waits until last write operation on RTC registers has finished.
+  * @note   This function must be called before any write to RTC registers.
+  * @param  None
+  * @retval None
+  */
+void RTC_WaitForLastTask(void)
+{
+  /* Loop until RTOFF flag is set */
+  while ((RTC->CRL & RTC_FLAG_RTOFF) == (uint16_t)RESET)
+  {
+  }
+}
+
+/**
+  * @brief  Waits until the RTC registers (RTC_CNT, RTC_ALR and RTC_PRL)
+  *   are synchronized with RTC APB clock.
+  * @note   This function must be called before any read operation after an APB reset
+  *   or an APB clock stop.
+  * @param  None
+  * @retval None
+  */
+void RTC_WaitForSynchro(void)
+{
+  /* Clear RSF flag */
+  RTC->CRL &= (uint16_t)~RTC_FLAG_RSF;
+  /* Loop until RSF flag is set */
+  while ((RTC->CRL & RTC_FLAG_RSF) == (uint16_t)RESET)
+  {
+  }
+}
+
+/**
+  * @brief  Checks whether the specified RTC flag is set or not.
+  * @param  RTC_FLAG: specifies the flag to check.
+  *   This parameter can be one the following values:
+  *     @arg RTC_FLAG_RTOFF: RTC Operation OFF flag
+  *     @arg RTC_FLAG_RSF: Registers Synchronized flag
+  *     @arg RTC_FLAG_OW: Overflow flag
+  *     @arg RTC_FLAG_ALR: Alarm flag
+  *     @arg RTC_FLAG_SEC: Second flag
+  * @retval The new state of RTC_FLAG (SET or RESET).
+  */
+FlagStatus RTC_GetFlagStatus(uint16_t RTC_FLAG)
+{
+  FlagStatus bitstatus = RESET;
+  
+  /* Check the parameters */
+  assert_param(IS_RTC_GET_FLAG(RTC_FLAG)); 
+  
+  if ((RTC->CRL & RTC_FLAG) != (uint16_t)RESET)
+  {
+    bitstatus = SET;
+  }
+  else
+  {
+    bitstatus = RESET;
+  }
+  return bitstatus;
+}
+
+/**
+  * @brief  Clears the RTC's pending flags.
+  * @param  RTC_FLAG: specifies the flag to clear.
+  *   This parameter can be any combination of the following values:
+  *     @arg RTC_FLAG_RSF: Registers Synchronized flag. This flag is cleared only after
+  *                        an APB reset or an APB Clock stop.
+  *     @arg RTC_FLAG_OW: Overflow flag
+  *     @arg RTC_FLAG_ALR: Alarm flag
+  *     @arg RTC_FLAG_SEC: Second flag
+  * @retval None
+  */
+void RTC_ClearFlag(uint16_t RTC_FLAG)
+{
+  /* Check the parameters */
+  assert_param(IS_RTC_CLEAR_FLAG(RTC_FLAG)); 
+    
+  /* Clear the corresponding RTC flag */
+  RTC->CRL &= (uint16_t)~RTC_FLAG;
+}
+
+/**
+  * @brief  Checks whether the specified RTC interrupt has occurred or not.
+  * @param  RTC_IT: specifies the RTC interrupts sources to check.
+  *   This parameter can be one of the following values:
+  *     @arg RTC_IT_OW: Overflow interrupt
+  *     @arg RTC_IT_ALR: Alarm interrupt
+  *     @arg RTC_IT_SEC: Second interrupt
+  * @retval The new state of the RTC_IT (SET or RESET).
+  */
+ITStatus RTC_GetITStatus(uint16_t RTC_IT)
+{
+  ITStatus bitstatus = RESET;
+  /* Check the parameters */
+  assert_param(IS_RTC_GET_IT(RTC_IT)); 
+  
+  bitstatus = (ITStatus)(RTC->CRL & RTC_IT);
+  if (((RTC->CRH & RTC_IT) != (uint16_t)RESET) && (bitstatus != (uint16_t)RESET))
+  {
+    bitstatus = SET;
+  }
+  else
+  {
+    bitstatus = RESET;
+  }
+  return bitstatus;
+}
+
+/**
+  * @brief  Clears the RTC's interrupt pending bits.
+  * @param  RTC_IT: specifies the interrupt pending bit to clear.
+  *   This parameter can be any combination of the following values:
+  *     @arg RTC_IT_OW: Overflow interrupt
+  *     @arg RTC_IT_ALR: Alarm interrupt
+  *     @arg RTC_IT_SEC: Second interrupt
+  * @retval None
+  */
+void RTC_ClearITPendingBit(uint16_t RTC_IT)
+{
+  /* Check the parameters */
+  assert_param(IS_RTC_IT(RTC_IT));  
+  
+  /* Clear the corresponding RTC pending bit */
+  RTC->CRL &= (uint16_t)~RTC_IT;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/STM32_4路称重_Git提交精简工程/src/STM32F10x_FWLib/src/stm32f10x_sdio.c b/STM32_4路称重_Git提交精简工程/src/STM32F10x_FWLib/src/stm32f10x_sdio.c
new file mode 100755
index 0000000..d1870ce
--- /dev/null
+++ b/STM32_4路称重_Git提交精简工程/src/STM32F10x_FWLib/src/stm32f10x_sdio.c
@@ -0,0 +1,799 @@
+/**
+  ******************************************************************************
+  * @file    stm32f10x_sdio.c
+  * @author  MCD Application Team
+  * @version V3.5.0
+  * @date    11-March-2011
+  * @brief   This file provides all the SDIO firmware functions.
+  ******************************************************************************
+  * @attention
+  *
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+  *
+  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x_sdio.h"
+#include "stm32f10x_rcc.h"
+
+/** @addtogroup STM32F10x_StdPeriph_Driver
+  * @{
+  */
+
+/** @defgroup SDIO 
+  * @brief SDIO driver modules
+  * @{
+  */ 
+
+/** @defgroup SDIO_Private_TypesDefinitions
+  * @{
+  */ 
+
+/* ------------ SDIO registers bit address in the alias region ----------- */
+#define SDIO_OFFSET                (SDIO_BASE - PERIPH_BASE)
+
+/* --- CLKCR Register ---*/
+
+/* Alias word address of CLKEN bit */
+#define CLKCR_OFFSET              (SDIO_OFFSET + 0x04)
+#define CLKEN_BitNumber           0x08
+#define CLKCR_CLKEN_BB            (PERIPH_BB_BASE + (CLKCR_OFFSET * 32) + (CLKEN_BitNumber * 4))
+
+/* --- CMD Register ---*/
+
+/* Alias word address of SDIOSUSPEND bit */
+#define CMD_OFFSET                (SDIO_OFFSET + 0x0C)
+#define SDIOSUSPEND_BitNumber     0x0B
+#define CMD_SDIOSUSPEND_BB        (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (SDIOSUSPEND_BitNumber * 4))
+
+/* Alias word address of ENCMDCOMPL bit */
+#define ENCMDCOMPL_BitNumber      0x0C
+#define CMD_ENCMDCOMPL_BB         (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (ENCMDCOMPL_BitNumber * 4))
+
+/* Alias word address of NIEN bit */
+#define NIEN_BitNumber            0x0D
+#define CMD_NIEN_BB               (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (NIEN_BitNumber * 4))
+
+/* Alias word address of ATACMD bit */
+#define ATACMD_BitNumber          0x0E
+#define CMD_ATACMD_BB             (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (ATACMD_BitNumber * 4))
+
+/* --- DCTRL Register ---*/
+
+/* Alias word address of DMAEN bit */
+#define DCTRL_OFFSET              (SDIO_OFFSET + 0x2C)
+#define DMAEN_BitNumber           0x03
+#define DCTRL_DMAEN_BB            (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (DMAEN_BitNumber * 4))
+
+/* Alias word address of RWSTART bit */
+#define RWSTART_BitNumber         0x08
+#define DCTRL_RWSTART_BB          (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (RWSTART_BitNumber * 4))
+
+/* Alias word address of RWSTOP bit */
+#define RWSTOP_BitNumber          0x09
+#define DCTRL_RWSTOP_BB           (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (RWSTOP_BitNumber * 4))
+
+/* Alias word address of RWMOD bit */
+#define RWMOD_BitNumber           0x0A
+#define DCTRL_RWMOD_BB            (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (RWMOD_BitNumber * 4))
+
+/* Alias word address of SDIOEN bit */
+#define SDIOEN_BitNumber          0x0B
+#define DCTRL_SDIOEN_BB           (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (SDIOEN_BitNumber * 4))
+
+/* ---------------------- SDIO registers bit mask ------------------------ */
+
+/* --- CLKCR Register ---*/
+
+/* CLKCR register clear mask */
+#define CLKCR_CLEAR_MASK         ((uint32_t)0xFFFF8100) 
+
+/* --- PWRCTRL Register ---*/
+
+/* SDIO PWRCTRL Mask */
+#define PWR_PWRCTRL_MASK         ((uint32_t)0xFFFFFFFC)
+
+/* --- DCTRL Register ---*/
+
+/* SDIO DCTRL Clear Mask */
+#define DCTRL_CLEAR_MASK         ((uint32_t)0xFFFFFF08)
+
+/* --- CMD Register ---*/
+
+/* CMD Register clear mask */
+#define CMD_CLEAR_MASK           ((uint32_t)0xFFFFF800)
+
+/* SDIO RESP Registers Address */
+#define SDIO_RESP_ADDR           ((uint32_t)(SDIO_BASE + 0x14))
+
+/**
+  * @}
+  */
+
+/** @defgroup SDIO_Private_Defines
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup SDIO_Private_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup SDIO_Private_Variables
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup SDIO_Private_FunctionPrototypes
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup SDIO_Private_Functions
+  * @{
+  */
+
+/**
+  * @brief  Deinitializes the SDIO peripheral registers to their default reset values.
+  * @param  None
+  * @retval None
+  */
+void SDIO_DeInit(void)
+{
+  SDIO->POWER = 0x00000000;
+  SDIO->CLKCR = 0x00000000;
+  SDIO->ARG = 0x00000000;
+  SDIO->CMD = 0x00000000;
+  SDIO->DTIMER = 0x00000000;
+  SDIO->DLEN = 0x00000000;
+  SDIO->DCTRL = 0x00000000;
+  SDIO->ICR = 0x00C007FF;
+  SDIO->MASK = 0x00000000;
+}
+
+/**
+  * @brief  Initializes the SDIO peripheral according to the specified 
+  *         parameters in the SDIO_InitStruct.
+  * @param  SDIO_InitStruct : pointer to a SDIO_InitTypeDef structure 
+  *         that contains the configuration information for the SDIO peripheral.
+  * @retval None
+  */
+void SDIO_Init(SDIO_InitTypeDef* SDIO_InitStruct)
+{
+  uint32_t tmpreg = 0;
+    
+  /* Check the parameters */
+  assert_param(IS_SDIO_CLOCK_EDGE(SDIO_InitStruct->SDIO_ClockEdge));
+  assert_param(IS_SDIO_CLOCK_BYPASS(SDIO_InitStruct->SDIO_ClockBypass));
+  assert_param(IS_SDIO_CLOCK_POWER_SAVE(SDIO_InitStruct->SDIO_ClockPowerSave));
+  assert_param(IS_SDIO_BUS_WIDE(SDIO_InitStruct->SDIO_BusWide));
+  assert_param(IS_SDIO_HARDWARE_FLOW_CONTROL(SDIO_InitStruct->SDIO_HardwareFlowControl)); 
+   
+/*---------------------------- SDIO CLKCR Configuration ------------------------*/  
+  /* Get the SDIO CLKCR value */
+  tmpreg = SDIO->CLKCR;
+  
+  /* Clear CLKDIV, PWRSAV, BYPASS, WIDBUS, NEGEDGE, HWFC_EN bits */
+  tmpreg &= CLKCR_CLEAR_MASK;
+  
+  /* Set CLKDIV bits according to SDIO_ClockDiv value */
+  /* Set PWRSAV bit according to SDIO_ClockPowerSave value */
+  /* Set BYPASS bit according to SDIO_ClockBypass value */
+  /* Set WIDBUS bits according to SDIO_BusWide value */
+  /* Set NEGEDGE bits according to SDIO_ClockEdge value */
+  /* Set HWFC_EN bits according to SDIO_HardwareFlowControl value */
+  tmpreg |= (SDIO_InitStruct->SDIO_ClockDiv  | SDIO_InitStruct->SDIO_ClockPowerSave |
+             SDIO_InitStruct->SDIO_ClockBypass | SDIO_InitStruct->SDIO_BusWide |
+             SDIO_InitStruct->SDIO_ClockEdge | SDIO_InitStruct->SDIO_HardwareFlowControl); 
+  
+  /* Write to SDIO CLKCR */
+  SDIO->CLKCR = tmpreg;
+}
+
+/**
+  * @brief  Fills each SDIO_InitStruct member with its default value.
+  * @param  SDIO_InitStruct: pointer to an SDIO_InitTypeDef structure which 
+  *   will be initialized.
+  * @retval None
+  */
+void SDIO_StructInit(SDIO_InitTypeDef* SDIO_InitStruct)
+{
+  /* SDIO_InitStruct members default value */
+  SDIO_InitStruct->SDIO_ClockDiv = 0x00;
+  SDIO_InitStruct->SDIO_ClockEdge = SDIO_ClockEdge_Rising;
+  SDIO_InitStruct->SDIO_ClockBypass = SDIO_ClockBypass_Disable;
+  SDIO_InitStruct->SDIO_ClockPowerSave = SDIO_ClockPowerSave_Disable;
+  SDIO_InitStruct->SDIO_BusWide = SDIO_BusWide_1b;
+  SDIO_InitStruct->SDIO_HardwareFlowControl = SDIO_HardwareFlowControl_Disable;
+}
+
+/**
+  * @brief  Enables or disables the SDIO Clock.
+  * @param  NewState: new state of the SDIO Clock. This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void SDIO_ClockCmd(FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  
+  *(__IO uint32_t *) CLKCR_CLKEN_BB = (uint32_t)NewState;
+}
+
+/**
+  * @brief  Sets the power status of the controller.
+  * @param  SDIO_PowerState: new state of the Power state. 
+  *   This parameter can be one of the following values:
+  *     @arg SDIO_PowerState_OFF
+  *     @arg SDIO_PowerState_ON
+  * @retval None
+  */
+void SDIO_SetPowerState(uint32_t SDIO_PowerState)
+{
+  /* Check the parameters */
+  assert_param(IS_SDIO_POWER_STATE(SDIO_PowerState));
+  
+  SDIO->POWER &= PWR_PWRCTRL_MASK;
+  SDIO->POWER |= SDIO_PowerState;
+}
+
+/**
+  * @brief  Gets the power status of the controller.
+  * @param  None
+  * @retval Power status of the controller. The returned value can
+  *   be one of the following:
+  * - 0x00: Power OFF
+  * - 0x02: Power UP
+  * - 0x03: Power ON 
+  */
+uint32_t SDIO_GetPowerState(void)
+{
+  return (SDIO->POWER & (~PWR_PWRCTRL_MASK));
+}
+
+/**
+  * @brief  Enables or disables the SDIO interrupts.
+  * @param  SDIO_IT: specifies the SDIO interrupt sources to be enabled or disabled.
+  *   This parameter can be one or a combination of the following values:
+  *     @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
+  *     @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
+  *     @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt
+  *     @arg SDIO_IT_DTIMEOUT: Data timeout interrupt
+  *     @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt
+  *     @arg SDIO_IT_RXOVERR:  Received FIFO overrun error interrupt
+  *     @arg SDIO_IT_CMDREND:  Command response received (CRC check passed) interrupt
+  *     @arg SDIO_IT_CMDSENT:  Command sent (no response required) interrupt
+  *     @arg SDIO_IT_DATAEND:  Data end (data counter, SDIDCOUNT, is zero) interrupt
+  *     @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide 
+  *                            bus mode interrupt
+  *     @arg SDIO_IT_DBCKEND:  Data block sent/received (CRC check passed) interrupt
+  *     @arg SDIO_IT_CMDACT:   Command transfer in progress interrupt
+  *     @arg SDIO_IT_TXACT:    Data transmit in progress interrupt
+  *     @arg SDIO_IT_RXACT:    Data receive in progress interrupt
+  *     @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
+  *     @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt
+  *     @arg SDIO_IT_TXFIFOF:  Transmit FIFO full interrupt
+  *     @arg SDIO_IT_RXFIFOF:  Receive FIFO full interrupt
+  *     @arg SDIO_IT_TXFIFOE:  Transmit FIFO empty interrupt
+  *     @arg SDIO_IT_RXFIFOE:  Receive FIFO empty interrupt
+  *     @arg SDIO_IT_TXDAVL:   Data available in transmit FIFO interrupt
+  *     @arg SDIO_IT_RXDAVL:   Data available in receive FIFO interrupt
+  *     @arg SDIO_IT_SDIOIT:   SD I/O interrupt received interrupt
+  *     @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61 interrupt
+  * @param  NewState: new state of the specified SDIO interrupts.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None 
+  */
+void SDIO_ITConfig(uint32_t SDIO_IT, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_SDIO_IT(SDIO_IT));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  
+  if (NewState != DISABLE)
+  {
+    /* Enable the SDIO interrupts */
+    SDIO->MASK |= SDIO_IT;
+  }
+  else
+  {
+    /* Disable the SDIO interrupts */
+    SDIO->MASK &= ~SDIO_IT;
+  } 
+}
+
+/**
+  * @brief  Enables or disables the SDIO DMA request.
+  * @param  NewState: new state of the selected SDIO DMA request.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void SDIO_DMACmd(FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  
+  *(__IO uint32_t *) DCTRL_DMAEN_BB = (uint32_t)NewState;
+}
+
+/**
+  * @brief  Initializes the SDIO Command according to the specified 
+  *         parameters in the SDIO_CmdInitStruct and send the command.
+  * @param  SDIO_CmdInitStruct : pointer to a SDIO_CmdInitTypeDef 
+  *         structure that contains the configuration information for the SDIO command.
+  * @retval None
+  */
+void SDIO_SendCommand(SDIO_CmdInitTypeDef *SDIO_CmdInitStruct)
+{
+  uint32_t tmpreg = 0;
+  
+  /* Check the parameters */
+  assert_param(IS_SDIO_CMD_INDEX(SDIO_CmdInitStruct->SDIO_CmdIndex));
+  assert_param(IS_SDIO_RESPONSE(SDIO_CmdInitStruct->SDIO_Response));
+  assert_param(IS_SDIO_WAIT(SDIO_CmdInitStruct->SDIO_Wait));
+  assert_param(IS_SDIO_CPSM(SDIO_CmdInitStruct->SDIO_CPSM));
+  
+/*---------------------------- SDIO ARG Configuration ------------------------*/
+  /* Set the SDIO Argument value */
+  SDIO->ARG = SDIO_CmdInitStruct->SDIO_Argument;
+  
+/*---------------------------- SDIO CMD Configuration ------------------------*/  
+  /* Get the SDIO CMD value */
+  tmpreg = SDIO->CMD;
+  /* Clear CMDINDEX, WAITRESP, WAITINT, WAITPEND, CPSMEN bits */
+  tmpreg &= CMD_CLEAR_MASK;
+  /* Set CMDINDEX bits according to SDIO_CmdIndex value */
+  /* Set WAITRESP bits according to SDIO_Response value */
+  /* Set WAITINT and WAITPEND bits according to SDIO_Wait value */
+  /* Set CPSMEN bits according to SDIO_CPSM value */
+  tmpreg |= (uint32_t)SDIO_CmdInitStruct->SDIO_CmdIndex | SDIO_CmdInitStruct->SDIO_Response
+           | SDIO_CmdInitStruct->SDIO_Wait | SDIO_CmdInitStruct->SDIO_CPSM;
+  
+  /* Write to SDIO CMD */
+  SDIO->CMD = tmpreg;
+}
+
+/**
+  * @brief  Fills each SDIO_CmdInitStruct member with its default value.
+  * @param  SDIO_CmdInitStruct: pointer to an SDIO_CmdInitTypeDef 
+  *         structure which will be initialized.
+  * @retval None
+  */
+void SDIO_CmdStructInit(SDIO_CmdInitTypeDef* SDIO_CmdInitStruct)
+{
+  /* SDIO_CmdInitStruct members default value */
+  SDIO_CmdInitStruct->SDIO_Argument = 0x00;
+  SDIO_CmdInitStruct->SDIO_CmdIndex = 0x00;
+  SDIO_CmdInitStruct->SDIO_Response = SDIO_Response_No;
+  SDIO_CmdInitStruct->SDIO_Wait = SDIO_Wait_No;
+  SDIO_CmdInitStruct->SDIO_CPSM = SDIO_CPSM_Disable;
+}
+
+/**
+  * @brief  Returns command index of last command for which response received.
+  * @param  None
+  * @retval Returns the command index of the last command response received.
+  */
+uint8_t SDIO_GetCommandResponse(void)
+{
+  return (uint8_t)(SDIO->RESPCMD);
+}
+
+/**
+  * @brief  Returns response received from the card for the last command.
+  * @param  SDIO_RESP: Specifies the SDIO response register. 
+  *   This parameter can be one of the following values:
+  *     @arg SDIO_RESP1: Response Register 1
+  *     @arg SDIO_RESP2: Response Register 2
+  *     @arg SDIO_RESP3: Response Register 3
+  *     @arg SDIO_RESP4: Response Register 4
+  * @retval The Corresponding response register value.
+  */
+uint32_t SDIO_GetResponse(uint32_t SDIO_RESP)
+{
+  __IO uint32_t tmp = 0;
+
+  /* Check the parameters */
+  assert_param(IS_SDIO_RESP(SDIO_RESP));
+
+  tmp = SDIO_RESP_ADDR + SDIO_RESP;
+  
+  return (*(__IO uint32_t *) tmp); 
+}
+
+/**
+  * @brief  Initializes the SDIO data path according to the specified 
+  *   parameters in the SDIO_DataInitStruct.
+  * @param  SDIO_DataInitStruct : pointer to a SDIO_DataInitTypeDef structure that
+  *   contains the configuration information for the SDIO command.
+  * @retval None
+  */
+void SDIO_DataConfig(SDIO_DataInitTypeDef* SDIO_DataInitStruct)
+{
+  uint32_t tmpreg = 0;
+  
+  /* Check the parameters */
+  assert_param(IS_SDIO_DATA_LENGTH(SDIO_DataInitStruct->SDIO_DataLength));
+  assert_param(IS_SDIO_BLOCK_SIZE(SDIO_DataInitStruct->SDIO_DataBlockSize));
+  assert_param(IS_SDIO_TRANSFER_DIR(SDIO_DataInitStruct->SDIO_TransferDir));
+  assert_param(IS_SDIO_TRANSFER_MODE(SDIO_DataInitStruct->SDIO_TransferMode));
+  assert_param(IS_SDIO_DPSM(SDIO_DataInitStruct->SDIO_DPSM));
+
+/*---------------------------- SDIO DTIMER Configuration ---------------------*/
+  /* Set the SDIO Data TimeOut value */
+  SDIO->DTIMER = SDIO_DataInitStruct->SDIO_DataTimeOut;
+
+/*---------------------------- SDIO DLEN Configuration -----------------------*/
+  /* Set the SDIO DataLength value */
+  SDIO->DLEN = SDIO_DataInitStruct->SDIO_DataLength;
+
+/*---------------------------- SDIO DCTRL Configuration ----------------------*/  
+  /* Get the SDIO DCTRL value */
+  tmpreg = SDIO->DCTRL;
+  /* Clear DEN, DTMODE, DTDIR and DBCKSIZE bits */
+  tmpreg &= DCTRL_CLEAR_MASK;
+  /* Set DEN bit according to SDIO_DPSM value */
+  /* Set DTMODE bit according to SDIO_TransferMode value */
+  /* Set DTDIR bit according to SDIO_TransferDir value */
+  /* Set DBCKSIZE bits according to SDIO_DataBlockSize value */
+  tmpreg |= (uint32_t)SDIO_DataInitStruct->SDIO_DataBlockSize | SDIO_DataInitStruct->SDIO_TransferDir
+           | SDIO_DataInitStruct->SDIO_TransferMode | SDIO_DataInitStruct->SDIO_DPSM;
+
+  /* Write to SDIO DCTRL */
+  SDIO->DCTRL = tmpreg;
+}
+
+/**
+  * @brief  Fills each SDIO_DataInitStruct member with its default value.
+  * @param  SDIO_DataInitStruct: pointer to an SDIO_DataInitTypeDef structure which
+  *         will be initialized.
+  * @retval None
+  */
+void SDIO_DataStructInit(SDIO_DataInitTypeDef* SDIO_DataInitStruct)
+{
+  /* SDIO_DataInitStruct members default value */
+  SDIO_DataInitStruct->SDIO_DataTimeOut = 0xFFFFFFFF;
+  SDIO_DataInitStruct->SDIO_DataLength = 0x00;
+  SDIO_DataInitStruct->SDIO_DataBlockSize = SDIO_DataBlockSize_1b;
+  SDIO_DataInitStruct->SDIO_TransferDir = SDIO_TransferDir_ToCard;
+  SDIO_DataInitStruct->SDIO_TransferMode = SDIO_TransferMode_Block;  
+  SDIO_DataInitStruct->SDIO_DPSM = SDIO_DPSM_Disable;
+}
+
+/**
+  * @brief  Returns number of remaining data bytes to be transferred.
+  * @param  None
+  * @retval Number of remaining data bytes to be transferred
+  */
+uint32_t SDIO_GetDataCounter(void)
+{ 
+  return SDIO->DCOUNT;
+}
+
+/**
+  * @brief  Read one data word from Rx FIFO.
+  * @param  None
+  * @retval Data received
+  */
+uint32_t SDIO_ReadData(void)
+{ 
+  return SDIO->FIFO;
+}
+
+/**
+  * @brief  Write one data word to Tx FIFO.
+  * @param  Data: 32-bit data word to write.
+  * @retval None
+  */
+void SDIO_WriteData(uint32_t Data)
+{ 
+  SDIO->FIFO = Data;
+}
+
+/**
+  * @brief  Returns the number of words left to be written to or read from FIFO.	
+  * @param  None
+  * @retval Remaining number of words.
+  */
+uint32_t SDIO_GetFIFOCount(void)
+{ 
+  return SDIO->FIFOCNT;
+}
+
+/**
+  * @brief  Starts the SD I/O Read Wait operation.	
+  * @param  NewState: new state of the Start SDIO Read Wait operation. 
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void SDIO_StartSDIOReadWait(FunctionalState NewState)
+{ 
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  
+  *(__IO uint32_t *) DCTRL_RWSTART_BB = (uint32_t) NewState;
+}
+
+/**
+  * @brief  Stops the SD I/O Read Wait operation.	
+  * @param  NewState: new state of the Stop SDIO Read Wait operation. 
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void SDIO_StopSDIOReadWait(FunctionalState NewState)
+{ 
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  
+  *(__IO uint32_t *) DCTRL_RWSTOP_BB = (uint32_t) NewState;
+}
+
+/**
+  * @brief  Sets one of the two options of inserting read wait interval.
+  * @param  SDIO_ReadWaitMode: SD I/O Read Wait operation mode.
+  *   This parameter can be:
+  *     @arg SDIO_ReadWaitMode_CLK: Read Wait control by stopping SDIOCLK
+  *     @arg SDIO_ReadWaitMode_DATA2: Read Wait control using SDIO_DATA2
+  * @retval None
+  */
+void SDIO_SetSDIOReadWaitMode(uint32_t SDIO_ReadWaitMode)
+{
+  /* Check the parameters */
+  assert_param(IS_SDIO_READWAIT_MODE(SDIO_ReadWaitMode));
+  
+  *(__IO uint32_t *) DCTRL_RWMOD_BB = SDIO_ReadWaitMode;
+}
+
+/**
+  * @brief  Enables or disables the SD I/O Mode Operation.
+  * @param  NewState: new state of SDIO specific operation. 
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void SDIO_SetSDIOOperation(FunctionalState NewState)
+{ 
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  
+  *(__IO uint32_t *) DCTRL_SDIOEN_BB = (uint32_t)NewState;
+}
+
+/**
+  * @brief  Enables or disables the SD I/O Mode suspend command sending.
+  * @param  NewState: new state of the SD I/O Mode suspend command.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void SDIO_SendSDIOSuspendCmd(FunctionalState NewState)
+{ 
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  
+  *(__IO uint32_t *) CMD_SDIOSUSPEND_BB = (uint32_t)NewState;
+}
+
+/**
+  * @brief  Enables or disables the command completion signal.
+  * @param  NewState: new state of command completion signal. 
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void SDIO_CommandCompletionCmd(FunctionalState NewState)
+{ 
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  
+  *(__IO uint32_t *) CMD_ENCMDCOMPL_BB = (uint32_t)NewState;
+}
+
+/**
+  * @brief  Enables or disables the CE-ATA interrupt.
+  * @param  NewState: new state of CE-ATA interrupt. This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void SDIO_CEATAITCmd(FunctionalState NewState)
+{ 
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  
+  *(__IO uint32_t *) CMD_NIEN_BB = (uint32_t)((~((uint32_t)NewState)) & ((uint32_t)0x1));
+}
+
+/**
+  * @brief  Sends CE-ATA command (CMD61).
+  * @param  NewState: new state of CE-ATA command. This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void SDIO_SendCEATACmd(FunctionalState NewState)
+{ 
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  
+  *(__IO uint32_t *) CMD_ATACMD_BB = (uint32_t)NewState;
+}
+
+/**
+  * @brief  Checks whether the specified SDIO flag is set or not.
+  * @param  SDIO_FLAG: specifies the flag to check. 
+  *   This parameter can be one of the following values:
+  *     @arg SDIO_FLAG_CCRCFAIL: Command response received (CRC check failed)
+  *     @arg SDIO_FLAG_DCRCFAIL: Data block sent/received (CRC check failed)
+  *     @arg SDIO_FLAG_CTIMEOUT: Command response timeout
+  *     @arg SDIO_FLAG_DTIMEOUT: Data timeout
+  *     @arg SDIO_FLAG_TXUNDERR: Transmit FIFO underrun error
+  *     @arg SDIO_FLAG_RXOVERR:  Received FIFO overrun error
+  *     @arg SDIO_FLAG_CMDREND:  Command response received (CRC check passed)
+  *     @arg SDIO_FLAG_CMDSENT:  Command sent (no response required)
+  *     @arg SDIO_FLAG_DATAEND:  Data end (data counter, SDIDCOUNT, is zero)
+  *     @arg SDIO_FLAG_STBITERR: Start bit not detected on all data signals in wide 
+  *                              bus mode.
+  *     @arg SDIO_FLAG_DBCKEND:  Data block sent/received (CRC check passed)
+  *     @arg SDIO_FLAG_CMDACT:   Command transfer in progress
+  *     @arg SDIO_FLAG_TXACT:    Data transmit in progress
+  *     @arg SDIO_FLAG_RXACT:    Data receive in progress
+  *     @arg SDIO_FLAG_TXFIFOHE: Transmit FIFO Half Empty
+  *     @arg SDIO_FLAG_RXFIFOHF: Receive FIFO Half Full
+  *     @arg SDIO_FLAG_TXFIFOF:  Transmit FIFO full
+  *     @arg SDIO_FLAG_RXFIFOF:  Receive FIFO full
+  *     @arg SDIO_FLAG_TXFIFOE:  Transmit FIFO empty
+  *     @arg SDIO_FLAG_RXFIFOE:  Receive FIFO empty
+  *     @arg SDIO_FLAG_TXDAVL:   Data available in transmit FIFO
+  *     @arg SDIO_FLAG_RXDAVL:   Data available in receive FIFO
+  *     @arg SDIO_FLAG_SDIOIT:   SD I/O interrupt received
+  *     @arg SDIO_FLAG_CEATAEND: CE-ATA command completion signal received for CMD61
+  * @retval The new state of SDIO_FLAG (SET or RESET).
+  */
+FlagStatus SDIO_GetFlagStatus(uint32_t SDIO_FLAG)
+{ 
+  FlagStatus bitstatus = RESET;
+  
+  /* Check the parameters */
+  assert_param(IS_SDIO_FLAG(SDIO_FLAG));
+  
+  if ((SDIO->STA & SDIO_FLAG) != (uint32_t)RESET)
+  {
+    bitstatus = SET;
+  }
+  else
+  {
+    bitstatus = RESET;
+  }
+  return bitstatus;
+}
+
+/**
+  * @brief  Clears the SDIO's pending flags.
+  * @param  SDIO_FLAG: specifies the flag to clear.  
+  *   This parameter can be one or a combination of the following values:
+  *     @arg SDIO_FLAG_CCRCFAIL: Command response received (CRC check failed)
+  *     @arg SDIO_FLAG_DCRCFAIL: Data block sent/received (CRC check failed)
+  *     @arg SDIO_FLAG_CTIMEOUT: Command response timeout
+  *     @arg SDIO_FLAG_DTIMEOUT: Data timeout
+  *     @arg SDIO_FLAG_TXUNDERR: Transmit FIFO underrun error
+  *     @arg SDIO_FLAG_RXOVERR:  Received FIFO overrun error
+  *     @arg SDIO_FLAG_CMDREND:  Command response received (CRC check passed)
+  *     @arg SDIO_FLAG_CMDSENT:  Command sent (no response required)
+  *     @arg SDIO_FLAG_DATAEND:  Data end (data counter, SDIDCOUNT, is zero)
+  *     @arg SDIO_FLAG_STBITERR: Start bit not detected on all data signals in wide 
+  *                              bus mode
+  *     @arg SDIO_FLAG_DBCKEND:  Data block sent/received (CRC check passed)
+  *     @arg SDIO_FLAG_SDIOIT:   SD I/O interrupt received
+  *     @arg SDIO_FLAG_CEATAEND: CE-ATA command completion signal received for CMD61
+  * @retval None
+  */
+void SDIO_ClearFlag(uint32_t SDIO_FLAG)
+{ 
+  /* Check the parameters */
+  assert_param(IS_SDIO_CLEAR_FLAG(SDIO_FLAG));
+   
+  SDIO->ICR = SDIO_FLAG;
+}
+
+/**
+  * @brief  Checks whether the specified SDIO interrupt has occurred or not.
+  * @param  SDIO_IT: specifies the SDIO interrupt source to check. 
+  *   This parameter can be one of the following values:
+  *     @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
+  *     @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
+  *     @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt
+  *     @arg SDIO_IT_DTIMEOUT: Data timeout interrupt
+  *     @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt
+  *     @arg SDIO_IT_RXOVERR:  Received FIFO overrun error interrupt
+  *     @arg SDIO_IT_CMDREND:  Command response received (CRC check passed) interrupt
+  *     @arg SDIO_IT_CMDSENT:  Command sent (no response required) interrupt
+  *     @arg SDIO_IT_DATAEND:  Data end (data counter, SDIDCOUNT, is zero) interrupt
+  *     @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide 
+  *                            bus mode interrupt
+  *     @arg SDIO_IT_DBCKEND:  Data block sent/received (CRC check passed) interrupt
+  *     @arg SDIO_IT_CMDACT:   Command transfer in progress interrupt
+  *     @arg SDIO_IT_TXACT:    Data transmit in progress interrupt
+  *     @arg SDIO_IT_RXACT:    Data receive in progress interrupt
+  *     @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
+  *     @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt
+  *     @arg SDIO_IT_TXFIFOF:  Transmit FIFO full interrupt
+  *     @arg SDIO_IT_RXFIFOF:  Receive FIFO full interrupt
+  *     @arg SDIO_IT_TXFIFOE:  Transmit FIFO empty interrupt
+  *     @arg SDIO_IT_RXFIFOE:  Receive FIFO empty interrupt
+  *     @arg SDIO_IT_TXDAVL:   Data available in transmit FIFO interrupt
+  *     @arg SDIO_IT_RXDAVL:   Data available in receive FIFO interrupt
+  *     @arg SDIO_IT_SDIOIT:   SD I/O interrupt received interrupt
+  *     @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61 interrupt
+  * @retval The new state of SDIO_IT (SET or RESET).
+  */
+ITStatus SDIO_GetITStatus(uint32_t SDIO_IT)
+{ 
+  ITStatus bitstatus = RESET;
+  
+  /* Check the parameters */
+  assert_param(IS_SDIO_GET_IT(SDIO_IT));
+  if ((SDIO->STA & SDIO_IT) != (uint32_t)RESET)  
+  {
+    bitstatus = SET;
+  }
+  else
+  {
+    bitstatus = RESET;
+  }
+  return bitstatus;
+}
+
+/**
+  * @brief  Clears the SDIO's interrupt pending bits.
+  * @param  SDIO_IT: specifies the interrupt pending bit to clear. 
+  *   This parameter can be one or a combination of the following values:
+  *     @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
+  *     @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
+  *     @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt
+  *     @arg SDIO_IT_DTIMEOUT: Data timeout interrupt
+  *     @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt
+  *     @arg SDIO_IT_RXOVERR:  Received FIFO overrun error interrupt
+  *     @arg SDIO_IT_CMDREND:  Command response received (CRC check passed) interrupt
+  *     @arg SDIO_IT_CMDSENT:  Command sent (no response required) interrupt
+  *     @arg SDIO_IT_DATAEND:  Data end (data counter, SDIDCOUNT, is zero) interrupt
+  *     @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide 
+  *                            bus mode interrupt
+  *     @arg SDIO_IT_SDIOIT:   SD I/O interrupt received interrupt
+  *     @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61
+  * @retval None
+  */
+void SDIO_ClearITPendingBit(uint32_t SDIO_IT)
+{ 
+  /* Check the parameters */
+  assert_param(IS_SDIO_CLEAR_IT(SDIO_IT));
+   
+  SDIO->ICR = SDIO_IT;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/STM32_4路称重_Git提交精简工程/src/STM32F10x_FWLib/src/stm32f10x_spi.c b/STM32_4路称重_Git提交精简工程/src/STM32F10x_FWLib/src/stm32f10x_spi.c
new file mode 100755
index 0000000..51a9cce
--- /dev/null
+++ b/STM32_4路称重_Git提交精简工程/src/STM32F10x_FWLib/src/stm32f10x_spi.c
@@ -0,0 +1,908 @@
+/**
+  ******************************************************************************
+  * @file    stm32f10x_spi.c
+  * @author  MCD Application Team
+  * @version V3.5.0
+  * @date    11-March-2011
+  * @brief   This file provides all the SPI firmware functions.
+  ******************************************************************************
+  * @attention
+  *
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+  *
+  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x_spi.h"
+#include "stm32f10x_rcc.h"
+
+/** @addtogroup STM32F10x_StdPeriph_Driver
+  * @{
+  */
+
+/** @defgroup SPI 
+  * @brief SPI driver modules
+  * @{
+  */ 
+
+/** @defgroup SPI_Private_TypesDefinitions
+  * @{
+  */
+
+/**
+  * @}
+  */ 
+
+
+/** @defgroup SPI_Private_Defines
+  * @{
+  */
+
+/* SPI SPE mask */
+#define CR1_SPE_Set          ((uint16_t)0x0040)
+#define CR1_SPE_Reset        ((uint16_t)0xFFBF)
+
+/* I2S I2SE mask */
+#define I2SCFGR_I2SE_Set     ((uint16_t)0x0400)
+#define I2SCFGR_I2SE_Reset   ((uint16_t)0xFBFF)
+
+/* SPI CRCNext mask */
+#define CR1_CRCNext_Set      ((uint16_t)0x1000)
+
+/* SPI CRCEN mask */
+#define CR1_CRCEN_Set        ((uint16_t)0x2000)
+#define CR1_CRCEN_Reset      ((uint16_t)0xDFFF)
+
+/* SPI SSOE mask */
+#define CR2_SSOE_Set         ((uint16_t)0x0004)
+#define CR2_SSOE_Reset       ((uint16_t)0xFFFB)
+
+/* SPI registers Masks */
+#define CR1_CLEAR_Mask       ((uint16_t)0x3040)
+#define I2SCFGR_CLEAR_Mask   ((uint16_t)0xF040)
+
+/* SPI or I2S mode selection masks */
+#define SPI_Mode_Select      ((uint16_t)0xF7FF)
+#define I2S_Mode_Select      ((uint16_t)0x0800) 
+
+/* I2S clock source selection masks */
+#define I2S2_CLOCK_SRC       ((uint32_t)(0x00020000))
+#define I2S3_CLOCK_SRC       ((uint32_t)(0x00040000))
+#define I2S_MUL_MASK         ((uint32_t)(0x0000F000))
+#define I2S_DIV_MASK         ((uint32_t)(0x000000F0))
+
+/**
+  * @}
+  */
+
+/** @defgroup SPI_Private_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup SPI_Private_Variables
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup SPI_Private_FunctionPrototypes
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup SPI_Private_Functions
+  * @{
+  */
+
+/**
+  * @brief  Deinitializes the SPIx peripheral registers to their default
+  *         reset values (Affects also the I2Ss).
+  * @param  SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.
+  * @retval None
+  */
+void SPI_I2S_DeInit(SPI_TypeDef* SPIx)
+{
+  /* Check the parameters */
+  assert_param(IS_SPI_ALL_PERIPH(SPIx));
+
+  if (SPIx == SPI1)
+  {
+    /* Enable SPI1 reset state */
+    RCC_APB2PeriphResetCmd(RCC_APB2Periph_SPI1, ENABLE);
+    /* Release SPI1 from reset state */
+    RCC_APB2PeriphResetCmd(RCC_APB2Periph_SPI1, DISABLE);
+  }
+  else if (SPIx == SPI2)
+  {
+    /* Enable SPI2 reset state */
+    RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI2, ENABLE);
+    /* Release SPI2 from reset state */
+    RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI2, DISABLE);
+  }
+  else
+  {
+    if (SPIx == SPI3)
+    {
+      /* Enable SPI3 reset state */
+      RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI3, ENABLE);
+      /* Release SPI3 from reset state */
+      RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI3, DISABLE);
+    }
+  }
+}
+
+/**
+  * @brief  Initializes the SPIx peripheral according to the specified 
+  *         parameters in the SPI_InitStruct.
+  * @param  SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.
+  * @param  SPI_InitStruct: pointer to a SPI_InitTypeDef structure that
+  *         contains the configuration information for the specified SPI peripheral.
+  * @retval None
+  */
+void SPI_Init(SPI_TypeDef* SPIx, SPI_InitTypeDef* SPI_InitStruct)
+{
+  uint16_t tmpreg = 0;
+  
+  /* check the parameters */
+  assert_param(IS_SPI_ALL_PERIPH(SPIx));   
+  
+  /* Check the SPI parameters */
+  assert_param(IS_SPI_DIRECTION_MODE(SPI_InitStruct->SPI_Direction));
+  assert_param(IS_SPI_MODE(SPI_InitStruct->SPI_Mode));
+  assert_param(IS_SPI_DATASIZE(SPI_InitStruct->SPI_DataSize));
+  assert_param(IS_SPI_CPOL(SPI_InitStruct->SPI_CPOL));
+  assert_param(IS_SPI_CPHA(SPI_InitStruct->SPI_CPHA));
+  assert_param(IS_SPI_NSS(SPI_InitStruct->SPI_NSS));
+  assert_param(IS_SPI_BAUDRATE_PRESCALER(SPI_InitStruct->SPI_BaudRatePrescaler));
+  assert_param(IS_SPI_FIRST_BIT(SPI_InitStruct->SPI_FirstBit));
+  assert_param(IS_SPI_CRC_POLYNOMIAL(SPI_InitStruct->SPI_CRCPolynomial));
+
+/*---------------------------- SPIx CR1 Configuration ------------------------*/
+  /* Get the SPIx CR1 value */
+  tmpreg = SPIx->CR1;
+  /* Clear BIDIMode, BIDIOE, RxONLY, SSM, SSI, LSBFirst, BR, MSTR, CPOL and CPHA bits */
+  tmpreg &= CR1_CLEAR_Mask;
+  /* Configure SPIx: direction, NSS management, first transmitted bit, BaudRate prescaler
+     master/salve mode, CPOL and CPHA */
+  /* Set BIDImode, BIDIOE and RxONLY bits according to SPI_Direction value */
+  /* Set SSM, SSI and MSTR bits according to SPI_Mode and SPI_NSS values */
+  /* Set LSBFirst bit according to SPI_FirstBit value */
+  /* Set BR bits according to SPI_BaudRatePrescaler value */
+  /* Set CPOL bit according to SPI_CPOL value */
+  /* Set CPHA bit according to SPI_CPHA value */
+  tmpreg |= (uint16_t)((uint32_t)SPI_InitStruct->SPI_Direction | SPI_InitStruct->SPI_Mode |
+                  SPI_InitStruct->SPI_DataSize | SPI_InitStruct->SPI_CPOL |  
+                  SPI_InitStruct->SPI_CPHA | SPI_InitStruct->SPI_NSS |  
+                  SPI_InitStruct->SPI_BaudRatePrescaler | SPI_InitStruct->SPI_FirstBit);
+  /* Write to SPIx CR1 */
+  SPIx->CR1 = tmpreg;
+  
+  /* Activate the SPI mode (Reset I2SMOD bit in I2SCFGR register) */
+  SPIx->I2SCFGR &= SPI_Mode_Select;		
+
+/*---------------------------- SPIx CRCPOLY Configuration --------------------*/
+  /* Write to SPIx CRCPOLY */
+  SPIx->CRCPR = SPI_InitStruct->SPI_CRCPolynomial;
+}
+
+/**
+  * @brief  Initializes the SPIx peripheral according to the specified 
+  *         parameters in the I2S_InitStruct.
+  * @param  SPIx: where x can be  2 or 3 to select the SPI peripheral
+  *         (configured in I2S mode).
+  * @param  I2S_InitStruct: pointer to an I2S_InitTypeDef structure that
+  *         contains the configuration information for the specified SPI peripheral
+  *         configured in I2S mode.
+  * @note
+  *  The function calculates the optimal prescaler needed to obtain the most 
+  *  accurate audio frequency (depending on the I2S clock source, the PLL values 
+  *  and the product configuration). But in case the prescaler value is greater 
+  *  than 511, the default value (0x02) will be configured instead.  *   
+  * @retval None
+  */
+void I2S_Init(SPI_TypeDef* SPIx, I2S_InitTypeDef* I2S_InitStruct)
+{
+  uint16_t tmpreg = 0, i2sdiv = 2, i2sodd = 0, packetlength = 1;
+  uint32_t tmp = 0;
+  RCC_ClocksTypeDef RCC_Clocks;
+  uint32_t sourceclock = 0;
+  
+  /* Check the I2S parameters */
+  assert_param(IS_SPI_23_PERIPH(SPIx));
+  assert_param(IS_I2S_MODE(I2S_InitStruct->I2S_Mode));
+  assert_param(IS_I2S_STANDARD(I2S_InitStruct->I2S_Standard));
+  assert_param(IS_I2S_DATA_FORMAT(I2S_InitStruct->I2S_DataFormat));
+  assert_param(IS_I2S_MCLK_OUTPUT(I2S_InitStruct->I2S_MCLKOutput));
+  assert_param(IS_I2S_AUDIO_FREQ(I2S_InitStruct->I2S_AudioFreq));
+  assert_param(IS_I2S_CPOL(I2S_InitStruct->I2S_CPOL));  
+
+/*----------------------- SPIx I2SCFGR & I2SPR Configuration -----------------*/
+  /* Clear I2SMOD, I2SE, I2SCFG, PCMSYNC, I2SSTD, CKPOL, DATLEN and CHLEN bits */
+  SPIx->I2SCFGR &= I2SCFGR_CLEAR_Mask; 
+  SPIx->I2SPR = 0x0002;
+  
+  /* Get the I2SCFGR register value */
+  tmpreg = SPIx->I2SCFGR;
+  
+  /* If the default value has to be written, reinitialize i2sdiv and i2sodd*/
+  if(I2S_InitStruct->I2S_AudioFreq == I2S_AudioFreq_Default)
+  {
+    i2sodd = (uint16_t)0;
+    i2sdiv = (uint16_t)2;   
+  }
+  /* If the requested audio frequency is not the default, compute the prescaler */
+  else
+  {
+    /* Check the frame length (For the Prescaler computing) */
+    if(I2S_InitStruct->I2S_DataFormat == I2S_DataFormat_16b)
+    {
+      /* Packet length is 16 bits */
+      packetlength = 1;
+    }
+    else
+    {
+      /* Packet length is 32 bits */
+      packetlength = 2;
+    }
+
+    /* Get the I2S clock source mask depending on the peripheral number */
+    if(((uint32_t)SPIx) == SPI2_BASE)
+    {
+      /* The mask is relative to I2S2 */
+      tmp = I2S2_CLOCK_SRC;
+    }
+    else 
+    {
+      /* The mask is relative to I2S3 */      
+      tmp = I2S3_CLOCK_SRC;
+    }
+
+    /* Check the I2S clock source configuration depending on the Device:
+       Only Connectivity line devices have the PLL3 VCO clock */
+#ifdef STM32F10X_CL
+    if((RCC->CFGR2 & tmp) != 0)
+    {
+      /* Get the configuration bits of RCC PLL3 multiplier */
+      tmp = (uint32_t)((RCC->CFGR2 & I2S_MUL_MASK) >> 12);
+
+      /* Get the value of the PLL3 multiplier */      
+      if((tmp > 5) && (tmp < 15))
+      {
+        /* Multiplier is between 8 and 14 (value 15 is forbidden) */
+        tmp += 2;
+      }
+      else
+      {
+        if (tmp == 15)
+        {
+          /* Multiplier is 20 */
+          tmp = 20;
+        }
+      }      
+      /* Get the PREDIV2 value */
+      sourceclock = (uint32_t)(((RCC->CFGR2 & I2S_DIV_MASK) >> 4) + 1);
+      
+      /* Calculate the Source Clock frequency based on PLL3 and PREDIV2 values */
+      sourceclock = (uint32_t) ((HSE_Value / sourceclock) * tmp * 2); 
+    }
+    else
+    {
+      /* I2S Clock source is System clock: Get System Clock frequency */
+      RCC_GetClocksFreq(&RCC_Clocks);      
+      
+      /* Get the source clock value: based on System Clock value */
+      sourceclock = RCC_Clocks.SYSCLK_Frequency;
+    }        
+#else /* STM32F10X_HD */
+    /* I2S Clock source is System clock: Get System Clock frequency */
+    RCC_GetClocksFreq(&RCC_Clocks);      
+      
+    /* Get the source clock value: based on System Clock value */
+    sourceclock = RCC_Clocks.SYSCLK_Frequency;    
+#endif /* STM32F10X_CL */    
+
+    /* Compute the Real divider depending on the MCLK output state with a floating point */
+    if(I2S_InitStruct->I2S_MCLKOutput == I2S_MCLKOutput_Enable)
+    {
+      /* MCLK output is enabled */
+      tmp = (uint16_t)(((((sourceclock / 256) * 10) / I2S_InitStruct->I2S_AudioFreq)) + 5);
+    }
+    else
+    {
+      /* MCLK output is disabled */
+      tmp = (uint16_t)(((((sourceclock / (32 * packetlength)) *10 ) / I2S_InitStruct->I2S_AudioFreq)) + 5);
+    }
+    
+    /* Remove the floating point */
+    tmp = tmp / 10;  
+      
+    /* Check the parity of the divider */
+    i2sodd = (uint16_t)(tmp & (uint16_t)0x0001);
+   
+    /* Compute the i2sdiv prescaler */
+    i2sdiv = (uint16_t)((tmp - i2sodd) / 2);
+   
+    /* Get the Mask for the Odd bit (SPI_I2SPR[8]) register */
+    i2sodd = (uint16_t) (i2sodd << 8);
+  }
+  
+  /* Test if the divider is 1 or 0 or greater than 0xFF */
+  if ((i2sdiv < 2) || (i2sdiv > 0xFF))
+  {
+    /* Set the default values */
+    i2sdiv = 2;
+    i2sodd = 0;
+  }
+
+  /* Write to SPIx I2SPR register the computed value */
+  SPIx->I2SPR = (uint16_t)(i2sdiv | (uint16_t)(i2sodd | (uint16_t)I2S_InitStruct->I2S_MCLKOutput));  
+ 
+  /* Configure the I2S with the SPI_InitStruct values */
+  tmpreg |= (uint16_t)(I2S_Mode_Select | (uint16_t)(I2S_InitStruct->I2S_Mode | \
+                  (uint16_t)(I2S_InitStruct->I2S_Standard | (uint16_t)(I2S_InitStruct->I2S_DataFormat | \
+                  (uint16_t)I2S_InitStruct->I2S_CPOL))));
+ 
+  /* Write to SPIx I2SCFGR */  
+  SPIx->I2SCFGR = tmpreg;   
+}
+
+/**
+  * @brief  Fills each SPI_InitStruct member with its default value.
+  * @param  SPI_InitStruct : pointer to a SPI_InitTypeDef structure which will be initialized.
+  * @retval None
+  */
+void SPI_StructInit(SPI_InitTypeDef* SPI_InitStruct)
+{
+/*--------------- Reset SPI init structure parameters values -----------------*/
+  /* Initialize the SPI_Direction member */
+  SPI_InitStruct->SPI_Direction = SPI_Direction_2Lines_FullDuplex;
+  /* initialize the SPI_Mode member */
+  SPI_InitStruct->SPI_Mode = SPI_Mode_Slave;
+  /* initialize the SPI_DataSize member */
+  SPI_InitStruct->SPI_DataSize = SPI_DataSize_8b;
+  /* Initialize the SPI_CPOL member */
+  SPI_InitStruct->SPI_CPOL = SPI_CPOL_Low;
+  /* Initialize the SPI_CPHA member */
+  SPI_InitStruct->SPI_CPHA = SPI_CPHA_1Edge;
+  /* Initialize the SPI_NSS member */
+  SPI_InitStruct->SPI_NSS = SPI_NSS_Hard;
+  /* Initialize the SPI_BaudRatePrescaler member */
+  SPI_InitStruct->SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_2;
+  /* Initialize the SPI_FirstBit member */
+  SPI_InitStruct->SPI_FirstBit = SPI_FirstBit_MSB;
+  /* Initialize the SPI_CRCPolynomial member */
+  SPI_InitStruct->SPI_CRCPolynomial = 7;
+}
+
+/**
+  * @brief  Fills each I2S_InitStruct member with its default value.
+  * @param  I2S_InitStruct : pointer to a I2S_InitTypeDef structure which will be initialized.
+  * @retval None
+  */
+void I2S_StructInit(I2S_InitTypeDef* I2S_InitStruct)
+{
+/*--------------- Reset I2S init structure parameters values -----------------*/
+  /* Initialize the I2S_Mode member */
+  I2S_InitStruct->I2S_Mode = I2S_Mode_SlaveTx;
+  
+  /* Initialize the I2S_Standard member */
+  I2S_InitStruct->I2S_Standard = I2S_Standard_Phillips;
+  
+  /* Initialize the I2S_DataFormat member */
+  I2S_InitStruct->I2S_DataFormat = I2S_DataFormat_16b;
+  
+  /* Initialize the I2S_MCLKOutput member */
+  I2S_InitStruct->I2S_MCLKOutput = I2S_MCLKOutput_Disable;
+  
+  /* Initialize the I2S_AudioFreq member */
+  I2S_InitStruct->I2S_AudioFreq = I2S_AudioFreq_Default;
+  
+  /* Initialize the I2S_CPOL member */
+  I2S_InitStruct->I2S_CPOL = I2S_CPOL_Low;
+}
+
+/**
+  * @brief  Enables or disables the specified SPI peripheral.
+  * @param  SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.
+  * @param  NewState: new state of the SPIx peripheral. 
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void SPI_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_SPI_ALL_PERIPH(SPIx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  if (NewState != DISABLE)
+  {
+    /* Enable the selected SPI peripheral */
+    SPIx->CR1 |= CR1_SPE_Set;
+  }
+  else
+  {
+    /* Disable the selected SPI peripheral */
+    SPIx->CR1 &= CR1_SPE_Reset;
+  }
+}
+
+/**
+  * @brief  Enables or disables the specified SPI peripheral (in I2S mode).
+  * @param  SPIx: where x can be 2 or 3 to select the SPI peripheral.
+  * @param  NewState: new state of the SPIx peripheral. 
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void I2S_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_SPI_23_PERIPH(SPIx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  if (NewState != DISABLE)
+  {
+    /* Enable the selected SPI peripheral (in I2S mode) */
+    SPIx->I2SCFGR |= I2SCFGR_I2SE_Set;
+  }
+  else
+  {
+    /* Disable the selected SPI peripheral (in I2S mode) */
+    SPIx->I2SCFGR &= I2SCFGR_I2SE_Reset;
+  }
+}
+
+/**
+  * @brief  Enables or disables the specified SPI/I2S interrupts.
+  * @param  SPIx: where x can be
+  *   - 1, 2 or 3 in SPI mode 
+  *   - 2 or 3 in I2S mode
+  * @param  SPI_I2S_IT: specifies the SPI/I2S interrupt source to be enabled or disabled. 
+  *   This parameter can be one of the following values:
+  *     @arg SPI_I2S_IT_TXE: Tx buffer empty interrupt mask
+  *     @arg SPI_I2S_IT_RXNE: Rx buffer not empty interrupt mask
+  *     @arg SPI_I2S_IT_ERR: Error interrupt mask
+  * @param  NewState: new state of the specified SPI/I2S interrupt.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void SPI_I2S_ITConfig(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT, FunctionalState NewState)
+{
+  uint16_t itpos = 0, itmask = 0 ;
+  /* Check the parameters */
+  assert_param(IS_SPI_ALL_PERIPH(SPIx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  assert_param(IS_SPI_I2S_CONFIG_IT(SPI_I2S_IT));
+
+  /* Get the SPI/I2S IT index */
+  itpos = SPI_I2S_IT >> 4;
+
+  /* Set the IT mask */
+  itmask = (uint16_t)1 << (uint16_t)itpos;
+
+  if (NewState != DISABLE)
+  {
+    /* Enable the selected SPI/I2S interrupt */
+    SPIx->CR2 |= itmask;
+  }
+  else
+  {
+    /* Disable the selected SPI/I2S interrupt */
+    SPIx->CR2 &= (uint16_t)~itmask;
+  }
+}
+
+/**
+  * @brief  Enables or disables the SPIx/I2Sx DMA interface.
+  * @param  SPIx: where x can be
+  *   - 1, 2 or 3 in SPI mode 
+  *   - 2 or 3 in I2S mode
+  * @param  SPI_I2S_DMAReq: specifies the SPI/I2S DMA transfer request to be enabled or disabled. 
+  *   This parameter can be any combination of the following values:
+  *     @arg SPI_I2S_DMAReq_Tx: Tx buffer DMA transfer request
+  *     @arg SPI_I2S_DMAReq_Rx: Rx buffer DMA transfer request
+  * @param  NewState: new state of the selected SPI/I2S DMA transfer request.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void SPI_I2S_DMACmd(SPI_TypeDef* SPIx, uint16_t SPI_I2S_DMAReq, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_SPI_ALL_PERIPH(SPIx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  assert_param(IS_SPI_I2S_DMAREQ(SPI_I2S_DMAReq));
+  if (NewState != DISABLE)
+  {
+    /* Enable the selected SPI/I2S DMA requests */
+    SPIx->CR2 |= SPI_I2S_DMAReq;
+  }
+  else
+  {
+    /* Disable the selected SPI/I2S DMA requests */
+    SPIx->CR2 &= (uint16_t)~SPI_I2S_DMAReq;
+  }
+}
+
+/**
+  * @brief  Transmits a Data through the SPIx/I2Sx peripheral.
+  * @param  SPIx: where x can be
+  *   - 1, 2 or 3 in SPI mode 
+  *   - 2 or 3 in I2S mode
+  * @param  Data : Data to be transmitted.
+  * @retval None
+  */
+void SPI_I2S_SendData(SPI_TypeDef* SPIx, uint16_t Data)
+{
+  /* Check the parameters */
+  assert_param(IS_SPI_ALL_PERIPH(SPIx));
+  
+  /* Write in the DR register the data to be sent */
+  SPIx->DR = Data;
+}
+
+/**
+  * @brief  Returns the most recent received data by the SPIx/I2Sx peripheral. 
+  * @param  SPIx: where x can be
+  *   - 1, 2 or 3 in SPI mode 
+  *   - 2 or 3 in I2S mode
+  * @retval The value of the received data.
+  */
+uint16_t SPI_I2S_ReceiveData(SPI_TypeDef* SPIx)
+{
+  /* Check the parameters */
+  assert_param(IS_SPI_ALL_PERIPH(SPIx));
+  
+  /* Return the data in the DR register */
+  return SPIx->DR;
+}
+
+/**
+  * @brief  Configures internally by software the NSS pin for the selected SPI.
+  * @param  SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.
+  * @param  SPI_NSSInternalSoft: specifies the SPI NSS internal state.
+  *   This parameter can be one of the following values:
+  *     @arg SPI_NSSInternalSoft_Set: Set NSS pin internally
+  *     @arg SPI_NSSInternalSoft_Reset: Reset NSS pin internally
+  * @retval None
+  */
+void SPI_NSSInternalSoftwareConfig(SPI_TypeDef* SPIx, uint16_t SPI_NSSInternalSoft)
+{
+  /* Check the parameters */
+  assert_param(IS_SPI_ALL_PERIPH(SPIx));
+  assert_param(IS_SPI_NSS_INTERNAL(SPI_NSSInternalSoft));
+  if (SPI_NSSInternalSoft != SPI_NSSInternalSoft_Reset)
+  {
+    /* Set NSS pin internally by software */
+    SPIx->CR1 |= SPI_NSSInternalSoft_Set;
+  }
+  else
+  {
+    /* Reset NSS pin internally by software */
+    SPIx->CR1 &= SPI_NSSInternalSoft_Reset;
+  }
+}
+
+/**
+  * @brief  Enables or disables the SS output for the selected SPI.
+  * @param  SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.
+  * @param  NewState: new state of the SPIx SS output. 
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void SPI_SSOutputCmd(SPI_TypeDef* SPIx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_SPI_ALL_PERIPH(SPIx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  if (NewState != DISABLE)
+  {
+    /* Enable the selected SPI SS output */
+    SPIx->CR2 |= CR2_SSOE_Set;
+  }
+  else
+  {
+    /* Disable the selected SPI SS output */
+    SPIx->CR2 &= CR2_SSOE_Reset;
+  }
+}
+
+/**
+  * @brief  Configures the data size for the selected SPI.
+  * @param  SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.
+  * @param  SPI_DataSize: specifies the SPI data size.
+  *   This parameter can be one of the following values:
+  *     @arg SPI_DataSize_16b: Set data frame format to 16bit
+  *     @arg SPI_DataSize_8b: Set data frame format to 8bit
+  * @retval None
+  */
+void SPI_DataSizeConfig(SPI_TypeDef* SPIx, uint16_t SPI_DataSize)
+{
+  /* Check the parameters */
+  assert_param(IS_SPI_ALL_PERIPH(SPIx));
+  assert_param(IS_SPI_DATASIZE(SPI_DataSize));
+  /* Clear DFF bit */
+  SPIx->CR1 &= (uint16_t)~SPI_DataSize_16b;
+  /* Set new DFF bit value */
+  SPIx->CR1 |= SPI_DataSize;
+}
+
+/**
+  * @brief  Transmit the SPIx CRC value.
+  * @param  SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.
+  * @retval None
+  */
+void SPI_TransmitCRC(SPI_TypeDef* SPIx)
+{
+  /* Check the parameters */
+  assert_param(IS_SPI_ALL_PERIPH(SPIx));
+  
+  /* Enable the selected SPI CRC transmission */
+  SPIx->CR1 |= CR1_CRCNext_Set;
+}
+
+/**
+  * @brief  Enables or disables the CRC value calculation of the transferred bytes.
+  * @param  SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.
+  * @param  NewState: new state of the SPIx CRC value calculation.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void SPI_CalculateCRC(SPI_TypeDef* SPIx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_SPI_ALL_PERIPH(SPIx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  if (NewState != DISABLE)
+  {
+    /* Enable the selected SPI CRC calculation */
+    SPIx->CR1 |= CR1_CRCEN_Set;
+  }
+  else
+  {
+    /* Disable the selected SPI CRC calculation */
+    SPIx->CR1 &= CR1_CRCEN_Reset;
+  }
+}
+
+/**
+  * @brief  Returns the transmit or the receive CRC register value for the specified SPI.
+  * @param  SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.
+  * @param  SPI_CRC: specifies the CRC register to be read.
+  *   This parameter can be one of the following values:
+  *     @arg SPI_CRC_Tx: Selects Tx CRC register
+  *     @arg SPI_CRC_Rx: Selects Rx CRC register
+  * @retval The selected CRC register value..
+  */
+uint16_t SPI_GetCRC(SPI_TypeDef* SPIx, uint8_t SPI_CRC)
+{
+  uint16_t crcreg = 0;
+  /* Check the parameters */
+  assert_param(IS_SPI_ALL_PERIPH(SPIx));
+  assert_param(IS_SPI_CRC(SPI_CRC));
+  if (SPI_CRC != SPI_CRC_Rx)
+  {
+    /* Get the Tx CRC register */
+    crcreg = SPIx->TXCRCR;
+  }
+  else
+  {
+    /* Get the Rx CRC register */
+    crcreg = SPIx->RXCRCR;
+  }
+  /* Return the selected CRC register */
+  return crcreg;
+}
+
+/**
+  * @brief  Returns the CRC Polynomial register value for the specified SPI.
+  * @param  SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.
+  * @retval The CRC Polynomial register value.
+  */
+uint16_t SPI_GetCRCPolynomial(SPI_TypeDef* SPIx)
+{
+  /* Check the parameters */
+  assert_param(IS_SPI_ALL_PERIPH(SPIx));
+  
+  /* Return the CRC polynomial register */
+  return SPIx->CRCPR;
+}
+
+/**
+  * @brief  Selects the data transfer direction in bi-directional mode for the specified SPI.
+  * @param  SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.
+  * @param  SPI_Direction: specifies the data transfer direction in bi-directional mode. 
+  *   This parameter can be one of the following values:
+  *     @arg SPI_Direction_Tx: Selects Tx transmission direction
+  *     @arg SPI_Direction_Rx: Selects Rx receive direction
+  * @retval None
+  */
+void SPI_BiDirectionalLineConfig(SPI_TypeDef* SPIx, uint16_t SPI_Direction)
+{
+  /* Check the parameters */
+  assert_param(IS_SPI_ALL_PERIPH(SPIx));
+  assert_param(IS_SPI_DIRECTION(SPI_Direction));
+  if (SPI_Direction == SPI_Direction_Tx)
+  {
+    /* Set the Tx only mode */
+    SPIx->CR1 |= SPI_Direction_Tx;
+  }
+  else
+  {
+    /* Set the Rx only mode */
+    SPIx->CR1 &= SPI_Direction_Rx;
+  }
+}
+
+/**
+  * @brief  Checks whether the specified SPI/I2S flag is set or not.
+  * @param  SPIx: where x can be
+  *   - 1, 2 or 3 in SPI mode 
+  *   - 2 or 3 in I2S mode
+  * @param  SPI_I2S_FLAG: specifies the SPI/I2S flag to check. 
+  *   This parameter can be one of the following values:
+  *     @arg SPI_I2S_FLAG_TXE: Transmit buffer empty flag.
+  *     @arg SPI_I2S_FLAG_RXNE: Receive buffer not empty flag.
+  *     @arg SPI_I2S_FLAG_BSY: Busy flag.
+  *     @arg SPI_I2S_FLAG_OVR: Overrun flag.
+  *     @arg SPI_FLAG_MODF: Mode Fault flag.
+  *     @arg SPI_FLAG_CRCERR: CRC Error flag.
+  *     @arg I2S_FLAG_UDR: Underrun Error flag.
+  *     @arg I2S_FLAG_CHSIDE: Channel Side flag.
+  * @retval The new state of SPI_I2S_FLAG (SET or RESET).
+  */
+FlagStatus SPI_I2S_GetFlagStatus(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG)
+{
+  FlagStatus bitstatus = RESET;
+  /* Check the parameters */
+  assert_param(IS_SPI_ALL_PERIPH(SPIx));
+  assert_param(IS_SPI_I2S_GET_FLAG(SPI_I2S_FLAG));
+  /* Check the status of the specified SPI/I2S flag */
+  if ((SPIx->SR & SPI_I2S_FLAG) != (uint16_t)RESET)
+  {
+    /* SPI_I2S_FLAG is set */
+    bitstatus = SET;
+  }
+  else
+  {
+    /* SPI_I2S_FLAG is reset */
+    bitstatus = RESET;
+  }
+  /* Return the SPI_I2S_FLAG status */
+  return  bitstatus;
+}
+
+/**
+  * @brief  Clears the SPIx CRC Error (CRCERR) flag.
+  * @param  SPIx: where x can be
+  *   - 1, 2 or 3 in SPI mode 
+  * @param  SPI_I2S_FLAG: specifies the SPI flag to clear. 
+  *   This function clears only CRCERR flag.
+  * @note
+  *   - OVR (OverRun error) flag is cleared by software sequence: a read 
+  *     operation to SPI_DR register (SPI_I2S_ReceiveData()) followed by a read 
+  *     operation to SPI_SR register (SPI_I2S_GetFlagStatus()).
+  *   - UDR (UnderRun error) flag is cleared by a read operation to 
+  *     SPI_SR register (SPI_I2S_GetFlagStatus()).
+  *   - MODF (Mode Fault) flag is cleared by software sequence: a read/write 
+  *     operation to SPI_SR register (SPI_I2S_GetFlagStatus()) followed by a 
+  *     write operation to SPI_CR1 register (SPI_Cmd() to enable the SPI).
+  * @retval None
+  */
+void SPI_I2S_ClearFlag(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG)
+{
+  /* Check the parameters */
+  assert_param(IS_SPI_ALL_PERIPH(SPIx));
+  assert_param(IS_SPI_I2S_CLEAR_FLAG(SPI_I2S_FLAG));
+    
+    /* Clear the selected SPI CRC Error (CRCERR) flag */
+    SPIx->SR = (uint16_t)~SPI_I2S_FLAG;
+}
+
+/**
+  * @brief  Checks whether the specified SPI/I2S interrupt has occurred or not.
+  * @param  SPIx: where x can be
+  *   - 1, 2 or 3 in SPI mode 
+  *   - 2 or 3 in I2S mode
+  * @param  SPI_I2S_IT: specifies the SPI/I2S interrupt source to check. 
+  *   This parameter can be one of the following values:
+  *     @arg SPI_I2S_IT_TXE: Transmit buffer empty interrupt.
+  *     @arg SPI_I2S_IT_RXNE: Receive buffer not empty interrupt.
+  *     @arg SPI_I2S_IT_OVR: Overrun interrupt.
+  *     @arg SPI_IT_MODF: Mode Fault interrupt.
+  *     @arg SPI_IT_CRCERR: CRC Error interrupt.
+  *     @arg I2S_IT_UDR: Underrun Error interrupt.
+  * @retval The new state of SPI_I2S_IT (SET or RESET).
+  */
+ITStatus SPI_I2S_GetITStatus(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT)
+{
+  ITStatus bitstatus = RESET;
+  uint16_t itpos = 0, itmask = 0, enablestatus = 0;
+
+  /* Check the parameters */
+  assert_param(IS_SPI_ALL_PERIPH(SPIx));
+  assert_param(IS_SPI_I2S_GET_IT(SPI_I2S_IT));
+
+  /* Get the SPI/I2S IT index */
+  itpos = 0x01 << (SPI_I2S_IT & 0x0F);
+
+  /* Get the SPI/I2S IT mask */
+  itmask = SPI_I2S_IT >> 4;
+
+  /* Set the IT mask */
+  itmask = 0x01 << itmask;
+
+  /* Get the SPI_I2S_IT enable bit status */
+  enablestatus = (SPIx->CR2 & itmask) ;
+
+  /* Check the status of the specified SPI/I2S interrupt */
+  if (((SPIx->SR & itpos) != (uint16_t)RESET) && enablestatus)
+  {
+    /* SPI_I2S_IT is set */
+    bitstatus = SET;
+  }
+  else
+  {
+    /* SPI_I2S_IT is reset */
+    bitstatus = RESET;
+  }
+  /* Return the SPI_I2S_IT status */
+  return bitstatus;
+}
+
+/**
+  * @brief  Clears the SPIx CRC Error (CRCERR) interrupt pending bit.
+  * @param  SPIx: where x can be
+  *   - 1, 2 or 3 in SPI mode 
+  * @param  SPI_I2S_IT: specifies the SPI interrupt pending bit to clear.
+  *   This function clears only CRCERR interrupt pending bit.   
+  * @note
+  *   - OVR (OverRun Error) interrupt pending bit is cleared by software 
+  *     sequence: a read operation to SPI_DR register (SPI_I2S_ReceiveData()) 
+  *     followed by a read operation to SPI_SR register (SPI_I2S_GetITStatus()).
+  *   - UDR (UnderRun Error) interrupt pending bit is cleared by a read 
+  *     operation to SPI_SR register (SPI_I2S_GetITStatus()).
+  *   - MODF (Mode Fault) interrupt pending bit is cleared by software sequence:
+  *     a read/write operation to SPI_SR register (SPI_I2S_GetITStatus()) 
+  *     followed by a write operation to SPI_CR1 register (SPI_Cmd() to enable 
+  *     the SPI).
+  * @retval None
+  */
+void SPI_I2S_ClearITPendingBit(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT)
+{
+  uint16_t itpos = 0;
+  /* Check the parameters */
+  assert_param(IS_SPI_ALL_PERIPH(SPIx));
+  assert_param(IS_SPI_I2S_CLEAR_IT(SPI_I2S_IT));
+
+  /* Get the SPI IT index */
+  itpos = 0x01 << (SPI_I2S_IT & 0x0F);
+
+  /* Clear the selected SPI CRC Error (CRCERR) interrupt pending bit */
+  SPIx->SR = (uint16_t)~itpos;
+}
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/STM32_4路称重_Git提交精简工程/src/STM32F10x_FWLib/src/stm32f10x_tim.c b/STM32_4路称重_Git提交精简工程/src/STM32F10x_FWLib/src/stm32f10x_tim.c
new file mode 100755
index 0000000..81c8484
--- /dev/null
+++ b/STM32_4路称重_Git提交精简工程/src/STM32F10x_FWLib/src/stm32f10x_tim.c
@@ -0,0 +1,2890 @@
+/**
+  ******************************************************************************
+  * @file    stm32f10x_tim.c
+  * @author  MCD Application Team
+  * @version V3.5.0
+  * @date    11-March-2011
+  * @brief   This file provides all the TIM firmware functions.
+  ******************************************************************************
+  * @attention
+  *
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+  *
+  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x_tim.h"
+#include "stm32f10x_rcc.h"
+
+/** @addtogroup STM32F10x_StdPeriph_Driver
+  * @{
+  */
+
+/** @defgroup TIM 
+  * @brief TIM driver modules
+  * @{
+  */
+
+/** @defgroup TIM_Private_TypesDefinitions
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Private_Defines
+  * @{
+  */
+
+/* ---------------------- TIM registers bit mask ------------------------ */
+#define SMCR_ETR_Mask               ((uint16_t)0x00FF) 
+#define CCMR_Offset                 ((uint16_t)0x0018)
+#define CCER_CCE_Set                ((uint16_t)0x0001)  
+#define	CCER_CCNE_Set               ((uint16_t)0x0004) 
+
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Private_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Private_Variables
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Private_FunctionPrototypes
+  * @{
+  */
+
+static void TI1_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
+                       uint16_t TIM_ICFilter);
+static void TI2_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
+                       uint16_t TIM_ICFilter);
+static void TI3_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
+                       uint16_t TIM_ICFilter);
+static void TI4_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
+                       uint16_t TIM_ICFilter);
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Private_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Private_Variables
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Private_FunctionPrototypes
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Private_Functions
+  * @{
+  */
+
+/**
+  * @brief  Deinitializes the TIMx peripheral registers to their default reset values.
+  * @param  TIMx: where x can be 1 to 17 to select the TIM peripheral.
+  * @retval None
+  */
+void TIM_DeInit(TIM_TypeDef* TIMx)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_ALL_PERIPH(TIMx)); 
+ 
+  if (TIMx == TIM1)
+  {
+    RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM1, ENABLE);
+    RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM1, DISABLE);  
+  }     
+  else if (TIMx == TIM2)
+  {
+    RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM2, ENABLE);
+    RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM2, DISABLE);
+  }
+  else if (TIMx == TIM3)
+  {
+    RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM3, ENABLE);
+    RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM3, DISABLE);
+  }
+  else if (TIMx == TIM4)
+  {
+    RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM4, ENABLE);
+    RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM4, DISABLE);
+  } 
+  else if (TIMx == TIM5)
+  {
+    RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM5, ENABLE);
+    RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM5, DISABLE);
+  } 
+  else if (TIMx == TIM6)
+  {
+    RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM6, ENABLE);
+    RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM6, DISABLE);
+  } 
+  else if (TIMx == TIM7)
+  {
+    RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM7, ENABLE);
+    RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM7, DISABLE);
+  } 
+  else if (TIMx == TIM8)
+  {
+    RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM8, ENABLE);
+    RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM8, DISABLE);
+  }
+  else if (TIMx == TIM9)
+  {      
+    RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM9, ENABLE);
+    RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM9, DISABLE);  
+   }  
+  else if (TIMx == TIM10)
+  {      
+    RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM10, ENABLE);
+    RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM10, DISABLE);  
+  }  
+  else if (TIMx == TIM11) 
+  {     
+    RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM11, ENABLE);
+    RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM11, DISABLE);  
+  }  
+  else if (TIMx == TIM12)
+  {      
+    RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM12, ENABLE);
+    RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM12, DISABLE);  
+  }  
+  else if (TIMx == TIM13) 
+  {       
+    RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM13, ENABLE);
+    RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM13, DISABLE);  
+  }
+  else if (TIMx == TIM14) 
+  {       
+    RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM14, ENABLE);
+    RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM14, DISABLE);  
+  }        
+  else if (TIMx == TIM15)
+  {
+    RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM15, ENABLE);
+    RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM15, DISABLE);
+  } 
+  else if (TIMx == TIM16)
+  {
+    RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM16, ENABLE);
+    RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM16, DISABLE);
+  } 
+  else
+  {
+    if (TIMx == TIM17)
+    {
+      RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM17, ENABLE);
+      RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM17, DISABLE);
+    }  
+  }
+}
+
+/**
+  * @brief  Initializes the TIMx Time Base Unit peripheral according to 
+  *         the specified parameters in the TIM_TimeBaseInitStruct.
+  * @param  TIMx: where x can be 1 to 17 to select the TIM peripheral.
+  * @param  TIM_TimeBaseInitStruct: pointer to a TIM_TimeBaseInitTypeDef
+  *         structure that contains the configuration information for the 
+  *         specified TIM peripheral.
+  * @retval None
+  */
+void TIM_TimeBaseInit(TIM_TypeDef* TIMx, TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct)
+{
+  uint16_t tmpcr1 = 0;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_ALL_PERIPH(TIMx)); 
+  assert_param(IS_TIM_COUNTER_MODE(TIM_TimeBaseInitStruct->TIM_CounterMode));
+  assert_param(IS_TIM_CKD_DIV(TIM_TimeBaseInitStruct->TIM_ClockDivision));
+
+  tmpcr1 = TIMx->CR1;  
+
+  if((TIMx == TIM1) || (TIMx == TIM8)|| (TIMx == TIM2) || (TIMx == TIM3)||
+     (TIMx == TIM4) || (TIMx == TIM5)) 
+  {
+    /* Select the Counter Mode */
+    tmpcr1 &= (uint16_t)(~((uint16_t)(TIM_CR1_DIR | TIM_CR1_CMS)));
+    tmpcr1 |= (uint32_t)TIM_TimeBaseInitStruct->TIM_CounterMode;
+  }
+ 
+  if((TIMx != TIM6) && (TIMx != TIM7))
+  {
+    /* Set the clock division */
+    tmpcr1 &= (uint16_t)(~((uint16_t)TIM_CR1_CKD));
+    tmpcr1 |= (uint32_t)TIM_TimeBaseInitStruct->TIM_ClockDivision;
+  }
+
+  TIMx->CR1 = tmpcr1;
+
+  /* Set the Autoreload value */
+  TIMx->ARR = TIM_TimeBaseInitStruct->TIM_Period ;
+ 
+  /* Set the Prescaler value */
+  TIMx->PSC = TIM_TimeBaseInitStruct->TIM_Prescaler;
+    
+  if ((TIMx == TIM1) || (TIMx == TIM8)|| (TIMx == TIM15)|| (TIMx == TIM16) || (TIMx == TIM17))  
+  {
+    /* Set the Repetition Counter value */
+    TIMx->RCR = TIM_TimeBaseInitStruct->TIM_RepetitionCounter;
+  }
+
+  /* Generate an update event to reload the Prescaler and the Repetition counter
+     values immediately */
+  TIMx->EGR = TIM_PSCReloadMode_Immediate;           
+}
+
+/**
+  * @brief  Initializes the TIMx Channel1 according to the specified
+  *         parameters in the TIM_OCInitStruct.
+  * @param  TIMx: where x can be  1 to 17 except 6 and 7 to select the TIM peripheral.
+  * @param  TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure
+  *         that contains the configuration information for the specified TIM peripheral.
+  * @retval None
+  */
+void TIM_OC1Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct)
+{
+  uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0;
+   
+  /* Check the parameters */
+  assert_param(IS_TIM_LIST8_PERIPH(TIMx));
+  assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode));
+  assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState));
+  assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity));   
+ /* Disable the Channel 1: Reset the CC1E Bit */
+  TIMx->CCER &= (uint16_t)(~(uint16_t)TIM_CCER_CC1E);
+  /* Get the TIMx CCER register value */
+  tmpccer = TIMx->CCER;
+  /* Get the TIMx CR2 register value */
+  tmpcr2 =  TIMx->CR2;
+  
+  /* Get the TIMx CCMR1 register value */
+  tmpccmrx = TIMx->CCMR1;
+    
+  /* Reset the Output Compare Mode Bits */
+  tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR1_OC1M));
+  tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR1_CC1S));
+
+  /* Select the Output Compare Mode */
+  tmpccmrx |= TIM_OCInitStruct->TIM_OCMode;
+  
+  /* Reset the Output Polarity level */
+  tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC1P));
+  /* Set the Output Compare Polarity */
+  tmpccer |= TIM_OCInitStruct->TIM_OCPolarity;
+  
+  /* Set the Output State */
+  tmpccer |= TIM_OCInitStruct->TIM_OutputState;
+    
+  if((TIMx == TIM1) || (TIMx == TIM8)|| (TIMx == TIM15)||
+     (TIMx == TIM16)|| (TIMx == TIM17))
+  {
+    assert_param(IS_TIM_OUTPUTN_STATE(TIM_OCInitStruct->TIM_OutputNState));
+    assert_param(IS_TIM_OCN_POLARITY(TIM_OCInitStruct->TIM_OCNPolarity));
+    assert_param(IS_TIM_OCNIDLE_STATE(TIM_OCInitStruct->TIM_OCNIdleState));
+    assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState));
+    
+    /* Reset the Output N Polarity level */
+    tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC1NP));
+    /* Set the Output N Polarity */
+    tmpccer |= TIM_OCInitStruct->TIM_OCNPolarity;
+    
+    /* Reset the Output N State */
+    tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC1NE));    
+    /* Set the Output N State */
+    tmpccer |= TIM_OCInitStruct->TIM_OutputNState;
+    
+    /* Reset the Output Compare and Output Compare N IDLE State */
+    tmpcr2 &= (uint16_t)(~((uint16_t)TIM_CR2_OIS1));
+    tmpcr2 &= (uint16_t)(~((uint16_t)TIM_CR2_OIS1N));
+    
+    /* Set the Output Idle state */
+    tmpcr2 |= TIM_OCInitStruct->TIM_OCIdleState;
+    /* Set the Output N Idle state */
+    tmpcr2 |= TIM_OCInitStruct->TIM_OCNIdleState;
+  }
+  /* Write to TIMx CR2 */
+  TIMx->CR2 = tmpcr2;
+  
+  /* Write to TIMx CCMR1 */
+  TIMx->CCMR1 = tmpccmrx;
+
+  /* Set the Capture Compare Register value */
+  TIMx->CCR1 = TIM_OCInitStruct->TIM_Pulse; 
+ 
+  /* Write to TIMx CCER */
+  TIMx->CCER = tmpccer;
+}
+
+/**
+  * @brief  Initializes the TIMx Channel2 according to the specified
+  *         parameters in the TIM_OCInitStruct.
+  * @param  TIMx: where x can be  1, 2, 3, 4, 5, 8, 9, 12 or 15 to select 
+  *         the TIM peripheral.
+  * @param  TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure
+  *         that contains the configuration information for the specified TIM peripheral.
+  * @retval None
+  */
+void TIM_OC2Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct)
+{
+  uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0;
+   
+  /* Check the parameters */
+  assert_param(IS_TIM_LIST6_PERIPH(TIMx)); 
+  assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode));
+  assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState));
+  assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity));   
+   /* Disable the Channel 2: Reset the CC2E Bit */
+  TIMx->CCER &= (uint16_t)(~((uint16_t)TIM_CCER_CC2E));
+  
+  /* Get the TIMx CCER register value */  
+  tmpccer = TIMx->CCER;
+  /* Get the TIMx CR2 register value */
+  tmpcr2 =  TIMx->CR2;
+  
+  /* Get the TIMx CCMR1 register value */
+  tmpccmrx = TIMx->CCMR1;
+    
+  /* Reset the Output Compare mode and Capture/Compare selection Bits */
+  tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR1_OC2M));
+  tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR1_CC2S));
+  
+  /* Select the Output Compare Mode */
+  tmpccmrx |= (uint16_t)(TIM_OCInitStruct->TIM_OCMode << 8);
+  
+  /* Reset the Output Polarity level */
+  tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC2P));
+  /* Set the Output Compare Polarity */
+  tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCPolarity << 4);
+  
+  /* Set the Output State */
+  tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputState << 4);
+    
+  if((TIMx == TIM1) || (TIMx == TIM8))
+  {
+    assert_param(IS_TIM_OUTPUTN_STATE(TIM_OCInitStruct->TIM_OutputNState));
+    assert_param(IS_TIM_OCN_POLARITY(TIM_OCInitStruct->TIM_OCNPolarity));
+    assert_param(IS_TIM_OCNIDLE_STATE(TIM_OCInitStruct->TIM_OCNIdleState));
+    assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState));
+    
+    /* Reset the Output N Polarity level */
+    tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC2NP));
+    /* Set the Output N Polarity */
+    tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCNPolarity << 4);
+    
+    /* Reset the Output N State */
+    tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC2NE));    
+    /* Set the Output N State */
+    tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputNState << 4);
+    
+    /* Reset the Output Compare and Output Compare N IDLE State */
+    tmpcr2 &= (uint16_t)(~((uint16_t)TIM_CR2_OIS2));
+    tmpcr2 &= (uint16_t)(~((uint16_t)TIM_CR2_OIS2N));
+    
+    /* Set the Output Idle state */
+    tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCIdleState << 2);
+    /* Set the Output N Idle state */
+    tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCNIdleState << 2);
+  }
+  /* Write to TIMx CR2 */
+  TIMx->CR2 = tmpcr2;
+  
+  /* Write to TIMx CCMR1 */
+  TIMx->CCMR1 = tmpccmrx;
+
+  /* Set the Capture Compare Register value */
+  TIMx->CCR2 = TIM_OCInitStruct->TIM_Pulse;
+  
+  /* Write to TIMx CCER */
+  TIMx->CCER = tmpccer;
+}
+
+/**
+  * @brief  Initializes the TIMx Channel3 according to the specified
+  *         parameters in the TIM_OCInitStruct.
+  * @param  TIMx: where x can be  1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+  * @param  TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure
+  *         that contains the configuration information for the specified TIM peripheral.
+  * @retval None
+  */
+void TIM_OC3Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct)
+{
+  uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0;
+   
+  /* Check the parameters */
+  assert_param(IS_TIM_LIST3_PERIPH(TIMx)); 
+  assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode));
+  assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState));
+  assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity));   
+  /* Disable the Channel 2: Reset the CC2E Bit */
+  TIMx->CCER &= (uint16_t)(~((uint16_t)TIM_CCER_CC3E));
+  
+  /* Get the TIMx CCER register value */
+  tmpccer = TIMx->CCER;
+  /* Get the TIMx CR2 register value */
+  tmpcr2 =  TIMx->CR2;
+  
+  /* Get the TIMx CCMR2 register value */
+  tmpccmrx = TIMx->CCMR2;
+    
+  /* Reset the Output Compare mode and Capture/Compare selection Bits */
+  tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR2_OC3M));
+  tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR2_CC3S));  
+  /* Select the Output Compare Mode */
+  tmpccmrx |= TIM_OCInitStruct->TIM_OCMode;
+  
+  /* Reset the Output Polarity level */
+  tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC3P));
+  /* Set the Output Compare Polarity */
+  tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCPolarity << 8);
+  
+  /* Set the Output State */
+  tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputState << 8);
+    
+  if((TIMx == TIM1) || (TIMx == TIM8))
+  {
+    assert_param(IS_TIM_OUTPUTN_STATE(TIM_OCInitStruct->TIM_OutputNState));
+    assert_param(IS_TIM_OCN_POLARITY(TIM_OCInitStruct->TIM_OCNPolarity));
+    assert_param(IS_TIM_OCNIDLE_STATE(TIM_OCInitStruct->TIM_OCNIdleState));
+    assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState));
+    
+    /* Reset the Output N Polarity level */
+    tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC3NP));
+    /* Set the Output N Polarity */
+    tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCNPolarity << 8);
+    /* Reset the Output N State */
+    tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC3NE));
+    
+    /* Set the Output N State */
+    tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputNState << 8);
+    /* Reset the Output Compare and Output Compare N IDLE State */
+    tmpcr2 &= (uint16_t)(~((uint16_t)TIM_CR2_OIS3));
+    tmpcr2 &= (uint16_t)(~((uint16_t)TIM_CR2_OIS3N));
+    /* Set the Output Idle state */
+    tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCIdleState << 4);
+    /* Set the Output N Idle state */
+    tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCNIdleState << 4);
+  }
+  /* Write to TIMx CR2 */
+  TIMx->CR2 = tmpcr2;
+  
+  /* Write to TIMx CCMR2 */
+  TIMx->CCMR2 = tmpccmrx;
+
+  /* Set the Capture Compare Register value */
+  TIMx->CCR3 = TIM_OCInitStruct->TIM_Pulse;
+  
+  /* Write to TIMx CCER */
+  TIMx->CCER = tmpccer;
+}
+
+/**
+  * @brief  Initializes the TIMx Channel4 according to the specified
+  *         parameters in the TIM_OCInitStruct.
+  * @param  TIMx: where x can be  1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+  * @param  TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure
+  *         that contains the configuration information for the specified TIM peripheral.
+  * @retval None
+  */
+void TIM_OC4Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct)
+{
+  uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0;
+   
+  /* Check the parameters */
+  assert_param(IS_TIM_LIST3_PERIPH(TIMx)); 
+  assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode));
+  assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState));
+  assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity));   
+  /* Disable the Channel 2: Reset the CC4E Bit */
+  TIMx->CCER &= (uint16_t)(~((uint16_t)TIM_CCER_CC4E));
+  
+  /* Get the TIMx CCER register value */
+  tmpccer = TIMx->CCER;
+  /* Get the TIMx CR2 register value */
+  tmpcr2 =  TIMx->CR2;
+  
+  /* Get the TIMx CCMR2 register value */
+  tmpccmrx = TIMx->CCMR2;
+    
+  /* Reset the Output Compare mode and Capture/Compare selection Bits */
+  tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR2_OC4M));
+  tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR2_CC4S));
+  
+  /* Select the Output Compare Mode */
+  tmpccmrx |= (uint16_t)(TIM_OCInitStruct->TIM_OCMode << 8);
+  
+  /* Reset the Output Polarity level */
+  tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC4P));
+  /* Set the Output Compare Polarity */
+  tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCPolarity << 12);
+  
+  /* Set the Output State */
+  tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputState << 12);
+    
+  if((TIMx == TIM1) || (TIMx == TIM8))
+  {
+    assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState));
+    /* Reset the Output Compare IDLE State */
+    tmpcr2 &= (uint16_t)(~((uint16_t)TIM_CR2_OIS4));
+    /* Set the Output Idle state */
+    tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCIdleState << 6);
+  }
+  /* Write to TIMx CR2 */
+  TIMx->CR2 = tmpcr2;
+  
+  /* Write to TIMx CCMR2 */  
+  TIMx->CCMR2 = tmpccmrx;
+
+  /* Set the Capture Compare Register value */
+  TIMx->CCR4 = TIM_OCInitStruct->TIM_Pulse;
+  
+  /* Write to TIMx CCER */
+  TIMx->CCER = tmpccer;
+}
+
+/**
+  * @brief  Initializes the TIM peripheral according to the specified
+  *         parameters in the TIM_ICInitStruct.
+  * @param  TIMx: where x can be  1 to 17 except 6 and 7 to select the TIM peripheral.
+  * @param  TIM_ICInitStruct: pointer to a TIM_ICInitTypeDef structure
+  *         that contains the configuration information for the specified TIM peripheral.
+  * @retval None
+  */
+void TIM_ICInit(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_CHANNEL(TIM_ICInitStruct->TIM_Channel));  
+  assert_param(IS_TIM_IC_SELECTION(TIM_ICInitStruct->TIM_ICSelection));
+  assert_param(IS_TIM_IC_PRESCALER(TIM_ICInitStruct->TIM_ICPrescaler));
+  assert_param(IS_TIM_IC_FILTER(TIM_ICInitStruct->TIM_ICFilter));
+  
+  if((TIMx == TIM1) || (TIMx == TIM8) || (TIMx == TIM2) || (TIMx == TIM3) ||
+     (TIMx == TIM4) ||(TIMx == TIM5))
+  {
+    assert_param(IS_TIM_IC_POLARITY(TIM_ICInitStruct->TIM_ICPolarity));
+  }
+  else
+  {
+    assert_param(IS_TIM_IC_POLARITY_LITE(TIM_ICInitStruct->TIM_ICPolarity));
+  }
+  if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_1)
+  {
+    assert_param(IS_TIM_LIST8_PERIPH(TIMx));
+    /* TI1 Configuration */
+    TI1_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity,
+               TIM_ICInitStruct->TIM_ICSelection,
+               TIM_ICInitStruct->TIM_ICFilter);
+    /* Set the Input Capture Prescaler value */
+    TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
+  }
+  else if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_2)
+  {
+    assert_param(IS_TIM_LIST6_PERIPH(TIMx));
+    /* TI2 Configuration */
+    TI2_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity,
+               TIM_ICInitStruct->TIM_ICSelection,
+               TIM_ICInitStruct->TIM_ICFilter);
+    /* Set the Input Capture Prescaler value */
+    TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
+  }
+  else if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_3)
+  {
+    assert_param(IS_TIM_LIST3_PERIPH(TIMx));
+    /* TI3 Configuration */
+    TI3_Config(TIMx,  TIM_ICInitStruct->TIM_ICPolarity,
+               TIM_ICInitStruct->TIM_ICSelection,
+               TIM_ICInitStruct->TIM_ICFilter);
+    /* Set the Input Capture Prescaler value */
+    TIM_SetIC3Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
+  }
+  else
+  {
+    assert_param(IS_TIM_LIST3_PERIPH(TIMx));
+    /* TI4 Configuration */
+    TI4_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity,
+               TIM_ICInitStruct->TIM_ICSelection,
+               TIM_ICInitStruct->TIM_ICFilter);
+    /* Set the Input Capture Prescaler value */
+    TIM_SetIC4Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
+  }
+}
+
+/**
+  * @brief  Configures the TIM peripheral according to the specified
+  *         parameters in the TIM_ICInitStruct to measure an external PWM signal.
+  * @param  TIMx: where x can be  1, 2, 3, 4, 5, 8, 9, 12 or 15 to select the TIM peripheral.
+  * @param  TIM_ICInitStruct: pointer to a TIM_ICInitTypeDef structure
+  *         that contains the configuration information for the specified TIM peripheral.
+  * @retval None
+  */
+void TIM_PWMIConfig(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct)
+{
+  uint16_t icoppositepolarity = TIM_ICPolarity_Rising;
+  uint16_t icoppositeselection = TIM_ICSelection_DirectTI;
+  /* Check the parameters */
+  assert_param(IS_TIM_LIST6_PERIPH(TIMx));
+  /* Select the Opposite Input Polarity */
+  if (TIM_ICInitStruct->TIM_ICPolarity == TIM_ICPolarity_Rising)
+  {
+    icoppositepolarity = TIM_ICPolarity_Falling;
+  }
+  else
+  {
+    icoppositepolarity = TIM_ICPolarity_Rising;
+  }
+  /* Select the Opposite Input */
+  if (TIM_ICInitStruct->TIM_ICSelection == TIM_ICSelection_DirectTI)
+  {
+    icoppositeselection = TIM_ICSelection_IndirectTI;
+  }
+  else
+  {
+    icoppositeselection = TIM_ICSelection_DirectTI;
+  }
+  if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_1)
+  {
+    /* TI1 Configuration */
+    TI1_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, TIM_ICInitStruct->TIM_ICSelection,
+               TIM_ICInitStruct->TIM_ICFilter);
+    /* Set the Input Capture Prescaler value */
+    TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
+    /* TI2 Configuration */
+    TI2_Config(TIMx, icoppositepolarity, icoppositeselection, TIM_ICInitStruct->TIM_ICFilter);
+    /* Set the Input Capture Prescaler value */
+    TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
+  }
+  else
+  { 
+    /* TI2 Configuration */
+    TI2_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, TIM_ICInitStruct->TIM_ICSelection,
+               TIM_ICInitStruct->TIM_ICFilter);
+    /* Set the Input Capture Prescaler value */
+    TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
+    /* TI1 Configuration */
+    TI1_Config(TIMx, icoppositepolarity, icoppositeselection, TIM_ICInitStruct->TIM_ICFilter);
+    /* Set the Input Capture Prescaler value */
+    TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
+  }
+}
+
+/**
+  * @brief  Configures the: Break feature, dead time, Lock level, the OSSI,
+  *         the OSSR State and the AOE(automatic output enable).
+  * @param  TIMx: where x can be  1 or 8 to select the TIM 
+  * @param  TIM_BDTRInitStruct: pointer to a TIM_BDTRInitTypeDef structure that
+  *         contains the BDTR Register configuration  information for the TIM peripheral.
+  * @retval None
+  */
+void TIM_BDTRConfig(TIM_TypeDef* TIMx, TIM_BDTRInitTypeDef *TIM_BDTRInitStruct)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_LIST2_PERIPH(TIMx));
+  assert_param(IS_TIM_OSSR_STATE(TIM_BDTRInitStruct->TIM_OSSRState));
+  assert_param(IS_TIM_OSSI_STATE(TIM_BDTRInitStruct->TIM_OSSIState));
+  assert_param(IS_TIM_LOCK_LEVEL(TIM_BDTRInitStruct->TIM_LOCKLevel));
+  assert_param(IS_TIM_BREAK_STATE(TIM_BDTRInitStruct->TIM_Break));
+  assert_param(IS_TIM_BREAK_POLARITY(TIM_BDTRInitStruct->TIM_BreakPolarity));
+  assert_param(IS_TIM_AUTOMATIC_OUTPUT_STATE(TIM_BDTRInitStruct->TIM_AutomaticOutput));
+  /* Set the Lock level, the Break enable Bit and the Ploarity, the OSSR State,
+     the OSSI State, the dead time value and the Automatic Output Enable Bit */
+  TIMx->BDTR = (uint32_t)TIM_BDTRInitStruct->TIM_OSSRState | TIM_BDTRInitStruct->TIM_OSSIState |
+             TIM_BDTRInitStruct->TIM_LOCKLevel | TIM_BDTRInitStruct->TIM_DeadTime |
+             TIM_BDTRInitStruct->TIM_Break | TIM_BDTRInitStruct->TIM_BreakPolarity |
+             TIM_BDTRInitStruct->TIM_AutomaticOutput;
+}
+
+/**
+  * @brief  Fills each TIM_TimeBaseInitStruct member with its default value.
+  * @param  TIM_TimeBaseInitStruct : pointer to a TIM_TimeBaseInitTypeDef
+  *         structure which will be initialized.
+  * @retval None
+  */
+void TIM_TimeBaseStructInit(TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct)
+{
+  /* Set the default configuration */
+  TIM_TimeBaseInitStruct->TIM_Period = 0xFFFF;
+  TIM_TimeBaseInitStruct->TIM_Prescaler = 0x0000;
+  TIM_TimeBaseInitStruct->TIM_ClockDivision = TIM_CKD_DIV1;
+  TIM_TimeBaseInitStruct->TIM_CounterMode = TIM_CounterMode_Up;
+  TIM_TimeBaseInitStruct->TIM_RepetitionCounter = 0x0000;
+}
+
+/**
+  * @brief  Fills each TIM_OCInitStruct member with its default value.
+  * @param  TIM_OCInitStruct : pointer to a TIM_OCInitTypeDef structure which will
+  *         be initialized.
+  * @retval None
+  */
+void TIM_OCStructInit(TIM_OCInitTypeDef* TIM_OCInitStruct)
+{
+  /* Set the default configuration */
+  TIM_OCInitStruct->TIM_OCMode = TIM_OCMode_Timing;
+  TIM_OCInitStruct->TIM_OutputState = TIM_OutputState_Disable;
+  TIM_OCInitStruct->TIM_OutputNState = TIM_OutputNState_Disable;
+  TIM_OCInitStruct->TIM_Pulse = 0x0000;
+  TIM_OCInitStruct->TIM_OCPolarity = TIM_OCPolarity_High;
+  TIM_OCInitStruct->TIM_OCNPolarity = TIM_OCPolarity_High;
+  TIM_OCInitStruct->TIM_OCIdleState = TIM_OCIdleState_Reset;
+  TIM_OCInitStruct->TIM_OCNIdleState = TIM_OCNIdleState_Reset;
+}
+
+/**
+  * @brief  Fills each TIM_ICInitStruct member with its default value.
+  * @param  TIM_ICInitStruct: pointer to a TIM_ICInitTypeDef structure which will
+  *         be initialized.
+  * @retval None
+  */
+void TIM_ICStructInit(TIM_ICInitTypeDef* TIM_ICInitStruct)
+{
+  /* Set the default configuration */
+  TIM_ICInitStruct->TIM_Channel = TIM_Channel_1;
+  TIM_ICInitStruct->TIM_ICPolarity = TIM_ICPolarity_Rising;
+  TIM_ICInitStruct->TIM_ICSelection = TIM_ICSelection_DirectTI;
+  TIM_ICInitStruct->TIM_ICPrescaler = TIM_ICPSC_DIV1;
+  TIM_ICInitStruct->TIM_ICFilter = 0x00;
+}
+
+/**
+  * @brief  Fills each TIM_BDTRInitStruct member with its default value.
+  * @param  TIM_BDTRInitStruct: pointer to a TIM_BDTRInitTypeDef structure which
+  *         will be initialized.
+  * @retval None
+  */
+void TIM_BDTRStructInit(TIM_BDTRInitTypeDef* TIM_BDTRInitStruct)
+{
+  /* Set the default configuration */
+  TIM_BDTRInitStruct->TIM_OSSRState = TIM_OSSRState_Disable;
+  TIM_BDTRInitStruct->TIM_OSSIState = TIM_OSSIState_Disable;
+  TIM_BDTRInitStruct->TIM_LOCKLevel = TIM_LOCKLevel_OFF;
+  TIM_BDTRInitStruct->TIM_DeadTime = 0x00;
+  TIM_BDTRInitStruct->TIM_Break = TIM_Break_Disable;
+  TIM_BDTRInitStruct->TIM_BreakPolarity = TIM_BreakPolarity_Low;
+  TIM_BDTRInitStruct->TIM_AutomaticOutput = TIM_AutomaticOutput_Disable;
+}
+
+/**
+  * @brief  Enables or disables the specified TIM peripheral.
+  * @param  TIMx: where x can be 1 to 17 to select the TIMx peripheral.
+  * @param  NewState: new state of the TIMx peripheral.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void TIM_Cmd(TIM_TypeDef* TIMx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_ALL_PERIPH(TIMx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  
+  if (NewState != DISABLE)
+  {
+    /* Enable the TIM Counter */
+    TIMx->CR1 |= TIM_CR1_CEN;
+  }
+  else
+  {
+    /* Disable the TIM Counter */
+    TIMx->CR1 &= (uint16_t)(~((uint16_t)TIM_CR1_CEN));
+  }
+}
+
+/**
+  * @brief  Enables or disables the TIM peripheral Main Outputs.
+  * @param  TIMx: where x can be 1, 8, 15, 16 or 17 to select the TIMx peripheral.
+  * @param  NewState: new state of the TIM peripheral Main Outputs.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void TIM_CtrlPWMOutputs(TIM_TypeDef* TIMx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_LIST2_PERIPH(TIMx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  if (NewState != DISABLE)
+  {
+    /* Enable the TIM Main Output */
+    TIMx->BDTR |= TIM_BDTR_MOE;
+  }
+  else
+  {
+    /* Disable the TIM Main Output */
+    TIMx->BDTR &= (uint16_t)(~((uint16_t)TIM_BDTR_MOE));
+  }  
+}
+
+/**
+  * @brief  Enables or disables the specified TIM interrupts.
+  * @param  TIMx: where x can be 1 to 17 to select the TIMx peripheral.
+  * @param  TIM_IT: specifies the TIM interrupts sources to be enabled or disabled.
+  *   This parameter can be any combination of the following values:
+  *     @arg TIM_IT_Update: TIM update Interrupt source
+  *     @arg TIM_IT_CC1: TIM Capture Compare 1 Interrupt source
+  *     @arg TIM_IT_CC2: TIM Capture Compare 2 Interrupt source
+  *     @arg TIM_IT_CC3: TIM Capture Compare 3 Interrupt source
+  *     @arg TIM_IT_CC4: TIM Capture Compare 4 Interrupt source
+  *     @arg TIM_IT_COM: TIM Commutation Interrupt source
+  *     @arg TIM_IT_Trigger: TIM Trigger Interrupt source
+  *     @arg TIM_IT_Break: TIM Break Interrupt source
+  * @note 
+  *   - TIM6 and TIM7 can only generate an update interrupt.
+  *   - TIM9, TIM12 and TIM15 can have only TIM_IT_Update, TIM_IT_CC1,
+  *      TIM_IT_CC2 or TIM_IT_Trigger. 
+  *   - TIM10, TIM11, TIM13, TIM14, TIM16 and TIM17 can have TIM_IT_Update or TIM_IT_CC1.   
+  *   - TIM_IT_Break is used only with TIM1, TIM8 and TIM15. 
+  *   - TIM_IT_COM is used only with TIM1, TIM8, TIM15, TIM16 and TIM17.    
+  * @param  NewState: new state of the TIM interrupts.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void TIM_ITConfig(TIM_TypeDef* TIMx, uint16_t TIM_IT, FunctionalState NewState)
+{  
+  /* Check the parameters */
+  assert_param(IS_TIM_ALL_PERIPH(TIMx));
+  assert_param(IS_TIM_IT(TIM_IT));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  
+  if (NewState != DISABLE)
+  {
+    /* Enable the Interrupt sources */
+    TIMx->DIER |= TIM_IT;
+  }
+  else
+  {
+    /* Disable the Interrupt sources */
+    TIMx->DIER &= (uint16_t)~TIM_IT;
+  }
+}
+
+/**
+  * @brief  Configures the TIMx event to be generate by software.
+  * @param  TIMx: where x can be 1 to 17 to select the TIM peripheral.
+  * @param  TIM_EventSource: specifies the event source.
+  *   This parameter can be one or more of the following values:	   
+  *     @arg TIM_EventSource_Update: Timer update Event source
+  *     @arg TIM_EventSource_CC1: Timer Capture Compare 1 Event source
+  *     @arg TIM_EventSource_CC2: Timer Capture Compare 2 Event source
+  *     @arg TIM_EventSource_CC3: Timer Capture Compare 3 Event source
+  *     @arg TIM_EventSource_CC4: Timer Capture Compare 4 Event source
+  *     @arg TIM_EventSource_COM: Timer COM event source  
+  *     @arg TIM_EventSource_Trigger: Timer Trigger Event source
+  *     @arg TIM_EventSource_Break: Timer Break event source
+  * @note 
+  *   - TIM6 and TIM7 can only generate an update event. 
+  *   - TIM_EventSource_COM and TIM_EventSource_Break are used only with TIM1 and TIM8.      
+  * @retval None
+  */
+void TIM_GenerateEvent(TIM_TypeDef* TIMx, uint16_t TIM_EventSource)
+{ 
+  /* Check the parameters */
+  assert_param(IS_TIM_ALL_PERIPH(TIMx));
+  assert_param(IS_TIM_EVENT_SOURCE(TIM_EventSource));
+  
+  /* Set the event sources */
+  TIMx->EGR = TIM_EventSource;
+}
+
+/**
+  * @brief  Configures the TIMx's DMA interface.
+  * @param  TIMx: where x can be  1, 2, 3, 4, 5, 8, 15, 16 or 17 to select 
+  *   the TIM peripheral.
+  * @param  TIM_DMABase: DMA Base address.
+  *   This parameter can be one of the following values:
+  *     @arg TIM_DMABase_CR, TIM_DMABase_CR2, TIM_DMABase_SMCR,
+  *          TIM_DMABase_DIER, TIM1_DMABase_SR, TIM_DMABase_EGR,
+  *          TIM_DMABase_CCMR1, TIM_DMABase_CCMR2, TIM_DMABase_CCER,
+  *          TIM_DMABase_CNT, TIM_DMABase_PSC, TIM_DMABase_ARR,
+  *          TIM_DMABase_RCR, TIM_DMABase_CCR1, TIM_DMABase_CCR2,
+  *          TIM_DMABase_CCR3, TIM_DMABase_CCR4, TIM_DMABase_BDTR,
+  *          TIM_DMABase_DCR.
+  * @param  TIM_DMABurstLength: DMA Burst length.
+  *   This parameter can be one value between:
+  *   TIM_DMABurstLength_1Transfer and TIM_DMABurstLength_18Transfers.
+  * @retval None
+  */
+void TIM_DMAConfig(TIM_TypeDef* TIMx, uint16_t TIM_DMABase, uint16_t TIM_DMABurstLength)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_LIST4_PERIPH(TIMx));
+  assert_param(IS_TIM_DMA_BASE(TIM_DMABase));
+  assert_param(IS_TIM_DMA_LENGTH(TIM_DMABurstLength));
+  /* Set the DMA Base and the DMA Burst Length */
+  TIMx->DCR = TIM_DMABase | TIM_DMABurstLength;
+}
+
+/**
+  * @brief  Enables or disables the TIMx's DMA Requests.
+  * @param  TIMx: where x can be  1, 2, 3, 4, 5, 6, 7, 8, 15, 16 or 17 
+  *   to select the TIM peripheral. 
+  * @param  TIM_DMASource: specifies the DMA Request sources.
+  *   This parameter can be any combination of the following values:
+  *     @arg TIM_DMA_Update: TIM update Interrupt source
+  *     @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
+  *     @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
+  *     @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
+  *     @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
+  *     @arg TIM_DMA_COM: TIM Commutation DMA source
+  *     @arg TIM_DMA_Trigger: TIM Trigger DMA source
+  * @param  NewState: new state of the DMA Request sources.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void TIM_DMACmd(TIM_TypeDef* TIMx, uint16_t TIM_DMASource, FunctionalState NewState)
+{ 
+  /* Check the parameters */
+  assert_param(IS_TIM_LIST9_PERIPH(TIMx));
+  assert_param(IS_TIM_DMA_SOURCE(TIM_DMASource));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  
+  if (NewState != DISABLE)
+  {
+    /* Enable the DMA sources */
+    TIMx->DIER |= TIM_DMASource; 
+  }
+  else
+  {
+    /* Disable the DMA sources */
+    TIMx->DIER &= (uint16_t)~TIM_DMASource;
+  }
+}
+
+/**
+  * @brief  Configures the TIMx internal Clock
+  * @param  TIMx: where x can be  1, 2, 3, 4, 5, 8, 9, 12 or 15
+  *         to select the TIM peripheral.
+  * @retval None
+  */
+void TIM_InternalClockConfig(TIM_TypeDef* TIMx)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_LIST6_PERIPH(TIMx));
+  /* Disable slave mode to clock the prescaler directly with the internal clock */
+  TIMx->SMCR &=  (uint16_t)(~((uint16_t)TIM_SMCR_SMS));
+}
+
+/**
+  * @brief  Configures the TIMx Internal Trigger as External Clock
+  * @param  TIMx: where x can be  1, 2, 3, 4, 5, 9, 12 or 15 to select the TIM peripheral.
+  * @param  TIM_ITRSource: Trigger source.
+  *   This parameter can be one of the following values:
+  * @param  TIM_TS_ITR0: Internal Trigger 0
+  * @param  TIM_TS_ITR1: Internal Trigger 1
+  * @param  TIM_TS_ITR2: Internal Trigger 2
+  * @param  TIM_TS_ITR3: Internal Trigger 3
+  * @retval None
+  */
+void TIM_ITRxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_LIST6_PERIPH(TIMx));
+  assert_param(IS_TIM_INTERNAL_TRIGGER_SELECTION(TIM_InputTriggerSource));
+  /* Select the Internal Trigger */
+  TIM_SelectInputTrigger(TIMx, TIM_InputTriggerSource);
+  /* Select the External clock mode1 */
+  TIMx->SMCR |= TIM_SlaveMode_External1;
+}
+
+/**
+  * @brief  Configures the TIMx Trigger as External Clock
+  * @param  TIMx: where x can be  1, 2, 3, 4, 5, 9, 12 or 15 to select the TIM peripheral.
+  * @param  TIM_TIxExternalCLKSource: Trigger source.
+  *   This parameter can be one of the following values:
+  *     @arg TIM_TIxExternalCLK1Source_TI1ED: TI1 Edge Detector
+  *     @arg TIM_TIxExternalCLK1Source_TI1: Filtered Timer Input 1
+  *     @arg TIM_TIxExternalCLK1Source_TI2: Filtered Timer Input 2
+  * @param  TIM_ICPolarity: specifies the TIx Polarity.
+  *   This parameter can be one of the following values:
+  *     @arg TIM_ICPolarity_Rising
+  *     @arg TIM_ICPolarity_Falling
+  * @param  ICFilter : specifies the filter value.
+  *   This parameter must be a value between 0x0 and 0xF.
+  * @retval None
+  */
+void TIM_TIxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_TIxExternalCLKSource,
+                                uint16_t TIM_ICPolarity, uint16_t ICFilter)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_LIST6_PERIPH(TIMx));
+  assert_param(IS_TIM_TIXCLK_SOURCE(TIM_TIxExternalCLKSource));
+  assert_param(IS_TIM_IC_POLARITY(TIM_ICPolarity));
+  assert_param(IS_TIM_IC_FILTER(ICFilter));
+  /* Configure the Timer Input Clock Source */
+  if (TIM_TIxExternalCLKSource == TIM_TIxExternalCLK1Source_TI2)
+  {
+    TI2_Config(TIMx, TIM_ICPolarity, TIM_ICSelection_DirectTI, ICFilter);
+  }
+  else
+  {
+    TI1_Config(TIMx, TIM_ICPolarity, TIM_ICSelection_DirectTI, ICFilter);
+  }
+  /* Select the Trigger source */
+  TIM_SelectInputTrigger(TIMx, TIM_TIxExternalCLKSource);
+  /* Select the External clock mode1 */
+  TIMx->SMCR |= TIM_SlaveMode_External1;
+}
+
+/**
+  * @brief  Configures the External clock Mode1
+  * @param  TIMx: where x can be  1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+  * @param  TIM_ExtTRGPrescaler: The external Trigger Prescaler.
+  *   This parameter can be one of the following values:
+  *     @arg TIM_ExtTRGPSC_OFF: ETRP Prescaler OFF.
+  *     @arg TIM_ExtTRGPSC_DIV2: ETRP frequency divided by 2.
+  *     @arg TIM_ExtTRGPSC_DIV4: ETRP frequency divided by 4.
+  *     @arg TIM_ExtTRGPSC_DIV8: ETRP frequency divided by 8.
+  * @param  TIM_ExtTRGPolarity: The external Trigger Polarity.
+  *   This parameter can be one of the following values:
+  *     @arg TIM_ExtTRGPolarity_Inverted: active low or falling edge active.
+  *     @arg TIM_ExtTRGPolarity_NonInverted: active high or rising edge active.
+  * @param  ExtTRGFilter: External Trigger Filter.
+  *   This parameter must be a value between 0x00 and 0x0F
+  * @retval None
+  */
+void TIM_ETRClockMode1Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity,
+                             uint16_t ExtTRGFilter)
+{
+  uint16_t tmpsmcr = 0;
+  /* Check the parameters */
+  assert_param(IS_TIM_LIST3_PERIPH(TIMx));
+  assert_param(IS_TIM_EXT_PRESCALER(TIM_ExtTRGPrescaler));
+  assert_param(IS_TIM_EXT_POLARITY(TIM_ExtTRGPolarity));
+  assert_param(IS_TIM_EXT_FILTER(ExtTRGFilter));
+  /* Configure the ETR Clock source */
+  TIM_ETRConfig(TIMx, TIM_ExtTRGPrescaler, TIM_ExtTRGPolarity, ExtTRGFilter);
+  
+  /* Get the TIMx SMCR register value */
+  tmpsmcr = TIMx->SMCR;
+  /* Reset the SMS Bits */
+  tmpsmcr &= (uint16_t)(~((uint16_t)TIM_SMCR_SMS));
+  /* Select the External clock mode1 */
+  tmpsmcr |= TIM_SlaveMode_External1;
+  /* Select the Trigger selection : ETRF */
+  tmpsmcr &= (uint16_t)(~((uint16_t)TIM_SMCR_TS));
+  tmpsmcr |= TIM_TS_ETRF;
+  /* Write to TIMx SMCR */
+  TIMx->SMCR = tmpsmcr;
+}
+
+/**
+  * @brief  Configures the External clock Mode2
+  * @param  TIMx: where x can be  1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+  * @param  TIM_ExtTRGPrescaler: The external Trigger Prescaler.
+  *   This parameter can be one of the following values:
+  *     @arg TIM_ExtTRGPSC_OFF: ETRP Prescaler OFF.
+  *     @arg TIM_ExtTRGPSC_DIV2: ETRP frequency divided by 2.
+  *     @arg TIM_ExtTRGPSC_DIV4: ETRP frequency divided by 4.
+  *     @arg TIM_ExtTRGPSC_DIV8: ETRP frequency divided by 8.
+  * @param  TIM_ExtTRGPolarity: The external Trigger Polarity.
+  *   This parameter can be one of the following values:
+  *     @arg TIM_ExtTRGPolarity_Inverted: active low or falling edge active.
+  *     @arg TIM_ExtTRGPolarity_NonInverted: active high or rising edge active.
+  * @param  ExtTRGFilter: External Trigger Filter.
+  *   This parameter must be a value between 0x00 and 0x0F
+  * @retval None
+  */
+void TIM_ETRClockMode2Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, 
+                             uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_LIST3_PERIPH(TIMx));
+  assert_param(IS_TIM_EXT_PRESCALER(TIM_ExtTRGPrescaler));
+  assert_param(IS_TIM_EXT_POLARITY(TIM_ExtTRGPolarity));
+  assert_param(IS_TIM_EXT_FILTER(ExtTRGFilter));
+  /* Configure the ETR Clock source */
+  TIM_ETRConfig(TIMx, TIM_ExtTRGPrescaler, TIM_ExtTRGPolarity, ExtTRGFilter);
+  /* Enable the External clock mode2 */
+  TIMx->SMCR |= TIM_SMCR_ECE;
+}
+
+/**
+  * @brief  Configures the TIMx External Trigger (ETR).
+  * @param  TIMx: where x can be  1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+  * @param  TIM_ExtTRGPrescaler: The external Trigger Prescaler.
+  *   This parameter can be one of the following values:
+  *     @arg TIM_ExtTRGPSC_OFF: ETRP Prescaler OFF.
+  *     @arg TIM_ExtTRGPSC_DIV2: ETRP frequency divided by 2.
+  *     @arg TIM_ExtTRGPSC_DIV4: ETRP frequency divided by 4.
+  *     @arg TIM_ExtTRGPSC_DIV8: ETRP frequency divided by 8.
+  * @param  TIM_ExtTRGPolarity: The external Trigger Polarity.
+  *   This parameter can be one of the following values:
+  *     @arg TIM_ExtTRGPolarity_Inverted: active low or falling edge active.
+  *     @arg TIM_ExtTRGPolarity_NonInverted: active high or rising edge active.
+  * @param  ExtTRGFilter: External Trigger Filter.
+  *   This parameter must be a value between 0x00 and 0x0F
+  * @retval None
+  */
+void TIM_ETRConfig(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity,
+                   uint16_t ExtTRGFilter)
+{
+  uint16_t tmpsmcr = 0;
+  /* Check the parameters */
+  assert_param(IS_TIM_LIST3_PERIPH(TIMx));
+  assert_param(IS_TIM_EXT_PRESCALER(TIM_ExtTRGPrescaler));
+  assert_param(IS_TIM_EXT_POLARITY(TIM_ExtTRGPolarity));
+  assert_param(IS_TIM_EXT_FILTER(ExtTRGFilter));
+  tmpsmcr = TIMx->SMCR;
+  /* Reset the ETR Bits */
+  tmpsmcr &= SMCR_ETR_Mask;
+  /* Set the Prescaler, the Filter value and the Polarity */
+  tmpsmcr |= (uint16_t)(TIM_ExtTRGPrescaler | (uint16_t)(TIM_ExtTRGPolarity | (uint16_t)(ExtTRGFilter << (uint16_t)8)));
+  /* Write to TIMx SMCR */
+  TIMx->SMCR = tmpsmcr;
+}
+
+/**
+  * @brief  Configures the TIMx Prescaler.
+  * @param  TIMx: where x can be 1 to 17 to select the TIM peripheral.
+  * @param  Prescaler: specifies the Prescaler Register value
+  * @param  TIM_PSCReloadMode: specifies the TIM Prescaler Reload mode
+  *   This parameter can be one of the following values:
+  *     @arg TIM_PSCReloadMode_Update: The Prescaler is loaded at the update event.
+  *     @arg TIM_PSCReloadMode_Immediate: The Prescaler is loaded immediately.
+  * @retval None
+  */
+void TIM_PrescalerConfig(TIM_TypeDef* TIMx, uint16_t Prescaler, uint16_t TIM_PSCReloadMode)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_ALL_PERIPH(TIMx));
+  assert_param(IS_TIM_PRESCALER_RELOAD(TIM_PSCReloadMode));
+  /* Set the Prescaler value */
+  TIMx->PSC = Prescaler;
+  /* Set or reset the UG Bit */
+  TIMx->EGR = TIM_PSCReloadMode;
+}
+
+/**
+  * @brief  Specifies the TIMx Counter Mode to be used.
+  * @param  TIMx: where x can be  1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+  * @param  TIM_CounterMode: specifies the Counter Mode to be used
+  *   This parameter can be one of the following values:
+  *     @arg TIM_CounterMode_Up: TIM Up Counting Mode
+  *     @arg TIM_CounterMode_Down: TIM Down Counting Mode
+  *     @arg TIM_CounterMode_CenterAligned1: TIM Center Aligned Mode1
+  *     @arg TIM_CounterMode_CenterAligned2: TIM Center Aligned Mode2
+  *     @arg TIM_CounterMode_CenterAligned3: TIM Center Aligned Mode3
+  * @retval None
+  */
+void TIM_CounterModeConfig(TIM_TypeDef* TIMx, uint16_t TIM_CounterMode)
+{
+  uint16_t tmpcr1 = 0;
+  /* Check the parameters */
+  assert_param(IS_TIM_LIST3_PERIPH(TIMx));
+  assert_param(IS_TIM_COUNTER_MODE(TIM_CounterMode));
+  tmpcr1 = TIMx->CR1;
+  /* Reset the CMS and DIR Bits */
+  tmpcr1 &= (uint16_t)(~((uint16_t)(TIM_CR1_DIR | TIM_CR1_CMS)));
+  /* Set the Counter Mode */
+  tmpcr1 |= TIM_CounterMode;
+  /* Write to TIMx CR1 register */
+  TIMx->CR1 = tmpcr1;
+}
+
+/**
+  * @brief  Selects the Input Trigger source
+  * @param  TIMx: where x can be  1, 2, 3, 4, 5, 8, 9, 12 or 15 to select the TIM peripheral.
+  * @param  TIM_InputTriggerSource: The Input Trigger source.
+  *   This parameter can be one of the following values:
+  *     @arg TIM_TS_ITR0: Internal Trigger 0
+  *     @arg TIM_TS_ITR1: Internal Trigger 1
+  *     @arg TIM_TS_ITR2: Internal Trigger 2
+  *     @arg TIM_TS_ITR3: Internal Trigger 3
+  *     @arg TIM_TS_TI1F_ED: TI1 Edge Detector
+  *     @arg TIM_TS_TI1FP1: Filtered Timer Input 1
+  *     @arg TIM_TS_TI2FP2: Filtered Timer Input 2
+  *     @arg TIM_TS_ETRF: External Trigger input
+  * @retval None
+  */
+void TIM_SelectInputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource)
+{
+  uint16_t tmpsmcr = 0;
+  /* Check the parameters */
+  assert_param(IS_TIM_LIST6_PERIPH(TIMx));
+  assert_param(IS_TIM_TRIGGER_SELECTION(TIM_InputTriggerSource));
+  /* Get the TIMx SMCR register value */
+  tmpsmcr = TIMx->SMCR;
+  /* Reset the TS Bits */
+  tmpsmcr &= (uint16_t)(~((uint16_t)TIM_SMCR_TS));
+  /* Set the Input Trigger source */
+  tmpsmcr |= TIM_InputTriggerSource;
+  /* Write to TIMx SMCR */
+  TIMx->SMCR = tmpsmcr;
+}
+
+/**
+  * @brief  Configures the TIMx Encoder Interface.
+  * @param  TIMx: where x can be  1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+  * @param  TIM_EncoderMode: specifies the TIMx Encoder Mode.
+  *   This parameter can be one of the following values:
+  *     @arg TIM_EncoderMode_TI1: Counter counts on TI1FP1 edge depending on TI2FP2 level.
+  *     @arg TIM_EncoderMode_TI2: Counter counts on TI2FP2 edge depending on TI1FP1 level.
+  *     @arg TIM_EncoderMode_TI12: Counter counts on both TI1FP1 and TI2FP2 edges depending
+  *                                on the level of the other input.
+  * @param  TIM_IC1Polarity: specifies the IC1 Polarity
+  *   This parameter can be one of the following values:
+  *     @arg TIM_ICPolarity_Falling: IC Falling edge.
+  *     @arg TIM_ICPolarity_Rising: IC Rising edge.
+  * @param  TIM_IC2Polarity: specifies the IC2 Polarity
+  *   This parameter can be one of the following values:
+  *     @arg TIM_ICPolarity_Falling: IC Falling edge.
+  *     @arg TIM_ICPolarity_Rising: IC Rising edge.
+  * @retval None
+  */
+void TIM_EncoderInterfaceConfig(TIM_TypeDef* TIMx, uint16_t TIM_EncoderMode,
+                                uint16_t TIM_IC1Polarity, uint16_t TIM_IC2Polarity)
+{
+  uint16_t tmpsmcr = 0;
+  uint16_t tmpccmr1 = 0;
+  uint16_t tmpccer = 0;
+    
+  /* Check the parameters */
+  assert_param(IS_TIM_LIST5_PERIPH(TIMx));
+  assert_param(IS_TIM_ENCODER_MODE(TIM_EncoderMode));
+  assert_param(IS_TIM_IC_POLARITY(TIM_IC1Polarity));
+  assert_param(IS_TIM_IC_POLARITY(TIM_IC2Polarity));
+
+  /* Get the TIMx SMCR register value */
+  tmpsmcr = TIMx->SMCR;
+  
+  /* Get the TIMx CCMR1 register value */
+  tmpccmr1 = TIMx->CCMR1;
+  
+  /* Get the TIMx CCER register value */
+  tmpccer = TIMx->CCER;
+  
+  /* Set the encoder Mode */
+  tmpsmcr &= (uint16_t)(~((uint16_t)TIM_SMCR_SMS));
+  tmpsmcr |= TIM_EncoderMode;
+  
+  /* Select the Capture Compare 1 and the Capture Compare 2 as input */
+  tmpccmr1 &= (uint16_t)(((uint16_t)~((uint16_t)TIM_CCMR1_CC1S)) & (uint16_t)(~((uint16_t)TIM_CCMR1_CC2S)));
+  tmpccmr1 |= TIM_CCMR1_CC1S_0 | TIM_CCMR1_CC2S_0;
+  
+  /* Set the TI1 and the TI2 Polarities */
+  tmpccer &= (uint16_t)(((uint16_t)~((uint16_t)TIM_CCER_CC1P)) & ((uint16_t)~((uint16_t)TIM_CCER_CC2P)));
+  tmpccer |= (uint16_t)(TIM_IC1Polarity | (uint16_t)(TIM_IC2Polarity << (uint16_t)4));
+  
+  /* Write to TIMx SMCR */
+  TIMx->SMCR = tmpsmcr;
+  /* Write to TIMx CCMR1 */
+  TIMx->CCMR1 = tmpccmr1;
+  /* Write to TIMx CCER */
+  TIMx->CCER = tmpccer;
+}
+
+/**
+  * @brief  Forces the TIMx output 1 waveform to active or inactive level.
+  * @param  TIMx: where x can be  1 to 17 except 6 and 7 to select the TIM peripheral.
+  * @param  TIM_ForcedAction: specifies the forced Action to be set to the output waveform.
+  *   This parameter can be one of the following values:
+  *     @arg TIM_ForcedAction_Active: Force active level on OC1REF
+  *     @arg TIM_ForcedAction_InActive: Force inactive level on OC1REF.
+  * @retval None
+  */
+void TIM_ForcedOC1Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction)
+{
+  uint16_t tmpccmr1 = 0;
+  /* Check the parameters */
+  assert_param(IS_TIM_LIST8_PERIPH(TIMx));
+  assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction));
+  tmpccmr1 = TIMx->CCMR1;
+  /* Reset the OC1M Bits */
+  tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC1M);
+  /* Configure The Forced output Mode */
+  tmpccmr1 |= TIM_ForcedAction;
+  /* Write to TIMx CCMR1 register */
+  TIMx->CCMR1 = tmpccmr1;
+}
+
+/**
+  * @brief  Forces the TIMx output 2 waveform to active or inactive level.
+  * @param  TIMx: where x can be  1, 2, 3, 4, 5, 8, 9, 12 or 15 to select the TIM peripheral.
+  * @param  TIM_ForcedAction: specifies the forced Action to be set to the output waveform.
+  *   This parameter can be one of the following values:
+  *     @arg TIM_ForcedAction_Active: Force active level on OC2REF
+  *     @arg TIM_ForcedAction_InActive: Force inactive level on OC2REF.
+  * @retval None
+  */
+void TIM_ForcedOC2Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction)
+{
+  uint16_t tmpccmr1 = 0;
+  /* Check the parameters */
+  assert_param(IS_TIM_LIST6_PERIPH(TIMx));
+  assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction));
+  tmpccmr1 = TIMx->CCMR1;
+  /* Reset the OC2M Bits */
+  tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC2M);
+  /* Configure The Forced output Mode */
+  tmpccmr1 |= (uint16_t)(TIM_ForcedAction << 8);
+  /* Write to TIMx CCMR1 register */
+  TIMx->CCMR1 = tmpccmr1;
+}
+
+/**
+  * @brief  Forces the TIMx output 3 waveform to active or inactive level.
+  * @param  TIMx: where x can be  1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+  * @param  TIM_ForcedAction: specifies the forced Action to be set to the output waveform.
+  *   This parameter can be one of the following values:
+  *     @arg TIM_ForcedAction_Active: Force active level on OC3REF
+  *     @arg TIM_ForcedAction_InActive: Force inactive level on OC3REF.
+  * @retval None
+  */
+void TIM_ForcedOC3Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction)
+{
+  uint16_t tmpccmr2 = 0;
+  /* Check the parameters */
+  assert_param(IS_TIM_LIST3_PERIPH(TIMx));
+  assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction));
+  tmpccmr2 = TIMx->CCMR2;
+  /* Reset the OC1M Bits */
+  tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC3M);
+  /* Configure The Forced output Mode */
+  tmpccmr2 |= TIM_ForcedAction;
+  /* Write to TIMx CCMR2 register */
+  TIMx->CCMR2 = tmpccmr2;
+}
+
+/**
+  * @brief  Forces the TIMx output 4 waveform to active or inactive level.
+  * @param  TIMx: where x can be  1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+  * @param  TIM_ForcedAction: specifies the forced Action to be set to the output waveform.
+  *   This parameter can be one of the following values:
+  *     @arg TIM_ForcedAction_Active: Force active level on OC4REF
+  *     @arg TIM_ForcedAction_InActive: Force inactive level on OC4REF.
+  * @retval None
+  */
+void TIM_ForcedOC4Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction)
+{
+  uint16_t tmpccmr2 = 0;
+  /* Check the parameters */
+  assert_param(IS_TIM_LIST3_PERIPH(TIMx));
+  assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction));
+  tmpccmr2 = TIMx->CCMR2;
+  /* Reset the OC2M Bits */
+  tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC4M);
+  /* Configure The Forced output Mode */
+  tmpccmr2 |= (uint16_t)(TIM_ForcedAction << 8);
+  /* Write to TIMx CCMR2 register */
+  TIMx->CCMR2 = tmpccmr2;
+}
+
+/**
+  * @brief  Enables or disables TIMx peripheral Preload register on ARR.
+  * @param  TIMx: where x can be  1 to 17 to select the TIM peripheral.
+  * @param  NewState: new state of the TIMx peripheral Preload register
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void TIM_ARRPreloadConfig(TIM_TypeDef* TIMx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_ALL_PERIPH(TIMx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  if (NewState != DISABLE)
+  {
+    /* Set the ARR Preload Bit */
+    TIMx->CR1 |= TIM_CR1_ARPE;
+  }
+  else
+  {
+    /* Reset the ARR Preload Bit */
+    TIMx->CR1 &= (uint16_t)~((uint16_t)TIM_CR1_ARPE);
+  }
+}
+
+/**
+  * @brief  Selects the TIM peripheral Commutation event.
+  * @param  TIMx: where x can be  1, 8, 15, 16 or 17 to select the TIMx peripheral
+  * @param  NewState: new state of the Commutation event.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void TIM_SelectCOM(TIM_TypeDef* TIMx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_LIST2_PERIPH(TIMx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  if (NewState != DISABLE)
+  {
+    /* Set the COM Bit */
+    TIMx->CR2 |= TIM_CR2_CCUS;
+  }
+  else
+  {
+    /* Reset the COM Bit */
+    TIMx->CR2 &= (uint16_t)~((uint16_t)TIM_CR2_CCUS);
+  }
+}
+
+/**
+  * @brief  Selects the TIMx peripheral Capture Compare DMA source.
+  * @param  TIMx: where x can be  1, 2, 3, 4, 5, 8, 15, 16 or 17 to select 
+  *         the TIM peripheral.
+  * @param  NewState: new state of the Capture Compare DMA source
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void TIM_SelectCCDMA(TIM_TypeDef* TIMx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_LIST4_PERIPH(TIMx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  if (NewState != DISABLE)
+  {
+    /* Set the CCDS Bit */
+    TIMx->CR2 |= TIM_CR2_CCDS;
+  }
+  else
+  {
+    /* Reset the CCDS Bit */
+    TIMx->CR2 &= (uint16_t)~((uint16_t)TIM_CR2_CCDS);
+  }
+}
+
+/**
+  * @brief  Sets or Resets the TIM peripheral Capture Compare Preload Control bit.
+  * @param  TIMx: where x can be   1, 2, 3, 4, 5, 8 or 15 
+  *         to select the TIMx peripheral
+  * @param  NewState: new state of the Capture Compare Preload Control bit
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void TIM_CCPreloadControl(TIM_TypeDef* TIMx, FunctionalState NewState)
+{ 
+  /* Check the parameters */
+  assert_param(IS_TIM_LIST5_PERIPH(TIMx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  if (NewState != DISABLE)
+  {
+    /* Set the CCPC Bit */
+    TIMx->CR2 |= TIM_CR2_CCPC;
+  }
+  else
+  {
+    /* Reset the CCPC Bit */
+    TIMx->CR2 &= (uint16_t)~((uint16_t)TIM_CR2_CCPC);
+  }
+}
+
+/**
+  * @brief  Enables or disables the TIMx peripheral Preload register on CCR1.
+  * @param  TIMx: where x can be  1 to 17 except 6 and 7 to select the TIM peripheral.
+  * @param  TIM_OCPreload: new state of the TIMx peripheral Preload register
+  *   This parameter can be one of the following values:
+  *     @arg TIM_OCPreload_Enable
+  *     @arg TIM_OCPreload_Disable
+  * @retval None
+  */
+void TIM_OC1PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload)
+{
+  uint16_t tmpccmr1 = 0;
+  /* Check the parameters */
+  assert_param(IS_TIM_LIST8_PERIPH(TIMx));
+  assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload));
+  tmpccmr1 = TIMx->CCMR1;
+  /* Reset the OC1PE Bit */
+  tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC1PE);
+  /* Enable or Disable the Output Compare Preload feature */
+  tmpccmr1 |= TIM_OCPreload;
+  /* Write to TIMx CCMR1 register */
+  TIMx->CCMR1 = tmpccmr1;
+}
+
+/**
+  * @brief  Enables or disables the TIMx peripheral Preload register on CCR2.
+  * @param  TIMx: where x can be  1, 2, 3, 4, 5, 8, 9, 12 or 15 to select 
+  *         the TIM peripheral.
+  * @param  TIM_OCPreload: new state of the TIMx peripheral Preload register
+  *   This parameter can be one of the following values:
+  *     @arg TIM_OCPreload_Enable
+  *     @arg TIM_OCPreload_Disable
+  * @retval None
+  */
+void TIM_OC2PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload)
+{
+  uint16_t tmpccmr1 = 0;
+  /* Check the parameters */
+  assert_param(IS_TIM_LIST6_PERIPH(TIMx));
+  assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload));
+  tmpccmr1 = TIMx->CCMR1;
+  /* Reset the OC2PE Bit */
+  tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC2PE);
+  /* Enable or Disable the Output Compare Preload feature */
+  tmpccmr1 |= (uint16_t)(TIM_OCPreload << 8);
+  /* Write to TIMx CCMR1 register */
+  TIMx->CCMR1 = tmpccmr1;
+}
+
+/**
+  * @brief  Enables or disables the TIMx peripheral Preload register on CCR3.
+  * @param  TIMx: where x can be  1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+  * @param  TIM_OCPreload: new state of the TIMx peripheral Preload register
+  *   This parameter can be one of the following values:
+  *     @arg TIM_OCPreload_Enable
+  *     @arg TIM_OCPreload_Disable
+  * @retval None
+  */
+void TIM_OC3PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload)
+{
+  uint16_t tmpccmr2 = 0;
+  /* Check the parameters */
+  assert_param(IS_TIM_LIST3_PERIPH(TIMx));
+  assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload));
+  tmpccmr2 = TIMx->CCMR2;
+  /* Reset the OC3PE Bit */
+  tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC3PE);
+  /* Enable or Disable the Output Compare Preload feature */
+  tmpccmr2 |= TIM_OCPreload;
+  /* Write to TIMx CCMR2 register */
+  TIMx->CCMR2 = tmpccmr2;
+}
+
+/**
+  * @brief  Enables or disables the TIMx peripheral Preload register on CCR4.
+  * @param  TIMx: where x can be  1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+  * @param  TIM_OCPreload: new state of the TIMx peripheral Preload register
+  *   This parameter can be one of the following values:
+  *     @arg TIM_OCPreload_Enable
+  *     @arg TIM_OCPreload_Disable
+  * @retval None
+  */
+void TIM_OC4PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload)
+{
+  uint16_t tmpccmr2 = 0;
+  /* Check the parameters */
+  assert_param(IS_TIM_LIST3_PERIPH(TIMx));
+  assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload));
+  tmpccmr2 = TIMx->CCMR2;
+  /* Reset the OC4PE Bit */
+  tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC4PE);
+  /* Enable or Disable the Output Compare Preload feature */
+  tmpccmr2 |= (uint16_t)(TIM_OCPreload << 8);
+  /* Write to TIMx CCMR2 register */
+  TIMx->CCMR2 = tmpccmr2;
+}
+
+/**
+  * @brief  Configures the TIMx Output Compare 1 Fast feature.
+  * @param  TIMx: where x can be  1 to 17 except 6 and 7 to select the TIM peripheral.
+  * @param  TIM_OCFast: new state of the Output Compare Fast Enable Bit.
+  *   This parameter can be one of the following values:
+  *     @arg TIM_OCFast_Enable: TIM output compare fast enable
+  *     @arg TIM_OCFast_Disable: TIM output compare fast disable
+  * @retval None
+  */
+void TIM_OC1FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast)
+{
+  uint16_t tmpccmr1 = 0;
+  /* Check the parameters */
+  assert_param(IS_TIM_LIST8_PERIPH(TIMx));
+  assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast));
+  /* Get the TIMx CCMR1 register value */
+  tmpccmr1 = TIMx->CCMR1;
+  /* Reset the OC1FE Bit */
+  tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC1FE);
+  /* Enable or Disable the Output Compare Fast Bit */
+  tmpccmr1 |= TIM_OCFast;
+  /* Write to TIMx CCMR1 */
+  TIMx->CCMR1 = tmpccmr1;
+}
+
+/**
+  * @brief  Configures the TIMx Output Compare 2 Fast feature.
+  * @param  TIMx: where x can be  1, 2, 3, 4, 5, 8, 9, 12 or 15 to select 
+  *         the TIM peripheral.
+  * @param  TIM_OCFast: new state of the Output Compare Fast Enable Bit.
+  *   This parameter can be one of the following values:
+  *     @arg TIM_OCFast_Enable: TIM output compare fast enable
+  *     @arg TIM_OCFast_Disable: TIM output compare fast disable
+  * @retval None
+  */
+void TIM_OC2FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast)
+{
+  uint16_t tmpccmr1 = 0;
+  /* Check the parameters */
+  assert_param(IS_TIM_LIST6_PERIPH(TIMx));
+  assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast));
+  /* Get the TIMx CCMR1 register value */
+  tmpccmr1 = TIMx->CCMR1;
+  /* Reset the OC2FE Bit */
+  tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC2FE);
+  /* Enable or Disable the Output Compare Fast Bit */
+  tmpccmr1 |= (uint16_t)(TIM_OCFast << 8);
+  /* Write to TIMx CCMR1 */
+  TIMx->CCMR1 = tmpccmr1;
+}
+
+/**
+  * @brief  Configures the TIMx Output Compare 3 Fast feature.
+  * @param  TIMx: where x can be  1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+  * @param  TIM_OCFast: new state of the Output Compare Fast Enable Bit.
+  *   This parameter can be one of the following values:
+  *     @arg TIM_OCFast_Enable: TIM output compare fast enable
+  *     @arg TIM_OCFast_Disable: TIM output compare fast disable
+  * @retval None
+  */
+void TIM_OC3FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast)
+{
+  uint16_t tmpccmr2 = 0;
+  /* Check the parameters */
+  assert_param(IS_TIM_LIST3_PERIPH(TIMx));
+  assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast));
+  /* Get the TIMx CCMR2 register value */
+  tmpccmr2 = TIMx->CCMR2;
+  /* Reset the OC3FE Bit */
+  tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC3FE);
+  /* Enable or Disable the Output Compare Fast Bit */
+  tmpccmr2 |= TIM_OCFast;
+  /* Write to TIMx CCMR2 */
+  TIMx->CCMR2 = tmpccmr2;
+}
+
+/**
+  * @brief  Configures the TIMx Output Compare 4 Fast feature.
+  * @param  TIMx: where x can be  1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+  * @param  TIM_OCFast: new state of the Output Compare Fast Enable Bit.
+  *   This parameter can be one of the following values:
+  *     @arg TIM_OCFast_Enable: TIM output compare fast enable
+  *     @arg TIM_OCFast_Disable: TIM output compare fast disable
+  * @retval None
+  */
+void TIM_OC4FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast)
+{
+  uint16_t tmpccmr2 = 0;
+  /* Check the parameters */
+  assert_param(IS_TIM_LIST3_PERIPH(TIMx));
+  assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast));
+  /* Get the TIMx CCMR2 register value */
+  tmpccmr2 = TIMx->CCMR2;
+  /* Reset the OC4FE Bit */
+  tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC4FE);
+  /* Enable or Disable the Output Compare Fast Bit */
+  tmpccmr2 |= (uint16_t)(TIM_OCFast << 8);
+  /* Write to TIMx CCMR2 */
+  TIMx->CCMR2 = tmpccmr2;
+}
+
+/**
+  * @brief  Clears or safeguards the OCREF1 signal on an external event
+  * @param  TIMx: where x can be  1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+  * @param  TIM_OCClear: new state of the Output Compare Clear Enable Bit.
+  *   This parameter can be one of the following values:
+  *     @arg TIM_OCClear_Enable: TIM Output clear enable
+  *     @arg TIM_OCClear_Disable: TIM Output clear disable
+  * @retval None
+  */
+void TIM_ClearOC1Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear)
+{
+  uint16_t tmpccmr1 = 0;
+  /* Check the parameters */
+  assert_param(IS_TIM_LIST3_PERIPH(TIMx));
+  assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear));
+
+  tmpccmr1 = TIMx->CCMR1;
+
+  /* Reset the OC1CE Bit */
+  tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC1CE);
+  /* Enable or Disable the Output Compare Clear Bit */
+  tmpccmr1 |= TIM_OCClear;
+  /* Write to TIMx CCMR1 register */
+  TIMx->CCMR1 = tmpccmr1;
+}
+
+/**
+  * @brief  Clears or safeguards the OCREF2 signal on an external event
+  * @param  TIMx: where x can be  1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+  * @param  TIM_OCClear: new state of the Output Compare Clear Enable Bit.
+  *   This parameter can be one of the following values:
+  *     @arg TIM_OCClear_Enable: TIM Output clear enable
+  *     @arg TIM_OCClear_Disable: TIM Output clear disable
+  * @retval None
+  */
+void TIM_ClearOC2Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear)
+{
+  uint16_t tmpccmr1 = 0;
+  /* Check the parameters */
+  assert_param(IS_TIM_LIST3_PERIPH(TIMx));
+  assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear));
+  tmpccmr1 = TIMx->CCMR1;
+  /* Reset the OC2CE Bit */
+  tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC2CE);
+  /* Enable or Disable the Output Compare Clear Bit */
+  tmpccmr1 |= (uint16_t)(TIM_OCClear << 8);
+  /* Write to TIMx CCMR1 register */
+  TIMx->CCMR1 = tmpccmr1;
+}
+
+/**
+  * @brief  Clears or safeguards the OCREF3 signal on an external event
+  * @param  TIMx: where x can be  1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+  * @param  TIM_OCClear: new state of the Output Compare Clear Enable Bit.
+  *   This parameter can be one of the following values:
+  *     @arg TIM_OCClear_Enable: TIM Output clear enable
+  *     @arg TIM_OCClear_Disable: TIM Output clear disable
+  * @retval None
+  */
+void TIM_ClearOC3Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear)
+{
+  uint16_t tmpccmr2 = 0;
+  /* Check the parameters */
+  assert_param(IS_TIM_LIST3_PERIPH(TIMx));
+  assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear));
+  tmpccmr2 = TIMx->CCMR2;
+  /* Reset the OC3CE Bit */
+  tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC3CE);
+  /* Enable or Disable the Output Compare Clear Bit */
+  tmpccmr2 |= TIM_OCClear;
+  /* Write to TIMx CCMR2 register */
+  TIMx->CCMR2 = tmpccmr2;
+}
+
+/**
+  * @brief  Clears or safeguards the OCREF4 signal on an external event
+  * @param  TIMx: where x can be  1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+  * @param  TIM_OCClear: new state of the Output Compare Clear Enable Bit.
+  *   This parameter can be one of the following values:
+  *     @arg TIM_OCClear_Enable: TIM Output clear enable
+  *     @arg TIM_OCClear_Disable: TIM Output clear disable
+  * @retval None
+  */
+void TIM_ClearOC4Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear)
+{
+  uint16_t tmpccmr2 = 0;
+  /* Check the parameters */
+  assert_param(IS_TIM_LIST3_PERIPH(TIMx));
+  assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear));
+  tmpccmr2 = TIMx->CCMR2;
+  /* Reset the OC4CE Bit */
+  tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC4CE);
+  /* Enable or Disable the Output Compare Clear Bit */
+  tmpccmr2 |= (uint16_t)(TIM_OCClear << 8);
+  /* Write to TIMx CCMR2 register */
+  TIMx->CCMR2 = tmpccmr2;
+}
+
+/**
+  * @brief  Configures the TIMx channel 1 polarity.
+  * @param  TIMx: where x can be 1 to 17 except 6 and 7 to select the TIM peripheral.
+  * @param  TIM_OCPolarity: specifies the OC1 Polarity
+  *   This parameter can be one of the following values:
+  *     @arg TIM_OCPolarity_High: Output Compare active high
+  *     @arg TIM_OCPolarity_Low: Output Compare active low
+  * @retval None
+  */
+void TIM_OC1PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity)
+{
+  uint16_t tmpccer = 0;
+  /* Check the parameters */
+  assert_param(IS_TIM_LIST8_PERIPH(TIMx));
+  assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity));
+  tmpccer = TIMx->CCER;
+  /* Set or Reset the CC1P Bit */
+  tmpccer &= (uint16_t)~((uint16_t)TIM_CCER_CC1P);
+  tmpccer |= TIM_OCPolarity;
+  /* Write to TIMx CCER register */
+  TIMx->CCER = tmpccer;
+}
+
+/**
+  * @brief  Configures the TIMx Channel 1N polarity.
+  * @param  TIMx: where x can be 1, 8, 15, 16 or 17 to select the TIM peripheral.
+  * @param  TIM_OCNPolarity: specifies the OC1N Polarity
+  *   This parameter can be one of the following values:
+  *     @arg TIM_OCNPolarity_High: Output Compare active high
+  *     @arg TIM_OCNPolarity_Low: Output Compare active low
+  * @retval None
+  */
+void TIM_OC1NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity)
+{
+  uint16_t tmpccer = 0;
+  /* Check the parameters */
+  assert_param(IS_TIM_LIST2_PERIPH(TIMx));
+  assert_param(IS_TIM_OCN_POLARITY(TIM_OCNPolarity));
+   
+  tmpccer = TIMx->CCER;
+  /* Set or Reset the CC1NP Bit */
+  tmpccer &= (uint16_t)~((uint16_t)TIM_CCER_CC1NP);
+  tmpccer |= TIM_OCNPolarity;
+  /* Write to TIMx CCER register */
+  TIMx->CCER = tmpccer;
+}
+
+/**
+  * @brief  Configures the TIMx channel 2 polarity.
+  * @param  TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select the TIM peripheral.
+  * @param  TIM_OCPolarity: specifies the OC2 Polarity
+  *   This parameter can be one of the following values:
+  *     @arg TIM_OCPolarity_High: Output Compare active high
+  *     @arg TIM_OCPolarity_Low: Output Compare active low
+  * @retval None
+  */
+void TIM_OC2PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity)
+{
+  uint16_t tmpccer = 0;
+  /* Check the parameters */
+  assert_param(IS_TIM_LIST6_PERIPH(TIMx));
+  assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity));
+  tmpccer = TIMx->CCER;
+  /* Set or Reset the CC2P Bit */
+  tmpccer &= (uint16_t)~((uint16_t)TIM_CCER_CC2P);
+  tmpccer |= (uint16_t)(TIM_OCPolarity << 4);
+  /* Write to TIMx CCER register */
+  TIMx->CCER = tmpccer;
+}
+
+/**
+  * @brief  Configures the TIMx Channel 2N polarity.
+  * @param  TIMx: where x can be 1 or 8 to select the TIM peripheral.
+  * @param  TIM_OCNPolarity: specifies the OC2N Polarity
+  *   This parameter can be one of the following values:
+  *     @arg TIM_OCNPolarity_High: Output Compare active high
+  *     @arg TIM_OCNPolarity_Low: Output Compare active low
+  * @retval None
+  */
+void TIM_OC2NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity)
+{
+  uint16_t tmpccer = 0;
+  /* Check the parameters */
+  assert_param(IS_TIM_LIST1_PERIPH(TIMx));
+  assert_param(IS_TIM_OCN_POLARITY(TIM_OCNPolarity));
+  
+  tmpccer = TIMx->CCER;
+  /* Set or Reset the CC2NP Bit */
+  tmpccer &= (uint16_t)~((uint16_t)TIM_CCER_CC2NP);
+  tmpccer |= (uint16_t)(TIM_OCNPolarity << 4);
+  /* Write to TIMx CCER register */
+  TIMx->CCER = tmpccer;
+}
+
+/**
+  * @brief  Configures the TIMx channel 3 polarity.
+  * @param  TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+  * @param  TIM_OCPolarity: specifies the OC3 Polarity
+  *   This parameter can be one of the following values:
+  *     @arg TIM_OCPolarity_High: Output Compare active high
+  *     @arg TIM_OCPolarity_Low: Output Compare active low
+  * @retval None
+  */
+void TIM_OC3PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity)
+{
+  uint16_t tmpccer = 0;
+  /* Check the parameters */
+  assert_param(IS_TIM_LIST3_PERIPH(TIMx));
+  assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity));
+  tmpccer = TIMx->CCER;
+  /* Set or Reset the CC3P Bit */
+  tmpccer &= (uint16_t)~((uint16_t)TIM_CCER_CC3P);
+  tmpccer |= (uint16_t)(TIM_OCPolarity << 8);
+  /* Write to TIMx CCER register */
+  TIMx->CCER = tmpccer;
+}
+
+/**
+  * @brief  Configures the TIMx Channel 3N polarity.
+  * @param  TIMx: where x can be 1 or 8 to select the TIM peripheral.
+  * @param  TIM_OCNPolarity: specifies the OC3N Polarity
+  *   This parameter can be one of the following values:
+  *     @arg TIM_OCNPolarity_High: Output Compare active high
+  *     @arg TIM_OCNPolarity_Low: Output Compare active low
+  * @retval None
+  */
+void TIM_OC3NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity)
+{
+  uint16_t tmpccer = 0;
+ 
+  /* Check the parameters */
+  assert_param(IS_TIM_LIST1_PERIPH(TIMx));
+  assert_param(IS_TIM_OCN_POLARITY(TIM_OCNPolarity));
+    
+  tmpccer = TIMx->CCER;
+  /* Set or Reset the CC3NP Bit */
+  tmpccer &= (uint16_t)~((uint16_t)TIM_CCER_CC3NP);
+  tmpccer |= (uint16_t)(TIM_OCNPolarity << 8);
+  /* Write to TIMx CCER register */
+  TIMx->CCER = tmpccer;
+}
+
+/**
+  * @brief  Configures the TIMx channel 4 polarity.
+  * @param  TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+  * @param  TIM_OCPolarity: specifies the OC4 Polarity
+  *   This parameter can be one of the following values:
+  *     @arg TIM_OCPolarity_High: Output Compare active high
+  *     @arg TIM_OCPolarity_Low: Output Compare active low
+  * @retval None
+  */
+void TIM_OC4PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity)
+{
+  uint16_t tmpccer = 0;
+  /* Check the parameters */
+  assert_param(IS_TIM_LIST3_PERIPH(TIMx));
+  assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity));
+  tmpccer = TIMx->CCER;
+  /* Set or Reset the CC4P Bit */
+  tmpccer &= (uint16_t)~((uint16_t)TIM_CCER_CC4P);
+  tmpccer |= (uint16_t)(TIM_OCPolarity << 12);
+  /* Write to TIMx CCER register */
+  TIMx->CCER = tmpccer;
+}
+
+/**
+  * @brief  Enables or disables the TIM Capture Compare Channel x.
+  * @param  TIMx: where x can be 1 to 17 except 6 and 7 to select the TIM peripheral.
+  * @param  TIM_Channel: specifies the TIM Channel
+  *   This parameter can be one of the following values:
+  *     @arg TIM_Channel_1: TIM Channel 1
+  *     @arg TIM_Channel_2: TIM Channel 2
+  *     @arg TIM_Channel_3: TIM Channel 3
+  *     @arg TIM_Channel_4: TIM Channel 4
+  * @param  TIM_CCx: specifies the TIM Channel CCxE bit new state.
+  *   This parameter can be: TIM_CCx_Enable or TIM_CCx_Disable. 
+  * @retval None
+  */
+void TIM_CCxCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCx)
+{
+  uint16_t tmp = 0;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_LIST8_PERIPH(TIMx));
+  assert_param(IS_TIM_CHANNEL(TIM_Channel));
+  assert_param(IS_TIM_CCX(TIM_CCx));
+
+  tmp = CCER_CCE_Set << TIM_Channel;
+
+  /* Reset the CCxE Bit */
+  TIMx->CCER &= (uint16_t)~ tmp;
+
+  /* Set or reset the CCxE Bit */ 
+  TIMx->CCER |=  (uint16_t)(TIM_CCx << TIM_Channel);
+}
+
+/**
+  * @brief  Enables or disables the TIM Capture Compare Channel xN.
+  * @param  TIMx: where x can be 1, 8, 15, 16 or 17 to select the TIM peripheral.
+  * @param  TIM_Channel: specifies the TIM Channel
+  *   This parameter can be one of the following values:
+  *     @arg TIM_Channel_1: TIM Channel 1
+  *     @arg TIM_Channel_2: TIM Channel 2
+  *     @arg TIM_Channel_3: TIM Channel 3
+  * @param  TIM_CCxN: specifies the TIM Channel CCxNE bit new state.
+  *   This parameter can be: TIM_CCxN_Enable or TIM_CCxN_Disable. 
+  * @retval None
+  */
+void TIM_CCxNCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCxN)
+{
+  uint16_t tmp = 0;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_LIST2_PERIPH(TIMx));
+  assert_param(IS_TIM_COMPLEMENTARY_CHANNEL(TIM_Channel));
+  assert_param(IS_TIM_CCXN(TIM_CCxN));
+
+  tmp = CCER_CCNE_Set << TIM_Channel;
+
+  /* Reset the CCxNE Bit */
+  TIMx->CCER &= (uint16_t) ~tmp;
+
+  /* Set or reset the CCxNE Bit */ 
+  TIMx->CCER |=  (uint16_t)(TIM_CCxN << TIM_Channel);
+}
+
+/**
+  * @brief  Selects the TIM Output Compare Mode.
+  * @note   This function disables the selected channel before changing the Output
+  *         Compare Mode.
+  *         User has to enable this channel using TIM_CCxCmd and TIM_CCxNCmd functions.
+  * @param  TIMx: where x can be 1 to 17 except 6 and 7 to select the TIM peripheral.
+  * @param  TIM_Channel: specifies the TIM Channel
+  *   This parameter can be one of the following values:
+  *     @arg TIM_Channel_1: TIM Channel 1
+  *     @arg TIM_Channel_2: TIM Channel 2
+  *     @arg TIM_Channel_3: TIM Channel 3
+  *     @arg TIM_Channel_4: TIM Channel 4
+  * @param  TIM_OCMode: specifies the TIM Output Compare Mode.
+  *   This parameter can be one of the following values:
+  *     @arg TIM_OCMode_Timing
+  *     @arg TIM_OCMode_Active
+  *     @arg TIM_OCMode_Toggle
+  *     @arg TIM_OCMode_PWM1
+  *     @arg TIM_OCMode_PWM2
+  *     @arg TIM_ForcedAction_Active
+  *     @arg TIM_ForcedAction_InActive
+  * @retval None
+  */
+void TIM_SelectOCxM(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_OCMode)
+{
+  uint32_t tmp = 0;
+  uint16_t tmp1 = 0;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_LIST8_PERIPH(TIMx));
+  assert_param(IS_TIM_CHANNEL(TIM_Channel));
+  assert_param(IS_TIM_OCM(TIM_OCMode));
+
+  tmp = (uint32_t) TIMx;
+  tmp += CCMR_Offset;
+
+  tmp1 = CCER_CCE_Set << (uint16_t)TIM_Channel;
+
+  /* Disable the Channel: Reset the CCxE Bit */
+  TIMx->CCER &= (uint16_t) ~tmp1;
+
+  if((TIM_Channel == TIM_Channel_1) ||(TIM_Channel == TIM_Channel_3))
+  {
+    tmp += (TIM_Channel>>1);
+
+    /* Reset the OCxM bits in the CCMRx register */
+    *(__IO uint32_t *) tmp &= (uint32_t)~((uint32_t)TIM_CCMR1_OC1M);
+   
+    /* Configure the OCxM bits in the CCMRx register */
+    *(__IO uint32_t *) tmp |= TIM_OCMode;
+  }
+  else
+  {
+    tmp += (uint16_t)(TIM_Channel - (uint16_t)4)>> (uint16_t)1;
+
+    /* Reset the OCxM bits in the CCMRx register */
+    *(__IO uint32_t *) tmp &= (uint32_t)~((uint32_t)TIM_CCMR1_OC2M);
+    
+    /* Configure the OCxM bits in the CCMRx register */
+    *(__IO uint32_t *) tmp |= (uint16_t)(TIM_OCMode << 8);
+  }
+}
+
+/**
+  * @brief  Enables or Disables the TIMx Update event.
+  * @param  TIMx: where x can be 1 to 17 to select the TIM peripheral.
+  * @param  NewState: new state of the TIMx UDIS bit
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void TIM_UpdateDisableConfig(TIM_TypeDef* TIMx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_ALL_PERIPH(TIMx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  if (NewState != DISABLE)
+  {
+    /* Set the Update Disable Bit */
+    TIMx->CR1 |= TIM_CR1_UDIS;
+  }
+  else
+  {
+    /* Reset the Update Disable Bit */
+    TIMx->CR1 &= (uint16_t)~((uint16_t)TIM_CR1_UDIS);
+  }
+}
+
+/**
+  * @brief  Configures the TIMx Update Request Interrupt source.
+  * @param  TIMx: where x can be 1 to 17 to select the TIM peripheral.
+  * @param  TIM_UpdateSource: specifies the Update source.
+  *   This parameter can be one of the following values:
+  *     @arg TIM_UpdateSource_Regular: Source of update is the counter overflow/underflow
+                                       or the setting of UG bit, or an update generation
+                                       through the slave mode controller.
+  *     @arg TIM_UpdateSource_Global: Source of update is counter overflow/underflow.
+  * @retval None
+  */
+void TIM_UpdateRequestConfig(TIM_TypeDef* TIMx, uint16_t TIM_UpdateSource)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_ALL_PERIPH(TIMx));
+  assert_param(IS_TIM_UPDATE_SOURCE(TIM_UpdateSource));
+  if (TIM_UpdateSource != TIM_UpdateSource_Global)
+  {
+    /* Set the URS Bit */
+    TIMx->CR1 |= TIM_CR1_URS;
+  }
+  else
+  {
+    /* Reset the URS Bit */
+    TIMx->CR1 &= (uint16_t)~((uint16_t)TIM_CR1_URS);
+  }
+}
+
+/**
+  * @brief  Enables or disables the TIMx's Hall sensor interface.
+  * @param  TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+  * @param  NewState: new state of the TIMx Hall sensor interface.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void TIM_SelectHallSensor(TIM_TypeDef* TIMx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_LIST6_PERIPH(TIMx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  if (NewState != DISABLE)
+  {
+    /* Set the TI1S Bit */
+    TIMx->CR2 |= TIM_CR2_TI1S;
+  }
+  else
+  {
+    /* Reset the TI1S Bit */
+    TIMx->CR2 &= (uint16_t)~((uint16_t)TIM_CR2_TI1S);
+  }
+}
+
+/**
+  * @brief  Selects the TIMx's One Pulse Mode.
+  * @param  TIMx: where x can be 1 to 17 to select the TIM peripheral.
+  * @param  TIM_OPMode: specifies the OPM Mode to be used.
+  *   This parameter can be one of the following values:
+  *     @arg TIM_OPMode_Single
+  *     @arg TIM_OPMode_Repetitive
+  * @retval None
+  */
+void TIM_SelectOnePulseMode(TIM_TypeDef* TIMx, uint16_t TIM_OPMode)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_ALL_PERIPH(TIMx));
+  assert_param(IS_TIM_OPM_MODE(TIM_OPMode));
+  /* Reset the OPM Bit */
+  TIMx->CR1 &= (uint16_t)~((uint16_t)TIM_CR1_OPM);
+  /* Configure the OPM Mode */
+  TIMx->CR1 |= TIM_OPMode;
+}
+
+/**
+  * @brief  Selects the TIMx Trigger Output Mode.
+  * @param  TIMx: where x can be 1, 2, 3, 4, 5, 6, 7, 8, 9, 12 or 15 to select the TIM peripheral.
+  * @param  TIM_TRGOSource: specifies the Trigger Output source.
+  *   This paramter can be one of the following values:
+  *
+  *  - For all TIMx
+  *     @arg TIM_TRGOSource_Reset:  The UG bit in the TIM_EGR register is used as the trigger output (TRGO).
+  *     @arg TIM_TRGOSource_Enable: The Counter Enable CEN is used as the trigger output (TRGO).
+  *     @arg TIM_TRGOSource_Update: The update event is selected as the trigger output (TRGO).
+  *
+  *  - For all TIMx except TIM6 and TIM7
+  *     @arg TIM_TRGOSource_OC1: The trigger output sends a positive pulse when the CC1IF flag
+  *                              is to be set, as soon as a capture or compare match occurs (TRGO).
+  *     @arg TIM_TRGOSource_OC1Ref: OC1REF signal is used as the trigger output (TRGO).
+  *     @arg TIM_TRGOSource_OC2Ref: OC2REF signal is used as the trigger output (TRGO).
+  *     @arg TIM_TRGOSource_OC3Ref: OC3REF signal is used as the trigger output (TRGO).
+  *     @arg TIM_TRGOSource_OC4Ref: OC4REF signal is used as the trigger output (TRGO).
+  *
+  * @retval None
+  */
+void TIM_SelectOutputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_TRGOSource)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_LIST7_PERIPH(TIMx));
+  assert_param(IS_TIM_TRGO_SOURCE(TIM_TRGOSource));
+  /* Reset the MMS Bits */
+  TIMx->CR2 &= (uint16_t)~((uint16_t)TIM_CR2_MMS);
+  /* Select the TRGO source */
+  TIMx->CR2 |=  TIM_TRGOSource;
+}
+
+/**
+  * @brief  Selects the TIMx Slave Mode.
+  * @param  TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select the TIM peripheral.
+  * @param  TIM_SlaveMode: specifies the Timer Slave Mode.
+  *   This parameter can be one of the following values:
+  *     @arg TIM_SlaveMode_Reset: Rising edge of the selected trigger signal (TRGI) re-initializes
+  *                               the counter and triggers an update of the registers.
+  *     @arg TIM_SlaveMode_Gated:     The counter clock is enabled when the trigger signal (TRGI) is high.
+  *     @arg TIM_SlaveMode_Trigger:   The counter starts at a rising edge of the trigger TRGI.
+  *     @arg TIM_SlaveMode_External1: Rising edges of the selected trigger (TRGI) clock the counter.
+  * @retval None
+  */
+void TIM_SelectSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_SlaveMode)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_LIST6_PERIPH(TIMx));
+  assert_param(IS_TIM_SLAVE_MODE(TIM_SlaveMode));
+ /* Reset the SMS Bits */
+  TIMx->SMCR &= (uint16_t)~((uint16_t)TIM_SMCR_SMS);
+  /* Select the Slave Mode */
+  TIMx->SMCR |= TIM_SlaveMode;
+}
+
+/**
+  * @brief  Sets or Resets the TIMx Master/Slave Mode.
+  * @param  TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select the TIM peripheral.
+  * @param  TIM_MasterSlaveMode: specifies the Timer Master Slave Mode.
+  *   This parameter can be one of the following values:
+  *     @arg TIM_MasterSlaveMode_Enable: synchronization between the current timer
+  *                                      and its slaves (through TRGO).
+  *     @arg TIM_MasterSlaveMode_Disable: No action
+  * @retval None
+  */
+void TIM_SelectMasterSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_MasterSlaveMode)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_LIST6_PERIPH(TIMx));
+  assert_param(IS_TIM_MSM_STATE(TIM_MasterSlaveMode));
+  /* Reset the MSM Bit */
+  TIMx->SMCR &= (uint16_t)~((uint16_t)TIM_SMCR_MSM);
+  
+  /* Set or Reset the MSM Bit */
+  TIMx->SMCR |= TIM_MasterSlaveMode;
+}
+
+/**
+  * @brief  Sets the TIMx Counter Register value
+  * @param  TIMx: where x can be 1 to 17 to select the TIM peripheral.
+  * @param  Counter: specifies the Counter register new value.
+  * @retval None
+  */
+void TIM_SetCounter(TIM_TypeDef* TIMx, uint16_t Counter)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_ALL_PERIPH(TIMx));
+  /* Set the Counter Register value */
+  TIMx->CNT = Counter;
+}
+
+/**
+  * @brief  Sets the TIMx Autoreload Register value
+  * @param  TIMx: where x can be 1 to 17 to select the TIM peripheral.
+  * @param  Autoreload: specifies the Autoreload register new value.
+  * @retval None
+  */
+void TIM_SetAutoreload(TIM_TypeDef* TIMx, uint16_t Autoreload)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_ALL_PERIPH(TIMx));
+  /* Set the Autoreload Register value */
+  TIMx->ARR = Autoreload;
+}
+
+/**
+  * @brief  Sets the TIMx Capture Compare1 Register value
+  * @param  TIMx: where x can be 1 to 17 except 6 and 7 to select the TIM peripheral.
+  * @param  Compare1: specifies the Capture Compare1 register new value.
+  * @retval None
+  */
+void TIM_SetCompare1(TIM_TypeDef* TIMx, uint16_t Compare1)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_LIST8_PERIPH(TIMx));
+  /* Set the Capture Compare1 Register value */
+  TIMx->CCR1 = Compare1;
+}
+
+/**
+  * @brief  Sets the TIMx Capture Compare2 Register value
+  * @param  TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select the TIM peripheral.
+  * @param  Compare2: specifies the Capture Compare2 register new value.
+  * @retval None
+  */
+void TIM_SetCompare2(TIM_TypeDef* TIMx, uint16_t Compare2)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_LIST6_PERIPH(TIMx));
+  /* Set the Capture Compare2 Register value */
+  TIMx->CCR2 = Compare2;
+}
+
+/**
+  * @brief  Sets the TIMx Capture Compare3 Register value
+  * @param  TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+  * @param  Compare3: specifies the Capture Compare3 register new value.
+  * @retval None
+  */
+void TIM_SetCompare3(TIM_TypeDef* TIMx, uint16_t Compare3)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_LIST3_PERIPH(TIMx));
+  /* Set the Capture Compare3 Register value */
+  TIMx->CCR3 = Compare3;
+}
+
+/**
+  * @brief  Sets the TIMx Capture Compare4 Register value
+  * @param  TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+  * @param  Compare4: specifies the Capture Compare4 register new value.
+  * @retval None
+  */
+void TIM_SetCompare4(TIM_TypeDef* TIMx, uint16_t Compare4)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_LIST3_PERIPH(TIMx));
+  /* Set the Capture Compare4 Register value */
+  TIMx->CCR4 = Compare4;
+}
+
+/**
+  * @brief  Sets the TIMx Input Capture 1 prescaler.
+  * @param  TIMx: where x can be 1 to 17 except 6 and 7 to select the TIM peripheral.
+  * @param  TIM_ICPSC: specifies the Input Capture1 prescaler new value.
+  *   This parameter can be one of the following values:
+  *     @arg TIM_ICPSC_DIV1: no prescaler
+  *     @arg TIM_ICPSC_DIV2: capture is done once every 2 events
+  *     @arg TIM_ICPSC_DIV4: capture is done once every 4 events
+  *     @arg TIM_ICPSC_DIV8: capture is done once every 8 events
+  * @retval None
+  */
+void TIM_SetIC1Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_LIST8_PERIPH(TIMx));
+  assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC));
+  /* Reset the IC1PSC Bits */
+  TIMx->CCMR1 &= (uint16_t)~((uint16_t)TIM_CCMR1_IC1PSC);
+  /* Set the IC1PSC value */
+  TIMx->CCMR1 |= TIM_ICPSC;
+}
+
+/**
+  * @brief  Sets the TIMx Input Capture 2 prescaler.
+  * @param  TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select the TIM peripheral.
+  * @param  TIM_ICPSC: specifies the Input Capture2 prescaler new value.
+  *   This parameter can be one of the following values:
+  *     @arg TIM_ICPSC_DIV1: no prescaler
+  *     @arg TIM_ICPSC_DIV2: capture is done once every 2 events
+  *     @arg TIM_ICPSC_DIV4: capture is done once every 4 events
+  *     @arg TIM_ICPSC_DIV8: capture is done once every 8 events
+  * @retval None
+  */
+void TIM_SetIC2Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_LIST6_PERIPH(TIMx));
+  assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC));
+  /* Reset the IC2PSC Bits */
+  TIMx->CCMR1 &= (uint16_t)~((uint16_t)TIM_CCMR1_IC2PSC);
+  /* Set the IC2PSC value */
+  TIMx->CCMR1 |= (uint16_t)(TIM_ICPSC << 8);
+}
+
+/**
+  * @brief  Sets the TIMx Input Capture 3 prescaler.
+  * @param  TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+  * @param  TIM_ICPSC: specifies the Input Capture3 prescaler new value.
+  *   This parameter can be one of the following values:
+  *     @arg TIM_ICPSC_DIV1: no prescaler
+  *     @arg TIM_ICPSC_DIV2: capture is done once every 2 events
+  *     @arg TIM_ICPSC_DIV4: capture is done once every 4 events
+  *     @arg TIM_ICPSC_DIV8: capture is done once every 8 events
+  * @retval None
+  */
+void TIM_SetIC3Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_LIST3_PERIPH(TIMx));
+  assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC));
+  /* Reset the IC3PSC Bits */
+  TIMx->CCMR2 &= (uint16_t)~((uint16_t)TIM_CCMR2_IC3PSC);
+  /* Set the IC3PSC value */
+  TIMx->CCMR2 |= TIM_ICPSC;
+}
+
+/**
+  * @brief  Sets the TIMx Input Capture 4 prescaler.
+  * @param  TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+  * @param  TIM_ICPSC: specifies the Input Capture4 prescaler new value.
+  *   This parameter can be one of the following values:
+  *     @arg TIM_ICPSC_DIV1: no prescaler
+  *     @arg TIM_ICPSC_DIV2: capture is done once every 2 events
+  *     @arg TIM_ICPSC_DIV4: capture is done once every 4 events
+  *     @arg TIM_ICPSC_DIV8: capture is done once every 8 events
+  * @retval None
+  */
+void TIM_SetIC4Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC)
+{  
+  /* Check the parameters */
+  assert_param(IS_TIM_LIST3_PERIPH(TIMx));
+  assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC));
+  /* Reset the IC4PSC Bits */
+  TIMx->CCMR2 &= (uint16_t)~((uint16_t)TIM_CCMR2_IC4PSC);
+  /* Set the IC4PSC value */
+  TIMx->CCMR2 |= (uint16_t)(TIM_ICPSC << 8);
+}
+
+/**
+  * @brief  Sets the TIMx Clock Division value.
+  * @param  TIMx: where x can be  1 to 17 except 6 and 7 to select 
+  *   the TIM peripheral.
+  * @param  TIM_CKD: specifies the clock division value.
+  *   This parameter can be one of the following value:
+  *     @arg TIM_CKD_DIV1: TDTS = Tck_tim
+  *     @arg TIM_CKD_DIV2: TDTS = 2*Tck_tim
+  *     @arg TIM_CKD_DIV4: TDTS = 4*Tck_tim
+  * @retval None
+  */
+void TIM_SetClockDivision(TIM_TypeDef* TIMx, uint16_t TIM_CKD)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_LIST8_PERIPH(TIMx));
+  assert_param(IS_TIM_CKD_DIV(TIM_CKD));
+  /* Reset the CKD Bits */
+  TIMx->CR1 &= (uint16_t)~((uint16_t)TIM_CR1_CKD);
+  /* Set the CKD value */
+  TIMx->CR1 |= TIM_CKD;
+}
+
+/**
+  * @brief  Gets the TIMx Input Capture 1 value.
+  * @param  TIMx: where x can be 1 to 17 except 6 and 7 to select the TIM peripheral.
+  * @retval Capture Compare 1 Register value.
+  */
+uint16_t TIM_GetCapture1(TIM_TypeDef* TIMx)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_LIST8_PERIPH(TIMx));
+  /* Get the Capture 1 Register value */
+  return TIMx->CCR1;
+}
+
+/**
+  * @brief  Gets the TIMx Input Capture 2 value.
+  * @param  TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select the TIM peripheral.
+  * @retval Capture Compare 2 Register value.
+  */
+uint16_t TIM_GetCapture2(TIM_TypeDef* TIMx)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_LIST6_PERIPH(TIMx));
+  /* Get the Capture 2 Register value */
+  return TIMx->CCR2;
+}
+
+/**
+  * @brief  Gets the TIMx Input Capture 3 value.
+  * @param  TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+  * @retval Capture Compare 3 Register value.
+  */
+uint16_t TIM_GetCapture3(TIM_TypeDef* TIMx)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_LIST3_PERIPH(TIMx)); 
+  /* Get the Capture 3 Register value */
+  return TIMx->CCR3;
+}
+
+/**
+  * @brief  Gets the TIMx Input Capture 4 value.
+  * @param  TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+  * @retval Capture Compare 4 Register value.
+  */
+uint16_t TIM_GetCapture4(TIM_TypeDef* TIMx)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_LIST3_PERIPH(TIMx));
+  /* Get the Capture 4 Register value */
+  return TIMx->CCR4;
+}
+
+/**
+  * @brief  Gets the TIMx Counter value.
+  * @param  TIMx: where x can be 1 to 17 to select the TIM peripheral.
+  * @retval Counter Register value.
+  */
+uint16_t TIM_GetCounter(TIM_TypeDef* TIMx)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_ALL_PERIPH(TIMx));
+  /* Get the Counter Register value */
+  return TIMx->CNT;
+}
+
+/**
+  * @brief  Gets the TIMx Prescaler value.
+  * @param  TIMx: where x can be 1 to 17 to select the TIM peripheral.
+  * @retval Prescaler Register value.
+  */
+uint16_t TIM_GetPrescaler(TIM_TypeDef* TIMx)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_ALL_PERIPH(TIMx));
+  /* Get the Prescaler Register value */
+  return TIMx->PSC;
+}
+
+/**
+  * @brief  Checks whether the specified TIM flag is set or not.
+  * @param  TIMx: where x can be 1 to 17 to select the TIM peripheral.
+  * @param  TIM_FLAG: specifies the flag to check.
+  *   This parameter can be one of the following values:
+  *     @arg TIM_FLAG_Update: TIM update Flag
+  *     @arg TIM_FLAG_CC1: TIM Capture Compare 1 Flag
+  *     @arg TIM_FLAG_CC2: TIM Capture Compare 2 Flag
+  *     @arg TIM_FLAG_CC3: TIM Capture Compare 3 Flag
+  *     @arg TIM_FLAG_CC4: TIM Capture Compare 4 Flag
+  *     @arg TIM_FLAG_COM: TIM Commutation Flag
+  *     @arg TIM_FLAG_Trigger: TIM Trigger Flag
+  *     @arg TIM_FLAG_Break: TIM Break Flag
+  *     @arg TIM_FLAG_CC1OF: TIM Capture Compare 1 overcapture Flag
+  *     @arg TIM_FLAG_CC2OF: TIM Capture Compare 2 overcapture Flag
+  *     @arg TIM_FLAG_CC3OF: TIM Capture Compare 3 overcapture Flag
+  *     @arg TIM_FLAG_CC4OF: TIM Capture Compare 4 overcapture Flag
+  * @note
+  *   - TIM6 and TIM7 can have only one update flag. 
+  *   - TIM9, TIM12 and TIM15 can have only TIM_FLAG_Update, TIM_FLAG_CC1,
+  *      TIM_FLAG_CC2 or TIM_FLAG_Trigger. 
+  *   - TIM10, TIM11, TIM13, TIM14, TIM16 and TIM17 can have TIM_FLAG_Update or TIM_FLAG_CC1.   
+  *   - TIM_FLAG_Break is used only with TIM1, TIM8 and TIM15. 
+  *   - TIM_FLAG_COM is used only with TIM1, TIM8, TIM15, TIM16 and TIM17.    
+  * @retval The new state of TIM_FLAG (SET or RESET).
+  */
+FlagStatus TIM_GetFlagStatus(TIM_TypeDef* TIMx, uint16_t TIM_FLAG)
+{ 
+  ITStatus bitstatus = RESET;  
+  /* Check the parameters */
+  assert_param(IS_TIM_ALL_PERIPH(TIMx));
+  assert_param(IS_TIM_GET_FLAG(TIM_FLAG));
+  
+  if ((TIMx->SR & TIM_FLAG) != (uint16_t)RESET)
+  {
+    bitstatus = SET;
+  }
+  else
+  {
+    bitstatus = RESET;
+  }
+  return bitstatus;
+}
+
+/**
+  * @brief  Clears the TIMx's pending flags.
+  * @param  TIMx: where x can be 1 to 17 to select the TIM peripheral.
+  * @param  TIM_FLAG: specifies the flag bit to clear.
+  *   This parameter can be any combination of the following values:
+  *     @arg TIM_FLAG_Update: TIM update Flag
+  *     @arg TIM_FLAG_CC1: TIM Capture Compare 1 Flag
+  *     @arg TIM_FLAG_CC2: TIM Capture Compare 2 Flag
+  *     @arg TIM_FLAG_CC3: TIM Capture Compare 3 Flag
+  *     @arg TIM_FLAG_CC4: TIM Capture Compare 4 Flag
+  *     @arg TIM_FLAG_COM: TIM Commutation Flag
+  *     @arg TIM_FLAG_Trigger: TIM Trigger Flag
+  *     @arg TIM_FLAG_Break: TIM Break Flag
+  *     @arg TIM_FLAG_CC1OF: TIM Capture Compare 1 overcapture Flag
+  *     @arg TIM_FLAG_CC2OF: TIM Capture Compare 2 overcapture Flag
+  *     @arg TIM_FLAG_CC3OF: TIM Capture Compare 3 overcapture Flag
+  *     @arg TIM_FLAG_CC4OF: TIM Capture Compare 4 overcapture Flag
+  * @note
+  *   - TIM6 and TIM7 can have only one update flag. 
+  *   - TIM9, TIM12 and TIM15 can have only TIM_FLAG_Update, TIM_FLAG_CC1,
+  *      TIM_FLAG_CC2 or TIM_FLAG_Trigger. 
+  *   - TIM10, TIM11, TIM13, TIM14, TIM16 and TIM17 can have TIM_FLAG_Update or TIM_FLAG_CC1.   
+  *   - TIM_FLAG_Break is used only with TIM1, TIM8 and TIM15. 
+  *   - TIM_FLAG_COM is used only with TIM1, TIM8, TIM15, TIM16 and TIM17.   
+  * @retval None
+  */
+void TIM_ClearFlag(TIM_TypeDef* TIMx, uint16_t TIM_FLAG)
+{  
+  /* Check the parameters */
+  assert_param(IS_TIM_ALL_PERIPH(TIMx));
+  assert_param(IS_TIM_CLEAR_FLAG(TIM_FLAG));
+   
+  /* Clear the flags */
+  TIMx->SR = (uint16_t)~TIM_FLAG;
+}
+
+/**
+  * @brief  Checks whether the TIM interrupt has occurred or not.
+  * @param  TIMx: where x can be 1 to 17 to select the TIM peripheral.
+  * @param  TIM_IT: specifies the TIM interrupt source to check.
+  *   This parameter can be one of the following values:
+  *     @arg TIM_IT_Update: TIM update Interrupt source
+  *     @arg TIM_IT_CC1: TIM Capture Compare 1 Interrupt source
+  *     @arg TIM_IT_CC2: TIM Capture Compare 2 Interrupt source
+  *     @arg TIM_IT_CC3: TIM Capture Compare 3 Interrupt source
+  *     @arg TIM_IT_CC4: TIM Capture Compare 4 Interrupt source
+  *     @arg TIM_IT_COM: TIM Commutation Interrupt source
+  *     @arg TIM_IT_Trigger: TIM Trigger Interrupt source
+  *     @arg TIM_IT_Break: TIM Break Interrupt source
+  * @note
+  *   - TIM6 and TIM7 can generate only an update interrupt.
+  *   - TIM9, TIM12 and TIM15 can have only TIM_IT_Update, TIM_IT_CC1,
+  *      TIM_IT_CC2 or TIM_IT_Trigger. 
+  *   - TIM10, TIM11, TIM13, TIM14, TIM16 and TIM17 can have TIM_IT_Update or TIM_IT_CC1.   
+  *   - TIM_IT_Break is used only with TIM1, TIM8 and TIM15. 
+  *   - TIM_IT_COM is used only with TIM1, TIM8, TIM15, TIM16 and TIM17.  
+  * @retval The new state of the TIM_IT(SET or RESET).
+  */
+ITStatus TIM_GetITStatus(TIM_TypeDef* TIMx, uint16_t TIM_IT)
+{
+  ITStatus bitstatus = RESET;  
+  uint16_t itstatus = 0x0, itenable = 0x0;
+  /* Check the parameters */
+  assert_param(IS_TIM_ALL_PERIPH(TIMx));
+  assert_param(IS_TIM_GET_IT(TIM_IT));
+   
+  itstatus = TIMx->SR & TIM_IT;
+  
+  itenable = TIMx->DIER & TIM_IT;
+  if ((itstatus != (uint16_t)RESET) && (itenable != (uint16_t)RESET))
+  {
+    bitstatus = SET;
+  }
+  else
+  {
+    bitstatus = RESET;
+  }
+  return bitstatus;
+}
+
+/**
+  * @brief  Clears the TIMx's interrupt pending bits.
+  * @param  TIMx: where x can be 1 to 17 to select the TIM peripheral.
+  * @param  TIM_IT: specifies the pending bit to clear.
+  *   This parameter can be any combination of the following values:
+  *     @arg TIM_IT_Update: TIM1 update Interrupt source
+  *     @arg TIM_IT_CC1: TIM Capture Compare 1 Interrupt source
+  *     @arg TIM_IT_CC2: TIM Capture Compare 2 Interrupt source
+  *     @arg TIM_IT_CC3: TIM Capture Compare 3 Interrupt source
+  *     @arg TIM_IT_CC4: TIM Capture Compare 4 Interrupt source
+  *     @arg TIM_IT_COM: TIM Commutation Interrupt source
+  *     @arg TIM_IT_Trigger: TIM Trigger Interrupt source
+  *     @arg TIM_IT_Break: TIM Break Interrupt source
+  * @note
+  *   - TIM6 and TIM7 can generate only an update interrupt.
+  *   - TIM9, TIM12 and TIM15 can have only TIM_IT_Update, TIM_IT_CC1,
+  *      TIM_IT_CC2 or TIM_IT_Trigger. 
+  *   - TIM10, TIM11, TIM13, TIM14, TIM16 and TIM17 can have TIM_IT_Update or TIM_IT_CC1.   
+  *   - TIM_IT_Break is used only with TIM1, TIM8 and TIM15. 
+  *   - TIM_IT_COM is used only with TIM1, TIM8, TIM15, TIM16 and TIM17.    
+  * @retval None
+  */
+void TIM_ClearITPendingBit(TIM_TypeDef* TIMx, uint16_t TIM_IT)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_ALL_PERIPH(TIMx));
+  assert_param(IS_TIM_IT(TIM_IT));
+  /* Clear the IT pending Bit */
+  TIMx->SR = (uint16_t)~TIM_IT;
+}
+
+/**
+  * @brief  Configure the TI1 as Input.
+  * @param  TIMx: where x can be 1 to 17 except 6 and 7 to select the TIM peripheral.
+  * @param  TIM_ICPolarity : The Input Polarity.
+  *   This parameter can be one of the following values:
+  *     @arg TIM_ICPolarity_Rising
+  *     @arg TIM_ICPolarity_Falling
+  * @param  TIM_ICSelection: specifies the input to be used.
+  *   This parameter can be one of the following values:
+  *     @arg TIM_ICSelection_DirectTI: TIM Input 1 is selected to be connected to IC1.
+  *     @arg TIM_ICSelection_IndirectTI: TIM Input 1 is selected to be connected to IC2.
+  *     @arg TIM_ICSelection_TRC: TIM Input 1 is selected to be connected to TRC.
+  * @param  TIM_ICFilter: Specifies the Input Capture Filter.
+  *   This parameter must be a value between 0x00 and 0x0F.
+  * @retval None
+  */
+static void TI1_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
+                       uint16_t TIM_ICFilter)
+{
+  uint16_t tmpccmr1 = 0, tmpccer = 0;
+  /* Disable the Channel 1: Reset the CC1E Bit */
+  TIMx->CCER &= (uint16_t)~((uint16_t)TIM_CCER_CC1E);
+  tmpccmr1 = TIMx->CCMR1;
+  tmpccer = TIMx->CCER;
+  /* Select the Input and set the filter */
+  tmpccmr1 &= (uint16_t)(((uint16_t)~((uint16_t)TIM_CCMR1_CC1S)) & ((uint16_t)~((uint16_t)TIM_CCMR1_IC1F)));
+  tmpccmr1 |= (uint16_t)(TIM_ICSelection | (uint16_t)(TIM_ICFilter << (uint16_t)4));
+  
+  if((TIMx == TIM1) || (TIMx == TIM8) || (TIMx == TIM2) || (TIMx == TIM3) ||
+     (TIMx == TIM4) ||(TIMx == TIM5))
+  {
+    /* Select the Polarity and set the CC1E Bit */
+    tmpccer &= (uint16_t)~((uint16_t)(TIM_CCER_CC1P));
+    tmpccer |= (uint16_t)(TIM_ICPolarity | (uint16_t)TIM_CCER_CC1E);
+  }
+  else
+  {
+    /* Select the Polarity and set the CC1E Bit */
+    tmpccer &= (uint16_t)~((uint16_t)(TIM_CCER_CC1P | TIM_CCER_CC1NP));
+    tmpccer |= (uint16_t)(TIM_ICPolarity | (uint16_t)TIM_CCER_CC1E);
+  }
+
+  /* Write to TIMx CCMR1 and CCER registers */
+  TIMx->CCMR1 = tmpccmr1;
+  TIMx->CCER = tmpccer;
+}
+
+/**
+  * @brief  Configure the TI2 as Input.
+  * @param  TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select the TIM peripheral.
+  * @param  TIM_ICPolarity : The Input Polarity.
+  *   This parameter can be one of the following values:
+  *     @arg TIM_ICPolarity_Rising
+  *     @arg TIM_ICPolarity_Falling
+  * @param  TIM_ICSelection: specifies the input to be used.
+  *   This parameter can be one of the following values:
+  *     @arg TIM_ICSelection_DirectTI: TIM Input 2 is selected to be connected to IC2.
+  *     @arg TIM_ICSelection_IndirectTI: TIM Input 2 is selected to be connected to IC1.
+  *     @arg TIM_ICSelection_TRC: TIM Input 2 is selected to be connected to TRC.
+  * @param  TIM_ICFilter: Specifies the Input Capture Filter.
+  *   This parameter must be a value between 0x00 and 0x0F.
+  * @retval None
+  */
+static void TI2_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
+                       uint16_t TIM_ICFilter)
+{
+  uint16_t tmpccmr1 = 0, tmpccer = 0, tmp = 0;
+  /* Disable the Channel 2: Reset the CC2E Bit */
+  TIMx->CCER &= (uint16_t)~((uint16_t)TIM_CCER_CC2E);
+  tmpccmr1 = TIMx->CCMR1;
+  tmpccer = TIMx->CCER;
+  tmp = (uint16_t)(TIM_ICPolarity << 4);
+  /* Select the Input and set the filter */
+  tmpccmr1 &= (uint16_t)(((uint16_t)~((uint16_t)TIM_CCMR1_CC2S)) & ((uint16_t)~((uint16_t)TIM_CCMR1_IC2F)));
+  tmpccmr1 |= (uint16_t)(TIM_ICFilter << 12);
+  tmpccmr1 |= (uint16_t)(TIM_ICSelection << 8);
+  
+  if((TIMx == TIM1) || (TIMx == TIM8) || (TIMx == TIM2) || (TIMx == TIM3) ||
+     (TIMx == TIM4) ||(TIMx == TIM5))
+  {
+    /* Select the Polarity and set the CC2E Bit */
+    tmpccer &= (uint16_t)~((uint16_t)(TIM_CCER_CC2P));
+    tmpccer |=  (uint16_t)(tmp | (uint16_t)TIM_CCER_CC2E);
+  }
+  else
+  {
+    /* Select the Polarity and set the CC2E Bit */
+    tmpccer &= (uint16_t)~((uint16_t)(TIM_CCER_CC2P | TIM_CCER_CC2NP));
+    tmpccer |= (uint16_t)(TIM_ICPolarity | (uint16_t)TIM_CCER_CC2E);
+  }
+  
+  /* Write to TIMx CCMR1 and CCER registers */
+  TIMx->CCMR1 = tmpccmr1 ;
+  TIMx->CCER = tmpccer;
+}
+
+/**
+  * @brief  Configure the TI3 as Input.
+  * @param  TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+  * @param  TIM_ICPolarity : The Input Polarity.
+  *   This parameter can be one of the following values:
+  *     @arg TIM_ICPolarity_Rising
+  *     @arg TIM_ICPolarity_Falling
+  * @param  TIM_ICSelection: specifies the input to be used.
+  *   This parameter can be one of the following values:
+  *     @arg TIM_ICSelection_DirectTI: TIM Input 3 is selected to be connected to IC3.
+  *     @arg TIM_ICSelection_IndirectTI: TIM Input 3 is selected to be connected to IC4.
+  *     @arg TIM_ICSelection_TRC: TIM Input 3 is selected to be connected to TRC.
+  * @param  TIM_ICFilter: Specifies the Input Capture Filter.
+  *   This parameter must be a value between 0x00 and 0x0F.
+  * @retval None
+  */
+static void TI3_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
+                       uint16_t TIM_ICFilter)
+{
+  uint16_t tmpccmr2 = 0, tmpccer = 0, tmp = 0;
+  /* Disable the Channel 3: Reset the CC3E Bit */
+  TIMx->CCER &= (uint16_t)~((uint16_t)TIM_CCER_CC3E);
+  tmpccmr2 = TIMx->CCMR2;
+  tmpccer = TIMx->CCER;
+  tmp = (uint16_t)(TIM_ICPolarity << 8);
+  /* Select the Input and set the filter */
+  tmpccmr2 &= (uint16_t)(((uint16_t)~((uint16_t)TIM_CCMR2_CC3S)) & ((uint16_t)~((uint16_t)TIM_CCMR2_IC3F)));
+  tmpccmr2 |= (uint16_t)(TIM_ICSelection | (uint16_t)(TIM_ICFilter << (uint16_t)4));
+    
+  if((TIMx == TIM1) || (TIMx == TIM8) || (TIMx == TIM2) || (TIMx == TIM3) ||
+     (TIMx == TIM4) ||(TIMx == TIM5))
+  {
+    /* Select the Polarity and set the CC3E Bit */
+    tmpccer &= (uint16_t)~((uint16_t)(TIM_CCER_CC3P));
+    tmpccer |= (uint16_t)(tmp | (uint16_t)TIM_CCER_CC3E);
+  }
+  else
+  {
+    /* Select the Polarity and set the CC3E Bit */
+    tmpccer &= (uint16_t)~((uint16_t)(TIM_CCER_CC3P | TIM_CCER_CC3NP));
+    tmpccer |= (uint16_t)(TIM_ICPolarity | (uint16_t)TIM_CCER_CC3E);
+  }
+  
+  /* Write to TIMx CCMR2 and CCER registers */
+  TIMx->CCMR2 = tmpccmr2;
+  TIMx->CCER = tmpccer;
+}
+
+/**
+  * @brief  Configure the TI4 as Input.
+  * @param  TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+  * @param  TIM_ICPolarity : The Input Polarity.
+  *   This parameter can be one of the following values:
+  *     @arg TIM_ICPolarity_Rising
+  *     @arg TIM_ICPolarity_Falling
+  * @param  TIM_ICSelection: specifies the input to be used.
+  *   This parameter can be one of the following values:
+  *     @arg TIM_ICSelection_DirectTI: TIM Input 4 is selected to be connected to IC4.
+  *     @arg TIM_ICSelection_IndirectTI: TIM Input 4 is selected to be connected to IC3.
+  *     @arg TIM_ICSelection_TRC: TIM Input 4 is selected to be connected to TRC.
+  * @param  TIM_ICFilter: Specifies the Input Capture Filter.
+  *   This parameter must be a value between 0x00 and 0x0F.
+  * @retval None
+  */
+static void TI4_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
+                       uint16_t TIM_ICFilter)
+{
+  uint16_t tmpccmr2 = 0, tmpccer = 0, tmp = 0;
+
+   /* Disable the Channel 4: Reset the CC4E Bit */
+  TIMx->CCER &= (uint16_t)~((uint16_t)TIM_CCER_CC4E);
+  tmpccmr2 = TIMx->CCMR2;
+  tmpccer = TIMx->CCER;
+  tmp = (uint16_t)(TIM_ICPolarity << 12);
+  /* Select the Input and set the filter */
+  tmpccmr2 &= (uint16_t)((uint16_t)(~(uint16_t)TIM_CCMR2_CC4S) & ((uint16_t)~((uint16_t)TIM_CCMR2_IC4F)));
+  tmpccmr2 |= (uint16_t)(TIM_ICSelection << 8);
+  tmpccmr2 |= (uint16_t)(TIM_ICFilter << 12);
+  
+  if((TIMx == TIM1) || (TIMx == TIM8) || (TIMx == TIM2) || (TIMx == TIM3) ||
+     (TIMx == TIM4) ||(TIMx == TIM5))
+  {
+    /* Select the Polarity and set the CC4E Bit */
+    tmpccer &= (uint16_t)~((uint16_t)(TIM_CCER_CC4P));
+    tmpccer |= (uint16_t)(tmp | (uint16_t)TIM_CCER_CC4E);
+  }
+  else
+  {
+    /* Select the Polarity and set the CC4E Bit */
+    tmpccer &= (uint16_t)~((uint16_t)(TIM_CCER_CC3P | TIM_CCER_CC4NP));
+    tmpccer |= (uint16_t)(TIM_ICPolarity | (uint16_t)TIM_CCER_CC4E);
+  }
+  /* Write to TIMx CCMR2 and CCER registers */
+  TIMx->CCMR2 = tmpccmr2;
+  TIMx->CCER = tmpccer;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/STM32_4路称重_Git提交精简工程/src/STM32F10x_FWLib/src/stm32f10x_usart.c b/STM32_4路称重_Git提交精简工程/src/STM32F10x_FWLib/src/stm32f10x_usart.c
new file mode 100755
index 0000000..a3f16f1
--- /dev/null
+++ b/STM32_4路称重_Git提交精简工程/src/STM32F10x_FWLib/src/stm32f10x_usart.c
@@ -0,0 +1,1058 @@
+/**
+  ******************************************************************************
+  * @file    stm32f10x_usart.c
+  * @author  MCD Application Team
+  * @version V3.5.0
+  * @date    11-March-2011
+  * @brief   This file provides all the USART firmware functions.
+  ******************************************************************************
+  * @attention
+  *
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+  *
+  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x_usart.h"
+#include "stm32f10x_rcc.h"
+
+/** @addtogroup STM32F10x_StdPeriph_Driver
+  * @{
+  */
+
+/** @defgroup USART 
+  * @brief USART driver modules
+  * @{
+  */
+
+/** @defgroup USART_Private_TypesDefinitions
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup USART_Private_Defines
+  * @{
+  */
+
+#define CR1_UE_Set                ((uint16_t)0x2000)  /*!< USART Enable Mask */
+#define CR1_UE_Reset              ((uint16_t)0xDFFF)  /*!< USART Disable Mask */
+
+#define CR1_WAKE_Mask             ((uint16_t)0xF7FF)  /*!< USART WakeUp Method Mask */
+
+#define CR1_RWU_Set               ((uint16_t)0x0002)  /*!< USART mute mode Enable Mask */
+#define CR1_RWU_Reset             ((uint16_t)0xFFFD)  /*!< USART mute mode Enable Mask */
+#define CR1_SBK_Set               ((uint16_t)0x0001)  /*!< USART Break Character send Mask */
+#define CR1_CLEAR_Mask            ((uint16_t)0xE9F3)  /*!< USART CR1 Mask */
+#define CR2_Address_Mask          ((uint16_t)0xFFF0)  /*!< USART address Mask */
+
+#define CR2_LINEN_Set              ((uint16_t)0x4000)  /*!< USART LIN Enable Mask */
+#define CR2_LINEN_Reset            ((uint16_t)0xBFFF)  /*!< USART LIN Disable Mask */
+
+#define CR2_LBDL_Mask             ((uint16_t)0xFFDF)  /*!< USART LIN Break detection Mask */
+#define CR2_STOP_CLEAR_Mask       ((uint16_t)0xCFFF)  /*!< USART CR2 STOP Bits Mask */
+#define CR2_CLOCK_CLEAR_Mask      ((uint16_t)0xF0FF)  /*!< USART CR2 Clock Mask */
+
+#define CR3_SCEN_Set              ((uint16_t)0x0020)  /*!< USART SC Enable Mask */
+#define CR3_SCEN_Reset            ((uint16_t)0xFFDF)  /*!< USART SC Disable Mask */
+
+#define CR3_NACK_Set              ((uint16_t)0x0010)  /*!< USART SC NACK Enable Mask */
+#define CR3_NACK_Reset            ((uint16_t)0xFFEF)  /*!< USART SC NACK Disable Mask */
+
+#define CR3_HDSEL_Set             ((uint16_t)0x0008)  /*!< USART Half-Duplex Enable Mask */
+#define CR3_HDSEL_Reset           ((uint16_t)0xFFF7)  /*!< USART Half-Duplex Disable Mask */
+
+#define CR3_IRLP_Mask             ((uint16_t)0xFFFB)  /*!< USART IrDA LowPower mode Mask */
+#define CR3_CLEAR_Mask            ((uint16_t)0xFCFF)  /*!< USART CR3 Mask */
+
+#define CR3_IREN_Set              ((uint16_t)0x0002)  /*!< USART IrDA Enable Mask */
+#define CR3_IREN_Reset            ((uint16_t)0xFFFD)  /*!< USART IrDA Disable Mask */
+#define GTPR_LSB_Mask             ((uint16_t)0x00FF)  /*!< Guard Time Register LSB Mask */
+#define GTPR_MSB_Mask             ((uint16_t)0xFF00)  /*!< Guard Time Register MSB Mask */
+#define IT_Mask                   ((uint16_t)0x001F)  /*!< USART Interrupt Mask */
+
+/* USART OverSampling-8 Mask */
+#define CR1_OVER8_Set             ((u16)0x8000)  /* USART OVER8 mode Enable Mask */
+#define CR1_OVER8_Reset           ((u16)0x7FFF)  /* USART OVER8 mode Disable Mask */
+
+/* USART One Bit Sampling Mask */
+#define CR3_ONEBITE_Set           ((u16)0x0800)  /* USART ONEBITE mode Enable Mask */
+#define CR3_ONEBITE_Reset         ((u16)0xF7FF)  /* USART ONEBITE mode Disable Mask */
+
+/**
+  * @}
+  */
+
+/** @defgroup USART_Private_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup USART_Private_Variables
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup USART_Private_FunctionPrototypes
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup USART_Private_Functions
+  * @{
+  */
+
+/**
+  * @brief  Deinitializes the USARTx peripheral registers to their default reset values.
+  * @param  USARTx: Select the USART or the UART peripheral. 
+  *   This parameter can be one of the following values: 
+  *      USART1, USART2, USART3, UART4 or UART5.
+  * @retval None
+  */
+void USART_DeInit(USART_TypeDef* USARTx)
+{
+  /* Check the parameters */
+  assert_param(IS_USART_ALL_PERIPH(USARTx));
+
+  if (USARTx == USART1)
+  {
+    RCC_APB2PeriphResetCmd(RCC_APB2Periph_USART1, ENABLE);
+    RCC_APB2PeriphResetCmd(RCC_APB2Periph_USART1, DISABLE);
+  }
+  else if (USARTx == USART2)
+  {
+    RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART2, ENABLE);
+    RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART2, DISABLE);
+  }
+  else if (USARTx == USART3)
+  {
+    RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART3, ENABLE);
+    RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART3, DISABLE);
+  }    
+  else if (USARTx == UART4)
+  {
+    RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART4, ENABLE);
+    RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART4, DISABLE);
+  }    
+  else
+  {
+    if (USARTx == UART5)
+    { 
+      RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART5, ENABLE);
+      RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART5, DISABLE);
+    }
+  }
+}
+
+/**
+  * @brief  Initializes the USARTx peripheral according to the specified
+  *         parameters in the USART_InitStruct .
+  * @param  USARTx: Select the USART or the UART peripheral. 
+  *   This parameter can be one of the following values:
+  *   USART1, USART2, USART3, UART4 or UART5.
+  * @param  USART_InitStruct: pointer to a USART_InitTypeDef structure
+  *         that contains the configuration information for the specified USART 
+  *         peripheral.
+  * @retval None
+  */
+void USART_Init(USART_TypeDef* USARTx, USART_InitTypeDef* USART_InitStruct)
+{
+  uint32_t tmpreg = 0x00, apbclock = 0x00;
+  uint32_t integerdivider = 0x00;
+  uint32_t fractionaldivider = 0x00;
+  uint32_t usartxbase = 0;
+  RCC_ClocksTypeDef RCC_ClocksStatus;
+  /* Check the parameters */
+  assert_param(IS_USART_ALL_PERIPH(USARTx));
+  assert_param(IS_USART_BAUDRATE(USART_InitStruct->USART_BaudRate));  
+  assert_param(IS_USART_WORD_LENGTH(USART_InitStruct->USART_WordLength));
+  assert_param(IS_USART_STOPBITS(USART_InitStruct->USART_StopBits));
+  assert_param(IS_USART_PARITY(USART_InitStruct->USART_Parity));
+  assert_param(IS_USART_MODE(USART_InitStruct->USART_Mode));
+  assert_param(IS_USART_HARDWARE_FLOW_CONTROL(USART_InitStruct->USART_HardwareFlowControl));
+  /* The hardware flow control is available only for USART1, USART2 and USART3 */
+  if (USART_InitStruct->USART_HardwareFlowControl != USART_HardwareFlowControl_None)
+  {
+    assert_param(IS_USART_123_PERIPH(USARTx));
+  }
+
+  usartxbase = (uint32_t)USARTx;
+
+/*---------------------------- USART CR2 Configuration -----------------------*/
+  tmpreg = USARTx->CR2;
+  /* Clear STOP[13:12] bits */
+  tmpreg &= CR2_STOP_CLEAR_Mask;
+  /* Configure the USART Stop Bits, Clock, CPOL, CPHA and LastBit ------------*/
+  /* Set STOP[13:12] bits according to USART_StopBits value */
+  tmpreg |= (uint32_t)USART_InitStruct->USART_StopBits;
+  
+  /* Write to USART CR2 */
+  USARTx->CR2 = (uint16_t)tmpreg;
+
+/*---------------------------- USART CR1 Configuration -----------------------*/
+  tmpreg = USARTx->CR1;
+  /* Clear M, PCE, PS, TE and RE bits */
+  tmpreg &= CR1_CLEAR_Mask;
+  /* Configure the USART Word Length, Parity and mode ----------------------- */
+  /* Set the M bits according to USART_WordLength value */
+  /* Set PCE and PS bits according to USART_Parity value */
+  /* Set TE and RE bits according to USART_Mode value */
+  tmpreg |= (uint32_t)USART_InitStruct->USART_WordLength | USART_InitStruct->USART_Parity |
+            USART_InitStruct->USART_Mode;
+  /* Write to USART CR1 */
+  USARTx->CR1 = (uint16_t)tmpreg;
+
+/*---------------------------- USART CR3 Configuration -----------------------*/  
+  tmpreg = USARTx->CR3;
+  /* Clear CTSE and RTSE bits */
+  tmpreg &= CR3_CLEAR_Mask;
+  /* Configure the USART HFC -------------------------------------------------*/
+  /* Set CTSE and RTSE bits according to USART_HardwareFlowControl value */
+  tmpreg |= USART_InitStruct->USART_HardwareFlowControl;
+  /* Write to USART CR3 */
+  USARTx->CR3 = (uint16_t)tmpreg;
+
+/*---------------------------- USART BRR Configuration -----------------------*/
+  /* Configure the USART Baud Rate -------------------------------------------*/
+  RCC_GetClocksFreq(&RCC_ClocksStatus);
+  if (usartxbase == USART1_BASE)
+  {
+    apbclock = RCC_ClocksStatus.PCLK2_Frequency;
+  }
+  else
+  {
+    apbclock = RCC_ClocksStatus.PCLK1_Frequency;
+  }
+  
+  /* Determine the integer part */
+  if ((USARTx->CR1 & CR1_OVER8_Set) != 0)
+  {
+    /* Integer part computing in case Oversampling mode is 8 Samples */
+    integerdivider = ((25 * apbclock) / (2 * (USART_InitStruct->USART_BaudRate)));    
+  }
+  else /* if ((USARTx->CR1 & CR1_OVER8_Set) == 0) */
+  {
+    /* Integer part computing in case Oversampling mode is 16 Samples */
+    integerdivider = ((25 * apbclock) / (4 * (USART_InitStruct->USART_BaudRate)));    
+  }
+  tmpreg = (integerdivider / 100) << 4;
+
+  /* Determine the fractional part */
+  fractionaldivider = integerdivider - (100 * (tmpreg >> 4));
+
+  /* Implement the fractional part in the register */
+  if ((USARTx->CR1 & CR1_OVER8_Set) != 0)
+  {
+    tmpreg |= ((((fractionaldivider * 8) + 50) / 100)) & ((uint8_t)0x07);
+  }
+  else /* if ((USARTx->CR1 & CR1_OVER8_Set) == 0) */
+  {
+    tmpreg |= ((((fractionaldivider * 16) + 50) / 100)) & ((uint8_t)0x0F);
+  }
+  
+  /* Write to USART BRR */
+  USARTx->BRR = (uint16_t)tmpreg;
+}
+
+/**
+  * @brief  Fills each USART_InitStruct member with its default value.
+  * @param  USART_InitStruct: pointer to a USART_InitTypeDef structure
+  *         which will be initialized.
+  * @retval None
+  */
+void USART_StructInit(USART_InitTypeDef* USART_InitStruct)
+{
+  /* USART_InitStruct members default value */
+  USART_InitStruct->USART_BaudRate = 9600;
+  USART_InitStruct->USART_WordLength = USART_WordLength_8b;
+  USART_InitStruct->USART_StopBits = USART_StopBits_1;
+  USART_InitStruct->USART_Parity = USART_Parity_No ;
+  USART_InitStruct->USART_Mode = USART_Mode_Rx | USART_Mode_Tx;
+  USART_InitStruct->USART_HardwareFlowControl = USART_HardwareFlowControl_None;  
+}
+
+/**
+  * @brief  Initializes the USARTx peripheral Clock according to the 
+  *          specified parameters in the USART_ClockInitStruct .
+  * @param  USARTx: where x can be 1, 2, 3 to select the USART peripheral.
+  * @param  USART_ClockInitStruct: pointer to a USART_ClockInitTypeDef
+  *         structure that contains the configuration information for the specified 
+  *         USART peripheral.  
+  * @note The Smart Card and Synchronous modes are not available for UART4 and UART5.
+  * @retval None
+  */
+void USART_ClockInit(USART_TypeDef* USARTx, USART_ClockInitTypeDef* USART_ClockInitStruct)
+{
+  uint32_t tmpreg = 0x00;
+  /* Check the parameters */
+  assert_param(IS_USART_123_PERIPH(USARTx));
+  assert_param(IS_USART_CLOCK(USART_ClockInitStruct->USART_Clock));
+  assert_param(IS_USART_CPOL(USART_ClockInitStruct->USART_CPOL));
+  assert_param(IS_USART_CPHA(USART_ClockInitStruct->USART_CPHA));
+  assert_param(IS_USART_LASTBIT(USART_ClockInitStruct->USART_LastBit));
+  
+/*---------------------------- USART CR2 Configuration -----------------------*/
+  tmpreg = USARTx->CR2;
+  /* Clear CLKEN, CPOL, CPHA and LBCL bits */
+  tmpreg &= CR2_CLOCK_CLEAR_Mask;
+  /* Configure the USART Clock, CPOL, CPHA and LastBit ------------*/
+  /* Set CLKEN bit according to USART_Clock value */
+  /* Set CPOL bit according to USART_CPOL value */
+  /* Set CPHA bit according to USART_CPHA value */
+  /* Set LBCL bit according to USART_LastBit value */
+  tmpreg |= (uint32_t)USART_ClockInitStruct->USART_Clock | USART_ClockInitStruct->USART_CPOL | 
+                 USART_ClockInitStruct->USART_CPHA | USART_ClockInitStruct->USART_LastBit;
+  /* Write to USART CR2 */
+  USARTx->CR2 = (uint16_t)tmpreg;
+}
+
+/**
+  * @brief  Fills each USART_ClockInitStruct member with its default value.
+  * @param  USART_ClockInitStruct: pointer to a USART_ClockInitTypeDef
+  *         structure which will be initialized.
+  * @retval None
+  */
+void USART_ClockStructInit(USART_ClockInitTypeDef* USART_ClockInitStruct)
+{
+  /* USART_ClockInitStruct members default value */
+  USART_ClockInitStruct->USART_Clock = USART_Clock_Disable;
+  USART_ClockInitStruct->USART_CPOL = USART_CPOL_Low;
+  USART_ClockInitStruct->USART_CPHA = USART_CPHA_1Edge;
+  USART_ClockInitStruct->USART_LastBit = USART_LastBit_Disable;
+}
+
+/**
+  * @brief  Enables or disables the specified USART peripheral.
+  * @param  USARTx: Select the USART or the UART peripheral. 
+  *         This parameter can be one of the following values:
+  *           USART1, USART2, USART3, UART4 or UART5.
+  * @param  NewState: new state of the USARTx peripheral.
+  *         This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void USART_Cmd(USART_TypeDef* USARTx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_USART_ALL_PERIPH(USARTx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  
+  if (NewState != DISABLE)
+  {
+    /* Enable the selected USART by setting the UE bit in the CR1 register */
+    USARTx->CR1 |= CR1_UE_Set;
+  }
+  else
+  {
+    /* Disable the selected USART by clearing the UE bit in the CR1 register */
+    USARTx->CR1 &= CR1_UE_Reset;
+  }
+}
+
+/**
+  * @brief  Enables or disables the specified USART interrupts.
+  * @param  USARTx: Select the USART or the UART peripheral. 
+  *   This parameter can be one of the following values:
+  *   USART1, USART2, USART3, UART4 or UART5.
+  * @param  USART_IT: specifies the USART interrupt sources to be enabled or disabled.
+  *   This parameter can be one of the following values:
+  *     @arg USART_IT_CTS:  CTS change interrupt (not available for UART4 and UART5)
+  *     @arg USART_IT_LBD:  LIN Break detection interrupt
+  *     @arg USART_IT_TXE:  Transmit Data Register empty interrupt
+  *     @arg USART_IT_TC:   Transmission complete interrupt
+  *     @arg USART_IT_RXNE: Receive Data register not empty interrupt
+  *     @arg USART_IT_IDLE: Idle line detection interrupt
+  *     @arg USART_IT_PE:   Parity Error interrupt
+  *     @arg USART_IT_ERR:  Error interrupt(Frame error, noise error, overrun error)
+  * @param  NewState: new state of the specified USARTx interrupts.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void USART_ITConfig(USART_TypeDef* USARTx, uint16_t USART_IT, FunctionalState NewState)
+{
+  uint32_t usartreg = 0x00, itpos = 0x00, itmask = 0x00;
+  uint32_t usartxbase = 0x00;
+  /* Check the parameters */
+  assert_param(IS_USART_ALL_PERIPH(USARTx));
+  assert_param(IS_USART_CONFIG_IT(USART_IT));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  /* The CTS interrupt is not available for UART4 and UART5 */
+  if (USART_IT == USART_IT_CTS)
+  {
+    assert_param(IS_USART_123_PERIPH(USARTx));
+  }   
+  
+  usartxbase = (uint32_t)USARTx;
+
+  /* Get the USART register index */
+  usartreg = (((uint8_t)USART_IT) >> 0x05);
+
+  /* Get the interrupt position */
+  itpos = USART_IT & IT_Mask;
+  itmask = (((uint32_t)0x01) << itpos);
+    
+  if (usartreg == 0x01) /* The IT is in CR1 register */
+  {
+    usartxbase += 0x0C;
+  }
+  else if (usartreg == 0x02) /* The IT is in CR2 register */
+  {
+    usartxbase += 0x10;
+  }
+  else /* The IT is in CR3 register */
+  {
+    usartxbase += 0x14; 
+  }
+  if (NewState != DISABLE)
+  {
+    *(__IO uint32_t*)usartxbase  |= itmask;
+  }
+  else
+  {
+    *(__IO uint32_t*)usartxbase &= ~itmask;
+  }
+}
+
+/**
+  * @brief  Enables or disables the USART�s DMA interface.
+  * @param  USARTx: Select the USART or the UART peripheral. 
+  *   This parameter can be one of the following values:
+  *   USART1, USART2, USART3, UART4 or UART5.
+  * @param  USART_DMAReq: specifies the DMA request.
+  *   This parameter can be any combination of the following values:
+  *     @arg USART_DMAReq_Tx: USART DMA transmit request
+  *     @arg USART_DMAReq_Rx: USART DMA receive request
+  * @param  NewState: new state of the DMA Request sources.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @note The DMA mode is not available for UART5 except in the STM32
+  *       High density value line devices(STM32F10X_HD_VL).  
+  * @retval None
+  */
+void USART_DMACmd(USART_TypeDef* USARTx, uint16_t USART_DMAReq, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_USART_ALL_PERIPH(USARTx));
+  assert_param(IS_USART_DMAREQ(USART_DMAReq));  
+  assert_param(IS_FUNCTIONAL_STATE(NewState)); 
+  if (NewState != DISABLE)
+  {
+    /* Enable the DMA transfer for selected requests by setting the DMAT and/or
+       DMAR bits in the USART CR3 register */
+    USARTx->CR3 |= USART_DMAReq;
+  }
+  else
+  {
+    /* Disable the DMA transfer for selected requests by clearing the DMAT and/or
+       DMAR bits in the USART CR3 register */
+    USARTx->CR3 &= (uint16_t)~USART_DMAReq;
+  }
+}
+
+/**
+  * @brief  Sets the address of the USART node.
+  * @param  USARTx: Select the USART or the UART peripheral. 
+  *   This parameter can be one of the following values:
+  *   USART1, USART2, USART3, UART4 or UART5.
+  * @param  USART_Address: Indicates the address of the USART node.
+  * @retval None
+  */
+void USART_SetAddress(USART_TypeDef* USARTx, uint8_t USART_Address)
+{
+  /* Check the parameters */
+  assert_param(IS_USART_ALL_PERIPH(USARTx));
+  assert_param(IS_USART_ADDRESS(USART_Address)); 
+    
+  /* Clear the USART address */
+  USARTx->CR2 &= CR2_Address_Mask;
+  /* Set the USART address node */
+  USARTx->CR2 |= USART_Address;
+}
+
+/**
+  * @brief  Selects the USART WakeUp method.
+  * @param  USARTx: Select the USART or the UART peripheral. 
+  *   This parameter can be one of the following values:
+  *   USART1, USART2, USART3, UART4 or UART5.
+  * @param  USART_WakeUp: specifies the USART wakeup method.
+  *   This parameter can be one of the following values:
+  *     @arg USART_WakeUp_IdleLine: WakeUp by an idle line detection
+  *     @arg USART_WakeUp_AddressMark: WakeUp by an address mark
+  * @retval None
+  */
+void USART_WakeUpConfig(USART_TypeDef* USARTx, uint16_t USART_WakeUp)
+{
+  /* Check the parameters */
+  assert_param(IS_USART_ALL_PERIPH(USARTx));
+  assert_param(IS_USART_WAKEUP(USART_WakeUp));
+  
+  USARTx->CR1 &= CR1_WAKE_Mask;
+  USARTx->CR1 |= USART_WakeUp;
+}
+
+/**
+  * @brief  Determines if the USART is in mute mode or not.
+  * @param  USARTx: Select the USART or the UART peripheral. 
+  *   This parameter can be one of the following values:
+  *   USART1, USART2, USART3, UART4 or UART5.
+  * @param  NewState: new state of the USART mute mode.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void USART_ReceiverWakeUpCmd(USART_TypeDef* USARTx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_USART_ALL_PERIPH(USARTx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState)); 
+  
+  if (NewState != DISABLE)
+  {
+    /* Enable the USART mute mode  by setting the RWU bit in the CR1 register */
+    USARTx->CR1 |= CR1_RWU_Set;
+  }
+  else
+  {
+    /* Disable the USART mute mode by clearing the RWU bit in the CR1 register */
+    USARTx->CR1 &= CR1_RWU_Reset;
+  }
+}
+
+/**
+  * @brief  Sets the USART LIN Break detection length.
+  * @param  USARTx: Select the USART or the UART peripheral. 
+  *   This parameter can be one of the following values:
+  *   USART1, USART2, USART3, UART4 or UART5.
+  * @param  USART_LINBreakDetectLength: specifies the LIN break detection length.
+  *   This parameter can be one of the following values:
+  *     @arg USART_LINBreakDetectLength_10b: 10-bit break detection
+  *     @arg USART_LINBreakDetectLength_11b: 11-bit break detection
+  * @retval None
+  */
+void USART_LINBreakDetectLengthConfig(USART_TypeDef* USARTx, uint16_t USART_LINBreakDetectLength)
+{
+  /* Check the parameters */
+  assert_param(IS_USART_ALL_PERIPH(USARTx));
+  assert_param(IS_USART_LIN_BREAK_DETECT_LENGTH(USART_LINBreakDetectLength));
+  
+  USARTx->CR2 &= CR2_LBDL_Mask;
+  USARTx->CR2 |= USART_LINBreakDetectLength;  
+}
+
+/**
+  * @brief  Enables or disables the USART�s LIN mode.
+  * @param  USARTx: Select the USART or the UART peripheral. 
+  *   This parameter can be one of the following values:
+  *   USART1, USART2, USART3, UART4 or UART5.
+  * @param  NewState: new state of the USART LIN mode.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void USART_LINCmd(USART_TypeDef* USARTx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_USART_ALL_PERIPH(USARTx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  
+  if (NewState != DISABLE)
+  {
+    /* Enable the LIN mode by setting the LINEN bit in the CR2 register */
+    USARTx->CR2 |= CR2_LINEN_Set;
+  }
+  else
+  {
+    /* Disable the LIN mode by clearing the LINEN bit in the CR2 register */
+    USARTx->CR2 &= CR2_LINEN_Reset;
+  }
+}
+
+/**
+  * @brief  Transmits single data through the USARTx peripheral.
+  * @param  USARTx: Select the USART or the UART peripheral. 
+  *   This parameter can be one of the following values:
+  *   USART1, USART2, USART3, UART4 or UART5.
+  * @param  Data: the data to transmit.
+  * @retval None
+  */
+void USART_SendData(USART_TypeDef* USARTx, uint16_t Data)
+{
+  /* Check the parameters */
+  assert_param(IS_USART_ALL_PERIPH(USARTx));
+  assert_param(IS_USART_DATA(Data)); 
+    
+  /* Transmit Data */
+  USARTx->DR = (Data & (uint16_t)0x01FF);
+}
+
+/**
+  * @brief  Returns the most recent received data by the USARTx peripheral.
+  * @param  USARTx: Select the USART or the UART peripheral. 
+  *   This parameter can be one of the following values:
+  *   USART1, USART2, USART3, UART4 or UART5.
+  * @retval The received data.
+  */
+uint16_t USART_ReceiveData(USART_TypeDef* USARTx)
+{
+  /* Check the parameters */
+  assert_param(IS_USART_ALL_PERIPH(USARTx));
+  
+  /* Receive Data */
+  return (uint16_t)(USARTx->DR & (uint16_t)0x01FF);
+}
+
+/**
+  * @brief  Transmits break characters.
+  * @param  USARTx: Select the USART or the UART peripheral. 
+  *   This parameter can be one of the following values:
+  *   USART1, USART2, USART3, UART4 or UART5.
+  * @retval None
+  */
+void USART_SendBreak(USART_TypeDef* USARTx)
+{
+  /* Check the parameters */
+  assert_param(IS_USART_ALL_PERIPH(USARTx));
+  
+  /* Send break characters */
+  USARTx->CR1 |= CR1_SBK_Set;
+}
+
+/**
+  * @brief  Sets the specified USART guard time.
+  * @param  USARTx: where x can be 1, 2 or 3 to select the USART peripheral.
+  * @param  USART_GuardTime: specifies the guard time.
+  * @note The guard time bits are not available for UART4 and UART5.   
+  * @retval None
+  */
+void USART_SetGuardTime(USART_TypeDef* USARTx, uint8_t USART_GuardTime)
+{    
+  /* Check the parameters */
+  assert_param(IS_USART_123_PERIPH(USARTx));
+  
+  /* Clear the USART Guard time */
+  USARTx->GTPR &= GTPR_LSB_Mask;
+  /* Set the USART guard time */
+  USARTx->GTPR |= (uint16_t)((uint16_t)USART_GuardTime << 0x08);
+}
+
+/**
+  * @brief  Sets the system clock prescaler.
+  * @param  USARTx: Select the USART or the UART peripheral. 
+  *   This parameter can be one of the following values:
+  *   USART1, USART2, USART3, UART4 or UART5.
+  * @param  USART_Prescaler: specifies the prescaler clock.  
+  * @note   The function is used for IrDA mode with UART4 and UART5.
+  * @retval None
+  */
+void USART_SetPrescaler(USART_TypeDef* USARTx, uint8_t USART_Prescaler)
+{ 
+  /* Check the parameters */
+  assert_param(IS_USART_ALL_PERIPH(USARTx));
+  
+  /* Clear the USART prescaler */
+  USARTx->GTPR &= GTPR_MSB_Mask;
+  /* Set the USART prescaler */
+  USARTx->GTPR |= USART_Prescaler;
+}
+
+/**
+  * @brief  Enables or disables the USART�s Smart Card mode.
+  * @param  USARTx: where x can be 1, 2 or 3 to select the USART peripheral.
+  * @param  NewState: new state of the Smart Card mode.
+  *   This parameter can be: ENABLE or DISABLE.     
+  * @note The Smart Card mode is not available for UART4 and UART5. 
+  * @retval None
+  */
+void USART_SmartCardCmd(USART_TypeDef* USARTx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_USART_123_PERIPH(USARTx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  if (NewState != DISABLE)
+  {
+    /* Enable the SC mode by setting the SCEN bit in the CR3 register */
+    USARTx->CR3 |= CR3_SCEN_Set;
+  }
+  else
+  {
+    /* Disable the SC mode by clearing the SCEN bit in the CR3 register */
+    USARTx->CR3 &= CR3_SCEN_Reset;
+  }
+}
+
+/**
+  * @brief  Enables or disables NACK transmission.
+  * @param  USARTx: where x can be 1, 2 or 3 to select the USART peripheral. 
+  * @param  NewState: new state of the NACK transmission.
+  *   This parameter can be: ENABLE or DISABLE.  
+  * @note The Smart Card mode is not available for UART4 and UART5.
+  * @retval None
+  */
+void USART_SmartCardNACKCmd(USART_TypeDef* USARTx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_USART_123_PERIPH(USARTx));  
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  if (NewState != DISABLE)
+  {
+    /* Enable the NACK transmission by setting the NACK bit in the CR3 register */
+    USARTx->CR3 |= CR3_NACK_Set;
+  }
+  else
+  {
+    /* Disable the NACK transmission by clearing the NACK bit in the CR3 register */
+    USARTx->CR3 &= CR3_NACK_Reset;
+  }
+}
+
+/**
+  * @brief  Enables or disables the USART�s Half Duplex communication.
+  * @param  USARTx: Select the USART or the UART peripheral. 
+  *   This parameter can be one of the following values:
+  *   USART1, USART2, USART3, UART4 or UART5.
+  * @param  NewState: new state of the USART Communication.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void USART_HalfDuplexCmd(USART_TypeDef* USARTx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_USART_ALL_PERIPH(USARTx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  
+  if (NewState != DISABLE)
+  {
+    /* Enable the Half-Duplex mode by setting the HDSEL bit in the CR3 register */
+    USARTx->CR3 |= CR3_HDSEL_Set;
+  }
+  else
+  {
+    /* Disable the Half-Duplex mode by clearing the HDSEL bit in the CR3 register */
+    USARTx->CR3 &= CR3_HDSEL_Reset;
+  }
+}
+
+
+/**
+  * @brief  Enables or disables the USART's 8x oversampling mode.
+  * @param  USARTx: Select the USART or the UART peripheral.
+  *   This parameter can be one of the following values:
+  *   USART1, USART2, USART3, UART4 or UART5.
+  * @param  NewState: new state of the USART one bit sampling method.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @note
+  *     This function has to be called before calling USART_Init()
+  *     function in order to have correct baudrate Divider value.   
+  * @retval None
+  */
+void USART_OverSampling8Cmd(USART_TypeDef* USARTx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_USART_ALL_PERIPH(USARTx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  
+  if (NewState != DISABLE)
+  {
+    /* Enable the 8x Oversampling mode by setting the OVER8 bit in the CR1 register */
+    USARTx->CR1 |= CR1_OVER8_Set;
+  }
+  else
+  {
+    /* Disable the 8x Oversampling mode by clearing the OVER8 bit in the CR1 register */
+    USARTx->CR1 &= CR1_OVER8_Reset;
+  }
+}
+
+/**
+  * @brief  Enables or disables the USART's one bit sampling method.
+  * @param  USARTx: Select the USART or the UART peripheral.
+  *   This parameter can be one of the following values:
+  *   USART1, USART2, USART3, UART4 or UART5.
+  * @param  NewState: new state of the USART one bit sampling method.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void USART_OneBitMethodCmd(USART_TypeDef* USARTx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_USART_ALL_PERIPH(USARTx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  
+  if (NewState != DISABLE)
+  {
+    /* Enable the one bit method by setting the ONEBITE bit in the CR3 register */
+    USARTx->CR3 |= CR3_ONEBITE_Set;
+  }
+  else
+  {
+    /* Disable tthe one bit method by clearing the ONEBITE bit in the CR3 register */
+    USARTx->CR3 &= CR3_ONEBITE_Reset;
+  }
+}
+
+/**
+  * @brief  Configures the USART's IrDA interface.
+  * @param  USARTx: Select the USART or the UART peripheral. 
+  *   This parameter can be one of the following values:
+  *   USART1, USART2, USART3, UART4 or UART5.
+  * @param  USART_IrDAMode: specifies the IrDA mode.
+  *   This parameter can be one of the following values:
+  *     @arg USART_IrDAMode_LowPower
+  *     @arg USART_IrDAMode_Normal
+  * @retval None
+  */
+void USART_IrDAConfig(USART_TypeDef* USARTx, uint16_t USART_IrDAMode)
+{
+  /* Check the parameters */
+  assert_param(IS_USART_ALL_PERIPH(USARTx));
+  assert_param(IS_USART_IRDA_MODE(USART_IrDAMode));
+    
+  USARTx->CR3 &= CR3_IRLP_Mask;
+  USARTx->CR3 |= USART_IrDAMode;
+}
+
+/**
+  * @brief  Enables or disables the USART's IrDA interface.
+  * @param  USARTx: Select the USART or the UART peripheral. 
+  *   This parameter can be one of the following values:
+  *   USART1, USART2, USART3, UART4 or UART5.
+  * @param  NewState: new state of the IrDA mode.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void USART_IrDACmd(USART_TypeDef* USARTx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_USART_ALL_PERIPH(USARTx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+    
+  if (NewState != DISABLE)
+  {
+    /* Enable the IrDA mode by setting the IREN bit in the CR3 register */
+    USARTx->CR3 |= CR3_IREN_Set;
+  }
+  else
+  {
+    /* Disable the IrDA mode by clearing the IREN bit in the CR3 register */
+    USARTx->CR3 &= CR3_IREN_Reset;
+  }
+}
+
+/**
+  * @brief  Checks whether the specified USART flag is set or not.
+  * @param  USARTx: Select the USART or the UART peripheral. 
+  *   This parameter can be one of the following values:
+  *   USART1, USART2, USART3, UART4 or UART5.
+  * @param  USART_FLAG: specifies the flag to check.
+  *   This parameter can be one of the following values:
+  *     @arg USART_FLAG_CTS:  CTS Change flag (not available for UART4 and UART5)
+  *     @arg USART_FLAG_LBD:  LIN Break detection flag
+  *     @arg USART_FLAG_TXE:  Transmit data register empty flag
+  *     @arg USART_FLAG_TC:   Transmission Complete flag
+  *     @arg USART_FLAG_RXNE: Receive data register not empty flag
+  *     @arg USART_FLAG_IDLE: Idle Line detection flag
+  *     @arg USART_FLAG_ORE:  OverRun Error flag
+  *     @arg USART_FLAG_NE:   Noise Error flag
+  *     @arg USART_FLAG_FE:   Framing Error flag
+  *     @arg USART_FLAG_PE:   Parity Error flag
+  * @retval The new state of USART_FLAG (SET or RESET).
+  */
+FlagStatus USART_GetFlagStatus(USART_TypeDef* USARTx, uint16_t USART_FLAG)
+{
+  FlagStatus bitstatus = RESET;
+  /* Check the parameters */
+  assert_param(IS_USART_ALL_PERIPH(USARTx));
+  assert_param(IS_USART_FLAG(USART_FLAG));
+  /* The CTS flag is not available for UART4 and UART5 */
+  if (USART_FLAG == USART_FLAG_CTS)
+  {
+    assert_param(IS_USART_123_PERIPH(USARTx));
+  }  
+  
+  if ((USARTx->SR & USART_FLAG) != (uint16_t)RESET)
+  {
+    bitstatus = SET;
+  }
+  else
+  {
+    bitstatus = RESET;
+  }
+  return bitstatus;
+}
+
+/**
+  * @brief  Clears the USARTx's pending flags.
+  * @param  USARTx: Select the USART or the UART peripheral. 
+  *   This parameter can be one of the following values:
+  *   USART1, USART2, USART3, UART4 or UART5.
+  * @param  USART_FLAG: specifies the flag to clear.
+  *   This parameter can be any combination of the following values:
+  *     @arg USART_FLAG_CTS:  CTS Change flag (not available for UART4 and UART5).
+  *     @arg USART_FLAG_LBD:  LIN Break detection flag.
+  *     @arg USART_FLAG_TC:   Transmission Complete flag.
+  *     @arg USART_FLAG_RXNE: Receive data register not empty flag.
+  *   
+  * @note
+  *   - PE (Parity error), FE (Framing error), NE (Noise error), ORE (OverRun 
+  *     error) and IDLE (Idle line detected) flags are cleared by software 
+  *     sequence: a read operation to USART_SR register (USART_GetFlagStatus()) 
+  *     followed by a read operation to USART_DR register (USART_ReceiveData()).
+  *   - RXNE flag can be also cleared by a read to the USART_DR register 
+  *     (USART_ReceiveData()).
+  *   - TC flag can be also cleared by software sequence: a read operation to 
+  *     USART_SR register (USART_GetFlagStatus()) followed by a write operation
+  *     to USART_DR register (USART_SendData()).
+  *   - TXE flag is cleared only by a write to the USART_DR register 
+  *     (USART_SendData()).
+  * @retval None
+  */
+void USART_ClearFlag(USART_TypeDef* USARTx, uint16_t USART_FLAG)
+{
+  /* Check the parameters */
+  assert_param(IS_USART_ALL_PERIPH(USARTx));
+  assert_param(IS_USART_CLEAR_FLAG(USART_FLAG));
+  /* The CTS flag is not available for UART4 and UART5 */
+  if ((USART_FLAG & USART_FLAG_CTS) == USART_FLAG_CTS)
+  {
+    assert_param(IS_USART_123_PERIPH(USARTx));
+  } 
+   
+  USARTx->SR = (uint16_t)~USART_FLAG;
+}
+
+/**
+  * @brief  Checks whether the specified USART interrupt has occurred or not.
+  * @param  USARTx: Select the USART or the UART peripheral. 
+  *   This parameter can be one of the following values:
+  *   USART1, USART2, USART3, UART4 or UART5.
+  * @param  USART_IT: specifies the USART interrupt source to check.
+  *   This parameter can be one of the following values:
+  *     @arg USART_IT_CTS:  CTS change interrupt (not available for UART4 and UART5)
+  *     @arg USART_IT_LBD:  LIN Break detection interrupt
+  *     @arg USART_IT_TXE:  Tansmit Data Register empty interrupt
+  *     @arg USART_IT_TC:   Transmission complete interrupt
+  *     @arg USART_IT_RXNE: Receive Data register not empty interrupt
+  *     @arg USART_IT_IDLE: Idle line detection interrupt
+  *     @arg USART_IT_ORE:  OverRun Error interrupt
+  *     @arg USART_IT_NE:   Noise Error interrupt
+  *     @arg USART_IT_FE:   Framing Error interrupt
+  *     @arg USART_IT_PE:   Parity Error interrupt
+  * @retval The new state of USART_IT (SET or RESET).
+  */
+ITStatus USART_GetITStatus(USART_TypeDef* USARTx, uint16_t USART_IT)
+{
+  uint32_t bitpos = 0x00, itmask = 0x00, usartreg = 0x00;
+  ITStatus bitstatus = RESET;
+  /* Check the parameters */
+  assert_param(IS_USART_ALL_PERIPH(USARTx));
+  assert_param(IS_USART_GET_IT(USART_IT));
+  /* The CTS interrupt is not available for UART4 and UART5 */ 
+  if (USART_IT == USART_IT_CTS)
+  {
+    assert_param(IS_USART_123_PERIPH(USARTx));
+  }   
+  
+  /* Get the USART register index */
+  usartreg = (((uint8_t)USART_IT) >> 0x05);
+  /* Get the interrupt position */
+  itmask = USART_IT & IT_Mask;
+  itmask = (uint32_t)0x01 << itmask;
+  
+  if (usartreg == 0x01) /* The IT  is in CR1 register */
+  {
+    itmask &= USARTx->CR1;
+  }
+  else if (usartreg == 0x02) /* The IT  is in CR2 register */
+  {
+    itmask &= USARTx->CR2;
+  }
+  else /* The IT  is in CR3 register */
+  {
+    itmask &= USARTx->CR3;
+  }
+  
+  bitpos = USART_IT >> 0x08;
+  bitpos = (uint32_t)0x01 << bitpos;
+  bitpos &= USARTx->SR;
+  if ((itmask != (uint16_t)RESET)&&(bitpos != (uint16_t)RESET))
+  {
+    bitstatus = SET;
+  }
+  else
+  {
+    bitstatus = RESET;
+  }
+  
+  return bitstatus;  
+}
+
+/**
+  * @brief  Clears the USARTx's interrupt pending bits.
+  * @param  USARTx: Select the USART or the UART peripheral. 
+  *   This parameter can be one of the following values:
+  *   USART1, USART2, USART3, UART4 or UART5.
+  * @param  USART_IT: specifies the interrupt pending bit to clear.
+  *   This parameter can be one of the following values:
+  *     @arg USART_IT_CTS:  CTS change interrupt (not available for UART4 and UART5)
+  *     @arg USART_IT_LBD:  LIN Break detection interrupt
+  *     @arg USART_IT_TC:   Transmission complete interrupt. 
+  *     @arg USART_IT_RXNE: Receive Data register not empty interrupt.
+  *   
+  * @note
+  *   - PE (Parity error), FE (Framing error), NE (Noise error), ORE (OverRun 
+  *     error) and IDLE (Idle line detected) pending bits are cleared by 
+  *     software sequence: a read operation to USART_SR register 
+  *     (USART_GetITStatus()) followed by a read operation to USART_DR register 
+  *     (USART_ReceiveData()).
+  *   - RXNE pending bit can be also cleared by a read to the USART_DR register 
+  *     (USART_ReceiveData()).
+  *   - TC pending bit can be also cleared by software sequence: a read 
+  *     operation to USART_SR register (USART_GetITStatus()) followed by a write 
+  *     operation to USART_DR register (USART_SendData()).
+  *   - TXE pending bit is cleared only by a write to the USART_DR register 
+  *     (USART_SendData()).
+  * @retval None
+  */
+void USART_ClearITPendingBit(USART_TypeDef* USARTx, uint16_t USART_IT)
+{
+  uint16_t bitpos = 0x00, itmask = 0x00;
+  /* Check the parameters */
+  assert_param(IS_USART_ALL_PERIPH(USARTx));
+  assert_param(IS_USART_CLEAR_IT(USART_IT));
+  /* The CTS interrupt is not available for UART4 and UART5 */
+  if (USART_IT == USART_IT_CTS)
+  {
+    assert_param(IS_USART_123_PERIPH(USARTx));
+  }   
+  
+  bitpos = USART_IT >> 0x08;
+  itmask = ((uint16_t)0x01 << (uint16_t)bitpos);
+  USARTx->SR = (uint16_t)~itmask;
+}
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/STM32_4路称重_Git提交精简工程/src/STM32F10x_FWLib/src/stm32f10x_wwdg.c b/STM32_4路称重_Git提交精简工程/src/STM32F10x_FWLib/src/stm32f10x_wwdg.c
new file mode 100755
index 0000000..77a7ce5
--- /dev/null
+++ b/STM32_4路称重_Git提交精简工程/src/STM32F10x_FWLib/src/stm32f10x_wwdg.c
@@ -0,0 +1,224 @@
+/**
+  ******************************************************************************
+  * @file    stm32f10x_wwdg.c
+  * @author  MCD Application Team
+  * @version V3.5.0
+  * @date    11-March-2011
+  * @brief   This file provides all the WWDG firmware functions.
+  ******************************************************************************
+  * @attention
+  *
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+  *
+  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x_wwdg.h"
+#include "stm32f10x_rcc.h"
+
+/** @addtogroup STM32F10x_StdPeriph_Driver
+  * @{
+  */
+
+/** @defgroup WWDG 
+  * @brief WWDG driver modules
+  * @{
+  */
+
+/** @defgroup WWDG_Private_TypesDefinitions
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup WWDG_Private_Defines
+  * @{
+  */
+
+/* ----------- WWDG registers bit address in the alias region ----------- */
+#define WWDG_OFFSET       (WWDG_BASE - PERIPH_BASE)
+
+/* Alias word address of EWI bit */
+#define CFR_OFFSET        (WWDG_OFFSET + 0x04)
+#define EWI_BitNumber     0x09
+#define CFR_EWI_BB        (PERIPH_BB_BASE + (CFR_OFFSET * 32) + (EWI_BitNumber * 4))
+
+/* --------------------- WWDG registers bit mask ------------------------ */
+
+/* CR register bit mask */
+#define CR_WDGA_Set       ((uint32_t)0x00000080)
+
+/* CFR register bit mask */
+#define CFR_WDGTB_Mask    ((uint32_t)0xFFFFFE7F)
+#define CFR_W_Mask        ((uint32_t)0xFFFFFF80)
+#define BIT_Mask          ((uint8_t)0x7F)
+
+/**
+  * @}
+  */
+
+/** @defgroup WWDG_Private_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup WWDG_Private_Variables
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup WWDG_Private_FunctionPrototypes
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup WWDG_Private_Functions
+  * @{
+  */
+
+/**
+  * @brief  Deinitializes the WWDG peripheral registers to their default reset values.
+  * @param  None
+  * @retval None
+  */
+void WWDG_DeInit(void)
+{
+  RCC_APB1PeriphResetCmd(RCC_APB1Periph_WWDG, ENABLE);
+  RCC_APB1PeriphResetCmd(RCC_APB1Periph_WWDG, DISABLE);
+}
+
+/**
+  * @brief  Sets the WWDG Prescaler.
+  * @param  WWDG_Prescaler: specifies the WWDG Prescaler.
+  *   This parameter can be one of the following values:
+  *     @arg WWDG_Prescaler_1: WWDG counter clock = (PCLK1/4096)/1
+  *     @arg WWDG_Prescaler_2: WWDG counter clock = (PCLK1/4096)/2
+  *     @arg WWDG_Prescaler_4: WWDG counter clock = (PCLK1/4096)/4
+  *     @arg WWDG_Prescaler_8: WWDG counter clock = (PCLK1/4096)/8
+  * @retval None
+  */
+void WWDG_SetPrescaler(uint32_t WWDG_Prescaler)
+{
+  uint32_t tmpreg = 0;
+  /* Check the parameters */
+  assert_param(IS_WWDG_PRESCALER(WWDG_Prescaler));
+  /* Clear WDGTB[1:0] bits */
+  tmpreg = WWDG->CFR & CFR_WDGTB_Mask;
+  /* Set WDGTB[1:0] bits according to WWDG_Prescaler value */
+  tmpreg |= WWDG_Prescaler;
+  /* Store the new value */
+  WWDG->CFR = tmpreg;
+}
+
+/**
+  * @brief  Sets the WWDG window value.
+  * @param  WindowValue: specifies the window value to be compared to the downcounter.
+  *   This parameter value must be lower than 0x80.
+  * @retval None
+  */
+void WWDG_SetWindowValue(uint8_t WindowValue)
+{
+  __IO uint32_t tmpreg = 0;
+
+  /* Check the parameters */
+  assert_param(IS_WWDG_WINDOW_VALUE(WindowValue));
+  /* Clear W[6:0] bits */
+
+  tmpreg = WWDG->CFR & CFR_W_Mask;
+
+  /* Set W[6:0] bits according to WindowValue value */
+  tmpreg |= WindowValue & (uint32_t) BIT_Mask;
+
+  /* Store the new value */
+  WWDG->CFR = tmpreg;
+}
+
+/**
+  * @brief  Enables the WWDG Early Wakeup interrupt(EWI).
+  * @param  None
+  * @retval None
+  */
+void WWDG_EnableIT(void)
+{
+  *(__IO uint32_t *) CFR_EWI_BB = (uint32_t)ENABLE;
+}
+
+/**
+  * @brief  Sets the WWDG counter value.
+  * @param  Counter: specifies the watchdog counter value.
+  *   This parameter must be a number between 0x40 and 0x7F.
+  * @retval None
+  */
+void WWDG_SetCounter(uint8_t Counter)
+{
+  /* Check the parameters */
+  assert_param(IS_WWDG_COUNTER(Counter));
+  /* Write to T[6:0] bits to configure the counter value, no need to do
+     a read-modify-write; writing a 0 to WDGA bit does nothing */
+  WWDG->CR = Counter & BIT_Mask;
+}
+
+/**
+  * @brief  Enables WWDG and load the counter value.                  
+  * @param  Counter: specifies the watchdog counter value.
+  *   This parameter must be a number between 0x40 and 0x7F.
+  * @retval None
+  */
+void WWDG_Enable(uint8_t Counter)
+{
+  /* Check the parameters */
+  assert_param(IS_WWDG_COUNTER(Counter));
+  WWDG->CR = CR_WDGA_Set | Counter;
+}
+
+/**
+  * @brief  Checks whether the Early Wakeup interrupt flag is set or not.
+  * @param  None
+  * @retval The new state of the Early Wakeup interrupt flag (SET or RESET)
+  */
+FlagStatus WWDG_GetFlagStatus(void)
+{
+  return (FlagStatus)(WWDG->SR);
+}
+
+/**
+  * @brief  Clears Early Wakeup interrupt flag.
+  * @param  None
+  * @retval None
+  */
+void WWDG_ClearFlag(void)
+{
+  WWDG->SR = (uint32_t)RESET;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/STM32_4路称重_Git提交精简工程/src/SYSTEM/debug/debug_conf.c b/STM32_4路称重_Git提交精简工程/src/SYSTEM/debug/debug_conf.c
new file mode 100755
index 0000000..8a901fd
--- /dev/null
+++ b/STM32_4路称重_Git提交精简工程/src/SYSTEM/debug/debug_conf.c
@@ -0,0 +1,36 @@
+/*************************** (C) COPYRIGHT 2017 YNHB ****************************
+ * �ļ���  ��debug_output.c
+ * ��  ��  �����������ӡ��Ϣ
+ * ��  ��  ��V1.0
+ * ��  ��  ��XuZhongPing
+ * ��  ��  ��2017/04/26 
+*********************************************************************************/
+#include "debug_conf.h"
+  
+//�������´���,֧��printf����,������Ҫѡ��use MicroLIB	  
+#if 1
+#pragma import(__use_no_semihosting)             
+//��׼����Ҫ��֧�ֺ���                 
+struct __FILE 
+{ 
+	int handle;
+}; 
+
+FILE __stdout;       
+//����_sys_exit()�Ա���ʹ�ð�����ģʽ    
+_sys_exit(int x) 
+{ 
+	x = x; 
+}
+
+//�ض���fputc���� 
+int fputc(int ch, FILE *f)
+{      
+	while(USART_GetFlagStatus(UART5,USART_FLAG_TC)==RESET){}; 
+	USART_SendData(UART5, (uint8_t)ch);   
+	return ch;
+}
+
+#endif 
+
+/******************** (C) COPYRIGHT 2017 YNHB *****END OF FILE*******************/
diff --git a/STM32_4路称重_Git提交精简工程/src/SYSTEM/debug/debug_conf.h b/STM32_4路称重_Git提交精简工程/src/SYSTEM/debug/debug_conf.h
new file mode 100755
index 0000000..398e756
--- /dev/null
+++ b/STM32_4路称重_Git提交精简工程/src/SYSTEM/debug/debug_conf.h
@@ -0,0 +1,16 @@
+/*************************** (C) COPYRIGHT 2017 YNHB ****************************
+ * �ļ���  ��debug_output.h
+ * ��  ��  �����������ӡ��Ϣͷ�ļ�
+ * ��  ��  ��V1.0
+ * ��  ��  ��XuZhongPing
+ * ��  ��  ��2017/04/26 
+*********************************************************************************/
+#ifndef __DEBUG_OUTPUT_H
+#define __DEBUG_OUTPUT_H
+
+#include "stm32f10x.h"
+#include "stdio.h"
+
+#endif
+
+/******************** (C) COPYRIGHT 2017 YNHB *****END OF FILE*******************/
diff --git a/STM32_4路称重_Git提交精简工程/src/SYSTEM/delay/delay.c b/STM32_4路称重_Git提交精简工程/src/SYSTEM/delay/delay.c
new file mode 100755
index 0000000..2582b2d
--- /dev/null
+++ b/STM32_4路称重_Git提交精简工程/src/SYSTEM/delay/delay.c
@@ -0,0 +1,54 @@
+#include "delay.h"
+	 
+static u8  fac_us=0;//us��ʱ������
+static u16 fac_ms=0;//ms��ʱ������
+
+//��ʼ���ӳٺ���
+//��ʹ��ucos��ʱ��,�˺������ʼ��ucos��ʱ�ӽ���
+//SYSTICK��ʱ�ӹ̶�ΪHCLKʱ�ӵ�1/8
+//SYSCLK:ϵͳʱ��
+void delay_init()	 
+{
+	SysTick_CLKSourceConfig(SysTick_CLKSource_HCLK_Div8);	//ѡ���ⲿʱ��  HCLK/8
+	fac_us=SystemCoreClock/8000000;	//Ϊϵͳʱ�ӵ�1/8  
+	 
+	fac_ms=(u16)fac_us*1000;//��ucos��,����ÿ��ms��Ҫ��systickʱ����   
+}								    
+
+//��ʱnus
+//nusΪҪ��ʱ��us��.		    								   
+void delay_us(u32 nus)
+{		
+	u32 temp;	    	 
+	SysTick->LOAD=nus*fac_us; //ʱ�����	  		 
+	SysTick->VAL=0x00;        //��ռ�����
+	SysTick->CTRL|=SysTick_CTRL_ENABLE_Msk ;          //��ʼ����	 
+	do
+	{
+		temp=SysTick->CTRL;
+	}
+	while(temp&0x01&&!(temp&(1<<16)));//�ȴ�ʱ�䵽��   
+	SysTick->CTRL&=~SysTick_CTRL_ENABLE_Msk;       //�رռ�����
+	SysTick->VAL =0X00;       //��ռ�����	 
+}
+//��ʱnms
+//ע��nms�ķ�Χ
+//SysTick->LOADΪ24λ�Ĵ���,����,�����ʱΪ:
+//nms<=0xffffff*8*1000/SYSCLK
+//SYSCLK��λΪHz,nms��λΪms
+//��72M������,nms<=1864 
+void delay_ms(u16 nms)
+{	 		  	  
+	u32 temp;		   
+	SysTick->LOAD=(u32)nms*fac_ms;//ʱ�����(SysTick->LOADΪ24bit)
+	SysTick->VAL =0x00;           //��ռ�����
+	SysTick->CTRL|=SysTick_CTRL_ENABLE_Msk ;          //��ʼ����  
+	do
+	{
+		temp=SysTick->CTRL;
+	}
+	while(temp&0x01&&!(temp&(1<<16)));//�ȴ�ʱ�䵽��   
+	SysTick->CTRL&=~SysTick_CTRL_ENABLE_Msk;       //�رռ�����
+	SysTick->VAL =0X00;       //��ռ�����	  	    
+} 
+
diff --git a/STM32_4路称重_Git提交精简工程/src/SYSTEM/delay/delay.h b/STM32_4路称重_Git提交精简工程/src/SYSTEM/delay/delay.h
new file mode 100755
index 0000000..0f8145d
--- /dev/null
+++ b/STM32_4路称重_Git提交精简工程/src/SYSTEM/delay/delay.h
@@ -0,0 +1,10 @@
+#ifndef __DELAY_H
+#define __DELAY_H 			   
+#include "stm32f10x.h"
+
+void delay_init(void);
+void delay_ms(u16 nms);
+void delay_us(u32 nus);
+
+#endif
+
diff --git a/STM32_4路称重_Git提交精简工程/src/USER/data_typedef.c b/STM32_4路称重_Git提交精简工程/src/USER/data_typedef.c
new file mode 100755
index 0000000..fdf955b
--- /dev/null
+++ b/STM32_4路称重_Git提交精简工程/src/USER/data_typedef.c
@@ -0,0 +1,371 @@
+/*************************** (C) COPYRIGHT 2017 CXHY ****************************
+ * �ļ���  ��DataProcessing.c
+ * ��  ��  �����ݴ�������     
+ * ��  ��  ��V1.0
+ * ��  ��  ��XuZhongPing
+ * ��  ��  ��2017/03/05 
+*********************************************************************************/
+#include "my_math.h"
+#include "delay.h"
+#include "data_typedef.h"	  
+#include "gsm_gprs.h" 
+#include "gps.h" 
+#include "message.h"
+#include "tcp_protocol.h"
+#include "device.h"
+
+char VersionStr[17];
+
+uint8_t deviceInitFlag = 0;								//�豸Ӳ���ӿڳ�ʼ����ɱ�־
+uint8_t swKeysVal = 0;
+uint8_t adcDevInitOK = 0;
+uint8_t synchronousOpenDoorMark = 1;			//ͬ�����ű�־��1��Ϊͬʱ���ţ�0��Ϊ�������ţ�
+
+uint16_t delayRandomTime = 0;							//����Ͽ���������ʱ�������ʱ��
+
+uint8_t water;														//ˮλ
+
+uint8_t optoSwitchStatus = 0;							//��翪��״̬
+uint8_t switchKey1Status = 0;							//�ӽ�����״̬
+uint8_t switchKey2Status = 0;							//�ӽ�����״̬
+uint8_t dropOffPortMark1 = 0;
+uint8_t dropOffPortMark2 = 0;
+
+uint8_t getRecycleClearDoorMark = 0;			//Ӳ����ȡ��������״̬
+uint8_t recycleClearDoorMark = 0;					//������״̬
+
+uint8_t smokeAlarmStatus = 0;							//��������״̬
+
+uint8_t dropPortClosedStatus1 = 0;				//Ͷ�ſڹر�״̬
+uint8_t dropPortClosedStatus2 = 0;
+
+uint8_t gpsConnectSta = 0;								//GPSģ��Ӳ������״̬
+uint8_t gpsStatus = 0;										//GPS��λ״̬
+uint8_t gpsEW = 0;												//���ȷ���0->E-��,W-����
+uint32_t gpsLon = 0;											//���ȣ��ѷŴ�1000000����
+uint8_t  gpsNS = 0;												//γ�ȷ���0->N-��,1->S-�ϣ�
+uint32_t gpsLat = 0;											//γ�ȣ��ѷŴ�1000000����
+uint8_t getGpsStatus = 0;									//ȡ��GPS��Ϣ
+
+uint8_t distance = 255;										//��·�������
+uint8_t getDistance1 = 255;								//������ֵ
+uint8_t getDistance2 = 255;								
+uint8_t getDistance3 = 255;								
+uint8_t getDistance4 = 255;		
+uint8_t updateDistanceMark = 0;	
+
+uint8_t fullMarkLeft = 0;									//��Ͱװ����־
+uint8_t fullMarkRight = 0;								//��Ͱװ����־
+
+uint8_t fullMark1 = 0;
+uint8_t fullMark2 = 0;
+uint8_t fullMark3 = 0;
+uint8_t fullMark4 = 0;
+
+uint16_t getWeight1 = 0;									//ȡ�õ�����
+uint16_t getWeight2 = 0;									
+uint16_t getWeight3 = 0;									
+uint16_t getWeight4 = 0;
+
+uint16_t getWeightBefore1 = 0;						//ȡ�õĵ�1·����Ͱ������������ǰ��
+uint16_t getWeightAfter1 = 0;							//ȡ�õĵ�1·����Ͱ�����������ź�
+uint16_t getWeightBefore2 = 0;						
+uint16_t getWeightAfter2 = 0;							
+uint16_t getWeightBefore3 = 0;						
+uint16_t getWeightAfter3 = 0;							
+uint16_t getWeightBefore4 = 0;					
+uint16_t getWeightAfter4 = 0;
+
+uint16_t weightChangeBefore_1 = 0;				//�����仯ǰ������
+uint16_t weightChangeBefore_2 = 0;							
+
+//�쳣����Ͷ������
+uint16_t exceptionWeight1 = 0;						//��⵽���쳣����Ͷ������
+uint16_t exceptionWeight2 = 0;									
+uint16_t exceptionWeight3 = 0;									
+uint16_t exceptionWeight4 = 0;		
+
+uint16_t exceptionWeightBefore1 = 0;			//ȡ�õĵ�1·�쳣Ͷ������������ǰ��
+uint16_t exceptionWeightAfter1 = 0;				//ȡ�õĵ�1·�쳣Ͷ�����������׺�
+uint16_t exceptionWeightBefore2 = 0;						
+uint16_t exceptionWeightAfter2 = 0;							
+uint16_t exceptionWeightBefore3 = 0;						
+uint16_t exceptionWeightAfter3 = 0;							
+uint16_t exceptionWeightBefore4 = 0;					
+uint16_t exceptionWeightAfter4 = 0;	
+
+uint16_t smallBottleCount = 0;						//С����ƿ����
+uint16_t bigBottleCount = 0;							//������ƿ����
+uint16_t cansCount = 0;										//��������������
+
+uint8_t getPutInType = 0;									//���յ���Ͷ�����ͣ���ť��IC������ά�롢�����������룩
+uint8_t getDataLength = 0;								//���յ���������Ϣ����
+uint8_t getDataBuf[256];										//���յ���������Ϣ����
+
+uint8_t sendPutInType = 0;								//����Ͷ�����ͣ���ť��IC������ά�롢�����������룩
+uint8_t sendDataLength = 0;								//����������Ϣ�ĳ���
+uint8_t sendDataBuf[256];									//����������Ϣ����
+
+uint8_t pcRequestOpenDoorMark = 0;				//��λ�������Ͷ�ſ�
+uint8_t openDoorNumber = 0;								//����򿪵�Ͷ�ڱ��
+
+uint8_t rspPCDoorNumber = 0;							//Ӧ����λ��Ͷ�ڱ��
+uint8_t rspPCWeightNumber = 0;						//Ӧ����λ�����̱��
+uint8_t rspPCDistanceNumber = 0;					//Ӧ����λ�������		
+uint8_t rspPCTemperatureNumber = 0;				//Ӧ����λ���¶ȱ��
+
+uint8_t pcRequestClooseDoorMark = 0;			//��λ������ر�Ͷ�ſ�
+
+//�����û���Ϣ�ϴ�
+uint8_t collectorSendAuthType = 0;				//����Ͷ�����ͣ���ť��IC������ά�롢�����������룩
+uint8_t collectorSendDataLength = 0;			//����������Ϣ�ĳ���
+uint8_t collectorSendDataBuf[35];					//����������Ϣ����
+
+uint8_t get_IC_ID[16];											//���յ���IC����
+uint8_t send_IC_ID[16];										//��Ҫ���͵���̨��IC����
+uint8_t getCardNumberBit[32];							//���ŷ��������17λʮ��������
+
+
+//��̨����Ӧ����ر���
+uint8_t userInfoQueryStatus = 0;					//�Ӻ�̨��ȡ�û���Ϣ����״̬
+uint8_t getUserInfoMark = 0;							//ȡ���û���Ϣ��־
+uint8_t putInUploadSuccessMark = 0;				//Ͷ���ϴ��ɹ���־
+uint8_t getSetDistanceParamMark = 0;			//ȡ�ú�̨�����������
+uint8_t getDeviceWorkStatusMark = 0;			//ȡ�ú�̨���õ��豸����״̬��־
+
+uint8_t deviceStatus = 0;									//�����������豸״̬
+
+uint8_t  isAuth;													//�Ƿ�ͨ����֤
+uint32_t userID;													//�û�ID
+uint32_t accountNum;											//�û��˺�
+uint8_t  nickNameLength;									//�ǳ����ݳ���
+uint8_t  nickName[64];										//�ǳ�����
+uint32_t capital = 0;											//�ʽ�
+uint32_t capitalAfter = 0;								//�ʽ�Ͷ�ź����
+uint8_t  residue;													//�����
+uint8_t  businessNum[8];									//������ˮ�� 
+uint16_t receiveBusinessNum;							//��̨���صĽ�����ˮ��
+uint8_t  isOutput;												//�Ƿ���Գ���
+
+uint8_t  barcodeLength = 0;								//��������ά�����ݳ���
+uint8_t  barcode[32];											//��������ά������
+
+//���������
+uint8_t getBoxOpenAckMark = 0;						//ȡ�ú�̨���ش�������״̬��־
+uint8_t boxOpenAckStatus = 0;							//��̨Ӧ��������Ŵ򿪱�־	
+
+//Ͷ�Ź��������õı���
+uint8_t putInProgress = 0;								//Ͷ�Ž����б�־
+uint8_t isOpenDoor = 0;
+uint8_t keyOpenDoorRequest = 0;						//������������
+
+uint8_t isOpenDoorRequest_1 = 0;					//�����ű�־
+uint8_t isOpenDoorRequest_2 = 0;
+uint8_t isOpenDoorRequest_3 = 0;
+uint8_t isOpenDoorRequest_4 = 0;
+uint8_t isOpenDoor_1 = 0;									//���ű�־
+uint8_t isOpenDoor_2 = 0;
+uint8_t isOpenDoor_3 = 0;
+uint8_t isOpenDoor_4 = 0;
+
+uint8_t isCloseDoorMark_1 = 0;						//������ű�־
+uint8_t isCloseDoorMark_2 = 0;
+uint8_t isCloseDoorMark_3 = 0;
+uint8_t isCloseDoorMark_4 = 0;
+
+uint8_t openDoorCtrlEndMark_1 = 0;				//�����ſ��ƽ�����־
+uint8_t openDoorCtrlEndMark_2 = 0;
+uint8_t openDoorCtrlEndMark_3 = 0;
+uint8_t openDoorCtrlEndMark_4 = 0;
+
+uint8_t putInEndMark = 0;									//�豸��ת���ƽ�����־
+
+uint8_t delayCloseDoorStatus = 0;					//���յ��ӳٹ���
+uint8_t delayCloseDoorStatus2 = 0;				//���յ��ӳٹ���
+
+uint8_t disablePutInMark = 0;							//��ֹͶ����ɱ�־
+uint8_t putInOKMark = 0;									//Ͷ����ɱ�־
+
+uint8_t getRemainingTimerStatus = 0;			//ȡ�õ���ʱʱ��״̬
+uint8_t remainingTimer = 0; 							//ʣ�����ʱ��
+
+uint8_t faceEntryFlag = 0;								//����¼�������־
+
+uint8_t devChannel1FaultMark = 0;					//���ϱ�־
+uint8_t devChannel2FaultMark = 0;					//���ϱ�־
+uint8_t devChannel3FaultMark = 0;					//���ϱ�־
+uint8_t devChannel4FaultMark = 0;					//���ϱ�־
+uint8_t deviceFault = 0;									//�豸����
+uint8_t faultLedFlashMark = 0;						//����ʱ����˸��־
+uint8_t faultCode_1 = 0;									//������
+uint8_t faultCode_2 = 0;
+uint8_t faultCode_3 = 0;
+uint8_t faultCode_4 = 0;
+uint8_t limitKeyExceptionMark = 0;				//��λ�����쳣��־
+uint8_t displayFaultCode = 0;							//��ʾ�Ĺ�����
+
+uint8_t exitMark = 0;											//�˳���־
+
+uint8_t boxOpenRecordMark = 0;						//���������ſ��ż�¼��־����־�Ƿ��Ѿ�������������ʱ��ά�뿪�ţ�
+uint8_t boxOpenMark = 0;									//ȡ����ʱ��ά�뿪���������ű�־
+uint8_t boxOpenQRMark = 0;								//ȡ����ʱ��ά�뿪���������ű�־
+
+//�豸��ز���
+//��ǰʹ�õĲ�������
+//>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>
+uint8_t deviceType = FOUR_CLASSIFICATION;		//�豸�����ͣ�Ĭ���ķ��ࣩ
+uint8_t devChannelNumbers = 4;						//Ͷ�ſ�ͨ������
+uint8_t leftBarrelType = GLASS;						//�豸��Ͱ����
+uint8_t rightBarrelType = METAL;					//�豸��Ͱ����
+
+uint8_t devChannel1Type = GLASS;					//�豸ͨ������
+uint8_t devChannel2Type = METAL;
+uint8_t devChannel3Type = PLASTIC;
+uint8_t devChannel4Type = PAPER;
+
+uint32_t password = 123321;								//�豸��������
+uint32_t customerID = 000000;							//�ͻ��ţ����ڿ���˭���Դ����������ţ�
+
+uint8_t distance_L_DepthVal;				//������Ͱ���Ͱ����ȣ�����Ͱ�ĸ߶ȣ�
+uint8_t distance_L_MaxVal;					//������Ͱ������ֵ������װ��ߵ��ֵ��
+uint8_t distance_L_AlarmPercent;		//������Ͱ���װ�������ٷֱ�
+
+uint8_t distance_R_MaxVal;					//������Ͱ������ֵ������װ��ߵ��ֵ��
+uint8_t distance_R_DepthVal;				//������Ͱ���Ͱ����ȣ�����Ͱ�ĸ߶ȣ�
+uint8_t distance_R_AlarmPercent;		//������Ͱ���װ�������ٷֱ�
+
+//�豸ͨ���������
+uint8_t distanceParamAtStart = 0;		//��ʼ����������������
+uint8_t PerCentSetVal = 30;					//��ʼ�������İٷֱ�����ֵ
+
+uint8_t devChannel1DisDepthVal = 100;				//���ò��Ͱ����ȣ�����Ͱ�ĸ߶ȣ�
+uint8_t devChannel1DisMaxVal = 155;					//���ò�����ֵ������װ��ߵ��ֵ��
+uint8_t devChannel1DisAlarmPercent = 90;		//���ò��װ�������ٷֱ�
+
+uint8_t devChannel2DisDepthVal = 100;				
+uint8_t devChannel2DisMaxVal = 155;
+uint8_t devChannel2DisAlarmPercent = 90;
+
+uint8_t devChannel3DisDepthVal = 100;
+uint8_t devChannel3DisMaxVal = 160;
+uint8_t devChannel3DisAlarmPercent = 90;
+
+uint8_t devChannel4DisDepthVal = 100;
+uint8_t devChannel4DisMaxVal = 160;
+uint8_t devChannel4DisAlarmPercent = 90;
+
+uint8_t disableICCardFunStatus = 0;				//����/ͣ�á����õ�IC�����ܿ��š����ܱ�־λ��1��ͣ�ù��ܣ��������ù��ܣ�Ĭ�����ù���
+uint8_t enableCleanQRCodeStatus = 0;			//����/ͣ�á����˶�ά�뿪�š����ܱ�־λ��1�����ù��ܣ�����ͣ�ù��ܣ�Ĭ��ͣ�ù���
+
+uint8_t deviceIdLength = 0;								//�豸��ų���
+uint8_t deviceIdBuf[33] = {0};						//�豸���
+
+uint8_t ipAddr0 = 255, ipAddr1 = 255, ipAddr2 = 255, ipAddr3 = 255;
+uint16_t ipPort = 8080;
+
+//ȡ�õĴ��޸ĺ󱣴�Ĳ�����������flash��ȡ������ͨ����ά��ȡ�õĴ������ʹ�õĲ���������
+uint8_t setDeviceType = 0;								//���õ��豸����
+uint8_t setDevChannelNumbers = 0;					//����ʱȡ�õ�Ͷ�ſ�ͨ������
+uint8_t setDevChannel1Type = 0;						//�����豸ͨ����������
+uint8_t setDevChannel2Type = 0;
+uint8_t setDevChannel3Type = 0;
+uint8_t setDevChannel4Type = 0;
+
+uint32_t setPassword = 0;									//Ҫ���õ��豸��������
+uint32_t setCustomerID = 0;								//�ͻ��ţ����ڿ���˭���Դ����������ţ�
+
+uint8_t setDevChannel1DisDepthVal = 0;		//����Ͱ����Ⱦ��루����Ͱ�ĸ߶ȣ�
+uint8_t setDevChannel1DisMaxVal = 0;			//���ô�������װ�߶Ⱦ������ֵ������װ��ߵ��ֵ��
+uint8_t setDevChannel1DisAlarmPercent = 0;//����������뱨���ٷֱ�
+
+uint8_t setDevChannel2DisDepthVal = 0;
+uint8_t setDevChannel2DisMaxVal = 0;
+uint8_t setDevChannel2DisAlarmPercent = 0;
+
+uint8_t setDevChannel3DisDepthVal = 0;
+uint8_t setDevChannel3DisMaxVal = 0;
+uint8_t setDevChannel3DisAlarmPercent = 0;
+
+uint8_t setDevChannel4DisDepthVal = 0;
+uint8_t setDevChannel4DisMaxVal = 0;
+uint8_t setDevChannel4DisAlarmPercent = 0;
+
+uint8_t setDisableICCardFunStatus = 0;		//��������/ͣ�á����õ�IC�����ܿ��š����ܱ�־λ��1��ͣ�ù��ܣ��������ù��ܣ�
+uint8_t setEnableCleanQRCodeStatus = 0;		//��������/ͣ�á����˶�ά�뿪�š����ܱ�־λ��1�����ù��ܣ�����ͣ�ù��ܣ�
+
+uint8_t setDeviceIdLength = 0;						//���õ��豸��ų���
+uint8_t setDeviceIdBuf[33];								//���õ��豸���
+
+uint8_t setIpAddr0 = 0, setIpAddr1 = 0, setIpAddr2 = 0, setIpAddr3 = 0;
+uint16_t setIpPort = 0;
+
+//�û�����ȡ�õĲ�������
+uint8_t getDeviceType = 0;								//ȡ�õ��豸����
+uint8_t getDevChannelNumbers = 0;					//����ʱȡ�õ�Ͷ�ſ�ͨ������
+uint8_t getDevChannel1Type = 0;						//ȡ�õ��豸ͨ����������
+uint8_t getDevChannel2Type = 0;
+uint8_t getDevChannel3Type = 0;
+uint8_t getDevChannel4Type = 0;
+
+uint32_t getConfirmPassword = 0;					//ȡ��ȷ������
+uint32_t getPassword = 0;									//ȡ�õ��豸��������
+uint32_t getCustomerID = 0;								//ȡ�õĿͻ���
+
+uint8_t getDevChannel1DisDepthVal = 0;		//����Ͱ����Ⱦ��루����Ͱ�ĸ߶ȣ�
+uint8_t getDevChannel1DisMaxVal = 0;			//���ô�������װ�߶Ⱦ������ֵ������װ��ߵ��ֵ��
+uint8_t getDevChannel1DisAlarmPercent = 0;//����������뱨���ٷֱ�
+
+uint8_t getDevChannel2DisDepthVal = 0;
+uint8_t getDevChannel2DisMaxVal = 0;
+uint8_t getDevChannel2DisAlarmPercent = 0;
+
+uint8_t getDevChannel3DisDepthVal = 0;
+uint8_t getDevChannel3DisMaxVal = 0;
+uint8_t getDevChannel3DisAlarmPercent = 0;
+
+uint8_t getDevChannel4DisDepthVal = 0;
+uint8_t getDevChannel4DisMaxVal = 0;
+uint8_t getDevChannel4DisAlarmPercent = 0;
+
+uint8_t getDisableICCardFunStatus = 0;		//ȡ������/ͣ�á����õ�IC�����ܿ��š����ܱ�־λ��1��ͣ�ù��ܣ��������ù��ܣ�
+uint8_t getEnableCleanQRCodeStatus = 0;		//ȡ������/ͣ�á����˶�ά�뿪�š����ܱ�־λ��1�����ù��ܣ�����ͣ�ù��ܣ�
+
+uint8_t getDeviceIdLength = 0;						//ȡ�õ��豸��ų���
+uint8_t getDeviceIdBuf[33];								//ȡ�õ��豸���
+
+uint8_t getIpAddr0 = 0, getIpAddr1 = 0, getIpAddr2 = 0, getIpAddr3 = 0;
+uint16_t getIpPort = 0;
+
+uint8_t getScaleNum = 0;									//ȡ��У׼���̵ı��
+
+//��ȡ����ز�����־
+uint8_t setParamSaveMark = 0;							//���ò�����Ҫ���б����־
+uint8_t setParamChangeMark = 0;						//���ò����б仯��־
+
+uint8_t getConfirmPasswordMark = 0;				//ȡ�ô�ȷ�������־
+uint8_t getPasswordMark = 0;							//ȡ��Ҫ���õ������־
+uint8_t getForceChangeMark = 0;						//ȡ��ǿ���޸������־
+uint8_t getDeviceTypeMark = 0;						//ȡ�������豸���ͱ�־
+uint8_t getCustomerIDMark = 0;						//ȡ�����ÿͻ��ű�־
+
+uint8_t getDisableICCardFunMark = 0;			//ȡ������/ͣ�á����õ�IC�����ܿ��š��������ñ�־
+uint8_t getEnableCleanQRCodeMark = 0;			//ȡ������/ͣ�á����˶�ά�뿪�š��������ñ�־
+
+uint8_t getOverflowSetMark = 0;						//ȡ���������������־
+
+uint8_t getScaleCalibrationMark = 0;			//ȡ�ó���У׼��־
+uint8_t getBoxOpenMark = 0;								//ȡ����ʱ��ά�뿪���������ű�־
+
+uint8_t getDeviceParamResetMark = 0;			//ȡ�ûָ���������
+//<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<
+
+uint8_t deviceWorkStatus = 1;							//�豸����״̬��������ͣ�ã�
+uint8_t deviceWorkStatusPre = 1;					//�豸����״̬�л�ǰ��״̬
+uint8_t getDeviceWorkStatusVal = 0;				//ȡ�ú�̨���õĹ���״ֵ̬
+
+uint8_t getMcu2SensorDataMark = 0;				//ȡ��MCU2���͵Ĵ��������ݱ�־
+
+uint16_t netStatus = 0;										//����״̬
+uint16_t devRunnigStatus = 0;							//�豸����״̬
+
+/******************** (C) COPYRIGHT 2017 CXHY *****END OF FILE*******************/ 
diff --git a/STM32_4路称重_Git提交精简工程/src/USER/data_typedef.h b/STM32_4路称重_Git提交精简工程/src/USER/data_typedef.h
new file mode 100755
index 0000000..e5c56e2
--- /dev/null
+++ b/STM32_4路称重_Git提交精简工程/src/USER/data_typedef.h
@@ -0,0 +1,412 @@
+/*************************** (C) COPYRIGHT 2017 CXHY ****************************
+ * �ļ���  ��data_typedef.h
+ * ��  ��  �����ݶ���    
+ * ��  ��  ��V1.0
+ * ��  ��  ��XuZhongPing
+ * ��  ��  ��2017/02/05 
+*********************************************************************************/
+#ifndef __DATA_DEF_H
+#define __DATA_DEF_H	 
+#include "stdio.h"
+#include "stdint.h"
+#include "message.h"
+#include "date_time.h"
+
+// �豸����
+typedef enum
+{   
+// 	SINGLE_BARREL_660L = 1,
+// 	DOUBLE_BARREL_480L = 2,
+// 	DOUBLE_BARREL_BOTTLE_480L = 3,
+// 	SINGLE_BARREL_480L = 4,
+	
+	SINGLE_CLASSIFICATION = 1,
+	DOUBLE_CLASSIFICATION = 2,
+	DOUBLE_CLASSIFICATION_BOTTLE = 3,
+	THREE_CLASSIFICATION = 4,
+	FOUR_CLASSIFICATION = 5,
+	
+}deviceDefine;
+
+// �ɻ���������
+typedef enum
+{    
+	PAPER = 1,										//ֽ��
+	PLASTIC = 3,									//����
+	GLASS = 4,										//����
+	METAL = 5,										//����
+	RECYCLED = 7,									//�ɻ�����
+	KITCHEN = 8,									//����
+	KITCHEN_1 = 81,								//����1
+	KITCHEN_2 = 82,								//����2	
+	BIG_BOTTLE = 9,								//������ƿ��
+	SMALL_BOTTLE = 10,						//С����ƿ��
+	CANS = 11,										//������
+	BATTERY = 13,									//���
+	FABRIC = 14,									//֯��
+	BOOK = 15,										//�鱾
+	NEWSPAPER = 16,								//��ֽ
+	PLASTIC_2 = 17,								//����2
+	OTHER = 18,										//����
+	HARMFUL = 30,									//�к�����
+	DRY_WASTES = 63,							//������
+	WET_WASTES = 64,							//ʪ����
+	PERISHABLE = 68,							//�׸�
+	
+}trashType;
+
+extern char VersionStr[17];
+
+extern uint8_t deviceInitFlag;							//�豸Ӳ���ӿڳ�ʼ����ɱ�־
+extern uint8_t swKeysVal;
+extern uint8_t adcDevInitOK;
+extern uint8_t synchronousOpenDoorMark;			//ͬ�����ű�־		
+
+extern uint16_t delayRandomTime;						//����Ͽ���������ʱ�������ʱ��
+
+extern uint8_t water;												//ˮλ
+
+extern uint8_t optoSwitchStatus;						//��翪��״̬
+extern uint8_t switchKey1Status;						//�ӽ�����״̬
+extern uint8_t switchKey2Status;						//�ӽ�����״̬
+extern uint8_t dropOffPortMark1;
+extern uint8_t dropOffPortMark2;
+
+extern uint8_t getRecycleClearDoorMark;			//Ӳ����ȡ��������״̬
+extern uint8_t recycleClearDoorMark;				//������״̬
+
+extern uint8_t smokeAlarmStatus;						//��������״̬
+
+extern uint8_t dropPortClosedStatus1;				//Ͷ�ſڹر�״̬
+extern uint8_t dropPortClosedStatus2;
+
+extern uint8_t gpsConnectSta;								//GPSģ��Ӳ������״̬
+extern uint8_t gpsStatus;										//GPS��λ״̬
+extern uint8_t gpsEW;												//���ȷ���0->E-��,W-����
+extern uint32_t gpsLon;											//���ȣ��ѷŴ�1000000����
+extern uint8_t  gpsNS;											//γ�ȷ���0->N-��,1->S-�ϣ�
+extern uint32_t gpsLat;											//γ�ȣ��ѷŴ�1000000����
+extern uint8_t getGpsStatus;								//ȡ��GPS��Ϣ
+
+extern uint8_t distance;										//�������
+extern uint8_t getDistance1;								//ȡ�õĵ�1·����
+extern uint8_t getDistance2;								
+extern uint8_t getDistance3;								
+extern uint8_t getDistance4;	
+extern uint8_t updateDistanceMark;			
+
+extern uint8_t fullMarkLeft;							//��Ͱװ����־
+extern uint8_t fullMarkRight;							//��Ͱװ����־
+
+extern uint8_t fullMark1;
+extern uint8_t fullMark2;
+extern uint8_t fullMark3;
+extern uint8_t fullMark4;
+
+extern uint16_t weight;											//��������
+extern uint16_t getWeight1;									//ȡ�õĵ�1·����
+extern uint16_t getWeight2;									
+extern uint16_t getWeight3;									
+extern uint16_t getWeight4;		
+
+extern uint16_t getWeightBefore1;						//ȡ�õĵ�1·����Ͱ������������ǰ��
+extern uint16_t getWeightAfter1;						
+extern uint16_t getWeightBefore2;						
+extern uint16_t getWeightAfter2;					
+extern uint16_t getWeightBefore3;						
+extern uint16_t getWeightAfter3;						
+extern uint16_t getWeightBefore4;						
+extern uint16_t getWeightAfter4;					
+
+extern uint16_t weightChangeBefore_1;				//�����仯ǰ������
+extern uint16_t weightChangeBefore_2;	
+
+//�쳣����Ͷ������
+extern uint16_t exceptionWeight1;						//��⵽���쳣����Ͷ������
+extern uint16_t exceptionWeight2;									
+extern uint16_t exceptionWeight3;									
+extern uint16_t exceptionWeight4;		
+
+extern uint16_t exceptionWeightBefore1;			//ȡ�õĵ�1·�쳣Ͷ������������ǰ��
+extern uint16_t exceptionWeightAfter1;			//ȡ�õĵ�1·�쳣Ͷ�����������׺�
+extern uint16_t exceptionWeightBefore2;						
+extern uint16_t exceptionWeightAfter2;							
+extern uint16_t exceptionWeightBefore3;						
+extern uint16_t exceptionWeightAfter3;							
+extern uint16_t exceptionWeightBefore4;					
+extern uint16_t exceptionWeightAfter4;						
+
+extern uint16_t smallBottleCount;						//С����ƿ����
+extern uint16_t bigBottleCount;							//������ƿ����
+extern uint16_t cansCount;									//��������������
+
+extern uint8_t getPutInType;								//ȡ�õ�Ͷ�����ͣ���ť��IC������ά�롢�����������룩
+extern uint8_t getDataLength;								//ȡ�õ�������Ϣ����
+extern uint8_t getDataBuf[256];							//ȡ�õ�������Ϣ����
+
+extern uint8_t sendPutInType;								//����Ͷ�����ͣ���ť��IC������ά�롢�����������룩
+extern uint8_t sendDataLength;							//����������Ϣ�ĳ���
+extern uint8_t sendDataBuf[256];							//����������Ϣ����
+
+extern uint8_t pcRequestOpenDoorMark;				//��λ�������Ͷ�ſ�
+extern uint8_t openDoorNumber;							//����򿪵�Ͷ�ڱ��
+
+extern uint8_t rspPCDoorNumber;							//Ӧ����λ��Ͷ�ڱ��	
+extern uint8_t rspPCWeightNumber;						//Ӧ����λ�����̱��
+extern uint8_t rspPCDistanceNumber;					//Ӧ����λ�������
+extern uint8_t rspPCTemperatureNumber;			//Ӧ����λ���¶ȱ��
+
+extern uint8_t pcRequestClooseDoorMark;			//��λ������ر�Ͷ�ſ�
+
+//�����û���Ϣ�ϴ�
+extern uint8_t collectorSendAuthType;				//����Ͷ�����ͣ���ť��IC������ά�롢�����������룩
+extern uint8_t collectorSendDataLength;			//����������Ϣ�ĳ���
+extern uint8_t collectorSendDataBuf[35];		//����������Ϣ����
+
+extern uint8_t get_IC_ID[16];								//���յ���IC����
+extern uint8_t send_IC_ID[16];								//��Ҫ���͵���̨��IC����
+extern uint8_t getCardNumberBit[32];				//���ŷ��������17λʮ��������
+
+
+//��̨����Ӧ����ر���
+extern uint8_t userInfoQueryStatus;					//�Ӻ�̨��ȡ�û���Ϣ����״̬
+extern uint8_t getUserInfoMark;							//ȡ���û���Ϣ��־
+extern uint8_t putInUploadSuccessMark;			//Ͷ���ϴ��ɹ���־
+extern uint8_t getSetDistanceParamMark;			//ȡ�ú�̨�����������
+extern uint8_t getDeviceWorkStatusMark;			//ȡ�ú�̨���õ��豸����״̬��־
+
+extern uint8_t 	deviceStatus;							//�����������豸״̬
+extern uint8_t 	isAuth;										//�Ƿ�ͨ����֤
+extern uint8_t 	rewardDisplayType;				//������ʾ��ʽ��������֣�
+extern uint32_t userID;										//�û�ID		
+extern uint32_t accountNum;								//�û��˺�
+extern uint8_t 	nickNameLength;						//�ǳ����ݳ���
+extern uint8_t 	nickName[64];							//�ǳ�����
+extern uint32_t capital;									//�ʽ�
+extern uint32_t capitalAfter;							//�ʽ�Ͷ�ź����
+extern uint8_t 	residue;									//�����
+extern uint8_t  businessNum[8];						//������ˮ��
+extern uint16_t receiveBusinessNum;				//��̨���صĽ�����ˮ��
+extern uint8_t  isOutput;									//�Ƿ���Գ���
+extern uint8_t  barcodeLength;						//��������ά�����ݳ���
+extern uint8_t  barcode[32];							//��������ά������
+
+//���������
+extern uint8_t getBoxOpenAckMark;						//ȡ�ú�̨���ش�������״̬��־
+extern uint8_t boxOpenAckStatus;						//��̨Ӧ��������Ŵ򿪱�־	
+
+//Ͷ�Ź��������õı���
+extern uint8_t putInProgress;								//Ͷ�Ž����б�־
+extern uint8_t isOpenDoor;
+extern uint8_t keyOpenDoorRequest;
+
+extern uint8_t isOpenDoorRequest_1;					//���յ����������ű�־
+extern uint8_t isOpenDoorRequest_2;
+extern uint8_t isOpenDoorRequest_3;
+extern uint8_t isOpenDoorRequest_4;
+extern uint8_t isOpenDoor_1;								//���յ����������ű�־
+extern uint8_t isOpenDoor_2;
+extern uint8_t isOpenDoor_3;
+extern uint8_t isOpenDoor_4;
+
+extern uint8_t isCloseDoorMark_1;						//������ű�־
+extern uint8_t isCloseDoorMark_2;
+extern uint8_t isCloseDoorMark_3;
+extern uint8_t isCloseDoorMark_4;
+
+extern uint8_t openDoorCtrlEndMark_1;				//�����ſ��ƽ�����־
+extern uint8_t openDoorCtrlEndMark_2;
+extern uint8_t openDoorCtrlEndMark_3;
+extern uint8_t openDoorCtrlEndMark_4;
+
+
+extern uint8_t putInEndMark;								//�豸��ת���ƽ�����־
+
+extern uint8_t delayCloseDoorStatus;				//���յ��ӳٹ���
+extern uint8_t delayCloseDoorStatus2;				//���յ��ӳٹ���
+
+extern uint8_t disablePutInMark;						//��ֹͶ����ɱ�־
+extern uint8_t putInOKMark;									//Ͷ����ɱ�־
+
+extern uint8_t getRemainingTimerStatus;			//ȡ�õ���ʱʱ��״̬
+extern uint8_t remainingTimer; 							//ʣ�����ʱ��
+
+extern uint8_t faceEntryFlag;							//����¼�������־
+
+extern uint8_t devChannel1FaultMark;			//���ϱ�־
+extern uint8_t devChannel2FaultMark;			//���ϱ�־
+extern uint8_t devChannel3FaultMark;			//���ϱ�־
+extern uint8_t devChannel4FaultMark;			//���ϱ�־
+extern uint8_t deviceFault;								//�豸����
+extern uint8_t faultLedFlashMark;					//����ʱ����˸��־
+extern uint8_t faultCode_1;								//������
+extern uint8_t faultCode_2;
+extern uint8_t faultCode_3;
+extern uint8_t faultCode_4;
+extern uint8_t limitKeyExceptionMark;				//��λ�����쳣��־
+extern uint8_t displayFaultCode;						//��ʾ�Ĺ�����
+
+extern uint8_t boxOpenRecordMark;					//���������ſ��ż�¼��־����־�Ƿ��Ѿ�������������ʱ��ά�뿪�ţ�
+extern uint8_t boxOpenMark;								//ȡ����ʱ��ά�뿪���������ű�־
+extern uint8_t boxOpenQRMark;							//ȡ����ʱ��ά�뿪���������ű�־
+
+extern uint8_t exitMark;									//�˳���־
+
+//�豸��ز���
+//��ǰʹ�õĲ�������
+//>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>
+extern uint8_t deviceType;								//�豸������
+extern uint8_t devChannelNumbers;					//�豸Ͷ�ſ�ͨ�������������Ͳ�����ʼ��������ֵ��
+extern uint8_t leftBarrelType;						//�豸��Ͱ����
+extern uint8_t rightBarrelType;						//�豸��Ͱ����
+
+extern uint8_t devChannel1Type;					//�豸ͨ������
+extern uint8_t devChannel2Type;
+extern uint8_t devChannel3Type;
+extern uint8_t devChannel4Type;
+
+extern uint32_t password;									//�豸��������
+extern uint32_t customerID;								//�ͻ��ţ����ڿ���˭���Դ����������ţ�
+
+extern uint8_t distance_L_DepthVal;				//������Ͱ���Ͱ����ȣ�����Ͱ�ĸ߶ȣ�
+extern uint8_t distance_L_MaxVal;					//������Ͱ������ֵ������װ��ߵ��ֵ��
+extern uint8_t distance_L_AlarmPercent;		//������Ͱ���װ�������ٷֱ�
+
+extern uint8_t distance_R_MaxVal;					//������Ͱ������ֵ������װ��ߵ��ֵ��
+extern uint8_t distance_R_DepthVal;				//������Ͱ���Ͱ����ȣ�����Ͱ�ĸ߶ȣ�
+extern uint8_t distance_R_AlarmPercent;		//������Ͱ���װ�������ٷֱ�
+
+
+extern uint8_t distanceParamAtStart;			//��ʼ����������������
+extern uint8_t PerCentSetVal;							//��ʼ�������İٷֱ�����ֵ
+
+extern uint8_t devChannel1DisDepthVal;				//�豸ͨ���������
+extern uint8_t devChannel1DisMaxVal;
+extern uint8_t devChannel1DisAlarmPercent;
+
+extern uint8_t devChannel2DisDepthVal;				//�豸ͨ���������
+extern uint8_t devChannel2DisMaxVal;
+extern uint8_t devChannel2DisAlarmPercent;
+
+extern uint8_t devChannel3DisDepthVal;				//�豸ͨ���������
+extern uint8_t devChannel3DisMaxVal;
+extern uint8_t devChannel3DisAlarmPercent;
+
+extern uint8_t devChannel4DisDepthVal;				//�豸ͨ���������
+extern uint8_t devChannel4DisMaxVal;
+extern uint8_t devChannel4DisAlarmPercent;
+
+extern uint8_t disableICCardFunStatus;		//����/ͣ�á����õ�IC�����ܿ��š�����״̬��1��ͣ�ù��ܣ��������ù��ܣ�
+extern uint8_t enableCleanQRCodeStatus;		//����/ͣ�á����˶�ά�뿪�š�����״̬��1�����ù��ܣ�����ͣ�ù��ܣ�
+
+extern uint8_t deviceIdLength;						//�豸��ų���
+extern uint8_t deviceIdBuf[33];						//�豸���
+
+extern uint8_t ipAddr0, ipAddr1, ipAddr2, ipAddr3;		//������IP��ַ
+extern uint16_t ipPort;
+
+//ȡ�õĴ��޸ĺ󱣴�Ĳ�����������flash��ȡ������ͨ����ά��ȡ�õĴ������ʹ�õĲ���������
+extern uint8_t setDeviceType;							//���õ��豸����
+extern uint8_t setDevChannelNumbers;			//����ʱȡ�õ�Ͷ�ſ�ͨ������
+extern uint8_t setDevChannel1Type;				//�����豸ͨ����������
+extern uint8_t setDevChannel2Type;
+extern uint8_t setDevChannel3Type;
+extern uint8_t setDevChannel4Type;
+
+extern uint32_t setPassword;							//Ҫ���õ��豸��������
+extern uint32_t setCustomerID;						//�ͻ��ţ����ڿ���˭���Դ����������ţ�
+
+extern uint8_t setDevChannel1DisDepthVal;		//����Ͱ����Ⱦ��루����Ͱ�ĸ߶ȣ�
+extern uint8_t setDevChannel1DisMaxVal;			//���ô�������װ�߶Ⱦ������ֵ������װ��ߵ��ֵ��
+extern uint8_t setDevChannel1DisAlarmPercent;//����������뱨���ٷֱ�
+
+extern uint8_t setDevChannel2DisDepthVal;
+extern uint8_t setDevChannel2DisMaxVal;
+extern uint8_t setDevChannel2DisAlarmPercent;
+
+extern uint8_t setDevChannel3DisDepthVal;
+extern uint8_t setDevChannel3DisMaxVal;
+extern uint8_t setDevChannel3DisAlarmPercent;
+
+extern uint8_t setDevChannel4DisDepthVal;
+extern uint8_t setDevChannel4DisMaxVal;
+extern uint8_t setDevChannel4DisAlarmPercent;
+
+extern uint8_t setDisableICCardFunStatus;		//��������/ͣ�á����õ�IC�����ܿ��š�����״̬��1��ͣ�ù��ܣ��������ù��ܣ�
+extern uint8_t setEnableCleanQRCodeStatus;	//��������/ͣ�á����˶�ά�뿪�š�����״̬��1�����ù��ܣ�����ͣ�ù��ܣ�
+
+extern uint8_t setDeviceIdLength;					//ȡ�õ��豸��ų���
+extern uint8_t setDeviceIdBuf[33];				//ȡ�õ��豸���
+
+extern uint8_t setIpAddr0, setIpAddr1, setIpAddr2, setIpAddr3;
+extern uint16_t setIpPort;
+
+//�û�����ȡ�õĲ�������
+extern uint8_t getDeviceType;							//ȡ�õ��豸����
+extern uint8_t getDevChannelNumbers;			//����ʱȡ�õ�Ͷ�ſ�ͨ������
+extern uint8_t getDevChannel1Type;				//ȡ�õ��豸ͨ����������
+extern uint8_t getDevChannel2Type;
+extern uint8_t getDevChannel3Type;
+extern uint8_t getDevChannel4Type;
+
+extern uint32_t getConfirmPassword;				//ȡ��ȷ������
+extern uint32_t getPassword;							//ȡ�õ��豸��������
+extern uint32_t getCustomerID;						//ȡ�õĿͻ���
+
+extern uint8_t getDevChannel1DisDepthVal;		//����Ͱ����Ⱦ��루����Ͱ�ĸ߶ȣ�
+extern uint8_t getDevChannel1DisMaxVal;			//���ô�������װ�߶Ⱦ������ֵ������װ��ߵ��ֵ��
+extern uint8_t getDevChannel1DisAlarmPercent;//����������뱨���ٷֱ�
+
+extern uint8_t getDevChannel2DisDepthVal;
+extern uint8_t getDevChannel2DisMaxVal;
+extern uint8_t getDevChannel2DisAlarmPercent;
+
+extern uint8_t getDevChannel3DisDepthVal;
+extern uint8_t getDevChannel3DisMaxVal;
+extern uint8_t getDevChannel3DisAlarmPercent;
+
+extern uint8_t getDevChannel4DisDepthVal;
+extern uint8_t getDevChannel4DisMaxVal;
+extern uint8_t getDevChannel4DisAlarmPercent;
+
+extern uint8_t getDisableICCardFunStatus;	//ȡ������/ͣ�á����õ�IC�����ܿ��š�����״̬��1��ͣ�ù��ܣ��������ù��ܣ�
+extern uint8_t getEnableCleanQRCodeStatus;//ȡ������/ͣ�á����˶�ά�뿪�š�����״̬��1�����ù��ܣ�����ͣ�ù��ܣ�
+
+extern uint8_t getDeviceIdLength;					//ȡ�õ��豸��ų���
+extern uint8_t getDeviceIdBuf[33];				//ȡ�õ��豸���
+
+extern uint8_t getIpAddr0, getIpAddr1, getIpAddr2, getIpAddr3;
+extern uint16_t getIpPort;
+
+extern uint8_t getScaleNum;								//ȡ��У׼���̵ı��
+
+//��ȡ����ز�����־
+extern uint8_t setParamSaveMark;					//���ò�����Ҫ���б����־
+extern uint8_t setParamChangeMark;				//���ò����б仯��־
+
+extern uint8_t getConfirmPasswordMark;		//ȡ�ô�ȷ�������־
+extern uint8_t getPasswordMark;						//ȡ��Ҫ���õ������־
+extern uint8_t getForceChangeMark;				//ȡ��ǿ���޸������־
+extern uint8_t getDeviceTypeMark;					//ȡ�������豸���ͱ�־
+extern uint8_t getCustomerIDMark;					//ȡ�����ÿͻ��ű�־
+
+extern uint8_t getDisableICCardFunMark;		//ȡ������/ͣ�á����õ�IC�����ܿ��š����ܱ�־
+extern uint8_t getEnableCleanQRCodeMark;	//ȡ������/ͣ�á����˶�ά�뿪�š��������ñ�־
+
+extern uint8_t getOverflowSetMark;				//ȡ���������������־
+
+extern uint8_t getScaleCalibrationMark;		//ȡ�ó���У׼��־
+extern uint8_t getBoxOpenMark;						//ȡ����ʱ��ά�뿪���������ű�־
+extern uint8_t getDeviceParamResetMark;		//ȡ�ûָ���������
+//<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<
+
+extern uint8_t deviceWorkStatus;					//�豸����״̬��������ͣ�ã�
+extern uint8_t deviceWorkStatusPre;				//�豸����״̬�л�ǰ��״̬
+extern uint8_t getDeviceWorkStatusVal;		//ȡ�ú�̨���õĹ���״ֵ̬
+
+extern uint8_t getMcu2SensorDataMark;			//ȡ��MCU2���͵Ĵ��������ݱ�־
+
+extern uint16_t netStatus;								//����״̬
+extern uint16_t devRunnigStatus;					//�豸����״̬
+		 				    
+#endif
diff --git a/STM32_4路称重_Git提交精简工程/src/USER/date_time.c b/STM32_4路称重_Git提交精简工程/src/USER/date_time.c
new file mode 100755
index 0000000..635b1a1
--- /dev/null
+++ b/STM32_4路称重_Git提交精简工程/src/USER/date_time.c
@@ -0,0 +1,102 @@
+/*************************** (C) COPYRIGHT 2017 CXHY ****************************
+ * �ļ���  date_time.c
+ * ��  ��  ��ʱ��ʱ����س���
+ * ��  ��  ��V1.0
+ * ��  ��  ��XuZhongPing
+ * ��  ��  ��2021/02/05
+*********************************************************************************/
+#include "date_time.h"
+#include "timer.h"
+
+my_time_t GMT_Time;															//��������ʱ��
+my_time_t beijing_Time;													//����ʱ��
+
+uint8_t systemTime[20];													//ϵͳʱ���ʽΪYYYY-MM-DD hh:mm:ss
+uint8_t getDateTimeMark = 0;										//ȡ��ʱ��ʱ���־
+
+time_t timestamp_s = 0;													//����(s)Ϊ��λ��ʱ���
+
+struct tm* nowTime;
+
+/*
+***********************************************************************
+*	�� �� ��: UTC_To_Beijing
+*	����˵��: ��������ʱ��ת����ʱ��
+*	��    �Σ�time:ת��ǰ��GMTʱ��
+*	�� �� ֵ: �ޣ�Ӱ��ȫ�ֱ���beijing_Time��
+***********************************************************************
+*/
+void GMT_To_Beijing(my_time_t* time)
+{
+	struct tm stm;
+	struct tm dataTime;
+	time_t bj_timestamp_s;
+	
+	//GMT����ʱ��תʱ���
+	stm.tm_year = GMT_Time.year-1900;  
+	stm.tm_mon = GMT_Time.month-1;
+	stm.tm_mday = GMT_Time.day;
+	stm.tm_hour = GMT_Time.hour;  
+	stm.tm_min = GMT_Time.minute;
+	stm.tm_sec = GMT_Time.second;
+	
+	timestamp_s = mktime(&stm); 
+	
+	//UTCʱ���ת����ʱ���(����ʱ���UTCʱ����8Сʱ��28800��)
+	bj_timestamp_s = timestamp_s + 28800;
+	nowTime = localtime(&bj_timestamp_s);
+	
+	//�ַ�����ʽ
+	strftime((char*)systemTime, 20, "%Y-%m-%d %H:%M:%S", nowTime);
+	printf("\r\n����ʱ�䣺%s\r\n", (char*)systemTime);
+}
+
+/*
+***********************************************************************
+*	�� �� ��: TimerTask
+*	����˵��: ʱ������
+*	��    �Σ���
+*	�� �� ֵ: ��
+***********************************************************************
+*/
+void TimerTask(void)
+{
+	char buffer[128];
+	static timer Timer_1S;
+	struct tm dataTime;
+	time_t bj_timestamp_s;
+	
+	static uint8_t timer_ok = 0;
+	if(timer_ok == 0)
+	{
+		timer_ok = 1;
+
+		timer_set(&Timer_1S, CLOCK_SECOND*1);
+	}
+	
+	
+	if(timer_expired(&Timer_1S))
+	{
+		timer_restart(&Timer_1S);
+		
+		if(getDateTimeMark == 0)
+		{
+			printf("\r\nδ�������ʱ��!\r\n");
+		}
+		
+		timestamp_s++;
+		
+		bj_timestamp_s = timestamp_s + 28800;
+		nowTime = localtime(&bj_timestamp_s);
+		
+		strftime((char*)systemTime, 20, "%Y-%m-%d %H:%M:%S", nowTime);
+// 		strftime(buffer, sizeof(buffer), "Now time: %Y-%m-%d %H:%M:%S", nowTime);
+// 		printf("\r\n%s\r\n", buffer);
+
+// 		printf("\r\ntimestamp:%d\r\n", timestamp_s);
+// 		printf("\r\ntimestamp_ms_h:%04X\r\n", timestamp_ms_H32);
+// 		printf("\r\ntimestamp_ms_l:%08X\r\n", timestamp_ms_L32);
+	}
+}
+
+/******************** (C) COPYRIGHT 2017 CXHY *****END OF FILE*******************/
diff --git a/STM32_4路称重_Git提交精简工程/src/USER/date_time.h b/STM32_4路称重_Git提交精简工程/src/USER/date_time.h
new file mode 100755
index 0000000..b771b75
--- /dev/null
+++ b/STM32_4路称重_Git提交精简工程/src/USER/date_time.h
@@ -0,0 +1,42 @@
+/*************************** (C) COPYRIGHT 2017 CXHY ****************************
+ * �ļ���  ��date_time.h
+ * ��  ��  ������ʱ�����ͷ�ļ� 
+ * ��  ��  ��V1.0
+ * ��  ��  ��XuZhongPing
+ * ��  ��  ��2021/02/05
+*********************************************************************************/
+#ifndef __DATE_TIME_h
+#define __DATE_TIME_h
+
+#include "stdint.h" 
+#include "stdio.h" 
+#include "string.h"
+#include "time.h"
+
+typedef struct
+{
+	uint16_t year;
+	uint8_t month;
+	uint8_t day;
+	uint8_t hour;
+	uint8_t minute;
+	uint8_t second;
+}my_time_t;
+
+extern my_time_t GMT_Time;												//��������ʱ��
+extern my_time_t beijing_Time;										//����ʱ��
+
+extern uint8_t systemTime[20];										//ϵͳʱ���ʽΪYYYY-MM-DD hh:mm:ss
+extern uint8_t getDateTimeMark;										//ȡ��ʱ��ʱ���־
+
+extern time_t timestamp_s;												//����(s)Ϊ��λ��ʱ���
+
+extern struct tm* nowTime;
+
+void GMT_To_Beijing(my_time_t* time);
+void GetPutInTime(void);
+void TimerTask(void);
+
+#endif
+/******************** (C) COPYRIGHT 2017 CXHY *****END OF FILE*******************/
+
diff --git a/STM32_4路称重_Git提交精简工程/src/USER/main.c b/STM32_4路称重_Git提交精简工程/src/USER/main.c
new file mode 100755
index 0000000..1cc3056
--- /dev/null
+++ b/STM32_4路称重_Git提交精简工程/src/USER/main.c
@@ -0,0 +1,259 @@
+/*************************** (C) COPYRIGHT 2017 YNHB ****************************
+ * �ļ���  ��main.c
+ * ��  ��  ��������    
+ * ��  ��  ��V1.0
+ * ��  ��  ��XuZhongPing
+ * ��  ��  ��2017/03/05 
+*********************************************************************************/
+#include "stm32f10x.h"
+#include "wdg.h"
+#include "delay.h"
+#include "usart1.h"
+#include "usart2.h"
+#include "usart3.h"
+#include "usart4.h"
+#include "usart5.h"
+#include "timer.h"
+
+#include "gsm_gprs.h"
+#include "data_typedef.h"
+#include "message.h"
+#include "device.h" 
+#include "lcd.h"
+#include "display.h"
+#include "tcp_protocol.h"
+#include "user_app.h"
+
+#include "bsp_WM8978.h"
+#include "sound.h"
+#include "spi.h"
+#include "flash.h" 
+
+#include "pc_protocol.h"
+#include "IR_Distancer.h"
+#include "deviceSet.h"
+
+#include "m_s_comm.h"
+#include "netwer_appcall.h"
+
+void NVIC_Configuration(void);
+void RegularUploadTask(void);
+
+int main(void)
+{
+	static timer waitingTimer_1s;
+	timer_set(&waitingTimer_1s, CLOCK_SECOND*120);
+	
+	delay_init();	    	 							//��ʱ������ʼ��	  
+	NVIC_Configuration(); 	 					//����NVIC�жϷ���
+	
+	USART1_Init(9600);	 							//���ڳ�ʼ��Ϊ115200������RFID_IC������ά�����ݶ�ȡ��
+	USART2_Init(38400);								//����MCUͨ�Žӿ�
+	USART4_Init(9600);								//���ͨ�Ŵ���
+	USART5_Init(115200);							//������Ϣ�������
+	
+	TIM2_Int_Init(1000, 7200-1);			//10Khz�ļ���Ƶ�ʣ�������1000Ϊ100ms ����ÿ������Ϊ0.1ms��
+	TIM3_Int_Init(100, 7200-1);				//10Khz�ļ���Ƶ�ʣ�ÿ������Ϊ0.1ms������ʱ10ms������λ���غͰ�ťɨ��
+	TIM4_Int_Init(5000, 7200-1);			//10Khz�ļ���Ƶ�ʣ�ÿ������Ϊ0.1ms����������5000Ϊ500ms
+	TIM5_Int_Init(100, 7200-1);				//ͨ�ö�ʱ��5�����ڶ�ά���ͷ���ݽ�������ж�
+	
+	printf("\r\n***************System Running***************\r\n");
+	DeviceInit();											//Ӳ���豸��ʼ��
+	DeviceTest();											//Ӳ������
+	
+	printf("\r\n����IC��ģ����� -->\r\n");
+	SetRFID_Param();									//����IC��ģ�����
+	
+	Audio_Play(1);
+	
+	IWDG_Init(5, 625);    						//���Ź���ʼ������Ƶ��Ϊ128,����ֵΪ625,���ʱ��Ϊ2s	
+	PC_ProCommandSend(0x90);					//����λ���������ڿ���
+	
+	while(1)
+	{	
+		LED_Task();											//LED��ָʾ����
+		BeepTask();											//��������������
+// 		DataUploadPollingTask();
+		GSM_GPRS_Task();								//GSM_GPRSͨѶ����
+		DeviceScanning();								//�豸ɨ���⣨ɨ��ˢIC���Ͷ�ά�룩
+		UserIdentificationTask();				//�û�����ʶ��
+		PutInOpenDoorTask();						//�û�����Ͷ������		
+		OpenDoorRequestTask();					//�����������񣨼����Ƿ��п��Ű������£�
+		DeviceControlTask();						//�豸��������ת��������
+		OpenDoorControlTask();					//Ͷ�ڿ����ſ�������
+		GetTemperatureTask();						//ȡ���¶�����
+		DispalyTask();									//��ʾ����
+		PC_ProDecodeTask();							//��λ��ͨѶ����
+		M_S_DataDecodeTask();
+		Audio_PlayTask();								//�����������
+		BoxOpenTask();									//���������ſ�������
+		CollectorLockCtrlTask();				//������������������
+		RecycleClearDoorCheckTask();		//�����ż������
+		
+//		DistanceDataUpdata();
+		if(putInProgress == 0)					//Ͷ�Ź����в����в��Ϳ��Ű������
+		{
+			OverflowDetectionTask();			//����������
+			DeviceEnableTask();						//�豸����/���ÿ�������
+			KeysSendTask();								//��������ת������
+		}
+		
+		TimerTask();										//ʱ������
+		RegularUploadTask();						//��ʱ�ϴ�����
+		ParamSetTask();									//�豸��ز�����������
+		TimingSprayTask();							//��ʱ������������
+		TimingUVTask();									//��ʱ��������������
+		FillLightTask();								//����ƿ�������
+		CoolingFanCtrlTask();						//ɢ�ȷ��ȿ�������
+		SprayCtrlTask();								//������ܿ�������
+// 		SprayDisinfectingTask();				//������������
+// 		DisinfectingTask();							//UV������������
+// 		SystemExceptionTask();					//ϵͳ�쳣��������
+		IWDG_FeedTask();								//���Ź�ι������
+		
+		if(timer_expired(&waitingTimer_1s))
+		{
+			timer_restart(&waitingTimer_1s);
+			
+// 			gpsStatus = 1;
+// 			gpsLon = 114223476;
+// 			gpsLat = 22687142;
+		}
+		
+		//�����յ��������·�������ʱ��ʾ
+		if(TCP_recreceiveStatus == 1)
+		{
+			TCP_recreceiveStatus = 0;
+			printf("\r\nTCP <-- %d \r\n", recreceiveOrderCode);
+		}
+		
+		if(getMcu2SensorDataMark == 1)
+		{
+			getMcu2SensorDataMark = 0;
+			
+// 			printf("\r\nSensor:"
+// 							"\r\nW1 = %2.2f Kg, W2 = %2.2f Kg, W3 = %2.2f Kg, W4 = %2.2f Kg"\
+// 							"\r\nD1 = %3.1f cm, D2 = %3.1f cm, D3 = %3.1f cm, D4 = %3.1f cm"\
+// 							"\r\nT = %2.1f ��, SW = %d, T2 = %2.1f ��, SW1 = %d, SW2 = %d\r\n", 
+// 				(float)(weight1)/100, 
+// 				(float)(weight2)/100, 
+// 				(float)(weight3)/100, 
+// 				(float)(weight4)/100,
+// 				(float)getDistance1,
+// 				(float)getDistance2,
+// 				(float)getDistance3,
+// 				(float)getDistance4,
+// 				(float)temperature,
+// 				optoSwitchStatus,
+// 				(float)temperature_A,
+// 				switchKey1Status,
+// 				switchKey2Status
+// 				);
+		}
+		
+		if(getGpsStatus == 1)
+		{
+			getGpsStatus = 0;
+			
+//			printf("GPS����״̬��%d\r\n", gpsConnectSta);
+//			printf("��λ״̬��%d\r\n", gpsStatus);
+//			printf("���ȣ�%.6f %d\r\n", (double)gpsLon/1000000, gpsEW);
+//			printf("γ�ȣ�%.6f %d\r\n", (double)gpsLat/1000000, gpsNS);
+		}
+	}
+}
+
+
+/*
+***********************************************************************
+*	�� �� ��: RegularUploadTask
+*	����˵��: ��ʱ�ϴ�����
+*	��    �Σ���        
+*	�� �� ֵ: ��
+***********************************************************************
+*/
+void RegularUploadTask(void)
+{
+	static timer sendDevStaTimer;			//�ϴ��豸����״̬��Ϣ���¶ȡ��źš���ࣩ
+	static timer heartbeatTimer;
+	static timer gpsSendTimer;
+	
+	static uint8_t initDataSendFalg = 0;			//������ĳ�ʼ���ݷ��ͱ�־
+	static uint8_t gpsInitDataSendFalg = 0;
+	
+	static uint8_t timer_ok = 0;
+	if(timer_ok == 0)
+	{
+		timer_ok = 1;
+		
+		timer_set(&sendDevStaTimer, CLOCK_SECOND*30);		//�豸״̬�ϴ����ʱ��
+		timer_set(&heartbeatTimer, CLOCK_SECOND*120);			//�����ϴ�ʱ��
+		timer_set(&gpsSendTimer, CLOCK_SECOND*60);
+	}
+	
+	if(gsm_msg.Running == 1)
+	{
+		if(initDataSendFalg == 0)				//�״ο������ͳ�ʼ����
+		{
+			initDataSendFalg = 1;
+			
+			PC_ProCommandSend(0x31);
+		}
+	}
+	
+	if(gpsInitDataSendFalg == 0)		//�״ζ�λ��Ϣ����
+	{
+		if((gpsConnectSta == 1) && (gpsStatus == 1))
+		{
+			gpsInitDataSendFalg = 1;
+			
+			printf("\r\n�״�GPS��Ϣ���ͣ�\r\n");
+			PC_ProCommandSend(0x67);
+		}
+	}
+	
+	//�����ϴ�
+	if(timer_expired(&heartbeatTimer))
+	{
+		timer_restart(&heartbeatTimer);
+		
+		if(gsm_msg.Running == 1)
+		{
+			PC_ProCommandSend(0x31);
+		}
+	}
+	
+	//�豸����״̬��Ϣ�ϴ�
+	if(timer_expired(&sendDevStaTimer))
+	{
+		timer_restart(&sendDevStaTimer);
+		
+		if(putInProgress == 0)
+		{
+			PC_ProCommandSend(0x62);													//����λ�������豸״̬��Ϣ
+		}
+	}
+	
+	//�豸GPS��λ��Ϣ�ϴ�
+	if(timer_expired(&gpsSendTimer))
+	{
+		timer_restart(&gpsSendTimer);
+		
+		PC_ProCommandSend(0x67);
+	}
+}
+
+/*
+***********************************************************************
+*	�� �� ��: RegularUploadTask
+*	����˵��: ��ʱ�ϴ�����
+*	��    �Σ���        
+*	�� �� ֵ: ��
+***********************************************************************
+*/
+void NVIC_Configuration(void)
+{
+	NVIC_PriorityGroupConfig(NVIC_PriorityGroup_2);		//����NVIC�жϷ���2:2λ��ռ���ȼ���2λ��Ӧ���ȼ�
+}
+
+/******************** (C) COPYRIGHT 2017 YNHB *****END OF FILE*******************/ 
diff --git a/STM32_4路称重_Git提交精简工程/src/USER/message.c b/STM32_4路称重_Git提交精简工程/src/USER/message.c
new file mode 100755
index 0000000..592a1ec
--- /dev/null
+++ b/STM32_4路称重_Git提交精简工程/src/USER/message.c
@@ -0,0 +1,85 @@
+#include "message.h"
+
+MESSAGE_FIFO MsgFifos[MSG_FIFO_COUNT];		//����һ����Ϣ����
+MESSAGE sendMsg;													
+MESSAGE pcCmdMsg;													//������λ����Ϣ
+
+/*
+***********************************************************************
+*	�� �� ��: MessageInit
+*	����˵��: ��Ϣ������ʼ��
+*	��    �Σ���
+*	�� �� ֵ: ��
+***********************************************************************
+*/
+void MessageInit(void)					
+{
+	memset(&MsgFifos, 0, sizeof(MsgFifos));
+}
+
+/*
+***********************************************************************
+*	�� �� ��: MessageSend
+*	����˵��: ������Ϣ
+*	��    �Σ�
+* 					MsgFifoIndex������Ŀ��
+*						event��Ҫ���͵���Ϣ
+*	�� �� ֵ: _ErrStatus���ɹ�����_OK,���ɹ�����_ERROR
+***********************************************************************
+*/
+_ErrStatus MessageSend(uint8_t MsgFifoIndex, MESSAGE msg)
+{	
+	MESSAGE_FIFO *pMsgFifo = &MsgFifos[MsgFifoIndex]; 
+
+	if(pMsgFifo->Count >= MAX_FIFO_DEPTH)
+	{
+		return _ERROR;
+	}	
+	pMsgFifo->Buf[(pMsgFifo->IndexHead + (pMsgFifo->Count++)) % MAX_FIFO_DEPTH] = msg;
+	return OK;
+}
+
+
+/*
+***********************************************************************
+*	�� �� ��: MessageGet
+*	����˵��: ��ȡ��Ϣ
+*	��    �Σ�MsgFifoIndex������Ŀ�꣬�Ӵ�ģ�����
+*	�� �� ֵ: fifoΪ���򷵻�NULL�����򷵻ض�Ӧ��Ϣ��ָ��
+***********************************************************************
+*/
+MESSAGE *MessageGet(uint8_t MsgFifoIndex)							
+{
+	MESSAGE *pMsg = NULL;
+	MESSAGE_FIFO* pMsgFifo = &MsgFifos[MsgFifoIndex];
+
+	if(pMsgFifo->Count)
+	{
+		pMsg = &(pMsgFifo->Buf[pMsgFifo->IndexHead]);
+		pMsgFifo->IndexHead = (pMsgFifo->IndexHead + 1) % MAX_FIFO_DEPTH;
+		pMsgFifo->Count--;
+	}				
+	return pMsg;
+}
+
+/*
+***********************************************************************
+*	�� �� ��: GetMessageStatus
+*	����˵��: ��ȡ��Ϣ����ʣ��ռ�
+*	��    �Σ�MsgFifoIndex������Ŀ�꣬�Ӵ�ģ�����
+*	�� �� ֵ: ���ص�ǰ���л�ʣ��ռ�
+***********************************************************************
+*/
+uint8_t GetMessageRemainingSpace(uint8_t MsgFifoIndex)
+{
+	MESSAGE_FIFO* pMsgFifo = &MsgFifos[MsgFifoIndex];
+
+	if(pMsgFifo->Count <= MAX_FIFO_DEPTH)
+	{
+		return MAX_FIFO_DEPTH - pMsgFifo->Count;
+	}else{		
+		return 0;
+	}
+}
+
+/******************** (C) COPYRIGHT 2017 YNHB *****END OF FILE*******************/
diff --git a/STM32_4路称重_Git提交精简工程/src/USER/message.h b/STM32_4路称重_Git提交精简工程/src/USER/message.h
new file mode 100755
index 0000000..4d6fa7d
--- /dev/null
+++ b/STM32_4路称重_Git提交精简工程/src/USER/message.h
@@ -0,0 +1,60 @@
+#ifndef _MESSAGE_H
+#define _MESSAGE_H
+
+#include "stdio.h"
+#include "stdint.h"
+#include "string.h"
+
+#define	MAX_FIFO_DEPTH							20			//��Ϣ����������	
+
+typedef enum
+{
+	FALSE = 0,
+	TRUE = !FALSE
+}_bool;
+
+typedef enum {
+	_ERROR = 0, 
+	OK = !_ERROR
+}_ErrStatus;
+
+//��Ϣ�ṹ��
+typedef struct _ControlMessage
+{
+	uint16_t         		    msgType;					//Э������	
+	uint8_t 								msgData;					//��Ϣ������
+	uint8_t 								msgQos;						//��Ϣ�Ĵ���ȼ�
+	uint16_t								msgLen;						//������Ϣ����ָ��ָ������ݳ���
+	uint8_t* 								msgDataPrt;				//������Ϣ����ָ��
+}	MESSAGE;
+
+
+//��ϢFIFO�ṹ��
+typedef struct _MESSAGE_FIFO
+{
+ 	uint8_t									IndexHead;
+	uint8_t									Count;
+	MESSAGE 								Buf[MAX_FIFO_DEPTH];			//��Ϣ����
+
+} MESSAGE_FIFO;
+
+//��Ϣ���Ͷ���
+typedef enum _MSG_FIFO_INDEX
+{
+	MSG_FIFO_PROTOCOL = 0,										//��̨ͨѶЭ����Ϣ
+	MSG_FIFO_RS485_PROTOCOL,									//RS485ͨѶЭ����Ϣ
+	MSG_FIFO_PC_CMD,													//��λ���ӿ�ͨѶЭ����Ϣ
+	MSG_FIFO_COUNT														//��Ϣfifo�洢������
+
+} MSG_FIFO_INDEX;
+
+extern MESSAGE sendMsg;
+extern MESSAGE pcCmdMsg;				//��λ���ӿ���Ϣ
+
+void MessageInit(void);
+_ErrStatus MessageSend(uint8_t MsgFifoIndex, MESSAGE event);
+MESSAGE *MessageGet(uint8_t MsgFifoIndex);
+uint8_t GetMessageRemainingSpace(uint8_t MsgFifoIndex);
+
+#endif
+
diff --git a/STM32_4路称重_Git提交精简工程/src/USER/my_math.c b/STM32_4路称重_Git提交精简工程/src/USER/my_math.c
new file mode 100755
index 0000000..32332f8
--- /dev/null
+++ b/STM32_4路称重_Git提交精简工程/src/USER/my_math.c
@@ -0,0 +1,241 @@
+/*************************** (C) COPYRIGHT 2017 CXHY ****************************
+ * �ļ���  my_math.c
+ * ��  ��  ��������㴦������   
+ * ��  ��  ��V1.0
+ * ��  ��  ��XuZhongPing
+ * ��  ��  ��2017/04/26 
+*********************************************************************************/
+#include "my_math.h"
+#include "string.h" 
+
+/*
+***********************************************************************
+*	�� �� ��: Pow
+*	����˵��: ��ƽ��
+*	��    �Σ�m -> ����
+*    				n -> ָ��          
+*	�� �� ֵ: �����Ľ��
+***********************************************************************
+*/
+uint64_t Pow(uint8_t m, uint8_t n)
+{
+	uint64_t result = 1;	 
+	while(n--)result *= m;    
+	return result;
+}	
+
+/*
+***********************************************************************
+*	�� �� ��: sort_8
+*	����˵��: ����		
+*	��    �Σ�
+*       		x[]:��Ҫ����������
+*						n:����ĳ���
+*	�� �� ֵ: ��
+***********************************************************************
+*/
+void sort_8(uint8_t x[], uint8_t n)
+{
+	uint8_t i,j,k,t;             
+	for (i=0; i<n-1; i++)
+	{
+		k = i;
+		for(j=i+1; j<n; j++)
+		{
+			if(x[j] > x[k]) k = j;
+		}
+		if(k != i)
+		{
+			t = x[i];
+			x[i] = x[k];
+			x[k] = t;
+		}
+	}
+}
+
+/*
+***********************************************************************
+*	�� �� ��: sort_16
+*	����˵��: ����		
+*	��    �Σ�
+*       		x[]:��Ҫ����������
+*						n:����ĳ���
+*	�� �� ֵ: ��
+***********************************************************************
+*/
+void sort_16(uint16_t x[], uint8_t n)
+{
+	uint16_t i,j,k,t;             
+	for (i=0; i<n-1; i++)
+	{
+		k = i;
+		for(j=i+1; j<n; j++)
+		{
+			if(x[j] > x[k]) k = j;
+		}
+		if(k != i)
+		{
+			t = x[i];
+			x[i] = x[k];
+			x[k] = t;
+		}
+	}
+}
+
+/*
+***********************************************************************
+*	�� �� ��: sort_16
+*	����˵��: ����		
+*	��    �Σ�
+*       		x[]:��Ҫ����������
+*						n:����ĳ���
+*	�� �� ֵ: ��
+***********************************************************************
+*/
+void sort_32(uint32_t x[], uint16_t n)
+{
+	uint16_t i,j,k; 
+	uint32_t t;
+	for (i=0; i<n-1; i++)
+	{
+		k = i;
+		for(j=i+1; j<n; j++)
+		{
+			if(x[j] > x[k]) k = j;
+		}
+		if(k != i)
+		{
+			t = x[i];
+			x[i] = x[k];
+			x[k] = t;
+		}
+	}
+}
+
+/*
+***********************************************************************
+*	�� �� ��: uint average(uint *p,uchar n)
+*	����˵��: ȥ��������Сֵ����ƽ����
+*	��    �Σ�
+*       		x[]:��Ҫ����������
+*						n:����ĳ���
+*						discardVal:����ֵ
+*	�� �� ֵ: ������Ľ��
+***********************************************************************
+*/
+uint8_t average_8(uint8_t x[],uint8_t n, uint8_t discardVal)
+{
+	uint8_t i;
+	uint8_t aver = 0;
+	uint32_t sum = 0;
+	
+	for(i = discardVal; i < n-discardVal; i++)
+	{
+		sum = sum+x[i];
+	}
+	aver = sum/(n - discardVal*2);  
+	return aver;
+}
+
+/*
+***********************************************************************
+*	�� �� ��: average_16
+*	����˵��: ȥ��������Сֵ����ƽ����
+*	��    �Σ�
+*       		x[]:��Ҫ����������
+*						n:����ĳ���
+*						discardVal:����ֵ
+*	�� �� ֵ: ������Ľ��
+***********************************************************************
+*/
+uint16_t average_16(uint16_t x[], uint8_t n, uint8_t discardVal)
+{
+	uint8_t i;
+	uint16_t aver = 0;
+	uint32_t sum = 0;
+	for(i = discardVal; i < n-discardVal; i++)
+	{
+		sum = sum+x[i];
+	}
+	aver = sum/(n - discardVal*2);  
+	return aver;
+}
+
+/*
+***********************************************************************
+*	�� �� ��: average_16
+*	����˵��: ȥ��������Сֵ����ƽ����
+*	��    �Σ�
+*       		x[]:��Ҫ����������
+*						n:����ĳ���
+*						discardVal:����ֵ
+*	�� �� ֵ: ������Ľ��
+***********************************************************************
+*/
+uint32_t average_32(uint32_t x[], uint16_t n, uint16_t discardVal)
+{
+	uint16_t i;
+	double aver = 0;
+	float temp0;
+	uint32_t retData = 0;
+	uint32_t sum = 0;
+	uint8_t temp;
+	
+	for(i = discardVal; i < n-discardVal; i++)
+	{
+		sum = sum+x[i];
+	}
+	aver = (double)sum/(n - discardVal*2);  
+	
+	temp0 = (float)aver*10; 
+// 	printf(" %3.1f,  ", aver);
+	temp = (uint32_t)temp0%10;
+	if(temp >= 5)
+	{
+		aver += 1;
+	}
+
+// 	printf(" %d\r\n", (uint16_t)aver);
+	retData = aver;
+	
+	return aver;
+}
+
+/*
+***********************************************************************
+*	�� �� ��: DifferenceCompare
+*	����˵��: �Ƚ��ϴ������뱾�����ݵĲ�ֵ�Ƿ�����趨ֵ		
+*	��    �Σ�newData:��ֵ
+*						oleData:��ֵ
+*	�� �� ֵ:   1�����趨ֵ��0���趨ֵ��
+***********************************************************************
+*/
+uint8_t DifferenceCompare(uint32_t newData, uint32_t oleData, uint16_t LimitValue)
+{
+	uint16_t difference = 0;
+	
+	if(newData > oleData)
+	{
+		difference = newData - oleData;										
+		if(difference > LimitValue)								//����ֵ�����趨ƫ��ֵʱ����1
+		{
+			return 1;
+		}else
+		{
+			return 0;
+		}
+	}else if(newData < oleData){
+		difference = oleData - newData;										
+		if(difference > LimitValue)								//����ֵ�����趨ƫ��ֵʱ����1
+		{
+			return 1;
+		}else
+		{
+			return 0;
+		}
+	}else{
+		return 0;
+	}
+}
+
+/******************** (C) COPYRIGHT 2017 CXHY *****END OF FILE*******************/
diff --git a/STM32_4路称重_Git提交精简工程/src/USER/my_math.h b/STM32_4路称重_Git提交精简工程/src/USER/my_math.h
new file mode 100755
index 0000000..faaba00
--- /dev/null
+++ b/STM32_4路称重_Git提交精简工程/src/USER/my_math.h
@@ -0,0 +1,26 @@
+/*************************** (C) COPYRIGHT 2017 CXHY ****************************
+ * �ļ���  ��mathematics.h
+ * ��  ��  ���˲���������ͷ�ļ� 
+ * ��  ��  ��V1.0
+ * ��  ��  ��XuZhongPing
+ * ��  ��  ��2017/04/26 
+*********************************************************************************/
+#ifndef __MATHEMATICS_h
+#define __MATHEMATICS_h
+#include "stdint.h" 
+#include "string.h" 
+#include "stdlib.h"  
+#include "stdio.h" 
+
+uint64_t Pow(uint8_t m, uint8_t n);
+void sort_8(uint8_t x[], uint8_t n);
+void sort_16(uint16_t x[], uint8_t n);
+void sort_32(uint32_t x[], uint16_t n);
+uint8_t average_8(uint8_t x[],uint8_t n, uint8_t discardVal);
+uint16_t average_16(uint16_t x[], uint8_t n, uint8_t discardVal);
+uint32_t average_32(uint32_t x[], uint16_t n, uint16_t discardVal);
+uint8_t DifferenceCompare(uint32_t newData, uint32_t oleData, uint16_t LimitValue);
+
+#endif
+/******************** (C) COPYRIGHT 2017 CXHY *****END OF FILE*******************/
+
diff --git a/STM32_4路称重_Git提交精简工程/src/USER/over_flow.c b/STM32_4路称重_Git提交精简工程/src/USER/over_flow.c
new file mode 100755
index 0000000..e5a25c2
--- /dev/null
+++ b/STM32_4路称重_Git提交精简工程/src/USER/over_flow.c
@@ -0,0 +1,739 @@
+/*************************** (C) COPYRIGHT 2017 Ping ****************************
+ * �ļ���  ��user_app.c
+ * ��  ��  ���û�Ӧ�ó���
+ * ��  ��  ��V1.0
+ * ��  ��  ��XuZhongPing
+ * ��  ��  ��2017/09/04
+*********************************************************************************/
+#include "user_app.h"
+#include "usart.h"
+#include "delay.h"
+#include "timer.h"
+#include "display.h"
+
+#include "sound.h"
+
+
+static uint8_t putInPrompt = 0;					//Ͷ����Ϣ
+
+/*
+***********************************************************************
+*	�� �� ��: showHexData
+*	����˵��: ��ʮ��������ʾ�����������
+*	��    ��:	��
+*	�� �� ֵ: ��
+***********************************************************************
+*/
+void showHexData(uint8_t num[], uint8_t n)
+{
+    uint8_t i;
+		printf("\r\n");
+    for(i=0; i<n; i++)
+		{
+//       printf("%02X ",num[i]);
+			printf("0x%02X ",num[i]);
+		}
+		printf("\r\n");
+}
+
+/*
+***********************************************************************
+*	�� �� ��: GetPutInType
+*	����˵��: ȡ��Ͷ�ſ��ŷ�ʽ����
+*	��    �Σ���
+*	�� �� ֵ: 0x01->IC����0x02->��ά�룻0x03->�����룻0x04-> ��ť
+***********************************************************************
+*/
+uint8_t GetPutInType(void)
+{
+	uint8_t retData;
+	if(keyOpenDoorRequest == 1)											//���Ű�ť�ж�
+	{
+		retData = 0x04;
+		keyOpenDoorRequest = 0;
+	}else if((RFID_state == 1) || (scanIC_2CodeState == 1)){			//ˢIC����IC����ά���ж�
+		retData = 0x01;
+		RFID_state = 0;
+		scanIC_2CodeState = 0; 
+	}else if(sweep2CodeState == 1){									//��ά��ɨ���ж�
+		retData = 0x02;
+		sweep2CodeState = 0;
+	}else if(scanBarCodeState == 1){								//ɨ��������ά��
+		retData = 0x03;
+		scanBarCodeState = 0;
+	}else if(scanLabelCodeState == 1){							//��ά����ֽ��2018-04-28������
+		retData = 0x05;
+		scanLabelCodeState = 0;
+	}else{
+		retData = 0x00;
+	}
+	return retData;
+}
+
+/*
+***********************************************************************
+*	�� �� ��: GetUserInfo
+*	����˵��: �����û�����Ŀ��ŷ�ʽ��ȡ���û��������Ϣ��IC�����ά�룩
+*	��    �Σ�inputType->�û����ŷ�ʽ��IC�����ά�룩
+*	�� �� ֵ: �ޣ����ú�ı���ȫ�ֱ���getDataLength��getDataBuf��ֵ��
+***********************************************************************
+*/
+void GetUserInfo(uint8_t inputType)
+{
+	switch(inputType)																	//���ݿ�������ʽ���ض�Ӧ��������Ϣ
+	{
+		case 0x01:		//ˢIC������
+			getDataLength = 9;														//IC��������ϢΪ9�ֽ�
+			memcpy(getDataBuf, RFID_ID, 9);								//����IC��������Ϣ
+			memcpy(get_IC_ID, RFID_ID, 9);								//����IC��������Ϣ
+			memcpy(getCardNumberBit, cardNumberBit, 17);	//����IC��������Ϣ����λ��ʾ��
+// 			printf("\r\ngetDataLength = %d\r\n", getDataLength);
+// 			printf("\r\nRFID = %x\r\n", RFID_ID[0]);
+			break;
+			
+		case 0x02:		//ɨ��ά�뿪��
+			getDataLength = codeDataLength;								//��ά��������Ϣ����
+			memcpy(getDataBuf, codeBuf, codeDataLength);	//�����ά�뷢����Ϣ
+			memset(codeBuf, 0x00, 35);										//�����������
+// 			printf("\r\ngetDataLength = %d\r\n", getDataLength);
+			break;
+			
+		case 0x03:		//��������������ά�뿪��
+			getDataLength = codeDataLength;								//��ά��������Ϣ����
+			memcpy(getDataBuf, codeBuf, codeDataLength);	//�����ά�뷢����Ϣ
+			memset(codeBuf, 0x00, 35);										//�����������
+			break;
+			
+		case 0x04:		//��ť������������Ϣ
+			getDataLength = 0;								
+			break;
+			
+		case 0x05:		//��ά����ֽ����
+			getDataLength = codeDataLength;								//��ά��������Ϣ����
+			memcpy(getDataBuf, codeBuf, codeDataLength);	//�����ά�뷢����Ϣ
+			memset(codeBuf, 0x00, 35);										//�����������
+			break;
+	}
+}
+
+/*
+***********************************************************************
+*	�� �� ��: ShowPutInMSG
+*	����˵��: ��ʾͶ�ſ������ͼ�����ʶ�������Ϣ 
+*	��    �Σ�Ͷ������0x01->IC����0x02->��ά�룻0x03->�����룻0x04-> ��ť
+*	�� �� ֵ: ��
+***********************************************************************
+*/
+void ShowPutInInfo(uint8_t uType)
+{
+	switch(uType)																//���ݿ�������ʽ���ض�Ӧ��������Ϣ
+	{
+		case 0x01:		//ˢIC������
+			printf("\r\nˢIC����ɨIC����ά�뿪��\r\n");
+			break;
+			
+		case 0x02:		//ɨ��ά�뿪��
+			printf("\r\nɨ��ά�뿪��\r\n");
+			break;
+			
+		case 0x03:		//�����������뿪��
+			printf("\r\nɨ��������������ά�뿪��\r\n");
+			break;
+			
+		case 0x04:		//��ť������������Ϣ
+			printf("\r\n��ť����\r\n");							
+			break;
+			
+		case 0x05:		//��ά����ֽ����
+			printf("\r\n��ά����ֽ����\r\n");							
+			break;
+	}
+	
+	printf("\r\n�û�ʶ����ϢΪ��\r\n");	
+	printf("\r\n <>�������ͣ�%d\r\n", getPutInType);
+	printf("\r\n <>���ݳ��ȣ�%d\r\n", getDataLength);
+// 	printf("\r\n <>���ݣ�%s\r\n", getDataBuf);
+// 	showHexData(getDataBuf, 33);
+}
+
+/*
+***********************************************************************
+*	�� �� ��: ClearPutInInfo
+*	����˵��: Ͷ����ɺ����Ͷ����Ϣ��Ϊ��һ��������׼��
+*	��    �Σ���
+*	�� �� ֵ: ��
+***********************************************************************
+*/
+void ClearPutInInfo(void)
+{
+	keyOpenDoorRequest = 0;													//�����ť���±�־
+	RFID_state = 0;																	//���RFID_IC��ˢ����־
+	scanIC_2CodeState = 0;													//���ɨIC����ά�뿨�ű�־
+	sweep2CodeState = 0;														//�����ά��ɨ���־
+	scanBarCodeState = 0;														//���ɨ��������ά���־
+	scanLabelCodeState = 0;
+	
+	putInPrompt = 0;																//�����ʾ����Ͷ��������ʶ������һ��ֻ����һ�Σ�
+	
+	getPutInType = 0x00;														//�������������֤����
+	getDataLength = 0x00;														//�������������֤��Ϣ�����ݳ���
+	memset(getDataBuf, 0x00, 33);										//�������������֤��Ϣ����
+}
+
+/*
+***********************************************************************
+*	�� �� ��: FaultCodeCheck
+*	����˵��: �豸�������⣬����������1:��ʾ�й������ϴ�������
+*           0:��ʾû�й��ϲ����ϴ�������
+*	��    �Σ���
+*	�� �� ֵ: ��
+***********************************************************************
+*/
+#define codeLen 9
+uint8_t faultCode[codeLen] = {11, 12, 13, 22, 23, 24, 32, 33, 34};		//��������ϴ���
+
+static void FaultCodeCheck(uint8_t devType)
+{
+	uint8_t i = 0;
+	uint8_t faultMark = 0;
+	
+	switch(devType)
+	{
+		case DOUBLE_BARREL_480L:		//˫Ͱ480L
+			for(i = 0; i < codeLen; i++)
+			{
+				if((faultCode_1 == faultCode[i]) || (faultCode_2 == faultCode[i]))
+				{
+					faultMark = 1;
+					break;
+				}
+			}
+			break;
+			
+		case DOUBLE_BARREL_BOTTLE_480L:		//˫Ͱ480L����ƿ�ӣ�
+			for(i = 0; i < codeLen; i++)
+			{
+				if(faultCode_1 == faultCode[i])
+				{
+					faultMark = 1;
+					break;
+				}
+			}
+			break;
+			
+		case SINGLE_BARREL_660L:		//��Ͱ660L
+		case SINGLE_BARREL_480L:		//��Ͱ480L
+			for(i = 0; i < codeLen; i++)
+			{
+				if(faultCode_1 == faultCode[i])
+				{
+					faultMark = 1;
+					break;
+				}
+			}
+			break;
+			
+		default:
+			break;
+	}
+	
+	if(faultMark == 1)		//�й������ϴ�������
+	{
+		sendMsg.msgType = 6005;										//���ϴ����ϴ�
+		MessageSend(MSG_FIFO_PROTOCOL, sendMsg);
+	}
+}
+
+/*
+***********************************************************************
+*	�� �� ��: GetLimitKeyStatus
+*	����˵��: ȡ����λ���ص�״̬
+*	��    �Σ���
+*	�� �� ֵ: ������λ������λ״̬�������1���쳣��0��������
+***********************************************************************
+*/
+uint8_t GetLimitKeyStatus(void)
+{
+	uint8_t retData = 0;
+	
+	if(limitKeyExceptionMark > 0)
+	{	
+		switch(deviceType)
+		{
+			case DOUBLE_BARREL_480L:		//˫Ͱ480L
+				if(limitKeyExceptionMark & 0x10)
+				{
+					faultCode_1 = 20;
+				}
+				if(limitKeyExceptionMark & 0x01)
+				{
+					faultCode_2 = 20;
+				}
+				break;
+				
+			case DOUBLE_BARREL_BOTTLE_480L:
+				faultCode_1 = 0;										//Ŀǰƿ��Ͱû�����ù�����
+				if(limitKeyExceptionMark & 0x10)		//������ߵ���λ����
+				{
+					faultCode_2 = 20;
+				}
+				break;
+				
+			case SINGLE_BARREL_660L:		//��Ͱ660L	
+			case SINGLE_BARREL_480L:		//��Ͱ480L
+				if(limitKeyExceptionMark & 0x10)
+				{
+					faultCode_1 = 20;
+				}
+				faultCode_2 = 0;
+				break;
+				
+			default:
+				break;
+		}
+		
+		displayFaultCode = 20;
+		retData = 1;
+	}
+	return retData;
+}
+
+/*
+***********************************************************************
+*	�� �� ��: PutInOpenDoorTask
+*	����˵��: ����Ͷ����������
+*	��    �Σ���
+*	�� �� ֵ: ��
+***********************************************************************
+*/
+void PutInOpenDoorTask(void)
+{
+	uint8_t tempData;
+	static uint8_t putInStatus = 0x00;
+	static uint8_t infoDisplayStatus = 0;
+	
+	static timer waitingPutInTimer;
+	static timer displayTimer;
+	static timer waitingUploadTimer;
+	static timer outTimer;
+	static timer waitingTimer4S;
+	
+	static uint8_t timer_ok = 0;
+
+	if(timer_ok == 0)
+	{
+		timer_ok = 1;
+		timer_set(&waitingPutInTimer, CLOCK_SECOND*60);
+		timer_set(&displayTimer, CLOCK_SECOND*3);
+		timer_set(&waitingUploadTimer, CLOCK_SECOND*10);
+		timer_set(&outTimer, CLOCK_SECOND*2);
+		timer_set(&waitingTimer4S, CLOCK_SECOND*4);
+	}
+	
+	switch(putInStatus)
+	{
+		case 0x00:		//��ʼ״̬
+			tempData = GetPutInType();									//����Ƿ��п���Ͷ������
+
+//---------------------------------------------------			
+			//�ϻ�����
+// 			tempData = 0x04;
+//---------------------------------------------------
+			if(tempData > 0)														//�п�������
+			{
+				getPutInType = tempData;									//���濪��Ͷ�ŵ����ͣ���ť��IC������ά�롢�����������룩
+				tempData = 0;
+				
+				swipingCardStatus = 1;										//������ʾ��	
+				isOpenDoor = 1;														//��־Ҫ���Ų���
+				putInProgress = 1;												//��־�豸���ڽ��в���
+				
+				GetUserInfo(getPutInType);								//���ݿ��ŷ�ʽȡ���û������Ϣ
+				ShowPutInInfo(getPutInType);							//��ʾͶ�����������Ϣ
+				
+				//���û�����ʶ����Ϣ���浽���ͻ���
+				sendPutInType = getPutInType;							//����ʶ��ʽ
+				sendDataLength = getDataLength;						//����������Ϣ�ĳ���
+				memcpy(sendDataBuf, getDataBuf, 33);			//����������Ϣ
+				
+				audioNum = 0;
+				audioOutputMark = 1;
+				
+				putInOKMark = 0;													//�����Ͷ����ɱ�־
+				disablePutInMark = 0;											//�����װ����ֹ���ű�־
+				userInfoQueryStatus = 0;									//������Ӻ�̨��ȡ�õ��û���Ϣ
+				putInUploadSuccessMark = 0;								//�����Ͷ���ϴ��ɹ���־
+				
+				capitalAfter = 0;
+				accountNum = 0;
+				capital = 0;
+				isAuth = 0;
+				infoDisplayStatus = 0;										//�û���Ϣÿ��һ����ֻ��ʾһ��
+				
+				//��ʾ���ڼ����û�����
+				Screen_Landing();
+				
+				//���̨�����û���Ϣ
+				if(sendPutInType != 0x04)			//��������ʱ�����̨�����û���Ϣ
+				{
+					sendMsg.msgType = 4001;
+					MessageSend(MSG_FIFO_PROTOCOL, sendMsg);	//���̨���������������ȡ�û���Ϣָ��
+					printf("\r\n��ȡ�û���Ϣ\r\n");
+				}
+				
+				putInStatus = 0x01;
+				
+				printf("\r\n---------> �û�������Ͷ�ţ�����\r\n");
+				printf("\r\n���ڽ���Ͷ�Ų���......\r\n");
+				timer_restart(&waitingPutInTimer);
+				timer_restart(&waitingTimer4S);
+				break;
+			}
+			
+			if(GetLimitKeyStatus())		//MCU2�����豸����ָ�������ִ��������ֹͣʹ�ã�ֱ���޸���
+			{
+				sendMsg.msgType = 6005;										//���ϴ����ϴ�
+				MessageSend(MSG_FIFO_PROTOCOL, sendMsg);
+				printf("\r\n�豸���ϣ�����\r\n");
+				putInStatus = 0x10;
+				break;
+			}
+			break;
+			
+		case 0x01:		//�ȴ�Ͷ��
+			if(timer_expired(&waitingPutInTimer))
+			{
+				putInStatus = 0x00;
+				ClearPutInInfo();
+
+				Screen_Default();
+				printf("\r\n�ȴ�Ͷ����ɳ�ʱ����\r\n");
+				break;
+			}
+			
+			//-----------------------------------------------------
+			//������ʾ�û����������Ͷ��
+			if(putInPrompt == 0)
+			{
+				if(timer_expired(&waitingTimer4S))
+				{
+					AudioOutput(1);
+					putInPrompt = 1;
+				}
+			}
+			
+			//�Ƿ����ӳ�Ͷ��
+			if(delayCloseDoorStatus == 1)
+			{
+				delayCloseDoorStatus = 0;
+				timer_restart(&waitingPutInTimer);
+// 				printf("\r\n�ӳ�Ͷ��ʱ��\r\n");
+			}
+			
+			//��ʾ����ʱ
+			if(getRemainingTimerStatus == 1)
+			{
+				getRemainingTimerStatus = 0;
+				
+				if(getUserInfoMark)		//�Ƿ��Ѿ��յ���̨���ص��û���Ϣ����û���յ�ʱһֱ��ʾ���ڼ���...��
+				{
+					//��ʾ�û���Ϣ
+					if(accountNum > 0)			//�˺���Ч
+					{
+						if(infoDisplayStatus == 0)		//�û���Ϣÿ�ο���ֻ��ʾһ��
+						{
+							switch(sendPutInType)
+							{
+								case 0x01:		//ˢIC������
+									Screen_UserInfo(0x01, 1, getCardNumberBit, accountNum, capital);
+									break;
+								
+								//ɨAPP��ά�����������ά�뿪������ʾ�˺�
+								case 0x02:		//ɨ��ά�뿪��							
+								case 0x03:		//��������������ά�뿪��
+								case 0x05:
+									Screen_UserInfo(0x01, 0, NULL, accountNum, capital);
+									break;
+									
+								case 0x04:		//��ť������������Ϣ
+									break;
+							}
+							infoDisplayStatus = 1;			//����Ѿ���ʾ���û���Ϣ
+						}
+					}else{
+						Screen_UserInfo(0x05, 0, NULL, 0, 0);
+					}
+				}else{
+					if(infoDisplayStatus == 0)		//�û���Ϣÿ�ο���ֻ��ʾһ��
+					{
+						Screen_UserInfo(0x06, 0, NULL, 0, 0);
+						infoDisplayStatus = 1;			//����Ѿ���ʾ���û���Ϣ
+					}
+				}
+			
+				//��ʾ����ʱ
+				Screen_Countdown(remainingTimer);				
+
+				//-----------------------------------------------------
+				//��ʾ���ż����ر�
+				if(remainingTimer == 6)
+				{
+					AudioOutput(2);
+				}
+			}
+			
+			//����װ����ֹ����
+// 			if(disablePutInMark == 1)
+// 			{
+// 				disablePutInMark = 0;
+// 				Screen_ShowFull();
+// 				
+// 				timer_restart(&displayTimer);
+// 				printf("\r\nͰ��װ��\r\n");
+// 				putInStatus = 0x06;
+// 				break;
+// 			}
+			
+			
+			if(userInfoQueryStatus == 1)
+			{
+				userInfoQueryStatus = 0;
+				infoDisplayStatus = 0;												//���յ��û���Ϣ���������¸�����ʾ
+				getUserInfoMark = 1;
+				
+				printf("\r\n��ȡ�û���ϢOK\r\n");
+				printf("\r\naccountNum = %d \r\n", accountNum);
+				printf("\r\ncapital = %.2f \r\n", (float)capital/100);
+// 				printf("\r\nbarcodeLength = %4x \r\n", barcodeLength);
+// 				printf("\r\nbarcode = %s\r\n", barcode);
+				
+				if(accountNum > 0)			//�˺���Ч
+				{
+					switch(sendPutInType)
+					{
+						case 0x01:		//ˢIC������
+							Screen_Query(0x01, 1, getCardNumberBit, accountNum, capital);
+							break;
+						
+						//ɨAPP��ά�����������ά�뿪������ʾ�˺�
+						case 0x02:		//ɨ��ά�뿪��							
+						case 0x03:		//��������������ά�뿪��
+						case 0x05:
+							Screen_Query(0x01, 0, NULL, accountNum, capital);
+							break;
+							
+						case 0x04:		//��ť������������Ϣ
+							
+							break;
+					}
+					
+				}else{
+					Screen_Query(0x05, 0, NULL, 0, 0);
+				}
+				
+			}
+			
+			//�ж��Ƿ�Ͷ�����
+			if(putInOKMark == 1)
+			{
+				putInOKMark = 0;
+				
+				getWeight1 = uploadWeight1;
+				getWeight2 = uploadWeight2;
+				
+				getWeightBefore1 = uploadBeforeWeight1;
+				getWeightAfter1 = uploadAfterWeight1;
+				getWeightBefore2 = uploadBeforeWeight2;
+				getWeightAfter2 = uploadAfterWeight2;
+	
+				printf("\r\n�յ�Ͷ����ɣ����ڴ���......\r\n");
+				
+				printf("\r\n---> �յ�����Ͷ���������£�\r\n");
+				printf("\r\n�������ͣ�%d\r\n", sendPutInType);
+				printf("\r\n���ݳ��ȣ�%d\r\n", sendDataLength);
+				printf("\r\n���ݣ�%s\r\n", sendDataBuf);
+// 				showHexData(sendDataBuf, 33);
+				
+				switch(deviceType)
+				{
+					case DOUBLE_BARREL_480L:		//˫Ͱ480L
+						printf("\r\n��Ͱ����: %2.2f Kg��%2.2f Kg -> %2.2f Kg�����룺%3.1f cm\r\n",\
+									(float)getWeight1/100, (float)getWeightBefore1/100, (float)getWeightAfter1/100, (float)getDistance1);
+						printf("\r\n��Ͱ����: %2.2f Kg��%2.2f Kg -> %2.2f Kg�����룺%3.1f cm\r\n",\
+									(float)getWeight2/100, (float)getWeightBefore2/100, (float)getWeightAfter2/100, (float)getDistance2);
+						
+						printf("\r\n��Ͱ�����룺%d\r\n", faultCode_1);
+						printf("\r\n��Ͱ�����룺%d\r\n", faultCode_2);
+						
+						//��ʾ�û�Ͷ����Ϣ
+						Screen_ShowPutInInfo(deviceType, leftBarrelType, rightBarrelType, getWeight1, getWeight2);
+			
+						//ֻҪ�п��ž��ϴ�����20181101�޸�
+						sendMsg.msgType = 6011;														//���̨����Ͷ����Ϣ
+						MessageSend(MSG_FIFO_PROTOCOL, sendMsg);
+
+						break;
+						
+					case DOUBLE_BARREL_BOTTLE_480L:		//˫Ͱ480L��ƿ��				
+						smallBottleCount = smallBottleCount + bigBottleCount;		//��ǰ���ִ�Сƿ��
+						
+						printf("\r\nƿ��: %d ���� ���� = %3.1f cm\r\n", smallBottleCount, (float)getDistance1);
+						printf("\r\n��Ͱ����: %2.2f Kg��%2.2f Kg -> %2.2f Kg�����룺%3.1f cm\r\n",\
+									(float)getWeight2/100, (float)getWeightBefore2/100, (float)getWeightAfter2/100, (float)getDistance2);
+						
+						printf("\r\nƿ�ӹ����룺%d\r\n", faultCode_1);
+						printf("\r\n��Ͱ�����룺%d\r\n", faultCode_2);
+						
+						
+						//��ʾ�û�Ͷ����Ϣ
+						Screen_ShowPutInInfo(deviceType, leftBarrelType, rightBarrelType, smallBottleCount, getWeight2);
+						
+						//ֻҪ�п��ž��ϴ�����20181101�޸�
+						sendMsg.msgType = 6011;														//���̨����Ͷ����Ϣ
+						MessageSend(MSG_FIFO_PROTOCOL, sendMsg);
+						
+						break;
+					
+					case SINGLE_BARREL_480L:		//��Ͱ480L
+					case SINGLE_BARREL_660L:		//��Ͱ660L					
+						printf("\r\n��Ͱ����: %2.2f Kg��%2.2f Kg -> %2.2f Kg�����룺%3.1f cm\r\n",\
+									(float)getWeight1/100, (float)getWeightBefore1/100, (float)getWeightAfter1/100, (float)getDistance1);
+						
+						printf("\r\n�����룺%d\r\n", faultCode_1);
+						
+						//��ʾ�û�Ͷ����Ϣ
+						Screen_ShowPutInInfo(deviceType, leftBarrelType, 0, getWeight1, 0);
+
+						sendMsg.msgType = 6011;										//���̨����Ͷ����Ϣ
+						MessageSend(MSG_FIFO_PROTOCOL, sendMsg);
+						break;
+						
+					default:
+						break;
+				}
+
+// 				FaultCodeCheck(deviceType);			//���ϼ���ϴ�
+				
+				printf("\r\n---------->Ͷ����ɣ�ллʹ�ã�����\r\n");
+				
+				putInStatus = 0x02;
+				timer_restart(&displayTimer);
+			}
+			break;
+			
+		case 0x02:		//ͣ����ʾͶ����Ϣ����
+			if(timer_expired(&displayTimer))
+			{
+				//�����Ͷ�ţ���ȴ��ϴ��ظ�Ͷ�ź�����
+				if((getWeight2 > 0) || (getWeight1 > 0) || (smallBottleCount > 0))
+				{
+					printf("\r\n���ο�����Ͷ�ţ��ȴ��ϴ��ظ�Ͷ�ź�����\r\n");
+					
+					if((deviceType == SINGLE_BARREL_480L) && ((leftBarrelType == KITCHEN) || (leftBarrelType == OTHER)))		//����Ͱ��ʱ����ʾ�������
+					{
+						AudioOutput(3);
+						Screen_Exit();											//��ʾ���˳�ʹ�ý��桱
+						printf("\r\nͶ����ɣ��˳���\r\n");
+						putInStatus = 0x05;
+						timer_restart(&outTimer);
+					}else{
+						putInStatus = 0x03;
+						timer_restart(&waitingUploadTimer);
+					}
+				}else{																//û��Ͷ����ת��ллʹ�ý����˳�					
+					AudioOutput(3);
+				
+					Screen_Exit();											//��ʾ���˳�ʹ�ý��桱
+					printf("\r\n��ʾͶ��ʱ�䵽������Ͷ���˳�\r\n");
+					putInStatus = 0x05;
+					timer_restart(&outTimer);
+				}
+				
+			}
+			break;
+			
+		case 0x03:		//�ȴ��ϴ��ɹ���ʾͶ�ź�����
+			if(putInUploadSuccessMark == 1)
+			{
+				putInUploadSuccessMark = 0;
+				printf("\r\n֮ǰ��� = %.2f \r\n", (float)capital/100);
+				printf("\r\n֮����� = %.2f \r\n", (float)capitalAfter/100);
+				printf("\r\n������� = %.2f \r\n", (float)(capitalAfter - capital)/100);
+				
+				if(capitalAfter >= capital)
+				{
+					Screen_ShowPutInReward(capital, capitalAfter);
+				
+// 					printf("\r\n������� = %.2f \r\n", (float)(capitalAfter - capital)/100);
+// 					printf("\r\n��    �� = %.2f \r\n", (float)capitalAfter/100);
+				}
+				
+				putInStatus = 0x04;
+				timer_restart(&displayTimer);
+			}
+			
+			if(timer_expired(&waitingUploadTimer))
+			{
+				audioNum = 3;
+				audioOutputMark = 1;
+					
+				Screen_Exit();											//��ʾ���˳�ʹ�ý��桱
+				printf("\r\n��ʾͶ��ʱ�䵽\r\n");
+				putInStatus = 0x05;
+				timer_restart(&outTimer);
+			}
+			break;
+			
+		case 0x04:
+			if(timer_expired(&displayTimer))
+			{
+				audioNum = 3;
+				audioOutputMark = 1;
+				
+				Screen_Exit();											//��ʾ���˳�ʹ�ý��桱
+				printf("\r\n��ʾͶ��ʱ�䵽\r\n");
+				putInStatus = 0x05;
+				timer_restart(&outTimer);
+			}
+			break;
+			
+		case 0x05:		//ͣ����ʾ�˳�����
+			if(timer_expired(&outTimer))
+			{
+				printf("\r\n��ʾ����\r\n");
+				Screen_Default();
+				ClearPutInInfo();
+				putInProgress = 0;
+				putInStatus = 0x00;
+			}
+			break;
+			
+//-----------------------------------------------------------------------------------------	
+		
+		case 0x06:		//װ����ֹ����ʱ��ʾװ����ʾ
+			if(timer_expired(&displayTimer))
+			{
+				printf("\r\n��ʾ����\r\n");
+				Screen_Default();
+				ClearPutInInfo();
+				putInStatus = 0x00;
+			}
+			break;
+			
+		case 0x10:		//�豸����ת���˴��ȴ�����
+			Screen_Error(0, displayFaultCode, 0);
+				
+			putInStatus = 0x11;
+			break;
+			
+		case 0x11:
+			//����λ���س��ֹ���֮�����е��ˣ�ֱ���޸�
+			break;
+			
+		default:
+			putInStatus = 0x00;
+			break;
+	}
+}
+
+/******************** (C) COPYRIGHT 2017 Ping *****END OF FILE*******************/
diff --git a/STM32_4路称重_Git提交精简工程/src/USER/over_flow.h b/STM32_4路称重_Git提交精简工程/src/USER/over_flow.h
new file mode 100755
index 0000000..37c18aa
--- /dev/null
+++ b/STM32_4路称重_Git提交精简工程/src/USER/over_flow.h
@@ -0,0 +1,22 @@
+/*************************** (C) COPYRIGHT 2017 CXHY ****************************
+ * �ļ���  ��device.h
+ * ��  ��  ���豸���Ƴ���
+ * ��  ��  ��V1.0
+ * ��  ��  ��XuZhongPing
+ * ��  ��  ��2017/03/06 
+*********************************************************************************/
+#ifndef __USER_APP_H
+#define __USER_APP_H	 
+
+#include "sys.h" 
+#include "string.h" 
+#include "stdlib.h" 
+#include "device.h"
+#include "data_typedef.h"
+
+void showHexData(uint8_t num[], uint8_t n);
+void PutInOpenDoorTask(void);
+
+#endif
+
+/******************** (C) COPYRIGHT 2017 CXHY *****END OF FILE*******************/
diff --git a/STM32_4路称重_Git提交精简工程/src/USER/pc_protocol.c b/STM32_4路称重_Git提交精简工程/src/USER/pc_protocol.c
new file mode 100755
index 0000000..caea29b
--- /dev/null
+++ b/STM32_4路称重_Git提交精简工程/src/USER/pc_protocol.c
@@ -0,0 +1,909 @@
+/*************************** (C) COPYRIGHT 2017 CXHY ****************************
+ * �ļ���  pc_protocol.c
+ * ��  ��  ����λ��Э�鴦������
+ * ��  ��  ��V1.0
+ * ��  ��  ��XuZhongPing
+ * ��  ��  ��2017/03/16 
+*********************************************************************************/
+#include "pc_protocol.h"
+#include "delay.h"
+#include "timer.h"
+#include "usart1.h"
+#include "usart3.h"
+#include "string.h"
+#include "stdlib.h"  
+#include "data_typedef.h"
+#include "device.h"
+#include "gsm_uart_conf.h"
+#include "gsm_gprs.h"
+
+uint8_t PC_PRO_RX_BUF[PC_PRO_RECV_LEN];     	//���ջ���
+uint8_t PC_PRO_TX_BUF[PC_PRO_SEND_LEN];				//���ͻ���
+
+
+static void PC_ProCommandRun(uint8_t *pRxBuf, uint8_t *pTxBuf);
+
+/*
+***********************************************************************
+*	�� �� ��: show
+*	����˵��: ��ʮ��������ʾ�����������
+*	��    ��:	��
+*	�� �� ֵ: ��
+***********************************************************************
+*/
+void showHex(uint8_t num[], uint8_t n)
+{
+    uint8_t i;
+		printf("\r\n");
+    for(i=0; i<n; i++)
+		{
+      printf("%02X ",num[i]);
+		}
+		printf("\r\n");
+}
+
+/*
+***********************************************************************
+*	�� �� ��: PC_ProDataPackingAndSend
+*	����˵��: ����λ��ͨ�����ݴ��������
+*	��    ��:	*pdata -> ��Ҫ��������ݵ�ַ��dataLen -> ���ݳ���
+*	�� �� ֵ: ��
+***********************************************************************
+*/
+void PC_ProDataPackingAndSend(uint8_t *pdata, uint16_t dataLen)
+{
+	uint16_t i;
+	uint8_t CS = 0;
+	uint16_t TX_Size = 0;
+	
+	uint8_t tempSendDataBuf[256];
+	uint16_t dataAddrIndex = 0;
+	
+	tempSendDataBuf[dataAddrIndex++] = 0xFE; 				//����ǰ���ֽ�
+	tempSendDataBuf[dataAddrIndex++] = 0xFE; 			
+	tempSendDataBuf[dataAddrIndex++] = 0xFE; 
+	
+	tempSendDataBuf[dataAddrIndex++] = 0x68; 				//����֡ͷ
+	CS += 0x68;
+	
+	tempSendDataBuf[dataAddrIndex++] = *(pdata+0); 	//���͵�ַ
+	CS += *pdata;
+	
+	tempSendDataBuf[dataAddrIndex++] = 0x68; 				//����֡ͷ
+	CS += 0x68;
+	
+	tempSendDataBuf[dataAddrIndex++] = *(pdata+1); 	//����֡����
+	CS += *(pdata+1);
+	
+	tempSendDataBuf[dataAddrIndex++] = *(pdata+2); 	//�������ݳ��ȣ���8λ��
+	CS += *(pdata+2);
+	tempSendDataBuf[dataAddrIndex++] = *(pdata+3); 	//�������ݳ��ȣ���8λ��
+	CS += *(pdata+3);
+	
+	TX_Size = (*(pdata+2) << 8) | (*(pdata+3));			//ȡ��ͨѶ���ݳ���
+	for(i=0; i<TX_Size; i++) 												//���ط�������
+	{
+		tempSendDataBuf[dataAddrIndex++] = *(pdata+4+i);
+		CS += (*(pdata+4+i));
+	}
+	tempSendDataBuf[dataAddrIndex++] = CS; 					//����У���ֽ�
+	tempSendDataBuf[dataAddrIndex++] = 0x16;
+	
+// 	showHex(sendDataBuf, dataAddrIndex);
+
+	USART4_SendFrameData(tempSendDataBuf, dataAddrIndex);
+}
+
+/*
+***********************************************************************
+*	�� �� ��: PC_ProCommandRun
+*	����˵��: ����λ��ͨѶ����ִ��
+*	��    ��:	*pRxBuf -> ���ջ���ĵ�ַ��*pTxBuf -> �������ݻ����ַ 
+*	�� �� ֵ: ��
+***********************************************************************
+*/
+static void PC_ProCommandRun(uint8_t *pRxBuf, uint8_t *pTxBuf)
+{
+	uint8_t pc_proNum = 0;
+	uint16_t temp16BitData = 0;
+	
+	pc_proNum = *(pRxBuf+1);
+	
+	printf("\r\nPC <-- 0x%02X\r\n", pc_proNum);
+	switch(pc_proNum)														//ͨѶ��������
+	{
+		case 0x01:
+			break;
+		
+		case 0x02:		//��Ͷ��ָ��
+			openDoorNumber = *(pRxBuf+5);
+			if(openDoorNumber == 0)
+			{
+				openDoorNumber = 255;
+				rspPCDoorNumber = 255;
+				if((fullMark1 == 0) || (fullMark2 == 0) ||
+					 (fullMark3 == 0) || (fullMark4 == 0))
+				{
+					pcRequestOpenDoorMark = 1;
+				}
+			}else{
+				rspPCDoorNumber = openDoorNumber;
+				
+				switch(openDoorNumber)
+				{
+					case 1:
+						if(fullMark1 == 0)								//����ͨ��û��װ���ſ��Դ�
+						{
+							pcRequestOpenDoorMark = 1;
+						}
+						break;
+						
+					case 2:
+						if(fullMark2 == 0)								//����ͨ��û��װ���ſ��Դ�
+						{
+							pcRequestOpenDoorMark = 1;
+						}
+						break;
+
+					case 3:
+						if(fullMark3 == 0)
+						{
+							pcRequestOpenDoorMark = 1;
+						}
+						break;
+
+					case 4:
+						if(fullMark4 == 0)
+						{
+							pcRequestOpenDoorMark = 1;
+						}
+						break;
+						
+						
+					default:
+						break;
+				}
+			}
+			
+			PC_ProCommandSend(pc_proNum);
+// 			printf("\r\n�յ���λ��Ӧ��ָ��0x02\r\n");
+			break;
+			
+		case 0x03:		//�ر�Ͷ��ָ��
+			pcRequestClooseDoorMark = 1;
+			PC_ProCommandSend(pc_proNum);
+// 			printf("\r\n�յ���λ��Ӧ��ָ��0x02\r\n");
+			break;
+			
+		case 0x04:		//��������ָ��
+// 			openDoorNumber = *(pRxBuf+5);
+// 			if(openDoorNumber == 0)
+// 			{
+// 				openDoorNumber = 255;
+// 				rspPCDoorNumber = 255;
+// 			}else{
+// 				rspPCDoorNumber = openDoorNumber;
+// 			}
+			
+			boxOpenMark = 1;
+			PC_ProCommandSend(pc_proNum);
+			break;
+			
+		case 0x20:		//������ѯָ��
+			rspPCWeightNumber = *(pRxBuf+5);
+			if(rspPCWeightNumber == 0)
+			{
+				rspPCWeightNumber = 255;
+			}
+			
+			PC_ProCommandSend(pc_proNum);
+			break;
+			
+		case 0x21:		//����״̬��ѯ
+			rspPCDistanceNumber = *(pRxBuf+5);
+			if(rspPCDistanceNumber == 0)
+			{
+				rspPCDistanceNumber = 255;
+			}
+			
+			PC_ProCommandSend(pc_proNum);
+			break;
+			
+		case 0x22:		//�¶Ȳ�ѯָ��
+			rspPCTemperatureNumber = *(pRxBuf+5);
+			if(rspPCTemperatureNumber == 0)
+			{
+				rspPCTemperatureNumber = 255;
+			}
+			
+			PC_ProCommandSend(pc_proNum);
+			break;
+			
+		case 0x23:		//�����Źر�״̬��ѯָ��
+			PC_ProCommandSend(pc_proNum);
+			break;
+			
+		case 0x30:		//��ȡ��λ�������汾��ָ��
+			PC_ProCommandSend(pc_proNum);
+			break;
+			
+		case 0x31:		//��ȡIMEI��ָ��
+			PC_ProCommandSend(pc_proNum);
+			break;
+			
+		case 0x91:		//�豸ʱ��ͬ��
+			timestamp_s = *(pRxBuf+5) << 24;
+			timestamp_s |= *(pRxBuf+6) << 16;
+			timestamp_s |= *(pRxBuf+7) << 8;
+			timestamp_s |= *(pRxBuf+8);
+			getDateTimeMark = 1;
+			break;
+			
+		case 0x92:		//��λ���豸״̬ͬ��
+			temp16BitData |= *(pRxBuf+5) << 8;
+			temp16BitData |= *(pRxBuf+6);
+			
+			switch(temp16BitData)
+			{
+				case 0x0001:
+					netStatus = *(pRxBuf+7) << 8;
+					netStatus |= *(pRxBuf+8);
+					break;
+					
+				case 0x0002:
+					devRunnigStatus = *(pRxBuf+7) << 8;
+					devRunnigStatus |= *(pRxBuf+8);
+					break;
+					
+				default:
+					break;
+			}
+			break;
+			
+		default: 			//��������
+			break;
+	}
+}
+
+/*
+***********************************************************************
+*	�� �� ��: PC_ProDataPacking
+*	����˵��: ��λ������λ���������ݴ��
+*	��    ��:	protocolNo -> Э���
+*	�� �� ֵ: ��
+***********************************************************************
+*/
+void PC_ProDataPacking(uint8_t protocolNo)
+{
+	uint16_t dataAddr = 0;														//���͵�������������					
+
+	uint32_t temp = 0;
+	uint16_t len = 0;
+	
+	uint16_t tmpeData = 0;
+	uint8_t tempData1 = 0;
+	uint8_t tempAddr = 0;
+	uint8_t dataCunt = 0;
+	
+	PC_PRO_TX_BUF[dataAddr++] = 0x00; 												//���ôӻ�ͨѶ��ַ
+	PC_PRO_TX_BUF[dataAddr++] = protocolNo;										//����������
+	
+	PC_PRO_TX_BUF[dataAddr++] = 0x00;													//���͵����ݳ��ȣ����ݼ�����ɺ����룩
+	PC_PRO_TX_BUF[dataAddr++] = 0x00;
+	
+	printf("\r\nPC --> 0x%02X\r\n", protocolNo);
+	
+	switch(protocolNo)
+	{
+		case 0x01:		//�û�����ʶ��
+			PC_PRO_TX_BUF[dataAddr++] = 0x01;												//Э��汾��
+			
+			PC_PRO_TX_BUF[dataAddr++] = sendPutInType;							//ʶ��ʽ
+			PC_PRO_TX_BUF[dataAddr++] = sendDataLength;							//���ݳ���
+			memcpy(&PC_PRO_TX_BUF[dataAddr], sendDataBuf, sendDataLength);		//��������
+			dataAddr += sendDataLength;
+			break;
+			
+		case 0x02:		//��λ�������Ͷ�ڻ�Ӧ
+			PC_PRO_TX_BUF[dataAddr++] = 0x01;												//Э��汾��
+			
+			if(rspPCDoorNumber == 255)
+			{
+				PC_PRO_TX_BUF[dataAddr++] = 4;													//Ͷ������
+				
+				PC_PRO_TX_BUF[dataAddr++] = 1;													//Ͷ��1
+				PC_PRO_TX_BUF[dataAddr++] = fullMark1;									//��ǰ����״̬
+				
+				PC_PRO_TX_BUF[dataAddr++] = 2;													//Ͷ��2
+				PC_PRO_TX_BUF[dataAddr++] = fullMark2;									//��ǰ����״̬
+				
+				PC_PRO_TX_BUF[dataAddr++] = 3;													//Ͷ��3
+				PC_PRO_TX_BUF[dataAddr++] = fullMark3;									//��ǰ����״̬
+				
+				PC_PRO_TX_BUF[dataAddr++] = 4;													//Ͷ��4
+				PC_PRO_TX_BUF[dataAddr++] = fullMark4;									//��ǰ����״̬
+				
+			}else{
+				PC_PRO_TX_BUF[dataAddr++] = 1;													//Ͷ������
+				PC_PRO_TX_BUF[dataAddr++] = rspPCDoorNumber;
+				switch(rspPCDoorNumber)
+				{
+					case 1:
+						PC_PRO_TX_BUF[dataAddr++] = fullMark1;							//��ǰ����״̬
+						break;
+						
+					case 2:
+						PC_PRO_TX_BUF[dataAddr++] = fullMark2;
+						break;
+
+					case 3:
+						PC_PRO_TX_BUF[dataAddr++] = fullMark3;
+						break;
+
+					case 4:
+						PC_PRO_TX_BUF[dataAddr++] = fullMark4;
+						break;
+						
+					default:
+						PC_PRO_TX_BUF[dataAddr++] = 0x00;
+						break;
+				}									
+			}
+			break;
+			
+		case 0x03:
+			PC_PRO_TX_BUF[dataAddr++] = 0x01;												//Э��汾��
+			break;
+			
+		case 0x04:		//��λ������������Ż�Ӧ
+			PC_PRO_TX_BUF[dataAddr++] = 0x01;												//Э��汾��
+			
+			PC_PRO_TX_BUF[dataAddr++] = 1;													//����������
+			PC_PRO_TX_BUF[dataAddr++] = 1;
+			PC_PRO_TX_BUF[dataAddr++] = 0x00;												//��ǰ����״̬
+			break;
+			
+		case 0x08:
+			break;
+			
+		case 0x09:
+			break;
+			
+		case 0x20:		//��λ������ǰ����������Ӧ
+//			ģ���������
+// 			weight1 = 0x1234;
+// 			weight2 = 0x2345;
+// 			weight3 = 0x3456;
+// 			weight4 = 0x4567;
+			
+			PC_PRO_TX_BUF[dataAddr++] = 0x01;												//Э��汾��
+			
+			switch(rspPCWeightNumber)
+			{
+				case 1:
+					PC_PRO_TX_BUF[dataAddr++] = 1;													//Ͷ������
+					PC_PRO_TX_BUF[dataAddr++] = rspPCWeightNumber;
+					PC_PRO_TX_BUF[dataAddr++] = weight1 >> 8;								//��ǰ����
+					PC_PRO_TX_BUF[dataAddr++] = weight1;
+					break;
+					
+				case 2:
+					PC_PRO_TX_BUF[dataAddr++] = 1;													//Ͷ������
+					PC_PRO_TX_BUF[dataAddr++] = rspPCWeightNumber;
+					PC_PRO_TX_BUF[dataAddr++] = weight2 >> 8;								//��ǰ����
+					PC_PRO_TX_BUF[dataAddr++] = weight2;
+					break;
+					
+				case 3:
+					PC_PRO_TX_BUF[dataAddr++] = 1;													//Ͷ������
+					PC_PRO_TX_BUF[dataAddr++] = rspPCWeightNumber;
+					PC_PRO_TX_BUF[dataAddr++] = weight3 >> 8;								//��ǰ����
+					PC_PRO_TX_BUF[dataAddr++] = weight3;
+					break;
+					
+				case 4:
+					PC_PRO_TX_BUF[dataAddr++] = 1;													//Ͷ������
+					PC_PRO_TX_BUF[dataAddr++] = rspPCWeightNumber;
+					PC_PRO_TX_BUF[dataAddr++] = weight4 >> 8;								//��ǰ����
+					PC_PRO_TX_BUF[dataAddr++] = weight4;
+					break;
+					
+				case 255:
+					PC_PRO_TX_BUF[dataAddr++] = 4;													//Ͷ������
+					
+					PC_PRO_TX_BUF[dataAddr++] = 1;													//Ͷ��1
+					PC_PRO_TX_BUF[dataAddr++] = weight1 >> 8;								//��ǰ����
+					PC_PRO_TX_BUF[dataAddr++] = weight1;
+					
+					PC_PRO_TX_BUF[dataAddr++] = 2;													//Ͷ��2
+					PC_PRO_TX_BUF[dataAddr++] = weight2 >> 8;								//��ǰ����
+					PC_PRO_TX_BUF[dataAddr++] = weight2;
+					
+					PC_PRO_TX_BUF[dataAddr++] = 3;													//Ͷ��3
+					PC_PRO_TX_BUF[dataAddr++] = weight3 >> 8;								//��ǰ����
+					PC_PRO_TX_BUF[dataAddr++] = weight3;
+					
+					PC_PRO_TX_BUF[dataAddr++] = 4;													//Ͷ��4
+					PC_PRO_TX_BUF[dataAddr++] = weight4 >> 8;								//��ǰ����
+					PC_PRO_TX_BUF[dataAddr++] = weight4;
+					break;
+					
+				default:
+					break;
+			}
+			break;
+			
+		case 0x21:		//��λ������ǰ����״̬��Ӧ
+//			ģ���������
+// 			getDistance1 = 0x15;
+// 			getDistance2 = 0x25;
+// 			getDistance3 = 0x35;
+// 			getDistance4 = 0x45;
+			
+			PC_PRO_TX_BUF[dataAddr++] = 0x01;												//Э��汾��
+			
+			switch(rspPCDistanceNumber)
+			{
+				case 1:
+					PC_PRO_TX_BUF[dataAddr++] = 1;													//Ͷ������
+					PC_PRO_TX_BUF[dataAddr++] = rspPCDistanceNumber;
+					PC_PRO_TX_BUF[dataAddr++] = outputDistance1;								//��ǰ���ֵ
+					break;
+					
+				case 2:
+					PC_PRO_TX_BUF[dataAddr++] = 1;													//Ͷ������
+					PC_PRO_TX_BUF[dataAddr++] = rspPCDistanceNumber;
+					PC_PRO_TX_BUF[dataAddr++] = outputDistance2;								//��ǰ���ֵ
+					break;
+					
+				case 3:
+					PC_PRO_TX_BUF[dataAddr++] = 1;													//Ͷ������
+					PC_PRO_TX_BUF[dataAddr++] = rspPCDistanceNumber;
+					PC_PRO_TX_BUF[dataAddr++] = outputDistance3;							//��ǰ���ֵ
+					break;
+					
+				case 4:
+					PC_PRO_TX_BUF[dataAddr++] = 1;													//Ͷ������
+					PC_PRO_TX_BUF[dataAddr++] = rspPCDistanceNumber;
+					PC_PRO_TX_BUF[dataAddr++] = outputDistance4;							//��ǰ���ֵ
+					break;
+					
+				case 255:
+					PC_PRO_TX_BUF[dataAddr++] = 4;													//Ͷ������
+					
+					PC_PRO_TX_BUF[dataAddr++] = 1;													//Ͷ��1
+					PC_PRO_TX_BUF[dataAddr++] = outputDistance1;								//��ǰ���ֵ
+					
+					PC_PRO_TX_BUF[dataAddr++] = 2;													//Ͷ��2
+					PC_PRO_TX_BUF[dataAddr++] = outputDistance2;								//��ǰ���ֵ
+					
+					PC_PRO_TX_BUF[dataAddr++] = 3;													//Ͷ��3
+					PC_PRO_TX_BUF[dataAddr++] = outputDistance3;							//��ǰ���ֵ
+					
+					PC_PRO_TX_BUF[dataAddr++] = 4;													//Ͷ��4
+					PC_PRO_TX_BUF[dataAddr++] = outputDistance4;							//��ǰ���ֵ
+					break;
+					
+				default:
+					break;
+			}
+			break;
+			
+		case 0x22:		//��λ������ǰ�¶�ֵ��Ӧ			
+			PC_PRO_TX_BUF[dataAddr++] = 0x01;												//Э��汾��
+			switch(rspPCTemperatureNumber)
+			{
+				case 1:
+					PC_PRO_TX_BUF[dataAddr++] = 1;													//Ͷ������
+					PC_PRO_TX_BUF[dataAddr++] = rspPCTemperatureNumber;
+					PC_PRO_TX_BUF[dataAddr++] = 0x00;												//�¶ȷ���
+					tmpeData = temperature*10;															//�ϴ����ݷŴ�10��
+					PC_PRO_TX_BUF[dataAddr++] = tmpeData >> 8;							//�¶ȸ�8λ
+					PC_PRO_TX_BUF[dataAddr++] = tmpeData;										//�¶ȵ�8λ
+					break;
+					
+				case 2:
+					PC_PRO_TX_BUF[dataAddr++] = 1;													//Ͷ������
+					PC_PRO_TX_BUF[dataAddr++] = rspPCTemperatureNumber;
+					PC_PRO_TX_BUF[dataAddr++] = 0x00;												//�¶ȷ���
+					tmpeData = temperature*10;															//�ϴ����ݷŴ�10��
+					PC_PRO_TX_BUF[dataAddr++] = tmpeData >> 8;							//�¶ȸ�8λ
+					PC_PRO_TX_BUF[dataAddr++] = tmpeData;										//�¶ȵ�8λ
+					break;
+					
+				case 3:
+					PC_PRO_TX_BUF[dataAddr++] = 1;													//Ͷ������
+					PC_PRO_TX_BUF[dataAddr++] = rspPCTemperatureNumber;
+					PC_PRO_TX_BUF[dataAddr++] = 0x00;												//�¶ȷ���
+					tmpeData = temperature*10;															//�ϴ����ݷŴ�10��
+					PC_PRO_TX_BUF[dataAddr++] = tmpeData >> 8;							//�¶ȸ�8λ
+					PC_PRO_TX_BUF[dataAddr++] = tmpeData;										//�¶ȵ�8λ
+					break;
+					
+				case 4:
+					PC_PRO_TX_BUF[dataAddr++] = 1;													//Ͷ������
+					PC_PRO_TX_BUF[dataAddr++] = rspPCTemperatureNumber;
+					PC_PRO_TX_BUF[dataAddr++] = 0x00;												//�¶ȷ���
+					tmpeData = temperature*10;															//�ϴ����ݷŴ�10��
+					PC_PRO_TX_BUF[dataAddr++] = tmpeData >> 8;							//�¶ȸ�8λ
+					PC_PRO_TX_BUF[dataAddr++] = tmpeData;										//�¶ȵ�8λ
+					break;
+					
+				case 255:
+					PC_PRO_TX_BUF[dataAddr++] = 4;													//Ͷ������
+					
+					PC_PRO_TX_BUF[dataAddr++] = 1;													//Ͷ��1
+					PC_PRO_TX_BUF[dataAddr++] = 0x00;												//�¶ȷ���
+					tmpeData = temperature*10;															//�ϴ����ݷŴ�10��
+					PC_PRO_TX_BUF[dataAddr++] = tmpeData >> 8;							//�¶ȸ�8λ
+					PC_PRO_TX_BUF[dataAddr++] = tmpeData;										//�¶ȵ�8λ
+					
+					PC_PRO_TX_BUF[dataAddr++] = 2;													//Ͷ��2
+					PC_PRO_TX_BUF[dataAddr++] = 0x00;												//�¶ȷ���
+					tmpeData = temperature*10;															//�ϴ����ݷŴ�10��
+					PC_PRO_TX_BUF[dataAddr++] = tmpeData >> 8;							//�¶ȸ�8λ
+					PC_PRO_TX_BUF[dataAddr++] = tmpeData;										//�¶ȵ�8λ
+					
+					PC_PRO_TX_BUF[dataAddr++] = 3;													//Ͷ��3
+					PC_PRO_TX_BUF[dataAddr++] = 0x00;												//�¶ȷ���
+					tmpeData = temperature*10;															//�ϴ����ݷŴ�10��
+					PC_PRO_TX_BUF[dataAddr++] = tmpeData >> 8;							//�¶ȸ�8λ
+					PC_PRO_TX_BUF[dataAddr++] = tmpeData;										//�¶ȵ�8λ
+					
+					PC_PRO_TX_BUF[dataAddr++] = 4;													//Ͷ��4
+					PC_PRO_TX_BUF[dataAddr++] = 0x00;												//�¶ȷ���
+					tmpeData = temperature*10;															//�ϴ����ݷŴ�10��
+					PC_PRO_TX_BUF[dataAddr++] = tmpeData >> 8;							//�¶ȸ�8λ
+					PC_PRO_TX_BUF[dataAddr++] = tmpeData;										//�¶ȵ�8λ
+					break;
+					
+				default:
+					break;
+			}
+			break;
+			
+		case 0x23:		//������״̬���
+			PC_PRO_TX_BUF[dataAddr++] = 0x01;												//Э��汾��
+			
+			PC_PRO_TX_BUF[dataAddr++] = 0x01;												//Ͷ������
+			
+			PC_PRO_TX_BUF[dataAddr++] = 1;													//Ͷ�ڱ��
+			PC_PRO_TX_BUF[dataAddr++] = recycleClearDoorMark;				//������״̬
+			break;
+			
+		case 0x30:		//��ȡ��λ�������汾��
+			PC_PRO_TX_BUF[dataAddr++] = 0x01;												//Э��汾��
+			len = strlen(VersionNumber);
+			PC_PRO_TX_BUF[dataAddr++] = len;												//�����汾�ų���
+			memcpy(&PC_PRO_TX_BUF[dataAddr], VersionNumber, len);
+			dataAddr += len;
+			break;
+			
+		case 0x31:		//��ȡIMEI��
+			PC_PRO_TX_BUF[dataAddr++] = 0x01;												//Э��汾��
+			PC_PRO_TX_BUF[dataAddr++] = 15;													//IMEI�ų���
+			memcpy(&PC_PRO_TX_BUF[dataAddr], gsm_msg.IMEI, 15);
+			dataAddr += 15;
+			break;
+			
+		case 0x60:		//���ŵ���ʱ��ʾ
+			PC_PRO_TX_BUF[dataAddr++] = 0x01;												//Э��汾��
+			PC_PRO_TX_BUF[dataAddr++] = remainingTimer;	
+			break;
+			
+		case 0x61:		//Ͷ�������ϴ�
+			PC_PRO_TX_BUF[dataAddr++] = 0x01;												//Э��汾��
+			switch(deviceType)
+			{
+				case DOUBLE_CLASSIFICATION:		//������
+					PC_PRO_TX_BUF[dataAddr++] = 2;											//������
+					
+					//��1������
+					PC_PRO_TX_BUF[dataAddr++] = 1;											//ͶƷ���
+					
+					PC_PRO_TX_BUF[dataAddr++] = getWeight1 >> 8;				//����Ͷ������
+					PC_PRO_TX_BUF[dataAddr++] = getWeight1;
+					
+					PC_PRO_TX_BUF[dataAddr++] = getWeightBefore1 >> 8;	//Ͷ��ǰ����
+					PC_PRO_TX_BUF[dataAddr++] = getWeightBefore1;
+					
+					PC_PRO_TX_BUF[dataAddr++] = getWeightAfter1 >> 8;		//Ͷ�ź�����
+					PC_PRO_TX_BUF[dataAddr++] = getWeightAfter1;
+					
+					PC_PRO_TX_BUF[dataAddr++] = outputDistance1;						//���ֵ
+					
+					//��2������
+					PC_PRO_TX_BUF[dataAddr++] = 2;											//ͶƷ���
+					
+					PC_PRO_TX_BUF[dataAddr++] = getWeight2 >> 8;				//����Ͷ������
+					PC_PRO_TX_BUF[dataAddr++] = getWeight2;
+					
+					PC_PRO_TX_BUF[dataAddr++] = getWeightBefore2 >> 8;	//Ͷ��ǰ����
+					PC_PRO_TX_BUF[dataAddr++] = getWeightBefore2;
+					
+					PC_PRO_TX_BUF[dataAddr++] = getWeightAfter2 >> 8;		//Ͷ�ź�����
+					PC_PRO_TX_BUF[dataAddr++] = getWeightAfter2;
+					
+					PC_PRO_TX_BUF[dataAddr++] = outputDistance2;						//���ֵ
+					break;
+
+				case FOUR_CLASSIFICATION:
+					PC_PRO_TX_BUF[dataAddr++] = 4;
+
+					PC_PRO_TX_BUF[dataAddr++] = 1;
+					PC_PRO_TX_BUF[dataAddr++] = getWeight1 >> 8;
+					PC_PRO_TX_BUF[dataAddr++] = getWeight1;
+					PC_PRO_TX_BUF[dataAddr++] = getWeightBefore1 >> 8;
+					PC_PRO_TX_BUF[dataAddr++] = getWeightBefore1;
+					PC_PRO_TX_BUF[dataAddr++] = getWeightAfter1 >> 8;
+					PC_PRO_TX_BUF[dataAddr++] = getWeightAfter1;
+					PC_PRO_TX_BUF[dataAddr++] = outputDistance1;
+
+					PC_PRO_TX_BUF[dataAddr++] = 2;
+					PC_PRO_TX_BUF[dataAddr++] = getWeight2 >> 8;
+					PC_PRO_TX_BUF[dataAddr++] = getWeight2;
+					PC_PRO_TX_BUF[dataAddr++] = getWeightBefore2 >> 8;
+					PC_PRO_TX_BUF[dataAddr++] = getWeightBefore2;
+					PC_PRO_TX_BUF[dataAddr++] = getWeightAfter2 >> 8;
+					PC_PRO_TX_BUF[dataAddr++] = getWeightAfter2;
+					PC_PRO_TX_BUF[dataAddr++] = outputDistance2;
+
+					PC_PRO_TX_BUF[dataAddr++] = 3;
+					PC_PRO_TX_BUF[dataAddr++] = getWeight3 >> 8;
+					PC_PRO_TX_BUF[dataAddr++] = getWeight3;
+					PC_PRO_TX_BUF[dataAddr++] = getWeightBefore3 >> 8;
+					PC_PRO_TX_BUF[dataAddr++] = getWeightBefore3;
+					PC_PRO_TX_BUF[dataAddr++] = getWeightAfter3 >> 8;
+					PC_PRO_TX_BUF[dataAddr++] = getWeightAfter3;
+					PC_PRO_TX_BUF[dataAddr++] = outputDistance3;
+
+					PC_PRO_TX_BUF[dataAddr++] = 4;
+					PC_PRO_TX_BUF[dataAddr++] = getWeight4 >> 8;
+					PC_PRO_TX_BUF[dataAddr++] = getWeight4;
+					PC_PRO_TX_BUF[dataAddr++] = getWeightBefore4 >> 8;
+					PC_PRO_TX_BUF[dataAddr++] = getWeightBefore4;
+					PC_PRO_TX_BUF[dataAddr++] = getWeightAfter4 >> 8;
+					PC_PRO_TX_BUF[dataAddr++] = getWeightAfter4;
+					PC_PRO_TX_BUF[dataAddr++] = outputDistance4;
+					break;
+					
+				default:break;				
+			}
+			
+			printf("\r\n0x61 Update D1=%d, D2=%d, D3=%d, D4=%d\r\n",
+						 outputDistance1, outputDistance2, outputDistance3, outputDistance4);
+			break;
+			
+		case 0x62:
+			PC_PRO_TX_BUF[dataAddr++] = 0x01;												//Э��汾��
+			switch(deviceType)
+			{
+				case DOUBLE_CLASSIFICATION:		//������
+					PC_PRO_TX_BUF[dataAddr++] = 2;											//Ͷ������
+					
+					//ͨ��1
+					PC_PRO_TX_BUF[dataAddr++] = 0x01;										//Ͷ�ڱ��
+					
+					PC_PRO_TX_BUF[dataAddr++] = 0x00;
+					tmpeData = temperature*10;
+					PC_PRO_TX_BUF[dataAddr++] = tmpeData >> 8;					//�¶ȸ�8λ
+					PC_PRO_TX_BUF[dataAddr++] = tmpeData;								//�¶ȵ�8λ
+					
+					PC_PRO_TX_BUF[dataAddr++] = outputDistance1;						//���ֵ	
+					
+					//ͨ��2
+					PC_PRO_TX_BUF[dataAddr++] = 0x02;										//Ͷ�ڱ��
+					
+					PC_PRO_TX_BUF[dataAddr++] = 0x00;
+					tmpeData = temperature*10;
+					PC_PRO_TX_BUF[dataAddr++] = tmpeData >> 8;					//�¶ȸ�8λ
+					PC_PRO_TX_BUF[dataAddr++] = tmpeData;								//�¶ȵ�8λ
+					
+					PC_PRO_TX_BUF[dataAddr++] = outputDistance2;						//���ֵ
+					break;
+
+				case FOUR_CLASSIFICATION:
+					PC_PRO_TX_BUF[dataAddr++] = 4;
+					tmpeData = temperature*10;
+
+					PC_PRO_TX_BUF[dataAddr++] = 0x01;
+					PC_PRO_TX_BUF[dataAddr++] = 0x00;
+					PC_PRO_TX_BUF[dataAddr++] = tmpeData >> 8;
+					PC_PRO_TX_BUF[dataAddr++] = tmpeData;
+					PC_PRO_TX_BUF[dataAddr++] = outputDistance1;
+
+					PC_PRO_TX_BUF[dataAddr++] = 0x02;
+					PC_PRO_TX_BUF[dataAddr++] = 0x00;
+					PC_PRO_TX_BUF[dataAddr++] = tmpeData >> 8;
+					PC_PRO_TX_BUF[dataAddr++] = tmpeData;
+					PC_PRO_TX_BUF[dataAddr++] = outputDistance2;
+
+					PC_PRO_TX_BUF[dataAddr++] = 0x03;
+					PC_PRO_TX_BUF[dataAddr++] = 0x00;
+					PC_PRO_TX_BUF[dataAddr++] = tmpeData >> 8;
+					PC_PRO_TX_BUF[dataAddr++] = tmpeData;
+					PC_PRO_TX_BUF[dataAddr++] = outputDistance3;
+
+					PC_PRO_TX_BUF[dataAddr++] = 0x04;
+					PC_PRO_TX_BUF[dataAddr++] = 0x00;
+					PC_PRO_TX_BUF[dataAddr++] = tmpeData >> 8;
+					PC_PRO_TX_BUF[dataAddr++] = tmpeData;
+					PC_PRO_TX_BUF[dataAddr++] = outputDistance4;
+					break;
+					
+				default: break;
+			}
+			printf("\r\n0x62 OF = %d, %d, %d, %d\r\n",
+						 outputDistance1, outputDistance2, outputDistance3, outputDistance4);
+			break;
+			
+		case 0x63:		//�������
+			PC_PRO_TX_BUF[dataAddr++] = 0x01;												//Э��汾��
+			PC_PRO_TX_BUF[dataAddr++] = keyNum;
+			PC_PRO_TX_BUF[dataAddr++] = keyStatus;
+			break;
+			
+		case 0x64:		//���⿪��״̬���
+			PC_PRO_TX_BUF[dataAddr++] = 0x01;												//Э��汾��
+			PC_PRO_TX_BUF[dataAddr++] = 1;													//��Ӧ���ر��
+			PC_PRO_TX_BUF[dataAddr++] = humanSensingKeyStatus;
+			break;
+			
+		case 0x65:		//��������״̬���
+			PC_PRO_TX_BUF[dataAddr++] = 0x01;												//Э��汾��
+			PC_PRO_TX_BUF[dataAddr++] = 0x01;												//����������
+			PC_PRO_TX_BUF[dataAddr++] = 1;													//�������������
+			PC_PRO_TX_BUF[dataAddr++] = smokeAlarmStatus;
+			break;
+			
+		case 0x66:		//Ͷ�ſڹر�״̬���
+			PC_PRO_TX_BUF[dataAddr++] = 0x01;												//Э��汾��
+			
+			//��ʱռλ�����������ݺ�д��
+			tempAddr = dataAddr;
+			PC_PRO_TX_BUF[dataAddr++] = 0x00;												//Ͷ������
+			
+			dataCunt = 0;
+			if(dropOffPortMark1 == 1)
+			{
+				dropOffPortMark1 = 0;
+				PC_PRO_TX_BUF[dataAddr++] = 1;													//Ͷ�ڱ��
+				PC_PRO_TX_BUF[dataAddr++] = dropPortClosedStatus1;			//Ͷ�ڹر�״̬
+				
+				dataCunt++;
+			}
+			
+			if(dropOffPortMark2 == 1)
+			{
+				dropOffPortMark2 = 0;
+				PC_PRO_TX_BUF[dataAddr++] = 2;													//Ͷ�ڱ��
+				PC_PRO_TX_BUF[dataAddr++] = dropPortClosedStatus2;			//Ͷ�ڹر�״̬
+				
+				dataCunt++;
+			}
+			PC_PRO_TX_BUF[tempAddr] = dataCunt;					//�������
+			break;
+			
+		case 0x67:		//GPS��λ���
+			PC_PRO_TX_BUF[dataAddr++] = 0x01;												//Э��汾��
+			PC_PRO_TX_BUF[dataAddr++] = gpsStatus;									//��λ״̬
+			PC_PRO_TX_BUF[dataAddr++] = gpsEW;											//���ȷ���0->E-��,W-����
+			PC_PRO_TX_BUF[dataAddr++] = gpsLon >> 24;								//����
+			PC_PRO_TX_BUF[dataAddr++] = gpsLon >> 16;	
+			PC_PRO_TX_BUF[dataAddr++] = gpsLon >> 8;	
+			PC_PRO_TX_BUF[dataAddr++] = gpsLon;
+			
+			PC_PRO_TX_BUF[dataAddr++] = gpsNS;											//γ�ȷ���0->N-��,1->S-�ϣ�
+			PC_PRO_TX_BUF[dataAddr++] = gpsLat >> 24;								//γ��
+			PC_PRO_TX_BUF[dataAddr++] = gpsLat >> 16;	
+			PC_PRO_TX_BUF[dataAddr++] = gpsLat >> 8;	
+			PC_PRO_TX_BUF[dataAddr++] = gpsLat;
+			break;
+			
+		case 0x90:		//����ͬ���ź�
+			PC_PRO_TX_BUF[dataAddr++] = 0x01;												//Э��汾��
+			len = strlen("connect");
+			memcpy(&PC_PRO_TX_BUF[dataAddr], "connect", len);
+			dataAddr += len;
+			break;
+			
+		default:
+			printf("\r\nδָ֪�\r\n");
+			break;
+	}
+	
+	len = dataAddr - 4;																			//���㵱ǰͨѶ�����ݳ���
+	PC_PRO_TX_BUF[2] = (uint8_t)(len >> 8);									//����ͨѶ���ݳ������֣���8λ��
+	PC_PRO_TX_BUF[3] = (uint8_t)len;												//����ͨѶ���ݳ������֣���8λ��
+	
+	PC_ProDataPackingAndSend(PC_PRO_TX_BUF, dataAddr); 			//��ָ������������Ȼ����
+}
+
+/*
+***********************************************************************
+*	�� �� ��: PC_ProCommandSend
+*	����˵��: ��λ������λ����������ͨѶ����
+*	��    ��:	protocolNo -> Э���
+*	�� �� ֵ: ��
+***********************************************************************
+*/
+void PC_ProCommandSend(uint8_t protocolNo)
+{
+	pcCmdMsg.msgType = protocolNo;
+	MessageSend(MSG_FIFO_PC_CMD, pcCmdMsg);
+}
+
+/*
+***********************************************************************
+*	�� �� ��: PC_ProCommandSendHandler
+*	����˵��: ��λ������λ����������ͨѶ����
+*	��    ��:	protocolNo -> Э���
+*	�� �� ֵ: ��
+***********************************************************************
+*/
+static void PC_ProCommandSendHandler(void)
+{
+	static uint8_t currentStatus = 0;
+	static uint8_t nextStatus = 0;
+	
+	static MESSAGE *pMsg;
+	
+	static timer waitingTimer;
+	
+	static uint8_t timer_ok = 0;
+	if(timer_ok == 0)
+	{
+		timer_ok = 1;
+		timer_set(&waitingTimer, 2);
+	}
+	
+	currentStatus = nextStatus;
+	switch(currentStatus)
+	{
+		case 0x00:
+			pMsg = MessageGet(MSG_FIFO_PC_CMD);
+			if(pMsg)
+			{
+				PC_ProDataPacking((uint8_t)pMsg->msgType);
+				timer_restart(&waitingTimer);
+				nextStatus = 0x01;
+				break;
+			}
+			break;
+			
+		case 0x01:
+			if(timer_expired(&waitingTimer))
+			{
+				nextStatus = 0x00;
+				break;
+			}
+			break;
+			
+		default:
+			nextStatus = 0x00;
+			break;
+	}
+}
+
+/*
+***********************************************************************
+*	�� �� ��: PC_ProDecodeTask
+*	����˵��: ����λ��ͨѶЭ�鴦������
+*	��    ��:	��
+*	�� �� ֵ: ��
+***********************************************************************
+*/
+void PC_ProDecodeTask(void)
+{
+	if(USART4_RX_STA == 0xfd)													//�н��յ��������͵�����
+	{
+		PC_ProCommandRun(USART4_RX_BUF, USART4_TX_BUF); 	//���ͷ��ص�����
+		
+		memset(USART4_RX_BUF, 0x00, USART4_RECV_LEN);									//�����������
+		USART4_RX_STA = 0;
+	}
+	
+	PC_ProCommandSendHandler();
+}
+
+/******************** (C) COPYRIGHT 2017 CXHY *****END OF FILE*******************/ 
diff --git a/STM32_4路称重_Git提交精简工程/src/USER/pc_protocol.h b/STM32_4路称重_Git提交精简工程/src/USER/pc_protocol.h
new file mode 100755
index 0000000..25b9b13
--- /dev/null
+++ b/STM32_4路称重_Git提交精简工程/src/USER/pc_protocol.h
@@ -0,0 +1,16 @@
+#ifndef __PC_PROTOCOL_H
+#define __PC_PROTOCOL_H
+#include "stm32f10x.h"
+
+#define PC_PRO_RECV_LEN		256												//�����ջ����ֽ���
+#define PC_PRO_SEND_LEN		256												//����ͻ����ֽ���
+
+extern uint8_t PC_PRO_RX_BUF[PC_PRO_RECV_LEN];     	//���ջ���
+extern uint8_t PC_PRO_TX_BUF[PC_PRO_SEND_LEN];			//���ͻ���
+
+extern void PC_ProCommandSend(uint8_t protocolNo);
+void PC_ProDecodeTask(void);
+
+#endif
+
+/******************** (C) COPYRIGHT 2017 CXHY *****END OF FILE*******************/ 
diff --git a/STM32_4路称重_Git提交精简工程/src/USER/stm32f10x_conf.h b/STM32_4路称重_Git提交精简工程/src/USER/stm32f10x_conf.h
new file mode 100755
index 0000000..b17511e
--- /dev/null
+++ b/STM32_4路称重_Git提交精简工程/src/USER/stm32f10x_conf.h
@@ -0,0 +1,77 @@
+/**
+  ******************************************************************************
+  * @file    GPIO/IOToggle/stm32f10x_conf.h 
+  * @author  MCD Application Team
+  * @version V3.5.0
+  * @date    08-April-2011
+  * @brief   Library configuration file.
+  ******************************************************************************
+  * @attention
+  *
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+  *
+  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F10x_CONF_H
+#define __STM32F10x_CONF_H
+
+/* Includes ------------------------------------------------------------------*/
+/* Uncomment/Comment the line below to enable/disable peripheral header file inclusion */
+#include "stm32f10x_adc.h"
+//#include "stm32f10x_bkp.h"
+//#include "stm32f10x_can.h"
+//#include "stm32f10x_cec.h"
+//#include "stm32f10x_crc.h"
+//#include "stm32f10x_dac.h"
+#include "stm32f10x_dbgmcu.h"
+#include "stm32f10x_dma.h"
+#include "stm32f10x_exti.h"
+#include "stm32f10x_flash.h"
+#include "stm32f10x_fsmc.h"
+#include "stm32f10x_gpio.h"
+//#include "stm32f10x_i2c.h"
+#include "stm32f10x_iwdg.h"
+//#include "stm32f10x_pwr.h"
+#include "stm32f10x_rcc.h"
+#include "stm32f10x_rtc.h"
+//#include "stm32f10x_sdio.h"
+#include "stm32f10x_spi.h"
+#include "stm32f10x_tim.h"
+#include "stm32f10x_usart.h"
+//#include "stm32f10x_wwdg.h"
+#include "misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/* Uncomment the line below to expanse the "assert_param" macro in the 
+   Standard Peripheral Library drivers code */
+/* #define USE_FULL_ASSERT    1 */
+
+/* Exported macro ------------------------------------------------------------*/
+#ifdef  USE_FULL_ASSERT
+
+/**
+  * @brief  The assert_param macro is used for function's parameters check.
+  * @param  expr: If expr is false, it calls assert_failed function which reports 
+  *         the name of the source file and the source line number of the call 
+  *         that failed. If expr is true, it returns no value.
+  * @retval None
+  */
+  #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
+/* Exported functions ------------------------------------------------------- */
+  void assert_failed(uint8_t* file, uint32_t line);
+#else
+  #define assert_param(expr) ((void)0)
+#endif /* USE_FULL_ASSERT */
+
+#endif /* __STM32F10x_CONF_H */
+
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/STM32_4路称重_Git提交精简工程/src/USER/stm32f10x_it.c b/STM32_4路称重_Git提交精简工程/src/USER/stm32f10x_it.c
new file mode 100755
index 0000000..9b62a24
--- /dev/null
+++ b/STM32_4路称重_Git提交精简工程/src/USER/stm32f10x_it.c
@@ -0,0 +1,87 @@
+/**
+  ******************************************************************************
+  * @file    GPIO/IOToggle/stm32f10x_it.c 
+  * @author  MCD Application Team
+  * @version V3.5.0
+  * @date    08-April-2011
+  * @brief   Main Interrupt Service Routines.
+  *          This file provides template for all exceptions handler and peripherals
+  *          interrupt service routine.
+  ******************************************************************************
+  * @attention
+  *
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+  *
+  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x_it.h" 
+
+
+ 
+void NMI_Handler(void)
+{
+}
+ 
+void HardFault_Handler(void)
+{
+  /* Go to infinite loop when Hard Fault exception occurs */
+  while (1)
+  {
+  }
+}
+ 
+void MemManage_Handler(void)
+{
+  /* Go to infinite loop when Memory Manage exception occurs */
+  while (1)
+  {
+  }
+}
+
+ 
+void BusFault_Handler(void)
+{
+  /* Go to infinite loop when Bus Fault exception occurs */
+  while (1)
+  {
+  }
+}
+ 
+void UsageFault_Handler(void)
+{
+  /* Go to infinite loop when Usage Fault exception occurs */
+  while (1)
+  {
+  }
+}
+ 
+void SVC_Handler(void)
+{
+}
+ 
+void DebugMon_Handler(void)
+{
+}
+ 
+void PendSV_Handler(void)
+{
+}
+ 
+void SysTick_Handler(void)
+{
+}
+
+/******************************************************************************/
+/*                 STM32F10x Peripherals Interrupt Handlers                   */
+/*  Add here the Interrupt Handler for the used peripheral(s) (PPP), for the  */
+/*  available peripheral interrupt handler's name please refer to the startup */
+/*  file (startup_stm32f10x_xx.s).                                            */
+/******************************************************************************/
diff --git a/STM32_4路称重_Git提交精简工程/src/USER/stm32f10x_it.h b/STM32_4路称重_Git提交精简工程/src/USER/stm32f10x_it.h
new file mode 100755
index 0000000..696633d
--- /dev/null
+++ b/STM32_4路称重_Git提交精简工程/src/USER/stm32f10x_it.h
@@ -0,0 +1,46 @@
+/**
+  ******************************************************************************
+  * @file    GPIO/IOToggle/stm32f10x_it.h 
+  * @author  MCD Application Team
+  * @version V3.5.0
+  * @date    08-April-2011
+  * @brief   This file contains the headers of the interrupt handlers.
+  ******************************************************************************
+  * @attention
+  *
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+  *
+  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F10x_IT_H
+#define __STM32F10x_IT_H
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x.h"
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions ------------------------------------------------------- */
+
+void NMI_Handler(void);
+void HardFault_Handler(void);
+void MemManage_Handler(void);
+void BusFault_Handler(void);
+void UsageFault_Handler(void);
+void SVC_Handler(void);
+void DebugMon_Handler(void);
+void PendSV_Handler(void);
+void SysTick_Handler(void);
+
+#endif /* __STM32F10x_IT_H */
+
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/STM32_4路称重_Git提交精简工程/src/USER/tcp_protocol.c b/STM32_4路称重_Git提交精简工程/src/USER/tcp_protocol.c
new file mode 100755
index 0000000..262ccb4
--- /dev/null
+++ b/STM32_4路称重_Git提交精简工程/src/USER/tcp_protocol.c
@@ -0,0 +1,1381 @@
+/*************************** (C) COPYRIGHT 2017 CXHY ****************************
+ * �ļ���  ��protocol.c
+ * ��  ��  ��Э�鴦������
+ * ��  ��  ��V1.0
+ * ��  ��  ��XuZhongPing
+ * ��  ��  ��2017/03/16 
+*********************************************************************************/
+#include "tcp_protocol.h"
+#include "delay.h"
+#include "usart1.h"
+#include "usart2.h"
+#include "usart3.h"
+#include "message.h"
+#include "string.h"
+#include "stdlib.h"  
+#include "data_typedef.h"	
+#include "device.h"
+
+
+protocol_TypeDef userInfoQuery;				//�û���Ϣ��ѯָ��
+protocol_TypeDef tradingDataUpload;		//��Ʒ���������ϴ�����ѯ�Ƿ���Գ���
+
+uint16_t dataLength = 0;							//һ֡���ݵĳ���
+uint16_t operateType = 0;							//���̨������������ָ������
+uint16_t sendOrderCode = 0x00;				//���̨���͵�Э��ָ����	
+uint16_t recreceiveOrderCode = 0;			//���յ���̨�·���Э��ָ����
+uint8_t  TCP_recreceiveStatus = 0;		//TCP���ݽ��ձ�־��1Ϊ���յ�TCP���ݣ�0��
+
+/*
+***********************************************************************
+*	�� �� ��: ProtocolInit
+*	����˵��: Э�������ʼ��
+*	��    �Σ�	          
+*	�� �� ֵ: 
+***********************************************************************
+*/
+void ProtocolInit(void)
+{
+	memset(GPRS_DATA_BUF, 0x00, GPRS_MAX_SEND_LEN);
+	
+	//��λ�����̨������ͨѶָ��
+	userInfoQuery.protocolCode = 4002;
+	userInfoQuery.parseState = 0;
+	
+	tradingDataUpload.protocolCode = 4016;
+	tradingDataUpload.parseState = 0;
+	
+	//���Ż�����λ������λ��ͨѶָ��
+// 	VM_ProtocolInit();
+}
+
+/*
+***********************************************************************
+*	�� �� ��: CRC_Check
+*	����˵��: �������λ
+*	��    �Σ���
+*	�� �� ֵ: ��
+***********************************************************************
+*/
+static uint8_t CRC_Check(uint8_t *pData, uint16_t len)
+{
+	uint8_t crc;
+	uint16_t i;
+	//CRCУ����
+	crc = *pData;
+	for(i = 0; i < len-1; i++)
+	{
+		crc ^= *(++pData);
+	}
+	return crc;
+}
+
+/*
+***********************************************************************
+*	�� �� ��: ShowUploadData
+*	����˵��: ��ʾ�������ϴ�Ͷ������
+*	��    �Σ���
+*	�� �� ֵ: ��
+***********************************************************************
+*/
+static void ShowUploadData(uint8_t type, uint16_t inputVal, uint8_t inputDistance)
+{
+	switch(type)
+	{
+		case PAPER:
+			printf("\r\n�ϴ�ֽ������ = %2.2f Kg�� ���� = %d cm\r\n", (float)inputVal/100, inputDistance);	
+			break;
+			
+		case PLASTIC:
+			printf("\r\n�ϴ��������� = %2.2f Kg�� ���� = %d cm\r\n", (float)inputVal/100, inputDistance);
+			break;
+			
+		case GLASS:
+			printf("\r\n�ϴ��������� = %2.2f Kg�� ���� = %d cm\r\n", (float)inputVal/100, inputDistance);	
+			break;
+			
+		case METAL:
+			printf("\r\n�ϴ��������� = %2.2f Kg�� ���� = %d cm\r\n", (float)inputVal/100, inputDistance);
+			break;
+			
+		case RECYCLED:
+			printf("\r\n�ϴ��ɻ��������� = %2.2f Kg�� ���� = %d cm\r\n", (float)inputVal/100, inputDistance);
+			break;
+			
+		case KITCHEN:
+			printf("\r\n�ϴ��������� = %2.2f Kg�� ���� = %d cm\r\n", (float)inputVal/100, inputDistance);
+			break;
+			
+		case SMALL_BOTTLE:
+			printf("\r\n�ϴ�С����ƿ������ = %d ���� ���� = %d cm\r\n", inputVal, inputDistance);
+			break;
+			
+		case BIG_BOTTLE:
+			printf("\r\n�ϴ�������ƿ������ = %d ���� ���� = %d cm\r\n", inputVal, inputDistance);
+			break;
+			
+		case CANS:
+			printf("\r\n�ϴ����������� = %d ���� ���� = %d cm\r\n", inputVal, inputDistance);
+			break;
+			
+		case BATTERY:
+			printf("\r\n�ϴ�������� = %d ���� ���� = %d cm\r\n", inputVal, inputDistance);
+			break;
+			
+		case FABRIC:
+			printf("\r\n�ϴ�֯������ = %2.2f Kg�� ���� = %d cm\r\n", (float)inputVal/100, inputDistance);
+			break;
+			
+		case BOOK:
+			printf("\r\n�ϴ��鱾���� = %2.2f Kg�� ���� = %d cm\r\n", (float)inputVal/100, inputDistance);
+			break;
+			
+		case NEWSPAPER:
+			printf("\r\n�ϴ���ֽ���� = %2.2f Kg�� ���� = %d cm\r\n", (float)inputVal/100, inputDistance);
+			break;
+			
+		case KITCHEN_1:
+			printf("\r\n�ϴ�����1���� = %2.2f Kg�� ���� = %d cm\r\n", (float)inputVal/100, inputDistance);	
+			break;
+			
+		case KITCHEN_2:
+			printf("\r\n�ϴ�����2���� = %2.2f Kg�� ���� = %d cm\r\n", (float)inputVal/100, inputDistance);	
+			break;
+			
+		case PLASTIC_2:
+			printf("\r\n�ϴ�����2���� = %2.2f Kg�� ���� = %d cm\r\n", (float)inputVal/100, inputDistance);	
+			break;
+			
+		case OTHER:
+			printf("\r\n�ϴ��������� = %2.2f Kg�� ���� = %d cm\r\n", (float)inputVal/100, inputDistance);	
+			break;
+		
+		default:
+			break;
+	}
+}
+
+/*
+***********************************************************************
+*	�� �� ��: ShowDeviceRunningStatus
+*	����˵��: ��ʾ�ϴ��豸����״̬��Ϣ
+*	��    �Σ���
+*	�� �� ֵ: ��
+***********************************************************************
+*/
+static void ShowDeviceRunningStatus(uint8_t type, uint8_t inputDistance)
+{	
+	switch(type)
+	{
+		case PAPER:
+			printf(" ֽ�� = %3.1f cm ", (float)inputDistance);	
+			break;
+			
+		case PLASTIC:
+			printf(" ���� = %3.1f cm ", (float)inputDistance);	
+			break;
+			
+		case GLASS:
+			printf(" ���� = %3.1f cm ", (float)inputDistance);		
+			break;
+			
+		case METAL:
+			printf(" ���� = %3.1f cm ", (float)inputDistance);	
+			break;
+			
+		case RECYCLED:
+			printf(" �ɻ����� = %3.1f cm ", (float)inputDistance);	
+			break;
+			
+		case KITCHEN:
+			printf(" ���� = %3.1f cm ", (float)inputDistance);	
+			break;
+			
+		case SMALL_BOTTLE:
+			printf(" С����ƿ�� = %3.1f cm ", (float)inputDistance);	
+			break;
+			
+		case BIG_BOTTLE:
+			printf(" ������ƿ�� = %3.1f cm ", (float)inputDistance);	
+			break;
+			
+		case CANS:
+			printf(" ������ = %3.1f cm ", (float)inputDistance);	
+			break;
+			
+		case BATTERY:
+			printf(" ��� = %3.1f cm ", (float)inputDistance);	
+			break;
+			
+		case FABRIC:
+			printf(" ֯�� = %3.1f cm ", (float)inputDistance);	
+			break;
+			
+		case BOOK:
+			printf(" �鱾 = %3.1f cm ", (float)inputDistance);	
+			break;
+			
+		case NEWSPAPER:
+			printf(" ��ֽ = %3.1f cm ", (float)inputDistance);	
+			break;
+			
+		case KITCHEN_1:
+			printf(" ����1 = %3.1f cm ", (float)inputDistance);		
+			break;
+			
+		case KITCHEN_2:
+			printf(" ����2 = %3.1f cm ", (float)inputDistance);		
+			break;
+			
+		case PLASTIC_2:
+			printf(" ����2 = %3.1f cm ", (float)inputDistance);		
+			break;
+			
+		case OTHER:
+			printf(" ����2 = %3.1f cm ", (float)inputDistance);		
+			break;
+			
+		default:
+			break;
+	}
+}
+
+/*
+***********************************************************************
+*	�� �� ��: ShowUploadAllData
+*	����˵��: ��ʾ�������ϴ�Ͷ�����ݣ���������ǰ�����ݣ�
+*	��    �Σ���
+*	�� �� ֵ: ��
+***********************************************************************
+*/
+static void ShowUploadAllData(uint8_t type, uint16_t inputVal, uint8_t inputDistance, uint16_t beforeVal, uint16_t afterVal)
+{
+	switch(type)
+	{
+		case PAPER:
+			printf("\r\n�ϴ�ֽ��");	
+			break;
+			
+		case PLASTIC:
+			printf("\r\n�ϴ�����");
+			break;
+			
+		case GLASS:
+			printf("\r\n�ϴ�����");	
+			break;
+			
+		case METAL:
+			printf("\r\n�ϴ�����");
+			break;
+			
+		case RECYCLED:
+			printf("\r\n�ϴ��ɻ�����");
+			break;
+			
+		case KITCHEN:
+			printf("\r\n�ϴ�����");
+			break;
+			
+		case SMALL_BOTTLE:
+			printf("\r\n�ϴ�С����ƿ������ = %d ���� ���� = %d cm\r\n", inputVal, inputDistance);
+			break;
+			
+		case BIG_BOTTLE:
+			printf("\r\n�ϴ�������ƿ������ = %d ���� ���� = %d cm\r\n", inputVal, inputDistance);
+			break;
+			
+		case CANS:
+			printf("\r\n�ϴ�������");
+			break;
+			
+		case BATTERY:
+			printf("\r\n�ϴ����");
+			break;
+			
+		case FABRIC:
+			printf("\r\n�ϴ�֯��");
+			break;
+			
+		case BOOK:
+			printf("\r\n�ϴ��鱾");
+			break;
+			
+		case NEWSPAPER:
+			printf("\r\n�ϴ���ֽ");
+			break;
+			
+		case KITCHEN_1:
+			printf("\r\n�ϴ�����1");	
+			break;
+			
+		case KITCHEN_2:
+			printf("\r\n�ϴ�����2");	
+			break;
+			
+		case PLASTIC_2:
+			printf("\r\n�ϴ�����2");	
+
+			break;
+			
+		case OTHER:
+			printf("\r\n�ϴ�����");	
+
+			break;
+	}
+	
+	printf(": %2.2f Kg��%2.2f Kg -> %2.2f Kg�����룺%3.1f cm\r\n",\
+				(float)inputVal/100, (float)beforeVal/100, (float)afterVal/100, (float)inputDistance);
+}
+
+/*
+***********************************************************************
+*	�� �� ��: ProtocolPackaging
+*	����˵��: ����Э������������
+*	��    �Σ���
+*	�� �� ֵ: ��
+***********************************************************************
+*/
+uint16_t SendProtocolPackaging(uint16_t proNum)
+{
+	uint16_t proLen = 0;									//������Э���ܳ���
+	uint16_t dataLen = 0;									//���͵����ݳ���
+	uint8_t crc;
+	uint16_t tmpeData;
+	uint8_t transformPutInType = 0;
+	
+	uint8_t len = 0;
+	
+	static uint16_t serial_number = 0;		//Э����ˮ��
+	
+	//֡ͷ
+	GPRS_DATA_BUF[0] = 0x48;
+	GPRS_DATA_BUF[1] = 0x45;
+	GPRS_DATA_BUF[2] = 0x52;
+	GPRS_DATA_BUF[3] = 0x4F;
+	proLen += 4;
+	
+	//2�ֽ����ݳ��ȣ�����������ɺ�����
+// 	GPRS_DATA_BUF[proLen++] = (uint8_t)(dataLen >> 8);
+// 	GPRS_DATA_BUF[proLen++] = (uint8_t)dataLen;
+	
+	proLen += 2;		//2�ֽ����ڱ������ݳ���
+	//�豸��
+	memcpy(&GPRS_DATA_BUF[proLen], gsm_msg.IMEI_HEX, 8);
+	proLen += 8;
+	
+	//ָ�����
+	GPRS_DATA_BUF[proLen++] = (uint8_t)(proNum >> 8);
+	GPRS_DATA_BUF[proLen++] = (uint8_t)proNum;
+	
+	//���ط��͵����ݼ������ݳ���
+	switch(proNum)
+	{
+		case 1001:		//�ϴ�����
+			GPRS_DATA_BUF[proLen++] = 1;												//�豸���ͣ�1�������䣻2�����Ż���3:POS����
+			break;
+			
+		case 1003:		//�豸Ӳ����Ϣ�ϴ�
+			GPRS_DATA_BUF[proLen++] = 0;												//Э��汾��
+			GPRS_DATA_BUF[proLen++] = 1;
+			
+			GPRS_DATA_BUF[proLen++] = 1;												//�豸���ͣ�1�������䣻2�����Ż���3:POS����
+			
+			len = strlen(VersionNumber);
+			GPRS_DATA_BUF[proLen++] = len;											//Ӳ���汾�ų���
+			memcpy(&GPRS_DATA_BUF[proLen], VersionNumber, len);	//Ӳ���汾��
+			proLen += len;
+			
+			len = strlen((const char*)deviceIdBuf);
+			GPRS_DATA_BUF[proLen++] = len;											//�豸��ų���
+			memcpy(&GPRS_DATA_BUF[proLen], deviceIdBuf, len);		//�豸���
+			proLen += len;
+			
+			memcpy(&GPRS_DATA_BUF[proLen], gsm_msg.ICCID, 20);	//SIM��ICCID��
+			proLen += 20;
+			
+			switch(deviceType)
+			{
+				case THREE_CLASSIFICATION:		//������
+					GPRS_DATA_BUF[proLen++] = 0;												//�豸�ͺű���
+					GPRS_DATA_BUF[proLen++] = deviceType;
+					
+					GPRS_DATA_BUF[proLen++] = 3;												//Ͷ������
+					
+					GPRS_DATA_BUF[proLen++] = devChannel1Type >> 8;			//Ͷ���������ͣ���ǰ����Ϊ8λ��
+					GPRS_DATA_BUF[proLen++] = devChannel1Type;
+					GPRS_DATA_BUF[proLen++] = 1;												//Ͷ���ͺ�
+					
+					GPRS_DATA_BUF[proLen++] = devChannel2Type >> 8;
+					GPRS_DATA_BUF[proLen++] = devChannel2Type;
+					GPRS_DATA_BUF[proLen++] = 1;
+					
+					GPRS_DATA_BUF[proLen++] = devChannel3Type >> 8;
+					GPRS_DATA_BUF[proLen++] = devChannel3Type;
+					GPRS_DATA_BUF[proLen++] = 1;
+					break;
+					
+				case FOUR_CLASSIFICATION:		//�ķ���
+					GPRS_DATA_BUF[proLen++] = 0;												//�豸�ͺű���
+					GPRS_DATA_BUF[proLen++] = deviceType;
+					
+					GPRS_DATA_BUF[proLen++] = 4;												//Ͷ������
+					
+					GPRS_DATA_BUF[proLen++] = devChannel1Type >> 8;			//Ͷ���������ͣ���ǰ����Ϊ8λ��
+					GPRS_DATA_BUF[proLen++] = devChannel1Type;
+					GPRS_DATA_BUF[proLen++] = 1;												//Ͷ���ͺ�
+					
+					GPRS_DATA_BUF[proLen++] = devChannel2Type >> 8;
+					GPRS_DATA_BUF[proLen++] = devChannel2Type;
+					GPRS_DATA_BUF[proLen++] = 1;
+					
+					GPRS_DATA_BUF[proLen++] = devChannel3Type >> 8;
+					GPRS_DATA_BUF[proLen++] = devChannel3Type;
+					GPRS_DATA_BUF[proLen++] = 1;
+					
+					GPRS_DATA_BUF[proLen++] = devChannel4Type >> 8;
+					GPRS_DATA_BUF[proLen++] = devChannel4Type;
+					GPRS_DATA_BUF[proLen++] = 1;
+					break;
+			
+			}
+			
+			GPRS_DATA_BUF[proLen++] = 0;												//
+			GPRS_DATA_BUF[proLen++] = 0;
+			GPRS_DATA_BUF[proLen++] = 0;
+			GPRS_DATA_BUF[proLen++] = 0;
+			GPRS_DATA_BUF[proLen++] = 0;
+			GPRS_DATA_BUF[proLen++] = 0;
+			GPRS_DATA_BUF[proLen++] = 0;
+			GPRS_DATA_BUF[proLen++] = 0;
+			
+			printf("\r\n�����汾: %s, len: %d\r\n", VersionNumber, strlen(VersionNumber));
+			printf("\r\n�豸���: %s, len: %d\r\n", deviceIdBuf, strlen((const char*)deviceIdBuf));
+			printf("\r\nICCID��: %s\r\n", gsm_msg.ICCID);
+			
+			break;
+			
+		case 4001:		//��ȡ�û���Ϣ			
+		case 4011:		//��ȡ�û���Ϣ��������Ϣ������������ά�룩ǰ�ڵ�Э����һ����Ŀ���ϴ��ظ���,��4401����
+		case 4201:		//��ȡ�û���Ϣ����POS����Ȩ���ƿ���Ͷ�Ŵ�����������Ϣ������������ά�룩
+		case 4401:		//�滻4011��������Ϣ������������ά�룬���ڴ�ӡ���������
+			if(sendPutInType == 0x05)														//��ά����ֽ����
+			{
+				transformPutInType = 0x04;												//ʹ����������ά���ѯ�û���Ϣ������Ϊ0x04
+			}else{
+				transformPutInType = sendPutInType;
+			}
+			GPRS_DATA_BUF[proLen++] = transformPutInType;				//����ʶ��ʽ
+			GPRS_DATA_BUF[proLen++] = sendDataLength;						//����������Ϣ�ĳ���
+			memcpy(&GPRS_DATA_BUF[proLen], sendDataBuf, 33);		//����������Ϣ
+			proLen += 33;
+			
+			printf("\r\n�û����ݲ�ѯ:");	
+			printf("\r\n--> Type: %d", sendPutInType);
+			printf("\r\n--> Len: %d", sendDataLength);
+			if(getPutInType == 1)
+			{
+				printf("\r\n--> Data: ");
+				show(sendDataBuf, sendDataLength);
+			}else{
+				printf("\r\n--> Data: %s\r\n", sendDataBuf);
+			}
+			break;
+		
+		case 4301:		//���ڷ���������Ƿ��ܴ�Ͷ�ſ���
+			GPRS_DATA_BUF[proLen++] = 1;												//�豸���ͣ�1�������䣻2�����Ż���3:POS����
+			if(sendPutInType == 0x05)														//��ά����ֽ����
+			{
+				transformPutInType = 0x04;												//ʹ����������ά���ѯ�û���Ϣ������Ϊ0x04
+			}else{
+				transformPutInType = sendPutInType;
+			}
+			GPRS_DATA_BUF[proLen++] = transformPutInType;				//����ʶ��ʽ
+			GPRS_DATA_BUF[proLen++] = sendDataLength;						//����������Ϣ�ĳ���
+			memcpy(&GPRS_DATA_BUF[proLen], sendDataBuf, 33);		//����������Ϣ
+			proLen += 33;
+			
+			printf("\r\n�û����ݲ�ѯ:");	
+			printf("\r\n--> Type: %d", sendPutInType);
+			printf("\r\n--> Len: %d", sendDataLength);
+			if(getPutInType == 1)
+			{
+				printf("\r\n--> Data: ");
+				show(sendDataBuf, sendDataLength);
+			}else{
+				printf("\r\n--> Data: %s\r\n", sendDataBuf);
+			}
+// 			show(sendDataBuf, 33);
+			break;
+			
+		case 4701:		//���������ϴ�
+			GPRS_DATA_BUF[proLen++] = collectorSendAuthType;							//����ʶ��ʽ
+			GPRS_DATA_BUF[proLen++] = collectorSendDataLength;						//����������Ϣ�ĳ���
+			memcpy(&GPRS_DATA_BUF[proLen], collectorSendDataBuf, 33);							//����������Ϣ
+			proLen += 33;
+// 			printf("\r\ntype��%d\r\n", sendPutInType);
+// 			printf("\r\nlen��%d\r\n", sendDataLength);
+// 			printf("\r\ndata��%s\r\n", sendDataBuf);
+			
+// 			show(GPRS_DATA_BUF, proLen);
+			
+// 			show(sendDataBuf, 33);
+			break;
+			
+		case 4801:		//����Ͷ���ϴ�
+			GPRS_DATA_BUF[proLen++] = sendPutInType;						//����ʶ��ʽ
+			GPRS_DATA_BUF[proLen++] = sendDataLength;						//����������Ϣ�ĳ���
+			memcpy(&GPRS_DATA_BUF[proLen], sendDataBuf, 33);		//����������Ϣ
+			proLen += 33;
+			
+			switch(deviceType)
+			{
+				case DOUBLE_CLASSIFICATION:		//˫Ͱ480L
+					//������ͰͶ���ϴ�����
+					GPRS_DATA_BUF[proLen++] = leftBarrelType;						//�������ͣ������ࣩ
+					
+					GPRS_DATA_BUF[proLen++] = exceptionWeight1 >> 8;				//������8λ
+					GPRS_DATA_BUF[proLen++] = exceptionWeight1;
+				
+					GPRS_DATA_BUF[proLen++] = exceptionWeightBefore1 >> 8;			//Ͷ��ǰͰ��������
+					GPRS_DATA_BUF[proLen++] = exceptionWeightBefore1;
+					GPRS_DATA_BUF[proLen++] = exceptionWeightAfter1 >> 8;				//Ͷ�ź�Ͱ��������
+					GPRS_DATA_BUF[proLen++] = exceptionWeightAfter1;
+					
+					ShowUploadAllData(leftBarrelType, exceptionWeight1, getDistance1, exceptionWeightBefore1, exceptionWeightAfter1);
+					
+					//������ͰͶ���ϴ�����
+					GPRS_DATA_BUF[proLen++] = rightBarrelType;											//�������ͣ�������
+					
+					GPRS_DATA_BUF[proLen++] = exceptionWeight2 >> 8;				//������8λ
+					GPRS_DATA_BUF[proLen++] = exceptionWeight2;
+					
+					GPRS_DATA_BUF[proLen++] = exceptionWeightBefore2 >> 8;				//Ͷ��ǰͰ��������
+					GPRS_DATA_BUF[proLen++] = exceptionWeightBefore2;
+					GPRS_DATA_BUF[proLen++] = exceptionWeightAfter2 >> 8;				//Ͷ�ź�Ͱ��������
+					GPRS_DATA_BUF[proLen++] = exceptionWeightAfter2;
+					
+					ShowUploadAllData(rightBarrelType, exceptionWeight2, getDistance2, exceptionWeightBefore2, exceptionWeightAfter2);
+					break;
+					
+				case DOUBLE_CLASSIFICATION_BOTTLE:		//˫Ͱ480L��ƿ��	
+					//������ͰͶ���ϴ�����
+					GPRS_DATA_BUF[proLen++] = leftBarrelType;						//�ɻ���������
+					
+					//ƿ����ʱδ�����쳣���
+					smallBottleCount = 0;
+				
+					GPRS_DATA_BUF[proLen++] = smallBottleCount >> 8;		//С����ƿ��������8λ��
+					GPRS_DATA_BUF[proLen++] = smallBottleCount;					//С����ƿ��������8λ��
+					
+					GPRS_DATA_BUF[proLen++] = 0;												//Ͷ��ǰͰ��������
+					GPRS_DATA_BUF[proLen++] = 0;
+					GPRS_DATA_BUF[proLen++] = 0;												//Ͷ�ź�Ͱ��������
+					GPRS_DATA_BUF[proLen++] = 0;
+					
+					ShowUploadAllData(leftBarrelType, smallBottleCount, getDistance1, 0, 0);
+					
+					//������ͰͶ���ϴ�����
+					GPRS_DATA_BUF[proLen++] = rightBarrelType;					//��������
+					
+					GPRS_DATA_BUF[proLen++] = exceptionWeight2 >> 8;					//������8λ
+					GPRS_DATA_BUF[proLen++] = exceptionWeight2;
+					
+					GPRS_DATA_BUF[proLen++] = exceptionWeightBefore2 >> 8;			//Ͷ��ǰͰ��������
+					GPRS_DATA_BUF[proLen++] = exceptionWeightBefore2;
+					GPRS_DATA_BUF[proLen++] = exceptionWeightAfter2 >> 8;				//Ͷ�ź�Ͱ��������
+					GPRS_DATA_BUF[proLen++] = exceptionWeightAfter2;
+					
+					ShowUploadAllData(rightBarrelType, exceptionWeight2, getDistance2, exceptionWeightBefore2, exceptionWeightAfter2);
+					break;
+					
+				case SINGLE_CLASSIFICATION:		//��Ͱ660L
+					//������ͰͶ���ϴ�����
+					GPRS_DATA_BUF[proLen++] = leftBarrelType;						//��������
+
+					GPRS_DATA_BUF[proLen++] = exceptionWeight1 >> 8;					//������8λ
+					GPRS_DATA_BUF[proLen++] = exceptionWeight1;
+					
+					GPRS_DATA_BUF[proLen++] = exceptionWeightBefore1 >> 8;			//Ͷ��ǰͰ��������
+					GPRS_DATA_BUF[proLen++] = exceptionWeightBefore1;
+					GPRS_DATA_BUF[proLen++] = exceptionWeightAfter1 >> 8;				//Ͷ�ź�Ͱ��������
+					GPRS_DATA_BUF[proLen++] = exceptionWeightAfter1;
+					
+					ShowUploadAllData(leftBarrelType, exceptionWeight1, getDistance1, exceptionWeightBefore1, exceptionWeightAfter1);
+					break;
+					
+				default:
+					break;
+			}					
+			break;
+		
+		case 6001:		//�ϴ�Ͷ������ 
+			GPRS_DATA_BUF[proLen++] = sendPutInType;						//����ʶ��ʽ
+			GPRS_DATA_BUF[proLen++] = sendDataLength;						//����������Ϣ�ĳ���
+			memcpy(&GPRS_DATA_BUF[proLen], sendDataBuf, 33);		//����������Ϣ
+			proLen += 33;
+			
+			printf("\r\nsendUserData:");
+			show(sendDataBuf, 33);
+			
+			switch(deviceType)
+			{
+				case DOUBLE_CLASSIFICATION:		//˫Ͱ480L
+					//������Ͱ�ϴ�Ͷ������
+					GPRS_DATA_BUF[proLen++] = leftBarrelType;						//��������
+					
+					GPRS_DATA_BUF[proLen++] = getWeight1 >> 8;					//������8λ
+					GPRS_DATA_BUF[proLen++] = getWeight1;
+					
+					GPRS_DATA_BUF[proLen++] = getDistance1;							//���ֵ
+					
+					ShowUploadData(leftBarrelType, getWeight1, getDistance1);		//��ʾ�ϴ�����Ϣ
+					
+					//������Ͱ�ϴ�Ͷ������
+					GPRS_DATA_BUF[proLen++] = rightBarrelType;					//��������
+					
+					GPRS_DATA_BUF[proLen++] = getWeight2 >> 8;					//������8λ
+					GPRS_DATA_BUF[proLen++] = getWeight2;	
+					
+					GPRS_DATA_BUF[proLen++] = getDistance2;							//���ֵ
+					
+					ShowUploadData(rightBarrelType, getWeight2, getDistance2);		//��ʾ�ϴ�����Ϣ
+					break;
+					
+				case DOUBLE_CLASSIFICATION_BOTTLE:		//˫Ͱ480L��ƿ��	
+					//������Ͱ�ϴ�Ͷ������
+					GPRS_DATA_BUF[proLen++] = leftBarrelType;						//�ɻ���������
+					
+					GPRS_DATA_BUF[proLen++] = smallBottleCount >> 8;		//С����ƿ��������8λ��
+					GPRS_DATA_BUF[proLen++] = smallBottleCount;					//С����ƿ��������8λ��
+					
+					GPRS_DATA_BUF[proLen++] = getDistance1;							//���ֵ
+					
+					ShowUploadData(leftBarrelType, smallBottleCount, getDistance1);		//��ʾ�ϴ�����Ϣ	
+					
+					//������Ͱ�ϴ�Ͷ������
+					GPRS_DATA_BUF[proLen++] = rightBarrelType;					//��������
+					
+					GPRS_DATA_BUF[proLen++] = getWeight2 >> 8;			//������8λ
+					GPRS_DATA_BUF[proLen++] = getWeight2;
+					
+					GPRS_DATA_BUF[proLen++] = getDistance2;					//���ֵ
+					
+					ShowUploadData(rightBarrelType, getWeight2, getDistance2);		//��ʾ�ϴ�����Ϣ
+					break;
+					
+				case SINGLE_CLASSIFICATION:		//��Ͱ660L	
+					//����Ͱ�ϴ�Ͷ������
+					GPRS_DATA_BUF[proLen++] = leftBarrelType;						//�������ͣ�ֽ�ࣩ
+
+					GPRS_DATA_BUF[proLen++] = getWeight1 >> 8;				//������8λ
+					GPRS_DATA_BUF[proLen++] = getWeight1;
+	
+					GPRS_DATA_BUF[proLen++] = getDistance1;						//���ֵ
+					
+					ShowUploadData(leftBarrelType, getWeight1, getDistance1);		//��ʾ�ϴ�����Ϣ
+					break;
+					
+				default:
+					break;
+			}
+			
+			//Ԥ���ֶ�
+			GPRS_DATA_BUF[proLen++] = 0x00;		
+			GPRS_DATA_BUF[proLen++] = 0x00;			
+			GPRS_DATA_BUF[proLen++] = 0x00;
+			GPRS_DATA_BUF[proLen++] = 0x00;
+					
+			break;
+
+//-----------------------------�ϴ��豸����״̬��Ϣ���¶ȡ��źš���ࣩ---------------------------------			
+		case 6004:		//�ϴ��豸����״̬��Ϣ���¶ȡ��źš���ࣩ
+			GPRS_DATA_BUF[proLen++] = 0x00;											//�����¶ȱ�ʾλ
+			tmpeData = temperature*10;
+			GPRS_DATA_BUF[proLen++] = tmpeData >> 8;						//�¶ȸ�8λ
+			GPRS_DATA_BUF[proLen++] = tmpeData;									//�¶ȵ�8λ
+			
+			GPRS_DATA_BUF[proLen++] = signal;										//GSM�ź�
+			
+			switch(deviceType)
+			{
+				case DOUBLE_CLASSIFICATION:		//˫Ͱ480L
+					//������Ͱ�ϴ��豸����״̬��Ϣ
+					GPRS_DATA_BUF[proLen++] = leftBarrelType;					//��������			
+					GPRS_DATA_BUF[proLen++] = getDistance1;						//���ֵ			
+					
+					//������Ͱ�ϴ��豸����״̬��Ϣ
+					GPRS_DATA_BUF[proLen++] = rightBarrelType;				//��������	
+					GPRS_DATA_BUF[proLen++] = getDistance2;						//���ֵ
+					
+					printf("\r\n-----> �ϴ��豸����״̬Ϊ��\r\n");	
+					printf("\r\n�¶� = %2.1f ��, ", (float)temperature);
+					printf("�ź� = %d \r\n", signal);
+					printf("\r\n��ࣨ");	
+					ShowDeviceRunningStatus(leftBarrelType, getDistance1);
+					ShowDeviceRunningStatus(rightBarrelType, getDistance2);
+					printf("��\r\n");	
+					break;
+					
+				case DOUBLE_CLASSIFICATION_BOTTLE:		//˫Ͱ480L��ƿ��	
+					//������Ͱ�ϴ��豸����״̬��Ϣ
+					GPRS_DATA_BUF[proLen++] = leftBarrelType;				//��������			
+					GPRS_DATA_BUF[proLen++] = getDistance1;					//���ֵ			
+					
+					//������Ͱ�ϴ��豸����״̬��Ϣ
+					GPRS_DATA_BUF[proLen++] = rightBarrelType;			//��������
+					GPRS_DATA_BUF[proLen++] = getDistance2;					//���ֵ
+					
+					printf("\r\n-----> �ϴ��豸����״̬Ϊ��\r\n");	
+					printf("\r\n�¶� = %2.1f ��, ", (float)temperature);
+					printf("�ź� = %d \r\n", signal);
+					printf("\r\n��ࣨ");	
+					ShowDeviceRunningStatus(leftBarrelType, getDistance1);
+					ShowDeviceRunningStatus(rightBarrelType, getDistance2);
+					printf("��\r\n");	
+					break;
+					
+				case SINGLE_CLASSIFICATION:		//��Ͱ660L
+					//������Ͱ�ϴ��豸����״̬��Ϣ
+					GPRS_DATA_BUF[proLen++] = leftBarrelType;						//��������			
+					GPRS_DATA_BUF[proLen++] = getDistance1;							//���ֵ			
+					
+					printf("\r\n-----> �ϴ��豸����״̬Ϊ��\r\n");	
+					printf("\r\n�¶� = %2.1f ��, ", (float)temperature);
+					printf("�ź� = %d \r\n", signal);
+					printf("\r\n��ࣨ");	
+					ShowDeviceRunningStatus(leftBarrelType, getDistance1);
+					printf("��\r\n");						
+					break;
+					
+				case THREE_CLASSIFICATION:		//������
+					//���ص�1ͨ��Ͷ������
+					GPRS_DATA_BUF[proLen++] = devChannel1Type;						//��������
+					GPRS_DATA_BUF[proLen++] = getDistance1;								//���ֵ
+					
+					//���ص�2ͨ��Ͷ������
+					GPRS_DATA_BUF[proLen++] = devChannel2Type;						//��������
+					GPRS_DATA_BUF[proLen++] = getDistance2;								//���ֵ
+					
+					//���ص�3ͨ��Ͷ������
+					GPRS_DATA_BUF[proLen++] = devChannel3Type;						//��������
+					GPRS_DATA_BUF[proLen++] = getDistance3;								//���ֵ
+					break;
+					
+				case FOUR_CLASSIFICATION:		//�ķ���
+					//���ص�1ͨ��Ͷ������
+					GPRS_DATA_BUF[proLen++] = devChannel1Type;						//��������
+					GPRS_DATA_BUF[proLen++] = getDistance1;								//���ֵ
+					
+					//���ص�2ͨ��Ͷ������
+					GPRS_DATA_BUF[proLen++] = devChannel2Type;						//��������
+					GPRS_DATA_BUF[proLen++] = getDistance2;								//���ֵ
+					
+					//���ص�3ͨ��Ͷ������
+					GPRS_DATA_BUF[proLen++] = devChannel3Type;						//��������
+					GPRS_DATA_BUF[proLen++] = getDistance3;								//���ֵ
+
+					//���ص�4ͨ��Ͷ������
+					GPRS_DATA_BUF[proLen++] = devChannel4Type;						//��������
+					GPRS_DATA_BUF[proLen++] = getDistance4;								//���ֵ
+					break;
+					
+				default:
+					break;
+					
+			}
+			break;
+			
+		case 6005:		//�ϴ��豸������			
+			switch(deviceType)
+			{
+				case DOUBLE_CLASSIFICATION:		//˫Ͱ480L
+					GPRS_DATA_BUF[proLen++] = leftBarrelType;						//��������
+					GPRS_DATA_BUF[proLen++] = 0x00;											//������					
+					GPRS_DATA_BUF[proLen++] = faultCode_1;							//������		
+					
+					GPRS_DATA_BUF[proLen++] = rightBarrelType;					//��������
+					GPRS_DATA_BUF[proLen++] = 0x00;											//������
+					GPRS_DATA_BUF[proLen++] = faultCode_2;							//������
+					
+					printf("\r\n-----> �ϴ�������\r\n");	
+					printf("\r\n��Ͱ = %d, ", faultCode_1);
+					printf("��Ͱ = %d\r\n", faultCode_2);
+					break;
+					
+				case DOUBLE_CLASSIFICATION_BOTTLE:		//˫Ͱ480L��ƿ��	
+					faultCode_1 = 0;																		//Ŀǰƿ��Ͱû�����ù�����
+					GPRS_DATA_BUF[proLen++] = leftBarrelType;						//��������	
+					GPRS_DATA_BUF[proLen++] = 0x00;											//������		
+					GPRS_DATA_BUF[proLen++] = faultCode_1;							//������			
+					
+					GPRS_DATA_BUF[proLen++] = rightBarrelType;					//��������
+					GPRS_DATA_BUF[proLen++] = 0x00;											//������
+					GPRS_DATA_BUF[proLen++] = faultCode_2;							//������
+					
+					printf("\r\n-----> �ϴ�������\r\n");	
+					printf("\r\n��Ͱ = %d, ", faultCode_1);
+					printf("��Ͱ = %d\r\n", faultCode_2);
+					break;
+					
+				case SINGLE_CLASSIFICATION:		//��Ͱ660L
+					GPRS_DATA_BUF[proLen++] = leftBarrelType;						//��������
+					GPRS_DATA_BUF[proLen++] = 0x00;											//������
+					GPRS_DATA_BUF[proLen++] = faultCode_1;							//������	
+					
+					printf("\r\n-----> �ϴ�������\r\n");	
+					printf("\r\n������ = %d\r\n", faultCode_1);	
+					break;
+			}
+			break;
+
+//-------------------------------------�ɶ�����̨-------------------------------------			
+		case 6008:			//�ɶ�����̨����Э��
+		
+			break;
+		
+//-------------------------------------�ϴ��û�Ͷ����Ϣ���������ŵ�Ͱ��������-------------------------------------		
+		case 6011:		//�ϴ�Ͷ������ 
+			GPRS_DATA_BUF[proLen++] = sendPutInType;						//����ʶ��ʽ
+			GPRS_DATA_BUF[proLen++] = sendDataLength;						//����������Ϣ�ĳ���
+			memcpy(&GPRS_DATA_BUF[proLen], sendDataBuf, 33);		//����������Ϣ
+			proLen += 33;
+			
+// 			printf("\r\nsendUserData:");
+// 			show(sendDataBuf, 33);
+			
+			switch(deviceType)
+			{
+				case DOUBLE_CLASSIFICATION:		//˫Ͱ480L
+					//������ͰͶ���ϴ�����
+					GPRS_DATA_BUF[proLen++] = leftBarrelType;						//�������ͣ������ࣩ
+					
+					GPRS_DATA_BUF[proLen++] = getWeight1 >> 8;				//������8λ
+					GPRS_DATA_BUF[proLen++] = getWeight1;
+					
+					GPRS_DATA_BUF[proLen++] = getDistance1;						//���ֵ
+					
+					GPRS_DATA_BUF[proLen++] = getWeightBefore1 >> 8;			//Ͷ��ǰͰ��������
+					GPRS_DATA_BUF[proLen++] = getWeightBefore1;
+					GPRS_DATA_BUF[proLen++] = getWeightAfter1 >> 8;				//Ͷ�ź�Ͱ��������
+					GPRS_DATA_BUF[proLen++] = getWeightAfter1;
+					
+					ShowUploadAllData(leftBarrelType, getWeight1, getDistance1, getWeightBefore1, getWeightAfter1);
+					
+					//������ͰͶ���ϴ�����
+					GPRS_DATA_BUF[proLen++] = rightBarrelType;											//�������ͣ�������
+					
+					GPRS_DATA_BUF[proLen++] = getWeight2 >> 8;				//������8λ
+					GPRS_DATA_BUF[proLen++] = getWeight2;
+					
+					GPRS_DATA_BUF[proLen++] = getDistance2;						//���ֵ
+					
+					GPRS_DATA_BUF[proLen++] = getWeightBefore2 >> 8;				//Ͷ��ǰͰ��������
+					GPRS_DATA_BUF[proLen++] = getWeightBefore2;
+					GPRS_DATA_BUF[proLen++] = getWeightAfter2 >> 8;				//Ͷ�ź�Ͱ��������
+					GPRS_DATA_BUF[proLen++] = getWeightAfter2;
+					
+					ShowUploadAllData(rightBarrelType, getWeight2, getDistance2, getWeightBefore2, getWeightAfter2);
+					break;
+					
+				case DOUBLE_CLASSIFICATION_BOTTLE:		//˫Ͱ480L��ƿ��	
+					//������ͰͶ���ϴ�����
+					GPRS_DATA_BUF[proLen++] = leftBarrelType;						//�ɻ���������
+					
+					GPRS_DATA_BUF[proLen++] = smallBottleCount >> 8;		//С����ƿ��������8λ��
+					GPRS_DATA_BUF[proLen++] = smallBottleCount;					//С����ƿ��������8λ��
+					
+					GPRS_DATA_BUF[proLen++] = getDistance1;							//���ֵ
+					
+					GPRS_DATA_BUF[proLen++] = 0;												//Ͷ��ǰͰ��������
+					GPRS_DATA_BUF[proLen++] = 0;
+					GPRS_DATA_BUF[proLen++] = 0;												//Ͷ�ź�Ͱ��������
+					GPRS_DATA_BUF[proLen++] = 0;
+					
+					ShowUploadAllData(leftBarrelType, smallBottleCount, getDistance1, 0, 0);
+					
+					//������ͰͶ���ϴ�����
+					GPRS_DATA_BUF[proLen++] = rightBarrelType;					//��������
+					
+					GPRS_DATA_BUF[proLen++] = getWeight2 >> 8;					//������8λ
+					GPRS_DATA_BUF[proLen++] = getWeight2;
+					
+					GPRS_DATA_BUF[proLen++] = getDistance2;							//���ֵ
+					
+					GPRS_DATA_BUF[proLen++] = getWeightBefore2 >> 8;			//Ͷ��ǰͰ��������
+					GPRS_DATA_BUF[proLen++] = getWeightBefore2;
+					GPRS_DATA_BUF[proLen++] = getWeightAfter2 >> 8;				//Ͷ�ź�Ͱ��������
+					GPRS_DATA_BUF[proLen++] = getWeightAfter2;
+					
+					ShowUploadAllData(rightBarrelType, getWeight2, getDistance2, getWeightBefore2, getWeightAfter2);
+					break;
+					
+				case SINGLE_CLASSIFICATION:		//��Ͱ660L
+					//������ͰͶ���ϴ�����
+					GPRS_DATA_BUF[proLen++] = leftBarrelType;						//��������
+
+					GPRS_DATA_BUF[proLen++] = getWeight1 >> 8;					//������8λ
+					GPRS_DATA_BUF[proLen++] = getWeight1;
+	
+					GPRS_DATA_BUF[proLen++] = getDistance1;							//���ֵ
+					
+					GPRS_DATA_BUF[proLen++] = getWeightBefore1 >> 8;			//Ͷ��ǰͰ��������
+					GPRS_DATA_BUF[proLen++] = getWeightBefore1;
+					GPRS_DATA_BUF[proLen++] = getWeightAfter1 >> 8;				//Ͷ�ź�Ͱ��������
+					GPRS_DATA_BUF[proLen++] = getWeightAfter1;
+					
+					ShowUploadAllData(leftBarrelType, getWeight1, getDistance1, getWeightBefore1, getWeightAfter1);
+					break;
+					
+				case THREE_CLASSIFICATION:		//������
+					//���ص�1ͨ��Ͷ������
+					GPRS_DATA_BUF[proLen++] = devChannel1Type;						//��������
+					
+					GPRS_DATA_BUF[proLen++] = getWeight1 >> 8;						//����
+					GPRS_DATA_BUF[proLen++] = getWeight1;
+					
+					GPRS_DATA_BUF[proLen++] = getDistance1;								//���ֵ
+					
+					GPRS_DATA_BUF[proLen++] = getWeightBefore1 >> 8;			//Ͷ��ǰͰ��������
+					GPRS_DATA_BUF[proLen++] = getWeightBefore1;
+					GPRS_DATA_BUF[proLen++] = getWeightAfter1 >> 8;				//Ͷ�ź�Ͱ��������
+					GPRS_DATA_BUF[proLen++] = getWeightAfter1;
+					
+					ShowUploadAllData(devChannel1Type, getWeight1, getDistance1, getWeightBefore1, getWeightAfter1);
+					
+					//���ص�2ͨ��Ͷ������
+					GPRS_DATA_BUF[proLen++] = devChannel2Type;						//��������
+					
+					GPRS_DATA_BUF[proLen++] = getWeight2 >> 8;						//����
+					GPRS_DATA_BUF[proLen++] = getWeight2;
+					
+					GPRS_DATA_BUF[proLen++] = getDistance2;								//���ֵ
+					
+					GPRS_DATA_BUF[proLen++] = getWeightBefore2 >> 8;			//Ͷ��ǰͰ��������
+					GPRS_DATA_BUF[proLen++] = getWeightBefore2;
+					GPRS_DATA_BUF[proLen++] = getWeightAfter2 >> 8;				//Ͷ�ź�Ͱ��������
+					GPRS_DATA_BUF[proLen++] = getWeightAfter2;
+					
+					ShowUploadAllData(devChannel2Type, getWeight2, getDistance2, getWeightBefore2, getWeightAfter2);
+					
+					//���ص�3ͨ��Ͷ������
+					GPRS_DATA_BUF[proLen++] = devChannel3Type;						//��������
+					
+					GPRS_DATA_BUF[proLen++] = getWeight3 >> 8;						//����
+					GPRS_DATA_BUF[proLen++] = getWeight3;
+					
+					GPRS_DATA_BUF[proLen++] = getDistance3;								//���ֵ
+					
+					GPRS_DATA_BUF[proLen++] = getWeightBefore3 >> 8;			//Ͷ��ǰͰ��������
+					GPRS_DATA_BUF[proLen++] = getWeightBefore3;
+					GPRS_DATA_BUF[proLen++] = getWeightAfter3 >> 8;				//Ͷ�ź�Ͱ��������
+					GPRS_DATA_BUF[proLen++] = getWeightAfter3;
+					
+					ShowUploadAllData(devChannel3Type, getWeight3, getDistance3, getWeightBefore3, getWeightAfter3);
+					break;
+					
+				case FOUR_CLASSIFICATION:		//�ķ���
+					//���ص�1ͨ��Ͷ������
+					GPRS_DATA_BUF[proLen++] = devChannel1Type;						//��������
+					
+					GPRS_DATA_BUF[proLen++] = getWeight1 >> 8;						//����
+					GPRS_DATA_BUF[proLen++] = getWeight1;
+					
+					GPRS_DATA_BUF[proLen++] = getDistance1;								//���ֵ
+					
+					GPRS_DATA_BUF[proLen++] = getWeightBefore1 >> 8;			//Ͷ��ǰͰ��������
+					GPRS_DATA_BUF[proLen++] = getWeightBefore1;
+					GPRS_DATA_BUF[proLen++] = getWeightAfter1 >> 8;				//Ͷ�ź�Ͱ��������
+					GPRS_DATA_BUF[proLen++] = getWeightAfter1;
+					
+					ShowUploadAllData(devChannel1Type, getWeight1, getDistance1, getWeightBefore1, getWeightAfter1);
+					
+					//���ص�2ͨ��Ͷ������
+					GPRS_DATA_BUF[proLen++] = devChannel2Type;						//��������
+					
+					GPRS_DATA_BUF[proLen++] = getWeight2 >> 8;						//����
+					GPRS_DATA_BUF[proLen++] = getWeight2;
+					
+					GPRS_DATA_BUF[proLen++] = getDistance2;								//���ֵ
+					
+					GPRS_DATA_BUF[proLen++] = getWeightBefore2 >> 8;			//Ͷ��ǰͰ��������
+					GPRS_DATA_BUF[proLen++] = getWeightBefore2;
+					GPRS_DATA_BUF[proLen++] = getWeightAfter2 >> 8;				//Ͷ�ź�Ͱ��������
+					GPRS_DATA_BUF[proLen++] = getWeightAfter2;
+					
+					ShowUploadAllData(devChannel2Type, getWeight2, getDistance2, getWeightBefore2, getWeightAfter2);
+					
+					//���ص�3ͨ��Ͷ������
+					GPRS_DATA_BUF[proLen++] = devChannel3Type;						//��������
+					
+					GPRS_DATA_BUF[proLen++] = getWeight3 >> 8;						//����
+					GPRS_DATA_BUF[proLen++] = getWeight3;
+					
+					GPRS_DATA_BUF[proLen++] = getDistance3;								//���ֵ
+					
+					GPRS_DATA_BUF[proLen++] = getWeightBefore3 >> 8;			//Ͷ��ǰͰ��������
+					GPRS_DATA_BUF[proLen++] = getWeightBefore3;
+					GPRS_DATA_BUF[proLen++] = getWeightAfter3 >> 8;				//Ͷ�ź�Ͱ��������
+					GPRS_DATA_BUF[proLen++] = getWeightAfter3;
+					
+					ShowUploadAllData(devChannel3Type, getWeight3, getDistance3, getWeightBefore3, getWeightAfter3);
+					
+					//���ص�4ͨ��Ͷ������
+					GPRS_DATA_BUF[proLen++] = devChannel4Type;						//��������
+					
+					GPRS_DATA_BUF[proLen++] = getWeight4 >> 8;						//����
+					GPRS_DATA_BUF[proLen++] = getWeight4;
+					
+					GPRS_DATA_BUF[proLen++] = getDistance4;								//���ֵ
+					
+					GPRS_DATA_BUF[proLen++] = getWeightBefore4 >> 8;			//Ͷ��ǰͰ��������
+					GPRS_DATA_BUF[proLen++] = getWeightBefore4;
+					GPRS_DATA_BUF[proLen++] = getWeightAfter4 >> 8;				//Ͷ�ź�Ͱ��������
+					GPRS_DATA_BUF[proLen++] = getWeightAfter4;
+					
+					ShowUploadAllData(devChannel4Type, getWeight4, getDistance4, getWeightBefore4, getWeightAfter4);
+					break;
+					
+				default:
+					break;
+			}					
+			break;
+
+	}
+	//��ˮ��
+	GPRS_DATA_BUF[proLen++] = (uint8_t)serial_number >> 8;
+	GPRS_DATA_BUF[proLen++] = (uint8_t)serial_number;
+	
+	crc = CRC_Check(&GPRS_DATA_BUF[6], proLen - 6);		//��ȥ֡ͷ�ͳ���6���ֽ�
+	
+	//CRCУ����
+	GPRS_DATA_BUF[proLen++] = crc;
+	
+	//���͵����ݳ���
+	dataLen = proLen - 6;				//Э���ܳ��� - ��4�ֽ�֡ͷ + 2�ֽڳ��ȣ�
+	
+	GPRS_DATA_BUF[4] = (uint8_t)(dataLen >> 8);
+	GPRS_DATA_BUF[5] = (uint8_t)dataLen;
+	
+	printf("\r\nTCP --> No = %4d; Len = %d\r\n", proNum, proLen);
+// 	show(GPRS_DATA_BUF, proLen);
+	
+	serial_number++;
+	return proLen;							//���ر�Э����ܳ���
+}
+
+/*
+***********************************************************************
+*	�� �� ��: GetOrderCode
+*	����˵��: ȡ��ָ����
+*	��    �Σ���
+*	�� �� ֵ: ���յ����ݵ�ָ��
+***********************************************************************
+*/
+uint16_t GetOrderCode(uint8_t *pInputData)
+{
+	uint16_t returnData;
+	returnData = pInputData[14] << 8;
+	returnData |= pInputData[15];
+	return returnData;
+}
+
+/*
+***********************************************************************
+*	�� �� ��: CheckOrderCodeUploadAck
+*	����˵��: ���ָ���ϴ��Ƿ�ɹ�Ӧ��
+*	��    �Σ���
+*	�� �� ֵ: ���յ����ݵ�ָ��
+***********************************************************************
+*/
+uint8_t CheckOrderCodeUploadAck(uint16_t upCmd, uint16_t ackCmd)
+{
+	uint8_t returnSta = 0;
+	
+	switch(upCmd)
+	{
+		case 1001: if(ackCmd == 10011) returnSta = 1; break;
+		case 1003: if(ackCmd == 1003) returnSta = 1; break;
+		case 2001: if(ackCmd == 2001) returnSta = 1; break;
+		case 2003: if(ackCmd == 2003) returnSta = 1; break;
+		case 4001: if(ackCmd == 4002) returnSta = 1; break;
+		case 4011: if(ackCmd == 4022) returnSta = 1; break;
+		case 4201: if(ackCmd == 4202) returnSta = 1; break;
+		case 4301: if(ackCmd == 4302) returnSta = 1; break;
+		case 4401: if(ackCmd == 4402) returnSta = 1; break;
+		case 4111: if(ackCmd == 4222) returnSta = 1; break;
+		case 6011: if(ackCmd == 60011) returnSta = 1; break;
+		case 6021: if(ackCmd == 6021) returnSta = 1; break;
+		case 4701: if(ackCmd == 4702) returnSta = 1; break;
+		case 4801: if(ackCmd == 4802) returnSta = 1; break;
+		case 4901: if(ackCmd == 4901) returnSta = 1; break;
+		case 5001: if(ackCmd == 5001) returnSta = 1; break;
+		case 5002: if(ackCmd == 5002) returnSta = 1; break;
+		case 6004: if(ackCmd == 60041) returnSta = 1; break;
+			
+			
+		default:
+			break;
+	}
+	return returnSta;
+}
+
+/*
+***********************************************************************
+*	�� �� ��: ProtocolParsing
+*	����˵��: �Խ��յ����ݽ���Э�����
+*	��    �Σ���
+*	�� �� ֵ: ��
+***********************************************************************
+*/
+void TCP_Protocol(uint8_t* pCdmStr, uint8_t length)
+{
+	char *p;
+	uint8_t *pdata;						//���������ص�����ָ��
+	uint32_t dataTemp;
+	uint8_t tempData[32];
+	
+// 	p = (char*)strstr((const char*)pCdmStr, ":");
+// 	pdata = (uint8_t*)(p + 1);
+	
+	pdata = pCdmStr;
+
+	if((*(pdata) == 'H') && (*(pdata+1) == 'E') && (*(pdata+2) == 'R') && (*(pdata+3) == 'O'))	//�ǺϷ���Э��
+	{
+		TCP_recreceiveStatus = 1;														//��־���յ�TCP����
+		recreceiveOrderCode = GetOrderCode(pdata);					//��������Ӧ��ָ����	
+		
+		//��ӡ���յ��ĺ�̨����
+// 		printf("\r\nS -> %d \r\n", recreceiveOrderCode);
+// 		show(pCdmStr, length);
+		
+		if(CheckOrderCodeUploadAck(sendOrderCode, recreceiveOrderCode))
+		{
+			receiveDataMark = 1;
+		}
+		
+		switch(recreceiveOrderCode)		//����ָ����������ݵĽ���
+		{
+			case 10011:
+				pdata += 16;
+				getDeviceWorkStatusVal = *(pdata++);
+				getDeviceWorkStatusMark = 1;
+				break;
+				
+			case 4002:				//�����������û���ѯ��Ϣ
+				//ȡ���Ƿ�ͨ����֤
+				pdata += 16;
+				isAuth = *(pdata++);
+				
+				//�û�ID
+				dataTemp = *(pdata++) << 24;
+				dataTemp |= *(pdata++) << 16;
+				dataTemp |= *(pdata++) << 8;
+				dataTemp |= *(pdata++);
+				userID = dataTemp;
+				
+				//�û��˺�
+				dataTemp = *(pdata++) << 24;
+				dataTemp |= *(pdata++) << 16;
+				dataTemp |= *(pdata++) << 8;
+				dataTemp |= *(pdata++);
+				accountNum = dataTemp;
+				
+				//ȡ���ǳƵĳ���
+				nickNameLength = *(pdata++);
+				if(nickNameLength > 64)
+				{
+					printf("\r\nData overflow\r\n");
+					memcpy(nickName, pdata, 64);
+					
+				}else{
+					//ȡ���ǳ�����
+					memcpy(nickName, pdata, nickNameLength);
+				}
+				pdata += nickNameLength;
+				
+				//ȡ���ʽ�
+				dataTemp = *(pdata++) << 24;
+				dataTemp |= *(pdata++) << 16;
+				dataTemp |= *(pdata++) << 8;
+				dataTemp |= *(pdata++);
+				capital = dataTemp;
+				
+				//ȡ�����������
+				residue = *(pdata++);
+				
+				userInfoQueryStatus = 1;					//�û���Ϣ��ѯ�ɹ������ⲿ���
+				
+// 				printf("\r\nisAuth = %x \r\n", isAuth);
+// 				printf("\r\nuserID = %4x \r\n", userID);
+// 				printf("\r\naccountNum = %4x \r\n", accountNum);
+// 				printf("\r\nnickNameLength = %x \r\n", nickNameLength);
+// 				show(nickName, 20);
+// 				printf("\r\ncapital = %4x \r\n", capital);
+// 				printf("\r\nresidue = %x \r\n", residue);	
+				break;
+				
+			//�����������û���ѯ��Ϣ���������û��Ĺ̶����ݶ�ά����Ϣ��
+			case 4022:				//ǰ�ڵ�Э����һ����Ŀ���ϴ��ظ���,��4402����
+			case 4202:				//��ȡ�û���Ϣ����POS����Ȩ���ƿ���Ͷ�Ŵ�����������Ϣ������������ά�룩
+			case 4302:				//���ڷ���������Ƿ��ܴ�Ͷ�ſ���
+			case 4402:				//�滻4011��������Ϣ������������ά�룬���ڴ�ӡ���������
+				//ȡ���Ƿ�ͨ����֤
+				pdata += 16;
+				isAuth = *(pdata++);
+				
+				//�û�ID
+				dataTemp = *(pdata++) << 24;
+				dataTemp |= *(pdata++) << 16;
+				dataTemp |= *(pdata++) << 8;
+				dataTemp |= *(pdata++);
+				userID = dataTemp;
+				
+				//�û��˺�
+				dataTemp = *(pdata++) << 24;
+				dataTemp |= *(pdata++) << 16;
+				dataTemp |= *(pdata++) << 8;
+				dataTemp |= *(pdata++);
+				accountNum = dataTemp;
+				
+				//ȡ���ǳƵĳ���
+				nickNameLength = *(pdata++);
+				if(nickNameLength > 64)
+				{
+					printf("\r\nData overflow\r\n");
+					memcpy(nickName, pdata, 64);
+					
+				}else{
+					//ȡ���ǳ�����
+					memcpy(nickName, pdata, nickNameLength);
+				}
+				pdata += nickNameLength;
+				
+				//ȡ���ʽ�
+				dataTemp = *(pdata++) << 24;
+				dataTemp |= *(pdata++) << 16;
+				dataTemp |= *(pdata++) << 8;
+				dataTemp |= *(pdata++);
+				capital = dataTemp;
+				
+				//ȡ�����������
+				residue = *(pdata++);
+				
+				//ȡ���û�ID��ά����Ϣ���û���ӡ��ά�룩
+				barcodeLength = *(pdata++);
+				memset(tempData, 0, 32);
+				
+				if(barcodeLength > 32)
+				{
+					printf("\r\nData overflow\r\n");
+					memcpy(tempData, pdata, 32); 
+				}else{
+					memcpy(tempData, pdata, barcodeLength); 
+				}
+				
+				sprintf((char*)barcode, "yueng=%s", (char*)tempData);		//��̨���ص��û�ID��ά��û�а���ͷ����Ϣ"yueng="
+				barcodeLength += 6;	
+				
+				userInfoQueryStatus = 1;					//�û���Ϣ��ѯ�ɹ������ⲿ���
+// 				
+// 				printf("\r\nisAuth = %x \r\n", isAuth);
+// 				printf("\r\nuserID = %4x \r\n", userID);
+// 				printf("\r\naccountNum = %4x \r\n", accountNum);
+// 				printf("\r\nnickNameLength = %x \r\n", nickNameLength);
+// 				show(nickName, 20);
+// 				printf("\r\ncapital = %4x \r\n", capital);
+// 				printf("\r\nresidue = %x \r\n", residue);	
+// 				printf("\r\nbarcode = %s \r\n", barcode);	
+				break;
+				
+			case 4702:		//�����˺���֤Ӧ��
+				pdata += 16;
+				
+				boxOpenAckStatus = *(pdata++);
+				getBoxOpenAckMark = 1;
+				break;
+			
+			case 60011:
+				pdata += 16;
+				//ȡ���ʽ�
+				dataTemp = *(pdata++) << 24;
+				dataTemp |= *(pdata++) << 16;
+				dataTemp |= *(pdata++) << 8;
+				dataTemp |= *(pdata++);
+				capitalAfter = dataTemp;
+				
+				putInUploadSuccessMark = 1;
+				
+				break;
+				
+			case 60041:		//��̨Ӧ���豸״̬�ϴ�
+				pdata += 16;
+				
+				getDevChannelNumbers = *(pdata++);
+				
+				if((getDevChannelNumbers >= 1) && (getDevChannelNumbers <= 4))
+				{
+					getDevChannel1Type = *(pdata++);
+					getDevChannel1DisDepthVal = *(pdata++);
+					getDevChannel1DisMaxVal = *(pdata++);
+					getDevChannel1DisAlarmPercent = *(pdata++);
+
+					if(getDevChannelNumbers >= 2)
+					{
+						getDevChannel2Type = *(pdata++);
+						getDevChannel2DisDepthVal = *(pdata++);
+						getDevChannel2DisMaxVal = *(pdata++);
+						getDevChannel2DisAlarmPercent = *(pdata++);
+					}
+
+					if(getDevChannelNumbers >= 3)
+					{
+						getDevChannel3Type = *(pdata++);
+						getDevChannel3DisDepthVal = *(pdata++);
+						getDevChannel3DisMaxVal = *(pdata++);
+						getDevChannel3DisAlarmPercent = *(pdata++);
+					}
+
+					if(getDevChannelNumbers >= 4)
+					{
+						getDevChannel4Type = *(pdata++);
+						getDevChannel4DisDepthVal = *(pdata++);
+						getDevChannel4DisMaxVal = *(pdata++);
+						getDevChannel4DisAlarmPercent = *(pdata++);
+					}
+
+					getSetDistanceParamMark = 1;
+				}else{}
+				
+				break;
+				
+			default:
+				break;
+		}
+	}
+	memset(GPRS_RX_BUF, 0, GPRS_MAX_RECV_LEN);
+}
+
+/*
+***********************************************************************
+*	�� �� ��: SetSendProcotolSuccess
+*	����˵��: ���ñ��η��͵�Э���ѳɹ�����
+*	��    �Σ���
+*	�� �� ֵ: ��
+***********************************************************************
+*/
+void SetSendProcotolSuccess(void)
+{
+	switch(sendOrderCode)
+	{
+		case 6008:
+// 			printf("\r\n�ϴ��ɹ�\r\n");
+// 			uploadWightMark = 1;
+// 			SendScaleUploadOkMark();
+			break;
+			
+		default:
+			break;
+	}
+}
+
+/******************** (C) COPYRIGHT 2017 CXHY *****END OF FILE*******************/ 
diff --git a/STM32_4路称重_Git提交精简工程/src/USER/tcp_protocol.h b/STM32_4路称重_Git提交精简工程/src/USER/tcp_protocol.h
new file mode 100755
index 0000000..006f5b5
--- /dev/null
+++ b/STM32_4路称重_Git提交精简工程/src/USER/tcp_protocol.h
@@ -0,0 +1,26 @@
+#ifndef __PROTOCOL_H
+#define __PROTOCOL_H
+#include "stm32f10x.h"
+
+//ͨѶЭ��ṹ��
+typedef struct _protocol
+{
+	uint16_t  protocolCode;									//ָ����
+	uint8_t 	parseState;										//��Ϣ������
+}	protocol_TypeDef;
+
+extern uint16_t dataLength;								//һ֡���ݵĳ���
+extern uint16_t operateType;							//���̨������������ָ������
+extern uint16_t sendOrderCode;						//���̨���͵�Э��ָ����	
+extern uint16_t recreceiveOrderCode;			//���յ���̨�·���Э��ָ����
+extern uint8_t 	TCP_recreceiveStatus;			//TCP���ݽ��ձ�־��1Ϊ���յ�TCP���ݣ�0��
+
+void ProtocolInit(void);
+uint16_t SendProtocolPackaging(uint16_t proNum);
+void TCP_Protocol(uint8_t* pCdmStr, uint8_t length);
+
+void SetSendProcotolSuccess(void);
+
+#endif
+
+/******************** (C) COPYRIGHT 2017 CXHY *****END OF FILE*******************/ 
diff --git a/STM32_4路称重_Git提交精简工程/src/USER/user_app.c b/STM32_4路称重_Git提交精简工程/src/USER/user_app.c
new file mode 100755
index 0000000..2cd9120
--- /dev/null
+++ b/STM32_4路称重_Git提交精简工程/src/USER/user_app.c
@@ -0,0 +1,1661 @@
+/*************************** (C) COPYRIGHT 2017 Ping ****************************
+ * �ļ���  ��user_app.c
+ * ��  ��  ���û�Ӧ�ó���
+ * ��  ��  ��V1.0
+ * ��  ��  ��XuZhongPing
+ * ��  ��  ��2017/09/04
+*********************************************************************************/
+#include "user_app.h"
+#include "usart1.h"
+#include "delay.h"
+#include "timer.h"
+#include "display.h"
+
+#include "sound.h"
+#include "pc_protocol.h"
+#include "stmflash.h"
+#include "user_manag.h"
+#include "deviceSet.h"
+
+/*
+***********************************************************************
+*	�� �� ��: showHexData
+*	����˵��: ��ʮ��������ʾ�����������
+*	��    ��:	��
+*	�� �� ֵ: ��
+***********************************************************************
+*/
+void showHexData(uint8_t num[], uint8_t n)
+{
+    uint8_t i;
+		printf("\r\n");
+    for(i=0; i<n; i++)
+		{
+//       printf("%02X ",num[i]);
+			printf("0x%02X ",num[i]);
+		}
+		printf("\r\n");
+}
+
+/*
+***********************************************************************
+*	�� �� ��: UserInfoIdentityTask
+*	����˵��: �û�����ʶ��
+*	��    �Σ���
+*	�� �� ֵ: ��
+***********************************************************************
+*/
+void UserIdentificationTask(void)
+{
+	getPutInType = 0;
+	
+	if(RFID_state == 1)
+	{
+		RFID_state = 0;
+		
+		getPutInType = 1;
+		getDataLength = strlen((char*)cardNumberStr);
+		memset(getDataBuf, 0, 256);
+		memcpy(getDataBuf, cardNumberStr, getDataLength);
+			
+	}else if(sweep2CodeState == 1){
+		sweep2CodeState = 0;
+		
+		getPutInType = 2;
+		getDataLength = codeDataLength;
+		memset(getDataBuf, 0, 256);
+		memcpy(getDataBuf, codeBuf, getDataLength);
+	}else{}
+	
+	if((getPutInType != 0) && (getDataLength > 0))
+	{
+		beep_shortBeepMark = 1;
+		
+		sendPutInType = 0;
+		sendDataLength = 0;
+		memset(sendDataBuf, 0, 256);
+		
+		sendPutInType = getPutInType;
+		sendDataLength = getDataLength;
+		memcpy(sendDataBuf, getDataBuf, getDataLength);
+		
+		printf("\r\n�û�����ʶ��\r\n");
+		printf("Type: %d\r\n", sendPutInType);
+		printf("Len: %d\r\n", sendDataLength);
+		printf("DataBuf: %s\r\n", sendDataBuf);
+		
+		PC_ProCommandSend(0x01);
+	}
+}
+
+/*
+***********************************************************************
+*	�� �� ��: GetPutInType
+*	����˵��: ȡ��Ͷ�ſ��ŷ�ʽ����
+*	��    �Σ���
+*	�� �� ֵ: 0x01->IC����0x02->��ά�룻0x03->�����룻0x04-> ��ť
+***********************************************************************
+*/
+uint8_t GetPutInType(void)
+{
+	uint8_t retData;
+	if(keyOpenDoorRequest == 1)											//���Ű�ť�ж�
+	{
+		retData = 0x04;
+		keyOpenDoorRequest = 0;
+	}else if((RFID_state == 1) || (scanIC_2CodeState == 1)){			//ˢIC����IC����ά���ж�
+		retData = 0x01;
+		RFID_state = 0;
+		scanIC_2CodeState = 0; 
+	}else if(sweep2CodeState == 1){									//��ά��ɨ���ж�
+		retData = 0x02;
+		sweep2CodeState = 0;
+	}else if(scanBarCodeState == 1){								//ɨ��������ά��
+		retData = 0x03;
+		scanBarCodeState = 0;
+	}else if(scanLabelCodeState == 1){							//��ά����ֽ��2018-04-28������
+		retData = 0x05;
+		scanLabelCodeState = 0;
+	}else if(RFID_state == 3){											//���п�
+		if(cardNumberLen == 10)												//���ų���Ϊ10λ���Զ��忨�ţ�
+		{
+			retData = 0x0A;
+		}else{																				//���п�����Ϊ��ɫ�����
+			retData = 0x07;
+		}
+		RFID_state = 0;
+	}else if(RFID_state == 4){											//����֤
+		retData = 0x08;
+		RFID_state = 0;
+	}else if(RFID_state == 5){											//����IC��
+		retData = 0x09;
+		RFID_state = 0;
+	}else{
+		retData = 0x00;
+	}
+	return retData;
+}
+
+/*
+***********************************************************************
+*	�� �� ��: GetUserInfo
+*	����˵��: �����û�����Ŀ��ŷ�ʽ��ȡ���û��������Ϣ��IC�����ά�룩
+*	��    �Σ�inputType->�û����ŷ�ʽ��IC�����ά�룩
+*	�� �� ֵ: �ޣ����ú�ı���ȫ�ֱ���getDataLength��getDataBuf��ֵ��
+***********************************************************************
+*/
+void GetUserInfo(uint8_t inputType)
+{
+	uint8_t dataBuf[17] = {0};
+	
+	switch(inputType)																	//���ݿ�������ʽ���ض�Ӧ��������Ϣ
+	{
+		case 0x01:		//ˢIC������
+			getDataLength = 9;														//IC��������ϢΪ9�ֽ�
+			memcpy(getDataBuf, RFID_ID, 9);								//����IC��������Ϣ
+			memcpy(get_IC_ID, RFID_ID, 9);								//����IC��������Ϣ
+			memcpy(getCardNumberBit, cardNumberBit, 17);	//����IC��������Ϣ����λ��ʾ��
+// 			printf("\r\ngetDataLength = %d\r\n", getDataLength);
+// 			printf("\r\nRFID = %x\r\n", RFID_ID[0]);
+			break;
+			
+		case 0x02:		//ɨ��ά�뿪��
+			getDataLength = codeDataLength;								//��ά��������Ϣ����
+			memcpy(getDataBuf, codeBuf, codeDataLength);	//�����ά�뷢����Ϣ
+			memset(codeBuf, 0x00, 35);										//�����������
+// 			printf("\r\ngetDataLength = %d\r\n", getDataLength);
+			break;
+			
+		case 0x03:		//��������������ά�뿪��
+			getDataLength = codeDataLength;								//��ά��������Ϣ����
+			memcpy(getDataBuf, codeBuf, codeDataLength);	//�����ά�뷢����Ϣ
+			memset(codeBuf, 0x00, 35);										//�����������
+			break;
+			
+		case 0x04:		//��ť������������Ϣ
+			getDataLength = 0;								
+			break;
+			
+		case 0x05:		//��ά����ֽ����
+			getDataLength = codeDataLength;								//��ά��������Ϣ����
+			memcpy(getDataBuf, codeBuf, codeDataLength);	//�����ά�뷢����Ϣ
+			memset(codeBuf, 0x00, 35);										//�����������
+			break;
+			
+		case 0x07:		//���п�
+		case 0x0A:		//���п�(�Զ��忨��)
+			getDataLength = cardNumberLen;
+			memcpy(getDataBuf, cardNumberStr, getDataLength);
+			
+			memcpy(&dataBuf[11], &cardNumberBit[getDataLength-6], 6);			//ȡ���ŵĺ�6λ������ʾ
+			memcpy(getCardNumberBit, dataBuf, 17);
+			memset(cardNumberStr, 0x00, 33);
+			break;
+			
+		case 0x09:		//����IC��
+			getDataLength = 24;														//��ά��������Ϣ����
+			memcpy(getDataBuf, cardNumberStr, getDataLength);	//�����ά�뷢����Ϣ
+			memset(cardNumberStr, 0x00, 33);										//�����������
+			break;
+	}
+}
+
+/*
+***********************************************************************
+*	�� �� ��: ShowPutInMSG
+*	����˵��: ��ʾͶ�ſ������ͼ�����ʶ�������Ϣ 
+*	��    �Σ�Ͷ������0x01->IC����0x02->��ά�룻0x03->�����룻0x04-> ��ť
+*	�� �� ֵ: ��
+***********************************************************************
+*/
+void ShowPutInInfo(uint8_t uType)
+{
+	switch(uType)																//���ݿ�������ʽ���ض�Ӧ��������Ϣ
+	{
+		case 0x01:		//ˢIC������
+			printf("\r\nˢIC����ɨIC����ά�뿪��\r\n");
+			break;
+			
+		case 0x02:		//ɨ��ά�뿪��
+			printf("\r\nɨ��ά�뿪��\r\n");
+			break;
+			
+		case 0x03:		//�����������뿪��
+			printf("\r\nɨ��������������ά�뿪��\r\n");
+			break;
+			
+		case 0x04:		//��ť������������Ϣ
+			printf("\r\n��ť����\r\n");							
+			break;
+			
+		case 0x05:		//��ά����ֽ����
+			printf("\r\n��ά����ֽ����\r\n");							
+			break;
+	}
+	
+	printf("\r\n�û�ʶ����ϢΪ��\r\n");	
+	printf("\r\n <>�������ͣ�%d\r\n", getPutInType);
+	printf("\r\n <>���ݳ��ȣ�%d\r\n", getDataLength);
+// 	printf("\r\n <>���ݣ�%s\r\n", getDataBuf);
+// 	showHexData(getDataBuf, 33);
+}
+
+/*
+***********************************************************************
+*	�� �� ��: ClearPutInInfo
+*	����˵��: Ͷ����ɺ����Ͷ����Ϣ��Ϊ��һ��������׼��
+*	��    �Σ���
+*	�� �� ֵ: ��
+***********************************************************************
+*/
+void ClearPutInInfo(void)
+{
+	keyOpenDoorRequest = 0;													//�����ť���±�־
+	RFID_state = 0;																	//���RFID_IC��ˢ����־
+	scanIC_2CodeState = 0;													//���ɨIC����ά�뿨�ű�־
+	sweep2CodeState = 0;														//�����ά��ɨ���־
+	scanBarCodeState = 0;														//���ɨ��������ά���־
+	scanLabelCodeState = 0;
+	
+	optoKeyStatus = 0;
+	putInProgress = 0;	
+	
+	getPutInType = 0x00;														//�������������֤����
+	getDataLength = 0x00;														//�������������֤��Ϣ�����ݳ���
+	memset(getDataBuf, 0x00, 33);										//�������������֤��Ϣ����
+	memset(get_IC_ID, 0x00, 9);											//���ȡ�õ�IC��������
+	memset(getCardNumberBit, 0x00, 17);							//���ȡ�õ�IC��������
+}
+
+/*
+***********************************************************************
+*	�� �� ��: FaultCodeCheck
+*	����˵��: �豸�������⣬����������1:��ʾ�й������ϴ�������
+*           0:��ʾû�й��ϲ����ϴ�������
+*	��    �Σ���
+*	�� �� ֵ: ��
+***********************************************************************
+*/
+#define codeLen 9
+uint8_t faultCode[codeLen] = {11, 12, 13, 22, 23, 24, 32, 33, 34};		//��������ϴ���
+
+static void FaultCodeCheck(uint8_t devType)
+{
+	uint8_t i = 0;
+	uint8_t faultMark = 0;
+	
+	switch(devType)
+	{
+		case DOUBLE_CLASSIFICATION:		//˫Ͱ480L
+			for(i = 0; i < codeLen; i++)
+			{
+				if((faultCode_1 == faultCode[i]) || (faultCode_2 == faultCode[i]))
+				{
+					faultMark = 1;
+					break;
+				}
+			}
+			break;
+			
+		case DOUBLE_CLASSIFICATION_BOTTLE:		//˫Ͱ480L����ƿ�ӣ�
+			for(i = 0; i < codeLen; i++)
+			{
+				if(faultCode_1 == faultCode[i])
+				{
+					faultMark = 1;
+					break;
+				}
+			}
+			break;
+			
+		case SINGLE_CLASSIFICATION:		//��Ͱ660L
+			for(i = 0; i < codeLen; i++)
+			{
+				if(faultCode_1 == faultCode[i])
+				{
+					faultMark = 1;
+					break;
+				}
+			}
+			break;
+			
+		default:
+			break;
+	}
+	
+	if(faultMark == 1)		//�й������ϴ�������
+	{
+		sendMsg.msgType = 6005;										//���ϴ����ϴ�
+		MessageSend(MSG_FIFO_PROTOCOL, sendMsg);
+	}
+}
+
+/*
+***********************************************************************
+*	�� �� ��: GetLimitKeyStatus
+*	����˵��: ȡ����λ���ص�״̬
+*	��    �Σ���
+*	�� �� ֵ: ������λ������λ״̬�������1���쳣��0��������
+***********************************************************************
+*/
+uint8_t GetLimitKeyStatus(void)
+{
+	uint8_t retData = 0;
+	
+	if(limitKeyExceptionMark > 0)
+	{	
+		switch(deviceType)
+		{
+			case DOUBLE_CLASSIFICATION:		//˫Ͱ480L
+				if(limitKeyExceptionMark & 0x10)
+				{
+					faultCode_1 = 20;
+				}
+				if(limitKeyExceptionMark & 0x01)
+				{
+					faultCode_2 = 20;
+				}
+				break;
+				
+			case DOUBLE_CLASSIFICATION_BOTTLE:
+				faultCode_1 = 0;										//Ŀǰƿ��Ͱû�����ù�����
+				if(limitKeyExceptionMark & 0x10)		//������ߵ���λ����
+				{
+					faultCode_2 = 20;
+				}
+				break;
+				
+			case SINGLE_CLASSIFICATION:		//��Ͱ660L	
+				if(limitKeyExceptionMark & 0x10)
+				{
+					faultCode_1 = 20;
+				}
+				faultCode_2 = 0;
+				break;
+				
+			default:
+				break;
+		}
+		
+		displayFaultCode = 20;
+		retData = 1;
+	}
+	return retData;
+}
+
+/*
+***********************************************************************
+*	�� �� ��: PutInOpenDoorTask
+*	����˵��: ����Ͷ����������
+*	��    �Σ���
+*	�� �� ֵ: ��
+***********************************************************************
+*/
+void PutInOpenDoorTask(void)
+{
+	uint8_t tempData = 0;
+	uint8_t temp = 0;
+	static uint8_t putInStatus = 0x00;
+	static uint8_t infoDisplayStatus = 0;
+	
+	static uint8_t putInPrompt = 0;					//Ͷ����ʾ���ţ�ÿ����һ�β���һ�Σ�
+	
+	static timer waitingTimer;
+	static timer playWaitingTimer;
+	static timer waitingPutInTimer;
+	static timer displayTimer;
+	static timer waitingUploadTimer;
+	static timer outTimer;
+	static timer waitingTimer4S;
+	static timer faceEntryTimer;
+	
+	static uint8_t timer_ok = 0;
+
+	if(timer_ok == 0)
+	{
+		timer_ok = 1;
+		timer_set(&waitingTimer, 10);
+		timer_set(&playWaitingTimer, 15);
+		timer_set(&waitingPutInTimer, CLOCK_SECOND*200);
+		timer_set(&displayTimer, CLOCK_SECOND*3);
+		timer_set(&waitingUploadTimer, CLOCK_SECOND*10);
+		timer_set(&outTimer, CLOCK_SECOND*2);
+		timer_set(&waitingTimer4S, CLOCK_SECOND*3);
+		timer_set(&faceEntryTimer, CLOCK_SECOND*60*5);
+	}
+	
+	switch(putInStatus)
+	{
+		case 0x00:		//��ʼ״̬
+			if(pcRequestOpenDoorMark == 1)														//�п�������
+			{
+				pcRequestOpenDoorMark = 0;
+				
+				beep_shortBeepMark = 1;										//������ʾ��
+				
+				//���������ǰ�������״̬��־
+				putInOKMark = 0;													//�����Ͷ����ɱ�־
+				disablePutInMark = 0;											//�����װ����ֹ���ű�־
+				userInfoQueryStatus = 0;									//������Ӻ�̨��ȡ�õ��û���Ϣ
+				putInUploadSuccessMark = 0;								//�����Ͷ���ϴ��ɹ���־
+				
+				infoDisplayStatus = 0;										//�û���Ϣÿ��һ����ֻ��ʾһ��
+				getUserInfoMark = 0;
+				putInPrompt = 0;													//�����ʾ����Ͷ��������ʶ������һ��Ͷ��ֻ����һ�Σ�
+				
+				Audio_Play(1);
+
+				Screen_Landing();
+
+				printf("\r\n---------> �û�������Ͷ�ţ�����\r\n");
+				isOpenDoor = 1;														//��־Ҫ���Ų���
+				putInProgress = 1;												//��־�豸���ڽ��в���
+				printf("\r\n���ڽ���Ͷ�Ų���......\r\n");
+				timer_restart(&playWaitingTimer);
+				timer_restart(&waitingPutInTimer);
+				timer_restart(&waitingTimer4S);
+				
+				putInStatus = 0x01;
+				break;
+			}
+			break;
+			
+		case 0x01:		//�ȴ�Ͷ��
+			if(timer_expired(&waitingPutInTimer))
+			{
+				putInStatus = 0x00;
+				ClearPutInInfo();
+
+				Screen_Default();
+				printf("\r\n�ȴ�Ͷ����ɳ�ʱ����\r\n");
+				break;
+			}
+			
+			//-----------------------------------------------------
+			//������ʾ�û����������Ͷ��
+			if(putInPrompt == 0)
+			{
+				if(timer_expired(&waitingTimer4S))
+				{
+					if(synchronousOpenDoorMark == 1)
+					{
+						Audio_Play(2);
+					}else{
+						Audio_Play(6);
+					}
+					putInPrompt = 1;
+				}
+			}
+			
+			//�Ƿ����ӳ�Ͷ��
+			if(delayCloseDoorStatus == 1)
+			{
+				delayCloseDoorStatus = 0;
+				timer_restart(&waitingPutInTimer);
+// 				printf("\r\n�ӳ�Ͷ��ʱ��\r\n");
+			}
+			
+			//��ʾ����ʱ
+			if(getRemainingTimerStatus == 1)
+			{
+				getRemainingTimerStatus = 0;
+			
+				//��ʾ����ʱ
+				Screen_Countdown(remainingTimer);		
+				PC_ProCommandSend(0x60);											//����λ������������ʾ�Ĺ��ŵ���ʱ				
+
+				//-----------------------------------------------------
+				//��ʾ���ż����ر�
+				if(remainingTimer == 6)
+				{
+					Audio_Play(3);
+				}
+			}
+			
+			//������յ��˳�����ָ����˳�
+			if(exitMark == 1)
+			{
+				exitMark = 0;
+				putInStatus = 0x05;
+				timer_restart(&outTimer);
+				break;
+			}
+			
+			//�ж��Ƿ�Ͷ�����
+			if(putInOKMark == 1)
+			{
+				putInOKMark = 0;
+	
+				printf("\r\n�յ�Ͷ����ɣ����ڴ���......\r\n");
+				
+				//Ͷ��״̬���
+				DropOffPortCheckTask();
+
+				PC_ProCommandSend(0x61);											//����λ�������û�Ͷ������������ʾ
+				
+				printf("\r\n--> �յ�����Ͷ���������£�");
+				printf("\r\n--> Type: %d", sendPutInType);
+				printf("\r\n--> Len: %d", sendDataLength);
+				if(getPutInType == 1)
+				{
+					printf("\r\n--> Data: ");
+					showHexData(sendDataBuf, sendDataLength);
+				}else{
+					printf("\r\n--> Data: %s\r\n", sendDataBuf);
+				}
+				
+				switch(deviceType)
+				{
+					case THREE_CLASSIFICATION:		//������
+						printf("\r\nͰ1: %2.2f Kg��%2.2f Kg -> %2.2f Kg�����룺%3.1f cm\r\n",\
+									(float)getWeight1/100, (float)getWeightBefore1/100, (float)getWeightAfter1/100, (float)getDistance1);
+									
+						printf("\r\nͰ2: %2.2f Kg��%2.2f Kg -> %2.2f Kg�����룺%3.1f cm\r\n",\
+									(float)getWeight2/100, (float)getWeightBefore2/100, (float)getWeightAfter2/100, (float)getDistance2);
+									
+						printf("\r\nͰ3: %2.2f Kg��%2.2f Kg -> %2.2f Kg�����룺%3.1f cm\r\n",\
+									(float)getWeight3/100, (float)getWeightBefore3/100, (float)getWeightAfter3/100, (float)getDistance3);
+						
+// 						printf("\r\n������ = %d\r\n", faultCode_L);
+						
+						//��ʾ�û�Ͷ����Ϣ
+						Screen_ShowPutInInfo2(getWeight1, getWeight2, getWeight3, getWeight4);
+						break;
+						
+					case FOUR_CLASSIFICATION:		//�ķ���
+						printf("\r\nͰ1: %2.2f Kg��%2.2f Kg -> %2.2f Kg�����룺%3.1f cm\r\n",\
+									(float)getWeight1/100, (float)getWeightBefore1/100, (float)getWeightAfter1/100, (float)getDistance1);
+									
+						printf("\r\nͰ2: %2.2f Kg��%2.2f Kg -> %2.2f Kg�����룺%3.1f cm\r\n",\
+									(float)getWeight2/100, (float)getWeightBefore2/100, (float)getWeightAfter2/100, (float)getDistance2);
+									
+						printf("\r\nͰ3: %2.2f Kg��%2.2f Kg -> %2.2f Kg�����룺%3.1f cm\r\n",\
+									(float)getWeight3/100, (float)getWeightBefore3/100, (float)getWeightAfter3/100, (float)getDistance3);
+									
+						printf("\r\nͰ4: %2.2f Kg��%2.2f Kg -> %2.2f Kg�����룺%3.1f cm\r\n",\
+									(float)getWeight4/100, (float)getWeightBefore4/100, (float)getWeightAfter4/100, (float)getDistance4);
+						
+// 						printf("\r\n������ = %d\r\n", faultCode_L);
+						
+						//��ʾ�û�Ͷ����Ϣ
+						Screen_ShowPutInInfo2(getWeight1, getWeight2, getWeight3, getWeight4);
+						break;
+						
+					default:
+						break;
+				}
+
+// 				FaultCodeCheck(deviceType);			//���ϼ���ϴ�
+				
+				printf("\r\n---------->Ͷ����ɣ�����\r\n");
+				
+				fillLightMask = 1;
+				
+// 				putInStatus = 0x02;
+// 				timer_restart(&displayTimer);
+				
+				timer_restart(&outTimer);
+				putInStatus = 0x05;
+				break;
+			}
+			break;
+			
+		case 0x02:		//ͣ����ʾͶ����Ϣ����
+			if(timer_expired(&displayTimer))
+			{
+				//�����Ͷ�ţ���ȴ��ϴ��ظ�Ͷ�ź�����
+				if((getWeight1 > 0) || (getWeight2 > 0) || (getWeight3 > 0) || (getWeight4 > 0) || (smallBottleCount > 0))
+				{
+					printf("\r\n������Ͷ�ţ��ȴ���̨��Ӧ����\r\n");
+					
+					timer_restart(&waitingUploadTimer);
+					putInStatus = 0x03;
+					break;
+				}else{																//û��Ͷ����ת��ллʹ�ý����˳�					
+					Audio_Play(4);
+					Screen_Exit();											//��ʾ���˳�ʹ�ý��桱
+					printf("\r\n��ʾͶ��ʱ�䵽������Ͷ���˳�\r\n");
+					timer_restart(&outTimer);
+					putInStatus = 0x05;
+					break;
+				}
+				
+			}
+			break;
+			
+		case 0x03:		//�ȴ��ϴ��ɹ���ʾͶ�ź�����
+			if(putInUploadSuccessMark == 1)
+			{
+				putInUploadSuccessMark = 0;
+				printf("\r\n֮ǰ��� = %.2f \r\n", (float)capital/100);
+				printf("\r\n֮����� = %.2f \r\n", (float)capitalAfter/100);
+				
+				if(capitalAfter >= capital)
+				{
+					Screen_ShowPutInReward(capital, capitalAfter);
+					PC_ProCommandSend(0x05);											//����λ�������û�Ͷ������������ʾ
+					printf("\r\n������� = %.2f \r\n", (float)(capitalAfter - capital)/100);
+				
+// 					printf("\r\n������� = %.2f \r\n", (float)(capitalAfter - capital)/100);
+// 					printf("\r\n��    �� = %.2f \r\n", (float)capitalAfter/100);
+				}
+				
+				putInStatus = 0x04;
+				timer_restart(&displayTimer);
+			}
+			
+			if(timer_expired(&waitingUploadTimer))
+			{
+				Audio_Play(4);
+					
+				Screen_Exit();											//��ʾ���˳�ʹ�ý��桱
+				printf("\r\n��ʾͶ��ʱ�䵽\r\n");
+				putInStatus = 0x05;
+				timer_restart(&outTimer);
+			}
+			break;
+			
+		case 0x04:
+			if(timer_expired(&displayTimer))
+			{
+				Audio_Play(4);
+				
+				Screen_Exit();											//��ʾ���˳�ʹ�ý��桱
+				printf("\r\n��ʾͶ��ʱ�䵽\r\n");
+				putInStatus = 0x05;
+				timer_restart(&outTimer);
+			}
+			break;
+			
+		case 0x05:		//ͣ����ʾ�˳�����
+			if(timer_expired(&outTimer))
+			{
+				printf("\r\n��ʾ����\r\n");
+				Screen_Default();
+				
+				PC_ProCommandSend(0x09);											//����λ������Ͷ�Ž���
+				ClearPutInInfo();
+				putInProgress = 0;
+				pcRequestOpenDoorMark = 0;
+				putInStatus = 0x00;
+			}
+			break;
+			
+		case 0x06:
+			if(timer_expired(&outTimer))
+			{
+				putInStatus = 0x00;
+			}
+			break;
+			
+//-----------------------------------------------------------------------------------------	
+		
+		case 0x66:		//װ����ֹ����ʱ��ʾװ����ʾ
+			if(timer_expired(&displayTimer))
+			{
+				printf("\r\n��ʾ����\r\n");
+				Screen_Default();
+				ClearPutInInfo();
+				putInStatus = 0x00;
+			}
+			break;
+			
+		case 0x10:		//�豸����ת���˴��ȴ�����
+			Screen_Error(0, displayFaultCode, 0);
+			PC_ProCommandSend(0x30);											//����λ�������豸����������ʾ
+			putInStatus = 0x11;
+			break;
+			
+		case 0x11:
+			//����λ���س��ֹ���֮�����е��ˣ�ֱ���޸�
+			break;
+
+//----------------------------------------------------------------------------------
+//�û����ô�������			
+		case 0x20:		//���õ��û���ʾ
+			Screen_Query(0x03, 0, NULL, 0, 0);
+			
+			sendMsg.msgType = 4301;
+			MessageSend(MSG_FIFO_PROTOCOL, sendMsg);	//���̨���������������ȡ�û���Ϣָ��
+			printf("\r\nGet user Info\r\n");
+					
+			putInStatus = 0x21;
+			timer_restart(&waitingUploadTimer);
+			timer_restart(&outTimer);
+			break;
+			
+		case 0x21:		//�ȴ���̨�����û���Ϣ
+			if(timer_expired(&waitingUploadTimer))
+			{
+				putInStatus = 0x05;
+				break;
+			}
+			
+			//�յ���̨Ӧ����û�������Ϣ
+			if(userInfoQueryStatus == 1)
+			{
+				userInfoQueryStatus = 0;
+				
+				if(isAuth == 1)			//�˺���Ч
+				{
+					printf("\r\n�˺Żָ�������\r\n");
+					DelDisableUser(curIcCard);
+					ShowDisableUserList();
+				}else{
+					printf("\r\n�˺Ŵ��ڽ���״̬��\r\n");
+				}
+				putInStatus = 0x05;
+				break;
+			}
+			break;
+
+//------------------------------------------------------------------------------------
+//����¼�봦������			
+		case 0x30:		//��������¼�����
+			sendMsg.msgType = 4401;
+			MessageSend(MSG_FIFO_PROTOCOL, sendMsg);	//���̨���������������ȡ�û���Ϣָ��
+			putInStatus = 0x31;
+			timer_restart(&faceEntryTimer);
+			break;
+		
+		case 0x31:		//����¼�����
+			if(userInfoQueryStatus == 1)
+			{
+				userInfoQueryStatus = 0;
+				
+				PC_ProCommandSend(0x02);											//����λ�������û����������Ϣ������ʾ
+			}
+			
+			//¼�����������ʧ�ܿ��Լ������������Ϣ
+			tempData = GetPutInType();									//����Ƿ��п���Ͷ������
+			if(tempData > 0)														//�п�������
+			{
+				getPutInType = tempData;									//���濪��Ͷ�ŵ����ͣ���ť��IC������ά�롢�����������룩
+				tempData = 0;
+				
+				//20190627�޸����ǰһ�ε��û���Ϣ
+				accountNum = 0;
+				isAuth = 0;
+				userInfoQueryStatus = 0;
+				memset(get_IC_ID, 0x00, 9);								//���ȡ�õ�IC��������
+				
+				GetUserInfo(getPutInType);								//���ݿ��ŷ�ʽȡ���û������Ϣ
+// 				ShowPutInInfo(getPutInType);							//��ʾͶ�����������Ϣ
+				
+				//���û�����ʶ����Ϣ���浽���ͻ���
+				sendPutInType = getPutInType;							//����ʶ��ʽ
+				sendDataLength = getDataLength;						//����������Ϣ�ĳ���
+				memcpy(sendDataBuf, getDataBuf, 33);			//����������Ϣ
+		
+				putInStatus = 0x30;
+				printf("\r\n����¼�����²���\r\n");
+				break;
+			}
+			
+			if(faceEntryFlag == 0)
+			{
+				printf("\r\n����¼���˳���\r\n");
+				ClearPutInInfo();
+				putInStatus = 0x00;
+				break;
+			}
+			
+			if(timer_expired(&faceEntryTimer))
+			{
+				printf("\r\n¼�볬ʱ�˳���\r\n");
+				ClearPutInInfo();
+				faceEntryFlag = 0;
+				putInStatus = 0x00;
+				break;
+			}
+			break;
+			
+		default:
+			putInStatus = 0x00;
+			break;
+	}
+}
+
+/*
+***********************************************************************
+*	�� �� ��: BoxOpenTask
+*	����˵��: �����ţ������ţ����ſ�������
+*	��    �Σ���
+*	�� �� ֵ: ��
+***********************************************************************
+*/
+void BoxOpenTask(void)
+{
+	uint8_t temp = 0;
+	static uint8_t boxOpenSteps = 0;
+	static uint8_t boxOpenType = 0;									//�������������ŵķ�ʽ
+
+	static timer waitingTimer;
+	static timer waitingAckTimer;										//�ȴ���̨Ӧ��ʱ��
+	static timer waitingUnlockingTimer;							//�ȴ���������ʱ��
+	
+	static uint8_t timer_ok = 0;
+	
+	if(timer_ok == 0)
+	{
+		timer_ok = 1;
+		timer_set(&waitingTimer, CLOCK_SECOND*1);	
+		timer_set(&waitingAckTimer, CLOCK_SECOND*10);	
+		timer_set(&waitingUnlockingTimer, CLOCK_SECOND*2);
+	}
+
+	switch(boxOpenSteps)
+	{
+		case 0x00:		//��ʼ״̬
+			//ˢ���˿�����
+			if(RFID_state == 2)
+			{
+				RFID_state = 0;
+				
+				boxOpenType = 1;											//��־��ǰΪIC����������
+				beep_shortBeepMark = 1;								//������ʾ��
+				
+				//ȡ����ǰ�ͻ���
+				getCustomerID = 0;
+				getCustomerID = RFID_ID[0] << 16;
+				getCustomerID |= RFID_ID[1] << 8;
+				getCustomerID |= RFID_ID[2];
+				
+				if(getCustomerID == customerID)		//�Ƿ�Ϊ���������˿�
+				{
+					printf("\r\n���ſ�ƥ�䣡\r\n");						
+					
+					memcpy(curIcCard, RFID_ID, 9);				//ȡ����ǰ��IC������Ϣ
+					printf("\r\n��ʼ����\r\n");
+					temp = FindUserStatus(curIcCard);
+					if(temp > 0)
+					{
+						beep_warningBeepMark = 1;
+						printf("\r\n��ǰ�û��Ѿ������ã��� %d λ\r\n", temp);
+						boxOpenSteps =0x20;
+						break;
+					}else{
+						printf("\r\n��ǰ�û�������\r\n");
+						boxOpenSteps = 0x01;
+						break;
+					}
+				}else{
+					beep_warningBeepMark = 1;
+					printf("\r\n���ſ���ƥ�䣡\r\n");
+					timer_restart(&waitingTimer);
+					boxOpenSteps = 0x04;									//�˳�
+					break;
+				}
+			}
+			
+			//��ʱ��ά�뿪����������
+			if(boxOpenQRMark == 1)
+			{
+				boxOpenQRMark = 0;											//��־Ҫ�������ţ��ɿ���������������
+				beep_shortBeepMark = 1;									//������ʾ��
+				
+				if(enableCleanQRCodeStatus == 1)				//���������˶�ά�뿪��
+				{
+					printf("\r\n��ʱ���Ŷ�ά�뿪�ţ�\r\n");
+					boxOpenType = 2;
+					boxOpenSteps = 0x01;
+					break;
+				}else{
+					printf("\r\n�����˶�ά�뿪�š�������ͣ�ã�\r\n");
+					boxOpenSteps = 0x04;
+					break;
+				}
+			}
+			break;
+			
+		case 0x01:		//�ϴ�������Ա������Ϣ
+			if(boxOpenType == 1)
+			{
+				boxOpenMark = 1;												//��־Ҫ�������ţ��ɿ���������������
+				
+				//�ϴ�������Ա������Ϣ
+				getDataLength = 9;											//IC��������ϢΪ9�ֽ�
+				memcpy(getDataBuf, RFID_ID, 9);					//����IC��������Ϣ
+			}else if(boxOpenType == 2){
+				//��ʱ��û�ж�ά�뿪����Ϣ
+			}else{
+				boxOpenSteps = 0x04;
+			}
+			
+			//���û�����ʶ����Ϣ���浽���ͻ���
+			collectorSendAuthType = boxOpenType;							//����ʶ��ʽ
+			collectorSendDataLength = getDataLength;					//����������Ϣ�ĳ���
+			memcpy(collectorSendDataBuf, getDataBuf, 33);			//����������Ϣ
+			
+			
+			if(ConnectionStatus == OFFLINE)
+			{
+				boxOpenSteps = 0x04;
+				break;
+			}
+			
+			//ֱ���˳�
+			timer_restart(&waitingUnlockingTimer);
+			boxOpenSteps = 0x03;
+			break;
+			
+// 			sendMsg.msgType = 4701;
+// 			MessageSend(MSG_FIFO_PROTOCOL, sendMsg);	//���̨���������������ȡ�û���Ϣָ��
+// 			
+// 			timer_restart(&waitingAckTimer);
+// 			boxOpenSteps = 0x02;
+// 			break;
+			
+		case 0x02:		//�ȴ���̨�û�������֤
+			if(timer_expired(&waitingAckTimer))
+			{
+				printf("\r\n��֤��ʱ�˳���\r\n");
+				boxOpenSteps = 0x04;
+				break;
+			}
+			
+			if(getBoxOpenAckMark == 1)		//�յ���̨���������ϴ�Ӧ��
+			{
+				getBoxOpenAckMark = 0;
+				
+				//���ݺ�̨��Ӧ��״̬������Ӧ�Ĵ���
+				switch(boxOpenAckStatus)	
+				{
+					case 0:		//��Ч��δ�Ǽ�
+						//��ʱ���������������IC��ǰһ״̬�Ѿ����Կ��ţ���ά�����޷���
+						printf("\r\n�����˺���Ч��δ�Ǽǣ�\r\n");
+						break;
+						
+					case 1:		//���������˺�
+						printf("\r\n�����˺�������\r\n");
+						if(boxOpenType == 1)				//����IC������
+						{
+// 								boxOpenMark = 1;												//��־Ҫ�������ţ��ɿ���������������
+// 							unlockMark = 1;																	//�ɿ�ɣ�������Ʊ�־
+							break;
+						}else if(boxOpenType == 2)	//���˶�ά�뿪��
+						{
+							boxOpenMark = 1;												//��־Ҫ�������ţ��ɿ���������������
+							break;
+						}
+						break;
+						
+					case 2:		//���õ������˺�
+						if(boxOpenType == 1)				//����IC������
+						{
+							AddDisableUser(curIcCard);							// ���ӵ������б�
+							ShowDisableUserList();
+						}else if(boxOpenType == 2)	//���˶�ά�뿪��
+						{
+							//���õ��˺��޷�����
+							printf("\r\n�����˺ű����ã�\r\n");
+						}
+						break;
+						
+					default:
+						break;
+				}
+				
+				timer_restart(&waitingUnlockingTimer);
+				boxOpenSteps = 0x03;
+				break;
+			}
+			break;
+			
+		case 0x03:		//�ȴ����������������
+			if(timer_expired(&waitingUnlockingTimer))
+			{
+				boxOpenSteps = 0x04;
+			}
+			break;
+			
+		case 0x04:		//�˳�
+			//�����صı���
+			RFID_state = 0;
+			boxOpenMark = 0;
+			boxOpenSteps = 0x00;
+			break;
+			
+//----------------------------------------------------------------------------
+//���õ������˺Ŵ���			
+		case 0x20:		//���õ������˺Ŵ������ٴ������ж��Ƿ�ָ�������
+// 			Screen_Query(0x03, 0, NULL, 0, 0);
+			//�ϴ�������Ա������Ϣ
+			getDataLength = 9;											//IC��������ϢΪ9�ֽ�
+			memcpy(getDataBuf, RFID_ID, 9);					//����IC��������Ϣ
+				
+			//���û�����ʶ����Ϣ���浽���ͻ���			
+			collectorSendAuthType = boxOpenType;							//����ʶ��ʽ
+			collectorSendDataLength = getDataLength;					//����������Ϣ�ĳ���
+			memcpy(collectorSendDataBuf, getDataBuf, 33);			//����������Ϣ
+			
+			sendMsg.msgType = 4701;
+			MessageSend(MSG_FIFO_PROTOCOL, sendMsg);	//���̨���������������ȡ�û���Ϣָ��
+			printf("\r\nGet user Info\r\n");
+					
+			boxOpenSteps = 0x21;
+			timer_restart(&waitingAckTimer);
+			break;
+			
+		case 0x21:		//�ȴ���̨�����û���Ϣ
+			if(timer_expired(&waitingAckTimer))
+			{
+				boxOpenSteps = 0x04;
+				break;
+			}
+			
+			//�յ���̨Ӧ����û�������Ϣ
+			if(getBoxOpenAckMark == 1) 
+			{
+				getBoxOpenAckMark = 0;
+				
+				//���ݺ�̨��Ӧ��״̬������Ӧ�Ĵ���
+				switch(boxOpenAckStatus)	
+				{
+					case 0:		//��Ч��δ�Ǽ�
+						//��ʱ��������
+						printf("\r\n�����˺���Ч��δ�Ǽǣ�\r\n");
+						break;
+						
+					case 1:		//���������˺�
+						printf("\r\n�����˺�������\r\n");
+						if(boxOpenType == 1)				//����IC������
+						{
+							printf("\r\n�˺Żָ�������\r\n");
+							DelDisableUser(curIcCard);
+							ShowDisableUserList();
+							break;
+						}else if(boxOpenType == 2)	//���˶�ά�뿪��
+						{
+							boxOpenMark = 1;												//��־Ҫ�������ţ��ɿ���������������
+							break;
+						}
+						break;
+						
+					case 2:		//���õ������˺�
+						if(boxOpenType == 1)				//����IC������
+						{
+							printf("\r\n�˺Ŵ��ڽ���״̬��\r\n");
+						}else if(boxOpenType == 2)	//���˶�ά�뿪��
+						{
+							//���õ��˺��޷�����
+							printf("\r\n�����˺ű����ã�\r\n");
+						}
+						break;
+						
+					default:
+						break;
+				}
+				
+				boxOpenSteps = 0x04;
+				break;
+			}
+			break;
+			
+		default:
+			boxOpenSteps = 0x00;
+			break;
+	}
+}
+
+/*
+***********************************************************************
+*	�� �� ��: ServerSetupParam
+*	����˵��: ��̨���ò�������
+*	��    �Σ��� 
+*	�� �� ֵ: ��
+***********************************************************************
+*/
+void ServerSetupParamTask(void)
+{
+	uint8_t passMark = 0;
+	
+	if(getSetDistanceParamMark == 1)
+	{
+		getSetDistanceParamMark = 0;
+		
+		printf("\r\nGetDis: N=%d, T1=%d, h1=%d, H1=%d, A1=%d; T2=%d, h2=%d, H2=%d, A2=%d\r\n", getDevChannelNumbers,
+						getDevChannel1Type, getDevChannel1DisDepthVal, getDevChannel1DisMaxVal, getDevChannel1DisAlarmPercent,
+						getDevChannel2Type, getDevChannel2DisDepthVal, getDevChannel2DisMaxVal, getDevChannel2DisAlarmPercent);
+		
+		//���ݼ���
+		if((getDevChannelNumbers == devChannelNumbers) &&
+			 (getDevChannel1Type == devChannel1Type) &&
+			 (getDevChannel2Type == devChannel2Type) &&
+			 (getDevChannel3Type == devChannel3Type) &&
+			 (getDevChannel4Type == devChannel4Type) &&
+			 (getDevChannel1DisDepthVal > 0) && (getDevChannel1DisMaxVal >= getDevChannel1DisDepthVal) &&
+			 (getDevChannel2DisDepthVal > 0) && (getDevChannel2DisMaxVal >= getDevChannel2DisDepthVal) &&
+			 (getDevChannel3DisDepthVal > 0) && (getDevChannel3DisMaxVal >= getDevChannel3DisDepthVal) &&
+			 (getDevChannel4DisDepthVal > 0) && (getDevChannel4DisMaxVal >= getDevChannel4DisDepthVal) &&
+			 (getDevChannel1DisAlarmPercent <= 140) && (getDevChannel2DisAlarmPercent <= 140) &&
+			 (getDevChannel3DisAlarmPercent <= 140) && (getDevChannel4DisAlarmPercent <= 140))
+		{
+			passMark = 1;
+		}else{
+			passMark = 0;
+			printf("\r\n���ݼ������\r\n");
+		}
+		
+		if(passMark == 1)
+		{
+			setDevChannel1DisMaxVal = getDevChannel1DisMaxVal;
+			setDevChannel1DisDepthVal = getDevChannel1DisDepthVal;
+			setDevChannel1DisAlarmPercent = getDevChannel1DisAlarmPercent;
+
+			setDevChannel2DisMaxVal = getDevChannel2DisMaxVal;
+			setDevChannel2DisDepthVal = getDevChannel2DisDepthVal;
+			setDevChannel2DisAlarmPercent = getDevChannel2DisAlarmPercent;
+
+			setDevChannel3DisMaxVal = getDevChannel3DisMaxVal;
+			setDevChannel3DisDepthVal = getDevChannel3DisDepthVal;
+			setDevChannel3DisAlarmPercent = getDevChannel3DisAlarmPercent;
+
+			setDevChannel4DisMaxVal = getDevChannel4DisMaxVal;
+			setDevChannel4DisDepthVal = getDevChannel4DisDepthVal;
+			setDevChannel4DisAlarmPercent = getDevChannel4DisAlarmPercent;
+			
+			SaveDeviceConfig();
+			DeviceParamInit();							//�����б䶯�������³�ʼ���豸����
+			CalcOverflowStartPointParam();
+		}
+	}
+}
+
+/*
+***********************************************************************
+*	�� �� ��: DeviceEnableTask
+*	����˵��: �豸����/���ÿ�������
+*	��    �Σ���
+*	�� �� ֵ: ��
+***********************************************************************
+*/
+void DeviceEnableTask(void)
+{
+	uint8_t dataTemp = 0;
+	
+	if(getDeviceWorkStatusMark == 1)
+	{
+		getDeviceWorkStatusMark = 0;
+		
+		printf("\r\nWorkSta = %d\r\n", getDeviceWorkStatusVal);
+
+		if(getDeviceWorkStatusVal >= 1)
+		{
+			deviceWorkStatus = 1;
+		}else{
+			deviceWorkStatus = 0;
+		}
+		
+		//�����豸��ǰ����״̬������ʾ
+		if(deviceWorkStatus == 0)
+		{
+			Screen_DeviceDisable();
+		}else{
+			Screen_Default();
+		}
+		
+		if(deviceWorkStatus != deviceWorkStatusPre)
+		{
+			printf("\r\n�豸����״̬�б仯��\r\n");
+			deviceWorkStatusPre = deviceWorkStatus;
+		}
+	}
+}
+
+/*
+***********************************************************************
+*	�� �� ��: KeysSendTask
+*	����˵��: ��������ת������λ������
+*	��    ��:	��
+*	�� �� ֵ: ��
+***********************************************************************
+*/
+void KeysSendTask(void)
+{
+	if(keyType == 1)		//����ʹ�ô�������
+	{
+		if(keyValue > 0)
+		{
+	// 		printf("\r\nkey = %x\r\n", keyValue);
+			if((keyValue & 0xF0) == 0)		//�����̰����
+			{
+				keyNum = keyValue;
+				keyStatus = 1;
+	// 			printf("\r\n�����̰���key = %x\r\n", keyNum);
+			}else{												//�����������
+				keyNum = keyValue & 0x0F;
+				keyStatus = 2;
+	// 			printf("\r\n����������key = %x\r\n", keyNum);
+			}
+			
+			PC_ProCommandSend(0x11);											//����λ�������û����������Ϣ������ʾ
+			printf("\r\n�������: Num = %x, Sta = %x\r\n", keyNum, keyStatus);
+			keyValue = 0;
+		}
+		
+		if(keyReleaseMark == 1)			//�����ɿ�ʱ�����
+		{
+			keyStatus = 3;
+			PC_ProCommandSend(0x11);											//����λ�������û����������Ϣ������ʾ
+			printf("\r\n�������: Num = %x, Sta = %x\r\n", keyNum, keyStatus);
+			
+			keyReleaseMark = 0;
+		}
+	}
+	
+	
+	//ͬʱʹ�û�е�����ʹ��������������л����͵ļ�ֵ��MCU2�Ĺ�翪�ؽӿ����룩
+// 	if(optoKeyStatus > 0)		
+// 	{
+// 		if(optoKeyStatus == 1)
+// 		{
+// 			keyNum = 3;
+// 			keyStatus = 1;
+// 		}else if(optoKeyStatus == 3){
+// 			keyNum = 3;
+// 			keyStatus = 3;
+// 		}else{}
+// 		
+// 		PC_ProCommandSend(0x11);											//����λ�������û����������Ϣ������ʾ
+// 		printf("\r\n�������: Num = %x, Sta = %x\r\n", keyNum, keyStatus);
+// 		
+// 		optoKeyStatus = 0;
+// 	}
+}
+
+/*
+***********************************************************************
+*	�� �� ��: HumanSensingTask
+*	����˵��: �����Ӧ����
+*	��    ��:	��
+*	�� �� ֵ: ��
+***********************************************************************
+*/
+void HumanSensingTask(void)
+{
+	if(optoKeyStatus > 0)		
+	{
+		if(optoKeyStatus == 1)
+		{
+			humanSensingKeyStatus = 1;
+		}else if(optoKeyStatus == 3){
+			humanSensingKeyStatus = 3;
+		}else{}
+		
+		PC_ProCommandSend(0x64);											//����λ�������û����������Ϣ������ʾ
+		printf("\r\n�����Ӧ״̬: Num = %x, Sta = %x\r\n", 1, humanSensingKeyStatus);
+		
+		optoKeyStatus = 0;
+	}
+}
+
+/*
+***********************************************************************
+*	�� �� ��: DropOffPortCheck
+*	����˵��: Ͷ�ſ�״̬�������
+*	��    �Σ���
+*	�� �� ֵ: ��
+***********************************************************************
+*/
+void DropOffPortCheckTask(void)
+{
+	static uint8_t preDropOffPortSta1 = 0;
+	static uint8_t preDropOffPortSta2 = 0;
+	
+	if(preDropOffPortSta1 != switchKey1Status)
+	{
+		dropOffPortMark1 = 1;							//��־��ǰͶ�ſ�״̬�����仯
+		dropPortClosedStatus1 = switchKey1Status;
+		preDropOffPortSta1 = dropPortClosedStatus1;
+		printf("\r\nͶ�ſ�1״̬�����仯��%d��\r\n", dropPortClosedStatus1);
+	}
+	
+	if(preDropOffPortSta2 != switchKey2Status)
+	{
+		dropOffPortMark2 = 1;							//��־��ǰͶ�ſ�״̬�����仯
+		dropPortClosedStatus2 = switchKey2Status;
+		preDropOffPortSta2 = dropPortClosedStatus2;
+		printf("\r\nͶ�ſ�2״̬�����仯��%d��\r\n", dropPortClosedStatus2);
+	}
+	
+	if((dropOffPortMark1 == 1) || (dropOffPortMark2 == 1)) 
+	{
+		PC_ProCommandSend(0x66);											//����λ������Ͷ�ڹر�״̬
+	}
+}
+
+/*
+***********************************************************************
+*	�� �� ��: RecycleClearDoorCheckTask
+*	����˵��: ������״̬�������
+*	��    ��:	��
+*	�� �� ֵ: ��
+***********************************************************************
+*/
+void RecycleClearDoorCheckTask(void)
+{
+	static uint8_t currentStatus = 0x00;
+	static uint8_t nextStatus = 0x00;
+	
+	static uint8_t preStatus = 0;
+	uint8_t curStatus = 0;
+	
+	static uint8_t preRecycleClearDoorMark = 0;
+	
+	static uint8_t initOk = 0;
+	
+	static timer waitingInitTimer;
+	static timer waitingTimer;
+	
+	static uint8_t timer_ok = 0;
+	if(timer_ok == 0)
+	{
+		timer_ok = 1;
+		
+		timer_set(&waitingInitTimer, CLOCK_SECOND*30);
+		timer_set(&waitingTimer, CLOCK_SECOND*2);
+	}
+	
+	curStatus = getRecycleClearDoorMark;
+	
+	currentStatus = nextStatus;
+	switch(currentStatus)
+	{
+		case 0x00:
+			if(curStatus != preStatus)
+			{
+				timer_restart(&waitingTimer);
+				nextStatus = 0x01;
+				break;
+			}
+			break;
+			
+		case 0x01:
+			if(timer_expired(&waitingTimer))
+			{
+				if(curStatus != preStatus)
+				{
+					printf("\r\n������״̬�����仯��\r\n");
+					recycleClearDoorMark = curStatus;
+					preStatus = curStatus;
+				}
+				nextStatus = 0x00;
+			}
+			break;
+			
+		default:
+			nextStatus = 0x00;
+			break;		
+	}
+	
+	
+	if(recycleClearDoorMark != preRecycleClearDoorMark)
+	{
+		if(recycleClearDoorMark == 0)
+		{
+			printf("\r\n�����Źرգ�\r\n");
+		}else{
+			printf("\r\n�����Ŵ򿪣�\r\n");
+		}
+		
+		preRecycleClearDoorMark = recycleClearDoorMark;
+		
+		PC_ProCommandSend(0x23);
+	}
+	
+	
+	if(initOk == 0)
+	{
+		if(timer_expired(&waitingInitTimer))
+		{
+			initOk = 1;
+			
+			printf("\r\n���ο�������λ������������״̬��\r\n");
+			if(recycleClearDoorMark == 0)
+			{
+				printf("\r\n�����Źرգ�\r\n");
+			}else{
+				printf("\r\n�����Ŵ򿪣�\r\n");
+			}
+			PC_ProCommandSend(0x23);
+		}
+	}
+}
+
+/*
+***********************************************************************
+*	�� �� ��: NowTimeIsOnTheHour
+*	����˵��: ��ǰʱ���Ƿ�Ϊ����
+*	��    �Σ���
+*	�� �� ֵ: ���㷵��1,���򷵻�0
+***********************************************************************
+*/
+uint8_t NowTimeIsOnTheHour(void)
+{
+	if((nowTime->tm_min == 0) && (nowTime->tm_sec == 0))
+	{
+		return 1;
+	}else{
+		return 0;
+	}
+}
+
+/*
+***********************************************************************
+*	�� �� ��: TimingSprayTask
+*	����˵��: ��ʱ������������
+*	��    �Σ���
+*	�� �� ֵ: ��
+***********************************************************************
+*/
+void TimingSprayTask(void)
+{
+	static uint8_t currentStatus = 0x00;
+	static uint8_t nextStatus = 0x00;
+	uint8_t onTheHourStatus = 0;
+	
+	static timer waitingTimer;
+	static timer turnOnTimer;
+	
+	static uint8_t timer_ok = 0;
+	if(timer_ok == 0)
+	{
+		timer_ok = 1;
+		
+		timer_set(&waitingTimer, CLOCK_SECOND*1);
+ 		timer_set(&turnOnTimer, CLOCK_SECOND*2);
+	}
+	
+	onTheHourStatus = NowTimeIsOnTheHour();
+	
+	currentStatus = nextStatus;
+	switch(currentStatus)
+	{
+		case 0x00:
+			if((getDateTimeMark == 1) && (onTheHourStatus == 1))
+			{
+//				//���ݲ�ͬʱ����������ܴ�����00:00 - 08:59 3Сʱ��һ�Σ�09:00 - 23:59M 1Сʱ��һ�Σ�
+//				if((nowTime->tm_hour == 0) || (nowTime->tm_hour == 3) || (nowTime->tm_hour == 6) || (nowTime->tm_hour >= 9))
+				
+				if((nowTime->tm_hour)%3 == 0)		//ÿ3Сʱ��һ�� 20230727�޸�
+				{
+					printf("\r\n��ʱ��������������(%s)\r\n", systemTime);
+					
+					if((sprayDisinfectingMark != 2) && (putInProgress != 1))			//��ǰ������û�д�״̬��û��Ͷ�Ų�������ִ��������������
+					{
+						StartUpSprayDisinfection();
+					}
+					timer_restart(&turnOnTimer);
+					nextStatus = 0x01;
+					break;
+				}
+			}
+			break;
+			
+		case 0x01:		//����״̬
+			if(timer_expired(&turnOnTimer))
+			{
+				printf("\r\n����ʱ�䵽�ر�����������\r\n");
+				
+				StopSprayDisinfection();
+				nextStatus = 0x00;
+				break;
+			}
+			
+			//Ͷ��ʱ��ͣ����
+			if(putInProgress == 1)
+			{
+				printf("\r\n��ǰ����Ͷ�ţ���ͣ����������\r\n");
+				
+				StopSprayDisinfection();
+				nextStatus = 0x02;
+				break;
+			}
+			
+			//�������Ž�������
+			if(sprayDisinfectingMark == 2)
+			{
+				printf("\r\n�������Ž�������������\r\n");
+				
+				StopSprayDisinfection();
+				sprayDisinfectingMark = 0;
+				
+				timer_restart(&waitingTimer);
+				nextStatus = 0x10;
+				break;
+			}
+			break;
+			
+		case 0x02:		//��ͣ״̬
+			if(putInProgress == 0)
+			{
+				printf("\r\nͶ�Ž������ָ�����������\r\n");
+				
+				StartUpSprayDisinfection();
+				timer_restart(&turnOnTimer);
+				nextStatus = 0x01;
+				break;
+			}
+			break;
+			
+		case 0x10:
+			if(timer_expired(&waitingTimer))
+			{
+				sprayDisinfectingMark = 0;
+				nextStatus = 0x00;
+				break;
+			}
+			break;
+			
+		default:
+			break;
+	}
+}
+
+/*
+***********************************************************************
+*	�� �� ��: TimingUVTask
+*	����˵��: ��ʱ��������������
+*	��    �Σ���
+*	�� �� ֵ: ��
+***********************************************************************
+*/
+void TimingUVTask(void)
+{
+	static uint8_t currentStatus = 0x00;
+	static uint8_t nextStatus = 0x00;
+	uint8_t onTheHourStatus = 0;
+	
+	static timer waitingTimer;
+	static timer turnOnTimer;
+	
+	static uint8_t timer_ok = 0;
+	if(timer_ok == 0)
+	{
+		timer_ok = 1;
+		
+		timer_set(&waitingTimer, CLOCK_SECOND*1);
+ 		timer_set(&turnOnTimer, CLOCK_SECOND*60*10);
+	}
+	
+	onTheHourStatus = NowTimeIsOnTheHour();
+	
+	currentStatus = nextStatus;
+	switch(currentStatus)
+	{
+		case 0x00:
+			if((getDateTimeMark == 1) && (onTheHourStatus == 1))
+			{
+				printf("\r\n��ʱ����UV������(%s)\r\n", systemTime);
+				
+				if((disinfectingMark != 2) && (putInProgress != 1))			//��ǰ������û�д�״̬��û��Ͷ�Ų�������ִ��UV��������
+				{
+					StartUpDisinfection();
+				}
+				timer_restart(&turnOnTimer);
+				nextStatus = 0x01;
+				break;
+			}
+			break;
+			
+		case 0x01:		//����״̬
+			if(timer_expired(&turnOnTimer))
+			{
+				printf("\r\n����ʱ�䵽�ر�UV������\r\n");
+				
+				StopDisinfection();
+				nextStatus = 0x00;
+			}
+			
+			//Ͷ��ʱ��ͣ����
+			if(putInProgress == 1)
+			{
+				printf("\r\n��ǰ����Ͷ�ţ���ͣUV������\r\n");
+				
+				StopDisinfection();
+				nextStatus = 0x02;
+				break;
+			}
+			
+			//�������Ž���UV����
+			if(disinfectingMark == 2)
+			{
+				printf("\r\n�������Ž���UV������\r\n");
+				
+				StopDisinfection();
+				disinfectingMark = 0;
+				
+				timer_restart(&waitingTimer);
+				nextStatus = 0x10;
+				break;
+			}
+			break;
+			
+		case 0x02:		//��ͣ״̬
+			if(putInProgress == 0)
+			{
+				printf("\r\nͶ�Ž������ָ�UV������\r\n");
+				
+				StartUpDisinfection();
+//				timer_restart(&turnOnTimer);
+				nextStatus = 0x01;
+				break;
+			}
+			break;
+			
+		case 0x10:
+			if(timer_expired(&waitingTimer))
+			{
+				disinfectingMark = 0;
+				nextStatus = 0x00;
+				break;
+			}
+			break;
+			
+		default:
+			break;
+	}
+}
+
+/******************** (C) COPYRIGHT 2017 Ping *****END OF FILE*******************/
diff --git a/STM32_4路称重_Git提交精简工程/src/USER/user_app.h b/STM32_4路称重_Git提交精简工程/src/USER/user_app.h
new file mode 100755
index 0000000..f98b42e
--- /dev/null
+++ b/STM32_4路称重_Git提交精简工程/src/USER/user_app.h
@@ -0,0 +1,31 @@
+/*************************** (C) COPYRIGHT 2017 CXHY ****************************
+ * �ļ���  ��device.h
+ * ��  ��  ���豸���Ƴ���
+ * ��  ��  ��V1.0
+ * ��  ��  ��XuZhongPing
+ * ��  ��  ��2017/03/06 
+*********************************************************************************/
+#ifndef __USER_APP_H
+#define __USER_APP_H	 
+#include "stm32f10x.h"
+#include "string.h" 
+#include "stdlib.h" 
+#include "device.h"
+#include "data_typedef.h"
+
+void showHexData(uint8_t num[], uint8_t n);
+void PutInOpenDoorTask(void);
+void BoxOpenTask(void);
+void ServerSetupParamTask(void);
+void DeviceEnableTask(void);
+
+void KeysSendTask(void);
+void HumanSensingTask(void);
+void DropOffPortCheckTask(void);
+void RecycleClearDoorCheckTask(void);
+void TimingSprayTask(void);
+void TimingUVTask(void);
+
+#endif
+
+/******************** (C) COPYRIGHT 2017 CXHY *****END OF FILE*******************/
diff --git a/STM32_4路称重_Git提交精简工程/src/USER/user_manag.c b/STM32_4路称重_Git提交精简工程/src/USER/user_manag.c
new file mode 100755
index 0000000..6091141
--- /dev/null
+++ b/STM32_4路称重_Git提交精简工程/src/USER/user_manag.c
@@ -0,0 +1,207 @@
+/*************************** (C) COPYRIGHT 2017 Ping ****************************
+ * �ļ���  : user_manag.c
+ * ��  ��  ���û���������
+ * ��  ��  ��V1.0
+ * ��  ��  ��XuZhongPing
+ * ��  ��  ��2019/07/20
+*********************************************************************************/
+#include "user_manag.h"
+#include "usart1.h"
+#include "delay.h"
+#include "timer.h"
+#include "display.h"
+
+#include "stmflash.h"
+
+IC_CARD DisableUserList[USER_LEN];	//����һ�黺�����ڱ�����õ�IC���û���Ϣ
+IC_CARD curIcCard;									//��ǰ��IC���û���Ϣ
+uint8_t nextSaveIndex = 0;					//��һ��Ҫ�����IC������������ַ
+uint8_t DisUserCount = 0;						//��ǰ�Ѿ�����Ľ����û�����
+
+
+/*
+***********************************************************************
+*	�� �� ��: showHexData
+*	����˵��: ��ʮ��������ʾ�����������
+*	��    ��:	��
+*	�� �� ֵ: ��
+***********************************************************************
+*/
+void showHex1(uint8_t num[], uint8_t n)
+{
+	uint8_t i;
+	
+	printf("\r\n");
+	for(i=0; i<n; i++)
+	{
+		printf("0x%02X ",num[i]);
+	}
+	printf("\r\n");
+}
+
+/*
+***********************************************************************
+*	�� �� ��: ShowDisableUserList
+*	����˵��: ��ʾ�����û��б�����
+*	��    ��:	��
+*	�� �� ֵ: ��
+***********************************************************************
+*/
+void ShowDisableUserList(void)
+{
+	uint8_t i;
+	
+	printf("\r\n��ǰ�û�������%d, nextIndex = %d:", DisUserCount, nextSaveIndex);
+	for(i = 0; i < DisUserCount; i++)
+	{
+		showHex1(DisableUserList[i], 16);
+	}
+}
+
+/*
+***********************************************************************
+*	�� �� ��: DisableUserListInit
+*	����˵��: �����û��б���ʼ��
+*	��    �Σ���
+*	�� �� ֵ: 0x00->����ͬ��0x01->��ͬ
+***********************************************************************
+*/
+void DisableUserListInit(void)
+{
+	uint8_t i;
+	IC_CARD userTemp = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00};
+	
+	if(DisUserCount == 0)
+	{
+		nextSaveIndex = 0;
+	}
+	
+	for(i = 0; i < 15; i++)
+	{
+		userTemp[8] += 1;
+		AddDisableUser(userTemp);
+		
+		ShowDisableUserList();
+	}
+}
+
+/*
+***********************************************************************
+*	�� �� ��: CheckArrayEquality
+*	����˵��: �ж����������Ƿ���ͬ�����û���Ϣ�Ƿ���ȣ�
+*	��    �Σ���
+*	�� �� ֵ: 0x00->����ͬ��0x01->��ͬ
+***********************************************************************
+*/
+static uint8_t CheckArrayEquality(IC_CARD arr1, IC_CARD arr2)
+{
+	uint8_t i;
+	
+	for(i = 0; i < 16; i++)
+	{
+		if(arr1[i] != arr2[i])
+		{
+			return 0;
+		}
+	}
+	
+	return 1;
+}
+
+/*
+***********************************************************************
+*	�� �� ��: FindUserStatus
+*	����˵��: ��ѯ��ǰIC���û�״̬����ѯ�Ƿ񱻽��ã�
+*	��    �Σ���
+*	�� �� ֵ: 0x00->�������н����򷵻ض�Ӧ�ı����ַ����1��ʼ���㣩
+***********************************************************************
+*/
+uint8_t FindUserStatus(IC_CARD inPutInfo)
+{
+	uint8_t i;
+	
+	if(DisUserCount > 0)
+	{
+		for(i = 0; i < DisUserCount; i++)
+		{
+			if(CheckArrayEquality(DisableUserList[i], inPutInfo))
+			{
+				return i+1;				//�����б����е�ǰ�û���Ϣ���򷵻ص�ǰ�����λ��
+			}
+		}
+		return 0;						//�����б�����������û�з��֣��򷵻�0
+		
+	}else{
+		return 0;
+	}
+}
+
+/*
+***********************************************************************
+*	�� �� ��: ArrCpy
+*	����˵��: ���鿽��
+*	��    �Σ�desArr -> Ŀ�����飻SouArr -> Դ����
+*	�� �� ֵ: ��
+***********************************************************************
+*/
+static void ArrCpy(IC_CARD desArr, IC_CARD SouArr)
+{
+	memcpy(desArr, SouArr, 16);
+}
+
+/*
+***********************************************************************
+*	�� �� ��: AddDisableUser
+*	����˵��: ���ӽ��õ��û��������б�
+*	��    �Σ���
+*	�� �� ֵ: ��
+***********************************************************************
+*/
+void AddDisableUser(IC_CARD inPutInfo)
+{
+	ArrCpy(DisableUserList[nextSaveIndex], inPutInfo); 
+	
+	nextSaveIndex++;
+	DisUserCount++;
+	
+	if(nextSaveIndex >= USER_LEN)			//����λ���Ѿ��������һλ�����µ���λ��
+	{
+		nextSaveIndex = 0;
+	}
+	
+	if(DisUserCount >= USER_LEN)			//������������û������󣬸���ǰ��ģ������������ֵ
+	{
+		DisUserCount = USER_LEN;
+	}
+}
+
+/*
+***********************************************************************
+*	�� �� ��: DelDisableUser
+*	����˵��: ����ǰ�û��ӽ����б����Ƴ�
+*	��    �Σ�Ҫɾ�����û���Ϣ
+*	�� �� ֵ: ��
+***********************************************************************
+*/
+void DelDisableUser(IC_CARD delUserInfo)
+{
+	uint8_t i;
+	uint8_t curIndex = 0;
+	uint8_t tempBuf[16];
+	
+	memset(tempBuf, 0xff, 16);
+	
+	curIndex = FindUserStatus(delUserInfo);
+	if(curIndex > 0)		//��ǰ�û��ڽ����б���
+	{
+		for(i = curIndex - 1; i < (DisUserCount - 1); i++)
+		{
+			ArrCpy(DisableUserList[i], DisableUserList[i+1]);
+		}
+		ArrCpy(DisableUserList[DisUserCount - 1], tempBuf);
+		DisUserCount--;
+		nextSaveIndex = DisUserCount;				//������һ��Ҫд���λ��
+	}
+}
+
+/******************** (C) COPYRIGHT 2017 Ping *****END OF FILE*******************/
diff --git a/STM32_4路称重_Git提交精简工程/src/USER/user_manag.h b/STM32_4路称重_Git提交精简工程/src/USER/user_manag.h
new file mode 100755
index 0000000..136ec5a
--- /dev/null
+++ b/STM32_4路称重_Git提交精简工程/src/USER/user_manag.h
@@ -0,0 +1,31 @@
+/*************************** (C) COPYRIGHT 2017 CXHY ****************************
+ * �ļ���  ��user_manag.h
+ * ��  ��  ���û���������
+ * ��  ��  ��V1.0
+ * ��  ��  ��XuZhongPing
+ * ��  ��  ��2019/07/20 
+*********************************************************************************/
+#ifndef __USER_MANAG_H
+#define __USER_MANAG_H	 
+
+#include "stm32f10x.h"
+#include "string.h" 
+#include "stdlib.h" 
+#include "device.h"
+#include "data_typedef.h"
+
+#define USER_LEN	100											//�ܱ���Ľ����û�����
+typedef uint8_t IC_CARD[16];							//����һ��IC����Ϣ����
+extern IC_CARD DisableUserList[USER_LEN];	//����һ�黺�����ڱ�����õ�IC���û���Ϣ
+extern IC_CARD curIcCard;									//��ǰ��IC���û���Ϣ
+extern uint8_t nextSaveIndex;							//��һ��Ҫ�����IC������������ַ
+extern uint8_t DisUserCount;							//��ǰ�Ѿ�����Ľ����û�����
+
+void ShowDisableUserList(void);
+void DisableUserListInit(void);
+uint8_t FindUserStatus(IC_CARD inPutInfo);
+void AddDisableUser(IC_CARD inPutInfo);
+void DelDisableUser(IC_CARD inPutInfo);
+#endif
+
+/******************** (C) COPYRIGHT 2017 CXHY *****END OF FILE*******************/